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AgeCommit message (Expand)Author
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-07-23Bridge: Use EventWrapper instead of Event subclass for sendEventAndreas Hansson
2012-07-23test: Update eio ref outputs due to recent changesSteve Reinhardt
2012-07-23test: Restore eio ref files clobbered in rev 8800b05e1cb3.Steve Reinhardt
2012-07-22Regression: Update stats due to changes to x86 cpuid instructionNilay Vaish
2012-07-22X86 CPUID: Return false if unknown processor familyNilay Vaish
2012-07-21Regression: Fix topologies path in failing pc-simple-timing-rubyAndreas Hansson
2012-07-19Added tag stable_2012_06_28 for changeset f75ee4849c40Steve Reinhardt
2012-07-19Added tag stable_2012_02_02 for changeset 549b72de8f72Steve Reinhardt
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-12scons: Add LIBRARY_PATH from the user environment to SconsAndreas Hansson
2012-07-12Regression: update ruby.stats fileNilay Vaish
2012-07-12Ruby: remove config information from ruby.statsNilay Vaish
2012-07-12Ruby: remove some unused stuff from SLICC filesNilay Vaish
2012-07-11x86: added page size in bytes tlb entry functionBrad Beckmann
2012-07-11ruby: improved DRAM reset commentBrad Beckmann
2012-07-10regress: ruby stat additions and config changesBrad Beckmann
2012-07-10syscall emulation: Add the futex system call.Marc Orr
2012-07-10x86: logSize and lruSeq are now optional ckpt paramsBrad Beckmann
2012-07-10Add hook to call map() on Process from python.Steve Reinhardt
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10imported patch jason/slicc-external-structure-fixBrad Beckmann
2012-07-10ruby: banked cache array resource modelBrad Beckmann
2012-07-10ruby: tag and data cache access supportJoel Hestness
2012-07-10ruby: adds reset function to Ruby memory controllersNuwan Jayasena
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-07-10cpu: added assertions to ensure the correct proxies are usedBrad Beckmann
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-07-09EventManager: Rename queue accessor and remove cast operatorAndreas Hansson
2012-07-09Mem: Make members relating to range and size constantAndreas Hansson
2012-07-09Port: Hide the queue implementation in SimpleTimingPortAndreas Hansson
2012-07-09Stats: Updates due to bus changesAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Bus: Make the default bus width 8 bytes instead of 64Andreas Hansson
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add getAddrRanges to master port (asking slave port)Andreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-07-02gcc: Fix warnings for gcc 4.7 and clang 3.1Andreas Hansson
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
2012-06-29Bus: enable non/coherent buses sub-classesUri Wiener
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
2012-06-29Style: Make style.py's invalid warning print which file caused the infraction.Matt Evans
2012-06-29Mem: Fix a livelock resulting in LLSC/locked memory access implementation.Matt Evans