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Author
2012-07-23
Config: Use clock option in se/fs script and pass to switch_cpus
Andreas Hansson
2012-07-23
Bridge: Use EventWrapper instead of Event subclass for sendEvent
Andreas Hansson
2012-07-23
test: Update eio ref outputs due to recent changes
Steve Reinhardt
2012-07-23
test: Restore eio ref files clobbered in rev 8800b05e1cb3.
Steve Reinhardt
2012-07-22
Regression: Update stats due to changes to x86 cpuid instruction
Nilay Vaish
2012-07-22
X86 CPUID: Return false if unknown processor family
Nilay Vaish
2012-07-21
Regression: Fix topologies path in failing pc-simple-timing-ruby
Andreas Hansson
2012-07-19
Added tag stable_2012_06_28 for changeset f75ee4849c40
Steve Reinhardt
2012-07-19
Added tag stable_2012_02_02 for changeset 549b72de8f72
Steve Reinhardt
2012-07-12
Mem: Make SimpleMemory single ported
Andreas Hansson
2012-07-12
scons: Add LIBRARY_PATH from the user environment to Scons
Andreas Hansson
2012-07-12
Regression: update ruby.stats file
Nilay Vaish
2012-07-12
Ruby: remove config information from ruby.stats
Nilay Vaish
2012-07-12
Ruby: remove some unused stuff from SLICC files
Nilay Vaish
2012-07-11
x86: added page size in bytes tlb entry function
Brad Beckmann
2012-07-11
ruby: improved DRAM reset comment
Brad Beckmann
2012-07-10
regress: ruby stat additions and config changes
Brad Beckmann
2012-07-10
syscall emulation: Add the futex system call.
Marc Orr
2012-07-10
x86: logSize and lruSeq are now optional ckpt params
Brad Beckmann
2012-07-10
Add hook to call map() on Process from python.
Steve Reinhardt
2012-07-10
# User Brad Beckmann <Brad.Beckmann@amd.com>
Brad Beckmann
2012-07-10
ruby: remove the cpu assumptions for the random tester
Brad Beckmann
2012-07-10
# User Brad Beckmann <Brad.Beckmann@amd.com>
Brad Beckmann
2012-07-10
imported patch jason/slicc-external-structure-fix
Brad Beckmann
2012-07-10
ruby: banked cache array resource model
Brad Beckmann
2012-07-10
ruby: tag and data cache access support
Joel Hestness
2012-07-10
ruby: adds reset function to Ruby memory controllers
Nuwan Jayasena
2012-07-10
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Nuwan Jayasena
2012-07-10
cpu: added assertions to ensure the correct proxies are used
Brad Beckmann
2012-07-10
ruby: changes how Topologies are created
Brad Beckmann
2012-07-09
EventManager: Rename queue accessor and remove cast operator
Andreas Hansson
2012-07-09
Mem: Make members relating to range and size constant
Andreas Hansson
2012-07-09
Port: Hide the queue implementation in SimpleTimingPort
Andreas Hansson
2012-07-09
Stats: Updates due to bus changes
Andreas Hansson
2012-07-09
Port: Align port names in C++ and Python
Andreas Hansson
2012-07-09
Bus: Make the default bus width 8 bytes instead of 64
Andreas Hansson
2012-07-09
Bus: Split the bus into separate request/response layers
Andreas Hansson
2012-07-09
Bus: Add a notion of layers to the buses
Andreas Hansson
2012-07-09
Bus: Replace tickNextIdle and inRetry with a state variable
Andreas Hansson
2012-07-09
Port: Make getAddrRanges const
Andreas Hansson
2012-07-09
Port: Add getAddrRanges to master port (asking slave port)
Andreas Hansson
2012-07-09
Port: Add isSnooping to slave port (asking master port)
Andreas Hansson
2012-07-09
Port: Move retry from port base class to Master/SlavePort
Andreas Hansson
2012-07-09
Fix: Address a few benign memory leaks
Andreas Hansson
2012-07-02
gcc: Fix warnings for gcc 4.7 and clang 3.1
Andreas Hansson
2012-06-29
Cache: Fix the LRU policy for classic memory hierarchy
Lena Olson
2012-06-29
Bus: enable non/coherent buses sub-classes
Uri Wiener
2012-06-29
Mem: fix master id assertion in cache_impl.hh
Dam Sunwoo
2012-06-29
Style: Make style.py's invalid warning print which file caused the infraction.
Matt Evans
2012-06-29
Mem: Fix a livelock resulting in LLSC/locked memory access implementation.
Matt Evans
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