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AgeCommit message (Expand)Author
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-12-01ruby: Converted old ruby debug calls to M5 debug callsNilay Vaish
2010-11-26IGbE: return 0 on an invalid descriptor size instead of -1.Ali Saidi
2010-11-23Copyright: Add AMD copyright to the param changes I just made.Gabe Black
2010-11-23Params: Add parameter types for IP addresses in various forms.Gabe Black
2010-11-23X86: Loosen an assert for x86 and connect the APIC ports when caches are used.Gabe Black
2010-11-23X86: Obey the PCD (cache disable) bit in the page tables.Gabe Black
2010-11-22X86: Mark IO space accesses as uncachable.Gabe Black
2010-11-22X86: Remove reserved* from the m5 utility program for x86.Gabe Black
2010-11-22IDE,X86: Fix IDE controller BAR configuration for x86.Gabe Black
2010-11-20random: small comment about our random number generator and its originNathan Binkert
2010-11-19SE: Fix simulating more than 4GB of RAM in SE modeAli Saidi
2010-11-19SCons: Fix compilation on OS XAli Saidi
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-18O3: Fix fp destination register flattening, and index offset adjusting.Gabe Black
2010-11-17Config: Change misleading "cycle" message to say "tick".Gabe Black
2010-11-15Stats: Update the O3 fetch stats for SPARC.Gabe Black
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15O3: reset architetural state by calling clear()Ali Saidi
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-11-15Regressions: Update regressions for SIMD opclass changesAli Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15ARM: Compile O3 CPU by defaultAli Saidi
2010-11-15O3: prevent a squash when completeAcc() modifies misc reg through TC.Min Kyu Jeong
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-11-15ARM: Update regressions for CLCD and KMI additionsAli Saidi
2010-11-15ARM: Add a Keyboard Mouse Interface controllerWilliam Wang
2010-11-15ARM: Implement a CLCD Frame bufferWilliam Wang
2010-11-15ARM: Add support for GDB on ARMWilliam Wang
2010-11-15ARM: Make utility.hh meet style guidelinesAli Saidi
2010-11-15ARM: Add support for a dumb IDE controllerAli Saidi
2010-11-15ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.Ali Saidi
2010-11-15ARM: Add support for switching CPUsAli Saidi
2010-11-15ARM: Use the correct delete operator for RFEAli Saidi
2010-11-15ARM: Fix SRS instruction to micro-code memory operation and register update.Ali Saidi
2010-11-15CPU: Fix bug when a split transaction is issued to a faster cacheAli Saidi
2010-11-15ARM: Do something predictable for an UNPREDICTABLE branch.Ali Saidi
2010-11-11Params: Fix an off by one error and a misleading comment.Gabe Black
2010-11-11SimObject: Add a comment near clear_child that it's unlikely to be called.Gabe Black
2010-11-11SPARC: Clean up some historical style issues.Gabe Black
2010-11-10Update EIO regressions for last set of patchesAli Saidi
2010-11-09scons: Work around for old versions of scons mistaking strings for sequences.Gabe Black
2010-11-09SimObject: Use "self" when calling the clear_child method.Gabe Black
2010-11-08X86: Fix X86_FS compilation.Gabe Black
2010-11-08ARM: Update SE stats for TLB stats additionsAli Saidi
2010-11-08ARM: Add full-system regressionsAli Saidi