gem5 - gem5

Age	Commit message (Expand)	Author
2018-07-16	arch-arm: Introduce ARMv8.1 Virtual Timer System Registers	Giacomo Travaglini
2018-07-16	arch-arm: Introduce RAS System Registers	Giacomo Travaglini
2018-07-13	configs: Update the DRAM sweep script to use PyTrafficGen	Andreas Sandberg
2018-07-13	cpu: Add a Python-enabled traffic generator	Andreas Sandberg
2018-07-13	cpu: Support trace termination in BaseTrafficGen	Andreas Sandberg
2018-07-13	cpu: Unify error handling for address generators	Andreas Sandberg
2018-07-13	cpu: Split the traffic generator into two classes	Andreas Sandberg
2018-07-10	misc: Fix BaseCPU doxygen	Jason Lowe-Power
2018-07-09	arch-riscv: enable rudimentary fs simulation	Robert
2018-07-09	arch-riscv: Fix the srlw and srliw instructions.	Austin Harris
2018-06-29	base: Add a M5_PUBLIC and M5_LOCAL attribute macro	Andreas Sandberg
2018-06-28	python: Fix call bug in @cxxMethod when override is True	Andreas Sandberg
2018-06-28	cpu: Remove reduntant protobuf includes	Andreas Sandberg
2018-06-28	python: Fixup incorrect syntax in PyBind argument handler	Andreas Sandberg
2018-06-28	mem: Add a memory delay simulator	Andreas Sandberg
2018-06-28	arch-arm: Fix incorrect t{0,1}sz field in TTBCR	Andreas Sandberg
2018-06-28	base: Add an asymmetrical Coroutine class	Giacomo Travaglini
2018-06-26	gpu-compute: Remove unneeded Request::setVirt call	Alexandru Dutu
2018-06-26	python: Add support for multiplying proxies to compatible Param	Nikos Nikoleris
2018-06-26	scons: Generalize building binaries.	Gabe Black
2018-06-25	syscall_emul: adding symlink system call	Matt Sinclair
2018-06-25	syscall_emul: adding link system call	Matt Sinclair
2018-06-22	mem-cache: Promote deferred targets on cache clean responses	Nikos Nikoleris
2018-06-22	mem-cache: Promote targets that don't require writable	Nikos Nikoleris
2018-06-22	mem-cache: Fix promoting of targets that need writable	Nikos Nikoleris
2018-06-22	mem-cache: Selectively clear downstream pending	Nikos Nikoleris
2018-06-22	SConstruct: additional message for the error checking of the python 2.7 headers	Matteo M. Fusi
2018-06-22	arch-arm: AArch32 execution triggering AArch64 SW Break	Giacomo Travaglini
2018-06-22	arch-arm: BadMode checking if corresponding EL is implemented	Giacomo Travaglini
2018-06-21	base: Add a class which encapsulates Fibers.	Gabe Black
2018-06-21	sim: Use the canonical way of iterating over a dictionary	Andreas Sandberg
2018-06-21	dev-arm: Use recurseDeviceTree instead of custom in platform	Andreas Sandberg
2018-06-21	cpu: Fix bug introduced by RequestPtr type change	Giacomo Travaglini
2018-06-20	base: Fix includes in AddrRangeMap header file	Nikos Nikoleris
2018-06-20	mem-cache: Fix TempCacheBlock insert	Jason Lowe-Power
2018-06-19	mem: Use address range to find the right physical address	Nikos Nikoleris
2018-06-19	mem: Use address range to find the destination port in the xbar	Nikos Nikoleris
2018-06-19	mem: Use the caching in the AddrRangeMap class in PhysicalMemory	Gabe Black
2018-06-19	mem: Use the caching built into AddrRangeMap in the xbar	Gabe Black
2018-06-19	base: Build caching into the AddrRangeMap class	Gabe Black
2018-06-19	base, mem: Disambiguate if an addr range is contained or overlaps	Nikos Nikoleris
2018-06-19	mem-cache: Fix support for secure blocks in the FALRU cache	Nikos Nikoleris
2018-06-15	mem-cache: Initialize CacheBlk data pointer	Daniel R. Carvalho
2018-06-15	mem-cache: Forward declare ReplaceableEntry	Daniel R. Carvalho
2018-06-15	dev-arm: Fix the address range for some I/O devices	Nikos Nikoleris
2018-06-15	tests,style: add RISC-V assembly tests	Tuan Ta
2018-06-15	sim: Add a SimObject python field which overrides the default c++ base.	Gabe Black
2018-06-14	cpu: Prevent suspended TimingSimple CPUs from fetching next instructions	Tuan Ta
2018-06-14	cpu: add a new instruction type 'Atomic'	Tuan Ta
2018-06-14	arch: support issuing Atomic Mem Operation (AMO) requests	Tuan Ta