summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-03-21Request::getVaddr()is-rebase10-DynInstPtrIru Cai
Change-Id: Ife5c04941a9181da30e5cc692dec7cfd53feb71f
2019-03-20attack code and exp scriptIru Cai
2019-03-20invisispec-1.0 configsIru Cai
2019-03-20invisispec-1.0 sourceIru Cai
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
Summary: Usage of const DynInstPtr& when possible and introduction of move operators to RefCountingPtr. In many places, scoped references to dynamic instructions do a copy of the DynInstPtr when a reference would do. This is detrimental to performance. On top of that, in case there is a need for reference tracking for debugging, the redundant copies make the process much more painful than it already is. Also, from the theoretical point of view, a function/method that defines a convenience name to access an instruction should not be considered an owner of the data, i.e., doing a copy and not a reference is not justified. On a related topic, C++11 introduces move semantics, and those are useful when, for example, there is a class modelling a HW structure that contains a list, and has a getHeadOfList function, to prevent doing a copy to an internal variable -> update pointer, remove from the list -> update pointer, return value making a copy to the assined variable -> update pointer, destroy the returned value -> update pointer. Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-15mem-cache: fix invalid iterator accessJavier Bueno
An iterator was assigned end() and then it was used to access its corresponding element. Change-Id: I87246cf56cbc694dd6b4e2cabbe84a08429d2ac3 Reviewed-on: https://gem5-review.googlesource.com/c/14361 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Make StridePrefetcher use Replacement PoliciesDaniel
Previously StridePrefetcher was only able to use random replacement policy. This change allows all replacement policies to be applied to the pc table. Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14360 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Add invalidation function to StrideEntryDaniel
Add invalidation function to StrideEntry so that every entry can be invalidated appropriately. Change-Id: I38c42b7d7c93d839f797d116f1d2c88572123c0e Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14359 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Make PCTable context independentDaniel
Move the unordered_map outside of the PCTable, as it belongs to the StridePrefetcher. By doing so we are moving towards a table that ressembles the ones of the Tags classes. Some functions have been moved from the prefetcher to the PCTable, as they didn't belong there. As such, they have been renamed to remove the unnecessary prefix. Change-Id: I3e54bc7dee65e1f78d96b0d548ac8345b7bd4364 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14358 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Vectorize StridePrefetcher's entries.Daniel
Turn StridePrefetcher::PCTable::entries into a vector of vectors. Change-Id: I2a4589a76eb205910c43723638b7989eddd5ca24 Reviewed-on: https://gem5-review.googlesource.com/c/14357 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Return entry in StridePrefetcher::pcTableHit()Daniel
Return a pointer to the entry instead of returning a boolean and passing a pointer reference. As a side effect, change the name of the function to be more descriptive of the functionality. Change-Id: Iad44979e98031754c1d0857b1790c0eaf77e9765 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14356 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Cleanup prefetchersDaniel
Prefetcher code had extra variables, dependencies that could be removed, code duplication, and missing overrides. Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14355 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15scons: add --gold-linker to link with the gold linkerCiro Santilli
This option can significantly speedup link time on Linux systems, which is the main bottleneck to rebuild after small changes. Change-Id: I3b0bdd61f7dcef0d73629c8ee2ee98091953fec3 Reviewed-on: https://gem5-review.googlesource.com/c/14075 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
The LTAGE paper states 1 hyst bit shared for 4 pred bits. Made this ratio configurable use 4 by default. Also changed the Bimodal structure to use two std::vector<bool> (one for pred and one for hyst bits) Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14120 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-14mem-cache: Remove Cache dependency from TagsDaniel R. Carvalho
Tags do not need to be aware of caches. Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14296 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-14mem-cache: Move access latency calculation to CacheDaniel R. Carvalho
Access latency was not being calculated properly, as it was always assuming that for hits reads take as long as writes, and that parallel accesses would produce the same latency for read and write misses. By moving the calculation to the Cache we can use the write/ read information, reduce latency variables duplication and remove Cache dependency from Tags. The tag lookup latency is still calculated by the Tags. Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13697 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-14arch-arm: Print register name when warning on AT instructionsGiacomo Travaglini
With this patch we don't print anymore the enum value when warning on any AT instruction usage, but we print the sys reg name instead Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14316 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-14mem-cache: implement a probe-based interfaceJavier Bueno
The HW Prefetcher of a cache can now listen events from their associated CPUs and from its own cache. Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3 Reviewed-on: https://gem5-review.googlesource.com/c/14155 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-14sim: Move BitUnion overloading to show/parseParamsGiacomo Travaglini
This patch is moving template overloading for BitUnions into the showParam, parseParams functions. Henceforth BitUnion types will use the common param wrapper. This patch implicitly implements (UN)SERIALIZE_CONTAINER for BitUnions. Change-Id: I0e1faadb4afd4dc9de5dc5fca40041e349c9ba73 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13636 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-14sim: Move paramIn/Out definition to header fileGiacomo Travaglini
This patch is moving the definitions of paramIn/Out templates to the header file. In this way we gain: 1) We don't have to do explicit instantiation anymore for user defined types. This spares us from including data type header files into serialize.cc 2) We can overload show/parseParam for BitUnions or any other type that requires special handling when serializing. Just by overloading the two templates we get all the containers' (list, vector, array..) serialization for free 2) gtest: With the idea of adding unit tests for Serializable objects, we can avoid importing serialize.cc and just redefine Serializable methods in the test source, implementing a Serializable stub Change-Id: I45a9bb87d5ef886a3668fd477005cd105f612e36 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13635 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
The PC needs to be shifted according to the instShiftAmt parameter Change-Id: I272619c093695b56cf7f8ff7163e3b5d23205d16 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14035 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-13mem-cache: Align how we handle requests in atomic with timingNikos Nikoleris
Requests, for which a cache has already committed to respond do not perform any lookups. Previously in atomic mode the packet would pay the lookup latency while in timing it wouldn't. This patch aligns recvAtomic with recvTimingReq and removes the lookup latency from the the handling of such requests. Change-Id: I50a0631f8058e5086d94d55af0e1788a60e2883f Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14175 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-12systemc: Push python headers on top of sourcesGiacomo Travaglini
Some build failures has been seen after USE_SYSTEMC being True by default and that has been caused by double definition of _XOPEN_SOURCE and _POSIX_C_SOURCE in some python versions (like 2.7.5, 2.7.13) and /usr/include/features.h (used by gcc) Python definition should preceed features.h one, since the latter will manually #undef them before #define them. Change-Id: I774711aaf8145df9ad7677a393a60cf3662d6816 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14095 Maintainer: Gabe Black <gabeblack@google.com>
2018-11-12systemc: Stop using python to set/manage the global time resolution.Gabe Black
Now that that's managed in c++, we can do that directly without having to depend on the python code being available, the code which lets us call from c++ to python, or for the embedded python interpretter to have started running and have loaded the appropriate modules. Change-Id: Ied110d8f22181095f8c0c645636a9bd67964263e Reviewed-on: https://gem5-review.googlesource.com/c/14056 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-12sim: Push the global frequency management code into C++.Gabe Black
That makes it available when python is left out, and makes it available to c++ code without having to call back into python. Change-Id: If82e7e8eff526f2b957f84afe046e1d56fed4aa2 Reviewed-on: https://gem5-review.googlesource.com/c/14055 Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-09configs: Revamp ruby mem test to align with MemTestNikos Nikoleris
The test script was broken as it was based on an older version of MemTest, this changes revamps the creation of MemTest and removes parameters that are not any longer valid. Change-Id: Ib87369c1e4717c2da23e8108c72eec871e56f6ed Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13596 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-09systemc: Get rid of a duplicated base class initializer for sc_fifo.Gabe Black
These were consistent, but redundant and incorrect none the less. Change-Id: I9ff7fdb9c83f9a8af6fbe969c6c73b9aab8967ad Reviewed-on: https://gem5-review.googlesource.com/c/14136 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-09systemc: Add a missing "const" on one of the sc_event operators.Gabe Black
Change-Id: I073ccb0f2c6d1bfebadb95869d6acf7f4ce565af Reviewed-on: https://gem5-review.googlesource.com/c/14135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-09systemc: Only build python utility code if python is enabled.Gabe Black
Change-Id: I58054ddd0d5ef0dbee18028c4218e7418347f959 Reviewed-on: https://gem5-review.googlesource.com/c/13979 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-09systemc: Separate and conditionalize exposing sc_main to python.Gabe Black
Change-Id: Ib39dd79c607b277ba94f90dee41c09c1b3b66481 Reviewed-on: https://gem5-review.googlesource.com/c/13978 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-09systemc: Seperate out the sc_main fiber and its bookkeeping.Gabe Black
By pulling out the sc_main fiber (scMainFiber), we can make it available to different entities in the simulator and avoid having to have parallel bookkeeping. Also this will make it possible to hook into sc_main without putting the code in sc_main.cc. Change-Id: I7689441424238e9b2e4d2b48e945dea35fd8cc5d Reviewed-on: https://gem5-review.googlesource.com/c/13977 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-09systemc: Stop using python init to set up predefined message ids.Gabe Black
We can now be sure register_id will work even mid static initializers, so we don't have to use python initialization as a hook to install these predefined message ids. Change-Id: I2e4d0c678ddda0a9ce5b114bdf1710f36e955f23 Reviewed-on: https://gem5-review.googlesource.com/c/13976 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-09systemc: Wrap some report maps in functions.Gabe Black
By declaring the map as a static variable in that function and then returning it, we can guarantee that it's initialized relative to other static initializers so that we don't try to use a data structure that isn't constructed yet. This will let us get rid of the dependence on python for setting up that mapping. Change-Id: I031ce2039de8f5f79fbb9d76cf1363f15207b64b Reviewed-on: https://gem5-review.googlesource.com/c/13975 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-08configs: Add missing path to ruby importsDaniel R. Carvalho
Add missing addToPath to ruby files, so that import modules from previous folder are visible. Change-Id: I912d78a2f709974f72fe768e73abac1617126f46 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13995 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-07mem-ruby: Use Packet writing functions instead of memcpyDaniel R. Carvalho
Classes were using memcpy instead of the Packet functions created for writing to/from the packet. This allows these writes to be better checked and tracked. Change-Id: Iae3fba1351330916ee1d4103809c71e151b1639e Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13915 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-07misc: Update workflow requirements in CONTRIBUTING.mdTony Gutierrez
Change-Id: I5394ef58930fccea343414964c1fc3e18829d609 Reviewed-on: https://gem5-review.googlesource.com/c/13755 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-07arch-arm: Deprecate usage of legacy bootloader patchingGiacomo Travaglini
This patch is implicitly deprecating the usage of bootloader patching, which is injecting instructions from gem5 into the bootloader binary. This was probably meant to provide a dynamic bootloader entry point. This is not needed in ARMv8.0, since we can simply update the ArmSystem::resetAddress with the bootloader entry point. Change-Id: I0c469873b8d69f7b49a7383e0754468bc1f2bd72 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14001 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32Giacomo Travaglini
ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Implement AArch32 RVBARGiacomo Travaglini
RVBAR has been added to the system register list since ARMv8.0-A. It is implemented only if the highest Exception Level is different (minor) than EL3. If that's not the case, MVBAR is used. Since the two registers are mutually exclusive (depending on the presence of EL3), they share the same coprocessor numbers: p15, 0, c12, c0, 1 Rather than introducing a new register alias, we overload MVBAR so that it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR). N.B MVBAR is RW, whereas RVBAR is RO Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13999 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Remove SCTLR.VE bitGiacomo Travaglini
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are removing it from gem5 since we were not handling it anyway. Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13998 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Refactor ISA::clear by adding a ISA::clear32 methodGiacomo Travaglini
The patch is also moving some initialization code to be used by AArch64 as well since the registers are mapped to AArch64 ones. Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13997 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Remove MISCREG commented numbersGiacomo Travaglini
Having an enum number might be useful in case we wanted to know how many miscregs we have, but on the other hand it makes it tedious to update the register list, since every commented number must be bumped. This patch is removing the comments holding the MISCREG numbers Change-Id: Ic5aba93885e4b8d6cb3bd6a4c49900b9e5474276 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13996 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07systemc: Fix some paths in the tlm SCons(script|struct).Gabe Black
The code in util/systemc was moved into a subdirectory recently. The scons support here referred to it, and needed to be updated. Change-Id: Ib457d9bdafb2bba5058e6ecf99b9d33b3072c5b3 Reviewed-on: https://gem5-review.googlesource.com/c/13955 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-06mips: Change the integer and fp register widths to be 64 bits.Gabe Black
This makes them more consistent with the other architectures, helping to facilitate having a single, unified type across ISAs in the future. Change-Id: I65efb10e39d453281b8429eeedbb46fa6b023a2b Reviewed-on: https://gem5-review.googlesource.com/c/13620 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-06mips: Clean up type overrides for operands.Gabe Black
For operands which default to uw (uint32_t), there's no reason to explicitly specify that all over the place. Also, when assigning to a 32 bit value which is supposed to be the full width of the resulting register, there's no reason to override the value to be signed. If the value is expanded into a larger value, then extra bits may get set unintentionally through sign extension. Even if an instruction produces a value which should be interpreted as signed, it will still only produce a value of a certain predefined width, even if that answer ends up stored in a larger variable. Change-Id: I048d68c5dd08a1d40e8117ae9d36d70e05ec21c8 Reviewed-on: https://gem5-review.googlesource.com/c/13618 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-06mips: Explicitly truncate the syscall return value down to 32 bits.Gabe Black
The IntReg type is 32 bits, and using it to cast the syscall return value is appropriate, but we're attempting to get rid of the ISA specific register types. Change-Id: I42496dd2cc086a6b718e1ce087fef81bb897d02f Reviewed-on: https://gem5-review.googlesource.com/c/13619 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-05null: Claim to use 64 bit floating point registers.Gabe Black
The NULL ISA doesn't actually have registers, so this setting doesn't matter. By making it 64 bits the ISA is more compatible with the other ISAs. Change-Id: I2c9b6d9a6f612719b8b00eb9dbed55fa2159e9b5 Reviewed-on: https://gem5-review.googlesource.com/c/13617 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-05sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.Gabe Black
These types aren't used by the ISA itself since they're defined to be particular primitive types in the ISA description. This just affects code outside of the ISA which work with those types of registers. Change-Id: I4f62ab8fe04184cc23845090c82b250145a71747 Reviewed-on: https://gem5-review.googlesource.com/c/13616 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-05base: Add standard types for floating and nonfloating point register values.Gabe Black
These should be used instead of the ISA specific ones, and should be at least as large as the largest primitive register type in all the ISAs. Change-Id: Iaac104eef74eabcdd87787b1cdf8bea22d449eda Reviewed-on: https://gem5-review.googlesource.com/c/13615 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-05systemc: Enable systemc support by default.Gabe Black
Change-Id: I9375518a54e14413a499d065f5bc5e1031834c81 Reviewed-on: https://gem5-review.googlesource.com/c/13535 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-05 16:48:46 +0000