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gem5
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invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
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is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
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decoder.isa
Age
Commit message (
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Author
2006-05-22
New directory structure:
Steve Reinhardt
2006-05-12
Merge zeep.pool:/z/saidi/work/m5.head
Ali Saidi
2006-05-11
make m5 panic a little more verbose
Ali Saidi
2006-04-18
Changed MIPS and Alpha to pass the syscall number to the syscall function
Gabe Black
2006-03-05
Merge ktlim@zizzer:/bk/m5
Kevin Lim
2006-03-04
Steps towards setting up the infrastructure to allow the new CPU model to wor...
Kevin Lim
2006-03-03
Merge ktlim@zizzer:/bk/m5
Kevin Lim
2006-03-03
Changes to support automatic renaming of the shadow registers at decode time....
Kevin Lim
2006-03-01
Merge zizzer:/bk/m5
Ali Saidi
2006-02-28
Add quiesceNs, quiesceTime, quiesceCycles, and m5panic pseudo ops.
Ali Saidi
2006-02-28
Merge ktlim@zizzer:/bk/m5
Kevin Lim
2006-02-27
Changes to put all the misc regs within the misc reg file. This includes the...
Kevin Lim
2006-02-24
Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appr...
Gabe Black
2006-02-16
Changed the fault enum into a class, and fixed everything up to work with it....
Gabe Black
2006-02-12
Pseudo instructions are now passed whatever instructions they need by the dec...
Gabe Black
2006-02-11
Add keyword parameters and list-valued arguments to
Steve Reinhardt
2006-02-10
Change how memory operands are handled in ISA descriptions.
Steve Reinhardt
2006-02-09
Split Alpha ISA description into multiple files
Steve Reinhardt