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path: root/configs/example/memtest.py
AgeCommit message (Expand)Author
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
2018-03-06config: Switch from the print statement to the print function.Gabe Black
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
2015-12-17configs: Make the default memtest behaviour more complexAndreas Hansson
2015-11-06config: Update memtest to stress test clean writebacksAndreas Hansson
2015-11-06config: Update memtest to stress test cache clusivityAndreas Hansson
2015-08-21mem: Add explicit Cache subclass and make BaseCache abstractAndreas Hansson
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-03-19config: Add soak test for memtest.pyAndreas Hansson
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-02-16config: Add memcheck stress testAndreas Hansson
2015-02-11config: Revamp memtest to allow testers on any levelAndreas Hansson
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-08-10config: Fix cache latency param in mem testRadhika Jagtap
2013-10-17config: Fix memtest example scriptAli Saidi
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2012-09-27Configs: Fix memtest cache latency to match new parametersAndreas Hansson
2012-09-27Configs: Fix memtest.py by moving the system portAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2010-08-25memtest: scale associativity and mshrs according to configSteve Reinhardt
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
2007-07-15Fix problem with unset max_loads in memtest.Steve Reinhardt
2007-07-15Punt on old -n/-c memtest args.Steve Reinhardt
2007-07-15Add --force-bus option to memtest.py.Steve Reinhardt
2007-07-14New tree-based algorithm for creating more complex cache hierarchies.Steve Reinhardt
2007-06-27Get rid of coherence protocol object.Steve Reinhardt
2007-06-21Getting closer...Steve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-05-22memtest.py:Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2006-11-12Update for maxtick in splash2/memtest configsRon Dreslinski
2006-10-20Give physical memory some latency to stress the systemRon Dreslinski
2006-10-20Add a config file in the example with the memtester and some parser options.Ron Dreslinski