gem5 - gem5

Age	Commit message (Expand)	Author
2018-09-10	configs: Use the same address ranges for dir and mem_ctrls	Nikos Nikoleris
2018-03-20	arch-arm, configs: Treat the bootloader rom as cacheable memory	Nikos Nikoleris
2017-06-13	ruby: Add support for address ranges in the directory	Nikos Nikoleris
2015-07-20	ruby: more flexible ruby tester support	Brad Beckmann
2015-08-30	ruby: specify number of vnets for each protocol	Nilay Vaish
2015-08-21	ruby: Move Rubys cache class from Cache.py to RubyCache.py	Andreas Hansson
2015-08-14	ruby: Protocol changes for SimObject MessageBuffers	Joel Hestness
2015-08-14	ruby: Remove the RubyCache/CacheMemory latency	Joel Hestness
2015-07-10	ruby: remove extra whitespace and correct misspelled words	Brandon Potter
2014-12-04	config: ruby: mi protocol: correct master slave setting for dma	Nilay Vaish
2014-11-06	x86 isa: This patch attempts an implementation at mwait.	Marc Orr
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-11-06	ruby: single physical memory in fs mode	Nilay Vaish
2014-09-01	ruby: message buffers: significant changes	Nilay Vaish
2014-09-01	ruby: Fixes clock domains in configuration files	Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-03-17	config: ruby: remove piobus from protocols	Nilay Vaish
2014-02-24	ruby: correct errors in changeset 4eec7bdde5b0	Nilay Vaish
2014-01-04	ruby: remove cntrl_id from python config scripts.	Nilay Vaish
2013-08-20	ruby: add option for number of transitions per cycle	Nilay Vaish
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-06-28	ruby: check for compatibility between mem size and num dirs	Nilay Vaish
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-01-14	config: move ruby objects under ruby_system in obj hierarchy	Malek Musleh
2012-09-19	AddrRange: Simplify AddrRange params Python hierarchy	Andreas Hansson
2012-08-16	Ruby: Add RubySystem parameter to MemoryControl	Jason Power
2012-07-10	ruby: changes how Topologies are created	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2011-07-26	Ruby: Fix instantiations of DMA controller and sequencer	Nilay Vaish
2011-07-25	Ruby: Fix dma controller configs/ruby/MI_example.py	Nilay Vaish
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-05-23	config: tweak ruby configs to clean up hierarchy	Steve Reinhardt
2011-04-28	network: convert links & switches to first class C++ SimObjects	Brad Beckmann
2011-03-28	Config: Import math in MI_example.py	Nilay Vaish
2011-03-25	ruby: fixed cache index setting	Brad Beckmann
2010-08-20	memtest: Memtester support for DMA	Brad Beckmann
2010-08-20	config: Improve ruby simobject names	Brad Beckmann
2010-08-20	config: reorganized how ruby specifies command-line options	Brad Beckmann
2010-08-20	config: moved python protocol config files	Brad Beckmann
2010-03-21	ruby: Reorganized Ruby topology and protocol files	Brad Beckmann
2010-03-21	ruby: Ruby support for sparse memory	Brad Beckmann
2010-03-21	ruby: Python config files now sets a unique id for each sequencer	Brad Beckmann
2010-01-29	ruby: MI_example updates to use the new config system	Brad Beckmann