gem5 - gem5

Age	Commit message (Expand)	Author
2006-05-22	New directory structure:	Steve Reinhardt
2006-05-18	Change Packet parameters on Port methods from references to pointers.	Steve Reinhardt
2006-05-17	Get basic full-system working with AtomicSimpleCPU.	Steve Reinhardt
2006-04-28	devices should increment pkt.time instead of assiging to it	Ali Saidi
2006-04-24	Mostly done with all device models for new memory system. Still need to get t...	Ali Saidi
2006-04-20	make ide disk work for newmem	Ali Saidi
2006-04-11	fullsys now builds and runs for about one cycle	Ali Saidi
2006-04-10	Panic if physical memory isn't connected to anything	Ali Saidi
2006-04-10	Merge zizzer:/bk/newmem	Ali Saidi
2006-04-10	updates for newmem	Ali Saidi
2006-04-07	Move to a model with a unified request object.	Ron Dreslinski
2006-04-06	fixes for new memory system	Ali Saidi
2006-03-29	move stuff around so PageShift is defined before it is needed	Ali Saidi
2006-03-25	Implement a very very simple bus	Ali Saidi
2006-03-21	Make PioPort/DmaPort,DmaDevice/PioDevice compile.	Ali Saidi
2006-02-21	Rename port methods:	Steve Reinhardt
2006-01-31	changed sendresult -> bool,tick,void as appropriate	Ali Saidi
2005-06-05	Many files:	Steve Reinhardt
2005-01-15	New and improved configuration mechanism. No more writing of	Nathan Binkert
2004-07-12	make the cache access latency a parameter that is based on bus	Nathan Binkert
2004-06-08	Updated Copyright with information in bitkeeper changelogs	Ali Saidi
2004-04-06	Beta version of Python configuration tool. Generates .ini files from	Steve Reinhardt
2004-02-20	make the dma interface useable.	Nathan Binkert
2004-02-11	Add support for all devices to get requests from a timing memory bus.	Nathan Binkert