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path: root/src/arch/arm/isa.cc
AgeCommit message (Expand)Author
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.Ali Saidi
2010-11-08ARM: Keep the warnings to a minimum.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-01ARM: Clean up use of TBit and JBit.Ali Saidi
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-25ARM: Set the high bits in the part number so it's considered new by some code.Ali Saidi
2010-08-25ARM: Fix VFP enabled checks for mem instructionsAli Saidi
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-23ARM: Clean up flattening for SPSR addingMin Kyu Jeong
2010-08-23ARM: Get SCTLR TE bit from reset SCTLRGene Wu
2010-08-23ARM: We don't currently support ThumbEE exceptions, so don't report that we doAli Saidi
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-06-03ARM: Fix issue with m5.fast and ARMAli Saidi
2010-06-02ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...Dam Sunwoo
2010-06-02ARM: Move the ISA "clear" function into isa.cc.Gabe Black
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Move Miscreg functions out of isa.hhAli Saidi