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isa.cc
Age
Commit message (
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Author
2019-11-25
arch-arm: default MIDR for Armv8 ISA processors
Adrian Herrera
2019-11-18
arch-arm: R/W interface to AArch32 HCR2 misc reg
Adrian Herrera
2019-10-19
arch: Make a base class for Interrupts.
Gabe Black
2019-09-19
arch-arm: PSTATE.PAN changes should inval cached regs in TLB
Giacomo Travaglini
2019-09-06
arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs
Giacomo Travaglini
2019-08-07
arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero
2019-08-05
arch-arm: Implement ARMv8.1-PAN, Privileged access never
Giacomo Travaglini
2019-05-23
arch-arm: Expose haveGicv3CPUInterface to the ISA interface
Giacomo Travaglini
2019-04-25
arch-arm: Remove un-needed hyp flag in TLBI operations
Giacomo Travaglini
2019-04-25
arch-arm: Correct target EL field in TLBI operations
Giacomo Travaglini
2019-04-02
dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Giacomo Travaglini
2019-03-14
arch-arm,cpu: Add initial support for Arm SVE
Giacomo Gabrielli
2019-02-18
arch-arm: Move GICv3 detection at startup time
Giacomo Travaglini
2019-01-25
arch-arm: Inital vector rename mode depending on A32/A64
Giacomo Travaglini
2019-01-22
arch: cpu: Stop passing around misc registers by reference.
Gabe Black
2019-01-22
arm: Get rid of some register type definitions.
Gabe Black
2019-01-16
arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled
Giacomo Travaglini
2019-01-16
arch-arm: Added TLBI_ALL EL2 instruction
Anouk Van Laer
2019-01-10
dev-arm: Add a GICv3 model
Jairo Balart
2019-01-03
arm: properly handle RES0/1 for SCTLRs
Curtis Dunham
2018-12-19
arch-arm: Add Crypto in SE mode
Giacomo Travaglini
2018-11-14
arch-arm: Print register name when warning on AT instructions
Giacomo Travaglini
2018-11-07
arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32
Giacomo Travaglini
2018-11-07
arch-arm: Refactor ISA::clear by adding a ISA::clear32 method
Giacomo Travaglini
2018-10-09
arch-arm: Add have_crypto System parameter
Giacomo Travaglini
2018-10-01
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
Giacomo Travaglini
2018-10-01
arch-arm: Init AArch64 ID registers in SE mode
Giacomo Travaglini
2018-09-10
arm: Add support for tracking TCs in ISA devices
Andreas Sandberg
2018-07-16
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Giacomo Travaglini
2018-06-14
arch-arm: Add Illegal Execution flag to PCState
Giacomo Travaglini
2018-06-11
misc: Using smart pointers for memory Requests
Giacomo Travaglini
2018-05-29
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
Giacomo Travaglini
2018-05-08
arch-arm: Map ID_x_EL1 registers to AArch32 version
Giacomo Travaglini
2018-04-19
arch-arm: Add ARMv8.1 TTBR1_EL2 register
Giacomo Travaglini
2018-04-18
arch-arm: Fix masking in CPACR_EL1
Chuan Zhu
2018-04-18
arch-arm: Mask out unsupported trapped exception handling bits
Chuan Zhu
2018-04-18
arch-arm: Correct masking of cp10 and cp11 in CPACR
Chuan Zhu
2018-04-18
arch-arm: Using explicit invalidation in TLB
Giacomo Travaglini
2018-04-06
arch-arm: Fix secure write of SCTLR when EL3 is AArch64
Giacomo Travaglini
2018-03-23
arch-arm: Distinguish IS TLBI from non-IS
Giacomo Travaglini
2018-03-23
arch-arm: Created function for TLB ASID Invalidation
Giacomo Travaglini
2018-03-12
arch-arm: Adding IPA-Based Invalidating instructions
Giacomo Travaglini
2018-03-12
arch-arm: Implement missing aarch32 TLBI registers
Giacomo Travaglini
2018-03-08
arch-arm: Fix FSC generation in AbortFault
Giacomo Travaglini
2018-02-16
arch-arm: Change ArmFault cast from reinterpret to static
Giacomo Travaglini
2018-02-08
arch-arm: Don't change PSTATE in Illegal Exception return
Giacomo Travaglini
2018-01-29
arch-arm: understandably initialize register permissions
Curtis Dunham
2018-01-29
arm: extend MiscReg metadata structures
Curtis Dunham
2018-01-29
arch-arm: understandably initialize register mappings
Curtis Dunham
2017-12-22
arch,cpu: "virtualize" the TLB interface.
Gabe Black
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