gem5 - gem5

Age	Commit message (Expand)	Author
2017-10-13	arch-arm: Signal an event when executing store exclusives	Nikos Nikoleris
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2011-09-26	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	Gabe Black
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-03-17	ARM: Previous change didn't end up setting instFlags, this does.	Ali Saidi
2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell
2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
2010-08-25	ARM: Fix VFP enabled checks for mem instructions	Ali Saidi
2010-08-23	ARM: Exclusive accesses must be double word aligned	Ali Saidi
2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi
2010-06-02	ARM: Implement the vstr instruction.	Gabe Black
2010-06-02	ARM: Implement the SRS instruction.	Gabe Black
2010-06-02	ARM: Implement the strex instructions.	Gabe Black
2010-06-02	ARM: Respect the E bit of the CPSR when doing loads and stores.	Gabe Black
2010-06-02	ARM: Implement the V7 version of alignment checking.	Gabe Black
2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black
2010-06-02	ARM: Remove the special naming for the new memory instructions.	Gabe Black
2010-06-02	ARM: Pull double memory instructions out of the decoder.	Gabe Black
2010-06-02	ARM: Define the store instructions from outside the decoder.	Gabe Black