| Age | Commit message (Expand) | Author |
|---|
| 2019-10-19 | arch: Make a base class for Interrupts. | Gabe Black |
| 2019-10-16 | arch,base,sim: Move Process loader hooks into the Process class. | Gabe Black |
| 2019-10-12 | arch,base: Separate the idea of a memory image and object file. | Gabe Black |
| 2019-10-10 | arch,base: Stop loading the interpreter in ElfObject. | Gabe Black |
| 2019-10-10 | arch, base: Stop assuming object files have three segments. | Gabe Black |
| 2019-10-09 | base: Rename Section to Segment, and some of its members. | Gabe Black |
| 2019-09-13 | sparc: Fix a warning/error in tlb.cc. | Gabe Black |
| 2019-05-30 | arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. | Gabe Black |
| 2019-05-30 | arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s. | Gabe Black |
| 2019-05-29 | sim-se: add a release parameter to Process.py | Ciro Santilli |
| 2019-05-29 | arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods. | Gabe Black |
| 2019-05-21 | sim-se: change syscall function signature | Brandon Potter |
| 2019-05-20 | sparc: Add an object file loader for linux and solaris. | Gabe Black |
| 2019-04-30 | arch: Stop using TheISA within the ISAs. | Gabe Black |
| 2019-04-30 | sparc: Move translation constants from isa_traits.hh into tlb.hh. | Gabe Black |
| 2019-04-30 | sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh. | Gabe Black |
| 2019-04-30 | arch: Remove the mt.hh switching header. | Gabe Black |
| 2019-04-28 | arch, sim: Simplify the AuxVector type. | Gabe Black |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-22 | sparc: Get rid of some register type definitions. | Gabe Black |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
| 2019-01-16 | arch: Make the ISA register types aliases for the global types. | Gabe Black |
| 2019-01-10 | sim-se: Refactor clone to avoid most ifdefs | Andreas Sandberg |
| 2018-11-05 | sparc: Switch the FloatReg and FloatRegBits types to be 64 bit. | Gabe Black |
| 2018-10-17 | arch: Get rid of the unused type AnyReg. | Gabe Black |
| 2018-10-12 | sparc: Use big endian packet accessors. | Gabe Black |
| 2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-03-27 | sparc: Add some missing M5_FALLTHROUGHs and breaks. | Gabe Black |
| 2018-03-26 | arch: Fix all override related warnings. | Gabe Black |
| 2018-03-26 | arch: Add a virtual asBytes function to the StaticInst class. | Gabe Black |
| 2018-03-08 | sparc: Passify a new g++ warning. | Gabe Black |
| 2018-02-24 | sparc: Fix FS Checkpoint loading | Khalique |
| 2018-02-13 | sim: Make Stats truly non-copy-constructible | Rekai Gonzalez-Alberquilla |
| 2018-01-23 | tarch, mem: Abstract the data stored in the SE page tables. | Gabe Black |
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
