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path: root/src/cpu/base_dyn_inst.hh
AgeCommit message (Expand)Author
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-15cpu, o3: consider split requests for LSQ checksnoop operationsHongil Yoon
2015-08-07base: Declare a type for context IDsAndreas Sandberg
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-05-15misc: Appease gcc 5.1Andreas Hansson
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-03-02cpu: o3 register renaming request handling improvedRekai
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-01-25sim: Clean up InstRecordAli Saidi
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2013-10-17cpu: Fix O3 uncacheable load that is replayed but misses the TLBAli Saidi
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-07Faults: Turn off arch/faults.hhGabe Black
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2011-11-18SE/FS: Get rid of includes of config/full_system.hh.Gabe Black
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
2011-08-14O3: Add a pointer to the macroop for a microop in the dyninst.Gabe Black
2011-08-07Translation: Use a pointer type as the template argument.Gabe Black
2011-08-02O3: Get rid of the raw ExtMachInst constructor on DynInsts.Gabe Black
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ExecContext: Get rid of the now unused read/write templated functions.Gabe Black
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
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