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path: root/src/cpu/checker/cpu.cc
AgeCommit message (Expand)Author
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2017-12-05cpu: Add support for CMOs in the cpu modelsNikos Nikoleris
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2014-10-29cpu: Add support to checker for CACHE_BLOCK_ZERO commands.Ali Saidi
2014-09-27scons: Address issues related to gcc 4.9.1Andreas Hansson
2014-09-12style: Fix line continuation, especially in debug messagesAndrew Bardsley
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-08-28Checker: Fix checker CPU portsAndreas Hansson
2012-05-10gem5: fix a number of use after free issuesAli Saidi
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-07Checker: Access workload element 0 only if there is an element 0.Gabe Black
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-04-15includes: sort all includesNathan Binkert
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2009-11-10Mem: Eliminate the NO_FAULT request flag.Gabe Black
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-15ThreadState: initialize status to Halted in constructor.Steve Reinhardt
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2007-02-12some forgotten commitsAli Saidi
2006-11-07Put kernel_stats back into arch.Gabe Black
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
2006-06-22Split Checker up properly into templated and non-templated definitions.Kevin Lim
2006-06-17Split off instantiation into separate CC files for each of the models. This ...Kevin Lim
2006-06-16Miscellaneous minor fixes.Kevin Lim
2006-06-16Checker updates.Kevin Lim