gem5 - gem5

Age	Commit message (Expand)	Author
2018-11-28	cpu,arch-arm: Initialise data members	Rekai Gonzalez-Alberquilla
2018-06-11	misc: Using smart pointers for memory Requests	Giacomo Travaglini
2018-06-11	misc: Substitute pointer to Request with aliased RequestPtr	Giacomo Travaglini
2018-04-27	sim,cpu,mem,arch: Introduced MasterInfo data structure	Giacomo Travaglini
2017-12-05	cpu: Add support for CMOs in the cpu models	Nikos Nikoleris
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-08-15	cpu, arch: fix the type used for the request flags	Nikos Nikoleris
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-02-11	sim: Move the BaseTLB to src/arch/generic/	Andreas Sandberg
2015-01-22	mem: Clean up Request initialisation	Andreas Hansson
2014-10-29	cpu: Add support to checker for CACHE_BLOCK_ZERO commands.	Ali Saidi
2014-09-27	scons: Address issues related to gcc 4.9.1	Andreas Hansson
2014-09-12	style: Fix line continuation, especially in debug messages	Andrew Bardsley
2014-05-13	mem: Refactor assignment of Packet types	Curtis Dunham
2014-01-24	checker: CheckerCPU handling of MiscRegs was incorrect	Geoffrey Blake
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-03-26	cpu: Remove CpuPort and use MasterPort in the CPU classes	Andreas Hansson
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-08-28	Checker: Fix checker CPU ports	Andreas Hansson
2012-05-10	gem5: fix a number of use after free issues	Ali Saidi
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-07	Checker: Access workload element 0 only if there is an element 0.	Gabe Black
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2009-11-10	Mem: Eliminate the NO_FAULT request flag.	Gabe Black
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2009-04-15	ThreadState: initialize status to Halted in constructor.	Steve Reinhardt
2009-02-25	ISA: Replace the translate functions in the TLBs with translateAtomic.	Gabe Black
2009-02-25	CPU: Get rid of translate... functions from various interface classes.	Gabe Black
2007-02-12	some forgotten commits	Ali Saidi
2006-11-07	Put kernel_stats back into arch.	Gabe Black
2006-10-31	Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...	Kevin Lim
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
2006-10-19	refactor code for the packet, get rid of packet_impl.hh	Nathan Binkert
2006-10-08	Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().	Steve Reinhardt
2006-06-22	Split Checker up properly into templated and non-templated definitions.	Kevin Lim
2006-06-17	Split off instantiation into separate CC files for each of the models. This ...	Kevin Lim
2006-06-16	Miscellaneous minor fixes.	Kevin Lim