gem5 - gem5

Age	Commit message (Expand)	Author
2015-04-20	cpu: Remove the InOrderCPU from the tree	Andreas Hansson
2015-02-11	mem: restructure Packet cmd initialization a bit more	Steve Reinhardt
2015-01-25	sim: Clean up InstRecord	Ali Saidi
2014-12-02	mem: Add const getters for write packet data	Andreas Hansson
2014-09-19	arch: Pass faults by const reference where possible	Andreas Hansson
2014-05-13	mem: Refactor assignment of Packet types	Curtis Dunham
2014-01-24	cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...	Ali Saidi
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-06-20	InOder: Fix a compile error.	Gabe Black
2011-06-19	inorder: cleanup dprintfs in cache unit	Korey Sewell
2011-06-19	inorder: SE mode TLB faults	Korey Sewell
2011-06-19	inorder: se compile fixes	Korey Sewell
2011-06-19	inorder: add necessary debug flag header files	Korey Sewell
2011-06-19	inorder/dtb: make sure DTB translate correct address	Korey Sewell
2011-06-19	inorder: handle serializing instructions	Korey Sewell
2011-06-19	inorder: dont handle multiple faults on same cycle	Korey Sewell
2011-06-19	inorder: register ports for FS mode	Korey Sewell
2011-06-19	inorder: check for interrupts each tick	Korey Sewell
2011-06-19	inorder: squash and trap behind a tlb fault	Korey Sewell
2011-06-19	inorder: stall stores on store conditionals & compare/swaps	Korey Sewell
2011-06-19	inorder: remove memdep tracking for default pipeline	Korey Sewell
2011-06-19	inorder: don't stall after stores	Korey Sewell
2011-06-19	inorder: don't stall after stores	Korey Sewell
2011-06-19	inorder: support for compare and swap insts	Korey Sewell
2011-06-19	inorder: add flatDestReg member to dyninst	Korey Sewell
2011-06-19	inorder: implement trap handling	Korey Sewell
2011-06-19	inorder: DynInst handling of stores for big-endian ISAs	Korey Sewell
2011-06-19	inorder: simplify handling of split accesses	Korey Sewell
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-02-23	inorder: cache packet handling	Korey Sewell
2011-02-18	inorder: fix cache/fetch unit memory leaks	Korey Sewell
2011-02-18	inorder: update pipeline interface for handling finished resource reqs	Korey Sewell
2011-02-18	inorder: remove request map, use request vector	Korey Sewell
2011-02-18	inorder: remove reqRemoveList	Korey Sewell
2011-02-18	inorder: initialize res. req. vectors based on resource bandwidth	Korey Sewell
2011-02-12	inorder: clean up the old way of inst. scheduling	Korey Sewell
2011-02-12	inorder: utilize cached skeds in pipeline	Korey Sewell
2011-02-04	inorder: fault handling	Korey Sewell
2011-02-04	inorder: add a fetch buffer to fetch unit	Korey Sewell