gem5 - gem5

Age	Commit message (Expand)	Author
2014-10-09	cpu: Remove Ozone CPU from the source tree	Mitch Hayenga
2013-01-07	cpu: Rename defer_registration->switched_out	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-04-15	includes: sort all includes	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2008-02-10	Fix #include lines for renamed cache files.	Steve Reinhardt
2007-10-02	CPU: Make the cpuid parameter get set in SE mode as well.	Gabe Black
2007-10-02	CPU: Make sure the system parameter gets set in the cpu builders. Other param...	Gabe Black
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2006-11-01	Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...	Gabe Black
2006-06-22	Changes to get OzoneCPU to compile once more.	Kevin Lim