index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
simple
Age
Commit message (
Expand
)
Author
2017-12-05
cpu: Add support for CMOs in the cpu models
Nikos Nikoleris
2017-12-04
misc: Rename misc.(hh|cc) to logging.(hh|cc)
Gabe Black
2017-11-21
cpu, cpu, sim: move Cycle probe update
Jose Marinho
2017-11-20
pwr: Adds logic to enter power gating for the cpu model
Anouk Van Laer
2017-07-12
cpu: Refactor some Event subclasses to lambdas
Sean Wilson
2017-07-05
arch: ISA parser additions of vector registers
Rekai Gonzalez-Alberquilla
2017-07-05
cpu: Added interface for vector reg file
Rekai Gonzalez-Alberquilla
2017-07-05
cpu: Simplify the rename interface and use RegId
Rekai Gonzalez-Alberquilla
2017-07-05
arch, cpu: Architectural Register structural indexing
Nathanael Premillieu
2017-06-20
cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper
Sean Wilson
2015-07-20
syscall_emul: [patch 13/22] add system call retry capability
Brandon Potter
2016-11-09
style: [patch 1/22] use /r/3648/ to reorganize includes
Brandon Potter
2016-08-15
cpu, arch: fix the type used for the request flags
Nikos Nikoleris
2016-06-06
pwr: Low-power idle power state for idle CPUs
David Guillen Fandos
2016-04-07
mem: Remove threadId from memory request class
Mitch Hayenga
2016-04-06
Revert power patch sets with unexpected interactions
Andreas Sandberg
2016-04-05
mem: Remove threadId from memory request class
Mitch Hayenga
2014-12-09
power: Low-power idle power state for idle CPUs
Akash Bagdia
2015-11-27
base: Add support for changing output directories
Andreas Sandberg
2015-07-19
cpu: Fix LLSC atomic CPU wakeup
Krishnendra Nathella
2016-02-10
mem: Deduce if cache should forward snoops
Andreas Hansson
2016-02-06
style: fix missing spaces in control statements
Steve Reinhardt
2016-02-06
style: remove trailing whitespace
Steve Reinhardt
2016-01-17
cpu. arch: add initiateMemRead() to ExecContext interface
Steve Reinhardt
2015-10-12
misc: Add explicit overrides and fix other clang >= 3.5 issues
Andreas Hansson
2015-10-12
misc: Remove redundant compiler-specific defines
Andreas Hansson
2015-09-30
cpu,isa,mem: Add per-thread wakeup logic
Mitch Hayenga
2015-09-30
isa,cpu: Add support for FS SMT Interrupts
Mitch Hayenga
2015-09-30
cpu: Add per-thread monitors
Mitch Hayenga
2015-09-30
config,cpu: Add SMT support to Atomic and Timing CPUs
Mitch Hayenga
2015-07-28
revert 5af8f40d8f2c
Nilay Vaish
2015-07-26
cpu: implements vector registers
Nilay Vaish
2015-07-07
sim: Refactor and simplify the drain API
Andreas Sandberg
2015-07-07
sim: Refactor the serialization base class
Andreas Sandberg
2015-04-13
cpu: re-organizes the branch predictor structure.
Dibakar Gope
2015-04-03
cpu: fix system total instructions accounting
Nikos Nikoleris
2015-03-23
mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW
Steve Reinhardt
2015-02-11
mem: restructure Packet cmd initialization a bit more
Steve Reinhardt
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-02-16
arch: Make readMiscRegNoEffect const throughout
Andreas Hansson
2015-02-03
cpu: Ensure timing CPU sinks response before sending new request
Andreas Hansson
2015-01-25
sim: Clean up InstRecord
Ali Saidi
2015-01-25
cpu: Remove all notion that we know when the cpu is misspeculating.
Ali Saidi
2015-01-22
mem: Clean up Request initialisation
Andreas Hansson
2015-01-20
cpu: commit probe notification on every microop or macroop
Nikos Nikoleris
2014-12-05
cpu: Only check for PC events on instruction boundaries.
Gabe Black
2014-12-02
mem: Assume all dynamic packet data is array allocated
Andreas Hansson
2014-12-02
mem: Add const getters for write packet data
Andreas Hansson
2014-11-14
arm: Fixes based on UBSan and static analysis
Andreas Hansson
2014-11-12
arm: Fix timing wakeup with LLSC
Ali Saidi
[prev]
[next]