| Age | Commit message (Expand) | Author |
|---|
| 2010-06-02 | ARM: Make the predecoder handle Thumb instructions. | Gabe Black |
| 2010-03-23 | cpu: get rid of uncached access "events" | Steve Reinhardt |
| 2010-03-23 | cpu: fix exec tracing memory corruption bug | Steve Reinhardt |
| 2010-03-21 | TimingSimpleCPU: Fixed uncacacheable request read bug | Brad Beckmann |
| 2010-02-26 | cpu_models: get rid of cpu_models.py and move the stuff into SCons | Nathan Binkert |
| 2010-02-12 | BaseDynInst: Make the TLB translation timing instead of atomic. | Timothy M. Jones |
| 2009-11-18 | m5: Fixed bug in atomic cpu destructor | Brad Beckmann |
| 2009-11-10 | Mem: Eliminate the NO_FAULT request flag. | Gabe Black |
| 2009-09-23 | arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh | Nathan Binkert |
| 2009-09-22 | python: Move more code into m5.util allow SCons to use that code. | Nathan Binkert |
| 2009-08-23 | Atomic CPU: Respect the NO_ACCESS request flag. | Gabe Black |
| 2009-08-01 | Fix setting of INST_FETCH flag for O3 CPU. | Steve Reinhardt |
| 2009-07-08 | Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. | Gabe Black |
| 2009-07-08 | Registers: Get rid of the float register width parameter. | Gabe Black |
| 2009-06-04 | types: clean up types, especially signed vs unsigned | Nathan Binkert |
| 2009-05-26 | types: add a type for thread IDs and try to use it everywhere | Nathan Binkert |
| 2009-05-17 | includes: sort includes again | Nathan Binkert |
| 2009-05-17 | types: Move stuff for global types into src/base/types.hh | Nathan Binkert |
| 2009-04-20 | request: rename INST_READ to INST_FETCH. | Steve Reinhardt |
| 2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black |
| 2009-04-19 | CPUs: Make the atomic CPU support locked memory accesses. | Gabe Black |
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black |
| 2009-04-19 | CPU: If the simple CPU is already idle, just return from suspendContext, don'... | Gabe Black |
| 2009-04-15 | Get rid of the Unallocated thread context state. | Steve Reinhardt |
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
| 2009-03-11 | cpu: fix minor endian issue with trace output | Steve Reinhardt |
| 2009-03-05 | stats: Fix all stats usages to deal with template fixes | Nathan Binkert |
| 2009-02-26 | CPA: Add code to automatically record function symbols as CPU executes. | Ali Saidi |
| 2009-02-25 | CPU: Don't fetch when executing a macroop. | Gabe Black |
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert t... | Gabe Black |
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black |
| 2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black |
| 2009-02-01 | CPU: Don't always reset the micro pc on faults. Let the faults handle it. | Gabe Black |
| 2009-02-01 | X86: Make sure the predecoder is cleared out for interrupts. | Gabe Black |
| 2009-01-24 | cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep. | Nathan Binkert |
| 2009-01-06 | Tracing: Make tracing aware of macro and micro ops. | Gabe Black |
| 2008-11-13 | CPU: Refactor read/write in the simple timing CPU. | Gabe Black |
| 2008-11-09 | CPU: Make unaligned accesses work in the timing simple CPU. | Gabe Black |
| 2008-11-09 | X86: Make the timing simple CPU handle variable length instructions. | Gabe Black |
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu |
| 2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu |
| 2008-10-27 | CPU: The API change to EventWrapper did not get propagated to the entirety o... | Clint Smullen |
| 2008-10-21 | style: Use the correct m5 style for things relating to interrupts. | Nathan Binkert |
| 2008-10-20 | O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo... | Ali Saidi |
| 2008-10-12 | CPU: Explain why some code is commented out. | Gabe Black |
| 2008-10-12 | X86: Don't fetch in the simple CPU if you're in the ROM. | Gabe Black |
| 2008-10-12 | CPU: Make the highest order bit in the micro pc determine if it's combination... | Gabe Black |
| 2008-10-12 | Turn Interrupts objects into SimObjects. Also, move local APIC state into x86... | Gabe Black |
| 2008-10-11 | CPU: Eliminate the simPalCheck funciton. | Gabe Black |
