gem5 - gem5

Age	Commit message (Expand)	Author
2009-11-18	m5: Fixed bug in atomic cpu destructor	Brad Beckmann
2009-11-10	Mem: Eliminate the NO_FAULT request flag.	Gabe Black
2009-11-04	build: fix compile problems pointed out by gcc 4.4	Nathan Binkert
2009-11-04	o3: get rid of unused physmem pointer	Steve Reinhardt
2009-10-27	POWER: Add support for the Power ISA	Timothy M. Jones
2009-10-17	ISA: Fix compilation.	Gabe Black
2009-10-15	fixed MC146818 checkpointing bug and added isa serialization calls to simple_...	Brad Beckmann
2009-10-01	inorder-debug: print out workload	Korey Sewell
2009-09-29	commit Soumyaroop's bug catch about max_insts_all_threads	Lisa Hsu
2009-09-26	O3: Add flag to control whether faulting instructions are traced.	Steve Reinhardt
2009-09-26	O3: Mark fetch stage as active if it faults.	Steve Reinhardt
2009-09-25	inorder-debug: fix cpu tick debug message	Korey Sewell
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2009-09-17	inorder-mdu: multiplier latency fix	Korey Sewell
2009-09-16	inorder-smt: remove hardcoded values	Soumyaroop Roy
2009-09-15	inorder-alpha-fs: edit inorder model to compile FS mode	Korey Sewell
2009-09-01	SCons fix to always make MemTest object	Polina Dudnik
2009-08-23	Atomic CPU: Respect the NO_ACCESS request flag.	Gabe Black
2009-08-01	Fix setting of INST_FETCH flag for O3 CPU.	Steve Reinhardt
2009-07-29	Simple CPU: Make the simple CPU handle the IntRegs trace flag.	Gabe Black
2009-07-27	ARM: Make native trace print out what instruction caused an error.	Gabe Black
2009-07-25	o3-smt: enforce numThreads parameter for SMT SE mode	Korey Sewell
2009-07-19	CPU: Separate out native trace into ISA (in)dependent code and SimObjects.	Gabe Black
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined RegFile class.	Gabe Black
2009-07-08	Registers: Move the PCs out of the ISAs and into the CPUs.	Gabe Black
2009-07-08	ARM, Simple CPU: Fix an index and add assert checks.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined integer register file.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined floating point register file.	Gabe Black
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-06-04	move: put predictor includes and cc files into the same place	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-05-12	cpus: add InOrderCPU to default build	Korey Sewell
2009-05-12	inorder-resources: delete events	Korey Sewell
2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
2009-05-12	inorder-tlb: squash insts in TLB correctly	Korey Sewell
2009-05-12	inorder-faults: ignore unalign translation faults for prefetches	Korey Sewell
2009-05-12	inorder-stc: update interface to handle store conditionals	Korey Sewell
2009-05-12	inorder-float: Fix storage of FP results	Korey Sewell
2009-05-12	inorder-fetch: update model to use predecoder	Korey Sewell
2009-05-12	inorder-mem: clean up allocation/deletion of requests/packets	Korey Sewell
2009-05-12	inorder-mem: skeleton support for prefetch/writehints	Korey Sewell
2009-05-12	inorder-o3: allow both to compile together	Korey Sewell
2009-05-12	inorder-unified-tlb: use unified TLB instead of old TLB model	Korey Sewell