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path: root/src/mem/cache/base.cc
AgeCommit message (Expand)Author
2018-06-08mem-cache: Change Cache block tag checkDaniel R. Carvalho
2018-06-08mem-cache: Use secure bit in findVictimDaniel R. Carvalho
2018-06-08mem-cache: Return evictions along with victimsDaniel R. Carvalho
2018-06-01mem-cache: Create an address aware TempCacheBlkDaniel R. Carvalho
2018-06-01mem-cache: Fix secure bit modificationDaniel R. Carvalho
2018-05-31mem-cache: Replace block visitor with std::functionNikos Nikoleris
2018-05-31mem-cache: Move cache bypass mechanism to the portsNikos Nikoleris
2018-05-31mem-cache: Adopt a more sensible cache class hierarchyNikos Nikoleris
2018-05-17mem-cache: Move replacements stat to the base cache classNikos Nikoleris
2018-03-22mem-cache: Split array indexing and replacement policies.Daniel R. Carvalho
2017-06-20mem: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-05-26mem: fix headers include order in the cache related classesNikos Nikoleris
2016-05-26mem: change NULL to nullptr in the cache related classesNikos Nikoleris
2016-05-26mem: fix the line length in the cache related classesNikos Nikoleris
2016-04-21mem: Include WriteLineReq in cache demand statsAndreas Hansson
2016-04-21mem: Remove unused cache statsAndreas Hansson
2015-05-27mem: Add unused prefetch counter in cachesRekai Gonzalez Alberquilla
2016-03-17mem: Adjust cache queue reserve to more conservative valuesAndreas Hansson
2016-03-17mem: Create a separate class for the cache write bufferAndreas Hansson
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2015-08-21mem: Add explicit Cache subclass and make BaseCache abstractAndreas Hansson
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-07-03mem: Add ReadCleanReq and ReadSharedReq packetsAndreas Hansson
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-05-05mem: Remove templates in cache modelDavid Guillen
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2014-12-23mem: Add parameter to reserve MSHR entries for demand accessMitch Hayenga
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-06-27mem: write streaming support via WriteInvalidate promotionCurtis Dunham
2014-09-03mem: Fix a bug in the cache port flow controlAndreas Hansson
2014-07-28mem: refactor LRU cache tags and add random replacement tagsAnthony Gutierrez
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Remove the cache builderAndreas Hansson
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
2013-01-07sim: Fatal if a clocked object is set to have a clock of 0Andreas Hansson
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
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