summaryrefslogtreecommitdiff
path: root/src/mem/noncoherent_bus.cc
AgeCommit message (Expand)Author
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2013-05-30mem: Make the buses multi layeredAndreas Hansson
2013-05-30mem: Tidy up a few variables in the busAndreas Hansson
2013-05-30mem: Add basic stats to the busesUri Wiener
2013-03-26mem: Separate waiting for the bus and waiting for a peerAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson