gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2013-05-30	mem: Make the buses multi layered	Andreas Hansson
2013-05-30	mem: Tidy up a few variables in the bus	Andreas Hansson
2013-05-30	mem: Add basic stats to the buses	Uri Wiener
2013-03-26	mem: Separate waiting for the bus and waiting for a peer	Andreas Hansson
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2013-02-19	mem: Make packet bus-related time accounting relative	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Bus: Split the bus into separate request/response layers	Andreas Hansson
2012-07-09	Bus: Add a notion of layers to the buses	Andreas Hansson
2012-07-09	Bus: Replace tickNextIdle and inRetry with a state variable	Andreas Hansson
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson