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path: root/src/python/m5/SimObject.py
AgeCommit message (Expand)Author
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
2018-01-29arm: DT autogeneration - Device Tree generation methodsGlenn Bergmans
2017-09-26sim: Don't add the NULL SimObject as a child of other SimObjects.Gabe Black
2017-05-22python: Prevent Python wrappers from deleting SimObjectsAndreas Sandberg
2017-05-22python: Fix weird memory issue in wrapped AddrRange vectorsAndreas Sandberg
2017-05-15style: fix line lengths and include orderingBrandon Potter
2017-05-02python: Remove SWIGAndreas Sandberg
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2017-01-27python: Move native wrappers to the _m5 namespaceAndreas Sandberg
2017-01-03sim: Remove redundant export_method_cxx_predeclsAndreas Sandberg
2015-12-01config: Fix broken SimObject listingAndreas Sandberg
2015-07-07sim: Move mem(Writeback|Invalidate) to SimObjectAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2014-12-02scons: Ensure dictionary iteration is sorted by keyAndreas Hansson
2014-11-12sim: Sort SimObject descendants and portsAndreas Hansson
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-09-20config: Cleanup .json config file generationAndrew Bardsley
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
2014-05-09config: Avoid generating a reference to myself for Parent.anyGeoffrey Blake
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-03python: provide better error message for wrapped C++ methodsSteve Reinhardt
2014-01-03python: don't die on assignment to cloned objectSteve Reinhardt
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
2013-02-15base: Add warn() and inform() to m5.utils for use from pythonSascha Bischoff
2013-01-07config: Traverse lists when visiting children in all proxyAndreas Hansson
2012-11-02sim: Add SWIG interface for SerializableAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-05-23Config: Use the attribute naming and include ports in JSONAndreas Hansson
2012-05-10DOT: improved dot-based system visualizationUri Wiener
2012-05-10DOT: fixed broken code for visualizing configuration using dotUri Wiener
2012-04-05Python: Make the All proxy traverse SimObject children as wellAndreas Hansson
2012-03-21Python: Fix a conditional expression that requires Python 2.5Andreas Hansson
2012-03-19scripts: Fix to ensure that port connection count is always setAndreas Hansson
2012-02-29SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1Andreas Hansson
2012-02-20SimObject: make get_config_as_dict() tolerate undefined paramsSteve Reinhardt
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-09Config: Fix issue with JSON outputAli Saidi
2012-01-09config: support outputing a pickle of the configuration treeAli Saidi
2011-10-20SimObject: add export_method* hooks to export C++ methods to PythonSteve Reinhardt
2011-10-20scons/swig: refactor some of the scons/SWIG codeSteve Reinhardt