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AgeCommit message (Expand)Author
2011-05-23sim: add some DPRINTFs for debugging unserializationSteve Reinhardt
2011-05-04Debug: Add a function to cause the simulator to create a checkpoint from GDB.Ali Saidi
2011-05-04Core: Add some documentation about the sim clocks.Ali Saidi
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-15python: cleanup python code so stuff doesn't automatically happen at startupNathan Binkert
2011-04-15scons: make a flexible system for guarding source filesNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15debug: create a Debug namespaceNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-03-29sim: typecast Tick to UTick for eventQ assertKorey Sewell
2011-03-17ARM: Add minimal ARM_SE support for m5threads.Chris Emmons
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2011-02-11Serialization: Allow serialization of stl listsAli Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-11Timesync: Make sure timesync event is setup after curTick is unserializedAli Saidi
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-02-03Fault: Forgot to refresh to grab these header guard updates.Gabe Black
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2011-01-31Fault: Move the definition of NoFault from faults.hh to fault.hh.Gabe Black
2011-01-20checkpointing: fix bug from curTick accessor conversion.Steve Reinhardt
2011-01-19TimeSync: Use the new setTick and getTick functions.Gabe Black
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
2011-01-15time: improve time datastructureNathan Binkert
2011-01-10Root: Get rid of unnecessary includes in root.cc.Gabe Black
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2011-01-07stats: rename StatEvent() function to schedStatEvent().Steve Reinhardt
2011-01-07sim: clean up CountedDrainEvent slightly.Steve Reinhardt
2011-01-07sim: delete unused CheckSwapEvent code.Steve Reinhardt
2011-01-07pseudoinst: get rid of mainEventQueue references.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-11-19SE: Fix simulating more than 4GB of RAM in SE modeAli Saidi
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-11-08sim: Use forward declarations for ports.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-15GetArgument: Rework getArgument so that X86_FS compiles again.Gabe Black
2010-10-01Debug: Implement getArgument() and function skipping for ARM.Ali Saidi
2010-09-14CPU: Trim unnecessary includes from some common files.Gabe Black
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-09-09init: don't build files that centralize python and swig codeNathan Binkert
2010-09-09scons: use code_formatter wherever we can in the build systemNathan Binkert
2010-08-25Tracing: Fix trace so 'Predicated False' doesn't show upAli Saidi
2010-08-23Faults: Get rid of some commented out code in sim/faults.hh.Gabe Black
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory instru...Min Kyu Jeong
2010-08-23Loader: Make the load address mask be a parameter of the system rather than a...Ali Saidi
2010-08-23Compiler: Fixes for GCC 4.5.Ali Saidi
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
2010-08-17sim: revamp unserialization procedureSteve Reinhardt