Age | Commit message (Expand) | Author |
2020-01-22 | fastmodel: Implement CC reg accessors. | Gabe Black |
2020-01-22 | arm: Remove checkpointing from the ARM TLBs. | Gabe Black |
2020-01-22 | arch: Get rid of the unused (and mostly undefined) zeroRegisters. | Gabe Black |
2020-01-21 | dev-arm: add FixedClock SimObject | Adrian Herrera |
2020-01-21 | mem-cache: Fix invalidation of prefetchers | Daniel R. Carvalho |
2020-01-20 | arch-arm: Fix EL2 target exception level for SP alignment fault. | Jordi Vaquero |
2020-01-17 | mem-cache: Add print function to ReplaceableEntry | Daniel R. Carvalho |
2020-01-17 | mem-cache: Add getter for the number of valid sub-blks | Daniel R. Carvalho |
2020-01-17 | mem-cache: Add multiple eviction stats | Daniel R. Carvalho |
2020-01-17 | mem-cache: Make findVictim non-const | Daniel R. Carvalho |
2020-01-17 | mem-cache: Add more compression stats | Daniel R. Carvalho |
2020-01-17 | mem-cache: Factor out multiple block eviction | Daniel R. Carvalho |
2020-01-15 | arch-arm: ELIsInHost, check VHE and SecEL2 | Adrian Herrera |
2020-01-15 | arch-arm: Virtualization Host Extensions checking | Adrian Herrera |
2020-01-14 | mem-garnet: Use smart pointers for CrossbarSwitch's members | Daniel R. Carvalho |
2020-01-14 | x86: Stop clearing RAX for BIST in initCPU. | Gabe Black |
2020-01-14 | x86: Move local APIC initialization out of initCPU. | Gabe Black |
2020-01-14 | x86: Move miscreg initialization to the ISA class. | Gabe Black |
2020-01-13 | sim: Add a dumpSimcall mechanism to GuestABI. | Gabe Black |
2020-01-13 | sim: Add a unit test for the GuestABI mechanism. | Gabe Black |
2020-01-13 | sim: Implement a varargs like mechanism for GuestABI system. | Gabe Black |
2020-01-13 | systemc: keep SC_CONCAT* macro | Earl Ou |
2020-01-11 | arch: Make the generic micropc enabled PCState set nupc to 1. | Gabe Black |
2020-01-10 | dev-arm: VExpress_GEM5_Base, fix daughterboard reference | Adrian Herrera |
2020-01-09 | tests,base: Added GTest for base/socket.cc | Bobby R. Bruce |
2020-01-09 | tests: Updated gtest/logging.cc to print log rather than fail. | Bobby R. Bruce |
2020-01-09 | base: Include some required headers in amo.hh. | Gabe Black |
2020-01-09 | base, gpu-compute: Move gpu AMOs into the generic header | Giacomo Travaglini |
2020-01-08 | arch, base: Move arm AtomicOpFunctor into the generic header | Giacomo Travaglini |
2020-01-08 | base: Move AtomicOpFunctors to a dedicated header | Giacomo Travaglini |
2020-01-07 | arch,sim: Promote the m5ops_base param to the System base class. | Gabe Black |
2020-01-07 | cpu: Disable O3CPU value forwarding with write strobes | Gabor Dozsa |
2020-01-07 | cpu: Use enums for O3CPU store value forwarding | Gabor Dozsa |
2020-01-07 | misc: Reflect changes of arm bootloader name | Adrian Herrera |
2020-01-07 | mem-cache: Forward snoops when the cache is not responding | Nikos Nikoleris |
2020-01-07 | mem-cache: Ensure that responses get data from the right source | Nikos Nikoleris |
2020-01-07 | systemc: fix gem5_to_tlm bridge | Earl Ou |
2020-01-07 | fastmodel: Implement the vecPredReg accessor functions. | Gabe Black |
2020-01-07 | arch,sim: Stop decoding the pseudo inst subfunc value. | Gabe Black |
2020-01-06 | arch,sim: Use the guest ABI mechanism with pseudo instructions. | Gabe Black |
2020-01-06 | arch-arm: Semihosting, specify files root dir | Adrian Herrera |
2020-01-06 | dev-arm: Fix SMMUv3 walkMasks in page table ops | Michiel van Tol |
2020-01-06 | dev-arm: Fix SMMUv3 16KB next-level table address masking | Giacomo Travaglini |
2020-01-06 | dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour | Adrian Herrera |
2020-01-06 | mem-cache: Avoid write merging if there are reads in between | Nikos Nikoleris |
2020-01-03 | sim: Move destructor of Port to public | Yu-hsin Wang |
2020-01-03 | cpu: Fix issue with MinorCPU predicated-false mem. accesses | Giacomo Gabrielli |
2020-01-03 | cpu: Disable MinorCPU value forwarding with write strobes | Gabor Dozsa |
2019-12-30 | fastmodel: Fix compilation errors | Chun-Chen TK Hsu |
2019-12-27 | fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC. | Gabe Black |