gem5 - gem5

Age	Commit message (Expand)	Author
2019-03-19	python: Switch to the new getPort mechanism to connect ports.	Gabe Black
2019-03-19	mem: Move bind() and unbind() into the Port class.	Gabe Black
2019-03-19	sim: Add a getPort function to SimObject.	Gabe Black
2019-03-18	python: Change \|\| to && for MessageBuffers in connectPorts.	Gabe Black
2019-03-18	python: Improve how templated SimObject classes are handled.	Gabe Black
2019-03-18	scons: fix disable_partial logic for fast binary	Hoa Nguyen
2019-03-18	mem-cache: tautological comparison of byteOrder	Andrea Mondelli
2019-03-15	mem: Removed circular include ref	Ryan Gambord
2019-03-15	mem-cache: Added the Indirect Memory Prefetcher	Javier Bueno
2019-03-15	mem: Move the Port base class into sim.	Gabe Black
2019-03-15	dev: Make EtherInt inherit from Port.	Gabe Black
2019-03-15	mem: Track the MemObject owner in MasterPort and SlavePort.	Gabe Black
2019-03-15	python: Simplify connectPorts() around EtherObject/EtherDevice.	Gabe Black
2019-03-15	dev: Make the EtherDevice class inherit EtherObject.	Gabe Black
2019-03-15	dev: Turn EtherObject into an interface class.	Gabe Black
2019-03-15	mem-cache: Fix write hit latency calculation order	Daniel
2019-03-14	python: Teach cxxMethod how to set return_value_policy.	Gabe Black
2019-03-14	python: Teach PyBindMethod how to set return_value_policy.	Gabe Black
2019-03-14	cpu: Refactor of Physical Register implementation	Andrea Mondelli
2019-03-14	python: Fix unknown params and proxy multiplication	Daniel R. Carvalho
2019-03-14	dev-arm: cleanup of gicv3 CPU interface code and fixes	Jairo Balart
2019-03-14	arch-arm,cpu: Add initial support for Arm SVE	Giacomo Gabrielli
2019-03-12	sim: Add size to array unserialization error message	Daniel R. Carvalho
2019-03-12	dev-arm: cleanup of gicv3 code	Jairo Balart
2019-03-12	mem-cache: Removed default arg from get() in prefetch/base.hh	Ryan Gambord
2019-03-11	arch-hsail: changed gen.py shebang from python(3) to python2.7	Ryan Gambord
2019-03-11	arch-arm: Fixing implicit fallthrough build errors	Ryan Gambord
2019-03-11	mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"	Daniel R. Carvalho
2019-03-10	mem-cache: Added extra information to PrefetchInfo	Javier Bueno
2019-03-07	mem-cache: Add header delay to handleFill whenReady	Daniel R. Carvalho
2019-03-07	mem-cache: Allow tag-only accesses on latency calculation	Daniel R. Carvalho
2019-03-07	mem-cache: Add lookup latency to access' whenReady	Daniel R. Carvalho
2019-03-07	mem-cache: Fix recvTimingReq doWritebacks tick	Daniel R. Carvalho
2019-03-07	mem-cache: Use header delay on latency calculation	Daniel R. Carvalho
2019-03-07	mem-cache: Remove old todo about latency in hit function	Daniel R. Carvalho
2019-03-01	tlm: Add some includes to some tlm_utils header files.	Gabe Black
2019-03-01	python: Fix issue when Self proxy resolves to a another proxy	Andreas Sandberg
2019-03-01	mem-cache: alias to mem::getMasterPort in TLB class	Andrea Mondelli
2019-03-01	dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads	Giacomo Travaglini
2019-03-01	dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on reads	Giacomo Travaglini
2019-03-01	arch-arm: implement floating point aarch32 VCVTA family	Ciro Santilli
2019-02-28	systemc: Move systemc disabling checks to SConsopts.	Gabe Black
2019-02-28	ruby: Fix garnet's round robin arbitration for vc selection	Srikant Bharadwaj
2019-02-28	mem-cache: Sandbox Based Optimal Offset Implementation	Ivan Pizarro
2019-02-27	misc: Segmentation Fault during O3PipeView execution	Andrea Mondelli
2019-02-26	cpu: Fix indirect branch history updates	Srikant Bharadwaj
2019-02-26	mem-cache: Copy over flags to forwarded response	Nikos Nikoleris
2019-02-26	scons: Marshal Python sources using the same Python as gem5	Andreas Sandberg
2019-02-25	systemc: Remove _m5.systemc passthroughs from SystemC_Kernel.	Gabe Black
2019-02-25	systemc: Get rid of --working-dir in the test's config.py.	Gabe Black