gem5 - gem5

Age	Commit message (Expand)	Author
2019-12-10	arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs	Giacomo Travaglini
2019-12-09	mem: Add Request::isMasked to check for byte strobing	Giacomo Travaglini
2019-12-09	mem: Add byteEnable copy to Request copy constructor	Giacomo Travaglini
2019-12-08	arch-riscv: set MaxMiscDestRegs to 2	Alec Roelke
2019-12-07	scons: Set the partial linking group for EXTRAS dirs.	Gabe Black
2019-12-06	kvm,arm: Update the KVM ARM v8 CPU to use vector regs.	Gabe Black
2019-12-05	arch-x86: missing override specifier	Andrea Mondelli
2019-12-05	arch-x86: Adding LDDQU instruction	marjanfariborz
2019-12-04	sim: Add a suppression mechanism to the SyscallReturn class.	Gabe Black
2019-12-04	sim: Small style fixes in sim/syscall_return.hh.	Gabe Black
2019-12-04	sim: Change the syscall executor to a std::function.	Gabe Black
2019-12-04	sparc: Fix the getresuidFunc prototype.	Gabe Black
2019-12-04	sparc: Fix the predecoder's moreBytes method.	Gabe Black
2019-12-03	systemc: Purposefully expose bind in the initiator socket.	Gabe Black
2019-12-03	fastmodel: Switch the diagnostic pragmas to GCC from clang.	Gabe Black
2019-12-03	cpu,sim-se: move error checks in syscall methods	Brandon Potter
2019-12-03	systemc,fastmodel: Use the gem5_scons error and warning functions.	Gabe Black
2019-12-03	systemc: Suppress a spurious clang warning in the systemc headers.	Gabe Black
2019-12-03	systemc: Fix up some lingering Accellera specific code in TLM v1.	Gabe Black
2019-12-03	base: add the FmtStackTrace debug option	Ciro Santilli
2019-12-03	sim-se: Avoid function overloading for syscall implementation	Giacomo Travaglini
2019-12-03	systemc: Add a bunch of missing overrides to the systemc headers.	Gabe Black
2019-12-03	fastmodel: Suppress a spurious warning on clang for amba_pv.h.	Gabe Black
2019-12-01	arch-riscv: Fix disassembling of immediate for c.lui instruction	Ian Jiang
2019-11-28	dev-arm: Automatically assign PCI device ids in attachPciDevice	Ciro Santilli
2019-11-28	dev-arm: device name in AmbaFake accesses	Adrian Herrera
2019-11-28	mem-cache: Avoid hiding a virtual method in the dictionary compressor.	Gabe Black
2019-11-28	mem-cache: Remove a std::move clang says is unnecessary.	Gabe Black
2019-11-28	arm: Make sure not to shift off of the end of a uint32_t in KVM.	Gabe Black
2019-11-27	base, python: Allow dirname selection for the interpreter	Giacomo Travaglini
2019-11-27	base: Fix DPRINTF_UNCONDITIONAL on gem5.fast	Giacomo Travaglini
2019-11-27	sim-se: Check Path redirection when mmapping	Giacomo Travaglini
2019-11-26	sim: prefix --debug-flags Event logs with the flag name	Ciro Santilli
2019-11-26	cpu: prefix ExecEnable to the native trace to match DPRINTF	Ciro Santilli
2019-11-26	base: generalize ExecTicks to all messages with FmtTicksOff	Ciro Santilli
2019-11-26	base: create DPRINTF_UNCONDITIONAL	Ciro Santilli
2019-11-26	base: add the --debug-flag to DPRINTF output with FmtFlag	Ciro Santilli
2019-11-26	arch-arm: Make the Tarmac parsed registers case insensitive	Giacomo Travaglini
2019-11-26	arch-riscv: Fix immediate decoding for integer shift immediate instructions	Ian Jiang
2019-11-26	arch-riscv: Fix disassembling for fence and fence.i	Ian Jiang
2019-11-26	arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.	Gabe Black
2019-11-25	arm: Stop serializing ISA values wihch are cached from the system.	Gabe Black
2019-11-25	arch-arm: default MIDR for Armv8 ISA processors	Adrian Herrera
2019-11-25	dev-arm: Adjust off_chip ranges in VExpress_GEM5 platform	Giacomo Travaglini
2019-11-25	cpu: log thread activate and suspend with --debug-flags Thread	Ciro Santilli
2019-11-25	sim-se: don't wake up threads that are halted on futex	Ciro Santilli
2019-11-25	arch-riscv: Fix disassembling for atomic instructions	Ian Jiang
2019-11-25	arch-riscv: Fix disassembling of operand list for compressed instructions	Ian Jiang
2019-11-25	arch-riscv: Fix disassembling of immediate for U-type instructions	Ian Jiang
2019-11-22	arch-riscv: Fix bug in serialize and unserialize of Interrutps	IanJiangICT