gem5 - gem5

Age	Commit message (Expand)	Author
2019-08-27	sim: Add a takeOverFrom method to the base Port class.	Gabe Black
2019-08-27	mem, sim, systemc: Reorganize Port and co.s bind, unbind slightly.	Gabe Black
2019-08-26	dev-arm: Fix GICv3 ITS indexing error	Giacomo Travaglini
2019-08-26	dev-arm: Fix GITS_BASER initialization/access	Giacomo Travaglini
2019-08-23	arch-riscv: fix GDB register cache	Alec Roelke
2019-08-23	mem: Put gem5 protocols in their own directory.	Gabe Black
2019-08-23	mem: Move ruby protocols into a directory called ruby_protocol.	Gabe Black
2019-08-23	mem: Split the various protocols out of the gem5 master/slave ports.	Gabe Black
2019-08-22	mem-ruby: fix build with PROTOCOL=MOESI_hammer	Ciro Santilli
2019-08-22	dev-arm: Start using GITS_CTLR.quiescent bit	Giacomo Travaglini
2019-08-22	dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)	Giacomo Travaglini
2019-08-22	dev-arm,system-arm: missing GICv3 ranges property	Adrian Herrera
2019-08-21	arch-riscv: Update register file	Yifei Liu
2019-08-21	arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0	Ciro Santilli
2019-08-21	base: assert that stats bucket size is greater than 0	Ciro Santilli
2019-08-21	arch-arm: Fix implicit fallthrough build errors	Chun-Chen TK Hsu
2019-08-20	dev-arm: Add redistributor-stride property to GICv3	Giacomo Travaglini
2019-08-20	arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL	Giacomo Travaglini
2019-08-20	arch-arm: Replace direct use cpsr.el with currEL helper	Giacomo Travaglini
2019-08-20	arch-arm: Overload currEL helper with CPSR argument	Giacomo Travaglini
2019-08-20	arch-arm: Rewrite the currEL helper method to use opModeToEL	Giacomo Travaglini
2019-08-20	dev-arm: Add GITS_PIDR2 register to the ITS memory map	Giacomo Travaglini
2019-08-20	dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRx	Giacomo Travaglini
2019-08-19	mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescer	Pablo Prieto
2019-08-16	x86: Stop CPUID from claiming we support xsave.	Gabe Black
2019-08-15	x86: Make unsuccessful CPUID instructions zero the result.	Gabe Black
2019-08-13	sim: Add a hook Clocked objects can implement for frequency changes.	Gabe Black
2019-08-13	sim: Clean up some mild style bugs in clocked_object.hh.	Gabe Black
2019-08-13	mem-ruby: Use check_on_cache_probe on MI	Pouya Fotouhi
2019-08-13	mem-ruby: Use check_on_cache_probe on MOESI hammer	Pouya Fotouhi
2019-08-13	mem-ruby: Use check_on_cache_probe on MOESI CMP	Pouya Fotouhi
2019-08-13	mem-ruby: Use check_on_cache_probe on MOESI	Pouya Fotouhi
2019-08-12	arch-arm: Added LD/ST<op> atomic instruction family and SWP instrs	Jordi Vaquero
2019-08-12	mem-ruby: Use check_on_cache_probe to protect locked lines from eviction	Pouya Fotouhi
2019-08-12	mem-ruby: Use check_on_cache_probe to protect locked lines from eviction	Pouya Fotouhi
2019-08-12	dev-arm: Enable DTB autogeneration in GICv3	Giacomo Travaglini
2019-08-12	dev-arm: Fix PCI node's interrupt-map property	Giacomo Travaglini
2019-08-12	dev-arm: Use FdtState to generate GIC properites	Giacomo Travaglini
2019-08-12	python: FdtState using interrupt-cells	Giacomo Travaglini
2019-08-12	arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func	Jordi Vaquero
2019-08-12	sim-se: rename Process::setpgid member	Brandon Potter
2019-08-10	cpu: Pull more arch specialization to the top of BaseCPU.py.	Gabe Black
2019-08-10	x86: Move some fixed or dummy config information into X86LocalApic.py.	Gabe Black
2019-08-09	arch: Bump MaxVecRegLenInBytes to 4096	Tony Gutierrez
2019-08-09	sim-se: minor refactor for ProcessParams::create	Brandon Potter
2019-08-09	sim-se: remove unused parameter	Brandon Potter
2019-08-07	cpu-o3: fix atomic instructions non-speculative	Jordi Vaquero
2019-08-07	cpu-o3: added _amo_op parameter in o3 LSQ	Jordi Vaquero
2019-08-07	arch-arm: Add TypeAtomicOp class to be used by new atomic instructions	Jordi Vaquero
2019-08-07	arch-arm: adding register control flags enabling LSE implementation	Jordi Vaquero