gem5 - gem5

Age	Commit message (Expand)	Author
2019-10-03	dev, misc: Fixing "may be used unitialized" compilation error	Bobby R. Bruce
2019-10-03	sim-se: Fix invalid delete of params on clone	Jason Lowe-Power
2019-10-03	arch-arm: Annotate CM flag in AA64 CM Instructions	Giacomo Travaglini
2019-10-03	arch-arm: Set CM bit in DataAbort	Giacomo Travaglini
2019-10-02	sim: Mark System::getThreadContext method as const	Giacomo Travaglini
2019-10-02	dev-arm: Improve fault message on SMMUv3 translation fault	Marc Mari Barcelo
2019-10-02	dev-arm: Fix address used to update the SMMUv3 Walk Cache	Marc Mari Barcelo
2019-10-02	arch-arm: Create helper for sending events (SEV)	Giacomo Travaglini
2019-10-02	fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.	Gabe Black
2019-10-02	fastmodel: Implement a custom sendFunctional for CortexA76x1.	Gabe Black
2019-10-02	x86: Switch from MessageReq and Resp to WriteReq and Resp.	Gabe Black
2019-10-02	fastmodel: Let the EVS set an attribute for getSendFunctional to return.	Gabe Black
2019-10-01	fastmodel: Add a gem5Cpu attribute to the CortexA76x1.	Gabe Black
2019-10-01	fastmodel: Add a utility class which makes it easier to watch signals.	Gabe Black
2019-10-01	fastmodel: Pull out and simplify the interrupt mechanism in the GIC.	Gabe Black
2019-10-01	mem-cache: Fix invalid whenReady	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove inexistent functions from Util	Daniel R. Carvalho
2019-09-30	mem-ruby: Make bitSelect use bits<Addr>	Daniel R. Carvalho
2019-09-30	mem-ruby: Fix maskLowOrderBits	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove shiftLowOrderBits	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove maskHighOrderBits	Daniel R. Carvalho
2019-09-30	mem-ruby: Remove bitRemove	Daniel R. Carvalho
2019-09-30	cpu: Make use of DRAMCtrl::AddrMap in the traffic generators	Nikos Nikoleris
2019-09-30	misc: Added line wrapping functionality for Sim-Object desc	Bobby R. Bruce
2019-09-30	mem: Use new-style stats in the XBar models	Andreas Sandberg
2019-09-30	mem-cache: Switch to new-style stats	Andreas Sandberg
2019-09-30	mem: Convert DRAM controller to new-style stats	Andreas Sandberg
2019-09-28	ruby: 2x protocols has typo/syntax error that fails building	Timothy Hayes
2019-09-27	fastmodel: Add glue code which adapts fastmodels to run in gem5.	Gabe Black
2019-09-26	sim: Convert power modelling framework to new-style stats	Andreas Sandberg
2019-09-26	stats: Add a preDumpStats() callback to Stats::Group	Andreas Sandberg
2019-09-26	stats: Don't output index in vectors of length 1	Andreas Sandberg
2019-09-26	stats: Correctly print new-style dist stat names	Andreas Sandberg
2019-09-25	mem-ruby: prevent cacheProbe being called multiple times	Jing Qu
2019-09-24	cpu: Fix checker cpu instantiation	Nikos Nikoleris
2019-09-23	cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>	Jordi Vaquero
2019-09-21	mem: Delete the now unused Message*Port classes.	Gabe Black
2019-09-21	x86: Templatize the IntMasterPort.	Gabe Black
2019-09-21	x86: Templatize IntSlavePort.	Gabe Black
2019-09-21	x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.	Gabe Black
2019-09-20	gpu-compute: Fix overriden errors	Jing Qu
2019-09-20	dev, x86: Delete the now unused X86 specific interrupt pins/lines.	Gabe Black
2019-09-20	dev, x86: Convert x86 devices to the generic int pins.	Gabe Black
2019-09-20	arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts	Pouya Fotouhi
2019-09-19	dev: Terminal output's dump name conflicts	Andrea Mondelli
2019-09-19	arch-x86: Change warn to warn_once for NT instructions	Hoa Nguyen
2019-09-19	python: Don't try to bind a stat group to the NULL simobject.	Gabe Black
2019-09-19	dev-arm: Conditionally enable HDLcd when doing DTB autogen	Giacomo Travaglini
2019-09-19	dev-arm: Add HDLcd DTB autogeneration	Giacomo Travaglini
2019-09-19	arch-arm: PSTATE.PAN changes should inval cached regs in TLB	Giacomo Travaglini