gem5 - gem5

Age	Commit message (Expand)	Author
2019-12-21	base: Fix negative op-assign of SatCounter	Daniel R. Carvalho
2019-12-20	configs: arm realview(64) regressions using VExpress_GEM5_V1	Giacomo Travaglini
2019-12-20	systemc: Fix tlm2 socket integration	Jui-min Lee
2019-12-20	arch-arm: Fix clang warnings	Jui-min Lee
2019-12-19	arch-arm: Fix decoding of LDFF1x scalar plus scalar	Adrià Armejach
2019-12-18	arch-arm: Semihosting, fix SYS_FLEN	Adrian Herrera
2019-12-18	sim: kernelExtras optional load addresses	Adrian Herrera
2019-12-18	python: fix "fatal" usage in fdthelper	Adrian Herrera
2019-12-18	arch-arm: Secure EL2 checking	Adrian Herrera
2019-12-18	arch-arm: AArch64 trap check, arbitrary ECs/Imms	Adrian Herrera
2019-12-18	x86: Fix some bugs with KVM in SE mode on Intel machines.	Gabe Black
2019-12-17	sim: Include some required headers in the syscall debug macros header.	Gabe Black
2019-12-17	fastmodel: Tell fast model not to shutdown when time stops.	Gabe Black
2019-12-17	fastmodel: Implement port proxies.	Gabe Black
2019-12-17	fastmodel: Create a TLB model which uses IRIS to do translations.	Gabe Black
2019-12-17	fastmodel: Add an address translation mechanism to the ThreadContext.	Gabe Black
2019-12-17	base: Fix AddrRange::isSubset() check	Nikos Nikoleris
2019-12-17	scons: Added channel_addr.cc dependency to channel_addr GTest	Bobby R. Bruce
2019-12-17	fastmodel: Add a header for IRIS MSN constants.	Gabe Black
2019-12-16	sim: kernelExtras if no kernel provided	Adrian Herrera
2019-12-13	dev-virtio: VIO9P turns on diod verbose output with -d 1	Ciro Santilli
2019-12-13	dev-virtio: don't set the 9p default root	Ciro Santilli
2019-12-13	dev-virtio: use diod basename as the default 9p path	Ciro Santilli
2019-12-12	mem: Encapsulate mapping gem5 to host address space	Daniel R. Carvalho
2019-12-12	mem-cache: Move unused prefetches counter update	Daniel R. Carvalho
2019-12-12	python: Convert terminal escape sequences to strings.	Gabe Black
2019-12-11	arch-arm: Always initialize SVE memData	Giacomo Travaglini
2019-12-11	arch-arm: Avoid creating an empty byteEnable vector	Giacomo Travaglini
2019-12-11	cpu: Replace empty byteEnable check with Request::isMasked	Giacomo Travaglini
2019-12-11	cpu: Fix coding style (byteEnable->byte_enable)	Giacomo Travaglini
2019-12-11	cpu: Add byteEnable assertions to readMem and initateMemRead	Giacomo Travaglini
2019-12-10	sim,arch: Collapse the ISA specific versions of m5Syscall.	Gabe Black
2019-12-10	arch,cpu,sim: Push syscall number determination up to processes.	Gabe Black
2019-12-10	x86: Stop manually clearing RFLAGS.RF after a system call.	Gabe Black
2019-12-10	arch: Get rid of the now unused setSyscallArg.	Gabe Black
2019-12-10	arch: Stop using setSyscallArg to set argc and argv.	Gabe Black
2019-12-10	sim: Add a wrapper/subclass for SyscallDesc which uses GuestABI.	Gabe Black
2019-12-10	sim: Add a mechanism to translate ABIs to call host funcs from a TC.	Gabe Black
2019-12-10	sim: Get rid of the now unused SyscallDesc flags and methods.	Gabe Black
2019-12-10	arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.	Gabe Black
2019-12-10	sim: Reintroduce the ignoreWarnOnceFunc syscall handler.	Gabe Black
2019-12-10	sim: Make the syscalls use the SyscallReturn suppression mechanism.	Gabe Black
2019-12-10	dev-arm: GenericTimer, configurable base and low freqs	Adrian Herrera
2019-12-10	dev-arm: GenericTimer, freq as 32-bit value	Adrian Herrera
2019-12-10	arch-arm: Disambuiguate NumFloatV7ArchRegs usage	Giacomo Travaglini
2019-12-10	arch-arm: Unify VLdmStm behaviour when reg out of index	Giacomo Travaglini
2019-12-10	arch-arm: Fix NumVecV7ArchRegs value (64->16)	Giacomo Travaglini
2019-12-10	arch-arm: Reorder arch/arm/registers.hh constants	Giacomo Travaglini
2019-12-10	arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs	Giacomo Travaglini
2019-12-09	mem: Add Request::isMasked to check for byte strobing	Giacomo Travaglini