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AgeCommit message (Expand)Author
2019-05-13cpu: Make the indirect predictor into a SimObjectJairo Balart
2019-05-12mem-ruby: Replace string parameter in MultiBitSelBloomFilterDaniel R. Carvalho
2019-05-11arch-arm: Add initial support for SVE contiguous loads/storesGiacomo Gabrielli
2019-05-11cpu,mem: Add support for partial loads/stores and wide mem. accessesGiacomo Gabrielli
2019-05-11cpu: Add a memory access predicateGiacomo Gabrielli
2019-05-09mem-ruby: Fix MOESI_CMP_directory blocked line handlingTiago Muck
2019-05-08mem-cache: Remove writebacks packet listDaniel R. Carvalho
2019-05-08mem-cache: Handle data expansionDaniel R. Carvalho
2019-05-08mem-cache: Add co-allocation function to compressed tagsDaniel R. Carvalho
2019-05-08mem-cache: Add compression and decompression callsDaniel R. Carvalho
2019-05-08mem-cache: Create BDI CompressorDaniel R. Carvalho
2019-05-08mem-cache: Add compression statsDaniel R. Carvalho
2019-05-08mem-cache: Create cache compressorDaniel R. Carvalho
2019-05-08mem-cache: Add block size to findVictimDaniel R. Carvalho
2019-05-08mem-cache: Add compression data to CompressionBlkDaniel R. Carvalho
2019-05-08mem-cache: Create CacheComp debug flagDaniel R. Carvalho
2019-05-08mem-cache: Stub compression frameworkDaniel R. Carvalho
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
2019-05-06sim-se: correct statfs inclusion on !linux hostAndrea Mondelli
2019-05-04arch-riscv: Implement MHARTID CSRAlec Roelke
2019-05-03sim-se: fix a few bugs/warns from GCC 6Joe Gross
2019-05-03sim-se: add eventfd system callBrandon Potter
2019-05-03mem-cache: Mark block as dirty after a SWPrefetchEXRespNikos Nikoleris
2019-05-03arch-riscv,isa: Fix for compressed jump (c_j) immAvishai Tvila
2019-05-03dev: StreamID generation in DMA deviceGiacomo Travaglini
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
2019-04-30sparc: Move translation constants from isa_traits.hh into tlb.hh.Gabe Black
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
2019-04-30arch: Remove the mt.hh switching header.Gabe Black
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30alpha: Implement simPalCheck within the ISA description.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30sim-se: use DPRINTF_SYSCALL for ioctl/wait4Alexandru Dutu
2019-04-30sim-se: bugfix for 54c77aa055eBrandon Potter
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
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