gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-31	x86: Stop using/defining some ISA specific register types.	Gabe Black
2019-01-31	riscv: Get rid of some ISA specific register types.	Gabe Black
2019-01-31	arch: cpu: Rename FloatRegBits to FloatReg.	Gabe Black
2019-01-30	arch,cpu: Add vector predicate registers	Giacomo Gabrielli
2019-01-30	arch-arm, configs: Create single instance of DTB autogeneration	Giacomo Travaglini
2019-01-25	arch-arm: Remove floatReg operand type	Giacomo Travaglini
2019-01-25	arch-arm: Use VecElem instead of FloatReg for FP instruction	Giacomo Travaglini
2019-01-25	arch: Fix VecElem Operand generation in ISA parser	Giacomo Travaglini
2019-01-25	cpu, arch, arch-arm: Wire unused VecElem code in the O3 model	Giacomo Travaglini
2019-01-25	cpu: O3 rename using the flatIndex instead of index	Giacomo Travaglini
2019-01-25	arch-arm: Inital vector rename mode depending on A32/A64	Giacomo Travaglini
2019-01-25	cpu: Fix VecElemClass bugs in cpu models	Giacomo Travaglini
2019-01-25	cpu: Add VecElem entries in MinorCPU Scoreboard	Giacomo Travaglini
2019-01-25	arch-arm: Remove unused float operands	Giacomo Travaglini
2019-01-25	arch: Provide traceback when parsing ISA code	Giacomo Travaglini
2019-01-25	python: Always throw TypeError on slave-slave connections	Nicholas Lindsay
2019-01-24	hsail: Remove the MiscReg type.	Gabe Black
2019-01-24	base: arch: Get rid of the now unused FloatRegVal type.	Gabe Black
2019-01-24	dev-arm: fix --generate-dtb for ARM	Ciro Santilli
2019-01-24	cpu-o3: O3 LSQ Generalisation	Rekai Gonzalez-Alberquilla
2019-01-23	arch-arm: Implement LoadAcquire/StoreRelease in AArch32	Giacomo Travaglini
2019-01-23	arch-arm: IsStoreConditional flag set depending on flavor	Giacomo Travaglini
2019-01-23	arch-arm: Remove SWP and SWPB instructions	Giacomo Travaglini
2019-01-23	systemc: Fix TLM related includes.	Gabe Black
2019-01-23	arm: Replace MiscReg with RegVal in utility.(hh\|cc).	Gabe Black
2019-01-23	mem-ruby: Fix missing TBE allocation and deallocation	Zicong Wang
2019-01-22	sparc: Get rid of some register type definitions.	Gabe Black
2019-01-22	arch: cpu: Stop passing around misc registers by reference.	Gabe Black
2019-01-22	arm: Get rid of some register type definitions.	Gabe Black
2019-01-22	arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.	Gabe Black
2019-01-22	arch-arm: implement the GDB XML target description for ARM	Ciro Santilli
2019-01-22	scons: add helpers to access GDB XML description files	Ciro Santilli
2019-01-22	scons: allow embedding arbitrary blobs into the gem5 executable	Ciro Santilli
2019-01-22	base: add support for GDB's XML architecture definition	Ciro Santilli
2019-01-22	arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers	Giacomo Travaglini
2019-01-22	mem: Add tryTiming suppport to CommMonitor	Sascha Bischoff
2019-01-22	sim-se add readv and modifies writev	Brandon Potter
2019-01-22	sim-se: add ability to get/set sock metadata	Brandon Potter
2019-01-22	sim-se: add syscalls related to polling	Brandon Potter
2019-01-22	sim-se: add calls for network transmissions	Brandon Potter
2019-01-22	sim-se: add socket-based functionality	Brandon Potter
2019-01-18	base: Fix unitialized storage	Daniel R. Carvalho
2019-01-17	mem: Allow inserts in the begining of a packet queue	Nikos Nikoleris
2019-01-17	mem: Determine if a packet queue forces ordering at construction	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtROBPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtIQPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	python: Add support for scoped enums	Nikos Nikoleris