Age | Commit message (Expand) | Author |
2019-10-23 | cpu: Apply the ARM TLB rework to the O3 checker CPU. | Gabe Black |
2019-10-23 | arch: Drop sysctl support if built against glibc | Tommaso Marinelli |
2019-10-22 | configs: Clean setupBootLoader signature | Giacomo Travaglini |
2019-10-22 | dev-arm, configs: Using _on_chip_memory for on chip memory | Giacomo Travaglini |
2019-10-21 | cpu: Apply the ARM TLB rework to the checker CPU. | Gabe Black |
2019-10-19 | cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs. | Gabe Black |
2019-10-19 | arch: Remove the "interrupts.hh" switching header file. | Gabe Black |
2019-10-19 | arch: Make a base class for Interrupts. | Gabe Black |
2019-10-18 | dev-arm: Check for gem5 extensions in GicV2 | Tiago Muck |
2019-10-18 | tests: Added GTests for base/bitfield.hh | Bobby R. Bruce |
2019-10-18 | arch: Get rid of the unused GenericTLB. | Gabe Black |
2019-10-18 | cpu: Turn the stage 2 ARM MMUs from params to children. | Gabe Black |
2019-10-18 | x86: Turn the local APIC Interrupts class into a SimObject. | Gabe Black |
2019-10-18 | tests: Added GTests for base/atomicio.cc | Bobby R. Bruce |
2019-10-18 | base: Add classes that encapsulate a channel address | Andreas Sandberg |
2019-10-18 | mem: Delete the MessageReq and MessageResp memory commands. | Gabe Black |
2019-10-17 | arm: Don't force the ArmISA::TLB in vtophys.cc. | Gabe Black |
2019-10-17 | cpu: Clean up some style issues in pc_event.(hh|cc). | Gabe Black |
2019-10-17 | cpu: Get rid of load count based events. | Gabe Black |
2019-10-16 | base: Add addIntlvBits to AddrRange | Andreas Sandberg |
2019-10-16 | base: Using scoped string in DPRINTFNR | Giacomo Travaglini |
2019-10-16 | base: Fix gem5.fast compilation | Giacomo Travaglini |
2019-10-16 | arch,base,sim: Move Process loader hooks into the Process class. | Gabe Black |
2019-10-15 | x86: Use a std::function to handle MSI completion. | Gabe Black |
2019-10-15 | arch,base: Restructure the object file loaders. | Gabe Black |
2019-10-15 | cpu: Delete the unused sched_break_pc(_sys) functions. | Gabe Black |
2019-10-15 | arch-x86: Make LFENCE a serializing instruction | Isaac Richter |
2019-10-15 | dev-arm: Carve out a portion of VExpress_GEM5 for the bootloader | Giacomo Travaglini |
2019-10-15 | sim,cpu: Get rid of the unused instEventQueue. | Gabe Black |
2019-10-15 | x86: De-x86ify the IntMasterPort. | Gabe Black |
2019-10-14 | Tests: Added GTests for base/callback.cc | Bobby R. Bruce |
2019-10-14 | x86: Simplify and consolidate the code that assembles an MSI on x86. | Gabe Black |
2019-10-14 | fastmodel: Expose all CPU communication ports from the GIC. | Gabe Black |
2019-10-13 | mem-cache: set the second chance to false when inserting a block | Mingyuan |
2019-10-12 | mem-cache: Fixed a bug in MRU replacement policy | Mingyuan |
2019-10-12 | x86: Stop using and delete the x86 IntDevice class. | Gabe Black |
2019-10-12 | arch,base: Separate the idea of a memory image and object file. | Gabe Black |
2019-10-11 | mem-ruby: Allow Ruby to use all replacement policies in Classic | JingQuJQ |
2019-10-10 | arch,base: Stop loading the interpreter in ElfObject. | Gabe Black |
2019-10-10 | arch-arm: Move generateDtb to ArmSystem | Giacomo Travaglini |
2019-10-10 | dev-arm, configs: Remove RealViewPBX platform | Giacomo Travaglini |
2019-10-10 | arch, base: Stop assuming object files have three segments. | Gabe Black |
2019-10-09 | fastmodel: Export GICV3Comms directly. | Gabe Black |
2019-10-09 | tests: Migrated refcnt.cc test from src/unitttest to a gtest | Bobby R. Bruce |
2019-10-09 | arch-mips,arch-riscv,base: Get rid of the unused HexFile class. | Gabe Black |
2019-10-09 | base: Rename Section to Segment, and some of its members. | Gabe Black |
2019-10-08 | base: Get rid of the unused global pointer in object files. | Gabe Black |
2019-10-08 | base: Ensure %p format arguments are printed as pointers. | Gabe Black |
2019-10-07 | fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms. | Gabe Black |
2019-10-07 | kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR | Ciro Santilli |