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AgeCommit message (Expand)Author
2019-01-25arch: Fix VecElem Operand generation in ISA parserGiacomo Travaglini
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2019-01-25cpu: O3 rename using the flatIndex instead of indexGiacomo Travaglini
2019-01-25arch-arm: Inital vector rename mode depending on A32/A64Giacomo Travaglini
2019-01-25cpu: Fix VecElemClass bugs in cpu modelsGiacomo Travaglini
2019-01-25cpu: Add VecElem entries in MinorCPU ScoreboardGiacomo Travaglini
2019-01-25arch-arm: Remove unused float operandsGiacomo Travaglini
2019-01-25arch: Provide traceback when parsing ISA codeGiacomo Travaglini
2019-01-25python: Always throw TypeError on slave-slave connectionsNicholas Lindsay
2019-01-24hsail: Remove the MiscReg type.Gabe Black
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
2019-01-24cpu-o3: O3 LSQ GeneralisationRekai Gonzalez-Alberquilla
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
2019-01-23arch-arm: IsStoreConditional flag set depending on flavorGiacomo Travaglini
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
2019-01-23systemc: Fix TLM related includes.Gabe Black
2019-01-23arm: Replace MiscReg with RegVal in utility.(hh|cc).Gabe Black
2019-01-23mem-ruby: Fix missing TBE allocation and deallocationZicong Wang
2019-01-22sparc: Get rid of some register type definitions.Gabe Black
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-22arm: Get rid of some register type definitions.Gabe Black
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
2019-01-22arch-arm: implement the GDB XML target description for ARMCiro Santilli
2019-01-22scons: add helpers to access GDB XML description filesCiro Santilli
2019-01-22scons: allow embedding arbitrary blobs into the gem5 executableCiro Santilli
2019-01-22base: add support for GDB's XML architecture definitionCiro Santilli
2019-01-22arch-arm: Move AArch32 IMPLEMENTATION DEFINED registersGiacomo Travaglini
2019-01-22mem: Add tryTiming suppport to CommMonitorSascha Bischoff
2019-01-22sim-se add readv and modifies writevBrandon Potter
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
2019-01-22sim-se: add socket-based functionalityBrandon Potter
2019-01-18base: Fix unitialized storageDaniel R. Carvalho
2019-01-17mem: Allow inserts in the begining of a packet queueNikos Nikoleris
2019-01-17mem: Determine if a packet queue forces ordering at constructionNikos Nikoleris
2019-01-17cpu-o3: Make the smtCommitPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtROBPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtIQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtLSQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtFetchPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17python: Add support for scoped enumsNikos Nikoleris
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2019-01-16arm: Make the fp register types 64 bits.Gabe Black
2019-01-16mem-cache: Access Map Pattern Matching PrefetcherJavier Bueno
2019-01-16mem-cache: Signature Path PrefetcherJavier Bueno
2019-01-16mem-cache: allow prefetchers to emit page crossing referencesJavier Bueno
2019-01-16mem-cache: virtual address support for prefetchersJavier Bueno
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