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AgeCommit message (Expand)Author
2020-01-06arch,sim: Use the guest ABI mechanism with pseudo instructions.Gabe Black
2020-01-06arch-arm: Semihosting, specify files root dirAdrian Herrera
2020-01-06dev-arm: Fix SMMUv3 walkMasks in page table opsMichiel van Tol
2020-01-06dev-arm: Fix SMMUv3 16KB next-level table address maskingGiacomo Travaglini
2020-01-06dev-arm: GICv3, handle GICR_ICFGR0 WI behaviourAdrian Herrera
2020-01-06mem-cache: Avoid write merging if there are reads in betweenNikos Nikoleris
2020-01-03sim: Move destructor of Port to publicYu-hsin Wang
2020-01-03cpu: Fix issue with MinorCPU predicated-false mem. accessesGiacomo Gabrielli
2020-01-03cpu: Disable MinorCPU value forwarding with write strobesGabor Dozsa
2019-12-30fastmodel: Fix compilation errorsChun-Chen TK Hsu
2019-12-27fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.Gabe Black
2019-12-27fastmodel: Move the ARM IRIS threadcontext into CortexA76.Gabe Black
2019-12-27fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.Gabe Black
2019-12-27fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.Gabe Black
2019-12-27fastmodel: Handle "special" vector regs without calling into IRIS.Gabe Black
2019-12-24fastmodel: Implement readVecRegFlat for ArmThreadContext.Gabe Black
2019-12-24fastmodel: Determine what space to use for breakpoints dynamically.Gabe Black
2019-12-23fastmodel: Implement PC based events.Gabe Black
2019-12-21base: Fix negative op-assign of SatCounterDaniel R. Carvalho
2019-12-20configs: arm realview(64) regressions using VExpress_GEM5_V1Giacomo Travaglini
2019-12-20systemc: Fix tlm2 socket integrationJui-min Lee
2019-12-20arch-arm: Fix clang warningsJui-min Lee
2019-12-19arch-arm: Fix decoding of LDFF1x scalar plus scalarAdrià Armejach
2019-12-18arch-arm: Semihosting, fix SYS_FLENAdrian Herrera
2019-12-18sim: kernelExtras optional load addressesAdrian Herrera
2019-12-18python: fix "fatal" usage in fdthelperAdrian Herrera
2019-12-18arch-arm: Secure EL2 checkingAdrian Herrera
2019-12-18arch-arm: AArch64 trap check, arbitrary ECs/ImmsAdrian Herrera
2019-12-18x86: Fix some bugs with KVM in SE mode on Intel machines.Gabe Black
2019-12-17sim: Include some required headers in the syscall debug macros header.Gabe Black
2019-12-17fastmodel: Tell fast model not to shutdown when time stops.Gabe Black
2019-12-17fastmodel: Implement port proxies.Gabe Black
2019-12-17fastmodel: Create a TLB model which uses IRIS to do translations.Gabe Black
2019-12-17fastmodel: Add an address translation mechanism to the ThreadContext.Gabe Black
2019-12-17base: Fix AddrRange::isSubset() checkNikos Nikoleris
2019-12-17scons: Added channel_addr.cc dependency to channel_addr GTestBobby R. Bruce
2019-12-17fastmodel: Add a header for IRIS MSN constants.Gabe Black
2019-12-16sim: kernelExtras if no kernel providedAdrian Herrera
2019-12-13dev-virtio: VIO9P turns on diod verbose output with -d 1Ciro Santilli
2019-12-13dev-virtio: don't set the 9p default rootCiro Santilli
2019-12-13dev-virtio: use diod basename as the default 9p pathCiro Santilli
2019-12-12mem: Encapsulate mapping gem5 to host address spaceDaniel R. Carvalho
2019-12-12mem-cache: Move unused prefetches counter updateDaniel R. Carvalho
2019-12-12python: Convert terminal escape sequences to strings.Gabe Black
2019-12-11arch-arm: Always initialize SVE memDataGiacomo Travaglini
2019-12-11arch-arm: Avoid creating an empty byteEnable vectorGiacomo Travaglini
2019-12-11cpu: Replace empty byteEnable check with Request::isMaskedGiacomo Travaglini
2019-12-11cpu: Fix coding style (byteEnable->byte_enable)Giacomo Travaglini
2019-12-11cpu: Add byteEnable assertions to readMem and initateMemReadGiacomo Travaglini
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
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