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AgeCommit message (Expand)Author
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
2019-04-30sim-se: add socket ioctlsBrandon Potter
2019-04-30systemc: Add a distinct async_request_update mechanism.Gabe Black
2019-04-29cpu: Get rid of the (read|set)RegOtherThread methods.Gabe Black
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
2019-04-29cpu: Include debug flags regardless of whether the ISA is null.Gabe Black
2019-04-29sim-se: create Proc out files in out dirSteve Reinhardt
2019-04-29arch-arm: Faults DebugFlag now printing inst opcode if availableGiacomo Travaglini
2019-04-29arch-arm: Report real instruction encoding when UndefinedGiacomo Travaglini
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-27python: Get rid of the VectorPort constructor.Gabe Black
2019-04-27python: Replace the Master/Slave Ports with Request/Response ports.Gabe Black
2019-04-26arch-arm: updateMiscReg not setting isHyp in aarch64Giacomo Travaglini
2019-04-26arm: Factor some repetition out of the ProcessInfo constructor.Gabe Black
2019-04-25arm: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-25sim-se: add a faux-filesystemDavid Hashe
2019-04-25arch-arm: Remove un-needed hyp flag in TLBI operationsGiacomo Travaglini
2019-04-25arch-arm: Correct target EL field in TLBI operationsGiacomo Travaglini
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
2019-04-24cpu,mem: missing override specifierAndrea Mondelli
2019-04-24systemc: Use the new TLM socket types in the TLM bridge SimObjects.Gabe Black
2019-04-24systemc: Add Port types for initiator and target sockets.Gabe Black
2019-04-24dev: Use the new Port role mechanism to make an EtherInt Port type.Gabe Black
2019-04-24python: Generalize the Port.splice function.Gabe Black
2019-04-24python: Generalize the dot_writer to handle non Master/Slave roles.Gabe Black
2019-04-24python: Make Port roles a more generic concept.Gabe Black
2019-04-23python: fix tracing after Python 3 refactorCiro Santilli
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
2019-04-22mem-cache: Fix fix of replacement countDaniel
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
2019-04-19mem-cache: Fix increasing replacement countDaniel R. Carvalho
2019-04-19mem-cache: Remove blk_addr from Queue::trySatisfyFunctionalDaniel R. Carvalho
2019-04-19mem-cache: Add match functions to QueueEntryDaniel R. Carvalho
2019-04-19mem: Add packet matching functionsDaniel R. Carvalho
2019-04-19mem-cache: Move Target to QueueEntryDaniel R. Carvalho
2019-04-19mem-cache: Assert Entry inherits from QueueEntry in QueueDaniel R. Carvalho
2019-04-19mem: Make DRAMCtrl::decodeAddr constDaniel R. Carvalho
2019-04-19mem: Allow packet to provide its own addr rangeDaniel R. Carvalho
2019-04-16mem: missing override specifierAndrea Mondelli
2019-04-14mem: Teach SimpleMem to return a MemBackdoor when appropriate.Gabe Black
2019-04-14mem: Maintain a back door into the AbstractMem's backing store.Gabe Black
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