gem5 - gem5

Age	Commit message (Expand)	Author
2017-02-14	mem: Update DRAM configuration names	Wendy Elsasser
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-01-07	tests: Create base classes to encapsulate common test configurations	Andreas Sandberg
2012-10-26	config: Fix the cache class naming in regression scripts	Andreas Hansson
2012-10-25	config: Use shared cache config for regressions	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Regression: Use addTwoLevelCacheHierarchy in configs	Andreas Hansson
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-07-05	X86: Add a config for an FS regression on O3.	Gabe Black