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path: root/tests/configs/pc-o3-timing.py
AgeCommit message (Expand)Author
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-07-05X86: Add a config for an FS regression on O3.Gabe Black