| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-05-09 | tests: Reflect name change in DRAM tests | Andreas Hansson |
| 2013-08-19 | power: Add voltage domains to the clock domains | Akash Bagdia |
| 2013-06-27 | sim: Add the notion of clock domains to all ClockedObjects | Akash Bagdia |
| 2013-06-27 | config: Add a system clock command-line option | Akash Bagdia |
| 2013-06-27 | config: Remove redundant explicit setting of default clocks | Akash Bagdia |
| 2013-05-30 | mem: More descriptive DRAM config names | Andreas Hansson |
| 2013-01-31 | mem: Add DDR3 and LPDDR2 DRAM controller configurations | Andreas Hansson |
| 2013-01-07 | cpu: Add support for protobuf input for the trace generator | Andreas Hansson |
| 2012-09-21 | SimpleDRAM: A basic SimpleDRAM regression | Andreas Hansson |
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index : gem5 | |
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