1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
/*
* Copyright (c) 2011,2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Giacomo Gabrielli
* Giacomo Travaglini
*/
/**
* @file: This file contains the data structure used to rappresent
* Tarmac entities/informations. These data structures will
* be used and extended by either the Tarmac Parser and
* the Tarmac Tracer.
* Instruction execution is matched by Records, so that for
* every instruction executed there is a corresponding record.
* A trace is made of Records (Generated or Parsed) and a record
* is made of Entries.
*/
#ifndef __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
#define __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
#include "arch/arm/registers.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "sim/insttracer.hh"
class ThreadContext;
namespace Trace {
class TarmacBaseRecord : public InstRecord
{
public:
/** TARMAC trace record type. */
enum TarmacRecordType {
TARMAC_INST,
TARMAC_REG,
TARMAC_MEM,
TARMAC_UNSUPPORTED,
};
/** ARM instruction set state. */
enum ISetState { ISET_ARM, ISET_THUMB, ISET_A64,
ISET_UNSUPPORTED };
/** ARM register type. */
enum RegType { REG_R, REG_X, REG_S, REG_D, REG_Q, REG_MISC };
/** TARMAC instruction trace record. */
struct InstEntry
{
InstEntry() = default;
InstEntry(ThreadContext* thread,
TheISA::PCState pc,
const StaticInstPtr staticInst,
bool predicate);
bool taken;
Addr addr;
ArmISA::MachInst opcode;
std::string disassemble;
ISetState isetstate;
ArmISA::OperatingMode mode;
};
/** TARMAC register trace record. */
struct RegEntry
{
RegEntry() = default;
RegEntry(TheISA::PCState pc);
RegType type;
RegIndex index;
ISetState isetstate;
uint64_t valueHi;
uint64_t valueLo;
};
/** TARMAC memory access trace record (stores only). */
struct MemEntry
{
MemEntry() = default;
MemEntry(uint8_t _size, Addr _addr, uint64_t _data);
uint8_t size;
Addr addr;
uint64_t data;
};
public:
TarmacBaseRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
const StaticInstPtr _macroStaticInst = NULL);
virtual void dump() = 0;
/**
* Returns the Instruction Set State according to the current
* PCState.
*
* @param pc program counter (PCState) variable
* @return Instruction Set State for the given PCState
*/
static ISetState pcToISetState(TheISA::PCState pc);
};
} // namespace Trace
#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
|
