diff options
Diffstat (limited to 'Compute-Class-Methods')
| -rw-r--r-- | Compute-Class-Methods/cl50c0.h | 741 | ||||
| -rw-r--r-- | Compute-Class-Methods/cl85c0.h | 747 | ||||
| -rw-r--r-- | Compute-Class-Methods/cl90c0.h | 1033 | ||||
| -rw-r--r-- | Compute-Class-Methods/cl91c0.h | 1049 | ||||
| -rw-r--r-- | Compute-Class-Methods/cla0c0.h | 836 | ||||
| -rw-r--r-- | Compute-Class-Methods/cla1c0.h | 866 | ||||
| -rw-r--r-- | Compute-Class-Methods/clb0c0.h | 931 | ||||
| -rw-r--r-- | Compute-Class-Methods/clb1c0.h | 968 | ||||
| -rw-r--r-- | Compute-Class-Methods/clc0c0.h | 1006 | ||||
| -rw-r--r-- | Compute-Class-Methods/clc1c0.h | 1026 | ||||
| -rw-r--r-- | Compute-Class-Methods/clc3c0.h | 912 | ||||
| -rw-r--r-- | Compute-Class-Methods/clc5c0.h | 942 | ||||
| -rw-r--r-- | Compute-Class-Methods/index.html | 18 |
13 files changed, 0 insertions, 11075 deletions
diff --git a/Compute-Class-Methods/cl50c0.h b/Compute-Class-Methods/cl50c0.h deleted file mode 100644 index e22fed8..0000000 --- a/Compute-Class-Methods/cl50c0.h +++ /dev/null @@ -1,741 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_nv50_compute_h_ -#define _cl_nv50_compute_h_ - -/* This file is generated - do not edit. */ - -#include "nvtypes.h" - -#define NV50_COMPUTE 0x50C0 - -typedef volatile struct _cl50c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 Notify; - NvU32 Reserved_0x108[0x2]; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0xB]; - NvU32 PmTrigger; - NvU32 Reserved_0x144[0xF]; - NvU32 SetContextDmaNotify; - NvU32 Reserved_0x184[0x7]; - NvU32 SetCtxDmaGlobalMem; - NvU32 SetCtxDmaSemaphore; - NvU32 Reserved_0x1A8[0x4]; - NvU32 SetCtxDmaShaderThreadMemory; - NvU32 SetCtxDmaShaderThreadStack; - NvU32 SetCtxDmaShaderProgram; - NvU32 SetCtxDmaTextureSampler; - NvU32 SetCtxDmaTextureHeaders; - NvU32 SetCtxDmaTexture; - NvU32 Reserved_0x1D0[0xC]; - struct { - NvU32 Control; - NvU32 QuerySessionKey; - NvU32 GetSessionKey; - NvU32 SetEncryption; - } Decryption[0x1]; - NvU32 SetCtaProgramA; - NvU32 SetCtaProgramB; - NvU32 SetShaderThreadStackA; - NvU32 SetShaderThreadStackB; - NvU32 SetShaderThreadStackC; - NvU32 SetApiCallLimit; - NvU32 SetShaderL1CacheControl; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 LoadConstantSelector; - NvU32 LoadConstant[0x10]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 Reserved_0x284[0x1]; - NvU32 SetSmTimeoutInterval; - NvU32 TestForCompute; - NvU32 SetShaderScheduling; - NvU32 SetShaderThreadMemoryA; - NvU32 SetShaderThreadMemoryB; - NvU32 SetShaderThreadMemoryC; - NvU32 SetWorkDistribution; - NvU32 LoadConstantBufferTableA; - NvU32 LoadConstantBufferTableB; - NvU32 LoadConstantBufferTableC; - NvU32 SetShaderErrorTrapControl; - NvU32 SetCtaResourceAllocation; - NvU32 SetCtaThreadControl; - NvU32 SetPhaseIdControl; - NvU32 SetCtaRegisterCount; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 SetShaderPerformanceCounterValue[0x4]; - NvU32 SetShaderPerformanceCounterControl[0x4]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 ResetCtaTrackingRam; - NvU32 Initialize; - NvU32 SetShaderThreadMemoryThrottle; - NvU32 SetShaderThreadMemoryThrottleControl; - NvU32 SetShaderThreadStackThrottle; - NvU32 SetShaderThreadStackThrottleControl; - NvU32 PrefetchShaderInstructions; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 SetLaunchEnableA; - NvU32 SetLaunchEnableB; - NvU32 SetLaunchEnableC; - NvU32 SetCubemapAddressModeOverride; - NvU32 PipeNop; - NvU32 Reserved_0x334[0x3]; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x350[0x2]; - NvU32 SetGlobalColorKey; - NvU32 ResetRefCount; - NvU32 WaitRefCount; - NvU32 SetRefCountValue; - NvU32 Launch; - NvU32 SetLaunchId; - NvU32 SetLaunchControl; - NvU32 SetParameterSize; - NvU32 SetSamplerBinding; - NvU32 SetShaderControl; - NvU32 InvalidateShaderCache; - NvU32 SetRasterControl; - NvU32 SetCtaFlags; - NvU32 Reserved_0x38C[0x6]; - NvU32 SetCtaRasterSize; - NvU32 SetCtaGrfSize; - NvU32 SetCtaThreadDimensionA; - NvU32 SetCtaThreadDimensionB; - NvU32 SetCtaProgramStart; - NvU32 SetCtaRegisterAllocation; - NvU32 SetCtaTexture; - NvU32 BindCtaTextureSampler; - NvU32 BindCtaTextureHeader; - NvU32 BindConstantBuffer; - NvU32 PrefetchTextureSampler; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x3D4[0x6]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x3F0[0x4]; - struct { - NvU32 A; - NvU32 B; - NvU32 Size; - NvU32 Limit; - NvU32 Format; - NvU32 Reserved_0x14[0x3]; - } SetGlobalMem[0x10]; - NvU32 Parameter[0x40]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; -} nv50_compute_t; - - -#define NV50C0_SET_OBJECT 0x0000 -#define NV50C0_SET_OBJECT_POINTER 15:0 - -#define NV50C0_NO_OPERATION 0x0100 -#define NV50C0_NO_OPERATION_V 31:0 - -#define NV50C0_NOTIFY 0x0104 -#define NV50C0_NOTIFY_TYPE 31:0 -#define NV50C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NV50C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NV50C0_WAIT_FOR_IDLE 0x0110 -#define NV50C0_WAIT_FOR_IDLE_V 31:0 - -#define NV50C0_PM_TRIGGER 0x0140 -#define NV50C0_PM_TRIGGER_V 31:0 - -#define NV50C0_SET_CONTEXT_DMA_NOTIFY 0x0180 -#define NV50C0_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_GLOBAL_MEM 0x01a0 -#define NV50C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_SEMAPHORE 0x01a4 -#define NV50C0_SET_CTX_DMA_SEMAPHORE_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY 0x01b8 -#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK 0x01bc -#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM 0x01c0 -#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER 0x01c4 -#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS 0x01c8 -#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE 31:0 - -#define NV50C0_SET_CTX_DMA_TEXTURE 0x01cc -#define NV50C0_SET_CTX_DMA_TEXTURE_HANDLE 31:0 - -#define NV50C0_DECRYPTION_CONTROL(j) (0x0200+(j)*16) -#define NV50C0_DECRYPTION_CONTROL_ALGORITHM 15:0 -#define NV50C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE 0x00000000 -#define NV50C0_DECRYPTION_CONTROL_KEY_COUNT 23:16 - -#define NV50C0_DECRYPTION_QUERY_SESSION_KEY(j) (0x0204+(j)*16) -#define NV50C0_DECRYPTION_QUERY_SESSION_KEY_V 31:0 - -#define NV50C0_DECRYPTION_GET_SESSION_KEY(j) (0x0208+(j)*16) -#define NV50C0_DECRYPTION_GET_SESSION_KEY_V 31:0 - -#define NV50C0_DECRYPTION_SET_ENCRYPTION(j) (0x020c+(j)*16) -#define NV50C0_DECRYPTION_SET_ENCRYPTION_V 31:0 - -#define NV50C0_SET_CTA_PROGRAM_A 0x0210 -#define NV50C0_SET_CTA_PROGRAM_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_CTA_PROGRAM_B 0x0214 -#define NV50C0_SET_CTA_PROGRAM_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_SHADER_THREAD_STACK_A 0x0218 -#define NV50C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_SHADER_THREAD_STACK_B 0x021c -#define NV50C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_SHADER_THREAD_STACK_C 0x0220 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE 3:0 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__0 0x00000000 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1 0x00000001 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2 0x00000002 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4 0x00000003 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__8 0x00000004 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__16 0x00000005 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__32 0x00000006 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__64 0x00000007 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__128 0x00000008 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__256 0x00000009 -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__512 0x0000000A -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1024 0x0000000B -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2048 0x0000000C -#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4096 0x0000000D - -#define NV50C0_SET_API_CALL_LIMIT 0x0224 -#define NV50C0_SET_API_CALL_LIMIT_CTA 3:0 -#define NV50C0_SET_API_CALL_LIMIT_CTA__0 0x00000000 -#define NV50C0_SET_API_CALL_LIMIT_CTA__1 0x00000001 -#define NV50C0_SET_API_CALL_LIMIT_CTA__2 0x00000002 -#define NV50C0_SET_API_CALL_LIMIT_CTA__4 0x00000003 -#define NV50C0_SET_API_CALL_LIMIT_CTA__8 0x00000004 -#define NV50C0_SET_API_CALL_LIMIT_CTA__16 0x00000005 -#define NV50C0_SET_API_CALL_LIMIT_CTA__32 0x00000006 -#define NV50C0_SET_API_CALL_LIMIT_CTA__64 0x00000007 -#define NV50C0_SET_API_CALL_LIMIT_CTA__128 0x00000008 -#define NV50C0_SET_API_CALL_LIMIT_CTA_NO_CHECK 0x0000000F - -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL 0x0228 -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY 7:4 -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY 11:8 -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY 15:12 -#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY 19:16 - -#define NV50C0_SET_TEX_SAMPLER_POOL_A 0x022c -#define NV50C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_TEX_SAMPLER_POOL_B 0x0230 -#define NV50C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_TEX_SAMPLER_POOL_C 0x0234 -#define NV50C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NV50C0_LOAD_CONSTANT_SELECTOR 0x0238 -#define NV50C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX 7:0 -#define NV50C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX 23:8 - -#define NV50C0_LOAD_CONSTANT(i) (0x023c+(i)*4) -#define NV50C0_LOAD_CONSTANT_V 31:0 - -#define NV50C0_INVALIDATE_SAMPLER_CACHE 0x027c -#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NV50C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x0280 -#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NV50C0_SET_SM_TIMEOUT_INTERVAL 0x0288 -#define NV50C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NV50C0_TEST_FOR_COMPUTE 0x028c -#define NV50C0_TEST_FOR_COMPUTE_V 31:0 - -#define NV50C0_SET_SHADER_SCHEDULING 0x0290 -#define NV50C0_SET_SHADER_SCHEDULING_MODE 0:0 -#define NV50C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 -#define NV50C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 - -#define NV50C0_SET_SHADER_THREAD_MEMORY_A 0x0294 -#define NV50C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_SHADER_THREAD_MEMORY_B 0x0298 -#define NV50C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_SHADER_THREAD_MEMORY_C 0x029c -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE 3:0 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0 0x00000000 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1 0x00000001 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2 0x00000002 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4 0x00000003 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8 0x00000004 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16 0x00000005 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32 0x00000006 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64 0x00000007 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128 0x00000008 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256 0x00000009 -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512 0x0000000A -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024 0x0000000B -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048 0x0000000C -#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096 0x0000000D - -#define NV50C0_SET_WORK_DISTRIBUTION 0x02a0 -#define NV50C0_SET_WORK_DISTRIBUTION_V 3:0 -#define NV50C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY 0x00000000 -#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC 0x00000001 -#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC 0x00000002 -#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED 0x00000003 -#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED 0x00000004 -#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC 0x00000005 -#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC 0x00000006 -#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED 0x00000007 -#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED 0x00000008 - -#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A 0x02a4 -#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER 7:0 - -#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B 0x02a8 -#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER 31:0 - -#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C 0x02ac -#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE 15:0 -#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY 23:16 - -#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL 0x02b0 -#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK 0:0 -#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE 0x00000000 -#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE 0x00000001 -#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK 31:1 - -#define NV50C0_SET_CTA_RESOURCE_ALLOCATION 0x02b4 -#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT 15:0 -#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT 23:16 - -#define NV50C0_SET_CTA_THREAD_CONTROL 0x02b8 -#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH 0:0 -#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE 0x00000000 -#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE 0x00000001 - -#define NV50C0_SET_PHASE_ID_CONTROL 0x02bc -#define NV50C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE 2:0 -#define NV50C0_SET_PHASE_ID_CONTROL_LOCK_PHASE 6:4 - -#define NV50C0_SET_CTA_REGISTER_COUNT 0x02c0 -#define NV50C0_SET_CTA_REGISTER_COUNT_V 7:0 - -#define NV50C0_SET_TEX_HEADER_POOL_A 0x02c4 -#define NV50C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_TEX_HEADER_POOL_B 0x02c8 -#define NV50C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_TEX_HEADER_POOL_C 0x02cc -#define NV50C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x02d0+(i)*4) -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i) (0x02e0+(i)*4) -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE 0:0 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK 6:4 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE 0x00000000 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS 0x00000001 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM 0x00000002 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC 0x00000003 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP 0x00000004 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU 0x00000005 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC 23:8 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT 31:24 - -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x02f0 -#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 3:0 - -#define NV50C0_RESET_CTA_TRACKING_RAM 0x02f4 -#define NV50C0_RESET_CTA_TRACKING_RAM_V 31:0 - -#define NV50C0_INITIALIZE 0x02f8 -#define NV50C0_INITIALIZE_INIT_CTA_SHAPE 0:0 -#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_FALSE 0x00000000 -#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_TRUE 0x00000001 - -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE 0x02fc -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM 2:0 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 - -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL 0x0300 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V 2:0 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 -#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 - -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE 0x0304 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM 2:0 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 - -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL 0x0308 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V 2:0 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 -#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 - -#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS 0x030c -#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA 0:0 -#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE 0x00000000 -#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE 0x00000001 - -#define NV50C0_SET_REPORT_SEMAPHORE_A 0x0310 -#define NV50C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_REPORT_SEMAPHORE_B 0x0314 -#define NV50C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_REPORT_SEMAPHORE_C 0x0318 -#define NV50C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NV50C0_SET_REPORT_SEMAPHORE_D 0x031c -#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE 2:2 -#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE 3:3 -#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 7:4 -#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON 8:8 -#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 9:9 -#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT 14:10 -#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 15:15 -#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 - -#define NV50C0_SET_LAUNCH_ENABLE_A 0x0320 -#define NV50C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_LAUNCH_ENABLE_B 0x0324 -#define NV50C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_LAUNCH_ENABLE_C 0x0328 -#define NV50C0_SET_LAUNCH_ENABLE_C_MODE 2:0 -#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_FALSE 0x00000000 -#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_TRUE 0x00000001 -#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE 0x032c -#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE 31:0 -#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE 0x00000000 -#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE 0x00000001 - -#define NV50C0_PIPE_NOP 0x0330 -#define NV50C0_PIPE_NOP_V 31:0 - -#define NV50C0_SET_SPARE00 0x0340 -#define NV50C0_SET_SPARE00_V 31:0 - -#define NV50C0_SET_SPARE01 0x0344 -#define NV50C0_SET_SPARE01_V 31:0 - -#define NV50C0_SET_SPARE02 0x0348 -#define NV50C0_SET_SPARE02_V 31:0 - -#define NV50C0_SET_SPARE03 0x034c -#define NV50C0_SET_SPARE03_V 31:0 - -#define NV50C0_SET_GLOBAL_COLOR_KEY 0x0358 -#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE 31:0 -#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 -#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 - -#define NV50C0_RESET_REF_COUNT 0x035c -#define NV50C0_RESET_REF_COUNT_REF_CNT 3:0 - -#define NV50C0_WAIT_REF_COUNT 0x0360 -#define NV50C0_WAIT_REF_COUNT_COMPARE 7:4 -#define NV50C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT 0x00000000 -#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL 0x00000001 -#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND 0x00000002 -#define NV50C0_WAIT_REF_COUNT_REF_CNT 11:8 - -#define NV50C0_SET_REF_COUNT_VALUE 0x0364 -#define NV50C0_SET_REF_COUNT_VALUE_V 31:0 - -#define NV50C0_LAUNCH 0x0368 -#define NV50C0_LAUNCH_V 31:0 - -#define NV50C0_SET_LAUNCH_ID 0x036c -#define NV50C0_SET_LAUNCH_ID_REF_CNT 3:0 - -#define NV50C0_SET_LAUNCH_CONTROL 0x0370 -#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH 7:0 -#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH 0x00000000 -#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH 0x00000001 - -#define NV50C0_SET_PARAMETER_SIZE 0x0374 -#define NV50C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX 7:0 -#define NV50C0_SET_PARAMETER_SIZE_COUNT 15:8 - -#define NV50C0_SET_SAMPLER_BINDING 0x0378 -#define NV50C0_SET_SAMPLER_BINDING_V 0:0 -#define NV50C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 -#define NV50C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 - -#define NV50C0_SET_SHADER_CONTROL 0x037c -#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 -#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 -#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 -#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 -#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 -#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 - -#define NV50C0_INVALIDATE_SHADER_CACHE 0x0380 -#define NV50C0_INVALIDATE_SHADER_CACHE_V 1:0 -#define NV50C0_INVALIDATE_SHADER_CACHE_V_ALL 0x00000000 -#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1 0x00000001 -#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_DATA 0x00000002 -#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION 0x00000003 - -#define NV50C0_SET_RASTER_CONTROL 0x0384 -#define NV50C0_SET_RASTER_CONTROL_PROGRAM 7:0 -#define NV50C0_SET_RASTER_CONTROL_PROGRAM_DISABLE 0x00000000 -#define NV50C0_SET_RASTER_CONTROL_FIXED 15:8 -#define NV50C0_SET_RASTER_CONTROL_FIXED_DISABLE 0x00000000 -#define NV50C0_SET_RASTER_CONTROL_FIXED_SIMPLE 0x00000001 -#define NV50C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED 0x00000002 -#define NV50C0_SET_RASTER_CONTROL_DECRYPTION 23:16 -#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE 0x00000000 -#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE 0x00000001 - -#define NV50C0_SET_CTA_FLAGS 0x0388 -#define NV50C0_SET_CTA_FLAGS_V 15:0 - -#define NV50C0_SET_CTA_RASTER_SIZE 0x03a4 -#define NV50C0_SET_CTA_RASTER_SIZE_WIDTH 15:0 -#define NV50C0_SET_CTA_RASTER_SIZE_HEIGHT 31:16 - -#define NV50C0_SET_CTA_GRF_SIZE 0x03a8 -#define NV50C0_SET_CTA_GRF_SIZE_V 31:0 - -#define NV50C0_SET_CTA_THREAD_DIMENSION_A 0x03ac -#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 -#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 - -#define NV50C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 -#define NV50C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 - -#define NV50C0_SET_CTA_PROGRAM_START 0x03b4 -#define NV50C0_SET_CTA_PROGRAM_START_OFFSET 23:0 - -#define NV50C0_SET_CTA_REGISTER_ALLOCATION 0x03b8 -#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V 31:0 -#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THICK 0x00000001 -#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THIN 0x00000002 - -#define NV50C0_SET_CTA_TEXTURE 0x03bc -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS 7:4 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 -#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 - -#define NV50C0_BIND_CTA_TEXTURE_SAMPLER 0x03c0 -#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID 0:0 -#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 -#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 -#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 -#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_INDEX 24:12 - -#define NV50C0_BIND_CTA_TEXTURE_HEADER 0x03c4 -#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID 0:0 -#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE 0x00000000 -#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE 0x00000001 -#define NV50C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 -#define NV50C0_BIND_CTA_TEXTURE_HEADER_INDEX 30:9 - -#define NV50C0_BIND_CONSTANT_BUFFER 0x03c8 -#define NV50C0_BIND_CONSTANT_BUFFER_VALID 3:0 -#define NV50C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NV50C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE 7:4 -#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA 0x00000000 -#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 11:8 -#define NV50C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY 19:12 - -#define NV50C0_PREFETCH_TEXTURE_SAMPLER 0x03cc -#define NV50C0_PREFETCH_TEXTURE_SAMPLER_INDEX 21:0 - -#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE 0x03d0 -#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 5:4 -#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 -#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY 0x00000001 -#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2 0x00000002 - -#define NV50C0_SET_SHADER_EXCEPTIONS 0x03ec -#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NV50C0_SET_GLOBAL_MEM_A(j) (0x0400+(j)*32) -#define NV50C0_SET_GLOBAL_MEM_A_OFFSET_UPPER 7:0 - -#define NV50C0_SET_GLOBAL_MEM_B(j) (0x0404+(j)*32) -#define NV50C0_SET_GLOBAL_MEM_B_OFFSET_LOWER 31:0 - -#define NV50C0_SET_GLOBAL_MEM_SIZE(j) (0x0408+(j)*32) -#define NV50C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH 31:0 - -#define NV50C0_SET_GLOBAL_MEM_LIMIT(j) (0x040c+(j)*32) -#define NV50C0_SET_GLOBAL_MEM_LIMIT_MAX 31:0 - -#define NV50C0_SET_GLOBAL_MEM_FORMAT(j) (0x0410+(j)*32) -#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT 0:0 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR 0x00000000 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH 0x00000001 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH 7:4 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB 0x00000000 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT 11:8 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB 0x00000000 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS 0x00000001 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS 0x00000002 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS 0x00000003 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS 0x00000005 - -#define NV50C0_PARAMETER(i) (0x0600+(i)*4) -#define NV50C0_PARAMETER_V 31:0 - -#define NV50C0_SET_SPARE_NOOP00 0x0700 -#define NV50C0_SET_SPARE_NOOP00_V 31:0 - -#define NV50C0_SET_SPARE_NOOP01 0x0704 -#define NV50C0_SET_SPARE_NOOP01_V 31:0 - -#define NV50C0_SET_SPARE_NOOP02 0x0708 -#define NV50C0_SET_SPARE_NOOP02_V 31:0 - -#define NV50C0_SET_SPARE_NOOP03 0x070c -#define NV50C0_SET_SPARE_NOOP03_V 31:0 - -#define NV50C0_SET_SPARE_NOOP04 0x0710 -#define NV50C0_SET_SPARE_NOOP04_V 31:0 - -#define NV50C0_SET_SPARE_NOOP05 0x0714 -#define NV50C0_SET_SPARE_NOOP05_V 31:0 - -#define NV50C0_SET_SPARE_NOOP06 0x0718 -#define NV50C0_SET_SPARE_NOOP06_V 31:0 - -#define NV50C0_SET_SPARE_NOOP07 0x071c -#define NV50C0_SET_SPARE_NOOP07_V 31:0 - -#define NV50C0_SET_SPARE_NOOP08 0x0720 -#define NV50C0_SET_SPARE_NOOP08_V 31:0 - -#define NV50C0_SET_SPARE_NOOP09 0x0724 -#define NV50C0_SET_SPARE_NOOP09_V 31:0 - -#define NV50C0_SET_SPARE_NOOP10 0x0728 -#define NV50C0_SET_SPARE_NOOP10_V 31:0 - -#define NV50C0_SET_SPARE_NOOP11 0x072c -#define NV50C0_SET_SPARE_NOOP11_V 31:0 - -#define NV50C0_SET_SPARE_NOOP12 0x0730 -#define NV50C0_SET_SPARE_NOOP12_V 31:0 - -#define NV50C0_SET_SPARE_NOOP13 0x0734 -#define NV50C0_SET_SPARE_NOOP13_V 31:0 - -#define NV50C0_SET_SPARE_NOOP14 0x0738 -#define NV50C0_SET_SPARE_NOOP14_V 31:0 - -#define NV50C0_SET_SPARE_NOOP15 0x073c -#define NV50C0_SET_SPARE_NOOP15_V 31:0 - -#endif /* _cl_nv50_compute_h_ */ diff --git a/Compute-Class-Methods/cl85c0.h b/Compute-Class-Methods/cl85c0.h deleted file mode 100644 index 4234fd0..0000000 --- a/Compute-Class-Methods/cl85c0.h +++ /dev/null @@ -1,747 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_gt214_compute_h_ -#define _cl_gt214_compute_h_ - -/* This file is generated - do not edit. */ - -#include "nvtypes.h" - -#define GT214_COMPUTE 0x85C0 - -typedef volatile struct _cl85c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 Notify; - NvU32 Reserved_0x108[0x2]; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0xB]; - NvU32 PmTrigger; - NvU32 Reserved_0x144[0xF]; - NvU32 SetContextDmaNotify; - NvU32 Reserved_0x184[0x7]; - NvU32 SetCtxDmaGlobalMem; - NvU32 SetCtxDmaSemaphore; - NvU32 Reserved_0x1A8[0x4]; - NvU32 SetCtxDmaShaderThreadMemory; - NvU32 SetCtxDmaShaderThreadStack; - NvU32 SetCtxDmaShaderProgram; - NvU32 SetCtxDmaTextureSampler; - NvU32 SetCtxDmaTextureHeaders; - NvU32 SetCtxDmaTexture; - NvU32 Reserved_0x1D0[0xC]; - struct { - NvU32 Control; - NvU32 QuerySessionKey; - NvU32 GetSessionKey; - NvU32 SetEncryption; - } Decryption[0x1]; - NvU32 SetCtaProgramA; - NvU32 SetCtaProgramB; - NvU32 SetShaderThreadStackA; - NvU32 SetShaderThreadStackB; - NvU32 SetShaderThreadStackC; - NvU32 SetApiCallLimit; - NvU32 SetShaderL1CacheControl; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 LoadConstantSelector; - NvU32 LoadConstant[0x10]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 Reserved_0x284[0x1]; - NvU32 SetSmTimeoutInterval; - NvU32 TestForCompute; - NvU32 SetShaderScheduling; - NvU32 SetShaderThreadMemoryA; - NvU32 SetShaderThreadMemoryB; - NvU32 SetShaderThreadMemoryC; - NvU32 SetWorkDistribution; - NvU32 LoadConstantBufferTableA; - NvU32 LoadConstantBufferTableB; - NvU32 LoadConstantBufferTableC; - NvU32 SetShaderErrorTrapControl; - NvU32 SetCtaResourceAllocation; - NvU32 SetCtaThreadControl; - NvU32 SetPhaseIdControl; - NvU32 SetCtaRegisterCount; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 SetShaderPerformanceCounterValue[0x4]; - NvU32 SetShaderPerformanceCounterControl[0x4]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 ResetCtaTrackingRam; - NvU32 Initialize; - NvU32 SetShaderThreadMemoryThrottle; - NvU32 SetShaderThreadMemoryThrottleControl; - NvU32 SetShaderThreadStackThrottle; - NvU32 SetShaderThreadStackThrottleControl; - NvU32 PrefetchShaderInstructions; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 SetLaunchEnableA; - NvU32 SetLaunchEnableB; - NvU32 SetLaunchEnableC; - NvU32 SetCubemapAddressModeOverride; - NvU32 PipeNop; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop10; - NvU32 SetGlobalColorKey; - NvU32 ResetRefCount; - NvU32 WaitRefCount; - NvU32 SetRefCountValue; - NvU32 Launch; - NvU32 SetLaunchId; - NvU32 SetLaunchControl; - NvU32 SetParameterSize; - NvU32 SetSamplerBinding; - NvU32 SetShaderControl; - NvU32 InvalidateShaderCache; - NvU32 SetRasterControl; - NvU32 SetCtaFlags; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop15; - NvU32 SetSpareNoop11; - NvU32 SetSpare02; - NvU32 SetSpareNoop02; - NvU32 SetSpare03; - NvU32 SetCtaRasterSize; - NvU32 SetCtaGrfSize; - NvU32 SetCtaThreadDimensionA; - NvU32 SetCtaThreadDimensionB; - NvU32 SetCtaProgramStart; - NvU32 SetCtaRegisterAllocation; - NvU32 SetCtaTexture; - NvU32 BindCtaTextureSampler; - NvU32 BindCtaTextureHeader; - NvU32 BindConstantBuffer; - NvU32 PrefetchTextureSampler; - NvU32 InvalidateTextureDataCache; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop12; - NvU32 SetCubemapInterFaceFiltering; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x3F0[0x4]; - struct { - NvU32 A; - NvU32 B; - NvU32 Size; - NvU32 Limit; - NvU32 Format; - NvU32 Reserved_0x14[0x3]; - } SetGlobalMem[0x10]; - NvU32 Parameter[0x40]; -} gt214_compute_t; - - -#define NV85C0_SET_OBJECT 0x0000 -#define NV85C0_SET_OBJECT_POINTER 15:0 - -#define NV85C0_NO_OPERATION 0x0100 -#define NV85C0_NO_OPERATION_V 31:0 - -#define NV85C0_NOTIFY 0x0104 -#define NV85C0_NOTIFY_TYPE 31:0 -#define NV85C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NV85C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NV85C0_WAIT_FOR_IDLE 0x0110 -#define NV85C0_WAIT_FOR_IDLE_V 31:0 - -#define NV85C0_PM_TRIGGER 0x0140 -#define NV85C0_PM_TRIGGER_V 31:0 - -#define NV85C0_SET_CONTEXT_DMA_NOTIFY 0x0180 -#define NV85C0_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_GLOBAL_MEM 0x01a0 -#define NV85C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_SEMAPHORE 0x01a4 -#define NV85C0_SET_CTX_DMA_SEMAPHORE_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY 0x01b8 -#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK 0x01bc -#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM 0x01c0 -#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER 0x01c4 -#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS 0x01c8 -#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE 31:0 - -#define NV85C0_SET_CTX_DMA_TEXTURE 0x01cc -#define NV85C0_SET_CTX_DMA_TEXTURE_HANDLE 31:0 - -#define NV85C0_DECRYPTION_CONTROL(j) (0x0200+(j)*16) -#define NV85C0_DECRYPTION_CONTROL_ALGORITHM 15:0 -#define NV85C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE 0x00000000 -#define NV85C0_DECRYPTION_CONTROL_KEY_COUNT 23:16 - -#define NV85C0_DECRYPTION_QUERY_SESSION_KEY(j) (0x0204+(j)*16) -#define NV85C0_DECRYPTION_QUERY_SESSION_KEY_V 31:0 - -#define NV85C0_DECRYPTION_GET_SESSION_KEY(j) (0x0208+(j)*16) -#define NV85C0_DECRYPTION_GET_SESSION_KEY_V 31:0 - -#define NV85C0_DECRYPTION_SET_ENCRYPTION(j) (0x020c+(j)*16) -#define NV85C0_DECRYPTION_SET_ENCRYPTION_V 31:0 - -#define NV85C0_SET_CTA_PROGRAM_A 0x0210 -#define NV85C0_SET_CTA_PROGRAM_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_CTA_PROGRAM_B 0x0214 -#define NV85C0_SET_CTA_PROGRAM_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_SHADER_THREAD_STACK_A 0x0218 -#define NV85C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_SHADER_THREAD_STACK_B 0x021c -#define NV85C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_SHADER_THREAD_STACK_C 0x0220 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE 3:0 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__0 0x00000000 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1 0x00000001 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2 0x00000002 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4 0x00000003 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__8 0x00000004 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__16 0x00000005 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__32 0x00000006 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__64 0x00000007 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__128 0x00000008 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__256 0x00000009 -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__512 0x0000000A -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1024 0x0000000B -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2048 0x0000000C -#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4096 0x0000000D - -#define NV85C0_SET_API_CALL_LIMIT 0x0224 -#define NV85C0_SET_API_CALL_LIMIT_CTA 3:0 -#define NV85C0_SET_API_CALL_LIMIT_CTA__0 0x00000000 -#define NV85C0_SET_API_CALL_LIMIT_CTA__1 0x00000001 -#define NV85C0_SET_API_CALL_LIMIT_CTA__2 0x00000002 -#define NV85C0_SET_API_CALL_LIMIT_CTA__4 0x00000003 -#define NV85C0_SET_API_CALL_LIMIT_CTA__8 0x00000004 -#define NV85C0_SET_API_CALL_LIMIT_CTA__16 0x00000005 -#define NV85C0_SET_API_CALL_LIMIT_CTA__32 0x00000006 -#define NV85C0_SET_API_CALL_LIMIT_CTA__64 0x00000007 -#define NV85C0_SET_API_CALL_LIMIT_CTA__128 0x00000008 -#define NV85C0_SET_API_CALL_LIMIT_CTA_NO_CHECK 0x0000000F - -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL 0x0228 -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY 7:4 -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY 11:8 -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY 15:12 -#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY 19:16 - -#define NV85C0_SET_TEX_SAMPLER_POOL_A 0x022c -#define NV85C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_TEX_SAMPLER_POOL_B 0x0230 -#define NV85C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_TEX_SAMPLER_POOL_C 0x0234 -#define NV85C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NV85C0_LOAD_CONSTANT_SELECTOR 0x0238 -#define NV85C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX 7:0 -#define NV85C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX 23:8 - -#define NV85C0_LOAD_CONSTANT(i) (0x023c+(i)*4) -#define NV85C0_LOAD_CONSTANT_V 31:0 - -#define NV85C0_INVALIDATE_SAMPLER_CACHE 0x027c -#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NV85C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x0280 -#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NV85C0_SET_SM_TIMEOUT_INTERVAL 0x0288 -#define NV85C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NV85C0_TEST_FOR_COMPUTE 0x028c -#define NV85C0_TEST_FOR_COMPUTE_V 31:0 - -#define NV85C0_SET_SHADER_SCHEDULING 0x0290 -#define NV85C0_SET_SHADER_SCHEDULING_MODE 0:0 -#define NV85C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 -#define NV85C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 - -#define NV85C0_SET_SHADER_THREAD_MEMORY_A 0x0294 -#define NV85C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_SHADER_THREAD_MEMORY_B 0x0298 -#define NV85C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_SHADER_THREAD_MEMORY_C 0x029c -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE 3:0 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0 0x00000000 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1 0x00000001 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2 0x00000002 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4 0x00000003 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8 0x00000004 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16 0x00000005 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32 0x00000006 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64 0x00000007 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128 0x00000008 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256 0x00000009 -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512 0x0000000A -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024 0x0000000B -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048 0x0000000C -#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096 0x0000000D - -#define NV85C0_SET_WORK_DISTRIBUTION 0x02a0 -#define NV85C0_SET_WORK_DISTRIBUTION_V 3:0 -#define NV85C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY 0x00000000 -#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC 0x00000001 -#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC 0x00000002 -#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED 0x00000003 -#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED 0x00000004 -#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC 0x00000005 -#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC 0x00000006 -#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED 0x00000007 -#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED 0x00000008 - -#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A 0x02a4 -#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER 7:0 - -#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B 0x02a8 -#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER 31:0 - -#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C 0x02ac -#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE 15:0 -#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY 23:16 - -#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL 0x02b0 -#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK 0:0 -#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE 0x00000000 -#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE 0x00000001 -#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK 31:1 - -#define NV85C0_SET_CTA_RESOURCE_ALLOCATION 0x02b4 -#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT 15:0 -#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT 23:16 - -#define NV85C0_SET_CTA_THREAD_CONTROL 0x02b8 -#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH 0:0 -#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE 0x00000000 -#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE 0x00000001 - -#define NV85C0_SET_PHASE_ID_CONTROL 0x02bc -#define NV85C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE 2:0 -#define NV85C0_SET_PHASE_ID_CONTROL_LOCK_PHASE 6:4 - -#define NV85C0_SET_CTA_REGISTER_COUNT 0x02c0 -#define NV85C0_SET_CTA_REGISTER_COUNT_V 7:0 - -#define NV85C0_SET_TEX_HEADER_POOL_A 0x02c4 -#define NV85C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_TEX_HEADER_POOL_B 0x02c8 -#define NV85C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_TEX_HEADER_POOL_C 0x02cc -#define NV85C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x02d0+(i)*4) -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i) (0x02e0+(i)*4) -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE 0:0 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK 6:4 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE 0x00000000 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS 0x00000001 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM 0x00000002 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC 0x00000003 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP 0x00000004 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU 0x00000005 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC 23:8 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT 31:24 - -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x02f0 -#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 3:0 - -#define NV85C0_RESET_CTA_TRACKING_RAM 0x02f4 -#define NV85C0_RESET_CTA_TRACKING_RAM_V 31:0 - -#define NV85C0_INITIALIZE 0x02f8 -#define NV85C0_INITIALIZE_INIT_CTA_SHAPE 0:0 -#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_FALSE 0x00000000 -#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_TRUE 0x00000001 - -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE 0x02fc -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM 2:0 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__24 0x00000005 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 - -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL 0x0300 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V 2:0 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 -#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 - -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE 0x0304 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM 2:0 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__24 0x00000005 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 - -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL 0x0308 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V 2:0 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 -#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 - -#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS 0x030c -#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA 0:0 -#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE 0x00000000 -#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE 0x00000001 - -#define NV85C0_SET_REPORT_SEMAPHORE_A 0x0310 -#define NV85C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_REPORT_SEMAPHORE_B 0x0314 -#define NV85C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_REPORT_SEMAPHORE_C 0x0318 -#define NV85C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NV85C0_SET_REPORT_SEMAPHORE_D 0x031c -#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE 2:2 -#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE 3:3 -#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 7:4 -#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON 8:8 -#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 9:9 -#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT 14:10 -#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 15:15 -#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 - -#define NV85C0_SET_LAUNCH_ENABLE_A 0x0320 -#define NV85C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_LAUNCH_ENABLE_B 0x0324 -#define NV85C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_LAUNCH_ENABLE_C 0x0328 -#define NV85C0_SET_LAUNCH_ENABLE_C_MODE 2:0 -#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_FALSE 0x00000000 -#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_TRUE 0x00000001 -#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE 0x032c -#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE 31:0 -#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE 0x00000000 -#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE 0x00000001 - -#define NV85C0_PIPE_NOP 0x0330 -#define NV85C0_PIPE_NOP_V 31:0 - -#define NV85C0_SET_SPARE_NOOP13 0x0334 -#define NV85C0_SET_SPARE_NOOP13_V 31:0 - -#define NV85C0_SET_SPARE_NOOP09 0x0338 -#define NV85C0_SET_SPARE_NOOP09_V 31:0 - -#define NV85C0_SET_SPARE_NOOP14 0x033c -#define NV85C0_SET_SPARE_NOOP14_V 31:0 - -#define NV85C0_SET_SPARE_NOOP00 0x0340 -#define NV85C0_SET_SPARE_NOOP00_V 31:0 - -#define NV85C0_SET_SPARE_NOOP01 0x0344 -#define NV85C0_SET_SPARE_NOOP01_V 31:0 - -#define NV85C0_SET_SPARE00 0x0348 -#define NV85C0_SET_SPARE00_V 31:0 - -#define NV85C0_SET_SPARE01 0x034c -#define NV85C0_SET_SPARE01_V 31:0 - -#define NV85C0_SET_SPARE_NOOP05 0x0350 -#define NV85C0_SET_SPARE_NOOP05_V 31:0 - -#define NV85C0_SET_SPARE_NOOP10 0x0354 -#define NV85C0_SET_SPARE_NOOP10_V 31:0 - -#define NV85C0_SET_GLOBAL_COLOR_KEY 0x0358 -#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE 31:0 -#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 -#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 - -#define NV85C0_RESET_REF_COUNT 0x035c -#define NV85C0_RESET_REF_COUNT_REF_CNT 3:0 - -#define NV85C0_WAIT_REF_COUNT 0x0360 -#define NV85C0_WAIT_REF_COUNT_COMPARE 7:4 -#define NV85C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT 0x00000000 -#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL 0x00000001 -#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND 0x00000002 -#define NV85C0_WAIT_REF_COUNT_REF_CNT 11:8 - -#define NV85C0_SET_REF_COUNT_VALUE 0x0364 -#define NV85C0_SET_REF_COUNT_VALUE_V 31:0 - -#define NV85C0_LAUNCH 0x0368 -#define NV85C0_LAUNCH_V 31:0 - -#define NV85C0_SET_LAUNCH_ID 0x036c -#define NV85C0_SET_LAUNCH_ID_REF_CNT 3:0 - -#define NV85C0_SET_LAUNCH_CONTROL 0x0370 -#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH 7:0 -#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH 0x00000000 -#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH 0x00000001 - -#define NV85C0_SET_PARAMETER_SIZE 0x0374 -#define NV85C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX 7:0 -#define NV85C0_SET_PARAMETER_SIZE_COUNT 15:8 - -#define NV85C0_SET_SAMPLER_BINDING 0x0378 -#define NV85C0_SET_SAMPLER_BINDING_V 0:0 -#define NV85C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 -#define NV85C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 - -#define NV85C0_SET_SHADER_CONTROL 0x037c -#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 -#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 -#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 -#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 -#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 -#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 - -#define NV85C0_INVALIDATE_SHADER_CACHE 0x0380 -#define NV85C0_INVALIDATE_SHADER_CACHE_V 1:0 -#define NV85C0_INVALIDATE_SHADER_CACHE_V_ALL 0x00000000 -#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1 0x00000001 -#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_DATA 0x00000002 -#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION 0x00000003 - -#define NV85C0_SET_RASTER_CONTROL 0x0384 -#define NV85C0_SET_RASTER_CONTROL_PROGRAM 7:0 -#define NV85C0_SET_RASTER_CONTROL_PROGRAM_DISABLE 0x00000000 -#define NV85C0_SET_RASTER_CONTROL_FIXED 15:8 -#define NV85C0_SET_RASTER_CONTROL_FIXED_DISABLE 0x00000000 -#define NV85C0_SET_RASTER_CONTROL_FIXED_SIMPLE 0x00000001 -#define NV85C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED 0x00000002 -#define NV85C0_SET_RASTER_CONTROL_DECRYPTION 23:16 -#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE 0x00000000 -#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE 0x00000001 - -#define NV85C0_SET_CTA_FLAGS 0x0388 -#define NV85C0_SET_CTA_FLAGS_V 15:0 - -#define NV85C0_SET_SPARE_NOOP06 0x038c -#define NV85C0_SET_SPARE_NOOP06_V 31:0 - -#define NV85C0_SET_SPARE_NOOP15 0x0390 -#define NV85C0_SET_SPARE_NOOP15_V 31:0 - -#define NV85C0_SET_SPARE_NOOP11 0x0394 -#define NV85C0_SET_SPARE_NOOP11_V 31:0 - -#define NV85C0_SET_SPARE02 0x0398 -#define NV85C0_SET_SPARE02_V 31:0 - -#define NV85C0_SET_SPARE_NOOP02 0x039c -#define NV85C0_SET_SPARE_NOOP02_V 31:0 - -#define NV85C0_SET_SPARE03 0x03a0 -#define NV85C0_SET_SPARE03_V 31:0 - -#define NV85C0_SET_CTA_RASTER_SIZE 0x03a4 -#define NV85C0_SET_CTA_RASTER_SIZE_WIDTH 15:0 -#define NV85C0_SET_CTA_RASTER_SIZE_HEIGHT 31:16 - -#define NV85C0_SET_CTA_GRF_SIZE 0x03a8 -#define NV85C0_SET_CTA_GRF_SIZE_V 31:0 - -#define NV85C0_SET_CTA_THREAD_DIMENSION_A 0x03ac -#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 -#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 - -#define NV85C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 -#define NV85C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 - -#define NV85C0_SET_CTA_PROGRAM_START 0x03b4 -#define NV85C0_SET_CTA_PROGRAM_START_OFFSET 23:0 - -#define NV85C0_SET_CTA_REGISTER_ALLOCATION 0x03b8 -#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V 31:0 -#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THICK 0x00000001 -#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THIN 0x00000002 - -#define NV85C0_SET_CTA_TEXTURE 0x03bc -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS 7:4 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 -#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 - -#define NV85C0_BIND_CTA_TEXTURE_SAMPLER 0x03c0 -#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID 0:0 -#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 -#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 -#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 -#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_INDEX 24:12 - -#define NV85C0_BIND_CTA_TEXTURE_HEADER 0x03c4 -#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID 0:0 -#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE 0x00000000 -#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE 0x00000001 -#define NV85C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 -#define NV85C0_BIND_CTA_TEXTURE_HEADER_INDEX 30:9 - -#define NV85C0_BIND_CONSTANT_BUFFER 0x03c8 -#define NV85C0_BIND_CONSTANT_BUFFER_VALID 3:0 -#define NV85C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NV85C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE 7:4 -#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA 0x00000000 -#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 11:8 -#define NV85C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY 19:12 - -#define NV85C0_PREFETCH_TEXTURE_SAMPLER 0x03cc -#define NV85C0_PREFETCH_TEXTURE_SAMPLER_INDEX 21:0 - -#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE 0x03d0 -#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 5:4 -#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 -#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY 0x00000001 -#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2 0x00000002 - -#define NV85C0_SET_SPARE_NOOP03 0x03d4 -#define NV85C0_SET_SPARE_NOOP03_V 31:0 - -#define NV85C0_SET_SPARE_NOOP07 0x03d8 -#define NV85C0_SET_SPARE_NOOP07_V 31:0 - -#define NV85C0_SET_SPARE_NOOP04 0x03dc -#define NV85C0_SET_SPARE_NOOP04_V 31:0 - -#define NV85C0_SET_SPARE_NOOP08 0x03e0 -#define NV85C0_SET_SPARE_NOOP08_V 31:0 - -#define NV85C0_SET_SPARE_NOOP12 0x03e4 -#define NV85C0_SET_SPARE_NOOP12_V 31:0 - -#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x03e8 -#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 -#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 -#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 -#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 -#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 - -#define NV85C0_SET_SHADER_EXCEPTIONS 0x03ec -#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NV85C0_SET_GLOBAL_MEM_A(j) (0x0400+(j)*32) -#define NV85C0_SET_GLOBAL_MEM_A_OFFSET_UPPER 7:0 - -#define NV85C0_SET_GLOBAL_MEM_B(j) (0x0404+(j)*32) -#define NV85C0_SET_GLOBAL_MEM_B_OFFSET_LOWER 31:0 - -#define NV85C0_SET_GLOBAL_MEM_SIZE(j) (0x0408+(j)*32) -#define NV85C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH 31:0 - -#define NV85C0_SET_GLOBAL_MEM_LIMIT(j) (0x040c+(j)*32) -#define NV85C0_SET_GLOBAL_MEM_LIMIT_MAX 31:0 - -#define NV85C0_SET_GLOBAL_MEM_FORMAT(j) (0x0410+(j)*32) -#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT 0:0 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR 0x00000000 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH 0x00000001 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH 7:4 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB 0x00000000 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT 11:8 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB 0x00000000 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS 0x00000001 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS 0x00000002 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS 0x00000003 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS 0x00000005 - -#define NV85C0_PARAMETER(i) (0x0600+(i)*4) -#define NV85C0_PARAMETER_V 31:0 - -#endif /* _cl_gt214_compute_h_ */ diff --git a/Compute-Class-Methods/cl90c0.h b/Compute-Class-Methods/cl90c0.h deleted file mode 100644 index d49ab75..0000000 --- a/Compute-Class-Methods/cl90c0.h +++ /dev/null @@ -1,1033 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_fermi_compute_a_h_ -#define _cl_fermi_compute_a_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../class/bin/sw_header.pl fermi_compute_a */ - -#include "nvtypes.h" - -#define FERMI_COMPUTE_A 0x90C0 - -typedef volatile struct _cl90c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 LoadMmeInstructionRamPointer; - NvU32 LoadMmeInstructionRam; - NvU32 LoadMmeStartAddressRamPointer; - NvU32 LoadMmeStartAddressRam; - NvU32 SetMmeShadowRamControl; - NvU32 Reserved_0x128[0x2]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 Reserved_0x144[0x3]; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0x2B]; - NvU32 SetShaderLocalMemoryLowSize; - NvU32 SetShaderLocalMemoryHighSize; - NvU32 SetShaderLocalMemoryCrsSize; - NvU32 SetBindingControlTexture; - NvU32 SetShaderSharedMemoryWindow; - NvU32 Reserved_0x218[0x1]; - NvU32 InvalidateShaderCaches; - NvU32 Reserved_0x220[0x2]; - NvU32 BindTextureSampler; - NvU32 BindTextureHeader; - NvU32 BindExtraTextureSampler; - NvU32 BindExtraTextureHeader; - NvU32 SetCtaRasterSizeA; - NvU32 SetCtaRasterSizeB; - NvU32 Reserved_0x240[0x1]; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 Reserved_0x248[0x1]; - NvU32 SetShaderSharedMemorySize; - NvU32 SetCtaThreadCount; - NvU32 SetCtaBarrierCount; - NvU32 Reserved_0x258[0xD]; - NvU32 TestForCompute; - NvU32 Reserved_0x290[0x3]; - NvU32 BeginGrid; - NvU32 SetWorkDistribution; - NvU32 Reserved_0x2A4[0x7]; - NvU32 SetCtaRegisterCount; - NvU32 SetGaToVaMappingMode; - NvU32 LoadGaToVaMappingEntry; - NvU32 Reserved_0x2CC[0xF]; - NvU32 SetL1Configuration; - NvU32 SetRenderEnableControl; - NvU32 Reserved_0x310[0x14]; - NvU32 WaitRefCount; - NvU32 Reserved_0x364[0x1]; - NvU32 Launch; - NvU32 SetLaunchId; - NvU32 Reserved_0x370[0xF]; - NvU32 SetCtaThreadDimensionA; - NvU32 SetCtaThreadDimensionB; - NvU32 SetCtaProgramStart; - NvU32 Reserved_0x3B8[0x52]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x76]; - NvU32 SetMaxSmCount; - NvU32 Reserved_0x75C[0x8]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 SetGridParam; - NvU32 Reserved_0x784[0x3]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 SetShaderLocalMemoryC; - NvU32 SetShaderLocalMemoryD; - NvU32 SetShaderLocalMemoryE; - NvU32 Reserved_0x7A4[0x98]; - NvU32 EndGrid; - NvU32 SetLaunchSize; - NvU32 Reserved_0xA0C[0xD6]; - NvU32 SetApiVisibleCallLimit; - NvU32 Reserved_0xD68[0xB]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x2C]; - NvU32 SetForceOneTextureUnit; - NvU32 Reserved_0x1008[0xE]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x21]; - NvU32 UnbindAll; - NvU32 Reserved_0x10F8[0x4F]; - NvU32 SetSamplerBinding; - NvU32 Reserved_0x1238[0x14]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x8]; - NvU32 SetShaderScheduling; - NvU32 Reserved_0x12B0[0x20]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x6]; - NvU32 SetGlobalColorKey; - NvU32 Reserved_0x1358[0x33]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x3F]; - NvU32 PerfmonTransfer; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x15]; - NvU32 SetCubemapInterFaceFiltering; - NvU32 Reserved_0x1668[0xA]; - NvU32 SetShaderControl; - NvU32 BindConstantBuffer; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xA5]; - NvU32 InvalidateConstantBufferCache; - NvU32 Reserved_0x1934[0x4]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x21C]; - NvU32 SetConstantBufferSelectorA; - NvU32 SetConstantBufferSelectorB; - NvU32 SetConstantBufferSelectorC; - NvU32 LoadConstantBufferOffset; - NvU32 LoadConstantBuffer[0x10]; - NvU32 Reserved_0x23D0[0xCC]; - struct { - NvU32 A; - NvU32 B; - NvU32 C; - NvU32 D; - NvU32 Format; - NvU32 BlockSize; - NvU32 Reserved_0x18[0x2]; - } SetSuLdStTarget[0x8]; - NvU32 Reserved_0x2800[0x2D7]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 Reserved_0x33E0[0x8]; - NvU32 SetMmeShadowScratch[0x80]; - NvU32 Reserved_0x3600[0x80]; - struct { - NvU32 Macro; - NvU32 Data; - } CallMme[0x80]; -} fermi_compute_a_t; - - -#define NV90C0_SET_OBJECT 0x0000 -#define NV90C0_SET_OBJECT_CLASS_ID 15:0 -#define NV90C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NV90C0_NO_OPERATION 0x0100 -#define NV90C0_NO_OPERATION_V 31:0 - -#define NV90C0_SET_NOTIFY_A 0x0104 -#define NV90C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NV90C0_SET_NOTIFY_B 0x0108 -#define NV90C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NV90C0_NOTIFY 0x010c -#define NV90C0_NOTIFY_TYPE 31:0 -#define NV90C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NV90C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NV90C0_WAIT_FOR_IDLE 0x0110 -#define NV90C0_WAIT_FOR_IDLE_V 31:0 - -#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 -#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 - -#define NV90C0_LOAD_MME_INSTRUCTION_RAM 0x0118 -#define NV90C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 - -#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c -#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 - -#define NV90C0_LOAD_MME_START_ADDRESS_RAM 0x0120 -#define NV90C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 - -#define NV90C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 -#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 -#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 -#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 -#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 -#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 - -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NV90C0_SEND_GO_IDLE 0x013c -#define NV90C0_SEND_GO_IDLE_V 31:0 - -#define NV90C0_PM_TRIGGER 0x0140 -#define NV90C0_PM_TRIGGER_V 31:0 - -#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE 0x0204 -#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V 23:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE 0x0208 -#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V 23:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE 0x020c -#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V 20:0 - -#define NV90C0_SET_BINDING_CONTROL_TEXTURE 0x0210 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 -#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 - -#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NV90C0_INVALIDATE_SHADER_CACHES 0x021c -#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 -#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NV90C0_BIND_TEXTURE_SAMPLER 0x0228 -#define NV90C0_BIND_TEXTURE_SAMPLER_VALID 0:0 -#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 -#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 -#define NV90C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 -#define NV90C0_BIND_TEXTURE_SAMPLER_INDEX 24:12 - -#define NV90C0_BIND_TEXTURE_HEADER 0x022c -#define NV90C0_BIND_TEXTURE_HEADER_VALID 0:0 -#define NV90C0_BIND_TEXTURE_HEADER_VALID_FALSE 0x00000000 -#define NV90C0_BIND_TEXTURE_HEADER_VALID_TRUE 0x00000001 -#define NV90C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT 8:1 -#define NV90C0_BIND_TEXTURE_HEADER_INDEX 30:9 - -#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER 0x0230 -#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID 0:0 -#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 -#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 -#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 -#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 - -#define NV90C0_BIND_EXTRA_TEXTURE_HEADER 0x0234 -#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID 0:0 -#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 -#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 -#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 -#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_INDEX 30:9 - -#define NV90C0_SET_CTA_RASTER_SIZE_A 0x0238 -#define NV90C0_SET_CTA_RASTER_SIZE_A_WIDTH 15:0 -#define NV90C0_SET_CTA_RASTER_SIZE_A_HEIGHT 31:16 - -#define NV90C0_SET_CTA_RASTER_SIZE_B 0x023c -#define NV90C0_SET_CTA_RASTER_SIZE_B_DEPTH 15:0 - -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE 0x024c -#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE_V 17:0 - -#define NV90C0_SET_CTA_THREAD_COUNT 0x0250 -#define NV90C0_SET_CTA_THREAD_COUNT_V 15:0 - -#define NV90C0_SET_CTA_BARRIER_COUNT 0x0254 -#define NV90C0_SET_CTA_BARRIER_COUNT_V 7:0 - -#define NV90C0_TEST_FOR_COMPUTE 0x028c -#define NV90C0_TEST_FOR_COMPUTE_V 31:0 - -#define NV90C0_BEGIN_GRID 0x029c -#define NV90C0_BEGIN_GRID_V 0:0 - -#define NV90C0_SET_WORK_DISTRIBUTION 0x02a0 -#define NV90C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE 16:13 -#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE 4:4 -#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE 0x00000000 -#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE 0x00000001 -#define NV90C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS 12:5 - -#define NV90C0_SET_CTA_REGISTER_COUNT 0x02c0 -#define NV90C0_SET_CTA_REGISTER_COUNT_V 7:0 - -#define NV90C0_SET_GA_TO_VA_MAPPING_MODE 0x02c4 -#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V 0:0 -#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 -#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 - -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 -#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 - -#define NV90C0_SET_L1_CONFIGURATION 0x0308 -#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 -#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 - -#define NV90C0_SET_RENDER_ENABLE_CONTROL 0x030c -#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 -#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 -#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 - -#define NV90C0_WAIT_REF_COUNT 0x0360 -#define NV90C0_WAIT_REF_COUNT_REF_CNT 9:8 -#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM 0:0 -#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE 0x00000000 -#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE 0x00000001 - -#define NV90C0_LAUNCH 0x0368 -#define NV90C0_LAUNCHCTA_PARAM 31:0 - -#define NV90C0_SET_LAUNCH_ID 0x036c -#define NV90C0_SET_LAUNCH_ID_REF_CNT 1:0 - -#define NV90C0_SET_CTA_THREAD_DIMENSION_A 0x03ac -#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 -#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 - -#define NV90C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 -#define NV90C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 - -#define NV90C0_SET_CTA_PROGRAM_START 0x03b4 -#define NV90C0_SET_CTA_PROGRAM_START_OFFSET 31:0 - -#define NV90C0_SET_FALCON00 0x0500 -#define NV90C0_SET_FALCON00_V 31:0 - -#define NV90C0_SET_FALCON01 0x0504 -#define NV90C0_SET_FALCON01_V 31:0 - -#define NV90C0_SET_FALCON02 0x0508 -#define NV90C0_SET_FALCON02_V 31:0 - -#define NV90C0_SET_FALCON03 0x050c -#define NV90C0_SET_FALCON03_V 31:0 - -#define NV90C0_SET_FALCON04 0x0510 -#define NV90C0_SET_FALCON04_V 31:0 - -#define NV90C0_SET_FALCON05 0x0514 -#define NV90C0_SET_FALCON05_V 31:0 - -#define NV90C0_SET_FALCON06 0x0518 -#define NV90C0_SET_FALCON06_V 31:0 - -#define NV90C0_SET_FALCON07 0x051c -#define NV90C0_SET_FALCON07_V 31:0 - -#define NV90C0_SET_FALCON08 0x0520 -#define NV90C0_SET_FALCON08_V 31:0 - -#define NV90C0_SET_FALCON09 0x0524 -#define NV90C0_SET_FALCON09_V 31:0 - -#define NV90C0_SET_FALCON10 0x0528 -#define NV90C0_SET_FALCON10_V 31:0 - -#define NV90C0_SET_FALCON11 0x052c -#define NV90C0_SET_FALCON11_V 31:0 - -#define NV90C0_SET_FALCON12 0x0530 -#define NV90C0_SET_FALCON12_V 31:0 - -#define NV90C0_SET_FALCON13 0x0534 -#define NV90C0_SET_FALCON13_V 31:0 - -#define NV90C0_SET_FALCON14 0x0538 -#define NV90C0_SET_FALCON14_V 31:0 - -#define NV90C0_SET_FALCON15 0x053c -#define NV90C0_SET_FALCON15_V 31:0 - -#define NV90C0_SET_FALCON16 0x0540 -#define NV90C0_SET_FALCON16_V 31:0 - -#define NV90C0_SET_FALCON17 0x0544 -#define NV90C0_SET_FALCON17_V 31:0 - -#define NV90C0_SET_FALCON18 0x0548 -#define NV90C0_SET_FALCON18_V 31:0 - -#define NV90C0_SET_FALCON19 0x054c -#define NV90C0_SET_FALCON19_V 31:0 - -#define NV90C0_SET_FALCON20 0x0550 -#define NV90C0_SET_FALCON20_V 31:0 - -#define NV90C0_SET_FALCON21 0x0554 -#define NV90C0_SET_FALCON21_V 31:0 - -#define NV90C0_SET_FALCON22 0x0558 -#define NV90C0_SET_FALCON22_V 31:0 - -#define NV90C0_SET_FALCON23 0x055c -#define NV90C0_SET_FALCON23_V 31:0 - -#define NV90C0_SET_FALCON24 0x0560 -#define NV90C0_SET_FALCON24_V 31:0 - -#define NV90C0_SET_FALCON25 0x0564 -#define NV90C0_SET_FALCON25_V 31:0 - -#define NV90C0_SET_FALCON26 0x0568 -#define NV90C0_SET_FALCON26_V 31:0 - -#define NV90C0_SET_FALCON27 0x056c -#define NV90C0_SET_FALCON27_V 31:0 - -#define NV90C0_SET_FALCON28 0x0570 -#define NV90C0_SET_FALCON28_V 31:0 - -#define NV90C0_SET_FALCON29 0x0574 -#define NV90C0_SET_FALCON29_V 31:0 - -#define NV90C0_SET_FALCON30 0x0578 -#define NV90C0_SET_FALCON30_V 31:0 - -#define NV90C0_SET_FALCON31 0x057c -#define NV90C0_SET_FALCON31_V 31:0 - -#define NV90C0_SET_MAX_SM_COUNT 0x0758 -#define NV90C0_SET_MAX_SM_COUNT_V 8:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NV90C0_SET_GRID_PARAM 0x0780 -#define NV90C0_SET_GRID_PARAM_V 31:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NV90C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NV90C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_C 0x0798 -#define NV90C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_D 0x079c -#define NV90C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 - -#define NV90C0_SET_SHADER_LOCAL_MEMORY_E 0x07a0 -#define NV90C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 - -#define NV90C0_END_GRID 0x0a04 -#define NV90C0_END_GRID_V 0:0 - -#define NV90C0_SET_LAUNCH_SIZE 0x0a08 -#define NV90C0_SET_LAUNCH_SIZE_V 31:0 - -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT 0x0d64 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA 3:0 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0 0x00000000 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1 0x00000001 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2 0x00000002 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4 0x00000003 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8 0x00000004 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16 0x00000005 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32 0x00000006 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64 0x00000007 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128 0x00000008 -#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK 0x0000000F - -#define NV90C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NV90C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NV90C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NV90C0_SET_SPARE_NOOP12 0x0f44 -#define NV90C0_SET_SPARE_NOOP12_V 31:0 - -#define NV90C0_SET_SPARE_NOOP13 0x0f48 -#define NV90C0_SET_SPARE_NOOP13_V 31:0 - -#define NV90C0_SET_SPARE_NOOP14 0x0f4c -#define NV90C0_SET_SPARE_NOOP14_V 31:0 - -#define NV90C0_SET_SPARE_NOOP15 0x0f50 -#define NV90C0_SET_SPARE_NOOP15_V 31:0 - -#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 -#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 -#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 -#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 - -#define NV90C0_SET_SPARE_NOOP00 0x1040 -#define NV90C0_SET_SPARE_NOOP00_V 31:0 - -#define NV90C0_SET_SPARE_NOOP01 0x1044 -#define NV90C0_SET_SPARE_NOOP01_V 31:0 - -#define NV90C0_SET_SPARE_NOOP02 0x1048 -#define NV90C0_SET_SPARE_NOOP02_V 31:0 - -#define NV90C0_SET_SPARE_NOOP03 0x104c -#define NV90C0_SET_SPARE_NOOP03_V 31:0 - -#define NV90C0_SET_SPARE_NOOP04 0x1050 -#define NV90C0_SET_SPARE_NOOP04_V 31:0 - -#define NV90C0_SET_SPARE_NOOP05 0x1054 -#define NV90C0_SET_SPARE_NOOP05_V 31:0 - -#define NV90C0_SET_SPARE_NOOP06 0x1058 -#define NV90C0_SET_SPARE_NOOP06_V 31:0 - -#define NV90C0_SET_SPARE_NOOP07 0x105c -#define NV90C0_SET_SPARE_NOOP07_V 31:0 - -#define NV90C0_SET_SPARE_NOOP08 0x1060 -#define NV90C0_SET_SPARE_NOOP08_V 31:0 - -#define NV90C0_SET_SPARE_NOOP09 0x1064 -#define NV90C0_SET_SPARE_NOOP09_V 31:0 - -#define NV90C0_SET_SPARE_NOOP10 0x1068 -#define NV90C0_SET_SPARE_NOOP10_V 31:0 - -#define NV90C0_SET_SPARE_NOOP11 0x106c -#define NV90C0_SET_SPARE_NOOP11_V 31:0 - -#define NV90C0_UNBIND_ALL 0x10f4 -#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS 0:0 -#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 -#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 -#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 -#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 -#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 -#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS 8:8 -#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 -#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 - -#define NV90C0_SET_SAMPLER_BINDING 0x1234 -#define NV90C0_SET_SAMPLER_BINDING_V 0:0 -#define NV90C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 -#define NV90C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 - -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NV90C0_SET_SHADER_SCHEDULING 0x12ac -#define NV90C0_SET_SHADER_SCHEDULING_MODE 0:0 -#define NV90C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 -#define NV90C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 - -#define NV90C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 -#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 - -#define NV90C0_SET_GLOBAL_COLOR_KEY 0x1354 -#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 -#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 -#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 - -#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NV90C0_PERFMON_TRANSFER 0x1524 -#define NV90C0_PERFMON_TRANSFER_V 31:0 - -#define NV90C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NV90C0_SET_RENDER_ENABLE_A 0x1550 -#define NV90C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NV90C0_SET_RENDER_ENABLE_B 0x1554 -#define NV90C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NV90C0_SET_RENDER_ENABLE_C 0x1558 -#define NV90C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NV90C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NV90C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NV90C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NV90C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NV90C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NV90C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NV90C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NV90C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NV90C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NV90C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NV90C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NV90C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NV90C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NV90C0_SET_TEX_HEADER_POOL_C 0x157c -#define NV90C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NV90C0_SET_PROGRAM_REGION_A 0x1608 -#define NV90C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 - -#define NV90C0_SET_PROGRAM_REGION_B 0x160c -#define NV90C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 -#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 -#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 -#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 -#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 -#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 - -#define NV90C0_SET_SHADER_CONTROL 0x1690 -#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 -#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 -#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 -#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 -#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 -#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 - -#define NV90C0_BIND_CONSTANT_BUFFER 0x1694 -#define NV90C0_BIND_CONSTANT_BUFFER_VALID 0:0 -#define NV90C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NV90C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NV90C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 12:8 - -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM 8:8 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE 0x00000001 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 -#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 -#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 -#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 - -#define NV90C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NV90C0_PIPE_NOP 0x1a2c -#define NV90C0_PIPE_NOP_V 31:0 - -#define NV90C0_SET_SPARE00 0x1a30 -#define NV90C0_SET_SPARE00_V 31:0 - -#define NV90C0_SET_SPARE01 0x1a34 -#define NV90C0_SET_SPARE01_V 31:0 - -#define NV90C0_SET_SPARE02 0x1a38 -#define NV90C0_SET_SPARE02_V 31:0 - -#define NV90C0_SET_SPARE03 0x1a3c -#define NV90C0_SET_SPARE03_V 31:0 - -#define NV90C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NV90C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NV90C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NV90C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NV90C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NV90C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NV90C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 - -#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 -#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 - -#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 -#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 - -#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 -#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 - -#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET 0x238c -#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 - -#define NV90C0_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) -#define NV90C0_LOAD_CONSTANT_BUFFER_V 31:0 - -#define NV90C0_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) -#define NV90C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 - -#define NV90C0_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) -#define NV90C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 - -#define NV90C0_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) -#define NV90C0_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 - -#define NV90C0_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) -#define NV90C0_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 -#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 -#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 -#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 - -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F -#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT 25:17 - -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 - -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 - -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NV90C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NV90C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#define NV90C0_CALL_MME_MACRO(j) (0x3800+(j)*8) -#define NV90C0_CALL_MME_MACRO_V 31:0 - -#define NV90C0_CALL_MME_DATA(j) (0x3804+(j)*8) -#define NV90C0_CALL_MME_DATA_V 31:0 - -#endif /* _cl_fermi_compute_a_h_ */ diff --git a/Compute-Class-Methods/cl91c0.h b/Compute-Class-Methods/cl91c0.h deleted file mode 100644 index b83f4aa..0000000 --- a/Compute-Class-Methods/cl91c0.h +++ /dev/null @@ -1,1049 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_fermi_compute_b_h_ -#define _cl_fermi_compute_b_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../class/bin/sw_header.pl fermi_compute_b */ - -#include "nvtypes.h" - -#define FERMI_COMPUTE_B 0x91C0 - -typedef volatile struct _cl91c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 LoadMmeInstructionRamPointer; - NvU32 LoadMmeInstructionRam; - NvU32 LoadMmeStartAddressRamPointer; - NvU32 LoadMmeStartAddressRam; - NvU32 SetMmeShadowRamControl; - NvU32 Reserved_0x128[0x2]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 Reserved_0x144[0x3]; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0x2B]; - NvU32 SetShaderLocalMemoryLowSize; - NvU32 SetShaderLocalMemoryHighSize; - NvU32 SetShaderLocalMemoryCrsSize; - NvU32 SetBindingControlTexture; - NvU32 SetShaderSharedMemoryWindow; - NvU32 Reserved_0x218[0x1]; - NvU32 InvalidateShaderCaches; - NvU32 Reserved_0x220[0x2]; - NvU32 BindTextureSampler; - NvU32 BindTextureHeader; - NvU32 BindExtraTextureSampler; - NvU32 BindExtraTextureHeader; - NvU32 SetCtaRasterSizeA; - NvU32 SetCtaRasterSizeB; - NvU32 Reserved_0x240[0x1]; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 Reserved_0x248[0x1]; - NvU32 SetShaderSharedMemorySize; - NvU32 SetCtaThreadCount; - NvU32 SetCtaBarrierCount; - NvU32 Reserved_0x258[0xD]; - NvU32 TestForCompute; - NvU32 Reserved_0x290[0x3]; - NvU32 BeginGrid; - NvU32 SetWorkDistribution; - NvU32 Reserved_0x2A4[0x7]; - NvU32 SetCtaRegisterCount; - NvU32 SetGaToVaMappingMode; - NvU32 LoadGaToVaMappingEntry; - NvU32 Reserved_0x2CC[0x5]; - NvU32 SetTexHeaderExtendedDimensions; - NvU32 Reserved_0x2E4[0x9]; - NvU32 SetL1Configuration; - NvU32 SetRenderEnableControl; - NvU32 Reserved_0x310[0x14]; - NvU32 WaitRefCount; - NvU32 Reserved_0x364[0x1]; - NvU32 Launch; - NvU32 SetLaunchId; - NvU32 Reserved_0x370[0xF]; - NvU32 SetCtaThreadDimensionA; - NvU32 SetCtaThreadDimensionB; - NvU32 SetCtaProgramStart; - NvU32 Reserved_0x3B8[0x52]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x76]; - NvU32 SetMaxSmCount; - NvU32 Reserved_0x75C[0x8]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 SetGridParam; - NvU32 Reserved_0x784[0x3]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 SetShaderLocalMemoryC; - NvU32 SetShaderLocalMemoryD; - NvU32 SetShaderLocalMemoryE; - NvU32 Reserved_0x7A4[0x98]; - NvU32 EndGrid; - NvU32 SetLaunchSize; - NvU32 Reserved_0xA0C[0xD6]; - NvU32 SetApiVisibleCallLimit; - NvU32 Reserved_0xD68[0xB]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x2C]; - NvU32 SetForceOneTextureUnit; - NvU32 Reserved_0x1008[0xE]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x21]; - NvU32 UnbindAll; - NvU32 Reserved_0x10F8[0x4F]; - NvU32 SetSamplerBinding; - NvU32 Reserved_0x1238[0x14]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x8]; - NvU32 SetShaderScheduling; - NvU32 Reserved_0x12B0[0x20]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x6]; - NvU32 SetGlobalColorKey; - NvU32 Reserved_0x1358[0x33]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x3F]; - NvU32 PerfmonTransfer; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x15]; - NvU32 SetCubemapInterFaceFiltering; - NvU32 Reserved_0x1668[0xA]; - NvU32 SetShaderControl; - NvU32 BindConstantBuffer; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xA5]; - NvU32 InvalidateConstantBufferCache; - NvU32 Reserved_0x1934[0x4]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x21C]; - NvU32 SetConstantBufferSelectorA; - NvU32 SetConstantBufferSelectorB; - NvU32 SetConstantBufferSelectorC; - NvU32 LoadConstantBufferOffset; - NvU32 LoadConstantBuffer[0x10]; - NvU32 Reserved_0x23D0[0xCC]; - struct { - NvU32 A; - NvU32 B; - NvU32 C; - NvU32 D; - NvU32 Format; - NvU32 BlockSize; - NvU32 Reserved_0x18[0x2]; - } SetSuLdStTarget[0x8]; - NvU32 Reserved_0x2800[0x2D7]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 Reserved_0x33E0[0x8]; - NvU32 SetMmeShadowScratch[0x80]; - NvU32 Reserved_0x3600[0x80]; - struct { - NvU32 Macro; - NvU32 Data; - } CallMme[0x80]; -} fermi_compute_b_t; - - -#define NV91C0_SET_OBJECT 0x0000 -#define NV91C0_SET_OBJECT_CLASS_ID 15:0 -#define NV91C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NV91C0_NO_OPERATION 0x0100 -#define NV91C0_NO_OPERATION_V 31:0 - -#define NV91C0_SET_NOTIFY_A 0x0104 -#define NV91C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NV91C0_SET_NOTIFY_B 0x0108 -#define NV91C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NV91C0_NOTIFY 0x010c -#define NV91C0_NOTIFY_TYPE 31:0 -#define NV91C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NV91C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NV91C0_WAIT_FOR_IDLE 0x0110 -#define NV91C0_WAIT_FOR_IDLE_V 31:0 - -#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 -#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 - -#define NV91C0_LOAD_MME_INSTRUCTION_RAM 0x0118 -#define NV91C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 - -#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c -#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 - -#define NV91C0_LOAD_MME_START_ADDRESS_RAM 0x0120 -#define NV91C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 - -#define NV91C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 -#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 -#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 -#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 -#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 -#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 - -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NV91C0_SEND_GO_IDLE 0x013c -#define NV91C0_SEND_GO_IDLE_V 31:0 - -#define NV91C0_PM_TRIGGER 0x0140 -#define NV91C0_PM_TRIGGER_V 31:0 - -#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE 0x0204 -#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V 23:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE 0x0208 -#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V 23:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE 0x020c -#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V 20:0 - -#define NV91C0_SET_BINDING_CONTROL_TEXTURE 0x0210 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 -#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 - -#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NV91C0_INVALIDATE_SHADER_CACHES 0x021c -#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 -#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NV91C0_BIND_TEXTURE_SAMPLER 0x0228 -#define NV91C0_BIND_TEXTURE_SAMPLER_VALID 0:0 -#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 -#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 -#define NV91C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 -#define NV91C0_BIND_TEXTURE_SAMPLER_INDEX 24:12 - -#define NV91C0_BIND_TEXTURE_HEADER 0x022c -#define NV91C0_BIND_TEXTURE_HEADER_VALID 0:0 -#define NV91C0_BIND_TEXTURE_HEADER_VALID_FALSE 0x00000000 -#define NV91C0_BIND_TEXTURE_HEADER_VALID_TRUE 0x00000001 -#define NV91C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT 8:1 -#define NV91C0_BIND_TEXTURE_HEADER_INDEX 30:9 - -#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER 0x0230 -#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID 0:0 -#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 -#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 -#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 -#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 - -#define NV91C0_BIND_EXTRA_TEXTURE_HEADER 0x0234 -#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID 0:0 -#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 -#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 -#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 -#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_INDEX 30:9 - -#define NV91C0_SET_CTA_RASTER_SIZE_A 0x0238 -#define NV91C0_SET_CTA_RASTER_SIZE_A_WIDTH 15:0 -#define NV91C0_SET_CTA_RASTER_SIZE_A_HEIGHT 31:16 - -#define NV91C0_SET_CTA_RASTER_SIZE_B 0x023c -#define NV91C0_SET_CTA_RASTER_SIZE_B_DEPTH 15:0 -#define NV91C0_SET_CTA_RASTER_SIZE_B_WIDTH_UPPER 31:16 - -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE 0x024c -#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE_V 17:0 - -#define NV91C0_SET_CTA_THREAD_COUNT 0x0250 -#define NV91C0_SET_CTA_THREAD_COUNT_V 15:0 - -#define NV91C0_SET_CTA_BARRIER_COUNT 0x0254 -#define NV91C0_SET_CTA_BARRIER_COUNT_V 7:0 - -#define NV91C0_TEST_FOR_COMPUTE 0x028c -#define NV91C0_TEST_FOR_COMPUTE_V 31:0 - -#define NV91C0_BEGIN_GRID 0x029c -#define NV91C0_BEGIN_GRID_V 0:0 - -#define NV91C0_SET_WORK_DISTRIBUTION 0x02a0 -#define NV91C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE 16:13 -#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE 4:4 -#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE 0x00000000 -#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE 0x00000001 -#define NV91C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS 12:5 - -#define NV91C0_SET_CTA_REGISTER_COUNT 0x02c0 -#define NV91C0_SET_CTA_REGISTER_COUNT_V 7:0 - -#define NV91C0_SET_GA_TO_VA_MAPPING_MODE 0x02c4 -#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V 0:0 -#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 -#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 - -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 -#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 - -#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS 0x02e0 -#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE 0:0 -#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_FALSE 0x00000000 -#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_TRUE 0x00000001 - -#define NV91C0_SET_L1_CONFIGURATION 0x0308 -#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 -#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 -#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 -#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 - -#define NV91C0_SET_RENDER_ENABLE_CONTROL 0x030c -#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 -#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 -#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 - -#define NV91C0_WAIT_REF_COUNT 0x0360 -#define NV91C0_WAIT_REF_COUNT_REF_CNT 11:8 -#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM 0:0 -#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE 0x00000000 -#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE 0x00000001 - -#define NV91C0_LAUNCH 0x0368 -#define NV91C0_LAUNCHCTA_PARAM 31:0 - -#define NV91C0_SET_LAUNCH_ID 0x036c -#define NV91C0_SET_LAUNCH_ID_REF_CNT 3:0 - -#define NV91C0_SET_CTA_THREAD_DIMENSION_A 0x03ac -#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 -#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 - -#define NV91C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 -#define NV91C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 - -#define NV91C0_SET_CTA_PROGRAM_START 0x03b4 -#define NV91C0_SET_CTA_PROGRAM_START_OFFSET 31:0 - -#define NV91C0_SET_FALCON00 0x0500 -#define NV91C0_SET_FALCON00_V 31:0 - -#define NV91C0_SET_FALCON01 0x0504 -#define NV91C0_SET_FALCON01_V 31:0 - -#define NV91C0_SET_FALCON02 0x0508 -#define NV91C0_SET_FALCON02_V 31:0 - -#define NV91C0_SET_FALCON03 0x050c -#define NV91C0_SET_FALCON03_V 31:0 - -#define NV91C0_SET_FALCON04 0x0510 -#define NV91C0_SET_FALCON04_V 31:0 - -#define NV91C0_SET_FALCON05 0x0514 -#define NV91C0_SET_FALCON05_V 31:0 - -#define NV91C0_SET_FALCON06 0x0518 -#define NV91C0_SET_FALCON06_V 31:0 - -#define NV91C0_SET_FALCON07 0x051c -#define NV91C0_SET_FALCON07_V 31:0 - -#define NV91C0_SET_FALCON08 0x0520 -#define NV91C0_SET_FALCON08_V 31:0 - -#define NV91C0_SET_FALCON09 0x0524 -#define NV91C0_SET_FALCON09_V 31:0 - -#define NV91C0_SET_FALCON10 0x0528 -#define NV91C0_SET_FALCON10_V 31:0 - -#define NV91C0_SET_FALCON11 0x052c -#define NV91C0_SET_FALCON11_V 31:0 - -#define NV91C0_SET_FALCON12 0x0530 -#define NV91C0_SET_FALCON12_V 31:0 - -#define NV91C0_SET_FALCON13 0x0534 -#define NV91C0_SET_FALCON13_V 31:0 - -#define NV91C0_SET_FALCON14 0x0538 -#define NV91C0_SET_FALCON14_V 31:0 - -#define NV91C0_SET_FALCON15 0x053c -#define NV91C0_SET_FALCON15_V 31:0 - -#define NV91C0_SET_FALCON16 0x0540 -#define NV91C0_SET_FALCON16_V 31:0 - -#define NV91C0_SET_FALCON17 0x0544 -#define NV91C0_SET_FALCON17_V 31:0 - -#define NV91C0_SET_FALCON18 0x0548 -#define NV91C0_SET_FALCON18_V 31:0 - -#define NV91C0_SET_FALCON19 0x054c -#define NV91C0_SET_FALCON19_V 31:0 - -#define NV91C0_SET_FALCON20 0x0550 -#define NV91C0_SET_FALCON20_V 31:0 - -#define NV91C0_SET_FALCON21 0x0554 -#define NV91C0_SET_FALCON21_V 31:0 - -#define NV91C0_SET_FALCON22 0x0558 -#define NV91C0_SET_FALCON22_V 31:0 - -#define NV91C0_SET_FALCON23 0x055c -#define NV91C0_SET_FALCON23_V 31:0 - -#define NV91C0_SET_FALCON24 0x0560 -#define NV91C0_SET_FALCON24_V 31:0 - -#define NV91C0_SET_FALCON25 0x0564 -#define NV91C0_SET_FALCON25_V 31:0 - -#define NV91C0_SET_FALCON26 0x0568 -#define NV91C0_SET_FALCON26_V 31:0 - -#define NV91C0_SET_FALCON27 0x056c -#define NV91C0_SET_FALCON27_V 31:0 - -#define NV91C0_SET_FALCON28 0x0570 -#define NV91C0_SET_FALCON28_V 31:0 - -#define NV91C0_SET_FALCON29 0x0574 -#define NV91C0_SET_FALCON29_V 31:0 - -#define NV91C0_SET_FALCON30 0x0578 -#define NV91C0_SET_FALCON30_V 31:0 - -#define NV91C0_SET_FALCON31 0x057c -#define NV91C0_SET_FALCON31_V 31:0 - -#define NV91C0_SET_MAX_SM_COUNT 0x0758 -#define NV91C0_SET_MAX_SM_COUNT_V 8:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NV91C0_SET_GRID_PARAM 0x0780 -#define NV91C0_SET_GRID_PARAM_V 31:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NV91C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NV91C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_C 0x0798 -#define NV91C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_D 0x079c -#define NV91C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 - -#define NV91C0_SET_SHADER_LOCAL_MEMORY_E 0x07a0 -#define NV91C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 - -#define NV91C0_END_GRID 0x0a04 -#define NV91C0_END_GRID_V 0:0 - -#define NV91C0_SET_LAUNCH_SIZE 0x0a08 -#define NV91C0_SET_LAUNCH_SIZE_V 31:0 - -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT 0x0d64 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA 3:0 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0 0x00000000 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1 0x00000001 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2 0x00000002 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4 0x00000003 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8 0x00000004 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16 0x00000005 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32 0x00000006 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64 0x00000007 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128 0x00000008 -#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK 0x0000000F - -#define NV91C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NV91C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NV91C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NV91C0_SET_SPARE_NOOP12 0x0f44 -#define NV91C0_SET_SPARE_NOOP12_V 31:0 - -#define NV91C0_SET_SPARE_NOOP13 0x0f48 -#define NV91C0_SET_SPARE_NOOP13_V 31:0 - -#define NV91C0_SET_SPARE_NOOP14 0x0f4c -#define NV91C0_SET_SPARE_NOOP14_V 31:0 - -#define NV91C0_SET_SPARE_NOOP15 0x0f50 -#define NV91C0_SET_SPARE_NOOP15_V 31:0 - -#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 -#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 -#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 -#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 - -#define NV91C0_SET_SPARE_NOOP00 0x1040 -#define NV91C0_SET_SPARE_NOOP00_V 31:0 - -#define NV91C0_SET_SPARE_NOOP01 0x1044 -#define NV91C0_SET_SPARE_NOOP01_V 31:0 - -#define NV91C0_SET_SPARE_NOOP02 0x1048 -#define NV91C0_SET_SPARE_NOOP02_V 31:0 - -#define NV91C0_SET_SPARE_NOOP03 0x104c -#define NV91C0_SET_SPARE_NOOP03_V 31:0 - -#define NV91C0_SET_SPARE_NOOP04 0x1050 -#define NV91C0_SET_SPARE_NOOP04_V 31:0 - -#define NV91C0_SET_SPARE_NOOP05 0x1054 -#define NV91C0_SET_SPARE_NOOP05_V 31:0 - -#define NV91C0_SET_SPARE_NOOP06 0x1058 -#define NV91C0_SET_SPARE_NOOP06_V 31:0 - -#define NV91C0_SET_SPARE_NOOP07 0x105c -#define NV91C0_SET_SPARE_NOOP07_V 31:0 - -#define NV91C0_SET_SPARE_NOOP08 0x1060 -#define NV91C0_SET_SPARE_NOOP08_V 31:0 - -#define NV91C0_SET_SPARE_NOOP09 0x1064 -#define NV91C0_SET_SPARE_NOOP09_V 31:0 - -#define NV91C0_SET_SPARE_NOOP10 0x1068 -#define NV91C0_SET_SPARE_NOOP10_V 31:0 - -#define NV91C0_SET_SPARE_NOOP11 0x106c -#define NV91C0_SET_SPARE_NOOP11_V 31:0 - -#define NV91C0_UNBIND_ALL 0x10f4 -#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS 0:0 -#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 -#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 -#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 -#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 -#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 -#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS 8:8 -#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 -#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 - -#define NV91C0_SET_SAMPLER_BINDING 0x1234 -#define NV91C0_SET_SAMPLER_BINDING_V 0:0 -#define NV91C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 -#define NV91C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 - -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NV91C0_SET_SHADER_SCHEDULING 0x12ac -#define NV91C0_SET_SHADER_SCHEDULING_MODE 0:0 -#define NV91C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 -#define NV91C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 - -#define NV91C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 -#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 - -#define NV91C0_SET_GLOBAL_COLOR_KEY 0x1354 -#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 -#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 -#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 - -#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NV91C0_PERFMON_TRANSFER 0x1524 -#define NV91C0_PERFMON_TRANSFER_V 31:0 - -#define NV91C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NV91C0_SET_RENDER_ENABLE_A 0x1550 -#define NV91C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NV91C0_SET_RENDER_ENABLE_B 0x1554 -#define NV91C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NV91C0_SET_RENDER_ENABLE_C 0x1558 -#define NV91C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NV91C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NV91C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NV91C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NV91C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NV91C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NV91C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NV91C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NV91C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NV91C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NV91C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NV91C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NV91C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NV91C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NV91C0_SET_TEX_HEADER_POOL_C 0x157c -#define NV91C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NV91C0_SET_PROGRAM_REGION_A 0x1608 -#define NV91C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 - -#define NV91C0_SET_PROGRAM_REGION_B 0x160c -#define NV91C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 -#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 -#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 -#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 -#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 -#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 - -#define NV91C0_SET_SHADER_CONTROL 0x1690 -#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 -#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 -#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 -#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 -#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 -#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 -#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 -#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 -#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 -#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 -#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 -#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 - -#define NV91C0_BIND_CONSTANT_BUFFER 0x1694 -#define NV91C0_BIND_CONSTANT_BUFFER_VALID 0:0 -#define NV91C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NV91C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NV91C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 12:8 - -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM 8:8 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE 0x00000001 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 -#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 -#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 -#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 - -#define NV91C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NV91C0_PIPE_NOP 0x1a2c -#define NV91C0_PIPE_NOP_V 31:0 - -#define NV91C0_SET_SPARE00 0x1a30 -#define NV91C0_SET_SPARE00_V 31:0 - -#define NV91C0_SET_SPARE01 0x1a34 -#define NV91C0_SET_SPARE01_V 31:0 - -#define NV91C0_SET_SPARE02 0x1a38 -#define NV91C0_SET_SPARE02_V 31:0 - -#define NV91C0_SET_SPARE03 0x1a3c -#define NV91C0_SET_SPARE03_V 31:0 - -#define NV91C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NV91C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NV91C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NV91C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NV91C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NV91C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NV91C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 - -#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 -#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 - -#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 -#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 - -#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 -#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 - -#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET 0x238c -#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 - -#define NV91C0_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) -#define NV91C0_LOAD_CONSTANT_BUFFER_V 31:0 - -#define NV91C0_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) -#define NV91C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 - -#define NV91C0_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) -#define NV91C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 - -#define NV91C0_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) -#define NV91C0_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 - -#define NV91C0_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) -#define NV91C0_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 -#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 -#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 -#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 - -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_B8G8R8A8 0x00000047 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F -#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT 25:17 - -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 - -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 - -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NV91C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NV91C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#define NV91C0_CALL_MME_MACRO(j) (0x3800+(j)*8) -#define NV91C0_CALL_MME_MACRO_V 31:0 - -#define NV91C0_CALL_MME_DATA(j) (0x3804+(j)*8) -#define NV91C0_CALL_MME_DATA_V 31:0 - -#endif /* _cl_fermi_compute_b_h_ */ diff --git a/Compute-Class-Methods/cla0c0.h b/Compute-Class-Methods/cla0c0.h deleted file mode 100644 index e8677ad..0000000 --- a/Compute-Class-Methods/cla0c0.h +++ /dev/null @@ -1,836 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_kepler_compute_a_h_ -#define _cl_kepler_compute_a_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../class/bin/sw_header.pl kepler_compute_a */ - -#include "nvtypes.h" - -#define KEPLER_COMPUTE_A 0xA0C0 - -typedef volatile struct _cla0c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 Reserved_0x148[0x2]; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 Reserved_0x1E8[0x2]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 Reserved_0x200[0x4]; - NvU32 PerfmonTransfer; - NvU32 SetShaderSharedMemoryWindow; - NvU32 Reserved_0x218[0x1]; - NvU32 InvalidateShaderCaches; - NvU32 Reserved_0x220[0x8]; - NvU32 SetCwdControl; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 Reserved_0x24C[0xA]; - NvU32 InvalidateConstantBufferCacheA; - NvU32 InvalidateConstantBufferCacheB; - NvU32 InvalidateConstantBufferCacheC; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 Reserved_0x28C[0x1]; - NvU32 CheckQmdVersion; - NvU32 Reserved_0x294[0x7]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x9]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 SetShaderLocalMemoryThrottledA; - NvU32 SetShaderLocalMemoryThrottledB; - NvU32 SetShaderLocalMemoryThrottledC; - NvU32 Reserved_0x2FC[0x5]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x7B]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x7F]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 Reserved_0x780[0x4]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x17F]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x3B]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x86]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x29]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x20]; - NvU32 SetShaderControl; - NvU32 Reserved_0x1694[0x1]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BE]; - NvU32 SetBindlessTexture; - NvU32 SetTrapHandler; - NvU32 Reserved_0x2610[0x353]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 Reserved_0x33E0[0x8]; - NvU32 SetMmeShadowScratch[0x8]; -} kepler_compute_a_t; - - -#define NVA0C0_SET_OBJECT 0x0000 -#define NVA0C0_SET_OBJECT_CLASS_ID 15:0 -#define NVA0C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVA0C0_NO_OPERATION 0x0100 -#define NVA0C0_NO_OPERATION_V 31:0 - -#define NVA0C0_SET_NOTIFY_A 0x0104 -#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVA0C0_SET_NOTIFY_B 0x0108 -#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVA0C0_NOTIFY 0x010c -#define NVA0C0_NOTIFY_TYPE 31:0 -#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVA0C0_WAIT_FOR_IDLE 0x0110 -#define NVA0C0_WAIT_FOR_IDLE_V 31:0 - -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVA0C0_SEND_GO_IDLE 0x013c -#define NVA0C0_SEND_GO_IDLE_V 31:0 - -#define NVA0C0_PM_TRIGGER 0x0140 -#define NVA0C0_PM_TRIGGER_V 31:0 - -#define NVA0C0_PM_TRIGGER_WFI 0x0144 -#define NVA0C0_PM_TRIGGER_WFI_V 31:0 - -#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVA0C0_LINE_LENGTH_IN 0x0180 -#define NVA0C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVA0C0_LINE_COUNT 0x0184 -#define NVA0C0_LINE_COUNT_VALUE 31:0 - -#define NVA0C0_OFFSET_OUT_UPPER 0x0188 -#define NVA0C0_OFFSET_OUT_UPPER_VALUE 7:0 - -#define NVA0C0_OFFSET_OUT 0x018c -#define NVA0C0_OFFSET_OUT_VALUE 31:0 - -#define NVA0C0_PITCH_OUT 0x0190 -#define NVA0C0_PITCH_OUT_VALUE 31:0 - -#define NVA0C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVA0C0_SET_DST_WIDTH 0x0198 -#define NVA0C0_SET_DST_WIDTH_V 31:0 - -#define NVA0C0_SET_DST_HEIGHT 0x019c -#define NVA0C0_SET_DST_HEIGHT_V 31:0 - -#define NVA0C0_SET_DST_DEPTH 0x01a0 -#define NVA0C0_SET_DST_DEPTH_V 31:0 - -#define NVA0C0_SET_DST_LAYER 0x01a4 -#define NVA0C0_SET_DST_LAYER_V 31:0 - -#define NVA0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 - -#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 - -#define NVA0C0_LAUNCH_DMA 0x01b0 -#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVA0C0_LOAD_INLINE_DATA 0x01b4 -#define NVA0C0_LOAD_INLINE_DATA_V 31:0 - -#define NVA0C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVA0C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVA0C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVA0C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVA0C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVA0C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVA0C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVA0C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVA0C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVA0C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVA0C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVA0C0_PERFMON_TRANSFER 0x0210 -#define NVA0C0_PERFMON_TRANSFER_V 31:0 - -#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVA0C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVA0C0_SET_CWD_CONTROL 0x0240 -#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 -#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 -#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 - -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVA0C0_SET_CWD_REF_COUNTER 0x0248 -#define NVA0C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVA0C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 - -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 - -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 - -#define NVA0C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA0C0_SET_QMD_VERSION 0x0288 -#define NVA0C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA0C0_CHECK_QMD_VERSION 0x0290 -#define NVA0C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA0C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVA0C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVA0C0_SEND_PCAS_A 0x02b4 -#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVA0C0_SEND_PCAS_B 0x02b8 -#define NVA0C0_SEND_PCAS_B_FROM 23:0 -#define NVA0C0_SEND_PCAS_B_DELTA 31:24 - -#define NVA0C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVA0C0_SET_SPA_VERSION 0x0310 -#define NVA0C0_SET_SPA_VERSION_MINOR 7:0 -#define NVA0C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVA0C0_SET_FALCON00 0x0500 -#define NVA0C0_SET_FALCON00_V 31:0 - -#define NVA0C0_SET_FALCON01 0x0504 -#define NVA0C0_SET_FALCON01_V 31:0 - -#define NVA0C0_SET_FALCON02 0x0508 -#define NVA0C0_SET_FALCON02_V 31:0 - -#define NVA0C0_SET_FALCON03 0x050c -#define NVA0C0_SET_FALCON03_V 31:0 - -#define NVA0C0_SET_FALCON04 0x0510 -#define NVA0C0_SET_FALCON04_V 31:0 - -#define NVA0C0_SET_FALCON05 0x0514 -#define NVA0C0_SET_FALCON05_V 31:0 - -#define NVA0C0_SET_FALCON06 0x0518 -#define NVA0C0_SET_FALCON06_V 31:0 - -#define NVA0C0_SET_FALCON07 0x051c -#define NVA0C0_SET_FALCON07_V 31:0 - -#define NVA0C0_SET_FALCON08 0x0520 -#define NVA0C0_SET_FALCON08_V 31:0 - -#define NVA0C0_SET_FALCON09 0x0524 -#define NVA0C0_SET_FALCON09_V 31:0 - -#define NVA0C0_SET_FALCON10 0x0528 -#define NVA0C0_SET_FALCON10_V 31:0 - -#define NVA0C0_SET_FALCON11 0x052c -#define NVA0C0_SET_FALCON11_V 31:0 - -#define NVA0C0_SET_FALCON12 0x0530 -#define NVA0C0_SET_FALCON12_V 31:0 - -#define NVA0C0_SET_FALCON13 0x0534 -#define NVA0C0_SET_FALCON13_V 31:0 - -#define NVA0C0_SET_FALCON14 0x0538 -#define NVA0C0_SET_FALCON14_V 31:0 - -#define NVA0C0_SET_FALCON15 0x053c -#define NVA0C0_SET_FALCON15_V 31:0 - -#define NVA0C0_SET_FALCON16 0x0540 -#define NVA0C0_SET_FALCON16_V 31:0 - -#define NVA0C0_SET_FALCON17 0x0544 -#define NVA0C0_SET_FALCON17_V 31:0 - -#define NVA0C0_SET_FALCON18 0x0548 -#define NVA0C0_SET_FALCON18_V 31:0 - -#define NVA0C0_SET_FALCON19 0x054c -#define NVA0C0_SET_FALCON19_V 31:0 - -#define NVA0C0_SET_FALCON20 0x0550 -#define NVA0C0_SET_FALCON20_V 31:0 - -#define NVA0C0_SET_FALCON21 0x0554 -#define NVA0C0_SET_FALCON21_V 31:0 - -#define NVA0C0_SET_FALCON22 0x0558 -#define NVA0C0_SET_FALCON22_V 31:0 - -#define NVA0C0_SET_FALCON23 0x055c -#define NVA0C0_SET_FALCON23_V 31:0 - -#define NVA0C0_SET_FALCON24 0x0560 -#define NVA0C0_SET_FALCON24_V 31:0 - -#define NVA0C0_SET_FALCON25 0x0564 -#define NVA0C0_SET_FALCON25_V 31:0 - -#define NVA0C0_SET_FALCON26 0x0568 -#define NVA0C0_SET_FALCON26_V 31:0 - -#define NVA0C0_SET_FALCON27 0x056c -#define NVA0C0_SET_FALCON27_V 31:0 - -#define NVA0C0_SET_FALCON28 0x0570 -#define NVA0C0_SET_FALCON28_V 31:0 - -#define NVA0C0_SET_FALCON29 0x0574 -#define NVA0C0_SET_FALCON29_V 31:0 - -#define NVA0C0_SET_FALCON30 0x0578 -#define NVA0C0_SET_FALCON30_V 31:0 - -#define NVA0C0_SET_FALCON31 0x057c -#define NVA0C0_SET_FALCON31_V 31:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 - -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVA0C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVA0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVA0C0_SET_SPARE_NOOP12 0x0f44 -#define NVA0C0_SET_SPARE_NOOP12_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP13 0x0f48 -#define NVA0C0_SET_SPARE_NOOP13_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP14 0x0f4c -#define NVA0C0_SET_SPARE_NOOP14_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP15 0x0f50 -#define NVA0C0_SET_SPARE_NOOP15_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP00 0x1040 -#define NVA0C0_SET_SPARE_NOOP00_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP01 0x1044 -#define NVA0C0_SET_SPARE_NOOP01_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP02 0x1048 -#define NVA0C0_SET_SPARE_NOOP02_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP03 0x104c -#define NVA0C0_SET_SPARE_NOOP03_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP04 0x1050 -#define NVA0C0_SET_SPARE_NOOP04_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP05 0x1054 -#define NVA0C0_SET_SPARE_NOOP05_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP06 0x1058 -#define NVA0C0_SET_SPARE_NOOP06_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP07 0x105c -#define NVA0C0_SET_SPARE_NOOP07_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP08 0x1060 -#define NVA0C0_SET_SPARE_NOOP08_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP09 0x1064 -#define NVA0C0_SET_SPARE_NOOP09_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP10 0x1068 -#define NVA0C0_SET_SPARE_NOOP10_V 31:0 - -#define NVA0C0_SET_SPARE_NOOP11 0x106c -#define NVA0C0_SET_SPARE_NOOP11_V 31:0 - -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVA0C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVA0C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVA0C0_SET_RENDER_ENABLE_A 0x1550 -#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVA0C0_SET_RENDER_ENABLE_B 0x1554 -#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVA0C0_SET_RENDER_ENABLE_C 0x1558 -#define NVA0C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVA0C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NVA0C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVA0C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVA0C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NVA0C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVA0C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVA0C0_SET_PROGRAM_REGION_A 0x1608 -#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 - -#define NVA0C0_SET_PROGRAM_REGION_B 0x160c -#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NVA0C0_SET_SHADER_CONTROL 0x1690 -#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 -#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 -#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 - -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVA0C0_PIPE_NOP 0x1a2c -#define NVA0C0_PIPE_NOP_V 31:0 - -#define NVA0C0_SET_SPARE00 0x1a30 -#define NVA0C0_SET_SPARE00_V 31:0 - -#define NVA0C0_SET_SPARE01 0x1a34 -#define NVA0C0_SET_SPARE01_V 31:0 - -#define NVA0C0_SET_SPARE02 0x1a38 -#define NVA0C0_SET_SPARE02_V 31:0 - -#define NVA0C0_SET_SPARE03 0x1a3c -#define NVA0C0_SET_SPARE03_V 31:0 - -#define NVA0C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVA0C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVA0C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVA0C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 - -#define NVA0C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVA0C0_SET_TRAP_HANDLER 0x260c -#define NVA0C0_SET_TRAP_HANDLER_OFFSET 31:0 - -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVA0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVA0C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_kepler_compute_a_h_ */ diff --git a/Compute-Class-Methods/cla1c0.h b/Compute-Class-Methods/cla1c0.h deleted file mode 100644 index 37462b1..0000000 --- a/Compute-Class-Methods/cla1c0.h +++ /dev/null @@ -1,866 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_kepler_compute_b_h_ -#define _cl_kepler_compute_b_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../class/bin/sw_header.pl kepler_compute_b */ - -#include "nvtypes.h" - -#define KEPLER_COMPUTE_B 0xA1C0 - -typedef volatile struct _cla1c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 Reserved_0x148[0x2]; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 Reserved_0x1E8[0x2]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 SetValidSpanOverflowAreaA; - NvU32 SetValidSpanOverflowAreaB; - NvU32 SetValidSpanOverflowAreaC; - NvU32 SetCoalesceWaitingPeriodUnit; - NvU32 PerfmonTransfer; - NvU32 SetShaderSharedMemoryWindow; - NvU32 Reserved_0x218[0x1]; - NvU32 InvalidateShaderCaches; - NvU32 Reserved_0x220[0x8]; - NvU32 SetCwdControl; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 Reserved_0x24C[0xA]; - NvU32 InvalidateConstantBufferCacheA; - NvU32 InvalidateConstantBufferCacheB; - NvU32 InvalidateConstantBufferCacheC; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 Reserved_0x28C[0x1]; - NvU32 CheckQmdVersion; - NvU32 Reserved_0x294[0x7]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x1]; - NvU32 SetGlobalLoadViaTexture; - NvU32 Reserved_0x2C8[0x7]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 SetShaderLocalMemoryThrottledA; - NvU32 SetShaderLocalMemoryThrottledB; - NvU32 SetShaderLocalMemoryThrottledC; - NvU32 Reserved_0x2FC[0x5]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x7B]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x7F]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 Reserved_0x780[0x4]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x17F]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x3B]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x86]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x7]; - NvU32 ActivatePerfSettingsForComputeContext; - NvU32 Reserved_0x12AC[0x21]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x20]; - NvU32 SetShaderControl; - NvU32 Reserved_0x1694[0x1]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BE]; - NvU32 SetBindlessTexture; - NvU32 SetTrapHandler; - NvU32 Reserved_0x2610[0x353]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 Reserved_0x33E0[0x8]; - NvU32 SetMmeShadowScratch[0x8]; -} kepler_compute_b_t; - - -#define NVA1C0_SET_OBJECT 0x0000 -#define NVA1C0_SET_OBJECT_CLASS_ID 15:0 -#define NVA1C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVA1C0_NO_OPERATION 0x0100 -#define NVA1C0_NO_OPERATION_V 31:0 - -#define NVA1C0_SET_NOTIFY_A 0x0104 -#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVA1C0_SET_NOTIFY_B 0x0108 -#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVA1C0_NOTIFY 0x010c -#define NVA1C0_NOTIFY_TYPE 31:0 -#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVA1C0_WAIT_FOR_IDLE 0x0110 -#define NVA1C0_WAIT_FOR_IDLE_V 31:0 - -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVA1C0_SEND_GO_IDLE 0x013c -#define NVA1C0_SEND_GO_IDLE_V 31:0 - -#define NVA1C0_PM_TRIGGER 0x0140 -#define NVA1C0_PM_TRIGGER_V 31:0 - -#define NVA1C0_PM_TRIGGER_WFI 0x0144 -#define NVA1C0_PM_TRIGGER_WFI_V 31:0 - -#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVA1C0_LINE_LENGTH_IN 0x0180 -#define NVA1C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVA1C0_LINE_COUNT 0x0184 -#define NVA1C0_LINE_COUNT_VALUE 31:0 - -#define NVA1C0_OFFSET_OUT_UPPER 0x0188 -#define NVA1C0_OFFSET_OUT_UPPER_VALUE 7:0 - -#define NVA1C0_OFFSET_OUT 0x018c -#define NVA1C0_OFFSET_OUT_VALUE 31:0 - -#define NVA1C0_PITCH_OUT 0x0190 -#define NVA1C0_PITCH_OUT_VALUE 31:0 - -#define NVA1C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVA1C0_SET_DST_WIDTH 0x0198 -#define NVA1C0_SET_DST_WIDTH_V 31:0 - -#define NVA1C0_SET_DST_HEIGHT 0x019c -#define NVA1C0_SET_DST_HEIGHT_V 31:0 - -#define NVA1C0_SET_DST_DEPTH 0x01a0 -#define NVA1C0_SET_DST_DEPTH_V 31:0 - -#define NVA1C0_SET_DST_LAYER 0x01a4 -#define NVA1C0_SET_DST_LAYER_V 31:0 - -#define NVA1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 - -#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 - -#define NVA1C0_LAUNCH_DMA 0x01b0 -#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVA1C0_LOAD_INLINE_DATA 0x01b4 -#define NVA1C0_LOAD_INLINE_DATA_V 31:0 - -#define NVA1C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVA1C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVA1C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVA1C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVA1C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVA1C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVA1C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVA1C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVA1C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVA1C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVA1C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 -#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 - -#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 -#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 - -#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 -#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 - -#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c -#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 - -#define NVA1C0_PERFMON_TRANSFER 0x0210 -#define NVA1C0_PERFMON_TRANSFER_V 31:0 - -#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVA1C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVA1C0_SET_CWD_CONTROL 0x0240 -#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 -#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 -#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 - -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVA1C0_SET_CWD_REF_COUNTER 0x0248 -#define NVA1C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVA1C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 - -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 - -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 - -#define NVA1C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA1C0_SET_QMD_VERSION 0x0288 -#define NVA1C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA1C0_CHECK_QMD_VERSION 0x0290 -#define NVA1C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVA1C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVA1C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVA1C0_SEND_PCAS_A 0x02b4 -#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVA1C0_SEND_PCAS_B 0x02b8 -#define NVA1C0_SEND_PCAS_B_FROM 23:0 -#define NVA1C0_SEND_PCAS_B_DELTA 31:24 - -#define NVA1C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 -#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 -#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 -#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 -#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVA1C0_SET_SPA_VERSION 0x0310 -#define NVA1C0_SET_SPA_VERSION_MINOR 7:0 -#define NVA1C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVA1C0_SET_FALCON00 0x0500 -#define NVA1C0_SET_FALCON00_V 31:0 - -#define NVA1C0_SET_FALCON01 0x0504 -#define NVA1C0_SET_FALCON01_V 31:0 - -#define NVA1C0_SET_FALCON02 0x0508 -#define NVA1C0_SET_FALCON02_V 31:0 - -#define NVA1C0_SET_FALCON03 0x050c -#define NVA1C0_SET_FALCON03_V 31:0 - -#define NVA1C0_SET_FALCON04 0x0510 -#define NVA1C0_SET_FALCON04_V 31:0 - -#define NVA1C0_SET_FALCON05 0x0514 -#define NVA1C0_SET_FALCON05_V 31:0 - -#define NVA1C0_SET_FALCON06 0x0518 -#define NVA1C0_SET_FALCON06_V 31:0 - -#define NVA1C0_SET_FALCON07 0x051c -#define NVA1C0_SET_FALCON07_V 31:0 - -#define NVA1C0_SET_FALCON08 0x0520 -#define NVA1C0_SET_FALCON08_V 31:0 - -#define NVA1C0_SET_FALCON09 0x0524 -#define NVA1C0_SET_FALCON09_V 31:0 - -#define NVA1C0_SET_FALCON10 0x0528 -#define NVA1C0_SET_FALCON10_V 31:0 - -#define NVA1C0_SET_FALCON11 0x052c -#define NVA1C0_SET_FALCON11_V 31:0 - -#define NVA1C0_SET_FALCON12 0x0530 -#define NVA1C0_SET_FALCON12_V 31:0 - -#define NVA1C0_SET_FALCON13 0x0534 -#define NVA1C0_SET_FALCON13_V 31:0 - -#define NVA1C0_SET_FALCON14 0x0538 -#define NVA1C0_SET_FALCON14_V 31:0 - -#define NVA1C0_SET_FALCON15 0x053c -#define NVA1C0_SET_FALCON15_V 31:0 - -#define NVA1C0_SET_FALCON16 0x0540 -#define NVA1C0_SET_FALCON16_V 31:0 - -#define NVA1C0_SET_FALCON17 0x0544 -#define NVA1C0_SET_FALCON17_V 31:0 - -#define NVA1C0_SET_FALCON18 0x0548 -#define NVA1C0_SET_FALCON18_V 31:0 - -#define NVA1C0_SET_FALCON19 0x054c -#define NVA1C0_SET_FALCON19_V 31:0 - -#define NVA1C0_SET_FALCON20 0x0550 -#define NVA1C0_SET_FALCON20_V 31:0 - -#define NVA1C0_SET_FALCON21 0x0554 -#define NVA1C0_SET_FALCON21_V 31:0 - -#define NVA1C0_SET_FALCON22 0x0558 -#define NVA1C0_SET_FALCON22_V 31:0 - -#define NVA1C0_SET_FALCON23 0x055c -#define NVA1C0_SET_FALCON23_V 31:0 - -#define NVA1C0_SET_FALCON24 0x0560 -#define NVA1C0_SET_FALCON24_V 31:0 - -#define NVA1C0_SET_FALCON25 0x0564 -#define NVA1C0_SET_FALCON25_V 31:0 - -#define NVA1C0_SET_FALCON26 0x0568 -#define NVA1C0_SET_FALCON26_V 31:0 - -#define NVA1C0_SET_FALCON27 0x056c -#define NVA1C0_SET_FALCON27_V 31:0 - -#define NVA1C0_SET_FALCON28 0x0570 -#define NVA1C0_SET_FALCON28_V 31:0 - -#define NVA1C0_SET_FALCON29 0x0574 -#define NVA1C0_SET_FALCON29_V 31:0 - -#define NVA1C0_SET_FALCON30 0x0578 -#define NVA1C0_SET_FALCON30_V 31:0 - -#define NVA1C0_SET_FALCON31 0x057c -#define NVA1C0_SET_FALCON31_V 31:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 - -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVA1C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVA1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVA1C0_SET_SPARE_NOOP12 0x0f44 -#define NVA1C0_SET_SPARE_NOOP12_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP13 0x0f48 -#define NVA1C0_SET_SPARE_NOOP13_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP14 0x0f4c -#define NVA1C0_SET_SPARE_NOOP14_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP15 0x0f50 -#define NVA1C0_SET_SPARE_NOOP15_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP00 0x1040 -#define NVA1C0_SET_SPARE_NOOP00_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP01 0x1044 -#define NVA1C0_SET_SPARE_NOOP01_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP02 0x1048 -#define NVA1C0_SET_SPARE_NOOP02_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP03 0x104c -#define NVA1C0_SET_SPARE_NOOP03_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP04 0x1050 -#define NVA1C0_SET_SPARE_NOOP04_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP05 0x1054 -#define NVA1C0_SET_SPARE_NOOP05_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP06 0x1058 -#define NVA1C0_SET_SPARE_NOOP06_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP07 0x105c -#define NVA1C0_SET_SPARE_NOOP07_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP08 0x1060 -#define NVA1C0_SET_SPARE_NOOP08_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP09 0x1064 -#define NVA1C0_SET_SPARE_NOOP09_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP10 0x1068 -#define NVA1C0_SET_SPARE_NOOP10_V 31:0 - -#define NVA1C0_SET_SPARE_NOOP11 0x106c -#define NVA1C0_SET_SPARE_NOOP11_V 31:0 - -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 -#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 -#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 -#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 - -#define NVA1C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVA1C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVA1C0_SET_RENDER_ENABLE_A 0x1550 -#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVA1C0_SET_RENDER_ENABLE_B 0x1554 -#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVA1C0_SET_RENDER_ENABLE_C 0x1558 -#define NVA1C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVA1C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NVA1C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVA1C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVA1C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NVA1C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVA1C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVA1C0_SET_PROGRAM_REGION_A 0x1608 -#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 - -#define NVA1C0_SET_PROGRAM_REGION_B 0x160c -#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NVA1C0_SET_SHADER_CONTROL 0x1690 -#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 -#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 -#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 - -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVA1C0_PIPE_NOP 0x1a2c -#define NVA1C0_PIPE_NOP_V 31:0 - -#define NVA1C0_SET_SPARE00 0x1a30 -#define NVA1C0_SET_SPARE00_V 31:0 - -#define NVA1C0_SET_SPARE01 0x1a34 -#define NVA1C0_SET_SPARE01_V 31:0 - -#define NVA1C0_SET_SPARE02 0x1a38 -#define NVA1C0_SET_SPARE02_V 31:0 - -#define NVA1C0_SET_SPARE03 0x1a3c -#define NVA1C0_SET_SPARE03_V 31:0 - -#define NVA1C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVA1C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVA1C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVA1C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 - -#define NVA1C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVA1C0_SET_TRAP_HANDLER 0x260c -#define NVA1C0_SET_TRAP_HANDLER_OFFSET 31:0 - -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVA1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVA1C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_kepler_compute_b_h_ */ diff --git a/Compute-Class-Methods/clb0c0.h b/Compute-Class-Methods/clb0c0.h deleted file mode 100644 index 7f63b4a..0000000 --- a/Compute-Class-Methods/clb0c0.h +++ /dev/null @@ -1,931 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_maxwell_compute_a_h_ -#define _cl_maxwell_compute_a_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */ - -#include "nvtypes.h" - -#define MAXWELL_COMPUTE_A 0xB0C0 - -typedef volatile struct _clb0c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 Reserved_0x148[0x2]; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 Reserved_0x1E8[0x2]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 SetValidSpanOverflowAreaA; - NvU32 SetValidSpanOverflowAreaB; - NvU32 SetValidSpanOverflowAreaC; - NvU32 SetCoalesceWaitingPeriodUnit; - NvU32 PerfmonTransfer; - NvU32 SetShaderSharedMemoryWindow; - NvU32 SetSelectMaxwellTextureHeaders; - NvU32 InvalidateShaderCaches; - NvU32 SetReservedSwMethod00; - NvU32 SetReservedSwMethod01; - NvU32 SetReservedSwMethod02; - NvU32 SetReservedSwMethod03; - NvU32 SetReservedSwMethod04; - NvU32 SetReservedSwMethod05; - NvU32 SetReservedSwMethod06; - NvU32 SetReservedSwMethod07; - NvU32 SetCwdControl; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 SetReservedSwMethod08; - NvU32 SetReservedSwMethod09; - NvU32 SetReservedSwMethod10; - NvU32 SetReservedSwMethod11; - NvU32 SetReservedSwMethod12; - NvU32 SetReservedSwMethod13; - NvU32 SetReservedSwMethod14; - NvU32 SetReservedSwMethod15; - NvU32 Reserved_0x26C[0x2]; - NvU32 InvalidateConstantBufferCacheA; - NvU32 InvalidateConstantBufferCacheB; - NvU32 InvalidateConstantBufferCacheC; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 Reserved_0x28C[0x1]; - NvU32 CheckQmdVersion; - NvU32 Reserved_0x294[0x7]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x9]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 SetShaderLocalMemoryThrottledA; - NvU32 SetShaderLocalMemoryThrottledB; - NvU32 SetShaderLocalMemoryThrottledC; - NvU32 Reserved_0x2FC[0x5]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x7B]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x7F]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 Reserved_0x780[0x4]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x17F]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x3B]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x86]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x7]; - NvU32 ActivatePerfSettingsForComputeContext; - NvU32 Reserved_0x12AC[0x21]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x22]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BE]; - NvU32 SetBindlessTexture; - NvU32 SetTrapHandler; - NvU32 Reserved_0x2610[0x34B]; - NvU32 SetShaderPerformanceCounterValueUpper[0x8]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 StartShaderPerformanceCounter; - NvU32 StopShaderPerformanceCounter; - NvU32 Reserved_0x33E8[0x6]; - NvU32 SetMmeShadowScratch[0x8]; -} maxwell_compute_a_t; - - -#define NVB0C0_SET_OBJECT 0x0000 -#define NVB0C0_SET_OBJECT_CLASS_ID 15:0 -#define NVB0C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVB0C0_NO_OPERATION 0x0100 -#define NVB0C0_NO_OPERATION_V 31:0 - -#define NVB0C0_SET_NOTIFY_A 0x0104 -#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVB0C0_SET_NOTIFY_B 0x0108 -#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVB0C0_NOTIFY 0x010c -#define NVB0C0_NOTIFY_TYPE 31:0 -#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVB0C0_WAIT_FOR_IDLE 0x0110 -#define NVB0C0_WAIT_FOR_IDLE_V 31:0 - -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVB0C0_SEND_GO_IDLE 0x013c -#define NVB0C0_SEND_GO_IDLE_V 31:0 - -#define NVB0C0_PM_TRIGGER 0x0140 -#define NVB0C0_PM_TRIGGER_V 31:0 - -#define NVB0C0_PM_TRIGGER_WFI 0x0144 -#define NVB0C0_PM_TRIGGER_WFI_V 31:0 - -#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVB0C0_LINE_LENGTH_IN 0x0180 -#define NVB0C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVB0C0_LINE_COUNT 0x0184 -#define NVB0C0_LINE_COUNT_VALUE 31:0 - -#define NVB0C0_OFFSET_OUT_UPPER 0x0188 -#define NVB0C0_OFFSET_OUT_UPPER_VALUE 7:0 - -#define NVB0C0_OFFSET_OUT 0x018c -#define NVB0C0_OFFSET_OUT_VALUE 31:0 - -#define NVB0C0_PITCH_OUT 0x0190 -#define NVB0C0_PITCH_OUT_VALUE 31:0 - -#define NVB0C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVB0C0_SET_DST_WIDTH 0x0198 -#define NVB0C0_SET_DST_WIDTH_V 31:0 - -#define NVB0C0_SET_DST_HEIGHT 0x019c -#define NVB0C0_SET_DST_HEIGHT_V 31:0 - -#define NVB0C0_SET_DST_DEPTH 0x01a0 -#define NVB0C0_SET_DST_DEPTH_V 31:0 - -#define NVB0C0_SET_DST_LAYER 0x01a4 -#define NVB0C0_SET_DST_LAYER_V 31:0 - -#define NVB0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 - -#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 - -#define NVB0C0_LAUNCH_DMA 0x01b0 -#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVB0C0_LOAD_INLINE_DATA 0x01b4 -#define NVB0C0_LOAD_INLINE_DATA_V 31:0 - -#define NVB0C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVB0C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVB0C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVB0C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVB0C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVB0C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVB0C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVB0C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVB0C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVB0C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVB0C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 -#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 - -#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 -#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 - -#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 -#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 - -#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c -#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 - -#define NVB0C0_PERFMON_TRANSFER 0x0210 -#define NVB0C0_PERFMON_TRANSFER_V 31:0 - -#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 -#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 -#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 -#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 - -#define NVB0C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVB0C0_SET_RESERVED_SW_METHOD00 0x0220 -#define NVB0C0_SET_RESERVED_SW_METHOD00_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD01 0x0224 -#define NVB0C0_SET_RESERVED_SW_METHOD01_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD02 0x0228 -#define NVB0C0_SET_RESERVED_SW_METHOD02_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD03 0x022c -#define NVB0C0_SET_RESERVED_SW_METHOD03_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD04 0x0230 -#define NVB0C0_SET_RESERVED_SW_METHOD04_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD05 0x0234 -#define NVB0C0_SET_RESERVED_SW_METHOD05_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD06 0x0238 -#define NVB0C0_SET_RESERVED_SW_METHOD06_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD07 0x023c -#define NVB0C0_SET_RESERVED_SW_METHOD07_V 31:0 - -#define NVB0C0_SET_CWD_CONTROL 0x0240 -#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 -#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 -#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 - -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVB0C0_SET_CWD_REF_COUNTER 0x0248 -#define NVB0C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVB0C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVB0C0_SET_RESERVED_SW_METHOD08 0x024c -#define NVB0C0_SET_RESERVED_SW_METHOD08_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD09 0x0250 -#define NVB0C0_SET_RESERVED_SW_METHOD09_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD10 0x0254 -#define NVB0C0_SET_RESERVED_SW_METHOD10_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD11 0x0258 -#define NVB0C0_SET_RESERVED_SW_METHOD11_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD12 0x025c -#define NVB0C0_SET_RESERVED_SW_METHOD12_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD13 0x0260 -#define NVB0C0_SET_RESERVED_SW_METHOD13_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD14 0x0264 -#define NVB0C0_SET_RESERVED_SW_METHOD14_V 31:0 - -#define NVB0C0_SET_RESERVED_SW_METHOD15 0x0268 -#define NVB0C0_SET_RESERVED_SW_METHOD15_V 31:0 - -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 - -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 - -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 - -#define NVB0C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB0C0_SET_QMD_VERSION 0x0288 -#define NVB0C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB0C0_CHECK_QMD_VERSION 0x0290 -#define NVB0C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB0C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVB0C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVB0C0_SEND_PCAS_A 0x02b4 -#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVB0C0_SEND_PCAS_B 0x02b8 -#define NVB0C0_SEND_PCAS_B_FROM 23:0 -#define NVB0C0_SEND_PCAS_B_DELTA 31:24 - -#define NVB0C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVB0C0_SET_SPA_VERSION 0x0310 -#define NVB0C0_SET_SPA_VERSION_MINOR 7:0 -#define NVB0C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVB0C0_SET_FALCON00 0x0500 -#define NVB0C0_SET_FALCON00_V 31:0 - -#define NVB0C0_SET_FALCON01 0x0504 -#define NVB0C0_SET_FALCON01_V 31:0 - -#define NVB0C0_SET_FALCON02 0x0508 -#define NVB0C0_SET_FALCON02_V 31:0 - -#define NVB0C0_SET_FALCON03 0x050c -#define NVB0C0_SET_FALCON03_V 31:0 - -#define NVB0C0_SET_FALCON04 0x0510 -#define NVB0C0_SET_FALCON04_V 31:0 - -#define NVB0C0_SET_FALCON05 0x0514 -#define NVB0C0_SET_FALCON05_V 31:0 - -#define NVB0C0_SET_FALCON06 0x0518 -#define NVB0C0_SET_FALCON06_V 31:0 - -#define NVB0C0_SET_FALCON07 0x051c -#define NVB0C0_SET_FALCON07_V 31:0 - -#define NVB0C0_SET_FALCON08 0x0520 -#define NVB0C0_SET_FALCON08_V 31:0 - -#define NVB0C0_SET_FALCON09 0x0524 -#define NVB0C0_SET_FALCON09_V 31:0 - -#define NVB0C0_SET_FALCON10 0x0528 -#define NVB0C0_SET_FALCON10_V 31:0 - -#define NVB0C0_SET_FALCON11 0x052c -#define NVB0C0_SET_FALCON11_V 31:0 - -#define NVB0C0_SET_FALCON12 0x0530 -#define NVB0C0_SET_FALCON12_V 31:0 - -#define NVB0C0_SET_FALCON13 0x0534 -#define NVB0C0_SET_FALCON13_V 31:0 - -#define NVB0C0_SET_FALCON14 0x0538 -#define NVB0C0_SET_FALCON14_V 31:0 - -#define NVB0C0_SET_FALCON15 0x053c -#define NVB0C0_SET_FALCON15_V 31:0 - -#define NVB0C0_SET_FALCON16 0x0540 -#define NVB0C0_SET_FALCON16_V 31:0 - -#define NVB0C0_SET_FALCON17 0x0544 -#define NVB0C0_SET_FALCON17_V 31:0 - -#define NVB0C0_SET_FALCON18 0x0548 -#define NVB0C0_SET_FALCON18_V 31:0 - -#define NVB0C0_SET_FALCON19 0x054c -#define NVB0C0_SET_FALCON19_V 31:0 - -#define NVB0C0_SET_FALCON20 0x0550 -#define NVB0C0_SET_FALCON20_V 31:0 - -#define NVB0C0_SET_FALCON21 0x0554 -#define NVB0C0_SET_FALCON21_V 31:0 - -#define NVB0C0_SET_FALCON22 0x0558 -#define NVB0C0_SET_FALCON22_V 31:0 - -#define NVB0C0_SET_FALCON23 0x055c -#define NVB0C0_SET_FALCON23_V 31:0 - -#define NVB0C0_SET_FALCON24 0x0560 -#define NVB0C0_SET_FALCON24_V 31:0 - -#define NVB0C0_SET_FALCON25 0x0564 -#define NVB0C0_SET_FALCON25_V 31:0 - -#define NVB0C0_SET_FALCON26 0x0568 -#define NVB0C0_SET_FALCON26_V 31:0 - -#define NVB0C0_SET_FALCON27 0x056c -#define NVB0C0_SET_FALCON27_V 31:0 - -#define NVB0C0_SET_FALCON28 0x0570 -#define NVB0C0_SET_FALCON28_V 31:0 - -#define NVB0C0_SET_FALCON29 0x0574 -#define NVB0C0_SET_FALCON29_V 31:0 - -#define NVB0C0_SET_FALCON30 0x0578 -#define NVB0C0_SET_FALCON30_V 31:0 - -#define NVB0C0_SET_FALCON31 0x057c -#define NVB0C0_SET_FALCON31_V 31:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 - -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVB0C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVB0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVB0C0_SET_SPARE_NOOP12 0x0f44 -#define NVB0C0_SET_SPARE_NOOP12_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP13 0x0f48 -#define NVB0C0_SET_SPARE_NOOP13_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP14 0x0f4c -#define NVB0C0_SET_SPARE_NOOP14_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP15 0x0f50 -#define NVB0C0_SET_SPARE_NOOP15_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP00 0x1040 -#define NVB0C0_SET_SPARE_NOOP00_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP01 0x1044 -#define NVB0C0_SET_SPARE_NOOP01_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP02 0x1048 -#define NVB0C0_SET_SPARE_NOOP02_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP03 0x104c -#define NVB0C0_SET_SPARE_NOOP03_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP04 0x1050 -#define NVB0C0_SET_SPARE_NOOP04_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP05 0x1054 -#define NVB0C0_SET_SPARE_NOOP05_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP06 0x1058 -#define NVB0C0_SET_SPARE_NOOP06_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP07 0x105c -#define NVB0C0_SET_SPARE_NOOP07_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP08 0x1060 -#define NVB0C0_SET_SPARE_NOOP08_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP09 0x1064 -#define NVB0C0_SET_SPARE_NOOP09_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP10 0x1068 -#define NVB0C0_SET_SPARE_NOOP10_V 31:0 - -#define NVB0C0_SET_SPARE_NOOP11 0x106c -#define NVB0C0_SET_SPARE_NOOP11_V 31:0 - -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 -#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 -#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 -#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 - -#define NVB0C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVB0C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVB0C0_SET_RENDER_ENABLE_A 0x1550 -#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVB0C0_SET_RENDER_ENABLE_B 0x1554 -#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVB0C0_SET_RENDER_ENABLE_C 0x1558 -#define NVB0C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVB0C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NVB0C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVB0C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVB0C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NVB0C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVB0C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVB0C0_SET_PROGRAM_REGION_A 0x1608 -#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 - -#define NVB0C0_SET_PROGRAM_REGION_B 0x160c -#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVB0C0_PIPE_NOP 0x1a2c -#define NVB0C0_PIPE_NOP_V 31:0 - -#define NVB0C0_SET_SPARE00 0x1a30 -#define NVB0C0_SET_SPARE00_V 31:0 - -#define NVB0C0_SET_SPARE01 0x1a34 -#define NVB0C0_SET_SPARE01_V 31:0 - -#define NVB0C0_SET_SPARE02 0x1a38 -#define NVB0C0_SET_SPARE02_V 31:0 - -#define NVB0C0_SET_SPARE03 0x1a3c -#define NVB0C0_SET_SPARE03_V 31:0 - -#define NVB0C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVB0C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVB0C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVB0C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 - -#define NVB0C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVB0C0_SET_TRAP_HANDLER 0x260c -#define NVB0C0_SET_TRAP_HANDLER_OFFSET 31:0 - -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 - -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 -#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 -#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVB0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVB0C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_maxwell_compute_a_h_ */ diff --git a/Compute-Class-Methods/clb1c0.h b/Compute-Class-Methods/clb1c0.h deleted file mode 100644 index ba5519d..0000000 --- a/Compute-Class-Methods/clb1c0.h +++ /dev/null @@ -1,968 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_maxwell_compute_b_h_ -#define _cl_maxwell_compute_b_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */ - -#include "nvtypes.h" - -#define MAXWELL_COMPUTE_B 0xB1C0 - -typedef volatile struct _clb1c0_tag0 { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 Reserved_0x148[0x2]; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 Reserved_0x1E8[0x2]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 SetValidSpanOverflowAreaA; - NvU32 SetValidSpanOverflowAreaB; - NvU32 SetValidSpanOverflowAreaC; - NvU32 SetCoalesceWaitingPeriodUnit; - NvU32 PerfmonTransfer; - NvU32 SetShaderSharedMemoryWindow; - NvU32 SetSelectMaxwellTextureHeaders; - NvU32 InvalidateShaderCaches; - NvU32 SetReservedSwMethod00; - NvU32 SetReservedSwMethod01; - NvU32 SetReservedSwMethod02; - NvU32 SetReservedSwMethod03; - NvU32 SetReservedSwMethod04; - NvU32 SetReservedSwMethod05; - NvU32 SetReservedSwMethod06; - NvU32 SetReservedSwMethod07; - NvU32 SetCwdControl; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 SetReservedSwMethod08; - NvU32 SetReservedSwMethod09; - NvU32 SetReservedSwMethod10; - NvU32 SetReservedSwMethod11; - NvU32 SetReservedSwMethod12; - NvU32 SetReservedSwMethod13; - NvU32 SetReservedSwMethod14; - NvU32 SetReservedSwMethod15; - NvU32 SetGwcScgType; - NvU32 SetScgControl; - NvU32 InvalidateConstantBufferCacheA; - NvU32 InvalidateConstantBufferCacheB; - NvU32 InvalidateConstantBufferCacheC; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 SetWfiConfig; - NvU32 CheckQmdVersion; - NvU32 WaitForIdleScgType; - NvU32 InvalidateSkedCaches; - NvU32 SetScgRenderEnableControl; - NvU32 Reserved_0x2A0[0x4]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x9]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 SetShaderLocalMemoryThrottledA; - NvU32 SetShaderLocalMemoryThrottledB; - NvU32 SetShaderLocalMemoryThrottledC; - NvU32 Reserved_0x2FC[0x5]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x7B]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x7F]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 Reserved_0x780[0x4]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x17F]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x3B]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x67]; - NvU32 InvalidateSamplerCacheAll; - NvU32 InvalidateTextureHeaderCacheAll; - NvU32 Reserved_0x1214[0x1D]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x7]; - NvU32 ActivatePerfSettingsForComputeContext; - NvU32 Reserved_0x12AC[0x21]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x22]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BE]; - NvU32 SetBindlessTexture; - NvU32 SetTrapHandler; - NvU32 Reserved_0x2610[0x34B]; - NvU32 SetShaderPerformanceCounterValueUpper[0x8]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 StartShaderPerformanceCounter; - NvU32 StopShaderPerformanceCounter; - NvU32 Reserved_0x33E8[0x6]; - NvU32 SetMmeShadowScratch[0x8]; -} maxwell_compute_b_t; - - -#define NVB1C0_SET_OBJECT 0x0000 -#define NVB1C0_SET_OBJECT_CLASS_ID 15:0 -#define NVB1C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVB1C0_NO_OPERATION 0x0100 -#define NVB1C0_NO_OPERATION_V 31:0 - -#define NVB1C0_SET_NOTIFY_A 0x0104 -#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVB1C0_SET_NOTIFY_B 0x0108 -#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVB1C0_NOTIFY 0x010c -#define NVB1C0_NOTIFY_TYPE 31:0 -#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVB1C0_WAIT_FOR_IDLE 0x0110 -#define NVB1C0_WAIT_FOR_IDLE_V 31:0 - -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVB1C0_SEND_GO_IDLE 0x013c -#define NVB1C0_SEND_GO_IDLE_V 31:0 - -#define NVB1C0_PM_TRIGGER 0x0140 -#define NVB1C0_PM_TRIGGER_V 31:0 - -#define NVB1C0_PM_TRIGGER_WFI 0x0144 -#define NVB1C0_PM_TRIGGER_WFI_V 31:0 - -#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVB1C0_LINE_LENGTH_IN 0x0180 -#define NVB1C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVB1C0_LINE_COUNT 0x0184 -#define NVB1C0_LINE_COUNT_VALUE 31:0 - -#define NVB1C0_OFFSET_OUT_UPPER 0x0188 -#define NVB1C0_OFFSET_OUT_UPPER_VALUE 7:0 - -#define NVB1C0_OFFSET_OUT 0x018c -#define NVB1C0_OFFSET_OUT_VALUE 31:0 - -#define NVB1C0_PITCH_OUT 0x0190 -#define NVB1C0_PITCH_OUT_VALUE 31:0 - -#define NVB1C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVB1C0_SET_DST_WIDTH 0x0198 -#define NVB1C0_SET_DST_WIDTH_V 31:0 - -#define NVB1C0_SET_DST_HEIGHT 0x019c -#define NVB1C0_SET_DST_HEIGHT_V 31:0 - -#define NVB1C0_SET_DST_DEPTH 0x01a0 -#define NVB1C0_SET_DST_DEPTH_V 31:0 - -#define NVB1C0_SET_DST_LAYER 0x01a4 -#define NVB1C0_SET_DST_LAYER_V 31:0 - -#define NVB1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 - -#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 - -#define NVB1C0_LAUNCH_DMA 0x01b0 -#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVB1C0_LOAD_INLINE_DATA 0x01b4 -#define NVB1C0_LOAD_INLINE_DATA_V 31:0 - -#define NVB1C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVB1C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVB1C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVB1C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVB1C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVB1C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVB1C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVB1C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVB1C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVB1C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVB1C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 -#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 - -#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 -#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 - -#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 -#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 - -#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c -#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 - -#define NVB1C0_PERFMON_TRANSFER 0x0210 -#define NVB1C0_PERFMON_TRANSFER_V 31:0 - -#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 -#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 -#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 -#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 - -#define NVB1C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVB1C0_SET_RESERVED_SW_METHOD00 0x0220 -#define NVB1C0_SET_RESERVED_SW_METHOD00_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD01 0x0224 -#define NVB1C0_SET_RESERVED_SW_METHOD01_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD02 0x0228 -#define NVB1C0_SET_RESERVED_SW_METHOD02_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD03 0x022c -#define NVB1C0_SET_RESERVED_SW_METHOD03_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD04 0x0230 -#define NVB1C0_SET_RESERVED_SW_METHOD04_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD05 0x0234 -#define NVB1C0_SET_RESERVED_SW_METHOD05_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD06 0x0238 -#define NVB1C0_SET_RESERVED_SW_METHOD06_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD07 0x023c -#define NVB1C0_SET_RESERVED_SW_METHOD07_V 31:0 - -#define NVB1C0_SET_CWD_CONTROL 0x0240 -#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 -#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 -#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 - -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVB1C0_SET_CWD_REF_COUNTER 0x0248 -#define NVB1C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVB1C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVB1C0_SET_RESERVED_SW_METHOD08 0x024c -#define NVB1C0_SET_RESERVED_SW_METHOD08_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD09 0x0250 -#define NVB1C0_SET_RESERVED_SW_METHOD09_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD10 0x0254 -#define NVB1C0_SET_RESERVED_SW_METHOD10_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD11 0x0258 -#define NVB1C0_SET_RESERVED_SW_METHOD11_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD12 0x025c -#define NVB1C0_SET_RESERVED_SW_METHOD12_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD13 0x0260 -#define NVB1C0_SET_RESERVED_SW_METHOD13_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD14 0x0264 -#define NVB1C0_SET_RESERVED_SW_METHOD14_V 31:0 - -#define NVB1C0_SET_RESERVED_SW_METHOD15 0x0268 -#define NVB1C0_SET_RESERVED_SW_METHOD15_V 31:0 - -#define NVB1C0_SET_GWC_SCG_TYPE 0x026c -#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 -#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 -#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 - -#define NVB1C0_SET_SCG_CONTROL 0x0270 -#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 - -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 - -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 - -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 - -#define NVB1C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB1C0_SET_QMD_VERSION 0x0288 -#define NVB1C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB1C0_SET_WFI_CONFIG 0x028c -#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 -#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 -#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 - -#define NVB1C0_CHECK_QMD_VERSION 0x0290 -#define NVB1C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 -#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 - -#define NVB1C0_INVALIDATE_SKED_CACHES 0x0298 -#define NVB1C0_INVALIDATE_SKED_CACHES_V 0:0 - -#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c -#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 -#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 -#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 - -#define NVB1C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVB1C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVB1C0_SEND_PCAS_A 0x02b4 -#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVB1C0_SEND_PCAS_B 0x02b8 -#define NVB1C0_SEND_PCAS_B_FROM 23:0 -#define NVB1C0_SEND_PCAS_B_DELTA 31:24 - -#define NVB1C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVB1C0_SET_SPA_VERSION 0x0310 -#define NVB1C0_SET_SPA_VERSION_MINOR 7:0 -#define NVB1C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVB1C0_SET_FALCON00 0x0500 -#define NVB1C0_SET_FALCON00_V 31:0 - -#define NVB1C0_SET_FALCON01 0x0504 -#define NVB1C0_SET_FALCON01_V 31:0 - -#define NVB1C0_SET_FALCON02 0x0508 -#define NVB1C0_SET_FALCON02_V 31:0 - -#define NVB1C0_SET_FALCON03 0x050c -#define NVB1C0_SET_FALCON03_V 31:0 - -#define NVB1C0_SET_FALCON04 0x0510 -#define NVB1C0_SET_FALCON04_V 31:0 - -#define NVB1C0_SET_FALCON05 0x0514 -#define NVB1C0_SET_FALCON05_V 31:0 - -#define NVB1C0_SET_FALCON06 0x0518 -#define NVB1C0_SET_FALCON06_V 31:0 - -#define NVB1C0_SET_FALCON07 0x051c -#define NVB1C0_SET_FALCON07_V 31:0 - -#define NVB1C0_SET_FALCON08 0x0520 -#define NVB1C0_SET_FALCON08_V 31:0 - -#define NVB1C0_SET_FALCON09 0x0524 -#define NVB1C0_SET_FALCON09_V 31:0 - -#define NVB1C0_SET_FALCON10 0x0528 -#define NVB1C0_SET_FALCON10_V 31:0 - -#define NVB1C0_SET_FALCON11 0x052c -#define NVB1C0_SET_FALCON11_V 31:0 - -#define NVB1C0_SET_FALCON12 0x0530 -#define NVB1C0_SET_FALCON12_V 31:0 - -#define NVB1C0_SET_FALCON13 0x0534 -#define NVB1C0_SET_FALCON13_V 31:0 - -#define NVB1C0_SET_FALCON14 0x0538 -#define NVB1C0_SET_FALCON14_V 31:0 - -#define NVB1C0_SET_FALCON15 0x053c -#define NVB1C0_SET_FALCON15_V 31:0 - -#define NVB1C0_SET_FALCON16 0x0540 -#define NVB1C0_SET_FALCON16_V 31:0 - -#define NVB1C0_SET_FALCON17 0x0544 -#define NVB1C0_SET_FALCON17_V 31:0 - -#define NVB1C0_SET_FALCON18 0x0548 -#define NVB1C0_SET_FALCON18_V 31:0 - -#define NVB1C0_SET_FALCON19 0x054c -#define NVB1C0_SET_FALCON19_V 31:0 - -#define NVB1C0_SET_FALCON20 0x0550 -#define NVB1C0_SET_FALCON20_V 31:0 - -#define NVB1C0_SET_FALCON21 0x0554 -#define NVB1C0_SET_FALCON21_V 31:0 - -#define NVB1C0_SET_FALCON22 0x0558 -#define NVB1C0_SET_FALCON22_V 31:0 - -#define NVB1C0_SET_FALCON23 0x055c -#define NVB1C0_SET_FALCON23_V 31:0 - -#define NVB1C0_SET_FALCON24 0x0560 -#define NVB1C0_SET_FALCON24_V 31:0 - -#define NVB1C0_SET_FALCON25 0x0564 -#define NVB1C0_SET_FALCON25_V 31:0 - -#define NVB1C0_SET_FALCON26 0x0568 -#define NVB1C0_SET_FALCON26_V 31:0 - -#define NVB1C0_SET_FALCON27 0x056c -#define NVB1C0_SET_FALCON27_V 31:0 - -#define NVB1C0_SET_FALCON28 0x0570 -#define NVB1C0_SET_FALCON28_V 31:0 - -#define NVB1C0_SET_FALCON29 0x0574 -#define NVB1C0_SET_FALCON29_V 31:0 - -#define NVB1C0_SET_FALCON30 0x0578 -#define NVB1C0_SET_FALCON30_V 31:0 - -#define NVB1C0_SET_FALCON31 0x057c -#define NVB1C0_SET_FALCON31_V 31:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 - -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVB1C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVB1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVB1C0_SET_SPARE_NOOP12 0x0f44 -#define NVB1C0_SET_SPARE_NOOP12_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP13 0x0f48 -#define NVB1C0_SET_SPARE_NOOP13_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP14 0x0f4c -#define NVB1C0_SET_SPARE_NOOP14_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP15 0x0f50 -#define NVB1C0_SET_SPARE_NOOP15_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP00 0x1040 -#define NVB1C0_SET_SPARE_NOOP00_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP01 0x1044 -#define NVB1C0_SET_SPARE_NOOP01_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP02 0x1048 -#define NVB1C0_SET_SPARE_NOOP02_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP03 0x104c -#define NVB1C0_SET_SPARE_NOOP03_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP04 0x1050 -#define NVB1C0_SET_SPARE_NOOP04_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP05 0x1054 -#define NVB1C0_SET_SPARE_NOOP05_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP06 0x1058 -#define NVB1C0_SET_SPARE_NOOP06_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP07 0x105c -#define NVB1C0_SET_SPARE_NOOP07_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP08 0x1060 -#define NVB1C0_SET_SPARE_NOOP08_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP09 0x1064 -#define NVB1C0_SET_SPARE_NOOP09_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP10 0x1068 -#define NVB1C0_SET_SPARE_NOOP10_V 31:0 - -#define NVB1C0_SET_SPARE_NOOP11 0x106c -#define NVB1C0_SET_SPARE_NOOP11_V 31:0 - -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 - -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 - -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 -#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 -#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 -#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 - -#define NVB1C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVB1C0_SET_RENDER_ENABLE_A 0x1550 -#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVB1C0_SET_RENDER_ENABLE_B 0x1554 -#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVB1C0_SET_RENDER_ENABLE_C 0x1558 -#define NVB1C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVB1C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 - -#define NVB1C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVB1C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVB1C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 - -#define NVB1C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVB1C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVB1C0_SET_PROGRAM_REGION_A 0x1608 -#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 - -#define NVB1C0_SET_PROGRAM_REGION_B 0x160c -#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVB1C0_PIPE_NOP 0x1a2c -#define NVB1C0_PIPE_NOP_V 31:0 - -#define NVB1C0_SET_SPARE00 0x1a30 -#define NVB1C0_SET_SPARE00_V 31:0 - -#define NVB1C0_SET_SPARE01 0x1a34 -#define NVB1C0_SET_SPARE01_V 31:0 - -#define NVB1C0_SET_SPARE02 0x1a38 -#define NVB1C0_SET_SPARE02_V 31:0 - -#define NVB1C0_SET_SPARE03 0x1a3c -#define NVB1C0_SET_SPARE03_V 31:0 - -#define NVB1C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVB1C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVB1C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVB1C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 - -#define NVB1C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVB1C0_SET_TRAP_HANDLER 0x260c -#define NVB1C0_SET_TRAP_HANDLER_OFFSET 31:0 - -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 - -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 -#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 -#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVB1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVB1C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_maxwell_compute_b_h_ */ diff --git a/Compute-Class-Methods/clc0c0.h b/Compute-Class-Methods/clc0c0.h deleted file mode 100644 index ee090ec..0000000 --- a/Compute-Class-Methods/clc0c0.h +++ /dev/null @@ -1,1006 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_pascal_compute_a_h_ -#define _cl_pascal_compute_a_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */ - -#include "nvtypes.h" - -#define PASCAL_COMPUTE_A 0xC0C0 - -typedef volatile struct pascal_compute_a_struct { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 Reserved_0x148[0x2]; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 Reserved_0x1E8[0x2]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 SetValidSpanOverflowAreaA; - NvU32 SetValidSpanOverflowAreaB; - NvU32 SetValidSpanOverflowAreaC; - NvU32 SetCoalesceWaitingPeriodUnit; - NvU32 PerfmonTransfer; - NvU32 SetShaderSharedMemoryWindow; - NvU32 SetSelectMaxwellTextureHeaders; - NvU32 InvalidateShaderCaches; - NvU32 SetReservedSwMethod00; - NvU32 SetReservedSwMethod01; - NvU32 SetReservedSwMethod02; - NvU32 SetReservedSwMethod03; - NvU32 SetReservedSwMethod04; - NvU32 SetReservedSwMethod05; - NvU32 SetReservedSwMethod06; - NvU32 SetReservedSwMethod07; - NvU32 SetCwdControl; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 SetReservedSwMethod08; - NvU32 SetReservedSwMethod09; - NvU32 SetReservedSwMethod10; - NvU32 SetReservedSwMethod11; - NvU32 SetReservedSwMethod12; - NvU32 SetReservedSwMethod13; - NvU32 SetReservedSwMethod14; - NvU32 SetReservedSwMethod15; - NvU32 SetGwcScgType; - NvU32 SetScgControl; - NvU32 InvalidateConstantBufferCacheA; - NvU32 InvalidateConstantBufferCacheB; - NvU32 InvalidateConstantBufferCacheC; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 SetWfiConfig; - NvU32 CheckQmdVersion; - NvU32 WaitForIdleScgType; - NvU32 InvalidateSkedCaches; - NvU32 SetScgRenderEnableControl; - NvU32 SetShaderSharedMemoryWindowA; - NvU32 SetShaderSharedMemoryWindowB; - NvU32 Reserved_0x2A8[0x2]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x9]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 SetShaderLocalMemoryThrottledA; - NvU32 SetShaderLocalMemoryThrottledB; - NvU32 SetShaderLocalMemoryThrottledC; - NvU32 Reserved_0x2FC[0x5]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x1]; - NvU32 SetInlineQmdAddressA; - NvU32 SetInlineQmdAddressB; - NvU32 LoadInlineQmdData[0x40]; - NvU32 Reserved_0x420[0x38]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x7F]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 Reserved_0x780[0x4]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x6]; - NvU32 SetShaderLocalMemoryWindowA; - NvU32 SetShaderLocalMemoryWindowB; - NvU32 Reserved_0x7B8[0x177]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x3B]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x67]; - NvU32 InvalidateSamplerCacheAll; - NvU32 InvalidateTextureHeaderCacheAll; - NvU32 Reserved_0x1214[0x1D]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x7]; - NvU32 ActivatePerfSettingsForComputeContext; - NvU32 Reserved_0x12AC[0x21]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x22]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BE]; - NvU32 SetBindlessTexture; - NvU32 SetTrapHandler; - NvU32 Reserved_0x2610[0x34B]; - NvU32 SetShaderPerformanceCounterValueUpper[0x8]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 StartShaderPerformanceCounter; - NvU32 StopShaderPerformanceCounter; - NvU32 SetShaderPerformanceCounterSctlFilter; - NvU32 SetShaderPerformanceCounterCoreMioFilter; - NvU32 Reserved_0x33F0[0x4]; - NvU32 SetMmeShadowScratch[0x8]; -} pascal_compute_a_t; - - -#define NVC0C0_SET_OBJECT 0x0000 -#define NVC0C0_SET_OBJECT_CLASS_ID 15:0 -#define NVC0C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVC0C0_NO_OPERATION 0x0100 -#define NVC0C0_NO_OPERATION_V 31:0 - -#define NVC0C0_SET_NOTIFY_A 0x0104 -#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVC0C0_SET_NOTIFY_B 0x0108 -#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVC0C0_NOTIFY 0x010c -#define NVC0C0_NOTIFY_TYPE 31:0 -#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVC0C0_WAIT_FOR_IDLE 0x0110 -#define NVC0C0_WAIT_FOR_IDLE_V 31:0 - -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC0C0_SEND_GO_IDLE 0x013c -#define NVC0C0_SEND_GO_IDLE_V 31:0 - -#define NVC0C0_PM_TRIGGER 0x0140 -#define NVC0C0_PM_TRIGGER_V 31:0 - -#define NVC0C0_PM_TRIGGER_WFI 0x0144 -#define NVC0C0_PM_TRIGGER_WFI_V 31:0 - -#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVC0C0_LINE_LENGTH_IN 0x0180 -#define NVC0C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVC0C0_LINE_COUNT 0x0184 -#define NVC0C0_LINE_COUNT_VALUE 31:0 - -#define NVC0C0_OFFSET_OUT_UPPER 0x0188 -#define NVC0C0_OFFSET_OUT_UPPER_VALUE 16:0 - -#define NVC0C0_OFFSET_OUT 0x018c -#define NVC0C0_OFFSET_OUT_VALUE 31:0 - -#define NVC0C0_PITCH_OUT 0x0190 -#define NVC0C0_PITCH_OUT_VALUE 31:0 - -#define NVC0C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVC0C0_SET_DST_WIDTH 0x0198 -#define NVC0C0_SET_DST_WIDTH_V 31:0 - -#define NVC0C0_SET_DST_HEIGHT 0x019c -#define NVC0C0_SET_DST_HEIGHT_V 31:0 - -#define NVC0C0_SET_DST_DEPTH 0x01a0 -#define NVC0C0_SET_DST_DEPTH_V 31:0 - -#define NVC0C0_SET_DST_LAYER 0x01a4 -#define NVC0C0_SET_DST_LAYER_V 31:0 - -#define NVC0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V 20:0 - -#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 - -#define NVC0C0_LAUNCH_DMA 0x01b0 -#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVC0C0_LOAD_INLINE_DATA 0x01b4 -#define NVC0C0_LOAD_INLINE_DATA_V 31:0 - -#define NVC0C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC0C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC0C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC0C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVC0C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVC0C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVC0C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVC0C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVC0C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVC0C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVC0C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 -#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 - -#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 -#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 - -#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 -#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 - -#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c -#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 - -#define NVC0C0_PERFMON_TRANSFER 0x0210 -#define NVC0C0_PERFMON_TRANSFER_V 31:0 - -#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 -#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 -#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 -#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 - -#define NVC0C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVC0C0_SET_RESERVED_SW_METHOD00 0x0220 -#define NVC0C0_SET_RESERVED_SW_METHOD00_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD01 0x0224 -#define NVC0C0_SET_RESERVED_SW_METHOD01_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD02 0x0228 -#define NVC0C0_SET_RESERVED_SW_METHOD02_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD03 0x022c -#define NVC0C0_SET_RESERVED_SW_METHOD03_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD04 0x0230 -#define NVC0C0_SET_RESERVED_SW_METHOD04_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD05 0x0234 -#define NVC0C0_SET_RESERVED_SW_METHOD05_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD06 0x0238 -#define NVC0C0_SET_RESERVED_SW_METHOD06_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD07 0x023c -#define NVC0C0_SET_RESERVED_SW_METHOD07_V 31:0 - -#define NVC0C0_SET_CWD_CONTROL 0x0240 -#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 -#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 -#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 - -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVC0C0_SET_CWD_REF_COUNTER 0x0248 -#define NVC0C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVC0C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVC0C0_SET_RESERVED_SW_METHOD08 0x024c -#define NVC0C0_SET_RESERVED_SW_METHOD08_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD09 0x0250 -#define NVC0C0_SET_RESERVED_SW_METHOD09_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD10 0x0254 -#define NVC0C0_SET_RESERVED_SW_METHOD10_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD11 0x0258 -#define NVC0C0_SET_RESERVED_SW_METHOD11_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD12 0x025c -#define NVC0C0_SET_RESERVED_SW_METHOD12_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD13 0x0260 -#define NVC0C0_SET_RESERVED_SW_METHOD13_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD14 0x0264 -#define NVC0C0_SET_RESERVED_SW_METHOD14_V 31:0 - -#define NVC0C0_SET_RESERVED_SW_METHOD15 0x0268 -#define NVC0C0_SET_RESERVED_SW_METHOD15_V 31:0 - -#define NVC0C0_SET_GWC_SCG_TYPE 0x026c -#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 -#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 -#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 - -#define NVC0C0_SET_SCG_CONTROL 0x0270 -#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 - -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 - -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 - -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 - -#define NVC0C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC0C0_SET_QMD_VERSION 0x0288 -#define NVC0C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC0C0_SET_WFI_CONFIG 0x028c -#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 -#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 -#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 - -#define NVC0C0_CHECK_QMD_VERSION 0x0290 -#define NVC0C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 -#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 - -#define NVC0C0_INVALIDATE_SKED_CACHES 0x0298 -#define NVC0C0_INVALIDATE_SKED_CACHES_V 0:0 - -#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c -#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 -#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 -#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 - -#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 -#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 -#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC0C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVC0C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVC0C0_SEND_PCAS_A 0x02b4 -#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVC0C0_SEND_PCAS_B 0x02b8 -#define NVC0C0_SEND_PCAS_B_FROM 23:0 -#define NVC0C0_SEND_PCAS_B_DELTA 31:24 - -#define NVC0C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVC0C0_SET_SPA_VERSION 0x0310 -#define NVC0C0_SET_SPA_VERSION_MINOR 7:0 -#define NVC0C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVC0C0_SET_INLINE_QMD_ADDRESS_A 0x0318 -#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 - -#define NVC0C0_SET_INLINE_QMD_ADDRESS_B 0x031c -#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 - -#define NVC0C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) -#define NVC0C0_LOAD_INLINE_QMD_DATA_V 31:0 - -#define NVC0C0_SET_FALCON00 0x0500 -#define NVC0C0_SET_FALCON00_V 31:0 - -#define NVC0C0_SET_FALCON01 0x0504 -#define NVC0C0_SET_FALCON01_V 31:0 - -#define NVC0C0_SET_FALCON02 0x0508 -#define NVC0C0_SET_FALCON02_V 31:0 - -#define NVC0C0_SET_FALCON03 0x050c -#define NVC0C0_SET_FALCON03_V 31:0 - -#define NVC0C0_SET_FALCON04 0x0510 -#define NVC0C0_SET_FALCON04_V 31:0 - -#define NVC0C0_SET_FALCON05 0x0514 -#define NVC0C0_SET_FALCON05_V 31:0 - -#define NVC0C0_SET_FALCON06 0x0518 -#define NVC0C0_SET_FALCON06_V 31:0 - -#define NVC0C0_SET_FALCON07 0x051c -#define NVC0C0_SET_FALCON07_V 31:0 - -#define NVC0C0_SET_FALCON08 0x0520 -#define NVC0C0_SET_FALCON08_V 31:0 - -#define NVC0C0_SET_FALCON09 0x0524 -#define NVC0C0_SET_FALCON09_V 31:0 - -#define NVC0C0_SET_FALCON10 0x0528 -#define NVC0C0_SET_FALCON10_V 31:0 - -#define NVC0C0_SET_FALCON11 0x052c -#define NVC0C0_SET_FALCON11_V 31:0 - -#define NVC0C0_SET_FALCON12 0x0530 -#define NVC0C0_SET_FALCON12_V 31:0 - -#define NVC0C0_SET_FALCON13 0x0534 -#define NVC0C0_SET_FALCON13_V 31:0 - -#define NVC0C0_SET_FALCON14 0x0538 -#define NVC0C0_SET_FALCON14_V 31:0 - -#define NVC0C0_SET_FALCON15 0x053c -#define NVC0C0_SET_FALCON15_V 31:0 - -#define NVC0C0_SET_FALCON16 0x0540 -#define NVC0C0_SET_FALCON16_V 31:0 - -#define NVC0C0_SET_FALCON17 0x0544 -#define NVC0C0_SET_FALCON17_V 31:0 - -#define NVC0C0_SET_FALCON18 0x0548 -#define NVC0C0_SET_FALCON18_V 31:0 - -#define NVC0C0_SET_FALCON19 0x054c -#define NVC0C0_SET_FALCON19_V 31:0 - -#define NVC0C0_SET_FALCON20 0x0550 -#define NVC0C0_SET_FALCON20_V 31:0 - -#define NVC0C0_SET_FALCON21 0x0554 -#define NVC0C0_SET_FALCON21_V 31:0 - -#define NVC0C0_SET_FALCON22 0x0558 -#define NVC0C0_SET_FALCON22_V 31:0 - -#define NVC0C0_SET_FALCON23 0x055c -#define NVC0C0_SET_FALCON23_V 31:0 - -#define NVC0C0_SET_FALCON24 0x0560 -#define NVC0C0_SET_FALCON24_V 31:0 - -#define NVC0C0_SET_FALCON25 0x0564 -#define NVC0C0_SET_FALCON25_V 31:0 - -#define NVC0C0_SET_FALCON26 0x0568 -#define NVC0C0_SET_FALCON26_V 31:0 - -#define NVC0C0_SET_FALCON27 0x056c -#define NVC0C0_SET_FALCON27_V 31:0 - -#define NVC0C0_SET_FALCON28 0x0570 -#define NVC0C0_SET_FALCON28_V 31:0 - -#define NVC0C0_SET_FALCON29 0x0574 -#define NVC0C0_SET_FALCON29_V 31:0 - -#define NVC0C0_SET_FALCON30 0x0578 -#define NVC0C0_SET_FALCON30_V 31:0 - -#define NVC0C0_SET_FALCON31 0x057c -#define NVC0C0_SET_FALCON31_V 31:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 -#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC0C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVC0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVC0C0_SET_SPARE_NOOP12 0x0f44 -#define NVC0C0_SET_SPARE_NOOP12_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP13 0x0f48 -#define NVC0C0_SET_SPARE_NOOP13_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP14 0x0f4c -#define NVC0C0_SET_SPARE_NOOP14_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP15 0x0f50 -#define NVC0C0_SET_SPARE_NOOP15_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP00 0x1040 -#define NVC0C0_SET_SPARE_NOOP00_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP01 0x1044 -#define NVC0C0_SET_SPARE_NOOP01_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP02 0x1048 -#define NVC0C0_SET_SPARE_NOOP02_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP03 0x104c -#define NVC0C0_SET_SPARE_NOOP03_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP04 0x1050 -#define NVC0C0_SET_SPARE_NOOP04_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP05 0x1054 -#define NVC0C0_SET_SPARE_NOOP05_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP06 0x1058 -#define NVC0C0_SET_SPARE_NOOP06_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP07 0x105c -#define NVC0C0_SET_SPARE_NOOP07_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP08 0x1060 -#define NVC0C0_SET_SPARE_NOOP08_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP09 0x1064 -#define NVC0C0_SET_SPARE_NOOP09_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP10 0x1068 -#define NVC0C0_SET_SPARE_NOOP10_V 31:0 - -#define NVC0C0_SET_SPARE_NOOP11 0x106c -#define NVC0C0_SET_SPARE_NOOP11_V 31:0 - -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 - -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 - -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 -#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 -#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 -#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 - -#define NVC0C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVC0C0_SET_RENDER_ENABLE_A 0x1550 -#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC0C0_SET_RENDER_ENABLE_B 0x1554 -#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC0C0_SET_RENDER_ENABLE_C 0x1558 -#define NVC0C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC0C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC0C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC0C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVC0C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC0C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC0C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVC0C0_SET_PROGRAM_REGION_A 0x1608 -#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 - -#define NVC0C0_SET_PROGRAM_REGION_B 0x160c -#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVC0C0_PIPE_NOP 0x1a2c -#define NVC0C0_PIPE_NOP_V 31:0 - -#define NVC0C0_SET_SPARE00 0x1a30 -#define NVC0C0_SET_SPARE00_V 31:0 - -#define NVC0C0_SET_SPARE01 0x1a34 -#define NVC0C0_SET_SPARE01_V 31:0 - -#define NVC0C0_SET_SPARE02 0x1a38 -#define NVC0C0_SET_SPARE02_V 31:0 - -#define NVC0C0_SET_SPARE03 0x1a3c -#define NVC0C0_SET_SPARE03_V 31:0 - -#define NVC0C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC0C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC0C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC0C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 - -#define NVC0C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVC0C0_SET_TRAP_HANDLER 0x260c -#define NVC0C0_SET_TRAP_HANDLER_OFFSET 31:0 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 -#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 -#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 - -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec -#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 - -#define NVC0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVC0C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_pascal_compute_a_h_ */ diff --git a/Compute-Class-Methods/clc1c0.h b/Compute-Class-Methods/clc1c0.h deleted file mode 100644 index e5d824f..0000000 --- a/Compute-Class-Methods/clc1c0.h +++ /dev/null @@ -1,1026 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_pascal_compute_b_h_ -#define _cl_pascal_compute_b_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */ - -#include "nvtypes.h" - -#define PASCAL_COMPUTE_B 0xC1C0 - -typedef volatile struct pascal_compute_b_struct { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 FeAtomicSequenceBegin; - NvU32 FeAtomicSequenceEnd; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 Reserved_0x1E8[0x2]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 SetValidSpanOverflowAreaA; - NvU32 SetValidSpanOverflowAreaB; - NvU32 SetValidSpanOverflowAreaC; - NvU32 SetCoalesceWaitingPeriodUnit; - NvU32 PerfmonTransfer; - NvU32 SetShaderSharedMemoryWindow; - NvU32 SetSelectMaxwellTextureHeaders; - NvU32 InvalidateShaderCaches; - NvU32 SetReservedSwMethod00; - NvU32 SetReservedSwMethod01; - NvU32 SetReservedSwMethod02; - NvU32 SetReservedSwMethod03; - NvU32 SetReservedSwMethod04; - NvU32 SetReservedSwMethod05; - NvU32 SetReservedSwMethod06; - NvU32 SetReservedSwMethod07; - NvU32 SetCwdControl; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 SetReservedSwMethod08; - NvU32 SetReservedSwMethod09; - NvU32 SetReservedSwMethod10; - NvU32 SetReservedSwMethod11; - NvU32 SetReservedSwMethod12; - NvU32 SetReservedSwMethod13; - NvU32 SetReservedSwMethod14; - NvU32 SetReservedSwMethod15; - NvU32 SetGwcScgType; - NvU32 SetScgControl; - NvU32 InvalidateConstantBufferCacheA; - NvU32 InvalidateConstantBufferCacheB; - NvU32 InvalidateConstantBufferCacheC; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 SetWfiConfig; - NvU32 CheckQmdVersion; - NvU32 WaitForIdleScgType; - NvU32 InvalidateSkedCaches; - NvU32 SetScgRenderEnableControl; - NvU32 SetShaderSharedMemoryWindowA; - NvU32 SetShaderSharedMemoryWindowB; - NvU32 ScgHysteresisControl; - NvU32 Reserved_0x2AC[0x1]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x9]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 SetShaderLocalMemoryThrottledA; - NvU32 SetShaderLocalMemoryThrottledB; - NvU32 SetShaderLocalMemoryThrottledC; - NvU32 Reserved_0x2FC[0x5]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x1]; - NvU32 SetInlineQmdAddressA; - NvU32 SetInlineQmdAddressB; - NvU32 LoadInlineQmdData[0x40]; - NvU32 Reserved_0x420[0x38]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x7F]; - NvU32 SetShaderLocalMemoryWindow; - NvU32 Reserved_0x780[0x4]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x6]; - NvU32 SetShaderLocalMemoryWindowA; - NvU32 SetShaderLocalMemoryWindowB; - NvU32 Reserved_0x7B8[0x177]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x57]; - NvU32 SetSpareNoop12; - NvU32 SetSpareNoop13; - NvU32 SetSpareNoop14; - NvU32 SetSpareNoop15; - NvU32 Reserved_0xF54[0x3B]; - NvU32 SetSpareNoop00; - NvU32 SetSpareNoop01; - NvU32 SetSpareNoop02; - NvU32 SetSpareNoop03; - NvU32 SetSpareNoop04; - NvU32 SetSpareNoop05; - NvU32 SetSpareNoop06; - NvU32 SetSpareNoop07; - NvU32 SetSpareNoop08; - NvU32 SetSpareNoop09; - NvU32 SetSpareNoop10; - NvU32 SetSpareNoop11; - NvU32 Reserved_0x1070[0x67]; - NvU32 InvalidateSamplerCacheAll; - NvU32 InvalidateTextureHeaderCacheAll; - NvU32 Reserved_0x1214[0x1D]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x7]; - NvU32 ActivatePerfSettingsForComputeContext; - NvU32 Reserved_0x12AC[0x21]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x22]; - NvU32 SetProgramRegionA; - NvU32 SetProgramRegionB; - NvU32 Reserved_0x1610[0x22]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A24[0x1]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BE]; - NvU32 SetBindlessTexture; - NvU32 SetTrapHandler; - NvU32 Reserved_0x2610[0x34B]; - NvU32 SetShaderPerformanceCounterValueUpper[0x8]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 StartShaderPerformanceCounter; - NvU32 StopShaderPerformanceCounter; - NvU32 SetShaderPerformanceCounterSctlFilter; - NvU32 SetShaderPerformanceCounterCoreMioFilter; - NvU32 Reserved_0x33F0[0x4]; - NvU32 SetMmeShadowScratch[0x8]; -} pascal_compute_b_t; - - -#define NVC1C0_SET_OBJECT 0x0000 -#define NVC1C0_SET_OBJECT_CLASS_ID 15:0 -#define NVC1C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVC1C0_NO_OPERATION 0x0100 -#define NVC1C0_NO_OPERATION_V 31:0 - -#define NVC1C0_SET_NOTIFY_A 0x0104 -#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVC1C0_SET_NOTIFY_B 0x0108 -#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVC1C0_NOTIFY 0x010c -#define NVC1C0_NOTIFY_TYPE 31:0 -#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVC1C0_WAIT_FOR_IDLE 0x0110 -#define NVC1C0_WAIT_FOR_IDLE_V 31:0 - -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC1C0_SEND_GO_IDLE 0x013c -#define NVC1C0_SEND_GO_IDLE_V 31:0 - -#define NVC1C0_PM_TRIGGER 0x0140 -#define NVC1C0_PM_TRIGGER_V 31:0 - -#define NVC1C0_PM_TRIGGER_WFI 0x0144 -#define NVC1C0_PM_TRIGGER_WFI_V 31:0 - -#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 -#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 - -#define NVC1C0_FE_ATOMIC_SEQUENCE_END 0x014c -#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V 31:0 - -#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVC1C0_LINE_LENGTH_IN 0x0180 -#define NVC1C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVC1C0_LINE_COUNT 0x0184 -#define NVC1C0_LINE_COUNT_VALUE 31:0 - -#define NVC1C0_OFFSET_OUT_UPPER 0x0188 -#define NVC1C0_OFFSET_OUT_UPPER_VALUE 16:0 - -#define NVC1C0_OFFSET_OUT 0x018c -#define NVC1C0_OFFSET_OUT_VALUE 31:0 - -#define NVC1C0_PITCH_OUT 0x0190 -#define NVC1C0_PITCH_OUT_VALUE 31:0 - -#define NVC1C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVC1C0_SET_DST_WIDTH 0x0198 -#define NVC1C0_SET_DST_WIDTH_V 31:0 - -#define NVC1C0_SET_DST_HEIGHT 0x019c -#define NVC1C0_SET_DST_HEIGHT_V 31:0 - -#define NVC1C0_SET_DST_DEPTH 0x01a0 -#define NVC1C0_SET_DST_DEPTH_V 31:0 - -#define NVC1C0_SET_DST_LAYER 0x01a4 -#define NVC1C0_SET_DST_LAYER_V 31:0 - -#define NVC1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V 20:0 - -#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 - -#define NVC1C0_LAUNCH_DMA 0x01b0 -#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVC1C0_LOAD_INLINE_DATA 0x01b4 -#define NVC1C0_LOAD_INLINE_DATA_V 31:0 - -#define NVC1C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC1C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC1C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC1C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVC1C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVC1C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVC1C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVC1C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVC1C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVC1C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVC1C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 -#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 - -#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 -#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 - -#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 -#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 - -#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c -#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 - -#define NVC1C0_PERFMON_TRANSFER 0x0210 -#define NVC1C0_PERFMON_TRANSFER_V 31:0 - -#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 -#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 -#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 -#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 -#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 - -#define NVC1C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVC1C0_SET_RESERVED_SW_METHOD00 0x0220 -#define NVC1C0_SET_RESERVED_SW_METHOD00_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD01 0x0224 -#define NVC1C0_SET_RESERVED_SW_METHOD01_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD02 0x0228 -#define NVC1C0_SET_RESERVED_SW_METHOD02_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD03 0x022c -#define NVC1C0_SET_RESERVED_SW_METHOD03_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD04 0x0230 -#define NVC1C0_SET_RESERVED_SW_METHOD04_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD05 0x0234 -#define NVC1C0_SET_RESERVED_SW_METHOD05_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD06 0x0238 -#define NVC1C0_SET_RESERVED_SW_METHOD06_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD07 0x023c -#define NVC1C0_SET_RESERVED_SW_METHOD07_V 31:0 - -#define NVC1C0_SET_CWD_CONTROL 0x0240 -#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 -#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 -#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 - -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVC1C0_SET_CWD_REF_COUNTER 0x0248 -#define NVC1C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVC1C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVC1C0_SET_RESERVED_SW_METHOD08 0x024c -#define NVC1C0_SET_RESERVED_SW_METHOD08_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD09 0x0250 -#define NVC1C0_SET_RESERVED_SW_METHOD09_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD10 0x0254 -#define NVC1C0_SET_RESERVED_SW_METHOD10_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD11 0x0258 -#define NVC1C0_SET_RESERVED_SW_METHOD11_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD12 0x025c -#define NVC1C0_SET_RESERVED_SW_METHOD12_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD13 0x0260 -#define NVC1C0_SET_RESERVED_SW_METHOD13_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD14 0x0264 -#define NVC1C0_SET_RESERVED_SW_METHOD14_V 31:0 - -#define NVC1C0_SET_RESERVED_SW_METHOD15 0x0268 -#define NVC1C0_SET_RESERVED_SW_METHOD15_V 31:0 - -#define NVC1C0_SET_GWC_SCG_TYPE 0x026c -#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 -#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 -#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 - -#define NVC1C0_SET_SCG_CONTROL 0x0270 -#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 -#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 -#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 -#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 -#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 - -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 - -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 - -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 - -#define NVC1C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC1C0_SET_QMD_VERSION 0x0288 -#define NVC1C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC1C0_SET_WFI_CONFIG 0x028c -#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 -#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 -#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 - -#define NVC1C0_CHECK_QMD_VERSION 0x0290 -#define NVC1C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 -#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 - -#define NVC1C0_INVALIDATE_SKED_CACHES 0x0298 -#define NVC1C0_INVALIDATE_SKED_CACHES_V 0:0 - -#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c -#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 -#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 -#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 - -#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 -#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 -#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC1C0_SCG_HYSTERESIS_CONTROL 0x02a8 -#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 -#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 -#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 -#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 -#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 -#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 - -#define NVC1C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVC1C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVC1C0_SEND_PCAS_A 0x02b4 -#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVC1C0_SEND_PCAS_B 0x02b8 -#define NVC1C0_SEND_PCAS_B_FROM 23:0 -#define NVC1C0_SEND_PCAS_B_DELTA 31:24 - -#define NVC1C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVC1C0_SET_SPA_VERSION 0x0310 -#define NVC1C0_SET_SPA_VERSION_MINOR 7:0 -#define NVC1C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVC1C0_SET_INLINE_QMD_ADDRESS_A 0x0318 -#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 - -#define NVC1C0_SET_INLINE_QMD_ADDRESS_B 0x031c -#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 - -#define NVC1C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) -#define NVC1C0_LOAD_INLINE_QMD_DATA_V 31:0 - -#define NVC1C0_SET_FALCON00 0x0500 -#define NVC1C0_SET_FALCON00_V 31:0 - -#define NVC1C0_SET_FALCON01 0x0504 -#define NVC1C0_SET_FALCON01_V 31:0 - -#define NVC1C0_SET_FALCON02 0x0508 -#define NVC1C0_SET_FALCON02_V 31:0 - -#define NVC1C0_SET_FALCON03 0x050c -#define NVC1C0_SET_FALCON03_V 31:0 - -#define NVC1C0_SET_FALCON04 0x0510 -#define NVC1C0_SET_FALCON04_V 31:0 - -#define NVC1C0_SET_FALCON05 0x0514 -#define NVC1C0_SET_FALCON05_V 31:0 - -#define NVC1C0_SET_FALCON06 0x0518 -#define NVC1C0_SET_FALCON06_V 31:0 - -#define NVC1C0_SET_FALCON07 0x051c -#define NVC1C0_SET_FALCON07_V 31:0 - -#define NVC1C0_SET_FALCON08 0x0520 -#define NVC1C0_SET_FALCON08_V 31:0 - -#define NVC1C0_SET_FALCON09 0x0524 -#define NVC1C0_SET_FALCON09_V 31:0 - -#define NVC1C0_SET_FALCON10 0x0528 -#define NVC1C0_SET_FALCON10_V 31:0 - -#define NVC1C0_SET_FALCON11 0x052c -#define NVC1C0_SET_FALCON11_V 31:0 - -#define NVC1C0_SET_FALCON12 0x0530 -#define NVC1C0_SET_FALCON12_V 31:0 - -#define NVC1C0_SET_FALCON13 0x0534 -#define NVC1C0_SET_FALCON13_V 31:0 - -#define NVC1C0_SET_FALCON14 0x0538 -#define NVC1C0_SET_FALCON14_V 31:0 - -#define NVC1C0_SET_FALCON15 0x053c -#define NVC1C0_SET_FALCON15_V 31:0 - -#define NVC1C0_SET_FALCON16 0x0540 -#define NVC1C0_SET_FALCON16_V 31:0 - -#define NVC1C0_SET_FALCON17 0x0544 -#define NVC1C0_SET_FALCON17_V 31:0 - -#define NVC1C0_SET_FALCON18 0x0548 -#define NVC1C0_SET_FALCON18_V 31:0 - -#define NVC1C0_SET_FALCON19 0x054c -#define NVC1C0_SET_FALCON19_V 31:0 - -#define NVC1C0_SET_FALCON20 0x0550 -#define NVC1C0_SET_FALCON20_V 31:0 - -#define NVC1C0_SET_FALCON21 0x0554 -#define NVC1C0_SET_FALCON21_V 31:0 - -#define NVC1C0_SET_FALCON22 0x0558 -#define NVC1C0_SET_FALCON22_V 31:0 - -#define NVC1C0_SET_FALCON23 0x055c -#define NVC1C0_SET_FALCON23_V 31:0 - -#define NVC1C0_SET_FALCON24 0x0560 -#define NVC1C0_SET_FALCON24_V 31:0 - -#define NVC1C0_SET_FALCON25 0x0564 -#define NVC1C0_SET_FALCON25_V 31:0 - -#define NVC1C0_SET_FALCON26 0x0568 -#define NVC1C0_SET_FALCON26_V 31:0 - -#define NVC1C0_SET_FALCON27 0x056c -#define NVC1C0_SET_FALCON27_V 31:0 - -#define NVC1C0_SET_FALCON28 0x0570 -#define NVC1C0_SET_FALCON28_V 31:0 - -#define NVC1C0_SET_FALCON29 0x0574 -#define NVC1C0_SET_FALCON29_V 31:0 - -#define NVC1C0_SET_FALCON30 0x0578 -#define NVC1C0_SET_FALCON30_V 31:0 - -#define NVC1C0_SET_FALCON31 0x057c -#define NVC1C0_SET_FALCON31_V 31:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 -#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC1C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVC1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVC1C0_SET_SPARE_NOOP12 0x0f44 -#define NVC1C0_SET_SPARE_NOOP12_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP13 0x0f48 -#define NVC1C0_SET_SPARE_NOOP13_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP14 0x0f4c -#define NVC1C0_SET_SPARE_NOOP14_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP15 0x0f50 -#define NVC1C0_SET_SPARE_NOOP15_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP00 0x1040 -#define NVC1C0_SET_SPARE_NOOP00_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP01 0x1044 -#define NVC1C0_SET_SPARE_NOOP01_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP02 0x1048 -#define NVC1C0_SET_SPARE_NOOP02_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP03 0x104c -#define NVC1C0_SET_SPARE_NOOP03_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP04 0x1050 -#define NVC1C0_SET_SPARE_NOOP04_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP05 0x1054 -#define NVC1C0_SET_SPARE_NOOP05_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP06 0x1058 -#define NVC1C0_SET_SPARE_NOOP06_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP07 0x105c -#define NVC1C0_SET_SPARE_NOOP07_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP08 0x1060 -#define NVC1C0_SET_SPARE_NOOP08_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP09 0x1064 -#define NVC1C0_SET_SPARE_NOOP09_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP10 0x1068 -#define NVC1C0_SET_SPARE_NOOP10_V 31:0 - -#define NVC1C0_SET_SPARE_NOOP11 0x106c -#define NVC1C0_SET_SPARE_NOOP11_V 31:0 - -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 - -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 - -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 -#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 -#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 -#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 - -#define NVC1C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVC1C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVC1C0_SET_RENDER_ENABLE_A 0x1550 -#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC1C0_SET_RENDER_ENABLE_B 0x1554 -#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC1C0_SET_RENDER_ENABLE_C 0x1558 -#define NVC1C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC1C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC1C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC1C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVC1C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC1C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC1C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVC1C0_SET_PROGRAM_REGION_A 0x1608 -#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 - -#define NVC1C0_SET_PROGRAM_REGION_B 0x160c -#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 - -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVC1C0_PIPE_NOP 0x1a2c -#define NVC1C0_PIPE_NOP_V 31:0 - -#define NVC1C0_SET_SPARE00 0x1a30 -#define NVC1C0_SET_SPARE00_V 31:0 - -#define NVC1C0_SET_SPARE01 0x1a34 -#define NVC1C0_SET_SPARE01_V 31:0 - -#define NVC1C0_SET_SPARE02 0x1a38 -#define NVC1C0_SET_SPARE02_V 31:0 - -#define NVC1C0_SET_SPARE03 0x1a3c -#define NVC1C0_SET_SPARE03_V 31:0 - -#define NVC1C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC1C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC1C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC1C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 - -#define NVC1C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVC1C0_SET_TRAP_HANDLER 0x260c -#define NVC1C0_SET_TRAP_HANDLER_OFFSET 31:0 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 -#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 -#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 - -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec -#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 - -#define NVC1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVC1C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_pascal_compute_b_h_ */ diff --git a/Compute-Class-Methods/clc3c0.h b/Compute-Class-Methods/clc3c0.h deleted file mode 100644 index c70a44f..0000000 --- a/Compute-Class-Methods/clc3c0.h +++ /dev/null @@ -1,912 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_volta_compute_a_h_ -#define _cl_volta_compute_a_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */ - -#include "nvtypes.h" - -#define VOLTA_COMPUTE_A 0xC3C0 - -typedef volatile struct volta_compute_a_struct { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 FeAtomicSequenceBegin; - NvU32 FeAtomicSequenceEnd; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 Reserved_0x1E8[0x2]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 SetValidSpanOverflowAreaA; - NvU32 SetValidSpanOverflowAreaB; - NvU32 SetValidSpanOverflowAreaC; - NvU32 Reserved_0x20C[0x1]; - NvU32 PerfmonTransfer; - NvU32 Reserved_0x214[0x2]; - NvU32 InvalidateShaderCaches; - NvU32 SetReservedSwMethod00; - NvU32 SetReservedSwMethod01; - NvU32 SetReservedSwMethod02; - NvU32 SetReservedSwMethod03; - NvU32 SetReservedSwMethod04; - NvU32 SetReservedSwMethod05; - NvU32 SetReservedSwMethod06; - NvU32 SetReservedSwMethod07; - NvU32 Reserved_0x240[0x1]; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 SetReservedSwMethod08; - NvU32 SetReservedSwMethod09; - NvU32 SetReservedSwMethod10; - NvU32 SetReservedSwMethod11; - NvU32 SetReservedSwMethod12; - NvU32 SetReservedSwMethod13; - NvU32 SetReservedSwMethod14; - NvU32 SetReservedSwMethod15; - NvU32 Reserved_0x26C[0x1]; - NvU32 SetScgControl; - NvU32 Reserved_0x274[0x3]; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 Reserved_0x28C[0x1]; - NvU32 CheckQmdVersion; - NvU32 Reserved_0x294[0x1]; - NvU32 InvalidateSkedCaches; - NvU32 Reserved_0x29C[0x1]; - NvU32 SetShaderSharedMemoryWindowA; - NvU32 SetShaderSharedMemoryWindowB; - NvU32 ScgHysteresisControl; - NvU32 Reserved_0x2AC[0x1]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x3]; - NvU32 SetSkedCacheControl; - NvU32 Reserved_0x2D0[0x5]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 Reserved_0x2F0[0x8]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x1]; - NvU32 SetInlineQmdAddressA; - NvU32 SetInlineQmdAddressB; - NvU32 LoadInlineQmdData[0x40]; - NvU32 Reserved_0x420[0x38]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x84]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x6]; - NvU32 SetShaderLocalMemoryWindowA; - NvU32 SetShaderLocalMemoryWindowB; - NvU32 Reserved_0x7B8[0x177]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x13]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x109]; - NvU32 InvalidateSamplerCacheAll; - NvU32 InvalidateTextureHeaderCacheAll; - NvU32 Reserved_0x1214[0x1D]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x7]; - NvU32 ActivatePerfSettingsForComputeContext; - NvU32 Reserved_0x12AC[0x21]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x46]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BA]; - NvU32 SetTrapHandlerA; - NvU32 SetTrapHandlerB; - NvU32 Reserved_0x2600[0x2]; - NvU32 SetBindlessTexture; - NvU32 Reserved_0x260C[0x33A]; - NvU32 SetShaderPerformanceSnapshotCounterValue[0x8]; - NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8]; - NvU32 EnableShaderPerformanceSnapshotCounter; - NvU32 DisableShaderPerformanceSnapshotCounter; - NvU32 SetShaderPerformanceCounterValueUpper[0x8]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 StartShaderPerformanceCounter; - NvU32 StopShaderPerformanceCounter; - NvU32 SetShaderPerformanceCounterSctlFilter; - NvU32 SetShaderPerformanceCounterCoreMioFilter; - NvU32 Reserved_0x33F0[0x4]; - NvU32 SetMmeShadowScratch[0x8]; -} volta_compute_a_t; - - -#define NVC3C0_SET_OBJECT 0x0000 -#define NVC3C0_SET_OBJECT_CLASS_ID 15:0 -#define NVC3C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVC3C0_NO_OPERATION 0x0100 -#define NVC3C0_NO_OPERATION_V 31:0 - -#define NVC3C0_SET_NOTIFY_A 0x0104 -#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVC3C0_SET_NOTIFY_B 0x0108 -#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVC3C0_NOTIFY 0x010c -#define NVC3C0_NOTIFY_TYPE 31:0 -#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVC3C0_WAIT_FOR_IDLE 0x0110 -#define NVC3C0_WAIT_FOR_IDLE_V 31:0 - -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC3C0_SEND_GO_IDLE 0x013c -#define NVC3C0_SEND_GO_IDLE_V 31:0 - -#define NVC3C0_PM_TRIGGER 0x0140 -#define NVC3C0_PM_TRIGGER_V 31:0 - -#define NVC3C0_PM_TRIGGER_WFI 0x0144 -#define NVC3C0_PM_TRIGGER_WFI_V 31:0 - -#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 -#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 - -#define NVC3C0_FE_ATOMIC_SEQUENCE_END 0x014c -#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V 31:0 - -#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVC3C0_LINE_LENGTH_IN 0x0180 -#define NVC3C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVC3C0_LINE_COUNT 0x0184 -#define NVC3C0_LINE_COUNT_VALUE 31:0 - -#define NVC3C0_OFFSET_OUT_UPPER 0x0188 -#define NVC3C0_OFFSET_OUT_UPPER_VALUE 16:0 - -#define NVC3C0_OFFSET_OUT 0x018c -#define NVC3C0_OFFSET_OUT_VALUE 31:0 - -#define NVC3C0_PITCH_OUT 0x0190 -#define NVC3C0_PITCH_OUT_VALUE 31:0 - -#define NVC3C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVC3C0_SET_DST_WIDTH 0x0198 -#define NVC3C0_SET_DST_WIDTH_V 31:0 - -#define NVC3C0_SET_DST_HEIGHT 0x019c -#define NVC3C0_SET_DST_HEIGHT_V 31:0 - -#define NVC3C0_SET_DST_DEPTH 0x01a0 -#define NVC3C0_SET_DST_DEPTH_V 31:0 - -#define NVC3C0_SET_DST_LAYER 0x01a4 -#define NVC3C0_SET_DST_LAYER_V 31:0 - -#define NVC3C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V 20:0 - -#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 - -#define NVC3C0_LAUNCH_DMA 0x01b0 -#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVC3C0_LOAD_INLINE_DATA 0x01b4 -#define NVC3C0_LOAD_INLINE_DATA_V 31:0 - -#define NVC3C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC3C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC3C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC3C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVC3C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVC3C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVC3C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVC3C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVC3C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVC3C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVC3C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 -#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 - -#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 -#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 - -#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 -#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 - -#define NVC3C0_PERFMON_TRANSFER 0x0210 -#define NVC3C0_PERFMON_TRANSFER_V 31:0 - -#define NVC3C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVC3C0_SET_RESERVED_SW_METHOD00 0x0220 -#define NVC3C0_SET_RESERVED_SW_METHOD00_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD01 0x0224 -#define NVC3C0_SET_RESERVED_SW_METHOD01_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD02 0x0228 -#define NVC3C0_SET_RESERVED_SW_METHOD02_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD03 0x022c -#define NVC3C0_SET_RESERVED_SW_METHOD03_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD04 0x0230 -#define NVC3C0_SET_RESERVED_SW_METHOD04_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD05 0x0234 -#define NVC3C0_SET_RESERVED_SW_METHOD05_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD06 0x0238 -#define NVC3C0_SET_RESERVED_SW_METHOD06_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD07 0x023c -#define NVC3C0_SET_RESERVED_SW_METHOD07_V 31:0 - -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVC3C0_SET_CWD_REF_COUNTER 0x0248 -#define NVC3C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVC3C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVC3C0_SET_RESERVED_SW_METHOD08 0x024c -#define NVC3C0_SET_RESERVED_SW_METHOD08_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD09 0x0250 -#define NVC3C0_SET_RESERVED_SW_METHOD09_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD10 0x0254 -#define NVC3C0_SET_RESERVED_SW_METHOD10_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD11 0x0258 -#define NVC3C0_SET_RESERVED_SW_METHOD11_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD12 0x025c -#define NVC3C0_SET_RESERVED_SW_METHOD12_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD13 0x0260 -#define NVC3C0_SET_RESERVED_SW_METHOD13_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD14 0x0264 -#define NVC3C0_SET_RESERVED_SW_METHOD14_V 31:0 - -#define NVC3C0_SET_RESERVED_SW_METHOD15 0x0268 -#define NVC3C0_SET_RESERVED_SW_METHOD15_V 31:0 - -#define NVC3C0_SET_SCG_CONTROL 0x0270 -#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 -#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 -#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 -#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 -#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 - -#define NVC3C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC3C0_SET_QMD_VERSION 0x0288 -#define NVC3C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC3C0_CHECK_QMD_VERSION 0x0290 -#define NVC3C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC3C0_INVALIDATE_SKED_CACHES 0x0298 -#define NVC3C0_INVALIDATE_SKED_CACHES_V 0:0 - -#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 -#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 -#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC3C0_SCG_HYSTERESIS_CONTROL 0x02a8 -#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 -#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 -#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 -#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 -#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 -#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 - -#define NVC3C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVC3C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVC3C0_SEND_PCAS_A 0x02b4 -#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVC3C0_SEND_PCAS_B 0x02b8 -#define NVC3C0_SEND_PCAS_B_FROM 23:0 -#define NVC3C0_SEND_PCAS_B_DELTA 31:24 - -#define NVC3C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVC3C0_SET_SKED_CACHE_CONTROL 0x02cc -#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 -#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 -#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 - -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVC3C0_SET_SPA_VERSION 0x0310 -#define NVC3C0_SET_SPA_VERSION_MINOR 7:0 -#define NVC3C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVC3C0_SET_INLINE_QMD_ADDRESS_A 0x0318 -#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 - -#define NVC3C0_SET_INLINE_QMD_ADDRESS_B 0x031c -#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 - -#define NVC3C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) -#define NVC3C0_LOAD_INLINE_QMD_DATA_V 31:0 - -#define NVC3C0_SET_FALCON00 0x0500 -#define NVC3C0_SET_FALCON00_V 31:0 - -#define NVC3C0_SET_FALCON01 0x0504 -#define NVC3C0_SET_FALCON01_V 31:0 - -#define NVC3C0_SET_FALCON02 0x0508 -#define NVC3C0_SET_FALCON02_V 31:0 - -#define NVC3C0_SET_FALCON03 0x050c -#define NVC3C0_SET_FALCON03_V 31:0 - -#define NVC3C0_SET_FALCON04 0x0510 -#define NVC3C0_SET_FALCON04_V 31:0 - -#define NVC3C0_SET_FALCON05 0x0514 -#define NVC3C0_SET_FALCON05_V 31:0 - -#define NVC3C0_SET_FALCON06 0x0518 -#define NVC3C0_SET_FALCON06_V 31:0 - -#define NVC3C0_SET_FALCON07 0x051c -#define NVC3C0_SET_FALCON07_V 31:0 - -#define NVC3C0_SET_FALCON08 0x0520 -#define NVC3C0_SET_FALCON08_V 31:0 - -#define NVC3C0_SET_FALCON09 0x0524 -#define NVC3C0_SET_FALCON09_V 31:0 - -#define NVC3C0_SET_FALCON10 0x0528 -#define NVC3C0_SET_FALCON10_V 31:0 - -#define NVC3C0_SET_FALCON11 0x052c -#define NVC3C0_SET_FALCON11_V 31:0 - -#define NVC3C0_SET_FALCON12 0x0530 -#define NVC3C0_SET_FALCON12_V 31:0 - -#define NVC3C0_SET_FALCON13 0x0534 -#define NVC3C0_SET_FALCON13_V 31:0 - -#define NVC3C0_SET_FALCON14 0x0538 -#define NVC3C0_SET_FALCON14_V 31:0 - -#define NVC3C0_SET_FALCON15 0x053c -#define NVC3C0_SET_FALCON15_V 31:0 - -#define NVC3C0_SET_FALCON16 0x0540 -#define NVC3C0_SET_FALCON16_V 31:0 - -#define NVC3C0_SET_FALCON17 0x0544 -#define NVC3C0_SET_FALCON17_V 31:0 - -#define NVC3C0_SET_FALCON18 0x0548 -#define NVC3C0_SET_FALCON18_V 31:0 - -#define NVC3C0_SET_FALCON19 0x054c -#define NVC3C0_SET_FALCON19_V 31:0 - -#define NVC3C0_SET_FALCON20 0x0550 -#define NVC3C0_SET_FALCON20_V 31:0 - -#define NVC3C0_SET_FALCON21 0x0554 -#define NVC3C0_SET_FALCON21_V 31:0 - -#define NVC3C0_SET_FALCON22 0x0558 -#define NVC3C0_SET_FALCON22_V 31:0 - -#define NVC3C0_SET_FALCON23 0x055c -#define NVC3C0_SET_FALCON23_V 31:0 - -#define NVC3C0_SET_FALCON24 0x0560 -#define NVC3C0_SET_FALCON24_V 31:0 - -#define NVC3C0_SET_FALCON25 0x0564 -#define NVC3C0_SET_FALCON25_V 31:0 - -#define NVC3C0_SET_FALCON26 0x0568 -#define NVC3C0_SET_FALCON26_V 31:0 - -#define NVC3C0_SET_FALCON27 0x056c -#define NVC3C0_SET_FALCON27_V 31:0 - -#define NVC3C0_SET_FALCON28 0x0570 -#define NVC3C0_SET_FALCON28_V 31:0 - -#define NVC3C0_SET_FALCON29 0x0574 -#define NVC3C0_SET_FALCON29_V 31:0 - -#define NVC3C0_SET_FALCON30 0x0578 -#define NVC3C0_SET_FALCON30_V 31:0 - -#define NVC3C0_SET_FALCON31 0x057c -#define NVC3C0_SET_FALCON31_V 31:0 - -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 - -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 -#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC3C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVC3C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 - -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 - -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 -#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 -#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 -#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 - -#define NVC3C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVC3C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVC3C0_SET_RENDER_ENABLE_A 0x1550 -#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC3C0_SET_RENDER_ENABLE_B 0x1554 -#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC3C0_SET_RENDER_ENABLE_C 0x1558 -#define NVC3C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC3C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC3C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC3C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVC3C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC3C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC3C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVC3C0_PIPE_NOP 0x1a2c -#define NVC3C0_PIPE_NOP_V 31:0 - -#define NVC3C0_SET_SPARE00 0x1a30 -#define NVC3C0_SET_SPARE00_V 31:0 - -#define NVC3C0_SET_SPARE01 0x1a34 -#define NVC3C0_SET_SPARE01_V 31:0 - -#define NVC3C0_SET_SPARE02 0x1a38 -#define NVC3C0_SET_SPARE02_V 31:0 - -#define NVC3C0_SET_SPARE03 0x1a3c -#define NVC3C0_SET_SPARE03_V 31:0 - -#define NVC3C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC3C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC3C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC3C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 - -#define NVC3C0_SET_TRAP_HANDLER_A 0x25f8 -#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 - -#define NVC3C0_SET_TRAP_HANDLER_B 0x25fc -#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 - -#define NVC3C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) -#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) -#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 - -#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 -#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 - -#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 -#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 -#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 -#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 - -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec -#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 - -#define NVC3C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVC3C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_volta_compute_a_h_ */ diff --git a/Compute-Class-Methods/clc5c0.h b/Compute-Class-Methods/clc5c0.h deleted file mode 100644 index 3d0fd54..0000000 --- a/Compute-Class-Methods/clc5c0.h +++ /dev/null @@ -1,942 +0,0 @@ -/* - * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _cl_turing_compute_a_h_ -#define _cl_turing_compute_a_h_ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */ - -#include "nvtypes.h" - -#define TURING_COMPUTE_A 0xC5C0 - -typedef volatile struct turing_compute_a_struct { - NvU32 SetObject; - NvU32 Reserved_0x04[0x3F]; - NvU32 NoOperation; - NvU32 SetNotifyA; - NvU32 SetNotifyB; - NvU32 Notify; - NvU32 WaitForIdle; - NvU32 Reserved_0x114[0x7]; - NvU32 SetGlobalRenderEnableA; - NvU32 SetGlobalRenderEnableB; - NvU32 SetGlobalRenderEnableC; - NvU32 SendGoIdle; - NvU32 PmTrigger; - NvU32 PmTriggerWfi; - NvU32 FeAtomicSequenceBegin; - NvU32 FeAtomicSequenceEnd; - NvU32 SetInstrumentationMethodHeader; - NvU32 SetInstrumentationMethodData; - NvU32 Reserved_0x158[0xA]; - NvU32 LineLengthIn; - NvU32 LineCount; - NvU32 OffsetOutUpper; - NvU32 OffsetOut; - NvU32 PitchOut; - NvU32 SetDstBlockSize; - NvU32 SetDstWidth; - NvU32 SetDstHeight; - NvU32 SetDstDepth; - NvU32 SetDstLayer; - NvU32 SetDstOriginBytesX; - NvU32 SetDstOriginSamplesY; - NvU32 LaunchDma; - NvU32 LoadInlineData; - NvU32 Reserved_0x1B8[0x9]; - NvU32 SetI2mSemaphoreA; - NvU32 SetI2mSemaphoreB; - NvU32 SetI2mSemaphoreC; - NvU32 SetSmScgControl; - NvU32 Reserved_0x1EC[0x1]; - NvU32 SetI2mSpareNoop00; - NvU32 SetI2mSpareNoop01; - NvU32 SetI2mSpareNoop02; - NvU32 SetI2mSpareNoop03; - NvU32 SetValidSpanOverflowAreaA; - NvU32 SetValidSpanOverflowAreaB; - NvU32 SetValidSpanOverflowAreaC; - NvU32 Reserved_0x20C[0x1]; - NvU32 PerfmonTransfer; - NvU32 SetQmdVirtualizationBaseA; - NvU32 SetQmdVirtualizationBaseB; - NvU32 InvalidateShaderCaches; - NvU32 SetReservedSwMethod00; - NvU32 SetReservedSwMethod01; - NvU32 SetReservedSwMethod02; - NvU32 SetReservedSwMethod03; - NvU32 SetReservedSwMethod04; - NvU32 SetReservedSwMethod05; - NvU32 SetReservedSwMethod06; - NvU32 SetReservedSwMethod07; - NvU32 Reserved_0x240[0x1]; - NvU32 InvalidateTextureHeaderCacheNoWfi; - NvU32 SetCwdRefCounter; - NvU32 SetReservedSwMethod08; - NvU32 SetReservedSwMethod09; - NvU32 SetReservedSwMethod10; - NvU32 SetReservedSwMethod11; - NvU32 SetReservedSwMethod12; - NvU32 SetReservedSwMethod13; - NvU32 SetReservedSwMethod14; - NvU32 SetReservedSwMethod15; - NvU32 Reserved_0x26C[0x1]; - NvU32 SetScgControl; - NvU32 Reserved_0x274[0x3]; - NvU32 SetComputeClassVersion; - NvU32 CheckComputeClassVersion; - NvU32 SetQmdVersion; - NvU32 Reserved_0x28C[0x1]; - NvU32 CheckQmdVersion; - NvU32 Reserved_0x294[0x1]; - NvU32 InvalidateSkedCaches; - NvU32 SetQmdVirtualizationControl; - NvU32 SetShaderSharedMemoryWindowA; - NvU32 SetShaderSharedMemoryWindowB; - NvU32 ScgHysteresisControl; - NvU32 Reserved_0x2AC[0x1]; - NvU32 SetCwdSlotCount; - NvU32 SendPcasA; - NvU32 SendPcasB; - NvU32 SendSignalingPcasB; - NvU32 Reserved_0x2C0[0x3]; - NvU32 SetSkedCacheControl; - NvU32 Reserved_0x2D0[0x5]; - NvU32 SetShaderLocalMemoryNonThrottledA; - NvU32 SetShaderLocalMemoryNonThrottledB; - NvU32 SetShaderLocalMemoryNonThrottledC; - NvU32 Reserved_0x2F0[0x8]; - NvU32 SetSpaVersion; - NvU32 Reserved_0x314[0x1]; - NvU32 SetInlineQmdAddressA; - NvU32 SetInlineQmdAddressB; - NvU32 LoadInlineQmdData[0x40]; - NvU32 Reserved_0x420[0x38]; - NvU32 SetFalcon00; - NvU32 SetFalcon01; - NvU32 SetFalcon02; - NvU32 SetFalcon03; - NvU32 SetFalcon04; - NvU32 SetFalcon05; - NvU32 SetFalcon06; - NvU32 SetFalcon07; - NvU32 SetFalcon08; - NvU32 SetFalcon09; - NvU32 SetFalcon10; - NvU32 SetFalcon11; - NvU32 SetFalcon12; - NvU32 SetFalcon13; - NvU32 SetFalcon14; - NvU32 SetFalcon15; - NvU32 SetFalcon16; - NvU32 SetFalcon17; - NvU32 SetFalcon18; - NvU32 SetFalcon19; - NvU32 SetFalcon20; - NvU32 SetFalcon21; - NvU32 SetFalcon22; - NvU32 SetFalcon23; - NvU32 SetFalcon24; - NvU32 SetFalcon25; - NvU32 SetFalcon26; - NvU32 SetFalcon27; - NvU32 SetFalcon28; - NvU32 SetFalcon29; - NvU32 SetFalcon30; - NvU32 SetFalcon31; - NvU32 Reserved_0x580[0x84]; - NvU32 SetShaderLocalMemoryA; - NvU32 SetShaderLocalMemoryB; - NvU32 Reserved_0x798[0x6]; - NvU32 SetShaderLocalMemoryWindowA; - NvU32 SetShaderLocalMemoryWindowB; - NvU32 Reserved_0x7B8[0x177]; - NvU32 SetShaderCacheControl; - NvU32 Reserved_0xD98[0x2]; - NvU32 SetScgComputeSchedulingParameters[0x10]; - NvU32 Reserved_0xDE0[0x1]; - NvU32 SetSmTimeoutInterval; - NvU32 Reserved_0xDE8[0x128]; - NvU32 InvalidateTextureDataCacheNoWfi; - NvU32 Reserved_0x128C[0x7]; - NvU32 ActivatePerfSettingsForComputeContext; - NvU32 Reserved_0x12AC[0x21]; - NvU32 InvalidateSamplerCache; - NvU32 InvalidateTextureHeaderCache; - NvU32 InvalidateTextureDataCache; - NvU32 Reserved_0x133C[0x3A]; - NvU32 InvalidateSamplerCacheNoWfi; - NvU32 Reserved_0x1428[0x40]; - NvU32 SetShaderExceptions; - NvU32 Reserved_0x152C[0x9]; - NvU32 SetRenderEnableA; - NvU32 SetRenderEnableB; - NvU32 SetRenderEnableC; - NvU32 SetTexSamplerPoolA; - NvU32 SetTexSamplerPoolB; - NvU32 SetTexSamplerPoolC; - NvU32 Reserved_0x1568[0x3]; - NvU32 SetTexHeaderPoolA; - NvU32 SetTexHeaderPoolB; - NvU32 SetTexHeaderPoolC; - NvU32 Reserved_0x1580[0x46]; - NvU32 InvalidateShaderCachesNoWfi; - NvU32 Reserved_0x169C[0xAA]; - NvU32 SetRenderEnableOverride; - NvU32 Reserved_0x1948[0x37]; - NvU32 Reserved_0x1A28[0x1]; - NvU32 PipeNop; - NvU32 SetSpare00; - NvU32 SetSpare01; - NvU32 SetSpare02; - NvU32 SetSpare03; - NvU32 Reserved_0x1A40[0x30]; - NvU32 SetReportSemaphoreA; - NvU32 SetReportSemaphoreB; - NvU32 SetReportSemaphoreC; - NvU32 SetReportSemaphoreD; - NvU32 Reserved_0x1B10[0x2BA]; - NvU32 SetTrapHandlerA; - NvU32 SetTrapHandlerB; - NvU32 Reserved_0x2600[0x2]; - NvU32 SetBindlessTexture; - NvU32 Reserved_0x260C[0x33A]; - NvU32 SetShaderPerformanceSnapshotCounterValue[0x8]; - NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8]; - NvU32 EnableShaderPerformanceSnapshotCounter; - NvU32 DisableShaderPerformanceSnapshotCounter; - NvU32 SetShaderPerformanceCounterValueUpper[0x8]; - NvU32 SetShaderPerformanceCounterValue[0x8]; - NvU32 SetShaderPerformanceCounterEvent[0x8]; - NvU32 SetShaderPerformanceCounterControlA[0x8]; - NvU32 SetShaderPerformanceCounterControlB[0x8]; - NvU32 SetShaderPerformanceCounterTrapControl; - NvU32 StartShaderPerformanceCounter; - NvU32 StopShaderPerformanceCounter; - NvU32 SetShaderPerformanceCounterSctlFilter; - NvU32 SetShaderPerformanceCounterCoreMioFilter; - NvU32 Reserved_0x33F0[0x4]; - NvU32 SetMmeShadowScratch[0x8]; -} turing_compute_a_t; - - -#define NVC5C0_SET_OBJECT 0x0000 -#define NVC5C0_SET_OBJECT_CLASS_ID 15:0 -#define NVC5C0_SET_OBJECT_ENGINE_ID 20:16 - -#define NVC5C0_NO_OPERATION 0x0100 -#define NVC5C0_NO_OPERATION_V 31:0 - -#define NVC5C0_SET_NOTIFY_A 0x0104 -#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 - -#define NVC5C0_SET_NOTIFY_B 0x0108 -#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 - -#define NVC5C0_NOTIFY 0x010c -#define NVC5C0_NOTIFY_TYPE 31:0 -#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 -#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 - -#define NVC5C0_WAIT_FOR_IDLE 0x0110 -#define NVC5C0_WAIT_FOR_IDLE_V 31:0 - -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC5C0_SEND_GO_IDLE 0x013c -#define NVC5C0_SEND_GO_IDLE_V 31:0 - -#define NVC5C0_PM_TRIGGER 0x0140 -#define NVC5C0_PM_TRIGGER_V 31:0 - -#define NVC5C0_PM_TRIGGER_WFI 0x0144 -#define NVC5C0_PM_TRIGGER_WFI_V 31:0 - -#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 -#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 - -#define NVC5C0_FE_ATOMIC_SEQUENCE_END 0x014c -#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V 31:0 - -#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 -#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 - -#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 -#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 - -#define NVC5C0_LINE_LENGTH_IN 0x0180 -#define NVC5C0_LINE_LENGTH_IN_VALUE 31:0 - -#define NVC5C0_LINE_COUNT 0x0184 -#define NVC5C0_LINE_COUNT_VALUE 31:0 - -#define NVC5C0_OFFSET_OUT_UPPER 0x0188 -#define NVC5C0_OFFSET_OUT_UPPER_VALUE 16:0 - -#define NVC5C0_OFFSET_OUT 0x018c -#define NVC5C0_OFFSET_OUT_VALUE 31:0 - -#define NVC5C0_PITCH_OUT 0x0190 -#define NVC5C0_PITCH_OUT_VALUE 31:0 - -#define NVC5C0_SET_DST_BLOCK_SIZE 0x0194 -#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 -#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 -#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 -#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 -#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 -#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 -#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 -#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 -#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 -#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 -#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 -#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 -#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 -#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 -#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 -#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 - -#define NVC5C0_SET_DST_WIDTH 0x0198 -#define NVC5C0_SET_DST_WIDTH_V 31:0 - -#define NVC5C0_SET_DST_HEIGHT 0x019c -#define NVC5C0_SET_DST_HEIGHT_V 31:0 - -#define NVC5C0_SET_DST_DEPTH 0x01a0 -#define NVC5C0_SET_DST_DEPTH_V 31:0 - -#define NVC5C0_SET_DST_LAYER 0x01a4 -#define NVC5C0_SET_DST_LAYER_V 31:0 - -#define NVC5C0_SET_DST_ORIGIN_BYTES_X 0x01a8 -#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V 20:0 - -#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac -#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 - -#define NVC5C0_LAUNCH_DMA 0x01b0 -#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 -#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 -#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 -#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 -#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 -#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 -#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 -#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 -#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 -#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 -#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 -#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 -#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 -#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 -#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP 15:13 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 -#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 -#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 -#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 -#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 - -#define NVC5C0_LOAD_INLINE_DATA 0x01b4 -#define NVC5C0_LOAD_INLINE_DATA_V 31:0 - -#define NVC5C0_SET_I2M_SEMAPHORE_A 0x01dc -#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC5C0_SET_I2M_SEMAPHORE_B 0x01e0 -#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC5C0_SET_I2M_SEMAPHORE_C 0x01e4 -#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC5C0_SET_SM_SCG_CONTROL 0x01e8 -#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 -#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 -#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 - -#define NVC5C0_SET_I2M_SPARE_NOOP00 0x01f0 -#define NVC5C0_SET_I2M_SPARE_NOOP00_V 31:0 - -#define NVC5C0_SET_I2M_SPARE_NOOP01 0x01f4 -#define NVC5C0_SET_I2M_SPARE_NOOP01_V 31:0 - -#define NVC5C0_SET_I2M_SPARE_NOOP02 0x01f8 -#define NVC5C0_SET_I2M_SPARE_NOOP02_V 31:0 - -#define NVC5C0_SET_I2M_SPARE_NOOP03 0x01fc -#define NVC5C0_SET_I2M_SPARE_NOOP03_V 31:0 - -#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 -#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 - -#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 -#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 - -#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 -#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 - -#define NVC5C0_PERFMON_TRANSFER 0x0210 -#define NVC5C0_PERFMON_TRANSFER_V 31:0 - -#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 -#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 - -#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 -#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 - -#define NVC5C0_INVALIDATE_SHADER_CACHES 0x021c -#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 -#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 -#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA 4:4 -#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 -#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 -#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 -#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 -#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 -#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 -#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 - -#define NVC5C0_SET_RESERVED_SW_METHOD00 0x0220 -#define NVC5C0_SET_RESERVED_SW_METHOD00_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD01 0x0224 -#define NVC5C0_SET_RESERVED_SW_METHOD01_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD02 0x0228 -#define NVC5C0_SET_RESERVED_SW_METHOD02_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD03 0x022c -#define NVC5C0_SET_RESERVED_SW_METHOD03_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD04 0x0230 -#define NVC5C0_SET_RESERVED_SW_METHOD04_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD05 0x0234 -#define NVC5C0_SET_RESERVED_SW_METHOD05_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD06 0x0238 -#define NVC5C0_SET_RESERVED_SW_METHOD06_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD07 0x023c -#define NVC5C0_SET_RESERVED_SW_METHOD07_V 31:0 - -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 - -#define NVC5C0_SET_CWD_REF_COUNTER 0x0248 -#define NVC5C0_SET_CWD_REF_COUNTER_SELECT 5:0 -#define NVC5C0_SET_CWD_REF_COUNTER_VALUE 23:8 - -#define NVC5C0_SET_RESERVED_SW_METHOD08 0x024c -#define NVC5C0_SET_RESERVED_SW_METHOD08_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD09 0x0250 -#define NVC5C0_SET_RESERVED_SW_METHOD09_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD10 0x0254 -#define NVC5C0_SET_RESERVED_SW_METHOD10_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD11 0x0258 -#define NVC5C0_SET_RESERVED_SW_METHOD11_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD12 0x025c -#define NVC5C0_SET_RESERVED_SW_METHOD12_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD13 0x0260 -#define NVC5C0_SET_RESERVED_SW_METHOD13_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD14 0x0264 -#define NVC5C0_SET_RESERVED_SW_METHOD14_V 31:0 - -#define NVC5C0_SET_RESERVED_SW_METHOD15 0x0268 -#define NVC5C0_SET_RESERVED_SW_METHOD15_V 31:0 - -#define NVC5C0_SET_SCG_CONTROL 0x0270 -#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 -#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 -#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 -#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 -#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 - -#define NVC5C0_SET_COMPUTE_CLASS_VERSION 0x0280 -#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 -#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 -#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC5C0_SET_QMD_VERSION 0x0288 -#define NVC5C0_SET_QMD_VERSION_CURRENT 15:0 -#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC5C0_CHECK_QMD_VERSION 0x0290 -#define NVC5C0_CHECK_QMD_VERSION_CURRENT 15:0 -#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 - -#define NVC5C0_INVALIDATE_SKED_CACHES 0x0298 -#define NVC5C0_INVALIDATE_SKED_CACHES_V 0:0 - -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 - -#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 -#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 -#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC5C0_SCG_HYSTERESIS_CONTROL 0x02a8 -#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 -#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 -#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 -#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 -#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 -#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 - -#define NVC5C0_SET_CWD_SLOT_COUNT 0x02b0 -#define NVC5C0_SET_CWD_SLOT_COUNT_V 7:0 - -#define NVC5C0_SEND_PCAS_A 0x02b4 -#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 - -#define NVC5C0_SEND_PCAS_B 0x02b8 -#define NVC5C0_SEND_PCAS_B_FROM 23:0 -#define NVC5C0_SEND_PCAS_B_DELTA 31:24 - -#define NVC5C0_SEND_SIGNALING_PCAS_B 0x02bc -#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 -#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 -#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 -#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 -#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 -#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 - -#define NVC5C0_SET_SKED_CACHE_CONTROL 0x02cc -#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 -#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 -#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 - -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 - -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 - -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 - -#define NVC5C0_SET_SPA_VERSION 0x0310 -#define NVC5C0_SET_SPA_VERSION_MINOR 7:0 -#define NVC5C0_SET_SPA_VERSION_MAJOR 15:8 - -#define NVC5C0_SET_INLINE_QMD_ADDRESS_A 0x0318 -#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 - -#define NVC5C0_SET_INLINE_QMD_ADDRESS_B 0x031c -#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 - -#define NVC5C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) -#define NVC5C0_LOAD_INLINE_QMD_DATA_V 31:0 - -#define NVC5C0_SET_FALCON00 0x0500 -#define NVC5C0_SET_FALCON00_V 31:0 - -#define NVC5C0_SET_FALCON01 0x0504 -#define NVC5C0_SET_FALCON01_V 31:0 - -#define NVC5C0_SET_FALCON02 0x0508 -#define NVC5C0_SET_FALCON02_V 31:0 - -#define NVC5C0_SET_FALCON03 0x050c -#define NVC5C0_SET_FALCON03_V 31:0 - -#define NVC5C0_SET_FALCON04 0x0510 -#define NVC5C0_SET_FALCON04_V 31:0 - -#define NVC5C0_SET_FALCON05 0x0514 -#define NVC5C0_SET_FALCON05_V 31:0 - -#define NVC5C0_SET_FALCON06 0x0518 -#define NVC5C0_SET_FALCON06_V 31:0 - -#define NVC5C0_SET_FALCON07 0x051c -#define NVC5C0_SET_FALCON07_V 31:0 - -#define NVC5C0_SET_FALCON08 0x0520 -#define NVC5C0_SET_FALCON08_V 31:0 - -#define NVC5C0_SET_FALCON09 0x0524 -#define NVC5C0_SET_FALCON09_V 31:0 - -#define NVC5C0_SET_FALCON10 0x0528 -#define NVC5C0_SET_FALCON10_V 31:0 - -#define NVC5C0_SET_FALCON11 0x052c -#define NVC5C0_SET_FALCON11_V 31:0 - -#define NVC5C0_SET_FALCON12 0x0530 -#define NVC5C0_SET_FALCON12_V 31:0 - -#define NVC5C0_SET_FALCON13 0x0534 -#define NVC5C0_SET_FALCON13_V 31:0 - -#define NVC5C0_SET_FALCON14 0x0538 -#define NVC5C0_SET_FALCON14_V 31:0 - -#define NVC5C0_SET_FALCON15 0x053c -#define NVC5C0_SET_FALCON15_V 31:0 - -#define NVC5C0_SET_FALCON16 0x0540 -#define NVC5C0_SET_FALCON16_V 31:0 - -#define NVC5C0_SET_FALCON17 0x0544 -#define NVC5C0_SET_FALCON17_V 31:0 - -#define NVC5C0_SET_FALCON18 0x0548 -#define NVC5C0_SET_FALCON18_V 31:0 - -#define NVC5C0_SET_FALCON19 0x054c -#define NVC5C0_SET_FALCON19_V 31:0 - -#define NVC5C0_SET_FALCON20 0x0550 -#define NVC5C0_SET_FALCON20_V 31:0 - -#define NVC5C0_SET_FALCON21 0x0554 -#define NVC5C0_SET_FALCON21_V 31:0 - -#define NVC5C0_SET_FALCON22 0x0558 -#define NVC5C0_SET_FALCON22_V 31:0 - -#define NVC5C0_SET_FALCON23 0x055c -#define NVC5C0_SET_FALCON23_V 31:0 - -#define NVC5C0_SET_FALCON24 0x0560 -#define NVC5C0_SET_FALCON24_V 31:0 - -#define NVC5C0_SET_FALCON25 0x0564 -#define NVC5C0_SET_FALCON25_V 31:0 - -#define NVC5C0_SET_FALCON26 0x0568 -#define NVC5C0_SET_FALCON26_V 31:0 - -#define NVC5C0_SET_FALCON27 0x056c -#define NVC5C0_SET_FALCON27_V 31:0 - -#define NVC5C0_SET_FALCON28 0x0570 -#define NVC5C0_SET_FALCON28_V 31:0 - -#define NVC5C0_SET_FALCON29 0x0574 -#define NVC5C0_SET_FALCON29_V 31:0 - -#define NVC5C0_SET_FALCON30 0x0578 -#define NVC5C0_SET_FALCON30_V 31:0 - -#define NVC5C0_SET_FALCON31 0x057c -#define NVC5C0_SET_FALCON31_V 31:0 - -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 - -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 - -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 - -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 -#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 - -#define NVC5C0_SET_SHADER_CACHE_CONTROL 0x0d94 -#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 -#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 - -#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) -#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 - -#define NVC5C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 -#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 - -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 - -#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 -#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 -#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 -#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 - -#define NVC5C0_INVALIDATE_SAMPLER_CACHE 0x1330 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 - -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 -#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 - -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 -#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 - -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 -#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 - -#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 -#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 - -#define NVC5C0_SET_RENDER_ENABLE_A 0x1550 -#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 - -#define NVC5C0_SET_RENDER_ENABLE_B 0x1554 -#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 - -#define NVC5C0_SET_RENDER_ENABLE_C 0x1558 -#define NVC5C0_SET_RENDER_ENABLE_C_MODE 2:0 -#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 -#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 -#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 -#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 -#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 - -#define NVC5C0_SET_TEX_SAMPLER_POOL_A 0x155c -#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC5C0_SET_TEX_SAMPLER_POOL_B 0x1560 -#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC5C0_SET_TEX_SAMPLER_POOL_C 0x1564 -#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 - -#define NVC5C0_SET_TEX_HEADER_POOL_A 0x1574 -#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 - -#define NVC5C0_SET_TEX_HEADER_POOL_B 0x1578 -#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 - -#define NVC5C0_SET_TEX_HEADER_POOL_C 0x157c -#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 - -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 -#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 - -#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 -#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 -#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 -#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 -#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 - -#define NVC5C0_PIPE_NOP 0x1a2c -#define NVC5C0_PIPE_NOP_V 31:0 - -#define NVC5C0_SET_SPARE00 0x1a30 -#define NVC5C0_SET_SPARE00_V 31:0 - -#define NVC5C0_SET_SPARE01 0x1a34 -#define NVC5C0_SET_SPARE01_V 31:0 - -#define NVC5C0_SET_SPARE02 0x1a38 -#define NVC5C0_SET_SPARE02_V 31:0 - -#define NVC5C0_SET_SPARE03 0x1a3c -#define NVC5C0_SET_SPARE03_V 31:0 - -#define NVC5C0_SET_REPORT_SEMAPHORE_A 0x1b00 -#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 - -#define NVC5C0_SET_REPORT_SEMAPHORE_B 0x1b04 -#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 - -#define NVC5C0_SET_REPORT_SEMAPHORE_C 0x1b08 -#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 - -#define NVC5C0_SET_REPORT_SEMAPHORE_D 0x1b0c -#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 -#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 - -#define NVC5C0_SET_TRAP_HANDLER_A 0x25f8 -#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 - -#define NVC5C0_SET_TRAP_HANDLER_B 0x25fc -#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 - -#define NVC5C0_SET_BINDLESS_TEXTURE 0x2608 -#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) -#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) -#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 - -#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 -#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 - -#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 -#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 - -#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 -#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 -#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 - -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec -#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 - -#define NVC5C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) -#define NVC5C0_SET_MME_SHADOW_SCRATCH_V 31:0 - -#endif /* _cl_turing_compute_a_h_ */ diff --git a/Compute-Class-Methods/index.html b/Compute-Class-Methods/index.html deleted file mode 100644 index 4281791..0000000 --- a/Compute-Class-Methods/index.html +++ /dev/null @@ -1,18 +0,0 @@ -<html> - <head><title>Compute-Class-Methods</title></head> - <body> - <h1>Compute-Class-Methods</h1> - <a href="cl50c0.h">cl50c0.h</a><br/> - <a href="cl85c0.h">cl85c0.h</a><br/> - <a href="cl90c0.h">cl90c0.h</a><br/> - <a href="cl91c0.h">cl91c0.h</a><br/> - <a href="cla0c0.h">cla0c0.h</a><br/> - <a href="cla1c0.h">cla1c0.h</a><br/> - <a href="clb0c0.h">clb0c0.h</a><br/> - <a href="clb1c0.h">clb1c0.h</a><br/> - <a href="clc0c0.h">clc0c0.h</a><br/> - <a href="clc1c0.h">clc1c0.h</a><br/> - <a href="clc3c0.h">clc3c0.h</a><br/> - <a href="clc5c0.h">clc5c0.h</a><br/> - </body> -</html> |