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| author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:38:10 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:41:07 +0800 |
| commit | 08dd4564b1f5c3258caf6bfc4bdc77ead1b042d6 (patch) | |
| tree | 8c22427201972800453e6da9b8175e2bf730dc40 | |
| parent | 1de6c9a59765f804ba40ac69fb12220e43734115 (diff) | |
| download | uext4-08dd4564b1f5c3258caf6bfc4bdc77ead1b042d6.tar.xz | |
fix ARCH_DMA_MINALIGN mess
| -rw-r--r-- | arch/arm/include/asm/cache.h | 4 | ||||
| -rw-r--r-- | ext4_common.h | 3 | ||||
| -rw-r--r-- | include/memalign.h | 24 |
3 files changed, 5 insertions, 26 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 950ec1e..57e2149 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -47,6 +47,10 @@ void dram_bank_mmu_setup(int bank); * value than found in the L1 cache but this is OK to use in terms of * alignment. */ +#ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 /* should be enough */ +#endif #endif /* _ASM_CACHE_H */ diff --git a/ext4_common.h b/ext4_common.h index 238ff63..a3ac298 100644 --- a/ext4_common.h +++ b/ext4_common.h @@ -24,6 +24,7 @@ #include <ext4fs.h> #include <malloc.h> #include <linux/errno.h> +#include <asm/cache.h> #if defined(CONFIG_EXT4_WRITE) #include "ext4_journal.h" #include "crc16.h" @@ -40,8 +41,6 @@ #define SUPERBLOCK_SIZE 1024 #define F_FILE 1 -#define ARCH_DMA_MINALIGN 64 /* should be ok for all architectures */ - #ifdef DEBUG_PRINTF #define dbg_printf printf #else diff --git a/include/memalign.h b/include/memalign.h index 24d9da7..2f8a02b 100644 --- a/include/memalign.h +++ b/include/memalign.h @@ -93,30 +93,6 @@ #define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) -/** - * malloc_cache_aligned() - allocate a memory region aligned to cache line size - * - * This allocates memory at a cache-line boundary. The amount allocated may - * be larger than requested as it is rounded up to the nearest multiple of the - * cache-line size. This ensured that subsequent cache operations on this - * memory (flush, invalidate) will not affect subsequently allocated regions. - * - * @size: Minimum number of bytes to allocate - * - * @return pointer to new memory region, or NULL if there is no more memory - * available. - */ - -/* set ARCH_DMA_MINALIGN to 64, good for all architectures */ -#ifdef ARCH_DMA_MINALIGN -#undef ARCH_DMA_MINALIGN -#endif -#define ARCH_DMA_MINALIGN 64 - -static inline void *malloc_cache_aligned(size_t size) -{ - return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); -} #endif #endif /* __ALIGNMEM_H */ |