diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:43:26 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:43:26 +0800 |
| commit | a899a6c0ed9a3066557fb170850f977b6bd7366f (patch) | |
| tree | 78f7b1166fc1bd0265bcb61990130479528b09c4 | |
| parent | 1a691f101632955a994a0198fc5498b108e97fbc (diff) | |
| download | uext4-a899a6c0ed9a3066557fb170850f977b6bd7366f.tar.xz | |
rm arch/arm/include/asm/arch-*
558 files changed, 0 insertions, 92575 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h deleted file mode 100644 index 493be64..0000000 --- a/arch/arm/include/asm/arch-am33xx/chilisom.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Grinn - */ - -#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__ -#define __ARCH_ARM_MACH_CHILISOM_SOM_H__ - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -void chilisom_enable_pin_mux(void); -void chilisom_spl_board_init(void); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h deleted file mode 100644 index 6579cc0..0000000 --- a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * clk-synthesizer.h - * - * Clock synthesizer header - * - * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __CLK_SYNTHESIZER_H -#define __CLK_SYNTHESIZER_H - -#include <common.h> - -#define CLK_SYNTHESIZER_ID_REG 0x0 -#define CLK_SYNTHESIZER_XCSEL 0x05 -#define CLK_SYNTHESIZER_MUX_REG 0x14 -#define CLK_SYNTHESIZER_PDIV2_REG 0x16 -#define CLK_SYNTHESIZER_PDIV3_REG 0x17 - -#define CLK_SYNTHESIZER_BYTE_MODE 0x80 - -/** - * struct clk_synth: This structure holds data neeed for configuring - * for clock synthesizer. - * @id: The id of synthesizer - * @capacitor: value of the capacitor attached - * @mux: mux settings. - * @pdiv2: Div to be applied to second output - * @pdiv3: Div to be applied to third output - */ -struct clk_synth { - u32 id; - u32 capacitor; - u32 mux; - u32 pdiv2; - u32 pdiv3; -}; - -int setup_clock_synthesizer(struct clk_synth *data); - -#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h deleted file mode 100644 index dc7a9b1..0000000 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * clock.h - * - * clock header - * - * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef _CLOCKS_H_ -#define _CLOCKS_H_ - -#include <asm/arch/clocks_am33xx.h> -#include <asm/arch/hardware.h> - -#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) -#include <asm/arch/clock_ti81xx.h> -#endif - -#define LDELAY 1000000 - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 -#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) -#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13) -#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) -#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15) -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F - -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 m4; - s8 m5; - s8 m6; -}; - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_m4_dpll; - u32 cm_div_m5_dpll; - u32 cm_div_m6_dpll; -}; - -extern const struct dpll_regs dpll_mpu_regs; -extern const struct dpll_regs dpll_core_regs; -extern const struct dpll_regs dpll_per_regs; -extern const struct dpll_regs dpll_ddr_regs; -extern const struct dpll_regs dpll_disp_regs; -extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; -extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; -extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; -extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ]; -extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ]; -extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ]; - -extern struct cm_wkuppll *const cmwkup; - -const struct dpll_params *get_dpll_mpu_params(void); -const struct dpll_params *get_dpll_core_params(void); -const struct dpll_params *get_dpll_per_params(void); -const struct dpll_params *get_dpll_ddr_params(void); -void scale_vcores(void); -void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); -void prcm_init(void); -void enable_basic_clocks(void); - -void rtc_only_update_board_type(u32 btype); -u32 rtc_only_get_board_type(void); -void rtc_only_prcm_init(void); -void rtc_only_enable_basic_clocks(void); - -void do_enable_clocks(u32 *const *, u32 *const *, u8); -void do_disable_clocks(u32 *const *, u32 *const *, u8); - -void set_mpu_spreadspectrum(int permille); -#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h deleted file mode 100644 index f069922..0000000 --- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * ti81xx.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - */ - -#ifndef _CLOCK_TI81XX_H_ -#define _CLOCK_TI81XX_H_ - -#define PRCM_MOD_EN 0x2 - -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkstctrl; -#elif defined(CONFIG_TI816X) - unsigned int ocmc1clkstctrl; -#endif - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; -#if defined(CONFIG_TI814X) - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; -#elif defined(CONFIG_TI816X) - unsigned int resv1[1]; - unsigned int timer1clkctrl; - unsigned int timer2clkctrl; - unsigned int timer3clkctrl; - unsigned int timer4clkctrl; - unsigned int timer5clkctrl; - unsigned int timer6clkctrl; - unsigned int timer7clkctrl; -#endif - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv3[2]; -#elif defined(CONFIG_TI816X) - unsigned int resv3[1]; - unsigned int sdioclkctrl; -#endif - unsigned int ocmc0clkctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkctrl; -#elif defined(CONFIG_TI816X) - unsigned int ocmc1clkctrl; -#endif - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; -#if defined(CONFIG_TI814X) - unsigned int debugssclkctrl; -#elif defined(CONFIG_TI816X) - unsigned int resv6[1]; -#endif - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv6[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -#elif defined(CONFIG_TI816X) - unsigned int sr0clkctrl; - unsigned int sr1clkctrl; -#endif -}; - -#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h deleted file mode 100644 index e5ad507..0000000 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * clocks_am33xx.h - * - * AM33xx clock define - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef _CLOCKS_AM33XX_H_ -#define _CLOCKS_AM33XX_H_ - -/* MAIN PLL Fdll supported frequencies */ -#define MPUPLL_M_1000 1000 -#define MPUPLL_M_800 800 -#define MPUPLL_M_720 720 -#define MPUPLL_M_600 600 -#define MPUPLL_M_500 500 -#define MPUPLL_M_300 300 - -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -#define CM_DLL_CTRL_NO_OVERRIDE 0x0 -#define CM_DLL_READYST 0x4 - -#define NUM_OPPS 6 - -extern void enable_dmm_clocks(void); -extern void enable_emif_clocks(void); -extern const struct dpll_params dpll_core_opp100; -extern struct dpll_params dpll_mpu_opp100; - -#endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h deleted file mode 100644 index 9b819b0..0000000 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ /dev/null @@ -1,611 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * cpu.h - * - * AM33xx specific header file - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef _AM33XX_CPU_H -#define _AM33XX_CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <asm/arch/hardware.h> - -#define CL_BIT(x) (0 << x) - -/* Timer register bits */ -#define TCLR_ST BIT(0) /* Start=1 Stop=0 */ -#define TCLR_AR BIT(1) /* Auto reload */ -#define TCLR_PRE BIT(5) /* Pre-scaler enable */ -#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ -#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ -#define TCLR_CE BIT(6) /* compare mode enable */ -#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ -#define TCLR_TCM BIT(8) /* edge detection of input pin*/ -#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ -#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ -#define TCLR_CAPTMODE BIT(13) /* capture mode */ -#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ - -#define TCFG_RESET BIT(0) /* software reset */ -#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ -#define TCFG_IDLEMOD_SHIFT (2) /* power management */ - -/* cpu-id for AM43XX AM33XX and TI81XX family */ -#define AM437X 0xB98C -#define AM335X 0xB944 -#define TI81XX 0xB81E -#define DEVICE_ID (CTRL_BASE + 0x0600) -#define DEVICE_ID_MASK 0x1FFF -#define PACKAGE_TYPE_SHIFT 16 -#define PACKAGE_TYPE_MASK (3 << 16) - -/* Package Type */ -#define PACKAGE_TYPE_UNDEFINED 0x0 -#define PACKAGE_TYPE_ZCZ 0x1 -#define PACKAGE_TYPE_ZCE 0x2 -#define PACKAGE_TYPE_RESERVED 0x3 - -/* MPU max frequencies */ -#define AM335X_ZCZ_300 0x1FEF -#define AM335X_ZCZ_600 0x1FAF -#define AM335X_ZCZ_720 0x1F2F -#define AM335X_ZCZ_800 0x1E2F -#define AM335X_ZCZ_1000 0x1C2F -#define AM335X_ZCE_300 0x1FDF -#define AM335X_ZCE_600 0x1F9F - -/* This gives the status of the boot mode pins on the evm */ -#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ - | BIT(3) | BIT(4)) - -#define PRM_RSTCTRL_RESET 0x01 -#define PRM_RSTST_WARM_RESET_MASK 0x232 - -/* EMIF Control register bits */ -#define EMIF_CTRL_DEVOFF BIT(0) - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -#include <asm/ti-common/omap_wdt.h> - -#ifndef CONFIG_AM43XX -/* Encapsulating core pll registers */ -struct cm_wkuppll { - unsigned int wkclkstctrl; /* offset 0x00 */ - unsigned int wkctrlclkctrl; /* offset 0x04 */ - unsigned int wkgpio0clkctrl; /* offset 0x08 */ - unsigned int wkl4wkclkctrl; /* offset 0x0c */ - unsigned int timer0clkctrl; /* offset 0x10 */ - unsigned int resv2[3]; - unsigned int idlestdpllmpu; /* offset 0x20 */ - unsigned int sscdeltamstepdllmpu; /* off 0x24 */ - unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */ - unsigned int clkseldpllmpu; /* offset 0x2c */ - unsigned int resv4[1]; - unsigned int idlestdpllddr; /* offset 0x34 */ - unsigned int resv5[2]; - unsigned int clkseldpllddr; /* offset 0x40 */ - unsigned int resv6[4]; - unsigned int clkseldplldisp; /* offset 0x54 */ - unsigned int resv7[1]; - unsigned int idlestdpllcore; /* offset 0x5c */ - unsigned int resv8[2]; - unsigned int clkseldpllcore; /* offset 0x68 */ - unsigned int resv9[1]; - unsigned int idlestdpllper; /* offset 0x70 */ - unsigned int resv10[2]; - unsigned int clkdcoldodpllper; /* offset 0x7c */ - unsigned int divm4dpllcore; /* offset 0x80 */ - unsigned int divm5dpllcore; /* offset 0x84 */ - unsigned int clkmoddpllmpu; /* offset 0x88 */ - unsigned int clkmoddpllper; /* offset 0x8c */ - unsigned int clkmoddpllcore; /* offset 0x90 */ - unsigned int clkmoddpllddr; /* offset 0x94 */ - unsigned int clkmoddplldisp; /* offset 0x98 */ - unsigned int clkseldpllper; /* offset 0x9c */ - unsigned int divm2dpllddr; /* offset 0xA0 */ - unsigned int divm2dplldisp; /* offset 0xA4 */ - unsigned int divm2dpllmpu; /* offset 0xA8 */ - unsigned int divm2dpllper; /* offset 0xAC */ - unsigned int resv11[1]; - unsigned int wkup_uart0ctrl; /* offset 0xB4 */ - unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ - unsigned int wkup_adctscctrl; /* offset 0xBC */ - unsigned int resv12; - unsigned int timer1clkctrl; /* offset 0xC4 */ - unsigned int resv13[4]; - unsigned int divm6dpllcore; /* offset 0xD8 */ -}; - -/** - * Encapsulating peripheral functional clocks - * pll registers - */ -struct cm_perpll { - unsigned int l4lsclkstctrl; /* offset 0x00 */ - unsigned int l3sclkstctrl; /* offset 0x04 */ - unsigned int l4fwclkstctrl; /* offset 0x08 */ - unsigned int l3clkstctrl; /* offset 0x0c */ - unsigned int resv1; - unsigned int cpgmac0clkctrl; /* offset 0x14 */ - unsigned int lcdclkctrl; /* offset 0x18 */ - unsigned int usb0clkctrl; /* offset 0x1C */ - unsigned int resv2; - unsigned int tptc0clkctrl; /* offset 0x24 */ - unsigned int emifclkctrl; /* offset 0x28 */ - unsigned int ocmcramclkctrl; /* offset 0x2c */ - unsigned int gpmcclkctrl; /* offset 0x30 */ - unsigned int mcasp0clkctrl; /* offset 0x34 */ - unsigned int uart5clkctrl; /* offset 0x38 */ - unsigned int mmc0clkctrl; /* offset 0x3C */ - unsigned int elmclkctrl; /* offset 0x40 */ - unsigned int i2c2clkctrl; /* offset 0x44 */ - unsigned int i2c1clkctrl; /* offset 0x48 */ - unsigned int spi0clkctrl; /* offset 0x4C */ - unsigned int spi1clkctrl; /* offset 0x50 */ - unsigned int resv3[3]; - unsigned int l4lsclkctrl; /* offset 0x60 */ - unsigned int l4fwclkctrl; /* offset 0x64 */ - unsigned int mcasp1clkctrl; /* offset 0x68 */ - unsigned int uart1clkctrl; /* offset 0x6C */ - unsigned int uart2clkctrl; /* offset 0x70 */ - unsigned int uart3clkctrl; /* offset 0x74 */ - unsigned int uart4clkctrl; /* offset 0x78 */ - unsigned int timer7clkctrl; /* offset 0x7C */ - unsigned int timer2clkctrl; /* offset 0x80 */ - unsigned int timer3clkctrl; /* offset 0x84 */ - unsigned int timer4clkctrl; /* offset 0x88 */ - unsigned int resv4[8]; - unsigned int gpio1clkctrl; /* offset 0xAC */ - unsigned int gpio2clkctrl; /* offset 0xB0 */ - unsigned int gpio3clkctrl; /* offset 0xB4 */ - unsigned int resv5; - unsigned int tpccclkctrl; /* offset 0xBC */ - unsigned int dcan0clkctrl; /* offset 0xC0 */ - unsigned int dcan1clkctrl; /* offset 0xC4 */ - unsigned int resv6; - unsigned int epwmss1clkctrl; /* offset 0xCC */ - unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int epwmss0clkctrl; /* offset 0xD4 */ - unsigned int epwmss2clkctrl; /* offset 0xD8 */ - unsigned int l3instrclkctrl; /* offset 0xDC */ - unsigned int l3clkctrl; /* Offset 0xE0 */ - unsigned int resv8[2]; - unsigned int timer5clkctrl; /* offset 0xEC */ - unsigned int timer6clkctrl; /* offset 0xF0 */ - unsigned int mmc1clkctrl; /* offset 0xF4 */ - unsigned int mmc2clkctrl; /* offset 0xF8 */ - unsigned int resv9[8]; - unsigned int l4hsclkstctrl; /* offset 0x11C */ - unsigned int l4hsclkctrl; /* offset 0x120 */ - unsigned int resv10[8]; - unsigned int cpswclkstctrl; /* offset 0x144 */ - unsigned int lcdcclkstctrl; /* offset 0x148 */ -}; - -/* Encapsulating Display pll registers */ -struct cm_dpll { - unsigned int resv1; - unsigned int clktimer7clk; /* offset 0x04 */ - unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int clktimer3clk; /* offset 0x0C */ - unsigned int clktimer4clk; /* offset 0x10 */ - unsigned int resv2; - unsigned int clktimer5clk; /* offset 0x18 */ - unsigned int clktimer6clk; /* offset 0x1C */ - unsigned int resv3[2]; - unsigned int clktimer1clk; /* offset 0x28 */ - unsigned int resv4[2]; - unsigned int clklcdcpixelclk; /* offset 0x34 */ -}; - -struct prm_device_inst { - unsigned int prm_rstctrl; - unsigned int prm_rsttime; - unsigned int prm_rstst; -}; -#else -/* Encapsulating core pll registers */ -struct cm_wkuppll { - unsigned int resv0[136]; - unsigned int wkl4wkclkctrl; /* offset 0x220 */ - unsigned int resv1[7]; - unsigned int usbphy0clkctrl; /* offset 0x240 */ - unsigned int resv112; - unsigned int usbphy1clkctrl; /* offset 0x248 */ - unsigned int resv113[45]; - unsigned int wkclkstctrl; /* offset 0x300 */ - unsigned int resv2[15]; - unsigned int wkup_i2c0ctrl; /* offset 0x340 */ - unsigned int resv3; - unsigned int wkup_uart0ctrl; /* offset 0x348 */ - unsigned int resv4[5]; - unsigned int wkctrlclkctrl; /* offset 0x360 */ - unsigned int resv5; - unsigned int wkgpio0clkctrl; /* offset 0x368 */ - - unsigned int resv6[109]; - unsigned int clkmoddpllcore; /* offset 0x520 */ - unsigned int idlestdpllcore; /* offset 0x524 */ - unsigned int resv61; - unsigned int clkseldpllcore; /* offset 0x52C */ - unsigned int resv7[2]; - unsigned int divm4dpllcore; /* offset 0x538 */ - unsigned int divm5dpllcore; /* offset 0x53C */ - unsigned int divm6dpllcore; /* offset 0x540 */ - - unsigned int resv8[7]; - unsigned int clkmoddpllmpu; /* offset 0x560 */ - unsigned int idlestdpllmpu; /* offset 0x564 */ - unsigned int resv9; - unsigned int clkseldpllmpu; /* offset 0x56c */ - unsigned int divm2dpllmpu; /* offset 0x570 */ - - unsigned int resv10[11]; - unsigned int clkmoddpllddr; /* offset 0x5A0 */ - unsigned int idlestdpllddr; /* offset 0x5A4 */ - unsigned int resv11; - unsigned int clkseldpllddr; /* offset 0x5AC */ - unsigned int divm2dpllddr; /* offset 0x5B0 */ - - unsigned int resv12[11]; - unsigned int clkmoddpllper; /* offset 0x5E0 */ - unsigned int idlestdpllper; /* offset 0x5E4 */ - unsigned int resv13; - unsigned int clkseldpllper; /* offset 0x5EC */ - unsigned int divm2dpllper; /* offset 0x5F0 */ - unsigned int resv14[8]; - unsigned int clkdcoldodpllper; /* offset 0x614 */ - - unsigned int resv15[2]; - unsigned int clkmoddplldisp; /* offset 0x620 */ - unsigned int resv16[2]; - unsigned int clkseldplldisp; /* offset 0x62C */ - unsigned int divm2dplldisp; /* offset 0x630 */ -}; - -/* - * Encapsulating peripheral functional clocks - * pll registers - */ -struct cm_perpll { - unsigned int l3clkstctrl; /* offset 0x00 */ - unsigned int resv0[7]; - unsigned int l3clkctrl; /* Offset 0x20 */ - unsigned int resv112[7]; - unsigned int l3instrclkctrl; /* offset 0x40 */ - unsigned int resv2[3]; - unsigned int ocmcramclkctrl; /* offset 0x50 */ - unsigned int resv3[9]; - unsigned int tpccclkctrl; /* offset 0x78 */ - unsigned int resv4; - unsigned int tptc0clkctrl; /* offset 0x80 */ - - unsigned int resv5[7]; - unsigned int l4hsclkctrl; /* offset 0x0A0 */ - unsigned int resv6; - unsigned int l4fwclkctrl; /* offset 0x0A8 */ - unsigned int resv7[85]; - unsigned int l3sclkstctrl; /* offset 0x200 */ - unsigned int resv8[7]; - unsigned int gpmcclkctrl; /* offset 0x220 */ - unsigned int resv9[5]; - unsigned int mcasp0clkctrl; /* offset 0x238 */ - unsigned int resv10; - unsigned int mcasp1clkctrl; /* offset 0x240 */ - unsigned int resv11; - unsigned int mmc2clkctrl; /* offset 0x248 */ - unsigned int resv12[3]; - unsigned int qspiclkctrl; /* offset 0x258 */ - unsigned int resv121; - unsigned int usb0clkctrl; /* offset 0x260 */ - unsigned int resv122; - unsigned int usb1clkctrl; /* offset 0x268 */ - unsigned int resv13[101]; - unsigned int l4lsclkstctrl; /* offset 0x400 */ - unsigned int resv14[7]; - unsigned int l4lsclkctrl; /* offset 0x420 */ - unsigned int resv15; - unsigned int dcan0clkctrl; /* offset 0x428 */ - unsigned int resv16; - unsigned int dcan1clkctrl; /* offset 0x430 */ - unsigned int resv17[13]; - unsigned int elmclkctrl; /* offset 0x468 */ - - unsigned int resv18[3]; - unsigned int gpio1clkctrl; /* offset 0x478 */ - unsigned int resv19; - unsigned int gpio2clkctrl; /* offset 0x480 */ - unsigned int resv20; - unsigned int gpio3clkctrl; /* offset 0x488 */ - unsigned int resv41; - unsigned int gpio4clkctrl; /* offset 0x490 */ - unsigned int resv42; - unsigned int gpio5clkctrl; /* offset 0x498 */ - unsigned int resv21[3]; - - unsigned int i2c1clkctrl; /* offset 0x4A8 */ - unsigned int resv22; - unsigned int i2c2clkctrl; /* offset 0x4B0 */ - unsigned int resv23[3]; - unsigned int mmc0clkctrl; /* offset 0x4C0 */ - unsigned int resv24; - unsigned int mmc1clkctrl; /* offset 0x4C8 */ - - unsigned int resv25[13]; - unsigned int spi0clkctrl; /* offset 0x500 */ - unsigned int resv26; - unsigned int spi1clkctrl; /* offset 0x508 */ - unsigned int resv27[9]; - unsigned int timer2clkctrl; /* offset 0x530 */ - unsigned int resv28; - unsigned int timer3clkctrl; /* offset 0x538 */ - unsigned int resv29; - unsigned int timer4clkctrl; /* offset 0x540 */ - unsigned int resv30[5]; - unsigned int timer7clkctrl; /* offset 0x558 */ - - unsigned int resv31[9]; - unsigned int uart1clkctrl; /* offset 0x580 */ - unsigned int resv32; - unsigned int uart2clkctrl; /* offset 0x588 */ - unsigned int resv33; - unsigned int uart3clkctrl; /* offset 0x590 */ - unsigned int resv34; - unsigned int uart4clkctrl; /* offset 0x598 */ - unsigned int resv35; - unsigned int uart5clkctrl; /* offset 0x5A0 */ - unsigned int resv36[5]; - unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */ - unsigned int resv361; - unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */ - unsigned int resv3611[79]; - - unsigned int emifclkstctrl; /* offset 0x700 */ - unsigned int resv362[7]; - unsigned int emifclkctrl; /* offset 0x720 */ - unsigned int resv37[3]; - unsigned int emiffwclkctrl; /* offset 0x730 */ - unsigned int resv371; - unsigned int otfaemifclkctrl; /* offset 0x738 */ - unsigned int resv38[57]; - unsigned int lcdclkctrl; /* offset 0x820 */ - unsigned int resv39[183]; - unsigned int cpswclkstctrl; /* offset 0xB00 */ - unsigned int resv40[7]; - unsigned int cpgmac0clkctrl; /* offset 0xB20 */ -}; - -struct cm_device_inst { - unsigned int cm_clkout1_ctrl; - unsigned int cm_dll_ctrl; -}; - -struct prm_device_inst { - unsigned int rstctrl; - unsigned int rstst; - unsigned int rsttime; - unsigned int sram_count; - unsigned int ldo_sram_core_set; /* offset 0x10 */ - unsigned int ldo_sram_core_ctr; - unsigned int ldo_sram_mpu_setu; - unsigned int ldo_sram_mpu_ctrl; - unsigned int io_count; /* offset 0x20 */ - unsigned int io_pmctrl; - unsigned int vc_val_bypass; - unsigned int resv1; - unsigned int emif_ctrl; /* offset 0x30 */ -}; - -struct cm_dpll { - unsigned int resv1; - unsigned int clktimer2clk; /* offset 0x04 */ - unsigned int resv2[11]; - unsigned int clkselmacclk; /* offset 0x34 */ -}; -#endif /* CONFIG_AM43XX */ - -/* Control Module RTC registers */ -struct cm_rtc { - unsigned int rtcclkctrl; /* offset 0x0 */ - unsigned int clkstctrl; /* offset 0x4 */ -}; - -/* Timer 32 bit registers */ -struct gptimer { - unsigned int tidr; /* offset 0x00 */ - unsigned char res1[12]; - unsigned int tiocp_cfg; /* offset 0x10 */ - unsigned char res2[12]; - unsigned int tier; /* offset 0x20 */ - unsigned int tistatr; /* offset 0x24 */ - unsigned int tistat; /* offset 0x28 */ - unsigned int tisr; /* offset 0x2c */ - unsigned int tcicr; /* offset 0x30 */ - unsigned int twer; /* offset 0x34 */ - unsigned int tclr; /* offset 0x38 */ - unsigned int tcrr; /* offset 0x3c */ - unsigned int tldr; /* offset 0x40 */ - unsigned int ttgr; /* offset 0x44 */ - unsigned int twpc; /* offset 0x48 */ - unsigned int tmar; /* offset 0x4c */ - unsigned int tcar1; /* offset 0x50 */ - unsigned int tscir; /* offset 0x54 */ - unsigned int tcar2; /* offset 0x58 */ -}; - -/* UART Registers */ -struct uart_sys { - unsigned int resv1[21]; - unsigned int uartsyscfg; /* offset 0x54 */ - unsigned int uartsyssts; /* offset 0x58 */ -}; - -/* VTP Registers */ -struct vtp_reg { - unsigned int vtp0ctrlreg; -}; - -/* Control Status Register */ -struct ctrl_stat { - unsigned int resv1[16]; - unsigned int statusreg; /* ofset 0x40 */ - unsigned int resv2[51]; - unsigned int secure_emif_sdram_config; /* offset 0x0110 */ - unsigned int resv3[319]; - unsigned int dev_attr; -}; - -/* AM33XX GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0114 -#define OMAP_GPIO_IRQSTATUS1 0x002c -#define OMAP_GPIO_IRQSTATUS2 0x0030 -#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034 -#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038 -#define OMAP_GPIO_CTRL 0x0130 -#define OMAP_GPIO_OE 0x0134 -#define OMAP_GPIO_DATAIN 0x0138 -#define OMAP_GPIO_DATAOUT 0x013c -#define OMAP_GPIO_LEVELDETECT0 0x0140 -#define OMAP_GPIO_LEVELDETECT1 0x0144 -#define OMAP_GPIO_RISINGDETECT 0x0148 -#define OMAP_GPIO_FALLINGDETECT 0x014c -#define OMAP_GPIO_DEBOUNCE_EN 0x0150 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 -#define OMAP_GPIO_CLEARDATAOUT 0x0190 -#define OMAP_GPIO_SETDATAOUT 0x0194 - -/* Control Device Register */ - - /* Control Device Register */ -#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F -#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8 -#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F - -struct ctrl_dev { - unsigned int deviceid; /* offset 0x00 */ - unsigned int resv1[7]; - unsigned int usb_ctrl0; /* offset 0x20 */ - unsigned int resv2; - unsigned int usb_ctrl1; /* offset 0x28 */ - unsigned int resv3; - unsigned int macid0l; /* offset 0x30 */ - unsigned int macid0h; /* offset 0x34 */ - unsigned int macid1l; /* offset 0x38 */ - unsigned int macid1h; /* offset 0x3c */ - unsigned int resv4[4]; - unsigned int miisel; /* offset 0x50 */ - unsigned int resv5[7]; - unsigned int mreqprio_0; /* offset 0x70 */ - unsigned int mreqprio_1; /* offset 0x74 */ - unsigned int resv6[97]; - unsigned int efuse_sma; /* offset 0x1FC */ -}; - -/* Bandwidth Limiter Portion of the L3Fast Configuration Register */ -#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0 -#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0 -#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800 - -struct l3f_cfg_bwlimiter { - u32 padding0[2]; - u32 modena_init0_bw_fractional; - u32 modena_init0_bw_integer; - u32 modena_init0_watermark_0; -}; - -/* gmii_sel register defines */ -#define GMII1_SEL_MII 0x0 -#define GMII1_SEL_RMII 0x1 -#define GMII1_SEL_RGMII 0x2 -#define GMII2_SEL_MII 0x0 -#define GMII2_SEL_RMII 0x4 -#define GMII2_SEL_RGMII 0x8 -#define RGMII1_IDMODE BIT(4) -#define RGMII2_IDMODE BIT(5) -#define RMII1_IO_CLK_EN BIT(6) -#define RMII2_IO_CLK_EN BIT(7) - -#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) -#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) -#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) -#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) -#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) - -/* PWMSS */ -struct pwmss_regs { - unsigned int idver; - unsigned int sysconfig; - unsigned int clkconfig; - unsigned int clkstatus; -}; -#define ECAP_CLK_EN BIT(0) -#define ECAP_CLK_STOP_REQ BIT(1) -#define EPWM_CLK_EN BIT(8) -#define EPWM_CLK_STOP_REQ BIT(9) - -struct pwmss_ecap_regs { - unsigned int tsctr; - unsigned int ctrphs; - unsigned int cap1; - unsigned int cap2; - unsigned int cap3; - unsigned int cap4; - unsigned int resv1[4]; - unsigned short ecctl1; - unsigned short ecctl2; -}; - -struct pwmss_epwm_regs { - unsigned short tbctl; - unsigned short tbsts; - unsigned short tbphshr; - unsigned short tbphs; - unsigned short tbcnt; - unsigned short tbprd; - unsigned short res1; - unsigned short cmpctl; - unsigned short cmpahr; - unsigned short cmpa; - unsigned short cmpb; - unsigned short aqctla; - unsigned short aqctlb; - unsigned short aqsfrc; - unsigned short aqcsfrc; - unsigned short dbctl; - unsigned short dbred; - unsigned short dbfed; - unsigned short tzsel; - unsigned short tzctl; - unsigned short tzflg; - unsigned short tzclr; - unsigned short tzfrc; - unsigned short etsel; - unsigned short etps; - unsigned short etflg; - unsigned short etclr; - unsigned short etfrc; - unsigned short pcctl; - unsigned int res2[66]; - unsigned short hrcnfg; -}; - -/* Capture Control register 2 */ -#define ECTRL2_SYNCOSEL_MASK (0x03 << 6) -#define ECTRL2_MDSL_ECAP BIT(9) -#define ECTRL2_CTRSTP_FREERUN BIT(4) -#define ECTRL2_PLSL_LOW BIT(10) -#define ECTRL2_SYNC_EN BIT(5) - -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#endif /* _AM33XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h deleted file mode 100644 index 15a5b64..0000000 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ /dev/null @@ -1,383 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ddr_defs.h - * - * ddr specific header - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef _DDR_DEFS_H -#define _DDR_DEFS_H - -#include <asm/arch/hardware.h> -#include <asm/emif.h> - -/* AM335X EMIF Register values */ -#define VTP_CTRL_READY (0x1 << 5) -#define VTP_CTRL_ENABLE (0x1 << 6) -#define VTP_CTRL_START_EN (0x1) -#ifdef CONFIG_AM43XX -#define DDR_CKE_CTRL_NORMAL 0x3 -#else -#define DDR_CKE_CTRL_NORMAL 0x1 -#endif -#define PHY_EN_DYN_PWRDN (0x1 << 20) - -/* Micron MT47H128M16RT-25E */ -#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 -#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 -#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA -#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F -#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 -#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a -#define MT47H128M16RT25E_RATIO 0x80 -#define MT47H128M16RT25E_RD_DQS 0x12 -#define MT47H128M16RT25E_PHY_WR_DATA 0x40 -#define MT47H128M16RT25E_PHY_FIFO_WE 0x80 -#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B - -/* Micron MT41J128M16JT-125 */ -#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 -#define MT41J128MJT125_EMIF_TIM1 0x0888A39B -#define MT41J128MJT125_EMIF_TIM2 0x26337FDA -#define MT41J128MJT125_EMIF_TIM3 0x501F830F -#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 -#define MT41J128MJT125_EMIF_SDREF 0x0000093B -#define MT41J128MJT125_ZQ_CFG 0x50074BE4 -#define MT41J128MJT125_RATIO 0x40 -#define MT41J128MJT125_INVERT_CLKOUT 0x1 -#define MT41J128MJT125_RD_DQS 0x3B -#define MT41J128MJT125_WR_DQS 0x85 -#define MT41J128MJT125_PHY_WR_DATA 0xC1 -#define MT41J128MJT125_PHY_FIFO_WE 0x100 -#define MT41J128MJT125_IOCTRL_VALUE 0x18B - -/* Micron MT41J128M16JT-125 at 400MHz*/ -#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007 -#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB -#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA -#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF -#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2 -#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30 -#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4 -#define MT41J128MJT125_RATIO_400MHz 0x80 -#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0 -#define MT41J128MJT125_RD_DQS_400MHz 0x3A -#define MT41J128MJT125_WR_DQS_400MHz 0x3B -#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76 -#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96 - -/* Micron MT41K128M16JT-187E */ -#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 -#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB -#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA -#define MT41K128MJT187E_EMIF_TIM3 0x501F830F -#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 -#define MT41K128MJT187E_EMIF_SDREF 0x0000093B -#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 -#define MT41K128MJT187E_RATIO 0x40 -#define MT41K128MJT187E_INVERT_CLKOUT 0x1 -#define MT41K128MJT187E_RD_DQS 0x3B -#define MT41K128MJT187E_WR_DQS 0x85 -#define MT41K128MJT187E_PHY_WR_DATA 0xC1 -#define MT41K128MJT187E_PHY_FIFO_WE 0x100 -#define MT41K128MJT187E_IOCTRL_VALUE 0x18B - -/* Micron MT41K128M16JT-125 IT:K (256 MB) at 400MHz */ -#define MT41K128M16JT125K_EMIF_READ_LATENCY 0x07 -#define MT41K128M16JT125K_EMIF_TIM1 0x0AAAD4DB -#define MT41K128M16JT125K_EMIF_TIM2 0x2A437FDA -#define MT41K128M16JT125K_EMIF_TIM3 0x501F83FF -#define MT41K128M16JT125K_EMIF_SDCFG 0x61A052B2 -#define MT41K128M16JT125K_EMIF_SDREF 0x00000C30 -#define MT41K128M16JT125K_ZQ_CFG 0x50074BE4 -#define MT41K128M16JT125K_RATIO 0x80 -#define MT41K128M16JT125K_INVERT_CLKOUT 0x0 -#define MT41K128M16JT125K_RD_DQS 0x38 -#define MT41K128M16JT125K_WR_DQS 0x46 -#define MT41K128M16JT125K_PHY_WR_DATA 0x7D -#define MT41K128M16JT125K_PHY_FIFO_WE 0x9B -#define MT41K128M16JT125K_IOCTRL_VALUE 0x18B - -/* Micron MT41J64M16JT-125 */ -#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 - -/* Micron MT41J256M16JT-125 */ -#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 - -/* Micron MT41J256M8HX-15E */ -#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 -#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B -#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA -#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F -#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 -#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B -#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 -#define MT41J256M8HX15E_RATIO 0x40 -#define MT41J256M8HX15E_INVERT_CLKOUT 0x1 -#define MT41J256M8HX15E_RD_DQS 0x3B -#define MT41J256M8HX15E_WR_DQS 0x85 -#define MT41J256M8HX15E_PHY_WR_DATA 0xC1 -#define MT41J256M8HX15E_PHY_FIFO_WE 0x100 -#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B - -/* Micron MT41K256M16HA-125E */ -#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 -#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB -#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA -#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F -#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 -#define MT41K256M16HA125E_EMIF_SDREF 0xC30 -#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 -#define MT41K256M16HA125E_RATIO 0x80 -#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 -#define MT41K256M16HA125E_RD_DQS 0x38 -#define MT41K256M16HA125E_WR_DQS 0x44 -#define MT41K256M16HA125E_PHY_WR_DATA 0x7D -#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 -#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B - -/* Micron MT41J512M8RH-125 on EVM v1.5 */ -#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 -#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B -#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA -#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF -#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 -#define MT41J512M8RH125_EMIF_SDREF 0x0000093B -#define MT41J512M8RH125_ZQ_CFG 0x50074BE4 -#define MT41J512M8RH125_RATIO 0x80 -#define MT41J512M8RH125_INVERT_CLKOUT 0x0 -#define MT41J512M8RH125_RD_DQS 0x3B -#define MT41J512M8RH125_WR_DQS 0x3C -#define MT41J512M8RH125_PHY_FIFO_WE 0xA5 -#define MT41J512M8RH125_PHY_WR_DATA 0x74 -#define MT41J512M8RH125_IOCTRL_VALUE 0x18B - -/* Samsung K4B2G1646E-BIH9 */ -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 -#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B -#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA -#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF -#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 -#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 -#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 -#define K4B2G1646EBIH9_RATIO 0x80 -#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 -#define K4B2G1646EBIH9_RD_DQS 0x35 -#define K4B2G1646EBIH9_WR_DQS 0x3A -#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 -#define K4B2G1646EBIH9_PHY_WR_DATA 0x76 -#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B - -#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 -#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 -#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 -#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 -#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 -#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 -#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 - -#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 -#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 -#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 -#define DDR3_DATA0_IOCTRL_VALUE 0x84 -#define DDR3_DATA1_IOCTRL_VALUE 0x84 -#define DDR3_DATA2_IOCTRL_VALUE 0x84 -#define DDR3_DATA3_IOCTRL_VALUE 0x84 - -/** - * Configure DMM - */ -void config_dmm(const struct dmm_lisa_map_regs *regs); - -/** - * Configure SDRAM - */ -void config_sdram(const struct emif_regs *regs, int nr); -void config_sdram_emif4d5(const struct emif_regs *regs, int nr); - -/** - * Set SDRAM timings - */ -void set_sdram_timings(const struct emif_regs *regs, int nr); - -/** - * Configure DDR PHY - */ -void config_ddr_phy(const struct emif_regs *regs, int nr); - -struct ddr_cmd_regs { - unsigned int resv0[7]; - unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv1[3]; - unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv2[8]; - unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[3]; - unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv4[8]; - unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[3]; - unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv6[3]; -}; - -struct ddr_data_regs { - unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv1[4]; - unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv2[4]; - unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv3; - unsigned int dt0wimode0; /* offset 0x0F8 */ - unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv4; - unsigned int dt0gimode0; /* offset 0x104 */ - unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv5[4]; - unsigned int dt0dqoffset; /* offset 0x11C */ - unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv6[4]; - unsigned int dt0rdelays0; /* offset 0x134 */ - unsigned int dt0dldiff0; /* offset 0x138 */ - unsigned int resv7[12]; -}; - -/** - * This structure represents the DDR registers on AM33XX devices. - * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that - * correspond to DATA1 registers defined here. - */ -struct ddr_regs { - unsigned int resv0[3]; - unsigned int cm0config; /* offset 0x00C */ - unsigned int cm0configclk; /* offset 0x010 */ - unsigned int resv1[2]; - unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv2[3]; - unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv3[4]; - unsigned int cm1config; /* offset 0x040 */ - unsigned int cm1configclk; /* offset 0x044 */ - unsigned int resv4[2]; - unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv5[3]; - unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv6[4]; - unsigned int cm2config; /* offset 0x074 */ - unsigned int cm2configclk; /* offset 0x078 */ - unsigned int resv7[2]; - unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv8[3]; - unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv9[12]; - unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv10[4]; - unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv11[4]; - unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv12; - unsigned int dt0wimode0; /* offset 0x0F8 */ - unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv13; - unsigned int dt0gimode0; /* offset 0x104 */ - unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv14[4]; - unsigned int dt0dqoffset; /* offset 0x11C */ - unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv15[4]; - unsigned int dt0rdelays0; /* offset 0x134 */ - unsigned int dt0dldiff0; /* offset 0x138 */ -}; - -/** - * Encapsulates DDR CMD control registers. - */ -struct cmd_control { - unsigned long cmd0csratio; - unsigned long cmd0csforce; - unsigned long cmd0csdelay; - unsigned long cmd0iclkout; - unsigned long cmd1csratio; - unsigned long cmd1csforce; - unsigned long cmd1csdelay; - unsigned long cmd1iclkout; - unsigned long cmd2csratio; - unsigned long cmd2csforce; - unsigned long cmd2csdelay; - unsigned long cmd2iclkout; -}; - -/** - * Encapsulates DDR DATA registers. - */ -struct ddr_data { - unsigned long datardsratio0; - unsigned long datawdsratio0; - unsigned long datawiratio0; - unsigned long datagiratio0; - unsigned long datafwsratio0; - unsigned long datawrsratio0; -}; - -/** - * Configure DDR CMD control registers - */ -void config_cmd_ctrl(const struct cmd_control *cmd, int nr); - -/** - * Configure DDR DATA registers - */ -void config_ddr_data(const struct ddr_data *data, int nr); - -/** - * This structure represents the DDR io control on AM33XX devices. - */ -struct ddr_cmdtctrl { - unsigned int cm0ioctl; - unsigned int cm1ioctl; - unsigned int cm2ioctl; - unsigned int resv2[12]; - unsigned int dt0ioctl; - unsigned int dt1ioctl; - unsigned int dt2ioctrl; - unsigned int dt3ioctrl; - unsigned int resv3[4]; - unsigned int emif_sdram_config_ext; -}; - -struct ctrl_ioregs { - unsigned int cm0ioctl; - unsigned int cm1ioctl; - unsigned int cm2ioctl; - unsigned int dt0ioctl; - unsigned int dt1ioctl; - unsigned int dt2ioctrl; - unsigned int dt3ioctrl; - unsigned int emif_sdram_config_ext; -}; - -/** - * Configure DDR io control registers - */ -void config_io_ctrl(const struct ctrl_ioregs *ioregs); - -struct ddr_ctrl { - unsigned int ddrioctrl; - unsigned int resv1[325]; - unsigned int ddrckectrl; -}; - -#ifdef CONFIG_TI816X -void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, - const struct dmm_lisa_map_regs *lisa_regs, int nrs); -#else -void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, - const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, int nr); -#endif -void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); - -#endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h deleted file mode 100644 index eb6516d..0000000 --- a/arch/arm/include/asm/arch-am33xx/emac_defs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Texas Instruments - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - */ - -#ifndef _EMAC_DEFS_H_ -#define _EMAC_DEFS_H_ - -#ifdef CONFIG_TI816X -#define EMAC_BASE_ADDR (0x4A100000) -#define EMAC_WRAPPER_BASE_ADDR (0x4A100900) -#define EMAC_WRAPPER_RAM_ADDR (0x4A102000) -#define EMAC_MDIO_BASE_ADDR (0x4A100800) -#define EMAC_MDIO_BUS_FREQ (250000000UL) -#define EMAC_MDIO_CLOCK_FREQ (2000000UL) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int *dv_reg_p; - -#define DAVINCI_EMAC_VERSION2 -#define DAVINCI_EMAC_GIG_ENABLE -#endif - -#endif /* _EMAC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h deleted file mode 100644 index 24dc4bb..0000000 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _GPIO_AM33xx_H -#define _GPIO_AM33xx_H - -#include <asm/omap_gpio.h> - -#ifdef CONFIG_AM43XX -#define OMAP_MAX_GPIO 192 -#else -#define OMAP_MAX_GPIO 128 -#endif - -#define AM33XX_GPIO0_BASE 0x44E07000 -#define AM33XX_GPIO1_BASE 0x4804C000 -#define AM33XX_GPIO2_BASE 0x481AC000 -#define AM33XX_GPIO3_BASE 0x481AE000 -#define AM33XX_GPIO4_BASE 0x48320000 -#define AM33XX_GPIO5_BASE 0x48322000 - -/* GPIO CTRL register */ -#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 -#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) -#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK - -/* GPIO OUTPUT ENABLE register */ -#define GPIO_OE_ENABLE(x) (1 << x) - -/* GPIO SETDATAOUT register */ -#define GPIO_SETDATAOUT(x) (1 << x) -#endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h deleted file mode 100644 index 0508b8c..0000000 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware.h - * - * hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __AM33XX_HARDWARE_H -#define __AM33XX_HARDWARE_H - -#include <config.h> -#include <asm/arch/omap.h> -#ifdef CONFIG_AM33XX -#include <asm/arch/hardware_am33xx.h> -#elif defined(CONFIG_TI816X) -#include <asm/arch/hardware_ti816x.h> -#elif defined(CONFIG_TI814X) -#include <asm/arch/hardware_ti814x.h> -#elif defined(CONFIG_AM43XX) -#include <asm/arch/hardware_am43xx.h> -#endif - -/* - * Common hardware definitions - */ - -/* DM Timer base addresses */ -#define DM_TIMER0_BASE 0x4802C000 -#define DM_TIMER1_BASE 0x4802E000 -#define DM_TIMER2_BASE 0x48040000 -#define DM_TIMER3_BASE 0x48042000 -#define DM_TIMER4_BASE 0x48044000 -#define DM_TIMER5_BASE 0x48046000 -#define DM_TIMER6_BASE 0x48048000 -#define DM_TIMER7_BASE 0x4804A000 - -/* GPIO Base address */ -#define GPIO0_BASE 0x48032000 -#define GPIO1_BASE 0x4804C000 - -/* BCH Error Location Module */ -#define ELM_BASE 0x48080000 - -/* EMIF Base address */ -#define EMIF4_0_CFG_BASE 0x4C000000 -#define EMIF4_1_CFG_BASE 0x4D000000 - -/* DDR Base address */ -#define DDR_CTRL_ADDR 0x44E10E04 -#define DDR_CONTROL_BASE_ADDR 0x44E11404 - -/* UART */ -#if CONFIG_CONS_INDEX == 1 -# define DEFAULT_UART_BASE UART0_BASE -#elif CONFIG_CONS_INDEX == 2 -# define DEFAULT_UART_BASE UART1_BASE -#elif CONFIG_CONS_INDEX == 3 -# define DEFAULT_UART_BASE UART2_BASE -#elif CONFIG_CONS_INDEX == 4 -# define DEFAULT_UART_BASE UART3_BASE -#elif CONFIG_CONS_INDEX == 5 -# define DEFAULT_UART_BASE UART4_BASE -#elif CONFIG_CONS_INDEX == 6 -# define DEFAULT_UART_BASE UART5_BASE -#endif - -/* GPMC Base address */ -#define GPMC_BASE 0x50000000 - -/* CPSW Config space */ -#define CPSW_BASE 0x4A100000 - -/* Control status register */ -#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) -#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 -#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) -#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 -#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) -#define CTRL_SYSBOOT_15_14_SHIFT 22 - -#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 -#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 - -#define NUM_CRYSTAL_FREQ 0x4 - -int clk_get(int clk); -#endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h deleted file mode 100644 index 878ef3e..0000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware_am33xx.h - * - * AM33xx hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __AM33XX_HARDWARE_AM33XX_H -#define __AM33XX_HARDWARE_AM33XX_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x44E09000 -#define UART1_BASE 0x48022000 -#define UART2_BASE 0x48024000 -#define UART3_BASE 0x481A6000 -#define UART4_BASE 0x481A8000 -#define UART5_BASE 0x481AA000 - -/* GPIO Base address */ -#define GPIO2_BASE 0x481AC000 - -/* Watchdog Timer */ -#define WDT_BASE 0x44E35000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x44E10000 -#define CTRL_DEVICE_BASE 0x44E10600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x44E00000 -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 -#define CM_DPLL 0x44E00500 -#define CM_RTC 0x44E00800 - -#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x44E10E0C -#define VTP1_CTRL_ADDR 0x48140E10 -#define PRM_DEVICE_INST 0x44E00F00 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x44E12000 -#define DDR_PHY_DATA_ADDR 0x44E120C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 2 - -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A101000 - -/* RTC base address */ -#define RTC_BASE 0x44E3E000 - -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - -/* LCD Controller */ -#define LCD_CNTL_BASE 0x4830E000 - -/* PWMSS */ -#define PWMSS0_BASE 0x48300000 -#define AM33XX_ECAP0_BASE 0x48300100 -#define AM33XX_EPWM_BASE 0x48300200 - -#endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h deleted file mode 100644 index 64809d5..0000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware_am43xx.h - * - * AM43xx hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __AM43XX_HARDWARE_AM43XX_H -#define __AM43XX_HARDWARE_AM43XX_H - -/* Module base addresses */ - -/* L3 Fast Configuration Bandwidth Limiter Base Address */ -#define L3F_CFG_BWLIMITER 0x44005200 - -/* UART Base Address */ -#define UART0_BASE 0x44E09000 - -/* GPIO Base address */ -#define GPIO2_BASE 0x481AC000 - -/* Watchdog Timer */ -#define WDT_BASE 0x44E35000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x44E10000 -#define CTRL_DEVICE_BASE 0x44E10600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x44DF0000 -#define CM_WKUP 0x44DF2800 -#define CM_PER 0x44DF8800 -#define CM_DPLL 0x44DF4200 -#define CM_RTC 0x44DF8500 - -#define PRM_RSTCTRL (PRCM_BASE + 0x4000) -#define PRM_RSTST (PRM_RSTCTRL + 4) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x44E10E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* USB CTRL Base Address */ -#define USB1_CTRL 0x44e10628 -#define USB1_CTRL_CM_PWRDN BIT(0) -#define USB1_CTRL_OTG_PWRDN BIT(1) - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x44E12000 -#define DDR_PHY_DATA_ADDR 0x44E120C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 2 - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A101000 - -/* RTC base address */ -#define RTC_BASE 0x44E3E000 - -/* USB OTG */ -#define USB_OTG_SS1_BASE 0x48390000 -#define USB_OTG_SS1_GLUE_BASE 0x48380000 -#define USB2_PHY1_POWER 0x44E10620 - -#define USB_OTG_SS2_BASE 0x483D0000 -#define USB_OTG_SS2_GLUE_BASE 0x483C0000 -#define USB2_PHY2_POWER 0x44E10628 - -/* USB Clock Control */ -#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) -#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) -#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) -#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) - -#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) -#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) -#define USBPHYOCPSCP_MODULE_EN (1 << 1) -#define CM_DEVICE_INST 0x44df4100 -#define PRM_DEVICE_INST 0x44df4000 - -#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) -#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) - -/* EDMA3 Base Address */ -#define EDMA3_BASE 0x49000000 - -#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h deleted file mode 100644 index b00d592..0000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware_ti814x.h - * - * TI814x hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __AM33XX_HARDWARE_TI814X_H -#define __AM33XX_HARDWARE_TI814X_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x48020000 - -/* Watchdog Timer */ -#define WDT_BASE 0x481C7000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* PLL Subsystem Base Address */ -#define PLL_SUBSYS_BASE 0x481C5000 - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48140E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x47C0C400 -#define DDR_PHY_DATA_ADDR 0x47C0C4C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 4 - -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A100800 - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - -#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h deleted file mode 100644 index 78b7948..0000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * hardware_ti816x.h - * - * TI816x hardware specific header - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * Based on TI-PSP-04.00.02.14 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AM33XX_HARDWARE_TI816X_H -#define __AM33XX_HARDWARE_TI816X_H - -/* UART */ -#define UART0_BASE 0x48020000 -#define UART1_BASE 0x48022000 -#define UART2_BASE 0x48024000 - -/* Watchdog Timer */ -#define WDT_BASE 0x480C2000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48198358 -#define VTP1_CTRL_ADDR 0x4819A358 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x48198000 -#define DDR_PHY_DATA_ADDR 0x481980C8 -#define DDR_PHY_CMD_ADDR2 0x4819A000 -#define DDR_PHY_DATA_ADDR2 0x4819A0C8 -#define DDR_DATA_REGS_NR 4 - - -#define DDRPHY_0_CONFIG_BASE 0x48198000 -#define DDRPHY_1_CONFIG_BASE 0x4819A000 -#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ - DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h deleted file mode 100644 index c2a9850..0000000 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - */ -#ifndef _I2C_AM33XX_H_ -#define _I2C_AM33XX_H_ - -#include <asm/omap_i2c.h> - -#define I2C_BASE1 0x44E0B000 -#define I2C_BASE2 0x4802A000 -#define I2C_BASE3 0x4819C000 - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#define I2C_IP_CLK 48000000 -#define I2C_INTERNAL_SAMPLING_CLK 12000000 - -#endif /* _I2C_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h deleted file mode 100644 index 0fd52f8..0000000 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * Author - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Richard Woodruff <r-woodruff2@ti.com> - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -/* - * GPMC settings - - * Definitions is as per the following format - * #define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL - */ -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define M_NAND_GPMC_CONFIG1 0x00000800 -#define M_NAND_GPMC_CONFIG2 0x001e1e00 -#define M_NAND_GPMC_CONFIG3 0x001e1e00 -#define M_NAND_GPMC_CONFIG4 0x16051807 -#define M_NAND_GPMC_CONFIG5 0x00151e1e -#define M_NAND_GPMC_CONFIG6 0x16000f80 -#define M_NAND_GPMC_CONFIG7 0x00000008 - -#define STNOR_GPMC_CONFIG1 0x00001200 -#define STNOR_GPMC_CONFIG2 0x00101000 -#define STNOR_GPMC_CONFIG3 0x00030301 -#define STNOR_GPMC_CONFIG4 0x10041004 -#define STNOR_GPMC_CONFIG5 0x000C1010 -#define STNOR_GPMC_CONFIG6 0x08070280 -#define STNOR_GPMC_CONFIG7 0x00000F48 - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define DBG_MPDB 6 - -#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h deleted file mode 100644 index 5a2ea8f..0000000 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * mmc_host_def.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* - * OMAP HSMMC register definitions - */ -#define OMAP_HSMMC1_BASE 0x48060000 -#define OMAP_HSMMC2_BASE 0x481D8000 - -#if defined(CONFIG_TI814X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 192 /* MHz */ -#elif defined(CONFIG_TI816X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 48 /* MHz */ -#endif - -#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h deleted file mode 100644 index d8bf872..0000000 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * mux.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_H_ -#define _MUX_H_ - -#include <common.h> -#include <asm/io.h> - -#ifdef CONFIG_AM33XX -#include <asm/arch/mux_am33xx.h> -#elif defined(CONFIG_TI814X) -#include <asm/arch/mux_ti814x.h> -#elif defined(CONFIG_TI816X) -#include <asm/arch/mux_ti816x.h> -#elif defined(CONFIG_AM43XX) -#include <asm/arch/mux_am43xx.h> -#endif - -struct module_pin_mux { - short reg_offset; - unsigned int val; -}; - -/* Pad control register offset */ -#define PAD_CTRL_BASE 0x800 -#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\ - (PAD_CTRL_BASE))->x) - -/* - * Configure the pin mux for the module - */ -void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); - -#endif /* endif _MUX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h deleted file mode 100644 index d5cab3e..0000000 --- a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * mux_am33xx.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_AM33XX_H_ -#define _MUX_AM33XX_H_ - -#include <common.h> -#include <asm/io.h> - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 6) -#define RXACTIVE (0x1 << 5) -#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int gpmc_ad0; - int gpmc_ad1; - int gpmc_ad2; - int gpmc_ad3; - int gpmc_ad4; - int gpmc_ad5; - int gpmc_ad6; - int gpmc_ad7; - int gpmc_ad8; - int gpmc_ad9; - int gpmc_ad10; - int gpmc_ad11; - int gpmc_ad12; - int gpmc_ad13; - int gpmc_ad14; - int gpmc_ad15; - int gpmc_a0; - int gpmc_a1; - int gpmc_a2; - int gpmc_a3; - int gpmc_a4; - int gpmc_a5; - int gpmc_a6; - int gpmc_a7; - int gpmc_a8; - int gpmc_a9; - int gpmc_a10; - int gpmc_a11; - int gpmc_wait0; - int gpmc_wpn; - int gpmc_be1n; - int gpmc_csn0; - int gpmc_csn1; - int gpmc_csn2; - int gpmc_csn3; - int gpmc_clk; - int gpmc_advn_ale; - int gpmc_oen_ren; - int gpmc_wen; - int gpmc_be0n_cle; - int lcd_data0; - int lcd_data1; - int lcd_data2; - int lcd_data3; - int lcd_data4; - int lcd_data5; - int lcd_data6; - int lcd_data7; - int lcd_data8; - int lcd_data9; - int lcd_data10; - int lcd_data11; - int lcd_data12; - int lcd_data13; - int lcd_data14; - int lcd_data15; - int lcd_vsync; - int lcd_hsync; - int lcd_pclk; - int lcd_ac_bias_en; - int mmc0_dat3; - int mmc0_dat2; - int mmc0_dat1; - int mmc0_dat0; - int mmc0_clk; - int mmc0_cmd; - int mii1_col; - int mii1_crs; - int mii1_rxerr; - int mii1_txen; - int mii1_rxdv; - int mii1_txd3; - int mii1_txd2; - int mii1_txd1; - int mii1_txd0; - int mii1_txclk; - int mii1_rxclk; - int mii1_rxd3; - int mii1_rxd2; - int mii1_rxd1; - int mii1_rxd0; - int rmii1_refclk; - int mdio_data; - int mdio_clk; - int spi0_sclk; - int spi0_d0; - int spi0_d1; - int spi0_cs0; - int spi0_cs1; - int ecap0_in_pwm0_out; - int uart0_ctsn; - int uart0_rtsn; - int uart0_rxd; - int uart0_txd; - int uart1_ctsn; - int uart1_rtsn; - int uart1_rxd; - int uart1_txd; - int i2c0_sda; - int i2c0_scl; - int mcasp0_aclkx; - int mcasp0_fsx; - int mcasp0_axr0; - int mcasp0_ahclkr; - int mcasp0_aclkr; - int mcasp0_fsr; - int mcasp0_axr1; - int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; - int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; - int rsvd1; - int tms; - int tdi; - int tdo; - int tck; - int ntrst; - int emu0; - int emu1; - int osc1_in; - int osc1_out; - int pmic_power_en; - int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; - int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; - int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; - int ddr_a0; - int ddr_a1; - int ddr_a2; - int ddr_a3; - int ddr_a4; - int ddr_a5; - int ddr_a6; - int ddr_a7; - int ddr_a8; - int ddr_a9; - int ddr_a10; - int ddr_a11; - int ddr_a12; - int ddr_a13; - int ddr_a14; - int ddr_a15; - int ddr_odt; - int ddr_d0; - int ddr_d1; - int ddr_d2; - int ddr_d3; - int ddr_d4; - int ddr_d5; - int ddr_d6; - int ddr_d7; - int ddr_d8; - int ddr_d9; - int ddr_d10; - int ddr_d11; - int ddr_d12; - int ddr_d13; - int ddr_d14; - int ddr_d15; - int ddr_dqm0; - int ddr_dqm1; - int ddr_dqs0; - int ddr_dqsn0; - int ddr_dqs1; - int ddr_dqsn1; - int ddr_vref; - int ddr_vtp; - int ddr_strben0; - int ddr_strben1; - int ain7; - int ain6; - int ain5; - int ain4; - int ain3; - int ain2; - int ain1; - int ain0; - int vrefp; - int vrefn; -}; - -#endif /* endif _MUX_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h deleted file mode 100644 index 256c5e2..0000000 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ /dev/null @@ -1,211 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * mux_am43xx.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef _MUX_AM43XX_H_ -#define _MUX_AM43XX_H_ - -#include <common.h> -#include <asm/io.h> - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 19) -#define RXACTIVE (0x1 << 18) -#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ -#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ -#define MODE(val) val /* used for Readability */ - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int gpmc_ad0; - int gpmc_ad1; - int gpmc_ad2; - int gpmc_ad3; - int gpmc_ad4; - int gpmc_ad5; - int gpmc_ad6; - int gpmc_ad7; - int gpmc_ad8; - int gpmc_ad9; - int gpmc_ad10; - int gpmc_ad11; - int gpmc_ad12; - int gpmc_ad13; - int gpmc_ad14; - int gpmc_ad15; - int gpmc_a0; - int gpmc_a1; - int gpmc_a2; - int gpmc_a3; - int gpmc_a4; - int gpmc_a5; - int gpmc_a6; - int gpmc_a7; - int gpmc_a8; - int gpmc_a9; - int gpmc_a10; - int gpmc_a11; - int gpmc_wait0; - int gpmc_wpn; - int gpmc_be1n; - int gpmc_csn0; - int gpmc_csn1; - int gpmc_csn2; - int gpmc_csn3; - int gpmc_clk; - int gpmc_advn_ale; - int gpmc_oen_ren; - int gpmc_wen; - int gpmc_be0n_cle; - int lcd_data0; - int lcd_data1; - int lcd_data2; - int lcd_data3; - int lcd_data4; - int lcd_data5; - int lcd_data6; - int lcd_data7; - int lcd_data8; - int lcd_data9; - int lcd_data10; - int lcd_data11; - int lcd_data12; - int lcd_data13; - int lcd_data14; - int lcd_data15; - int lcd_vsync; - int lcd_hsync; - int lcd_pclk; - int lcd_ac_bias_en; - int mmc0_dat3; - int mmc0_dat2; - int mmc0_dat1; - int mmc0_dat0; - int mmc0_clk; - int mmc0_cmd; - int mii1_col; - int mii1_crs; - int mii1_rxerr; - int mii1_txen; - int mii1_rxdv; - int mii1_txd3; - int mii1_txd2; - int mii1_txd1; - int mii1_txd0; - int mii1_txclk; - int mii1_rxclk; - int mii1_rxd3; - int mii1_rxd2; - int mii1_rxd1; - int mii1_rxd0; - int rmii1_refclk; - int mdio_data; - int mdio_clk; - int spi0_sclk; - int spi0_d0; - int spi0_d1; - int spi0_cs0; - int spi0_cs1; - int ecap0_in_pwm0_out; - int uart0_ctsn; - int uart0_rtsn; - int uart0_rxd; - int uart0_txd; - int uart1_ctsn; - int uart1_rtsn; - int uart1_rxd; - int uart1_txd; - int i2c0_sda; - int i2c0_scl; - int mcasp0_aclkx; - int mcasp0_fsx; - int mcasp0_axr0; - int mcasp0_ahclkr; - int mcasp0_aclkr; - int mcasp0_fsr; - int mcasp0_axr1; - int mcasp0_ahclkx; - int cam0_hd; - int cam0_vd; - int cam0_field; - int cam0_wen; - int cam0_pclk; - int cam0_data8; - int cam0_data9; - int cam1_data9; - int cam1_data8; - int cam1_hd; - int cam1_vd; - int cam1_pclk; - int cam1_field; - int cam1_wen; - int cam1_data0; - int cam1_data1; - int cam1_data2; - int cam1_data3; - int cam1_data4; - int cam1_data5; - int cam1_data6; - int cam1_data7; - int cam0_data0; - int cam0_data1; - int cam0_data2; - int cam0_data3; - int cam0_data4; - int cam0_data5; - int cam0_data6; - int cam0_data7; - int uart3_rxd; - int uart3_txd; - int uart3_ctsn; - int uart3_rtsn; - int gpio5_8; - int gpio5_9; - int gpio5_10; - int gpio5_11; - int gpio5_12; - int gpio5_13; - int spi4_sclk; - int spi4_d0; - int spi4_d1; - int spi4_cs0; - int spi2_sclk; - int spi2_d0; - int spi2_d1; - int spi2_cs0; - int xdma_evt_intr0; - int xdma_evt_intr1; - int clkreq; - int nresetin_out; - int rsvd1; - int nnmi; - int rsvd2; - int rsvd3; - int tms; - int tdi; - int tdo; - int tck; - int ntrst; - int emu0; - int emu1; - int osc1_in; - int osc1_out; - int rtc_porz; - int ext_wakeup0; - int pmic_power_en0; - int usb0_drvvbus; - int usb1_drvvbus; -}; - -#endif /* _MUX_AM43XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h deleted file mode 100644 index a26e503..0000000 --- a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * mux_ti814x.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI814X_H_ -#define _MUX_TI814X_H_ - -/* PAD Control Fields */ -#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ -#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -#define MUX_CFG(value, offset) \ -{ \ - int tmp; \ - tmp = __raw_readl(CTRL_BASE + offset); \ - tmp &= PINCNTL_RSV_MSK; \ - __raw_writel(tmp | value, (CTRL_BASE + offset));\ -} - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; -}; - -#endif /* endif _MUX_TI814X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h deleted file mode 100644 index e4e5a48..0000000 --- a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * mux_ti816x.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI816X_H_ -#define _MUX_TI816X_H_ - -#include <common.h> -#include <asm/io.h> - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) (val) /* used for Readability */ - - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; - int pincntl271; - int pincntl272; - int pincntl273; - int pincntl274; - int pincntl275; - int pincntl276; - int pincntl277; - int pincntl278; - int pincntl279; - int pincntl280; - int pincntl281; - int pincntl282; - int pincntl283; - int pincntl284; - int pincntl285; - int pincntl286; - int pincntl287; - int pincntl288; - int pincntl289; - int pincntl290; - int pincntl291; - int pincntl292; - int pincntl293; - int pincntl294; - int pincntl295; - int pincntl296; - int pincntl297; - int pincntl298; - int pincntl299; - int pincntl300; - int pincntl301; - int pincntl302; - int pincntl303; - int pincntl304; - int pincntl305; - int pincntl306; - int pincntl307; - int pincntl308; - int pincntl309; - int pincntl310; - int pincntl311; - int pincntl312; - int pincntl313; - int pincntl314; - int pincntl315; - int pincntl316; - int pincntl317; - int pincntl318; - int pincntl319; - int pincntl320; - int pincntl321; - int pincntl322; - int pincntl323; -}; - -#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h deleted file mode 100644 index bc9f0a1..0000000 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * omap.h - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * Author: - * Chandan Nath <chandan.nath@ti.com> - * - * Derived from OMAP4 work by - * Aneesh V <aneesh@ti.com> - */ - -#ifndef _OMAP_H_ -#define _OMAP_H_ - -#include <linux/sizes.h> - -#ifdef CONFIG_AM33XX -#define NON_SECURE_SRAM_START 0x402F0400 -#define NON_SECURE_SRAM_END 0x40310000 -#define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40320000 -#define NON_SECURE_SRAM_IMG_END 0x4031B800 -#elif defined(CONFIG_AM43XX) -#define NON_SECURE_SRAM_START 0x402F0400 -#define NON_SECURE_SRAM_END 0x40340000 -#define NON_SECURE_SRAM_IMG_END 0x40337DE0 -#define QSPI_BASE 0x47900000 -#endif -#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) - -/* Boot parameters */ -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - unsigned int reserved; - unsigned int boot_device_descriptor; - unsigned char boot_device; - unsigned char reset_reason; -}; - -#define DEVICE_TYPE_SHIFT 0x8 -#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) -#endif - -#endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h deleted file mode 100644 index f3910c2..0000000 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0x00 -#define BOOT_DEVICE_MMC2_2 0xFF - -#if defined(CONFIG_TI814X) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x05 -#define BOOT_DEVICE_NAND_I2C 0x06 -#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */ -#define BOOT_DEVICE_MMC1 0x09 -#define BOOT_DEVICE_SPI 0x15 -#define BOOT_DEVICE_UART 0x41 -#define BOOT_DEVICE_USBETH 0x44 -#define BOOT_DEVICE_CPGMAC 0x46 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#elif defined(CONFIG_TI816X) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x03 -#define BOOT_DEVICE_ONENAND 0x04 -#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */ -#define BOOT_DEVICE_MMC1 0x06 -#define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_USB 0x45 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#elif defined(CONFIG_AM33XX) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x05 -#define BOOT_DEVICE_NAND_I2C 0x06 -#define BOOT_DEVICE_MMC1 0x08 -#define BOOT_DEVICE_MMC2 0x09 -#define BOOT_DEVICE_SPI 0x0B -#define BOOT_DEVICE_UART 0x41 -#define BOOT_DEVICE_USBETH 0x44 -#define BOOT_DEVICE_CPGMAC 0x46 -#define BOOT_DEVICE_ONENAND 0xFF /* ROM does not support OneNAND. */ - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#elif defined(CONFIG_AM43XX) -#define BOOT_DEVICE_NOR 0x01 -#define BOOT_DEVICE_NAND 0x05 -#define BOOT_DEVICE_MMC1 0x07 -#define BOOT_DEVICE_MMC2 0x08 -#define BOOT_DEVICE_SPI 0x0A -#define BOOT_DEVICE_USB 0x0D -#define BOOT_DEVICE_UART 0x41 -#define BOOT_DEVICE_USBETH 0x45 -#define BOOT_DEVICE_CPGMAC 0x47 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#ifdef CONFIG_SPL_USB_STORAGE -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB -#else -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#endif -#endif - -#endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h deleted file mode 100644 index be17aad..0000000 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sys_proto.h - * - * System information header - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ -#include <linux/mtd/omap_gpmc.h> -#include <asm/arch/cpu.h> - -u32 get_cpu_rev(void); -u32 get_sysboot_value(void); - -extern struct ctrl_stat *cstat; -u32 get_device_type(void); -void save_omap_boot_params(void); -void setup_early_clocks(void); -void setup_clocks_for_console(void); -void mpu_pll_config_val(int mpull_m); -void ddr_pll_config(unsigned int ddrpll_M); - -void sdelay(unsigned long); - -void gpmc_init(void); -void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, - u32 size); -int omap_nand_switch_ecc(uint32_t, uint32_t); - -void set_uart_mux_conf(void); -void set_mux_conf_regs(void); -void sdram_init(void); -u32 wait_on_value(u32, u32, void *, u32); -#ifdef CONFIG_NOR_BOOT -void enable_norboot_pin_mux(void); -#endif -void am33xx_spl_board_init(void); -int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); -int am335x_get_mpu_vdd(int sil_rev, int frequency); -int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); -#endif - -void enable_usb_clocks(int index); -void disable_usb_clocks(int index); -void do_board_detect(void); -u32 get_sys_clk_index(void); diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h deleted file mode 100644 index dd21ad3..0000000 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * Contributor: Mahavir Jain <mjain@marvell.com> - */ - -#ifndef _ASM_ARCH_ARMADA100_H -#define _ASM_ARCH_ARMADA100_H - -#if defined (CONFIG_ARMADA100) - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ -#define APBC_RST (1<<2) /* Reset Generation */ -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -/* Fast Ethernet Controller Clock register definition */ -#define FE_CLK_RST 0x1 -#define FE_CLK_ENA 0x8 - -/* SSP2 Clock Control */ -#define SSP2_APBCLK 0x01 -#define SSP2_FNCLK 0x02 - -/* USB Clock/reset control bits */ -#define USB_SPH_AXICLK_EN 0x10 -#define USB_SPH_AXI_RST 0x02 - -/* MPMU Clocks */ -#define APB2_26M_EN (1 << 20) -#define AP_26M (1 << 4) - -/* Register Base Addresses */ -#define ARMD1_DRAM_BASE 0xB0000000 -#define ARMD1_FEC_BASE 0xC0800000 -#define ARMD1_TIMER_BASE 0xD4014000 -#define ARMD1_APBC1_BASE 0xD4015000 -#define ARMD1_APBC2_BASE 0xD4015800 -#define ARMD1_UART1_BASE 0xD4017000 -#define ARMD1_UART2_BASE 0xD4018000 -#define ARMD1_GPIO_BASE 0xD4019000 -#define ARMD1_SSP1_BASE 0xD401B000 -#define ARMD1_SSP2_BASE 0xD401C000 -#define ARMD1_MFPR_BASE 0xD401E000 -#define ARMD1_SSP3_BASE 0xD401F000 -#define ARMD1_SSP4_BASE 0xD4020000 -#define ARMD1_SSP5_BASE 0xD4021000 -#define ARMD1_UART3_BASE 0xD4026000 -#define ARMD1_MPMU_BASE 0xD4050000 -#define ARMD1_USB_HOST_BASE 0xD4209000 -#define ARMD1_APMU_BASE 0xD4282800 -#define ARMD1_CPU_BASE 0xD4282C00 - -#endif /* CONFIG_ARMADA100 */ -#endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h deleted file mode 100644 index 2862dd0..0000000 --- a/arch/arm/include/asm/arch-armada100/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - */ - -/* - * This file should be included in board config header file. - * - * It supports common definitions for Armada100 platform - */ - -#ifndef _ARMD1_CONFIG_H -#define _ARMD1_CONFIG_H - -#include <asm/arch/armada100.h> - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE ARMD1_MFPR_BASE -#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ - -#endif /* _ARMD1_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h deleted file mode 100644 index cd5e505..0000000 --- a/arch/arm/include/asm/arch-armada100/cpu.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com> - */ - -#ifndef _ARMADA100CPU_H -#define _ARMADA100CPU_H - -#include <asm/io.h> -#include <asm/system.h> - -/* - * Main Power Management (MPMU) Registers - * Refer Datasheet Appendix A.8 - */ -struct armd1mpmu_registers { - u8 pad0[0x08 - 0x00]; - u32 fccr; /*0x0008*/ - u32 pocr; /*0x000c*/ - u32 posr; /*0x0010*/ - u32 succr; /*0x0014*/ - u8 pad1[0x030 - 0x014 - 4]; - u32 gpcr; /*0x0030*/ - u8 pad2[0x200 - 0x030 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad3[0x1000 - 0x200 - 4]; - u32 apcr; /*0x1000*/ - u32 apsr; /*0x1004*/ - u8 pad4[0x1020 - 0x1004 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ - u32 arsr; /*0x1028*/ -}; - -/* - * Application Subsystem Power Management - * Refer Datasheet Appendix A.9 - */ -struct armd1apmu_registers { - u32 pcr; /* 0x000 */ - u32 ccr; /* 0x004 */ - u32 pad1; - u32 ccsr; /* 0x00C */ - u32 fc_timer; /* 0x010 */ - u32 pad2; - u32 ideal_cfg; /* 0x018 */ - u8 pad3[0x04C - 0x018 - 4]; - u32 lcdcrc; /* 0x04C */ - u32 cciccrc; /* 0x050 */ - u32 sd1crc; /* 0x054 */ - u32 sd2crc; /* 0x058 */ - u32 usbcrc; /* 0x05C */ - u32 nfccrc; /* 0x060 */ - u32 dmacrc; /* 0x064 */ - u32 pad4; - u32 buscrc; /* 0x06C */ - u8 pad5[0x07C - 0x06C - 4]; - u32 wake_clr; /* 0x07C */ - u8 pad6[0x090 - 0x07C - 4]; - u32 core_status; /* 0x090 */ - u32 rfsc; /* 0x094 */ - u32 imr; /* 0x098 */ - u32 irwc; /* 0x09C */ - u32 isr; /* 0x0A0 */ - u8 pad7[0x0B0 - 0x0A0 - 4]; - u32 mhst; /* 0x0B0 */ - u32 msr; /* 0x0B4 */ - u8 pad8[0x0C0 - 0x0B4 - 4]; - u32 msst; /* 0x0C0 */ - u32 pllss; /* 0x0C4 */ - u32 smb; /* 0x0C8 */ - u32 gccrc; /* 0x0CC */ - u8 pad9[0x0D4 - 0x0CC - 4]; - u32 smccrc; /* 0x0D4 */ - u32 pad10; - u32 xdcrc; /* 0x0DC */ - u32 sd3crc; /* 0x0E0 */ - u32 sd4crc; /* 0x0E4 */ - u8 pad11[0x0F0 - 0x0E4 - 4]; - u32 cfcrc; /* 0x0F0 */ - u32 mspcrc; /* 0x0F4 */ - u32 cmucrc; /* 0x0F8 */ - u32 fecrc; /* 0x0FC */ - u32 pciecrc; /* 0x100 */ - u32 epdcrc; /* 0x104 */ -}; - -/* - * APB1 Clock Reset/Control Registers - * Refer Datasheet Appendix A.10 - */ -struct armd1apb1_registers { - u32 uart1; /*0x000*/ - u32 uart2; /*0x004*/ - u32 gpio; /*0x008*/ - u32 pwm1; /*0x00c*/ - u32 pwm2; /*0x010*/ - u32 pwm3; /*0x014*/ - u32 pwm4; /*0x018*/ - u8 pad0[0x028 - 0x018 - 4]; - u32 rtc; /*0x028*/ - u32 twsi0; /*0x02c*/ - u32 kpc; /*0x030*/ - u32 timers; /*0x034*/ - u8 pad1[0x03c - 0x034 - 4]; - u32 aib; /*0x03c*/ - u32 sw_jtag; /*0x040*/ - u32 timer1; /*0x044*/ - u32 onewire; /*0x048*/ - u8 pad2[0x050 - 0x048 - 4]; - u32 asfar; /*0x050 AIB Secure First Access Reg*/ - u32 assar; /*0x054 AIB Secure Second Access Reg*/ - u8 pad3[0x06c - 0x054 - 4]; - u32 twsi1; /*0x06c*/ - u32 uart3; /*0x070*/ - u8 pad4[0x07c - 0x070 - 4]; - u32 timer2; /*0x07C*/ - u8 pad5[0x084 - 0x07c - 4]; - u32 ac97; /*0x084*/ -}; - -/* -* APB2 Clock Reset/Control Registers -* Refer Datasheet Appendix A.11 -*/ -struct armd1apb2_registers { - u32 pad1[0x01C - 0x000]; - u32 ssp1_clkrst; /* 0x01C */ - u32 ssp2_clkrst; /* 0x020 */ - u32 pad2[0x04C - 0x020 - 4]; - u32 ssp3_clkrst; /* 0x04C */ - u32 pad3[0x058 - 0x04C - 4]; - u32 ssp4_clkrst; /* 0x058 */ - u32 ssp5_clkrst; /* 0x05C */ -}; - -/* - * CPU Interface Registers - * Refer Datasheet Appendix A.2 - */ -struct armd1cpu_registers { - u32 chip_id; /* Chip Id Reg */ - u32 pad; - u32 cpu_conf; /* CPU Conf Reg */ - u32 pad1; - u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ - u32 pad2; - u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ - u32 mcb_conf; /* MCB Conf Reg */ - u32 sys_boot_ctl; /* Sytem Boot Control */ -}; - -/* - * Functions - */ -u32 armd1_sdram_base(int); -u32 armd1_sdram_size(int); - -#endif /* _ARMADA100CPU_H */ diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h deleted file mode 100644 index b85f6a5..0000000 --- a/arch/arm/include/asm/arch-armada100/gpio.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact@8051projects.net> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - */ - -#ifndef _ASM_ARCH_GPIO_H -#define _ASM_ARCH_GPIO_H - -#include <asm/types.h> -#include <asm/arch/armada100.h> - -#define GPIO_HIGH 1 -#define GPIO_LOW 0 - -#define GPIO_TO_REG(gp) (gp >> 5) -#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) -#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) - -static inline void *get_gpio_base(int bank) -{ - const unsigned int offset[4] = {0, 4, 8, 0x100}; - /* gpio register bank offset - refer Appendix A.36 */ - return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); -} - -#endif /* _ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h deleted file mode 100644 index a808ee8..0000000 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h - * (C) Copyright 2007 - * Marvell Semiconductor <www.marvell.com> - * 2007-08-21: eric miao <eric.miao@marvell.com> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * Contributor: Mahavir Jain <mjain@marvell.com> - */ - -#ifndef __ARMADA100_MFP_H -#define __ARMADA100_MFP_H - -/* - * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -/* UART1 */ -#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART2 */ -#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART3 */ -#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* I2c */ -#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) - -/* Fast Ethernet */ -#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) - -/* SPI */ -#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) - -/* More macros can be defined here... */ - -#define MFP_PIN_MAX 117 - -#endif /* __ARMADA100_MFP_H */ diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h deleted file mode 100644 index 873ba6e..0000000 --- a/arch/arm/include/asm/arch-armada100/spi.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact@8051projects.net> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - */ - -#ifndef __ARMADA100_SPI_H_ -#define __ARMADA100_SPI_H_ - -#include <asm/arch/armada100.h> - -#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE -#define SSP_REG_BASE(x) CAT_BASE_ADDR(x) - -/* - * SSP Serial Port Registers - * refer Appendix A.26 - */ -struct ssp_reg { - u32 sscr0; /* SSP Control Register 0 - 0x000 */ - u32 sscr1; /* SSP Control Register 1 - 0x004 */ - u32 sssr; /* SSP Status Register - 0x008 */ - u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ - u32 ssdr; /* SSP Data Register - 0x010 */ - u32 pad1[5]; - u32 ssto; /* SSP Timeout Register - 0x028 */ - u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ - u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ - u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ - u32 sstss; /* SSP Timeslot Status Register - 0x038 */ -}; - -#define DEFAULT_WORD_LEN 8 -#define SSP_FLUSH_NUM 0x2000 -#define RX_THRESH_DEF 8 -#define TX_THRESH_DEF 8 -#define TIMEOUT_DEF 1000 - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity - setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ -#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ - -#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ -#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out - Interrupt enable */ - -#define SSCR0_DSS 0x0f /* Data Size Select (mask) */ -#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF 0x30 /* FRame Format (mask) */ -#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial - Peripheral Interface */ -#define SSCR0_TI (0x1 << 4) /* TI's Synchronous - Serial Protocol (SSP) */ -#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port - Enable */ - -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ - -#endif /* __ARMADA100_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h deleted file mode 100644 index 28147f4..0000000 --- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact@8051projects.net> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - */ - -#ifndef __UTMI_ARMADA100__ -#define __UTMI_ARMADA100__ - -#define UTMI_PHY_BASE 0xD4206000 - -/* utmi_ctrl - bits */ -#define INPKT_DELAY_SOF (1 << 28) -#define PLL_PWR_UP 2 -#define PHY_PWR_UP 1 - -/* utmi_pll - bits */ -#define PLL_FBDIV_MASK 0x00000FF0 -#define PLL_FBDIV 4 -#define PLL_REFDIV_MASK 0x0000000F -#define PLL_REFDIV 0 -#define PLL_READY 0x800000 -#define VCOCAL_START (1 << 21) - -#define N_DIVIDER 0xEE -#define M_DIVIDER 0x0B - -/* utmi_tx - bits */ -#define CK60_PHSEL 17 -#define PHSEL_VAL 0x4 -#define RCAL_START (1 << 12) - -/* - * USB PHY registers - * Refer Datasheet Appendix A.21 - */ -struct armd1usb_phy_reg { - u32 utmi_rev; /* USB PHY Revision */ - u32 utmi_ctrl; /* USB PHY Control register */ - u32 utmi_pll; /* PLL register */ - u32 utmi_tx; /* Tx register */ - u32 utmi_rx; /* Rx register */ - u32 utmi_ivref; /* IVREF register */ - u32 utmi_tst_g0; /* Test group 0 register */ - u32 utmi_tst_g1; /* Test group 1 register */ - u32 utmi_tst_g2; /* Test group 2 register */ - u32 utmi_tst_g3; /* Test group 3 register */ - u32 utmi_tst_g4; /* Test group 4 register */ - u32 utmi_tst_g5; /* Test group 5 register */ - u32 utmi_reserve; /* Reserve Register */ - u32 utmi_usb_int; /* USB interuppt register */ - u32 utmi_dbg_ctl; /* Debug control register */ - u32 utmi_otg_addon; /* OTG addon register */ -}; - -int utmi_init(void); - -#endif /* __UTMI_ARMADA100__ */ diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h deleted file mode 100644 index 8cb1144..0000000 --- a/arch/arm/include/asm/arch-armada8k/cache_llc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Marvell International Ltd. - * https://spdx.org/licenses - */ - -#ifndef _CACHE_LLC_H_ -#define _CACHE_LLC_H_ - -/* Armada-7K/8K last level cache */ - -#define MVEBU_A8K_REGS_BASE_MSB 0xf000 -#define LLC_BASE_ADDR 0x8000 -#define LLC_CACHE_SYNC 0x700 -#define LLC_CACHE_SYNC_COMPLETE 0x730 -#define LLC_FLUSH_BY_WAY 0x7fc -#define LLC_WAY_MASK 0xffffffff -#define LLC_CACHE_SYNC_MASK 0x1 - -#endif /* _CACHE_LLC_H_ */ diff --git a/arch/arm/include/asm/arch-armada8k/soc-info.h b/arch/arm/include/asm/arch-armada8k/soc-info.h deleted file mode 100644 index 64606ef..0000000 --- a/arch/arm/include/asm/arch-armada8k/soc-info.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Marvell International Ltd. - * https://spdx.org/licenses - */ - -#ifndef _SOC_INFO_H_ -#define _SOC_INFO_H_ - -/* Pin Ctrl driver definitions */ -#define BITS_PER_PIN 4 -#define PIN_FUNC_MASK ((1 << BITS_PER_PIN) - 1) -#define PIN_REG_SHIFT 3 -#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1) - -#endif /* _SOC_INFO_H_ */ diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h b/arch/arm/include/asm/arch-armv7/generictimer.h deleted file mode 100644 index f402686..0000000 --- a/arch/arm/include/asm/arch-armv7/generictimer.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2013 - ARM Ltd - * Author: Marc Zyngier <marc.zyngier@arm.com> - * - * Based on code by Carl van Schaik <carl@ok-labs.com>. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _GENERICTIMER_H_ -#define _GENERICTIMER_H_ - -#ifdef __ASSEMBLY__ - -/* - * This macro provide a physical timer that can be used for delay in the code. - * The macro is moved from sunxi/psci_sun7i.S - * - * reg: is used in this macro. - * ticks: The freq is based on generic timer. - */ -.macro timer_wait reg, ticks - movw \reg, #(\ticks & 0xffff) - movt \reg, #(\ticks >> 16) - mcr p15, 0, \reg, c14, c2, 0 - isb - mov \reg, #3 - mcr p15, 0, \reg, c14, c2, 1 -1 : isb - mrc p15, 0, \reg, c14, c2, 1 - ands \reg, \reg, #4 - bne 1b - mov \reg, #0 - mcr p15, 0, \reg, c14, c2, 1 - isb -.endm - -#endif /* __ASSEMBLY__ */ - -#endif /* _GENERICTIMER_H_ */ diff --git a/arch/arm/include/asm/arch-armv7/globaltimer.h b/arch/arm/include/asm/arch-armv7/globaltimer.h deleted file mode 100644 index 2d9cf77..0000000 --- a/arch/arm/include/asm/arch-armv7/globaltimer.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012 Renesas Solutions Corp. - */ -#ifndef _GLOBALTIMER_H_ -#define _GLOBALTIMER_H_ - -struct globaltimer { - u32 cnt_l; /* 0x00 */ - u32 cnt_h; - u32 ctl; - u32 stat; - u32 cmp_l; /* 0x10 */ - u32 cmp_h; - u32 inc; -}; - -#endif /* _GLOBALTIMER_H_ */ diff --git a/arch/arm/include/asm/arch-armv7/sysctrl.h b/arch/arm/include/asm/arch-armv7/sysctrl.h deleted file mode 100644 index fc72fac..0000000 --- a/arch/arm/include/asm/arch-armv7/sysctrl.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 Linaro - * Matt Waddel, <matt.waddel@linaro.org> - */ -#ifndef _SYSCTRL_H_ -#define _SYSCTRL_H_ - -/* System controller (SP810) register definitions */ -#define SP810_TIMER0_ENSEL (1 << 15) -#define SP810_TIMER1_ENSEL (1 << 17) -#define SP810_TIMER2_ENSEL (1 << 19) -#define SP810_TIMER3_ENSEL (1 << 21) - -struct sysctrl { - u32 scctrl; /* 0x000 */ - u32 scsysstat; - u32 scimctrl; - u32 scimstat; - u32 scxtalctrl; - u32 scpllctrl; - u32 scpllfctrl; - u32 scperctrl0; - u32 scperctrl1; - u32 scperen; - u32 scperdis; - u32 scperclken; - u32 scperstat; - u32 res1[0x006]; - u32 scflashctrl; /* 0x04c */ - u32 res2[0x3a4]; - u32 scsysid0; /* 0xee0 */ - u32 scsysid1; - u32 scsysid2; - u32 scsysid3; - u32 scitcr; - u32 scitir0; - u32 scitir1; - u32 scitor; - u32 sccntctrl; - u32 sccntdata; - u32 sccntstep; - u32 res3[0x32]; - u32 scperiphid0; /* 0xfe0 */ - u32 scperiphid1; - u32 scperiphid2; - u32 scperiphid3; - u32 scpcellid0; - u32 scpcellid1; - u32 scpcellid2; - u32 scpcellid3; -}; -#endif /* _SYSCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h deleted file mode 100644 index 04c4130..0000000 --- a/arch/arm/include/asm/arch-armv7/systimer.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 Linaro - * Matt Waddel, <matt.waddel@linaro.org> - */ -#ifndef _SYSTIMER_H_ -#define _SYSTIMER_H_ - -/* AMBA timer register base address */ -#define SYSTIMER_BASE 0x10011000 - -#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ -#define SYSTIMER_RELOAD 0xFFFFFFFF -#define SYSTIMER_EN (1 << 7) -#define SYSTIMER_32BIT (1 << 1) -#define SYSTIMER_PRESC_16 (1 << 2) -#define SYSTIMER_PRESC_256 (1 << 3) - -struct systimer { - u32 timer0load; /* 0x00 */ - u32 timer0value; - u32 timer0control; - u32 timer0intclr; - u32 timer0ris; - u32 timer0mis; - u32 timer0bgload; - u32 timer1load; /* 0x20 */ - u32 timer1value; - u32 timer1control; - u32 timer1intclr; - u32 timer1ris; - u32 timer1mis; - u32 timer1bgload; -}; -#endif /* _SYSTIMER_H_ */ diff --git a/arch/arm/include/asm/arch-armv7/wdt.h b/arch/arm/include/asm/arch-armv7/wdt.h deleted file mode 100644 index e3fa16f..0000000 --- a/arch/arm/include/asm/arch-armv7/wdt.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Matt Waddel, <matt.waddel@linaro.org> - */ -#ifndef _WDT_H_ -#define _WDT_H_ - -/* Watchdog timer (SP805) register base address */ -#define WDT_BASE 0x100E5000 - -#define WDT_EN 0x2 -#define WDT_RESET_LOAD 0x0 - -struct wdt { - u32 wdogload; /* 0x000 */ - u32 wdogvalue; - u32 wdogcontrol; - u32 wdogintclr; - u32 wdogris; - u32 wdogmis; - u32 res1[0x2F9]; - u32 wdoglock; /* 0xC00 */ - u32 res2[0xBE]; - u32 wdogitcr; /* 0xF00 */ - u32 wdogitop; - u32 res3[0x35]; - u32 wdogperiphid0; /* 0xFE0 */ - u32 wdogperiphid1; - u32 wdogperiphid2; - u32 wdogperiphid3; - u32 wdogpcellid0; - u32 wdogpcellid1; - u32 wdogpcellid2; - u32 wdogpcellid3; -}; - -#endif /* _WDT_H_ */ diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h b/arch/arm/include/asm/arch-aspeed/pinctrl.h deleted file mode 100644 index dd85464..0000000 --- a/arch/arm/include/asm/arch-aspeed/pinctrl.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Google, Inc - */ -#ifndef _ASM_ARCH_PERIPH_H -#define _ASM_ARCH_PERIPH_H - -/* - * Peripherals supported by the hardware. - * These are used to specify pinctrl settings. - */ - -enum periph_id { - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_UART4, - PERIPH_ID_LPC, - PERIPH_ID_PWM0, - PERIPH_ID_PWM1, - PERIPH_ID_PWM2, - PERIPH_ID_PWM3, - PERIPH_ID_PWM4, - PERIPH_ID_PWM5, - PERIPH_ID_PWM6, - PERIPH_ID_PWM7, - PERIPH_ID_PWM8, - PERIPH_ID_MAC1, - PERIPH_ID_MAC2, - PERIPH_ID_VIDEO, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_I2C8, - PERIPH_ID_I2C9, - PERIPH_ID_I2C10, - PERIPH_ID_I2C11, - PERIPH_ID_I2C12, - PERIPH_ID_I2C13, - PERIPH_ID_I2C14, - PERIPH_ID_SD1, - PERIPH_ID_SD2, -}; - -#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h deleted file mode 100644 index 8db4901..0000000 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - */ -#ifndef _ASM_ARCH_SCU_AST2500_H -#define _ASM_ARCH_SCU_AST2500_H - -#define SCU_UNLOCK_VALUE 0x1688a8a8 - -#define SCU_HWSTRAP_VGAMEM_SHIFT 2 -#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) -#define SCU_HWSTRAP_MAC1_RGMII (1 << 6) -#define SCU_HWSTRAP_MAC2_RGMII (1 << 7) -#define SCU_HWSTRAP_DDR4 (1 << 24) -#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) - -#define SCU_MPLL_DENUM_SHIFT 0 -#define SCU_MPLL_DENUM_MASK 0x1f -#define SCU_MPLL_NUM_SHIFT 5 -#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) -#define SCU_MPLL_POST_SHIFT 13 -#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) -#define SCU_PCLK_DIV_SHIFT 23 -#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) -#define SCU_SDCLK_DIV_SHIFT 12 -#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT) -#define SCU_HPLL_DENUM_SHIFT 0 -#define SCU_HPLL_DENUM_MASK 0x1f -#define SCU_HPLL_NUM_SHIFT 5 -#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) -#define SCU_HPLL_POST_SHIFT 13 -#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) - -#define SCU_MACCLK_SHIFT 16 -#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) - -#define SCU_MISC2_RGMII_HPLL (1 << 23) -#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 -#define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) -#define SCU_MISC2_RMII_MPLL (1 << 19) -#define SCU_MISC2_RMII_CLKDIV_SHIFT 16 -#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) -#define SCU_MISC2_UARTCLK_SHIFT 24 - -#define SCU_MISC_D2PLL_OFF (1 << 4) -#define SCU_MISC_UARTCLK_DIV13 (1 << 12) -#define SCU_MISC_GCRT_USB20CLK (1 << 21) - -#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 -#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ - << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) -#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 -#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ - << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) -#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 -#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) -#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 -#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) -#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) -#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) -#define SCU_MICDS_RMII1_RCLKEN (1 << 29) -#define SCU_MICDS_RMII2_RCLKEN (1 << 30) -#define SCU_MICDS_RGMIIPLL (1 << 31) - -/* - * SYSRESET is actually more like a Power register, - * except that corresponding bit set to 1 means that - * the peripheral is off. - */ -#define SCU_SYSRESET_XDMA (1 << 25) -#define SCU_SYSRESET_MCTP (1 << 24) -#define SCU_SYSRESET_ADC (1 << 23) -#define SCU_SYSRESET_JTAG (1 << 22) -#define SCU_SYSRESET_MIC (1 << 18) -#define SCU_SYSRESET_SDIO (1 << 16) -#define SCU_SYSRESET_USB11HOST (1 << 15) -#define SCU_SYSRESET_USBHUB (1 << 14) -#define SCU_SYSRESET_CRT (1 << 13) -#define SCU_SYSRESET_MAC2 (1 << 12) -#define SCU_SYSRESET_MAC1 (1 << 11) -#define SCU_SYSRESET_PECI (1 << 10) -#define SCU_SYSRESET_PWM (1 << 9) -#define SCU_SYSRESET_PCI_VGA (1 << 8) -#define SCU_SYSRESET_2D (1 << 7) -#define SCU_SYSRESET_VIDEO (1 << 6) -#define SCU_SYSRESET_LPC (1 << 5) -#define SCU_SYSRESET_HAC (1 << 4) -#define SCU_SYSRESET_USBHID (1 << 3) -#define SCU_SYSRESET_I2C (1 << 2) -#define SCU_SYSRESET_AHB (1 << 1) -#define SCU_SYSRESET_SDRAM_WDT (1 << 0) - -/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ -#define SCU_PINMUX_CTRL5_I2C (1 << 16) - -/* - * The values are grouped by function, not by register. - * They are actually scattered across multiple loosely related registers. - */ -#define SCU_PIN_FUN_MAC1_MDC (1 << 30) -#define SCU_PIN_FUN_MAC1_MDIO (1 << 31) -#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) -#define SCU_PIN_FUN_MAC2_MDIO (1 << 2) -#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) -#define SCU_PIN_FUN_SCL1 (1 << 12) -#define SCU_PIN_FUN_SCL2 (1 << 14) -#define SCU_PIN_FUN_SDA1 (1 << 13) -#define SCU_PIN_FUN_SDA2 (1 << 15) - -#define SCU_CLKSTOP_MAC1 (1 << 20) -#define SCU_CLKSTOP_MAC2 (1 << 21) -#define SCU_CLKSTOP_SDCLK (1 << 27) - -#define SCU_D2PLL_EXT1_OFF (1 << 0) -#define SCU_D2PLL_EXT1_BYPASS (1 << 1) -#define SCU_D2PLL_EXT1_RESET (1 << 2) -#define SCU_D2PLL_EXT1_MODE_SHIFT 3 -#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) -#define SCU_D2PLL_EXT1_PARAM_SHIFT 5 -#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) - -#define SCU_D2PLL_NUM_SHIFT 0 -#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) -#define SCU_D2PLL_DENUM_SHIFT 8 -#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) -#define SCU_D2PLL_POST_SHIFT 13 -#define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) -#define SCU_D2PLL_ODIV_SHIFT 19 -#define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) -#define SCU_D2PLL_SIC_SHIFT 22 -#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) -#define SCU_D2PLL_SIP_SHIFT 27 -#define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) - -#define SCU_CLKDUTY_DCLK_SHIFT 0 -#define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) -#define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 -#define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) -#define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 -#define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) - -#ifndef __ASSEMBLY__ - -struct ast2500_clk_priv { - struct ast2500_scu *scu; -}; - -struct ast2500_scu { - u32 protection_key; - u32 sysreset_ctrl1; - u32 clk_sel1; - u32 clk_stop_ctrl1; - u32 freq_counter_ctrl; - u32 freq_counter_cmp; - u32 intr_ctrl; - u32 d2_pll_param; - u32 m_pll_param; - u32 h_pll_param; - u32 d_pll_param; - u32 misc_ctrl1; - u32 pci_config[3]; - u32 sysreset_status; - u32 vga_handshake[2]; - u32 mac_clk_delay; - u32 misc_ctrl2; - u32 vga_scratch[8]; - u32 hwstrap; - u32 rng_ctrl; - u32 rng_data; - u32 rev_id; - u32 pinmux_ctrl[6]; - u32 reserved0; - u32 extrst_sel; - u32 pinmux_ctrl1[4]; - u32 reserved1[2]; - u32 mac_clk_delay_100M; - u32 mac_clk_delay_10M; - u32 wakeup_enable; - u32 wakeup_control; - u32 reserved2[3]; - u32 sysreset_ctrl2; - u32 clk_sel2; - u32 clk_stop_ctrl2; - u32 freerun_counter; - u32 freerun_counter_ext; - u32 clk_duty_meas_ctrl; - u32 clk_duty_meas_res; - u32 reserved3[4]; - /* The next registers are not key-protected */ - struct ast2500_cpu2 { - u32 ctrl; - u32 base_addr[9]; - u32 cache_ctrl; - } cpu2; - u32 reserved4; - u32 d_pll_ext_param[3]; - u32 d2_pll_ext_param[3]; - u32 mh_pll_ext_param; - u32 reserved5; - u32 chip_id[2]; - u32 reserved6[2]; - u32 uart_clk_ctrl; - u32 reserved7[7]; - u32 pcie_config; - u32 mmio_decode; - u32 reloc_ctrl_decode[2]; - u32 mailbox_addr; - u32 shared_sram_decode[2]; - u32 bmc_rev_id; - u32 reserved8; - u32 bmc_device_id; - u32 reserved9[13]; - u32 clk_duty_sel; -}; - -/** - * ast_get_clk() - get a pointer to Clock Driver - * - * @devp, OUT - pointer to Clock Driver - * @return zero on success, error code (< 0) otherwise. - */ -int ast_get_clk(struct udevice **devp); - -/** - * ast_get_scu() - get a pointer to SCU registers - * - * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise - */ -void *ast_get_scu(void); - -/** - * ast_scu_unlock() - unlock protected registers - * - * @scu, pointer to ast2500_scu - */ -void ast_scu_unlock(struct ast2500_scu *scu); - -/** - * ast_scu_lock() - lock protected registers - * - * @scu, pointer to ast2500_scu - */ -void ast_scu_lock(struct ast2500_scu *scu); - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h deleted file mode 100644 index 0bc551f..0000000 --- a/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - */ -#ifndef _ASM_ARCH_SDRAM_AST2500_H -#define _ASM_ARCH_SDRAM_AST2500_H - -#define SDRAM_UNLOCK_KEY 0xfc600309 -#define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f - -#define SDRAM_PCR_CKE_EN (1 << 0) -#define SDRAM_PCR_AUTOPWRDN_EN (1 << 1) -#define SDRAM_PCR_CKE_DELAY_SHIFT 4 -#define SDRAM_PCR_CKE_DELAY_MASK 7 -#define SDRAM_PCR_RESETN_DIS (1 << 7) -#define SDRAM_PCR_ODT_EN (1 << 8) -#define SDRAM_PCR_ODT_AUTO_ON (1 << 10) -#define SDRAM_PCR_ODT_EXT_EN (1 << 11) -#define SDRAM_PCR_TCKE_PW_SHIFT 12 -#define SDRAM_PCR_TCKE_PW_MASK 7 -#define SDRAM_PCR_RGAP_CTRL_EN (1 << 15) -#define SDRAM_PCR_MREQI_DIS (1 << 17) - -/* Fixed priority DRAM Requests mask */ -#define SDRAM_REQ_VGA_HW_CURSOR (1 << 0) -#define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1) -#define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2) -#define SDRAM_REQ_VGA_CRT (1 << 3) -#define SDRAM_REQ_SOC_DC_CURSOR (1 << 4) -#define SDRAM_REQ_SOC_DC_OCD (1 << 5) -#define SDRAM_REQ_SOC_DC_CRT (1 << 6) -#define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7) -#define SDRAM_REQ_USB20_EHCI1 (1 << 8) -#define SDRAM_REQ_USB20_EHCI2 (1 << 9) -#define SDRAM_REQ_CPU (1 << 10) -#define SDRAM_REQ_AHB2 (1 << 11) -#define SDRAM_REQ_AHB (1 << 12) -#define SDRAM_REQ_MAC0 (1 << 13) -#define SDRAM_REQ_MAC1 (1 << 14) -#define SDRAM_REQ_PCIE (1 << 16) -#define SDRAM_REQ_XDMA (1 << 17) -#define SDRAM_REQ_ENCRYPTION (1 << 18) -#define SDRAM_REQ_VIDEO_FLAG (1 << 21) -#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28) -#define SDRAM_REQ_2D_RW (1 << 29) -#define SDRAM_REQ_MEMCHECK (1 << 30) - -#define SDRAM_ICR_RESET_ALL (1 << 31) - -#define SDRAM_CONF_CAP_SHIFT 0 -#define SDRAM_CONF_CAP_MASK 3 -#define SDRAM_CONF_DDR4 (1 << 4) -#define SDRAM_CONF_SCRAMBLE (1 << 8) -#define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9) -#define SDRAM_CONF_CACHE_EN (1 << 10) -#define SDRAM_CONF_CACHE_INIT_EN (1 << 12) -#define SDRAM_CONF_DUALX8 (1 << 13) -#define SDRAM_CONF_CACHE_INIT_DONE (1 << 19) - -#define SDRAM_CONF_CAP_128M 0 -#define SDRAM_CONF_CAP_256M 1 -#define SDRAM_CONF_CAP_512M 2 -#define SDRAM_CONF_CAP_1024M 3 - -#define SDRAM_MISC_DDR4_TREFRESH (1 << 3) - -#define SDRAM_PHYCTRL0_INIT (1 << 0) -#define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1) -#define SDRAM_PHYCTRL0_NRST (1 << 2) - -#define SDRAM_REFRESH_CYCLES_SHIFT 0 -#define SDRAM_REFRESH_CYCLES_MASK 0xf -#define SDRAM_REFRESH_ZQCS_EN (1 << 7) -#define SDRAM_REFRESH_PERIOD_SHIFT 8 -#define SDRAM_REFRESH_PERIOD_MASK 0xf - -#define SDRAM_TEST_LEN_SHIFT 4 -#define SDRAM_TEST_LEN_MASK 0xfffff -#define SDRAM_TEST_START_ADDR_SHIFT 24 -#define SDRAM_TEST_START_ADDR_MASK 0x3f - -#define SDRAM_TEST_EN (1 << 0) -#define SDRAM_TEST_MODE_SHIFT 1 -#define SDRAM_TEST_MODE_MASK 3 -#define SDRAM_TEST_MODE_WO 0 -#define SDRAM_TEST_MODE_RB 1 -#define SDRAM_TEST_MODE_RW 2 -#define SDRAM_TEST_GEN_MODE_SHIFT 3 -#define SDRAM_TEST_GEN_MODE_MASK 7 -#define SDRAM_TEST_TWO_MODES (1 << 6) -#define SDRAM_TEST_ERRSTOP (1 << 7) -#define SDRAM_TEST_DONE (1 << 12) -#define SDRAM_TEST_FAIL (1 << 13) - -#define SDRAM_AC_TRFC_SHIFT 0 -#define SDRAM_AC_TRFC_MASK 0xff - -#ifndef __ASSEMBLY__ - -struct ast2500_sdrammc_regs { - u32 protection_key; - u32 config; - u32 gm_protection_key; - u32 refresh_timing; - u32 ac_timing[3]; - u32 misc_control; - u32 mr46_mode_setting; - u32 mr5_mode_setting; - u32 mode_setting_control; - u32 mr02_mode_setting; - u32 mr13_mode_setting; - u32 power_control; - u32 req_limit_mask; - u32 pri_group_setting; - u32 max_grant_len[4]; - u32 intr_ctrl; - u32 ecc_range_ctrl; - u32 first_ecc_err_addr; - u32 last_ecc_err_addr; - u32 phy_ctrl[4]; - u32 ecc_test_ctrl; - u32 test_addr; - u32 test_fail_dq_bit; - u32 test_init_val; - u32 phy_debug_ctrl; - u32 phy_debug_data; - u32 reserved1[30]; - u32 scu_passwd; - u32 reserved2[7]; - u32 scu_mpll; - u32 reserved3[19]; - u32 scu_hwstrap; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_SDRAM_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/timer.h b/arch/arm/include/asm/arch-aspeed/timer.h deleted file mode 100644 index ff24e2f..0000000 --- a/arch/arm/include/asm/arch-aspeed/timer.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - */ -#ifndef _ASM_ARCH_TIMER_H -#define _ASM_ARCH_TIMER_H - -/* Each timer has 4 control bits in ctrl1 register. - * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on, - * such that timer X uses bits (4 * X - 4):(4 * X - 1) - * If the timer does not support PWM, bit 4 is reserved. - */ -#define AST_TMC_EN (1 << 0) -#define AST_TMC_1MHZ (1 << 1) -#define AST_TMC_OVFINTR (1 << 2) -#define AST_TMC_PWM (1 << 3) - -/* Timers are counted from 1 in the datasheet. */ -#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1)) - -#define AST_TMC_RATE (1000*1000) - -#ifndef __ASSEMBLY__ - -/* - * All timers share control registers, which makes it harder to make them - * separate devices. Since only one timer is needed at the moment, making - * it this just one device. - */ - -struct ast_timer_counter { - u32 status; - u32 reload_val; - u32 match1; - u32 match2; -}; - -struct ast_timer { - struct ast_timer_counter timers1[3]; - u32 ctrl1; - u32 ctrl2; -#ifdef CONFIG_ASPEED_AST2500 - u32 ctrl3; - u32 ctrl1_clr; -#else - u32 reserved[2]; -#endif - struct ast_timer_counter timers2[5]; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_TIMER_H */ diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h b/arch/arm/include/asm/arch-aspeed/wdt.h deleted file mode 100644 index fb04d41..0000000 --- a/arch/arm/include/asm/arch-aspeed/wdt.h +++ /dev/null @@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Google, Inc - */ - -#ifndef _ASM_ARCH_WDT_H -#define _ASM_ARCH_WDT_H - -#define WDT_BASE 0x1e785000 - -/* - * Special value that needs to be written to counter_restart register to - * (re)start the timer - */ -#define WDT_COUNTER_RESTART_VAL 0x4755 - -/* Control register */ -#define WDT_CTRL_RESET_MODE_SHIFT 5 -#define WDT_CTRL_RESET_MODE_MASK 3 - -#define WDT_CTRL_EN (1 << 0) -#define WDT_CTRL_RESET (1 << 1) -#define WDT_CTRL_CLK1MHZ (1 << 4) -#define WDT_CTRL_2ND_BOOT (1 << 7) - -/* Values for Reset Mode */ -#define WDT_CTRL_RESET_SOC 0 -#define WDT_CTRL_RESET_CHIP 1 -#define WDT_CTRL_RESET_CPU 2 -#define WDT_CTRL_RESET_MASK 3 - -/* Reset Mask register */ -#define WDT_RESET_ARM (1 << 0) -#define WDT_RESET_COPROC (1 << 1) -#define WDT_RESET_SDRAM (1 << 2) -#define WDT_RESET_AHB (1 << 3) -#define WDT_RESET_I2C (1 << 4) -#define WDT_RESET_MAC1 (1 << 5) -#define WDT_RESET_MAC2 (1 << 6) -#define WDT_RESET_GCRT (1 << 7) -#define WDT_RESET_USB20 (1 << 8) -#define WDT_RESET_USB11_HOST (1 << 9) -#define WDT_RESET_USB11_EHCI2 (1 << 10) -#define WDT_RESET_VIDEO (1 << 11) -#define WDT_RESET_HAC (1 << 12) -#define WDT_RESET_LPC (1 << 13) -#define WDT_RESET_SDSDIO (1 << 14) -#define WDT_RESET_MIC (1 << 15) -#define WDT_RESET_CRT2C (1 << 16) -#define WDT_RESET_PWM (1 << 17) -#define WDT_RESET_PECI (1 << 18) -#define WDT_RESET_JTAG (1 << 19) -#define WDT_RESET_ADC (1 << 20) -#define WDT_RESET_GPIO (1 << 21) -#define WDT_RESET_MCTP (1 << 22) -#define WDT_RESET_XDMA (1 << 23) -#define WDT_RESET_SPI (1 << 24) -#define WDT_RESET_MISC (1 << 25) - -#define WDT_RESET_DEFAULT \ - (WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \ - WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \ - WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \ - WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC | \ - WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C | \ - WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG | \ - WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC) - -#ifndef __ASSEMBLY__ -struct ast_wdt { - u32 counter_status; - u32 counter_reload_val; - u32 counter_restart; - u32 ctrl; - u32 timeout_status; - u32 clr_timeout_status; - u32 reset_width; - /* On pre-ast2500 SoCs this register is reserved. */ - u32 reset_mask; -}; - -/** - * Given flags parameter passed to wdt_reset or wdt_start uclass functions, - * gets Reset Mode value from it. - * - * @flags: flags parameter passed into wdt_reset or wdt_start - * @return Reset Mode value - */ -u32 ast_reset_mode_from_flags(ulong flags); - -/** - * Given flags parameter passed to wdt_reset or wdt_start uclass functions, - * gets Reset Mask value from it. Reset Mask is only supported on ast2500 - * - * @flags: flags parameter passed into wdt_reset or wdt_start - * @return Reset Mask value - */ -u32 ast_reset_mask_from_flags(ulong flags); - -/** - * Given Reset Mask and Reset Mode values, converts them to flags, - * suitable for passing into wdt_start or wdt_reset uclass functions. - * - * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they - * can both be packed into single 32 bits wide value. - * - * @reset_mode: Reset Mode - * @reset_mask: Reset Mask - */ -ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask); -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_WDT_H */ diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h deleted file mode 100644 index 8cde42b..0000000 --- a/arch/arm/include/asm/arch-bcm235xx/boot0.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Broadcom Corporation. - */ - -/* BOOT0 header information */ -_start: - ARM_VECTORS - .word 0xbabeface - .word _end - _start diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h deleted file mode 100644 index 82c12bb..0000000 --- a/arch/arm/include/asm/arch-bcm235xx/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM235XX_GPIO_H -#define __ARCH_BCM235XX_GPIO_H - -/* - * Empty file - cmd_gpio.c requires this. The implementation - * is in drivers/gpio/kona_gpio.c instead of inlined here. - */ - -#endif diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h deleted file mode 100644 index ff6debc..0000000 --- a/arch/arm/include/asm/arch-bcm235xx/sysmap.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM235XX_SYSMAP_H - -#define BSC1_BASE_ADDR 0x3e016000 -#define BSC2_BASE_ADDR 0x3e017000 -#define BSC3_BASE_ADDR 0x3e018000 -#define GPIO2_BASE_ADDR 0x35003000 -#define HSOTG_BASE_ADDR 0x3f120000 -#define HSOTG_CTRL_BASE_ADDR 0x3f130000 -#define KONA_MST_CLK_BASE_ADDR 0x3f001000 -#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 -#define PMU_BSC_BASE_ADDR 0x3500d000 -#define SDIO1_BASE_ADDR 0x3f180000 -#define SDIO2_BASE_ADDR 0x3f190000 -#define SDIO3_BASE_ADDR 0x3f1a0000 -#define SDIO4_BASE_ADDR 0x3f1b0000 -#define TIMER_BASE_ADDR 0x3e00d000 - -#define HSOTG_DCTL_OFFSET 0x00000804 -#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 - -#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 -#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 -#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 - -#endif diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h deleted file mode 100644 index 8cde42b..0000000 --- a/arch/arm/include/asm/arch-bcm281xx/boot0.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Broadcom Corporation. - */ - -/* BOOT0 header information */ -_start: - ARM_VECTORS - .word 0xbabeface - .word _end - _start diff --git a/arch/arm/include/asm/arch-bcm281xx/gpio.h b/arch/arm/include/asm/arch-bcm281xx/gpio.h deleted file mode 100644 index 6716e1a..0000000 --- a/arch/arm/include/asm/arch-bcm281xx/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM281XX_GPIO_H -#define __ARCH_BCM281XX_GPIO_H - -/* - * Empty file - cmd_gpio.c requires this. The implementation - * is in drivers/gpio/kona_gpio.c instead of inlined here. - */ - -#endif diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h deleted file mode 100644 index 477b693..0000000 --- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM281XX_SYSMAP_H - -#define BSC1_BASE_ADDR 0x3e016000 -#define BSC2_BASE_ADDR 0x3e017000 -#define BSC3_BASE_ADDR 0x3e018000 -#define DWDMA_AHB_BASE_ADDR 0x38100000 -#define ESUB_CLK_BASE_ADDR 0x38000000 -#define ESW_CONTRL_BASE_ADDR 0x38200000 -#define GPIO2_BASE_ADDR 0x35003000 -#define HSOTG_BASE_ADDR 0x3f120000 -#define HSOTG_CTRL_BASE_ADDR 0x3f130000 -#define KONA_MST_CLK_BASE_ADDR 0x3f001000 -#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 -#define PMU_BSC_BASE_ADDR 0x3500d000 -#define PWRMGR_BASE_ADDR 0x35010000 -#define SDIO1_BASE_ADDR 0x3f180000 -#define SDIO2_BASE_ADDR 0x3f190000 -#define SDIO3_BASE_ADDR 0x3f1a0000 -#define SDIO4_BASE_ADDR 0x3f1b0000 -#define SECWD_BASE_ADDR 0x3500c000 -#define SECWD2_BASE_ADDR 0x35002f40 -#define TIMER_BASE_ADDR 0x3e00d000 - -#define HSOTG_DCTL_OFFSET 0x00000804 -#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 - -#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 -#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 -#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 - -#endif diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h deleted file mode 100644 index 9eafe43..0000000 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2017 Broadcom. - */ - -#ifndef __ARCH_CONFIGS_H -#define __ARCH_CONFIGS_H - -#include <asm/iproc-common/configs.h> - -/* uArchitecture specifics */ - -/* Serial Info */ -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_MEM32 - -#define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_CLK_DIV 54 -#define CONFIG_SERIAL_MULTI -#define CONFIG_SYS_NS16550_COM3 0x18023000 - -/* Ethernet */ -#define CONFIG_PHY_BROADCOM -#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/ - -#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h deleted file mode 100644 index 05fa9b9..0000000 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __ARCH_CONFIGS_H -#define __ARCH_CONFIGS_H - -#include <asm/iproc-common/configs.h> - -/* uArchitecture specifics */ - -/* Serial Info */ -/* no padding */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 0x03b9aca0 -#define CONFIG_SYS_NS16550_COM1 0x18000300 - -#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h deleted file mode 100644 index 272b644..0000000 --- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h +++ /dev/null @@ -1,666 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Cirrus Logic EP93xx register definitions. - * - * Copyright (C) 2013 - * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> - * - * Copyright (C) 2009 - * Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 - * Dominic Rath <Dominic.Rath@gmx.de> - * - * Copyright (C) 2004, 2005 - * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> - * - * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is - * - * Copyright (C) 2004 Ray Lehtiniemi - * Copyright (C) 2003 Cirrus Logic, Inc - * Copyright (C) 1999 ARM Limited. - */ - -#define EP93XX_AHB_BASE 0x80000000 -#define EP93XX_APB_BASE 0x80800000 - -/* - * 0x80000000 - 0x8000FFFF: DMA - */ -#define DMA_OFFSET 0x000000 -#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) - -#ifndef __ASSEMBLY__ -struct dma_channel { - uint32_t control; - uint32_t interrupt; - uint32_t ppalloc; - uint32_t status; - uint32_t reserved0; - uint32_t remain; - uint32_t reserved1[2]; - uint32_t maxcnt0; - uint32_t base0; - uint32_t current0; - uint32_t reserved2; - uint32_t maxcnt1; - uint32_t base1; - uint32_t current1; - uint32_t reserved3; -}; - -struct dma_regs { - struct dma_channel m2p_channel_0; - struct dma_channel m2p_channel_1; - struct dma_channel m2p_channel_2; - struct dma_channel m2p_channel_3; - struct dma_channel m2m_channel_0; - struct dma_channel m2m_channel_1; - struct dma_channel reserved0[2]; - struct dma_channel m2p_channel_5; - struct dma_channel m2p_channel_4; - struct dma_channel m2p_channel_7; - struct dma_channel m2p_channel_6; - struct dma_channel m2p_channel_9; - struct dma_channel m2p_channel_8; - uint32_t channel_arbitration; - uint32_t reserved[15]; - uint32_t global_interrupt; -}; -#endif - -/* - * 0x80010000 - 0x8001FFFF: Ethernet MAC - */ -#define MAC_OFFSET 0x010000 -#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) - -#ifndef __ASSEMBLY__ -struct mac_queue { - uint32_t badd; - union { /* deal with half-word aligned registers */ - uint32_t blen; - union { - uint16_t filler; - uint16_t curlen; - }; - }; - uint32_t curadd; -}; - -struct mac_regs { - uint32_t rxctl; - uint32_t txctl; - uint32_t testctl; - uint32_t reserved0; - uint32_t miicmd; - uint32_t miidata; - uint32_t miists; - uint32_t reserved1; - uint32_t selfctl; - uint32_t inten; - uint32_t intstsp; - uint32_t intstsc; - uint32_t reserved2[2]; - uint32_t diagad; - uint32_t diagdata; - uint32_t gt; - uint32_t fct; - uint32_t fcf; - uint32_t afp; - union { - struct { - uint32_t indad; - uint32_t indad_upper; - }; - uint32_t hashtbl; - }; - uint32_t reserved3[2]; - uint32_t giintsts; - uint32_t giintmsk; - uint32_t giintrosts; - uint32_t giintfrc; - uint32_t txcollcnt; - uint32_t rxmissnct; - uint32_t rxruntcnt; - uint32_t reserved4; - uint32_t bmctl; - uint32_t bmsts; - uint32_t rxbca; - uint32_t reserved5; - struct mac_queue rxdq; - uint32_t rxdqenq; - struct mac_queue rxstsq; - uint32_t rxstsqenq; - struct mac_queue txdq; - uint32_t txdqenq; - struct mac_queue txstsq; - uint32_t reserved6; - uint32_t rxbufthrshld; - uint32_t txbufthrshld; - uint32_t rxststhrshld; - uint32_t txststhrshld; - uint32_t rxdthrshld; - uint32_t txdthrshld; - uint32_t maxfrmlen; - uint32_t maxhdrlen; -}; -#endif - -#define SELFCTL_RWP (1 << 7) -#define SELFCTL_GPO0 (1 << 5) -#define SELFCTL_PUWE (1 << 4) -#define SELFCTL_PDWE (1 << 3) -#define SELFCTL_MIIL (1 << 2) -#define SELFCTL_RESET (1 << 0) - -#define INTSTS_RWI (1 << 30) -#define INTSTS_RXMI (1 << 29) -#define INTSTS_RXBI (1 << 28) -#define INTSTS_RXSQI (1 << 27) -#define INTSTS_TXLEI (1 << 26) -#define INTSTS_ECIE (1 << 25) -#define INTSTS_TXUHI (1 << 24) -#define INTSTS_MOI (1 << 18) -#define INTSTS_TXCOI (1 << 17) -#define INTSTS_RXROI (1 << 16) -#define INTSTS_MIII (1 << 12) -#define INTSTS_PHYI (1 << 11) -#define INTSTS_TI (1 << 10) -#define INTSTS_AHBE (1 << 8) -#define INTSTS_OTHER (1 << 4) -#define INTSTS_TXSQ (1 << 3) -#define INTSTS_RXSQ (1 << 2) - -#define BMCTL_MT (1 << 13) -#define BMCTL_TT (1 << 12) -#define BMCTL_UNH (1 << 11) -#define BMCTL_TXCHR (1 << 10) -#define BMCTL_TXDIS (1 << 9) -#define BMCTL_TXEN (1 << 8) -#define BMCTL_EH2 (1 << 6) -#define BMCTL_EH1 (1 << 5) -#define BMCTL_EEOB (1 << 4) -#define BMCTL_RXCHR (1 << 2) -#define BMCTL_RXDIS (1 << 1) -#define BMCTL_RXEN (1 << 0) - -#define BMSTS_TXACT (1 << 7) -#define BMSTS_TP (1 << 4) -#define BMSTS_RXACT (1 << 3) -#define BMSTS_QID_MASK 0x07 -#define BMSTS_QID_RXDATA 0x00 -#define BMSTS_QID_TXDATA 0x01 -#define BMSTS_QID_RXSTS 0x02 -#define BMSTS_QID_TXSTS 0x03 -#define BMSTS_QID_RXDESC 0x04 -#define BMSTS_QID_TXDESC 0x05 - -#define AFP_MASK 0x07 -#define AFP_IAPRIMARY 0x00 -#define AFP_IASECONDARY1 0x01 -#define AFP_IASECONDARY2 0x02 -#define AFP_IASECONDARY3 0x03 -#define AFP_TX 0x06 -#define AFP_HASH 0x07 - -#define RXCTL_PAUSEA (1 << 20) -#define RXCTL_RXFCE1 (1 << 19) -#define RXCTL_RXFCE0 (1 << 18) -#define RXCTL_BCRC (1 << 17) -#define RXCTL_SRXON (1 << 16) -#define RXCTL_RCRCA (1 << 13) -#define RXCTL_RA (1 << 12) -#define RXCTL_PA (1 << 11) -#define RXCTL_BA (1 << 10) -#define RXCTL_MA (1 << 9) -#define RXCTL_IAHA (1 << 8) -#define RXCTL_IA3 (1 << 3) -#define RXCTL_IA2 (1 << 2) -#define RXCTL_IA1 (1 << 1) -#define RXCTL_IA0 (1 << 0) - -#define TXCTL_DEFDIS (1 << 7) -#define TXCTL_MBE (1 << 6) -#define TXCTL_ICRC (1 << 5) -#define TXCTL_TPD (1 << 4) -#define TXCTL_OCOLL (1 << 3) -#define TXCTL_SP (1 << 2) -#define TXCTL_PB (1 << 1) -#define TXCTL_STXON (1 << 0) - -#define MIICMD_REGAD_MASK (0x001F) -#define MIICMD_PHYAD_MASK (0x03E0) -#define MIICMD_OPCODE_MASK (0xC000) -#define MIICMD_PHYAD_8950 (0x0000) -#define MIICMD_OPCODE_READ (0x8000) -#define MIICMD_OPCODE_WRITE (0x4000) - -#define MIISTS_BUSY (1 << 0) - -/* - * 0x80020000 - 0x8002FFFF: USB OHCI - */ -#define USB_OFFSET 0x020000 -#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) - -/* - * 0x80030000 - 0x8003FFFF: Raster engine - */ -#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315)) -#define RASTER_OFFSET 0x030000 -#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) -#endif - -/* - * 0x80040000 - 0x8004FFFF: Graphics accelerator - */ -#if defined(CONFIG_EP9315) -#define GFX_OFFSET 0x040000 -#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) -#endif - -/* - * 0x80050000 - 0x8005FFFF: Reserved - */ - -/* - * 0x80060000 - 0x8006FFFF: SDRAM controller - */ -#define SDRAM_OFFSET 0x060000 -#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) - -#ifndef __ASSEMBLY__ -struct sdram_regs { - uint32_t reserved; - uint32_t glconfig; - uint32_t refrshtimr; - uint32_t bootsts; - uint32_t devcfg0; - uint32_t devcfg1; - uint32_t devcfg2; - uint32_t devcfg3; -}; -#endif - -#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) -#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) -#define SDRAM_DEVCFG_SROMLL (1 << 5) -#define SDRAM_DEVCFG_CASLAT_2 0x00010000 -#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 - -#define SDRAM_OFF_GLCONFIG 0x0004 -#define SDRAM_OFF_REFRSHTIMR 0x0008 - -#define SDRAM_OFF_DEVCFG0 0x0010 -#define SDRAM_OFF_DEVCFG1 0x0014 -#define SDRAM_OFF_DEVCFG2 0x0018 -#define SDRAM_OFF_DEVCFG3 0x001C - -#define SDRAM_DEVCFG0_BASE 0xC0000000 -#define SDRAM_DEVCFG1_BASE 0xD0000000 -#define SDRAM_DEVCFG2_BASE 0xE0000000 -#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000 -#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000 - -#define GLCONFIG_INIT (1 << 0) -#define GLCONFIG_MRS (1 << 1) -#define GLCONFIG_SMEMBUSY (1 << 5) -#define GLCONFIG_LCR (1 << 6) -#define GLCONFIG_REARBEN (1 << 7) -#define GLCONFIG_CLKSHUTDOWN (1 << 30) -#define GLCONFIG_CKE (1 << 31) - -#define EP93XX_SDRAMCTRL 0x80060000 -#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001 -#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002 -#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020 -#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040 -#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080 -#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000 -#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000 - -#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF - -#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002 -#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001 -#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000 -#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003 -#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004 - -#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004 -#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008 -#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010 -#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020 -#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040 -#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000 -#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000 -#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000 -#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000 -#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000 -#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000 -#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000 - -/* - * 0x80070000 - 0x8007FFFF: Reserved - */ - -/* - * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA - */ -#define SMC_OFFSET 0x080000 -#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) - -#ifndef __ASSEMBLY__ -struct smc_regs { - uint32_t bcr0; - uint32_t bcr1; - uint32_t bcr2; - uint32_t bcr3; - uint32_t reserved0[2]; - uint32_t bcr6; - uint32_t bcr7; -#if defined(CONFIG_EP9315) - uint32_t pcattribute; - uint32_t pccommon; - uint32_t pcio; - uint32_t reserved1[5]; - uint32_t pcmciactrl; -#endif -}; -#endif - -#define EP93XX_OFF_SMCBCR0 0x00 -#define EP93XX_OFF_SMCBCR1 0x04 -#define EP93XX_OFF_SMCBCR2 0x08 -#define EP93XX_OFF_SMCBCR3 0x0C -#define EP93XX_OFF_SMCBCR6 0x18 -#define EP93XX_OFF_SMCBCR7 0x1C - -#define SMC_BCR_IDCY_SHIFT 0 -#define SMC_BCR_WST1_SHIFT 5 -#define SMC_BCR_BLE (1 << 10) -#define SMC_BCR_WST2_SHIFT 11 -#define SMC_BCR_MW_SHIFT 28 - -/* - * 0x80090000 - 0x8009FFFF: Boot ROM - */ - -/* - * 0x800A0000 - 0x800AFFFF: IDE interface - */ - -/* - * 0x800B0000 - 0x800BFFFF: VIC1 - */ - -/* - * 0x800C0000 - 0x800CFFFF: VIC2 - */ - -/* - * 0x800D0000 - 0x800FFFFF: Reserved - */ - -/* - * 0x80800000 - 0x8080FFFF: Reserved - */ - -/* - * 0x80810000 - 0x8081FFFF: Timers - */ -#define TIMER_OFFSET 0x010000 -#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) - -#ifndef __ASSEMBLY__ -struct timer { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t clear; -}; - -struct timer4 { - uint32_t value_low; - uint32_t value_high; -}; - -struct timer_regs { - struct timer timer1; - uint32_t reserved0[4]; - struct timer timer2; - uint32_t reserved1[12]; - struct timer4 timer4; - uint32_t reserved2[6]; - struct timer timer3; -}; -#endif - -/* - * 0x80820000 - 0x8082FFFF: I2S - */ -#define I2S_OFFSET 0x020000 -#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) - -/* - * 0x80830000 - 0x8083FFFF: Security - */ -#define SECURITY_OFFSET 0x030000 -#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) - -#define EXTENSIONID (SECURITY_BASE + 0x2714) - -/* - * 0x80840000 - 0x8084FFFF: GPIO - */ -#define GPIO_OFFSET 0x040000 -#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) - -#ifndef __ASSEMBLY__ -struct gpio_int { - uint32_t inttype1; - uint32_t inttype2; - uint32_t eoi; - uint32_t inten; - uint32_t intsts; - uint32_t rawintsts; - uint32_t db; -}; - -struct gpio_regs { - uint32_t padr; - uint32_t pbdr; - uint32_t pcdr; - uint32_t pddr; - uint32_t paddr; - uint32_t pbddr; - uint32_t pcddr; - uint32_t pdddr; - uint32_t pedr; - uint32_t peddr; - uint32_t reserved0[2]; - uint32_t pfdr; - uint32_t pfddr; - uint32_t pgdr; - uint32_t pgddr; - uint32_t phdr; - uint32_t phddr; - uint32_t reserved1; - uint32_t finttype1; - uint32_t finttype2; - uint32_t reserved2; - struct gpio_int pfint; - uint32_t reserved3[10]; - struct gpio_int paint; - struct gpio_int pbint; - uint32_t eedrive; -}; -#endif - -#define EP93XX_LED_DATA 0x80840020 -#define EP93XX_LED_GREEN_ON 0x0001 -#define EP93XX_LED_RED_ON 0x0002 - -#define EP93XX_LED_DDR 0x80840024 -#define EP93XX_LED_GREEN_ENABLE 0x0001 -#define EP93XX_LED_RED_ENABLE 0x00020000 - -/* - * 0x80850000 - 0x8087FFFF: Reserved - */ - -/* - * 0x80880000 - 0x8088FFFF: AAC - */ -#define AAC_OFFSET 0x080000 -#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) - -/* - * 0x80890000 - 0x8089FFFF: Reserved - */ - -/* - * 0x808A0000 - 0x808AFFFF: SPI - */ -#define SPI_OFFSET 0x0A0000 -#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) - -/* - * 0x808B0000 - 0x808BFFFF: IrDA - */ -#define IRDA_OFFSET 0x0B0000 -#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) - -/* - * 0x808C0000 - 0x808CFFFF: UART1 - */ -#define UART1_OFFSET 0x0C0000 -#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) - -/* - * 0x808D0000 - 0x808DFFFF: UART2 - */ -#define UART2_OFFSET 0x0D0000 -#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) - -/* - * 0x808E0000 - 0x808EFFFF: UART3 - */ -#define UART3_OFFSET 0x0E0000 -#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) - -/* - * 0x808F0000 - 0x808FFFFF: Key Matrix - */ -#define KEY_OFFSET 0x0F0000 -#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) - -/* - * 0x80900000 - 0x8090FFFF: Touchscreen - */ -#define TOUCH_OFFSET 0x900000 -#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) - -/* - * 0x80910000 - 0x8091FFFF: Pulse Width Modulation - */ -#define PWM_OFFSET 0x910000 -#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) - -/* - * 0x80920000 - 0x8092FFFF: Real time clock - */ -#define RTC_OFFSET 0x920000 -#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) - -/* - * 0x80930000 - 0x8093FFFF: Syscon - */ -#define SYSCON_OFFSET 0x930000 -#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) - -/* Security */ -#define SECURITY_EXTENSIONID 0x80832714 - -#ifndef __ASSEMBLY__ -struct syscon_regs { - uint32_t pwrsts; - uint32_t pwrcnt; - uint32_t halt; - uint32_t stby; - uint32_t reserved0[2]; - uint32_t teoi; - uint32_t stfclr; - uint32_t clkset1; - uint32_t clkset2; - uint32_t reserved1[6]; - uint32_t scratch0; - uint32_t scratch1; - uint32_t reserved2[2]; - uint32_t apbwait; - uint32_t bustmstrarb; - uint32_t bootmodeclr; - uint32_t reserved3[9]; - uint32_t devicecfg; - uint32_t vidclkdiv; - uint32_t mirclkdiv; - uint32_t i2sclkdiv; - uint32_t keytchclkdiv; - uint32_t chipid; - uint32_t reserved4; - uint32_t syscfg; - uint32_t reserved5[8]; - uint32_t sysswlock; -}; -#else -#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) -#endif - -#define SYSCON_OFF_CLKSET1 0x0020 -#define SYSCON_OFF_SYSCFG 0x009c - -#define SYSCON_PWRCNT_UART_BAUD (1 << 29) -#define SYSCON_PWRCNT_USH_EN (1 << 28) - -#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 -#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 -#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11 -#define SYSCON_CLKSET_PLL_PS_SHIFT 16 -#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 -#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 -#define SYSCON_CLKSET1_NBYP1 (1 << 23) -#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 - -#define SYSCON_CLKSET2_PLL2_EN (1 << 18) -#define SYSCON_CLKSET2_NBYP2 (1 << 19) -#define SYSCON_CLKSET2_USB_DIV_SHIFT 28 - -#define SYSCON_CHIPID_REV_MASK 0xF0000000 -#define SYSCON_DEVICECFG_SWRST (1 << 31) - -#define SYSCON_SYSCFG_LASDO 0x00000020 - -/* - * 0x80930000 - 0x8093FFFF: Watchdog Timer - */ -#define WATCHDOG_OFFSET 0x940000 -#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) - -/* - * 0x80950000 - 0x9000FFFF: Reserved - */ - -/* - * During low_level init we store memory layout in memory at specific location - */ -#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000 -#define UBOOT_MEMORYCNF_BANK_MASK 0x2004 -#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h deleted file mode 100644 index b37a08d..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019 NXP Semiconductors - * - */ - -#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ -#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ - -#include <common.h> - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_I2C_CLK, - MXC_DSPI_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -ulong get_ddr_freq(ulong); -uint get_svr(void); - -#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h deleted file mode 100644 index a83c70e..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ /dev/null @@ -1,404 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016-2018 NXP - * Copyright 2015, Freescale Semiconductor - */ - -#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ -#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ - -#include <linux/kconfig.h> -#include <fsl_ddrc_version.h> - -#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 - -/* - * Reserve secure memory - * To be aligned with MMU block size - */ -#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ -#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ - -#ifdef CONFIG_ARCH_LS2080A -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } -#define SRDS_MAX_LANES 8 -#define CONFIG_SYS_PAGE_SIZE 0x10000 -#ifndef L1_CACHE_BYTES -#define L1_CACHE_SHIFT 6 -#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) -#endif - -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ -#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ - -/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE - -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x06000000 -#define GICR_BASE 0x06100000 - -/* SMMU Defintions */ -#define SMMU_BASE 0x05000000 /* GR0 Base */ - -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - -/* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE - -/* Cache Coherent Interconnect */ -#define CCI_MN_BASE 0x04000000 -#define CCI_MN_RNF_NODEID_LIST 0x180 -#define CCI_MN_DVM_DOMAIN_CTL 0x200 -#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 - -#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) -#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) -#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ -#define CCN_HN_F_SAM_NODEID_MASK 0x7f -#define CCN_HN_F_SAM_NODEID_DDR0 0x4 -#define CCN_HN_F_SAM_NODEID_DDR1 0xe - -#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) -#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) -#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) -#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) -#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) -#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) - -#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) -#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) -#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) - -#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) - -/* TZ Protection Controller Definitions */ -#define TZPC_BASE 0x02200000 -#define TZPCR0SIZE_BASE (TZPC_BASE) -#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) -#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) -#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) -#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) -#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) -#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) -#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) -#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) - -#define DCSR_CGACRE5 0x700070914ULL -#define EPU_EPCMPR5 0x700060914ULL -#define EPU_EPCCR5 0x700060814ULL -#define EPU_EPSMCR5 0x700060228ULL -#define EPU_EPECR5 0x700060314ULL -#define EPU_EPCTR5 0x700060a14ULL -#define EPU_EPGCR 0x700060000ULL - -#define CONFIG_SYS_FSL_ERRATUM_A008751 - -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - -#elif defined(CONFIG_ARCH_LS1088A) -#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_GICV3 -#define CONFIG_SYS_PAGE_SIZE 0x10000 - -#define SRDS_MAX_LANES 4 - -/* TZ Protection Controller Definitions */ -#define TZPC_BASE 0x02200000 -#define TZPCR0SIZE_BASE (TZPC_BASE) -#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) -#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) -#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) -#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) -#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) -#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) -#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) -#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x06000000 -#define GICR_BASE 0x06100000 - -/* SMMU Defintions */ -#define SMMU_BASE 0x05000000 /* GR0 Base */ - -/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE - -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - -/* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ -#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ - -/* LX2160A Soc Support */ -#elif defined(CONFIG_ARCH_LX2160A) -#define TZPC_BASE 0x02200000 -#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#if !defined(CONFIG_DM_I2C) -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_EARLY_INIT -#endif -#define SRDS_MAX_LANES 8 -#ifndef L1_CACHE_BYTES -#define L1_CACHE_SHIFT 6 -#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) -#endif -#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 - -#define CONFIG_SYS_PAGE_SIZE 0x10000 - -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ -#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ - -/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE - -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x06000000 -#define GICR_BASE 0x06200000 - -/* SMMU Definitions */ -#define SMMU_BASE 0x05000000 /* GR0 Base */ - -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - -/* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE - -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - -#elif defined(CONFIG_ARCH_LS1028A) -#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_GICV3 -#define CONFIG_FSL_TZPC_BP147 -#define CONFIG_FSL_TZASC_400 - -/* TZ Protection Controller Definitions */ -#define TZPC_BASE 0x02200000 -#define TZPCR0SIZE_BASE (TZPC_BASE) -#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) -#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) -#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) -#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) -#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) -#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) -#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) -#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) - -#define SRDS_MAX_LANES 4 - -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ -#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x06000000 -#define GICR_BASE 0x06040000 - -/* SMMU Definitions */ -#define SMMU_BASE 0x05000000 /* GR0 Base */ - -/* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE - -#define CONFIG_SYS_FSL_CCSR_GUR_LE -#define CONFIG_SYS_FSL_CCSR_SCFG_LE -#define CONFIG_SYS_FSL_ESDHC_LE -#define CONFIG_SYS_FSL_PEX_LUT_LE - -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - -/* SFP */ -#define CONFIG_SYS_FSL_SFP_VER_3_4 -#define CONFIG_SYS_FSL_SFP_LE -#define CONFIG_SYS_FSL_SRK_LE - -/* SEC */ -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - -/* Security Monitor */ -#define CONFIG_SYS_FSL_SEC_MON_LE - -/* Secure Boot */ -#define CONFIG_ESBC_HDR_LS - -/* DCFG - GUR */ -#define CONFIG_SYS_FSL_CCSR_GUR_LE - -#elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ -#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ - -#define DCSR_DCFG_SBEESR2 0x20140534 -#define DCSR_DCFG_MBEESR2 0x20140544 - -#define CONFIG_SYS_FSL_CCSR_SCFG_BE -#define CONFIG_SYS_FSL_ESDHC_BE -#define CONFIG_SYS_FSL_WDOG_BE -#define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_QSPI_BE -#define CONFIG_SYS_FSL_CCSR_GUR_BE -#define CONFIG_SYS_FSL_PEX_LUT_BE - -/* SoC related */ -#ifdef CONFIG_ARCH_LS1043A -#define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FSL_QMAN_V3 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE - -#define QE_MURAM_SIZE 0x6000UL -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 - -#define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION - -/* SMMU Defintions */ -#define SMMU_BASE 0x09000000 - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x01401000 -#define GICC_BASE 0x01402000 -#define GICH_BASE 0x01404000 -#define GICV_BASE 0x01406000 -#define GICD_SIZE 0x1000 -#define GICC_SIZE 0x2000 -#define GICH_SIZE 0x2000 -#define GICV_SIZE 0x2000 -#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN -#define GICD_BASE_64K 0x01410000 -#define GICC_BASE_64K 0x01420000 -#define GICH_BASE_64K 0x01440000 -#define GICV_BASE_64K 0x01460000 -#define GICD_SIZE_64K 0x10000 -#define GICC_SIZE_64K 0x20000 -#define GICH_SIZE_64K 0x20000 -#define GICV_SIZE_64K 0x20000 -#endif - -#define DCFG_CCSR_SVR 0x1ee00a4 -#define REV1_0 0x10 -#define REV1_1 0x11 -#define GIC_ADDR_BIT 31 -#define SCFG_GIC400_ALIGN 0x1570188 - -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - -#elif defined(CONFIG_ARCH_LS1012A) -#define GICD_BASE 0x01401000 -#define GICC_BASE 0x01402000 -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE - -#elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FSL_QMAN_V3 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE - -#define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION - -/* SMMU Defintions */ -#define SMMU_BASE 0x09000000 - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x01410000 -#define GICC_BASE 0x01420000 - -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#else -#error SoC not defined -#endif -#endif - -#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h deleted file mode 100644 index 7759acd..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017-2018 NXP - * Copyright 2014-2015, Freescale Semiconductor - */ - -#ifndef _FSL_LAYERSCAPE_CPU_H -#define _FSL_LAYERSCAPE_CPU_H - -#ifdef CONFIG_FSL_LSCH3 -#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 -#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 -#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 -#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 -#ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 -#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 -#endif -#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 -#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 -#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 -#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 -#ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 -#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 -#endif -#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 -#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 -#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 -#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 -#define CONFIG_SYS_FSL_NI_BASE 0x810000000 -#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 -#ifdef CONFIG_ARCH_LS2080A -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 -#else -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 -#endif -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 -#define SYS_PCIE5_PHYS_SIZE 0x800000000 -#define SYS_PCIE6_PHYS_SIZE 0x800000000 -#endif -#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 -#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 -#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 -#ifndef CONFIG_ARCH_LX2160A -#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 -#else -#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 -#endif -#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 -#ifdef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 -#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 -#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 -#else -#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 -#endif -#elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 -#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 -#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 -#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 -#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 -#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 -#define CONFIG_SYS_FSL_IFC_BASE 0x60000000 -#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 -#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 -#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 -#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 -#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 -#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ -#endif - -int fsl_qoriq_core_to_cluster(unsigned int core); -u32 cpu_mask(void); - -#endif /* _FSL_LAYERSCAPE_CPU_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h deleted file mode 100644 index ebc999c..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ -#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ - -void fdt_fixup_board_enet(void *fdt); -#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h deleted file mode 100644 index 37e2fe4..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ /dev/null @@ -1,193 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef _FSL_ICID_H_ -#define _FSL_ICID_H_ - -#include <asm/types.h> -#include <fsl_qbman.h> -#include <fsl_sec.h> -#include <asm/armv8/sec_firmware.h> - -struct icid_id_table { - const char *compat; - u32 id; - u32 reg; - phys_addr_t compat_addr; - phys_addr_t reg_addr; - bool le; -}; - -struct fman_icid_id_table { - u32 port_id; - u32 icid; -}; - -u32 get_ppid_icid(int ppid_tbl_idx, int ppid); -int fdt_get_smmu_phandle(void *blob); -int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); -void set_icids(void); -void fdt_fixup_icid(void *blob); - -#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ - { .compat = name, \ - .id = idA, \ - .reg = regA, \ - .compat_addr = compataddr, \ - .reg_addr = addr, \ - .le = _le \ - } - -#ifdef CONFIG_SYS_FSL_SEC_LE -#define SEC_IS_LE true -#elif defined(CONFIG_SYS_FSL_SEC_BE) -#define SEC_IS_LE false -#endif - -#ifdef CONFIG_FSL_LSCH2 - -#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE -#define SCFG_IS_LE true -#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) -#define SCFG_IS_LE false -#endif - -#define QDMA_IS_LE false - -#define SET_SCFG_ICID(compat, streamid, name, compataddr) \ - SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ - offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ - compataddr, SCFG_IS_LE) - -#define SET_USB_ICID(usb_num, compat, streamid) \ - SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) - -#define SET_SATA_ICID(compat, streamid) \ - SET_SCFG_ICID(compat, streamid, sata_icid,\ - AHCI_BASE_ADDR) - -#define SET_SDHC_ICID(streamid) \ - SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ - CONFIG_SYS_FSL_ESDHC_ADDR) - -#define SET_EDMA_ICID(streamid) \ - SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ - EDMA_BASE_ADDR) - -#define SET_ETR_ICID(streamid) \ - SET_SCFG_ICID(NULL, streamid, etr_icid, 0) - -#define SET_DEBUG_ICID(streamid) \ - SET_SCFG_ICID(NULL, streamid, debug_icid, 0) - -#define SET_QE_ICID(streamid) \ - SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\ - QE_BASE_ADDR) - -#define SET_QMAN_ICID(streamid) \ - SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ - offsetof(struct ccsr_qman, liodnr) + \ - CONFIG_SYS_FSL_QMAN_ADDR, \ - CONFIG_SYS_FSL_QMAN_ADDR, false) - -#define SET_BMAN_ICID(streamid) \ - SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ - offsetof(struct ccsr_bman, liodnr) + \ - CONFIG_SYS_FSL_BMAN_ADDR, \ - CONFIG_SYS_FSL_BMAN_ADDR, false) - -#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ - { .port_id = (_port_id), .icid = (streamid) } - -#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid)) - -#define SET_SEC_QI_ICID(streamid) \ - SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ - 0, offsetof(ccsr_sec_t, qilcr_ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, \ - CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE) - -extern struct fman_icid_id_table fman_icid_tbl[]; -extern int fman_icid_tbl_sz; - -#else /* CONFIG_FSL_LSCH2 */ - -#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE -#define GUR_IS_LE true -#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) -#define GUR_IS_LE false -#endif - -#define QDMA_IS_LE true - -#define SET_GUR_ICID(compat, streamid, name, compataddr) \ - SET_ICID_ENTRY(compat, streamid, streamid, \ - offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \ - compataddr, GUR_IS_LE) - -#define SET_USB_ICID(usb_num, compat, streamid) \ - SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) - -#define SET_SATA_ICID(sata_num, compat, streamid) \ - SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ - AHCI_BASE_ADDR##sata_num) - -#define SET_SDHC_ICID(sdhc_num, streamid) \ - SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\ - FSL_ESDHC##sdhc_num##_BASE_ADDR) - -#define SET_EDMA_ICID(streamid) \ - SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\ - EDMA_BASE_ADDR) - -#define SET_GPU_ICID(compat, streamid) \ - SET_GUR_ICID(compat, streamid, misc1_amqr,\ - GPU_BASE_ADDR) - -#define SET_DISPLAY_ICID(streamid) \ - SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\ - DISPLAY_BASE_ADDR) - -#define SEC_ICID_REG_VAL(streamid) (streamid) - -#endif /* CONFIG_FSL_LSCH2 */ - -#define SET_QDMA_ICID(compat, streamid) \ - SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ - QDMA_BASE_ADDR, QDMA_IS_LE), \ - SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ - QDMA_BASE_ADDR, QDMA_IS_LE) - -#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ - SET_ICID_ENTRY( \ - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ - (FSL_SEC_JR##jr_num##_OFFSET == \ - SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ - ? NULL \ - : "fsl,sec-v4.0-job-ring"), \ - streamid, \ - SEC_ICID_REG_VAL(streamid), \ - offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, \ - FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE) - -#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ - SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ - offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) - -#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ - SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ - offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) - -extern struct icid_id_table icid_tbl[]; -extern int icid_tbl_sz; - -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h deleted file mode 100644 index 1577e93..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef _FSL_PORTALS_H_ -#define _FSL_PORTALS_H_ - -struct qportal_info { - u16 dicid; /* DQRR ICID */ - u16 ficid; /* frame data ICID */ - u16 icid; - u8 sdest; -}; - -#define SET_QP_INFO(streamid, dest) \ - { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \ - .sdest = (dest) } - -extern struct qportal_info qp_info[]; -void fdt_portal(void *blob, const char *compat, const char *container, - u64 addr, u32 size); - -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h deleted file mode 100644 index 8f43651..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ /dev/null @@ -1,218 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_SERDES_H__ -#define __FSL_SERDES_H__ - -#include <config.h> - -#ifdef CONFIG_FSL_LSCH3 -enum srds_prtcl { - /* - * Nobody will check whether the device 'NONE' has been configured, - * So use it to indicate if the serdes_prtcl_map has been initialized. - */ - NONE = 0, - PCIE1, - PCIE2, - PCIE3, - PCIE4, - PCIE5, - PCIE6, - SATA1, - SATA2, - SATA3, - SATA4, - XAUI1, - XAUI2, - XFI1, - XFI2, - XFI3, - XFI4, - XFI5, - XFI6, - XFI7, - XFI8, - XFI9, - XFI10, - XFI11, - XFI12, - XFI13, - XFI14, - SGMII1, - SGMII2, - SGMII3, - SGMII4, - SGMII5, - SGMII6, - SGMII7, - SGMII8, - SGMII9, - SGMII10, - SGMII11, - SGMII12, - SGMII13, - SGMII14, - SGMII15, - SGMII16, - SGMII17, - SGMII18, - QSGMII_A, - QSGMII_B, - QSGMII_C, - QSGMII_D, - SGMII_T1, - SGMII_T2, - SGMII_T3, - SGMII_T4, - SXGMII1, - SXGMII2, - SXGMII3, - SXGMII4, - QXGMII1, - QXGMII2, - QXGMII3, - QXGMII4, - _25GE1, - _25GE2, - _25GE3, - _25GE4, - _25GE5, - _25GE6, - _25GE7, - _25GE8, - _25GE9, - _25GE10, - _40GE1, - _40GE2, - _50GE1, - _50GE2, - _100GE1, - _100GE2, - SERDES_PRCTL_COUNT -}; - -enum srds { - FSL_SRDS_1 = 0, - FSL_SRDS_2 = 1, - NXP_SRDS_3 = 2, -}; -#elif defined(CONFIG_FSL_LSCH2) -enum srds_prtcl { - /* - * Nobody will check whether the device 'NONE' has been configured, - * So use it to indicate if the serdes_prtcl_map has been initialized. - */ - NONE = 0, - PCIE1, - PCIE2, - PCIE3, - PCIE4, - SATA1, - SATA2, - SRIO1, - SRIO2, - SGMII_FM1_DTSEC1, - SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, - SGMII_FM1_DTSEC5, - SGMII_FM1_DTSEC6, - SGMII_FM1_DTSEC9, - SGMII_FM1_DTSEC10, - SGMII_FM2_DTSEC1, - SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, - SGMII_FM2_DTSEC4, - SGMII_FM2_DTSEC5, - SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC9, - SGMII_FM2_DTSEC10, - SGMII_TSEC1, - SGMII_TSEC2, - SGMII_TSEC3, - SGMII_TSEC4, - XAUI_FM1, - XAUI_FM2, - AURORA, - CPRI1, - CPRI2, - CPRI3, - CPRI4, - CPRI5, - CPRI6, - CPRI7, - CPRI8, - XAUI_FM1_MAC9, - XAUI_FM1_MAC10, - XAUI_FM2_MAC9, - XAUI_FM2_MAC10, - HIGIG_FM1_MAC9, - HIGIG_FM1_MAC10, - HIGIG_FM2_MAC9, - HIGIG_FM2_MAC10, - QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */ - QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ - QSGMII_FM2_A, - QSGMII_FM2_B, - XFI_FM1_MAC1, - XFI_FM1_MAC2, - XFI_FM1_MAC9, - XFI_FM1_MAC10, - XFI_FM2_MAC9, - XFI_FM2_MAC10, - INTERLAKEN, - QSGMII_SW1_A, /* Indicates ports on L2 Switch */ - QSGMII_SW1_B, - SGMII_2500_FM1_DTSEC1, - SGMII_2500_FM1_DTSEC2, - SGMII_2500_FM1_DTSEC3, - SGMII_2500_FM1_DTSEC4, - SGMII_2500_FM1_DTSEC5, - SGMII_2500_FM1_DTSEC6, - SGMII_2500_FM1_DTSEC9, - SGMII_2500_FM1_DTSEC10, - SGMII_2500_FM2_DTSEC1, - SGMII_2500_FM2_DTSEC2, - SGMII_2500_FM2_DTSEC3, - SGMII_2500_FM2_DTSEC4, - SGMII_2500_FM2_DTSEC5, - SGMII_2500_FM2_DTSEC6, - SGMII_2500_FM2_DTSEC9, - SGMII_2500_FM2_DTSEC10, - TX_CLK, - SERDES_PRCTL_COUNT -}; - -enum srds { - FSL_SRDS_1 = 0, - FSL_SRDS_2 = 1, -}; - -#endif - -int is_serdes_configured(enum srds_prtcl device); -void fsl_serdes_init(void); -int serdes_get_first_lane(u32 sd, enum srds_prtcl device); -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); -int is_serdes_prtcl_valid(int serdes, u32 prtcl); -int serdes_get_number(int serdes, int cfg); -void fsl_rgmii_init(void); - -#ifdef CONFIG_FSL_LSCH2 -const char *serdes_clock_to_string(u32 clock); -int get_serdes_protocol(void); -#endif -#ifdef CONFIG_SYS_HAS_SERDES -/* Get the volt of SVDD in unit mV */ -int get_serdes_volt(void); -/* Set the volt of SVDD in unit mV */ -int set_serdes_volt(int svdd); -/* The target volt of SVDD in unit mV */ -int setup_serdes_volt(u32 svdd); -#endif - -#endif /* __FSL_SERDES_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h deleted file mode 100644 index 862ec2e..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ /dev/null @@ -1,709 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_FSL_LSCH2_IMMAP_H__ -#define __ARCH_FSL_LSCH2_IMMAP_H__ - -#include <fsl_immap.h> - -#define CONFIG_SYS_IMMR 0x01000000 -#define CONFIG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) -#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) - -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) -#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) -#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) -#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) -#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) -#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) -#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) -#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) -#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) -#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) - -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 -#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ - CONFIG_SYS_BMAN_MEM_BASE) -#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 - -#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 - -#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) -#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) -#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) -#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) - -#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) - -#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) -#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) - -#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) -#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) -#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) -#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) - -#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) - -#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) - -#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) - -#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) - -#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) -#define QMAN_CQSIDR_REG 0x20a80 - -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL -/* LUT registers */ -#ifdef CONFIG_ARCH_LS1012A -#define PCIE_LUT_BASE 0xC0000 -#else -#define PCIE_LUT_BASE 0x10000 -#endif -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC - -/* TZ Address Space Controller Definitions */ -#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ -#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ -#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ -#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ -#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) -#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) -#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) -#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) -#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) -#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) -#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) -#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) -#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) - -#define TP_ITYP_AV 0x00000001 /* Initiator available */ -#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ -#define TP_ITYP_TYPE_ARM 0x0 -#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ -#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ -#define TY_ITYP_VER_A7 0x1 -#define TY_ITYP_VER_A53 0x2 -#define TY_ITYP_VER_A57 0x3 -#define TY_ITYP_VER_A72 0x4 - -#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ -#define TP_INIT_PER_CLUSTER 4 - -/* - * Define default values for some CCSR macros to make header files cleaner* - * - * To completely disable CCSR relocation in a board header file, define - * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. - */ - -#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ -CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." -#endif - -#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 -#endif - -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR 0x01000000 -#endif - -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 -#endif - -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 -#endif - -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) - -struct sys_info { - unsigned long freq_processor[CONFIG_MAX_CPUS]; - /* frequency of platform PLL */ - unsigned long freq_systembus; - unsigned long freq_ddrbus; - unsigned long freq_localbus; - unsigned long freq_cga_m2; -#ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; -#endif - unsigned long freq_qman; -}; - -#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 -#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 -#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 -#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 -#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 -#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 -#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 - -#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 -#define CONFIG_SYS_FSL_FM1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) -#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) - -#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull -#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull -#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET -#define FSL_SEC_JR1_OFFSET 0x720000ull -#define FSL_SEC_JR2_OFFSET 0x730000ull -#define FSL_SEC_JR3_OFFSET 0x740000ull -#define CONFIG_SYS_FSL_SEC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) -#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) -#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) -#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) -#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) - -/* Device Configuration and Pin Control */ -#define DCFG_DCSR_PORCR1 0x0 -#define DCFG_DCSR_ECCCR2 0x524 -#define DISABLE_PFE_ECC BIT(13) - -struct ccsr_gur { - u32 porsr1; /* POR status 1 */ -#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 - u32 porsr2; /* POR status 2 */ - u8 res_008[0x20-0x8]; - u32 gpporcr1; /* General-purpose POR configuration */ - u32 gpporcr2; -#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 -#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F -#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 -#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F - u32 dcfg_fusesr; /* Fuse status register */ - u8 res_02c[0x70-0x2c]; - u32 devdisr; /* Device disable control */ -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 -#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 -#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 -#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 -#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 -#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 - u32 devdisr2; /* Device disable control 2 */ - u32 devdisr3; /* Device disable control 3 */ - u32 devdisr4; /* Device disable control 4 */ - u32 devdisr5; /* Device disable control 5 */ - u32 devdisr6; /* Device disable control 6 */ - u32 devdisr7; /* Device disable control 7 */ - u8 res_08c[0x94-0x8c]; - u32 coredisru; /* uppper portion for support of 64 cores */ - u32 coredisrl; /* lower portion for support of 64 cores */ - u8 res_09c[0xa0-0x9c]; - u32 pvr; /* Processor version */ - u32 svr; /* System version */ - u32 mvr; /* Manufacturing version */ - u8 res_0ac[0xb0-0xac]; - u32 rstcr; /* Reset control */ - u32 rstrqpblsr; /* Reset request preboot loader status */ - u8 res_0b8[0xc0-0xb8]; - u32 rstrqmr1; /* Reset request mask */ - u8 res_0c4[0xc8-0xc4]; - u32 rstrqsr1; /* Reset request status */ - u8 res_0cc[0xd4-0xcc]; - u32 rstrqwdtmrl; /* Reset request WDT mask */ - u8 res_0d8[0xdc-0xd8]; - u32 rstrqwdtsrl; /* Reset request WDT status */ - u8 res_0e0[0xe4-0xe0]; - u32 brrl; /* Boot release */ - u8 res_0e8[0x100-0xe8]; - u32 rcwsr[16]; /* Reset control word status */ -#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 -#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 -#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 -#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 -#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff -#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 -#define RCW_SB_EN_REG_INDEX 7 -#define RCW_SB_EN_MASK 0x00200000 - - u8 res_140[0x200-0x140]; - u32 scratchrw[4]; /* Scratch Read/Write */ - u8 res_210[0x300-0x210]; - u32 scratchw1r[4]; /* Scratch Read (Write once) */ - u8 res_310[0x400-0x310]; - u32 crstsr[12]; - u8 res_430[0x500-0x430]; - - /* PCI Express n Logical I/O Device Number register */ - u32 dcfg_ccsr_pex1liodnr; - u32 dcfg_ccsr_pex2liodnr; - u32 dcfg_ccsr_pex3liodnr; - u32 dcfg_ccsr_pex4liodnr; - /* RIO n Logical I/O Device Number register */ - u32 dcfg_ccsr_rio1liodnr; - u32 dcfg_ccsr_rio2liodnr; - u32 dcfg_ccsr_rio3liodnr; - u32 dcfg_ccsr_rio4liodnr; - /* USB Logical I/O Device Number register */ - u32 dcfg_ccsr_usb1liodnr; - u32 dcfg_ccsr_usb2liodnr; - u32 dcfg_ccsr_usb3liodnr; - u32 dcfg_ccsr_usb4liodnr; - /* SD/MMC Logical I/O Device Number register */ - u32 dcfg_ccsr_sdmmc1liodnr; - u32 dcfg_ccsr_sdmmc2liodnr; - u32 dcfg_ccsr_sdmmc3liodnr; - u32 dcfg_ccsr_sdmmc4liodnr; - /* RIO Message Unit Logical I/O Device Number register */ - u32 dcfg_ccsr_riomaintliodnr; - - u8 res_544[0x550-0x544]; - u32 sataliodnr[4]; - u8 res_560[0x570-0x560]; - - u32 dcfg_ccsr_misc1liodnr; - u32 dcfg_ccsr_misc2liodnr; - u32 dcfg_ccsr_misc3liodnr; - u32 dcfg_ccsr_misc4liodnr; - u32 dcfg_ccsr_dma1liodnr; - u32 dcfg_ccsr_dma2liodnr; - u32 dcfg_ccsr_dma3liodnr; - u32 dcfg_ccsr_dma4liodnr; - u32 dcfg_ccsr_spare1liodnr; - u32 dcfg_ccsr_spare2liodnr; - u32 dcfg_ccsr_spare3liodnr; - u32 dcfg_ccsr_spare4liodnr; - u8 res_5a0[0x600-0x5a0]; - u32 dcfg_ccsr_pblsr; - - u32 pamubypenr; - u32 dmacr1; - - u8 res_60c[0x610-0x60c]; - u32 dcfg_ccsr_gensr1; - u32 dcfg_ccsr_gensr2; - u32 dcfg_ccsr_gensr3; - u32 dcfg_ccsr_gensr4; - u32 dcfg_ccsr_gencr1; - u32 dcfg_ccsr_gencr2; - u32 dcfg_ccsr_gencr3; - u32 dcfg_ccsr_gencr4; - u32 dcfg_ccsr_gencr5; - u32 dcfg_ccsr_gencr6; - u32 dcfg_ccsr_gencr7; - u8 res_63c[0x658-0x63c]; - u32 dcfg_ccsr_cgensr1; - u32 dcfg_ccsr_cgensr0; - u8 res_660[0x678-0x660]; - u32 dcfg_ccsr_cgencr1; - - u32 dcfg_ccsr_cgencr0; - u8 res_680[0x700-0x680]; - u32 dcfg_ccsr_sriopstecr; - u32 dcfg_ccsr_dcsrcr; - - u8 res_708[0x740-0x708]; /* add more registers when needed */ - u32 tp_ityp[64]; /* Topology Initiator Type Register */ - struct { - u32 upper; - u32 lower; - } tp_cluster[16]; - u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ - u32 dcfg_ccsr_qmbm_warmrst; - u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ - u32 dcfg_ccsr_reserved0; - u32 dcfg_ccsr_reserved1; -}; - -#define SCFG_QSPI_CLKSEL 0x40100000 -#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 -#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 -#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 -#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 -#define SCFG_USBPWRFAULT_SHARED 0x00000001 -#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 -#define SCFG_USBPWRFAULT_USB3_SHIFT 4 -#define SCFG_USBPWRFAULT_USB2_SHIFT 2 -#define SCFG_USBPWRFAULT_USB1_SHIFT 0 - -#define SCFG_BASE 0x01570000 -#define SCFG_USB3PRM1CR_USB1 0x070 -#define SCFG_USB3PRM2CR_USB1 0x074 -#define SCFG_USB3PRM1CR_USB2 0x07C -#define SCFG_USB3PRM2CR_USB2 0x080 -#define SCFG_USB3PRM1CR_USB3 0x088 -#define SCFG_USB3PRM2CR_USB3 0x08c -#define SCFG_USB_TXVREFTUNE 0x9 -#define SCFG_USB_SQRXTUNE_MASK 0x7 -#define SCFG_USB_PCSTXSWINGFULL 0x47 -#define SCFG_USB_PHY1 0x084F0000 -#define SCFG_USB_PHY2 0x08500000 -#define SCFG_USB_PHY3 0x08510000 -#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c -#define USB_PHY_RX_EQ_VAL_1 0x0000 -#define USB_PHY_RX_EQ_VAL_2 0x0080 -#define USB_PHY_RX_EQ_VAL_3 0x0380 -#define USB_PHY_RX_EQ_VAL_4 0x0b80 - -#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 -#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 -#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 -#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 -#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 -#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 -#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 -#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 -#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 -#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 - -/* RGMIIPCR bit definitions*/ -#define SCFG_RGMIIPCR_EN_AUTO BIT(3) -#define SCFG_RGMIIPCR_SETSP_1000M BIT(2) -#define SCFG_RGMIIPCR_SETSP_100M 0 -#define SCFG_RGMIIPCR_SETSP_10M BIT(1) -#define SCFG_RGMIIPCR_SETFD BIT(0) - -/* PFEASBCR bit definitions */ -#define SCFG_PFEASBCR_ARCACHE0 BIT(31) -#define SCFG_PFEASBCR_AWCACHE0 BIT(30) -#define SCFG_PFEASBCR_ARCACHE1 BIT(29) -#define SCFG_PFEASBCR_AWCACHE1 BIT(28) -#define SCFG_PFEASBCR_ARSNP BIT(27) -#define SCFG_PFEASBCR_AWSNP BIT(26) - -/* WR_QoS1 PFE bit definitions */ -#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) -#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) - -/* RD_QoS1 PFE bit definitions */ -#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) -#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) - -/* Supplemental Configuration Unit */ -struct ccsr_scfg { - u8 res_000[0x100-0x000]; - u32 usb2_icid; - u32 usb3_icid; - u8 res_108[0x114-0x108]; - u32 dma_icid; - u32 sata_icid; - u32 usb1_icid; - u32 qe_icid; - u32 sdhc_icid; - u32 edma_icid; - u32 etr_icid; - u32 core_sft_rst[4]; - u8 res_140[0x158-0x140]; - u32 altcbar; - u32 qspi_cfg; - u8 res_160[0x164 - 0x160]; - u32 wr_qos1; - u32 wr_qos2; - u32 rd_qos1; - u32 rd_qos2; - u8 res_174[0x180 - 0x174]; - u32 dmamcr; - u8 res_184[0x188-0x184]; - u32 gic_align; - u32 debug_icid; - u8 res_190[0x1a4-0x190]; - u32 snpcnfgcr; - u8 res_1a8[0x1ac-0x1a8]; - u32 intpcr; - u8 res_1b0[0x204-0x1b0]; - u32 coresrencr; - u8 res_208[0x220-0x208]; - u32 rvbar0_0; - u32 rvbar0_1; - u32 rvbar1_0; - u32 rvbar1_1; - u32 rvbar2_0; - u32 rvbar2_1; - u32 rvbar3_0; - u32 rvbar3_1; - u32 lpmcsr; - u8 res_244[0x400-0x244]; - u32 qspidqscr; - u32 ecgtxcmcr; - u32 sdhciovselcr; - u32 rcwpmuxcr0; - u32 usbdrvvbus_selcr; - u32 usbpwrfault_selcr; - u32 usb_refclk_selcr1; - u32 usb_refclk_selcr2; - u32 usb_refclk_selcr3; - u8 res_424[0x434 - 0x424]; - u32 rgmiipcr; - u32 res_438; - u32 rgmiipsr; - u32 pfepfcssr1; - u32 pfeintencr1; - u32 pfepfcssr2; - u32 pfeintencr2; - u32 pfeerrcr; - u32 pfeeerrintencr; - u32 pfeasbcr; - u32 pfebsbcr; - u8 res_460[0x484 - 0x460]; - u32 mdioselcr; - u8 res_468[0x600 - 0x488]; - u32 scratchrw[4]; - u8 res_610[0x680-0x610]; - u32 corebcr; - u8 res_684[0x1000-0x684]; - u32 pex1msiir; - u32 pex1msir; - u8 res_1008[0x2000-0x1008]; - u32 pex2; - u32 pex2msir; - u8 res_2008[0x3000-0x2008]; - u32 pex3msiir; - u32 pex3msir; -}; - -/* Clocking */ -struct ccsr_clk { - struct { - u32 clkcncsr; /* core cluster n clock control status */ - u8 res_004[0x0c]; - u32 clkcghwacsr; /* Clock generator n hardware accelerator */ - u8 res_014[0x0c]; - } clkcsr[4]; - u8 res_040[0x780]; /* 0x100 */ - struct { - u32 pllcngsr; - u8 res_804[0x1c]; - } pllcgsr[2]; - u8 res_840[0x1c0]; - u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ - u8 res_a04[0x1fc]; - u32 pllpgsr; /* 0xc00 Platform PLL General Status */ - u8 res_c04[0x1c]; - u32 plldgsr; /* 0xc20 DDR PLL General Status */ - u8 res_c24[0x3dc]; -}; - -/* System Counter */ -struct sctr_regs { - u32 cntcr; - u32 cntsr; - u32 cntcv1; - u32 cntcv2; - u32 resv1[4]; - u32 cntfid0; - u32 cntfid1; - u32 resv2[1002]; - u32 counterid[12]; -}; - -#define SRDS_MAX_LANES 4 -struct ccsr_serdes { - struct { - u32 rstctl; /* Reset Control Register */ -#define SRDS_RSTCTL_RST 0x80000000 -#define SRDS_RSTCTL_RSTDONE 0x40000000 -#define SRDS_RSTCTL_RSTERR 0x20000000 -#define SRDS_RSTCTL_SWRST 0x10000000 -#define SRDS_RSTCTL_SDEN 0x00000020 -#define SRDS_RSTCTL_SDRST_B 0x00000040 -#define SRDS_RSTCTL_PLLRST_B 0x00000080 - u32 pllcr0; /* PLL Control Register 0 */ -#define SRDS_PLLCR0_POFF 0x80000000 -#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 -#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 -#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 -#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 -#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 -#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 -#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 -#define SRDS_PLLCR0_PLL_LCK 0x00800000 -#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 -#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 -#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 -#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 -#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 -#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 -#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 - u32 pllcr1; /* PLL Control Register 1 */ -#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 - u32 res_0c; /* 0x00c */ - u32 pllcr3; - u32 pllcr4; - u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ - u8 res_1c[0x20-0x1c]; - } bank[2]; - u8 res_40[0x90-0x40]; - u32 srdstcalcr; /* 0x90 TX Calibration Control */ - u8 res_94[0xa0-0x94]; - u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ - u8 res_a4[0xb0-0xa4]; - u32 srdsgr0; /* 0xb0 General Register 0 */ - u8 res_b4[0x100-0xb4]; - struct { - u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ - u8 res_104[0x120-0x104]; - } lnpssr[4]; /* Lane A, B, C, D */ - u8 res_180[0x200-0x180]; - u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ - u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ - u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ - u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ - u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ - u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ - u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ - u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ - u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ - u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ - u32 srdspccra; /* 0x228 Protocol Configuration A */ - u32 srdspccrb; /* 0x22c Protocol Configuration B */ - u8 res_230[0x800-0x230]; - struct { - u32 gcr0; /* 0x800 General Control Register 0 */ - u32 gcr1; /* 0x804 General Control Register 1 */ - u32 gcr2; /* 0x808 General Control Register 2 */ - u32 sscr0; - u32 recr0; /* 0x810 Receive Equalization Control */ - u32 recr1; - u32 tecr0; /* 0x818 Transmit Equalization Control */ - u32 sscr1; - u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ - u8 res_824[0x83c-0x824]; - u32 tcsr3; - } lane[4]; /* Lane A, B, C, D */ - u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ - struct { - u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ - u8 res_1004[0x1040-0x1004]; - } pcie[3]; - u8 res_10c0[0x1800-0x10c0]; - struct { - u8 res_1800[0x1804-0x1800]; - u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ - u8 res_1808[0x180c-0x1808]; - u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ - } sgmii[4]; /* Lane A, B, C, D */ - u8 res_1840[0x1880-0x1840]; - struct { - u8 res_1880[0x1884-0x1880]; - u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ - u8 res_1888[0x188c-0x1888]; - u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ - } qsgmii[2]; /* Lane A, B */ - u8 res_18a0[0x1980-0x18a0]; - struct { - u8 res_1980[0x1984-0x1980]; - u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ - u8 res_1988[0x198c-0x1988]; - u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ - } xfi[2]; /* Lane A, B */ - u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ -}; - -struct ccsr_gpio { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr; - u32 gpibe; -}; - -/* MMU 500 */ -#define SMMU_SCR0 (SMMU_BASE + 0x0) -#define SMMU_SCR1 (SMMU_BASE + 0x4) -#define SMMU_SCR2 (SMMU_BASE + 0x8) -#define SMMU_SACR (SMMU_BASE + 0x10) -#define SMMU_IDR0 (SMMU_BASE + 0x20) -#define SMMU_IDR1 (SMMU_BASE + 0x24) - -#define SMMU_NSCR0 (SMMU_BASE + 0x400) -#define SMMU_NSCR2 (SMMU_BASE + 0x408) -#define SMMU_NSACR (SMMU_BASE + 0x410) - -#define SCR0_CLIENTPD_MASK 0x00000001 -#define SCR0_USFCFG_MASK 0x00000400 - -#ifdef CONFIG_TFABOOT -#define RCW_SRC_MASK (0xFF800000) -#define RCW_SRC_BIT 23 - -/* RCW SRC NAND */ -#define RCW_SRC_NAND_MASK (0x100) -#define RCW_SRC_NAND_VAL (0x100) -#define NAND_RESERVED_MASK (0xFC) -#define NAND_RESERVED_1 (0x0) -#define NAND_RESERVED_2 (0x80) - -/* RCW SRC NOR */ -#define RCW_SRC_NOR_MASK (0x1F0) -#define NOR_8B_VAL (0x10) -#define NOR_16B_VAL (0x20) -#define SD_VAL (0x40) -#define QSPI_VAL1 (0x44) -#define QSPI_VAL2 (0x45) -#endif - -uint get_svr(void); - -#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h deleted file mode 100644 index 4f05047..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ /dev/null @@ -1,572 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LayerScape Internal Memory Map - * - * Copyright 2017-2019 NXP - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_FSL_LSCH3_IMMAP_H_ -#define __ARCH_FSL_LSCH3_IMMAP_H_ - -#define CONFIG_SYS_IMMR 0x01000000 -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) -#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) -#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) -#ifdef CONFIG_ARCH_LX2160A -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) -#else -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) -#endif -#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) -#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) -#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) -#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) -#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR -#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) -#ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) -#endif -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) -#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 -#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 -#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ - 0x18A0) -#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) -#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) - -#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) -#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) - -#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL -#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL -#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL -#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL - -#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) -#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) -#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) -#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) -#ifdef CONFIG_NXP_LSCH3_2 -#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) -#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) -#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) -#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) -#endif -#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) -#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) -#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) - -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) - -/* TZ Address Space Controller Definitions */ -#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ -#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ -#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ -#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ -#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) -#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) -#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) -#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) -#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) -#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) -#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) -#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) -#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) - -/* EDMA */ -#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000) - -/* SATA */ -#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) -#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) - -/* QDMA */ -#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) -#define QMAN_CQSIDR_REG 0x20a80 - -/* DISPLAY */ -#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000) - -/* GPU */ -#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) - -/* SFP */ -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) - -/* SEC */ -#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull -#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull -#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET -#define FSL_SEC_JR1_OFFSET 0x07020000ull -#define FSL_SEC_JR2_OFFSET 0x07030000ull -#define FSL_SEC_JR3_OFFSET 0x07040000ull -#define CONFIG_SYS_FSL_SEC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) -#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) -#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) -#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) -#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) - -#ifdef CONFIG_TFABOOT -#ifdef CONFIG_NXP_LSCH3_2 -/* RCW_SRC field in Power-On Reset Control Register 1 */ -#define RCW_SRC_MASK 0x07800000 -#define RCW_SRC_BIT 23 - -/* CFG_RCW_SRC[3:0] */ -#define RCW_SRC_TYPE_MASK 0x8 -#define RCW_SRC_ADDR_OFFSET_8MB 0x800000 - -/* RCW SRC HARDCODED */ -#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ - -#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ -#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ -#define RCW_SRC_I2C1_VAL 0xa /* 0xa */ -#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ -#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ -#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ -#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ -#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ -#else -#define RCW_SRC_MASK (0xFF800000) -#define RCW_SRC_BIT 23 -/* CFG_RCW_SRC[6:0] */ -#define RCW_SRC_TYPE_MASK (0x70) - -/* RCW SRC HARDCODED */ -#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ -/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ - -/* RCW SRC NOR */ -#define RCW_SRC_NOR_VAL (0x20) -#define NOR_TYPE_MASK (0x10) -#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ -#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ - -/* RCW SRC Serial Flash - * 1. SERIAL NOR (QSPI) - * 2. OTHERS (SD/MMC, SPI, I2C1 - */ -#define RCW_SRC_SERIAL_MASK (0x7F) -#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ -#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ -#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ -#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ -#endif -#endif - -/* Security Monitor */ -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) - -/* MMU 500 */ -#define SMMU_SCR0 (SMMU_BASE + 0x0) -#define SMMU_SCR1 (SMMU_BASE + 0x4) -#define SMMU_SCR2 (SMMU_BASE + 0x8) -#define SMMU_SACR (SMMU_BASE + 0x10) -#define SMMU_IDR0 (SMMU_BASE + 0x20) -#define SMMU_IDR1 (SMMU_BASE + 0x24) - -#define SMMU_NSCR0 (SMMU_BASE + 0x400) -#define SMMU_NSCR2 (SMMU_BASE + 0x408) -#define SMMU_NSACR (SMMU_BASE + 0x410) - -#define SCR0_CLIENTPD_MASK 0x00000001 -#define SCR0_USFCFG_MASK 0x00000400 - - -/* PCIe */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) -#ifdef CONFIG_ARCH_LX2160A -#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) -#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) -#endif - -#ifdef CONFIG_ARCH_LX2160A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL -#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL -#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL -#elif CONFIG_ARCH_LS1088A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL -#elif CONFIG_ARCH_LS1028A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL -/* this is used by integrated PCI on LS1028, includes ECAM and register space */ -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL -#else -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL -#endif - -/* Device Configuration */ -#define DCFG_BASE 0x01e00000 -#define DCFG_PORSR1 0x000 -#define DCFG_PORSR1_RCW_SRC 0xff800000 -#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 -#define DCFG_RCWSR13 0x130 -#define DCFG_RCWSR13_DSPI (0 << 8) -#define DCFG_RCWSR15 0x138 -#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 - -#define DCFG_DCSR_BASE 0X700100000ULL -#define DCFG_DCSR_PORCR1 0x000 - -/* Interrupt Sampling Control */ -#define ISC_BASE 0x01F70000 -#define IRQCR_OFFSET 0x14 - -/* Supplemental Configuration */ -#define SCFG_BASE 0x01fc0000 -#define SCFG_USB3PRM1CR 0x000 -#define SCFG_USB3PRM1CR_INIT 0x27672b2a -#define SCFG_USB_TXVREFTUNE 0x9 -#define SCFG_USB_SQRXTUNE_MASK 0x7 -#define SCFG_QSPICLKCTLR 0x10 - -#define DCSR_BASE 0x700000000ULL -#define DCSR_USB_PHY1 0x4600000 -#define DCSR_USB_PHY2 0x4610000 -#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C -#define USB_PHY_RX_EQ_VAL_1 0x0000 -#define USB_PHY_RX_EQ_VAL_2 0x0080 -#define USB_PHY_RX_EQ_VAL_3 0x0380 -#define USB_PHY_RX_EQ_VAL_4 0x0b80 -#define DCSR_USB_IOCR1 0x108004 -#define DCSR_USB_PCSTXSWINGFULL 0x71 - -#define TP_ITYP_AV 0x00000001 /* Initiator available */ -#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ -#define TP_ITYP_TYPE_ARM 0x0 -#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ -#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ -#define TY_ITYP_VER_A7 0x1 -#define TY_ITYP_VER_A53 0x2 -#define TY_ITYP_VER_A57 0x3 -#define TY_ITYP_VER_A72 0x4 - -#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ -#define TP_INIT_PER_CLUSTER 4 -/* This is chassis generation 3 */ -#ifndef __ASSEMBLY__ -struct sys_info { - unsigned long freq_processor[CONFIG_MAX_CPUS]; - /* frequency of platform PLL */ - unsigned long freq_systembus; - unsigned long freq_ddrbus; - unsigned long freq_cga_m2; -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - unsigned long freq_ddrbus2; -#endif - unsigned long freq_localbus; - unsigned long freq_qe; -#ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; -#endif -#ifdef CONFIG_SYS_DPAA_QBMAN - unsigned long freq_qman; -#endif -#ifdef CONFIG_SYS_DPAA_PME - unsigned long freq_pme; -#endif -}; - -/* Global Utilities Block */ -struct ccsr_gur { - u32 porsr1; /* POR status 1 */ - u32 porsr2; /* POR status 2 */ - u8 res_008[0x20-0x8]; - u32 gpporcr1; /* General-purpose POR configuration */ - u32 gpporcr2; /* General-purpose POR configuration 2 */ - u32 gpporcr3; - u32 gpporcr4; - u8 res_030[0x60-0x30]; -#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F -#if defined(CONFIG_ARCH_LS1088A) -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 -#else -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 -#endif - u32 dcfg_fusesr; /* Fuse status register */ - u8 res_064[0x70-0x64]; - u32 devdisr; /* Device disable control 1 */ - u32 devdisr2; /* Device disable control 2 */ - u32 devdisr3; /* Device disable control 3 */ - u32 devdisr4; /* Device disable control 4 */ - u32 devdisr5; /* Device disable control 5 */ - u32 devdisr6; /* Device disable control 6 */ - u8 res_088[0x94-0x88]; - u32 coredisr; /* Device disable control 7 */ -#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 -#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 -#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 -#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 -#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 -#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 -#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 -#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 -#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 -#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 -#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 -#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 -#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 - u8 res_098[0xa0-0x98]; - u32 pvr; /* Processor version */ - u32 svr; /* System version */ - u8 res_0a8[0x100-0xa8]; - u32 rcwsr[30]; /* Reset control word status */ - -#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 -#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f -#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 -#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 -#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f - -#if defined(CONFIG_ARCH_LS2080A) -#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 -#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 -#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 -#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 -#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK -#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK -#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS1_REGSR 29 -#define FSL_CHASSIS3_SRDS2_REGSR 29 -#elif defined(CONFIG_ARCH_LX2160A) -#define FSL_CHASSIS3_EC1_REGSR 27 -#define FSL_CHASSIS3_EC2_REGSR 27 -#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 -#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 -#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 -#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 -#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 -#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 -#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 -#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 -#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 -#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 -#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK -#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK -#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK -#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS1_REGSR 29 -#define FSL_CHASSIS3_SRDS2_REGSR 29 -#define FSL_CHASSIS3_SRDS3_REGSR 29 -#define FSL_CHASSIS3_RCWSR12_REGSR 12 -#define FSL_CHASSIS3_RCWSR13_REGSR 13 -#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000 -#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24 -#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038 -#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3 -#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00 -#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9 -#elif defined(CONFIG_ARCH_LS1088A) -#define FSL_CHASSIS3_EC1_REGSR 26 -#define FSL_CHASSIS3_EC2_REGSR 26 -#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 -#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 -#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 -#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 -#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 -#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 -#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF -#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0 -#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK -#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK -#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS1_REGSR 29 -#define FSL_CHASSIS3_SRDS2_REGSR 30 -#elif defined(CONFIG_ARCH_LS1028A) -#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 -#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 -#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK -#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT -#define FSL_CHASSIS3_SRDS1_REGSR 29 -#endif -#define RCW_SB_EN_REG_INDEX 9 -#define RCW_SB_EN_MASK 0x00000400 - - u8 res_178[0x200-0x178]; - u32 scratchrw[16]; /* Scratch Read/Write */ - u8 res_240[0x300-0x240]; - u32 scratchw1r[4]; /* Scratch Read (Write once) */ - u8 res_310[0x400-0x310]; - u32 bootlocptrl; /* Boot location pointer low-order addr */ - u32 bootlocptrh; /* Boot location pointer high-order addr */ - u8 res_408[0x520-0x408]; - u32 usb1_amqr; - u32 usb2_amqr; - u8 res_528[0x530-0x528]; /* add more registers when needed */ - u32 sdmm1_amqr; - u32 sdmm2_amqr; - u8 res_538[0x550 - 0x538]; /* add more registers when needed */ - u32 sata1_amqr; - u32 sata2_amqr; - u8 res_558[0x570-0x558]; /* add more registers when needed */ - u32 misc1_amqr; - u8 res_574[0x590-0x574]; /* add more registers when needed */ - u32 spare1_amqr; - u32 spare2_amqr; - u32 spare3_amqr; - u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ - u32 gencr[7]; /* General Control Registers */ - u8 res_63c[0x640-0x63c]; /* add more registers when needed */ - u32 cgensr1; /* Core General Status Register */ - u8 res_644[0x660-0x644]; /* add more registers when needed */ - u32 cgencr1; /* Core General Control Register */ - u8 res_664[0x740-0x664]; /* add more registers when needed */ - u32 tp_ityp[64]; /* Topology Initiator Type Register */ - struct { - u32 upper; - u32 lower; - } tp_cluster[4]; /* Core cluster n Topology Register */ - u8 res_864[0x920-0x864]; /* add more registers when needed */ - u32 ioqoscr[8]; /*I/O Quality of Services Register */ - u32 uccr; - u8 res_944[0x960-0x944]; /* add more registers when needed */ - u32 ftmcr; - u8 res_964[0x990-0x964]; /* add more registers when needed */ - u32 coredisablesr; - u8 res_994[0xa00-0x994]; /* add more registers when needed */ - u32 sdbgcr; /*Secure Debug Confifuration Register */ - u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ - u32 ipbrr1; - u32 ipbrr2; - u8 res_858[0x1000-0xc00]; -}; - -struct ccsr_clk_cluster_group { - struct { - u8 res_00[0x10]; - u32 csr; - u8 res_14[0x20-0x14]; - } hwncsr[3]; - u8 res_60[0x80-0x60]; - struct { - u32 gsr; - u8 res_84[0xa0-0x84]; - } pllngsr[3]; - u8 res_e0[0x100-0xe0]; -}; - -struct ccsr_clk_ctrl { - struct { - u32 csr; /* core cluster n clock control status */ - u8 res_04[0x20-0x04]; - } clkcncsr[8]; -}; - -struct ccsr_reset { - u32 rstcr; /* 0x000 */ - u32 rstcrsp; /* 0x004 */ - u8 res_008[0x10-0x08]; /* 0x008 */ - u32 rstrqmr1; /* 0x010 */ - u32 rstrqmr2; /* 0x014 */ - u32 rstrqsr1; /* 0x018 */ - u32 rstrqsr2; /* 0x01c */ - u32 rstrqwdtmrl; /* 0x020 */ - u32 rstrqwdtmru; /* 0x024 */ - u8 res_028[0x30-0x28]; /* 0x028 */ - u32 rstrqwdtsrl; /* 0x030 */ - u32 rstrqwdtsru; /* 0x034 */ - u8 res_038[0x60-0x38]; /* 0x038 */ - u32 brrl; /* 0x060 */ - u32 brru; /* 0x064 */ - u8 res_068[0x80-0x68]; /* 0x068 */ - u32 pirset; /* 0x080 */ - u32 pirclr; /* 0x084 */ - u8 res_088[0x90-0x88]; /* 0x088 */ - u32 brcorenbr; /* 0x090 */ - u8 res_094[0x100-0x94]; /* 0x094 */ - u32 rcw_reqr; /* 0x100 */ - u32 rcw_completion; /* 0x104 */ - u8 res_108[0x110-0x108]; /* 0x108 */ - u32 pbi_reqr; /* 0x110 */ - u32 pbi_completion; /* 0x114 */ - u8 res_118[0xa00-0x118]; /* 0x118 */ - u32 qmbm_warmrst; /* 0xa00 */ - u32 soc_warmrst; /* 0xa04 */ - u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ - u32 ip_rev1; /* 0xbf8 */ - u32 ip_rev2; /* 0xbfc */ -}; - -struct ccsr_serdes { - struct { - u32 rstctl; /* Reset Control Register */ - u32 pllcr0; /* PLL Control Register 0 */ - u32 pllcr1; /* PLL Control Register 1 */ - u32 pllcr2; /* PLL Control Register 2 */ - u32 pllcr3; /* PLL Control Register 3 */ - u32 pllcr4; /* PLL Control Register 4 */ - u32 pllcr5; /* PLL Control Register 5 */ - u8 res[0x20 - 0x1c]; - } bank[2]; - u8 res1[0x90 - 0x40]; - u32 srdstcalcr; /* TX Calibration Control */ - u32 srdstcalcr1; /* TX Calibration Control1 */ - u8 res2[0xa0 - 0x98]; - u32 srdsrcalcr; /* RX Calibration Control */ - u32 srdsrcalcr1; /* RX Calibration Control1 */ - u8 res3[0xb0 - 0xa8]; - u32 srdsgr0; /* General Register 0 */ - u8 res4[0x800 - 0xb4]; - struct serdes_lane { - u32 gcr0; /* General Control Register 0 */ - u32 gcr1; /* General Control Register 1 */ - u32 gcr2; /* General Control Register 2 */ - u32 ssc0; /* Speed Switch Control 0 */ - u32 rec0; /* Receive Equalization Control 0 */ - u32 rec1; /* Receive Equalization Control 1 */ - u32 tec0; /* Transmit Equalization Control 0 */ - u32 ssc1; /* Speed Switch Control 1 */ - u8 res1[0x840 - 0x820]; - } lane[8]; - u8 res5[0x19fc - 0xa00]; -}; - -#endif /*__ASSEMBLY__*/ -#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h deleted file mode 100644 index d709af8..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - */ - -#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ -#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ - -#define I2C_QUIRK_REG /* enable 8-bit driver */ - -#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h deleted file mode 100644 index 661cdea..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015, Freescale Semiconductor - */ - -#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ -#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ -void update_early_mmu_table(void); -#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h deleted file mode 100644 index 00aa91b..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2015, Freescale Semiconductor - */ - -#ifndef _FSL_LAYERSCAPE_MP_H -#define _FSL_LAYERSCAPE_MP_H - -/* -* Each spin table element is defined as -* struct { -* uint64_t entry_addr; -* uint64_t status; -* uint64_t lpid; -* uint64_t arch_comp; -* }; -* we pad this struct to 64 bytes so each entry is in its own cacheline -* the actual spin table is an array of these structures -*/ -#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 -#define SPIN_TABLE_ELEM_STATUS_IDX 1 -#define SPIN_TABLE_ELEM_LPID_IDX 2 -/* compare os arch and cpu arch */ -#define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3 -#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ -#define SPIN_TABLE_ELEM_SIZE 64 - -/* os arch is same as cpu arch */ -#define OS_ARCH_SAME 0 -/* os arch is different from cpu arch */ -#define OS_ARCH_DIFF 1 - -#define id_to_core(x) ((x & 3) | (x >> 6)) -#ifndef __ASSEMBLY__ -extern u64 __spin_table[]; -extern u64 __real_cntfrq; -extern u64 *secondary_boot_code; -extern size_t __secondary_boot_code_size; -#ifdef CONFIG_MP -int fsl_layerscape_wake_seconday_cores(void); -#else -static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } -#endif -void *get_spin_tbl_addr(void); -phys_addr_t determine_mp_bootpg(void); -void secondary_boot_func(void); -int is_core_online(u64 cpu_id); -u32 cpu_pos_mask(void); -#endif - -#endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h deleted file mode 100644 index a265106..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_NS_ACCESS_H_ -#define __FSL_NS_ACCESS_H_ -#include <fsl_csu.h> - -enum csu_cslx_ind { - CSU_CSLX_PCIE2_IO = 0, - CSU_CSLX_PCIE1_IO, - CSU_CSLX_MG2TPR_IP, - CSU_CSLX_IFC_MEM, - CSU_CSLX_OCRAM, - CSU_CSLX_GIC, - CSU_CSLX_PCIE1, - CSU_CSLX_OCRAM2, - CSU_CSLX_QSPI_MEM, - CSU_CSLX_PCIE2, - CSU_CSLX_SATA, - CSU_CSLX_USB1, - CSU_CSLX_QM_BM_SWPORTAL, - CSU_CSLX_PCIE3 = 16, - CSU_CSLX_PCIE3_IO, - CSU_CSLX_USB3 = 20, - CSU_CSLX_USB2, - CSU_CSLX_PFE = 23, - CSU_CSLX_SERDES = 32, - CSU_CSLX_QDMA, - CSU_CSLX_LPUART2, - CSU_CSLX_LPUART1, - CSU_CSLX_LPUART4, - CSU_CSLX_LPUART3, - CSU_CSLX_LPUART6, - CSU_CSLX_LPUART5, - CSU_CSLX_DSPI1 = 41, - CSU_CSLX_QSPI, - CSU_CSLX_ESDHC, - CSU_CSLX_IFC = 45, - CSU_CSLX_I2C1, - CSU_CSLX_USB_2, - CSU_CSLX_I2C3 = 48, - CSU_CSLX_I2C2, - CSU_CSLX_DUART2 = 50, - CSU_CSLX_DUART1, - CSU_CSLX_WDT2, - CSU_CSLX_WDT1, - CSU_CSLX_EDMA, - CSU_CSLX_SYS_CNT, - CSU_CSLX_DMA_MUX2, - CSU_CSLX_DMA_MUX1, - CSU_CSLX_DDR, - CSU_CSLX_QUICC, - CSU_CSLX_DCFG_CCU_RCPM = 60, - CSU_CSLX_SECURE_BOOTROM, - CSU_CSLX_SFP, - CSU_CSLX_TMU, - CSU_CSLX_SECURE_MONITOR, - CSU_CSLX_SCFG, - CSU_CSLX_FM = 66, - CSU_CSLX_SEC5_5, - CSU_CSLX_BM, - CSU_CSLX_QM, - CSU_CSLX_GPIO2 = 70, - CSU_CSLX_GPIO1, - CSU_CSLX_GPIO4, - CSU_CSLX_GPIO3, - CSU_CSLX_PLATFORM_CONT, - CSU_CSLX_CSU, - CSU_CSLX_IIC4 = 77, - CSU_CSLX_WDT4, - CSU_CSLX_WDT3, - CSU_CSLX_ESDHC2 = 80, - CSU_CSLX_WDT5 = 81, - CSU_CSLX_SAI2, - CSU_CSLX_SAI1, - CSU_CSLX_SAI4, - CSU_CSLX_SAI3, - CSU_CSLX_FTM2 = 86, - CSU_CSLX_FTM1, - CSU_CSLX_FTM4, - CSU_CSLX_FTM3, - CSU_CSLX_FTM6 = 90, - CSU_CSLX_FTM5, - CSU_CSLX_FTM8, - CSU_CSLX_FTM7, - CSU_CSLX_DSCR = 121, -}; - -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h deleted file mode 100644 index f0c4a84..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 NXP Semiconductor, Inc. - */ - -#ifndef __FSL_PPA_H_ -#define __FSL_PPA_H_ - -#ifdef CONFIG_FSL_LS_PPA -int ppa_init(void); -#endif -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h deleted file mode 100644 index 35719d7..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017-2019 NXP - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ -#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ - -#ifndef __ASSEMBLY__ -#include <linux/types.h> -#ifdef CONFIG_FSL_LSCH2 -#include <asm/arch/immap_lsch2.h> -#endif -#ifdef CONFIG_FSL_LSCH3 -#include <asm/arch/immap_lsch3.h> -#endif -#endif - -#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE -#define gur_in32(a) in_le32(a) -#define gur_out32(a, v) out_le32(a, v) -#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) -#define gur_in32(a) in_be32(a) -#define gur_out32(a, v) out_be32(a, v) -#endif - -#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE -#define scfg_in32(a) in_le32(a) -#define scfg_out32(a, v) out_le32(a, v) -#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear) -#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set) -#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) -#define scfg_in32(a) in_be32(a) -#define scfg_out32(a, v) out_be32(a, v) -#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear) -#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set) -#endif - -#ifdef CONFIG_SYS_FSL_PEX_LUT_LE -#define pex_lut_in32(a) in_le32(a) -#define pex_lut_out32(a, v) out_le32(a, v) -#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) -#define pex_lut_in32(a) in_be32(a) -#define pex_lut_out32(a, v) out_be32(a, v) -#endif -#ifndef __ASSEMBLY__ -struct cpu_type { - char name[15]; - u32 soc_ver; - u32 num_cores; -}; - -#define CPU_TYPE_ENTRY(n, v, nc) \ - { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} - -#ifdef CONFIG_TFABOOT -#define SMC_DRAM_BANK_INFO (0xC200FF12) -#define SIP_SVC_RCW 0xC200FF18 - -phys_size_t tfa_get_dram_size(void); - -enum boot_src { - BOOT_SOURCE_RESERVED = 0, - BOOT_SOURCE_IFC_NOR, - BOOT_SOURCE_IFC_NAND, - BOOT_SOURCE_QSPI_NOR, - BOOT_SOURCE_QSPI_NAND, - BOOT_SOURCE_XSPI_NOR, - BOOT_SOURCE_XSPI_NAND, - BOOT_SOURCE_SD_MMC, - BOOT_SOURCE_SD_MMC2, - BOOT_SOURCE_I2C1_EXTENDED, -}; - -enum boot_src get_boot_src(void); -#endif -#endif -#define SVR_WO_E 0xFFFFFE -#define SVR_LS1012A 0x870400 -#define SVR_LS1043A 0x879200 -#define SVR_LS1023A 0x879208 -/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ -#define SVR_LS1043A_P23 0x879202 -#define SVR_LS1023A_P23 0x87920A -#define SVR_LS1017A 0x870B24 -#define SVR_LS1018A 0x870B20 -#define SVR_LS1027A 0x870B04 -#define SVR_LS1028A 0x870B00 -#define SVR_LS1046A 0x870700 -#define SVR_LS1026A 0x870708 -#define SVR_LS1048A 0x870320 -#define SVR_LS1084A 0x870302 -#define SVR_LS1088A 0x870300 -#define SVR_LS1044A 0x870322 -#define SVR_LS2045A 0x870120 -#define SVR_LS2080A 0x870110 -#define SVR_LS2085A 0x870100 -#define SVR_LS2040A 0x870130 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 -#define SVR_LX2160A 0x873600 -#define SVR_LX2120A 0x873620 -#define SVR_LX2080A 0x873602 - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) -#define SVR_MIN(svr) (((svr) >> 0) & 0xf) -#define SVR_REV(svr) (((svr) >> 0) & 0xff) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) -#ifdef CONFIG_ARCH_LX2160A -#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) -#endif -#ifdef CONFIG_ARCH_LS1028A -#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) -#endif -#define IS_SVR_REV(svr, maj, min) \ - ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) -#define SVR_DEV(svr) ((svr) >> 8) -#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_FSL_LSCH3 -void fsl_lsch3_early_init_f(void); -int get_core_volt_from_fuse(void); -#elif defined(CONFIG_FSL_LSCH2) -void fsl_lsch2_early_init_f(void); -int setup_chip_volt(void); -/* Setup core vdd in unit mV */ -int board_setup_core_volt(u32 vdd); -#ifdef CONFIG_FSL_PFE -void init_pfe_scfg_dcfg_regs(void); -#endif -#endif -#ifdef CONFIG_QSPI_AHB_INIT -int qspi_ahb_init(void); -#endif - -void cpu_name(char *name); -#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 -void erratum_a009635(void); -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 -void erratum_a010315(void); -#endif - -bool soc_has_dp_ddr(void); -bool soc_has_aiop(void); -#endif - -#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h deleted file mode 100644 index 2672169..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/speed.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2015, Freescale Semiconductor, Inc. - */ - -#ifndef _FSL_LAYERSCAPE_SPEED_H -#define _FSL_LAYERSCAPE_SPEED_H -void get_sys_info(struct sys_info *sys_info); -#ifdef CONFIG_SYS_DPAA_QBMAN -unsigned long get_qman_freq(void); -#endif -#endif /* _FSL_LAYERSCAPE_SPEED_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h deleted file mode 100644 index 1b02d48..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP Semiconductor, Inc. - * - */ -#ifndef __FSL_STREAM_ID_H -#define __FSL_STREAM_ID_H - -/* - * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices - * are not hardwired and are programmed by sw. There are a limited number - * of stream IDs available, and the partitioning of them is scenario - * dependent. This header defines the partitioning between legacy, PCI, - * and DPAA1 devices. - * - * This partitioning can be customized in this file depending - * on the specific hardware config: - * - * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) - * -all legacy devices get a unique stream ID assigned and programmed in - * their AMQR registers by u-boot - * - * -PCIe - * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: - * -allocate a streamID - * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' - * -set a msi-map entry in the PEXn controller node in the - * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt - * for more info on the msi-map definition) - * -set a iommu-map entry in the PEXn controller node in the - * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt - * for more info on the iommu-map definition) - * - * -DPAA1 - * - Stream ids for DPAA1 use are reserved for future usecase. - * - */ - - -#define FSL_INVALID_STREAM_ID 0 - -/* legacy devices */ -#define FSL_USB1_STREAM_ID 1 -#define FSL_USB2_STREAM_ID 2 -#define FSL_USB3_STREAM_ID 3 -#define FSL_SDHC_STREAM_ID 4 -#define FSL_SATA_STREAM_ID 5 -#define FSL_QE_STREAM_ID 6 -#define FSL_QDMA_STREAM_ID 7 -#define FSL_EDMA_STREAM_ID 8 -#define FSL_ETR_STREAM_ID 9 -#define FSL_DEBUG_STREAM_ID 10 - -/* PCI - programmed in PEXn_LUT */ -#define FSL_PEX_STREAM_ID_START 11 -#define FSL_PEX_STREAM_ID_END 26 - -/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ -#define FSL_DPAA1_STREAM_ID_START 27 -#define FSL_DPAA1_STREAM_ID_END 63 - -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h deleted file mode 100644 index 93bdcc4..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015-2018 NXP - * Copyright 2014 Freescale Semiconductor, Inc. - * - */ -#ifndef __FSL_STREAM_ID_H -#define __FSL_STREAM_ID_H - -/* - * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) - * devices are not hardwired and are programmed by sw. There are a limited - * number of stream IDs available, and the partitioning of them is scenario - * dependent. This header defines the partitioning between legacy, - * PCI, and DPAA2 devices. - * - * This partitioning can be customized in this file depending - * on the specific hardware config: - * - * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) - * -all legacy devices get a unique stream ID assigned and programmed in - * their AMQR registers by u-boot - * - * -PCIe - * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: - * -allocate a streamID - * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' - * -set a msi-map entry in the PEXn controller node in the - * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt - * for more info on the msi-map definition) - * -set a iommu-map entry in the PEXn controller node in the - * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt - * for more info on the iommu-map definition) - * - * -DPAA2 - * -u-boot will allocate a range of stream IDs to be used by the Management - * Complex for containers and will set these values in the MC DPC image. - * -u-boot will fixup the iommu-map property in the fsl-mc node in the - * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt - * for more info on the msi-map definition) - * -the MC is responsible for allocating and setting up 'isolation context - * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. - * - * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for - * each of the different bus masters. The relationship between - * the AMQ registers and stream IDs is defined in the table below: - * AMQ bit streamID bit - * --------------------------- - * PL[18] 9 // privilege bit - * BMT[17] 8 // bypass translation - * VA[16] 7 // reserved - * [15] - // unused - * ICID[14:7] - // unused - * ICID[6:0] 6-0 // isolation context id - * ---------------------------- - * - */ - -#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ -#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ - -#define FSL_INVALID_STREAM_ID 0 - -#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) - -/* legacy devices */ -#define FSL_USB1_STREAM_ID 1 -#define FSL_USB2_STREAM_ID 2 -#define FSL_SDMMC_STREAM_ID 3 -#define FSL_SATA1_STREAM_ID 4 - -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) -#define FSL_SATA2_STREAM_ID 5 -#endif - -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) -#define FSL_DMA_STREAM_ID 6 -#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) -#define FSL_DMA_STREAM_ID 5 -#endif - -/* PCI - programmed in PEXn_LUT */ -#define FSL_PEX_STREAM_ID_START 7 - -#ifdef CONFIG_ARCH_LX2160A -#define FSL_PEX_STREAM_ID_NUM (0x100) -#endif - -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) -#define FSL_PEX_STREAM_ID_END 22 -#elif defined(CONFIG_ARCH_LS1088A) -#define FSL_PEX_STREAM_ID_END 18 -#endif - - -/* DPAA2 - set in MC DPC and alloced by MC */ -#define FSL_DPAA2_STREAM_ID_START 23 -#define FSL_DPAA2_STREAM_ID_END 63 - -#define FSL_SEC_STREAM_ID 64 -#define FSL_SEC_JR1_STREAM_ID 65 -#define FSL_SEC_JR2_STREAM_ID 66 -#define FSL_SEC_JR3_STREAM_ID 67 -#define FSL_SEC_JR4_STREAM_ID 68 - -#define FSL_SDMMC2_STREAM_ID 69 -#define FSL_EDMA_STREAM_ID 70 -#define FSL_GPU_STREAM_ID 71 -#define FSL_DISPLAY_STREAM_ID 72 - -#endif diff --git a/arch/arm/include/asm/arch-hi3660/hi3660.h b/arch/arm/include/asm/arch-hi3660/hi3660.h deleted file mode 100644 index 3ca0951..0000000 --- a/arch/arm/include/asm/arch-hi3660/hi3660.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Linaro - * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - */ - -#ifndef __HI3660_H__ -#define __HI3660_H__ - -#define HI3660_UART6_BASE 0xfff32000 - -#define PMU_REG_BASE 0xfff34000 -#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2)) - -#define SCTRL_REG_BASE 0xfff0a000 -#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120) -#define SCTRL_SCFPLLCTRL0_FPLL0_EN BIT(0) - -#define CRG_REG_BASE 0xfff35000 -#define CRG_PEREN2 (CRG_REG_BASE + 0x020) -#define CRG_PERDIS2 (CRG_REG_BASE + 0x024) -#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028) -#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C) -#define CRG_PEREN4 (CRG_REG_BASE + 0x040) -#define CRG_PERDIS4 (CRG_REG_BASE + 0x044) -#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048) -#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C) -#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078) -#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C) -#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080) -#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084) -#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088) -#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C) -#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090) -#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094) -#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098) -#define CRG_ISOEN (CRG_REG_BASE + 0x144) -#define CRG_ISODIS (CRG_REG_BASE + 0x148) -#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C) - -#define PINMUX4_BASE 0xfff11000 -#define PINMUX4_SDDET (PINMUX4_BASE + 0x60) - -#define PINCONF3_BASE 0xff37e800 -#define PINCONF3_SDCLK (PINCONF3_BASE + 0x00) -#define PINCONF3_SDCMD (PINCONF3_BASE + 0x04) -#define PINCONF3_SDDATA0 (PINCONF3_BASE + 0x08) -#define PINCONF3_SDDATA1 (PINCONF3_BASE + 0x0c) -#define PINCONF3_SDDATA2 (PINCONF3_BASE + 0x10) -#define PINCONF3_SDDATA3 (PINCONF3_BASE + 0x14) - -#endif /*__HI3660_H__*/ diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h deleted file mode 100644 index b98b45c..0000000 --- a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Linaro - * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> - */ - -#ifndef __HI3798cv200_H__ -#define __HI3798cv200_H__ - -#define REG_BASE_PERI_CTRL 0xF8A20000 -#define REG_BASE_CRG 0xF8A22000 - -/* DEVICES */ -#define REG_BASE_UART0 0xF8B00000 -#define HIOTG_BASE_ADDR 0xF98C0000 - -/* PERI control registers (4KB) */ - /* USB2 PHY01 configuration register */ -#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) - - /* USB2 controller configuration register */ -#define PERI_CTRL_USB3 (REG_BASE_PERI_CTRL + 0x12c) -#define USB2_2P_CHIPID (1 << 28) - -/* PERI CRG registers (4KB) */ - /* USB2 CTRL0 clock and soft reset */ -#define PERI_CRG46 (REG_BASE_CRG + 0xb8) -#define USB2_BUS_CKEN (1<<0) -#define USB2_OHCI48M_CKEN (1<<1) -#define USB2_OHCI12M_CKEN (1<<2) -#define USB2_OTG_UTMI_CKEN (1<<3) -#define USB2_HST_PHY_CKEN (1<<4) -#define USB2_UTMI0_CKEN (1<<5) -#define USB2_BUS_SRST_REQ (1<<12) -#define USB2_UTMI0_SRST_REQ (1<<13) -#define USB2_HST_PHY_SYST_REQ (1<<16) -#define USB2_OTG_PHY_SYST_REQ (1<<17) -#define USB2_CLK48_SEL (1<<20) - - /* USB2 PHY clock and soft reset */ -#define PERI_CRG47 (REG_BASE_CRG + 0xbc) -#define USB2_PHY01_REF_CKEN (1 << 0) -#define USB2_PHY2_REF_CKEN (1 << 2) -#define USB2_PHY01_SRST_REQ (1 << 4) -#define USB2_PHY2_SRST_REQ (1 << 6) -#define USB2_PHY01_SRST_TREQ0 (1 << 8) -#define USB2_PHY01_SRST_TREQ1 (1 << 9) -#define USB2_PHY2_SRST_TREQ (1 << 10) -#define USB2_PHY01_REFCLK_SEL (1 << 12) -#define USB2_PHY2_REFCLK_SEL (1 << 14) - - -#endif diff --git a/arch/arm/include/asm/arch-hi6220/dwmmc.h b/arch/arm/include/asm/arch-hi6220/dwmmc.h deleted file mode 100644 index cf51c17..0000000 --- a/arch/arm/include/asm/arch-hi6220/dwmmc.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h deleted file mode 100644 index c5ee359..0000000 --- a/arch/arm/include/asm/arch-hi6220/gpio.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef _HI6220_GPIO_H_ -#define _HI6220_GPIO_H_ - -#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \ - 0xf7020000 - 0x4000) + (0x1000 * bank)) - -#define HI6220_GPIO_PER_BANK 8 -#define HI6220_GPIO_DIR 0x400 - -struct gpio_bank { - u8 *base; /* address of registers in physical memory */ -}; - -/* Information about a GPIO bank */ -struct hikey_gpio_platdata { - int bank_index; - ulong base; /* address of registers in physical memory */ -}; - -#endif /* _HI6220_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h deleted file mode 100644 index 55729e3..0000000 --- a/arch/arm/include/asm/arch-hi6220/hi6220.h +++ /dev/null @@ -1,389 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __HI6220_H__ -#define __HI6220_H__ - -#include "hi6220_regs_alwayson.h" - -#define HI6220_MMC0_BASE 0xF723D000 -#define HI6220_MMC1_BASE 0xF723E000 - -#define HI6220_UART0_BASE 0xF8015000 -#define HI6220_UART3_BASE 0xF7113000 - -#define HI6220_PMUSSI_BASE 0xF8000000 - -#define HI6220_PERI_BASE 0xF7030000 - -struct peri_sc_periph_regs { - u32 ctrl1; /*0x0*/ - u32 ctrl2; - u32 ctrl3; - u32 ctrl4; - u32 ctrl5; - u32 ctrl6; - u32 ctrl8; - u32 ctrl9; - u32 ctrl10; - u32 ctrl12; - u32 ctrl13; - u32 ctrl14; - - u32 unknown_1[8]; - - u32 ddr_ctrl0; /*0x50*/ - - u32 unknown_2[16]; - - u32 stat1; /*0x94*/ - - u32 unknown_3[90]; - - u32 clk0_en; /*0x200*/ - u32 clk0_dis; - u32 clk0_stat; - - u32 unknown_4; - - u32 clk1_en; /*0x210*/ - u32 clk1_dis; - u32 clk1_stat; - - u32 unknown_5; - - u32 clk2_en; /*0x220*/ - u32 clk2_dis; - u32 clk2_stat; - - u32 unknown_6; - - u32 clk3_en; /*0x230*/ - u32 clk3_dis; - u32 clk3_stat; - - u32 unknown_7; - - u32 clk8_en; /*0x240*/ - u32 clk8_dis; - u32 clk8_stat; - - u32 unknown_8; - - u32 clk9_en; /*0x250*/ - u32 clk9_dis; - u32 clk9_stat; - - u32 unknown_9; - - u32 clk10_en; /*0x260*/ - u32 clk10_dis; - u32 clk10_stat; - - u32 unknown_10; - - u32 clk12_en; /*0x270*/ - u32 clk12_dis; - u32 clk12_stat; - - u32 unknown_11[33]; - - u32 rst0_en; /*0x300*/ - u32 rst0_dis; - u32 rst0_stat; - - u32 unknown_12; - - u32 rst1_en; /*0x310*/ - u32 rst1_dis; - u32 rst1_stat; - - u32 unknown_13; - - u32 rst2_en; /*0x320*/ - u32 rst2_dis; - u32 rst2_stat; - - u32 unknown_14; - - u32 rst3_en; /*0x330*/ - u32 rst3_dis; - u32 rst3_stat; - - u32 unknown_15; - - u32 rst8_en; /*0x340*/ - u32 rst8_dis; - u32 rst8_stat; - - u32 unknown_16[45]; - - u32 clk0_sel; /*0x400*/ - - u32 unknown_17[36]; - - u32 clkcfg8bit1; /*0x494*/ - u32 clkcfg8bit2; - - u32 unknown_18[538]; - - u32 reserved8_addr; /*0xd04*/ -}; - - -/* CTRL1 bit definitions */ - -#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) -#define PERI_CTRL1_HIFI_INT_MASK (1 << 1) -#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) -#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) -#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) -#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) - - -/* CTRL2 bit definitions */ - -#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) -#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) -#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) -#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) -#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) -#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) -#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) -#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) -#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) -#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) -#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) -#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) -#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) -#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) - -/* CTRL3 bit definitions */ - -#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) -#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) -#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) - -/* CTRL4 bit definitions */ - -#define PERI_CTRL4_PICO_FSELV (1 << 0) -#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) -#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) -#define PERI_CTRL4_PICO_SIDDQ (1 << 6) -#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) -#define PERI_CTRL4_PICO_OGDISABLE (1 << 8) -#define PERI_CTRL4_PICO_COMMONONN (1 << 9) -#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) -#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) -#define PERI_CTRL4_PICO_VATESTENB (1 << 12) -#define PERI_CTRL4_PICO_SUSPENDM (1 << 14) -#define PERI_CTRL4_PICO_SLEEPM (1 << 15) -#define PERI_CTRL4_BC11_C (1 << 16) -#define PERI_CTRL4_BC11_B (1 << 17) -#define PERI_CTRL4_BC11_A (1 << 18) -#define PERI_CTRL4_BC11_GND (1 << 19) -#define PERI_CTRL4_BC11_FLOAT (1 << 20) -#define PERI_CTRL4_OTG_PHY_SEL (1 << 21) -#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) -#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) -#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) -#define PERI_CTRL4_OTG_IDPULLUP (1 << 26) -#define PERI_CTRL4_OTG_DRVBUS (1 << 27) -#define PERI_CTRL4_OTG_SESSEND (1 << 28) -#define PERI_CTRL4_OTG_BVALID (1 << 29) -#define PERI_CTRL4_OTG_AVALID (1 << 30) -#define PERI_CTRL4_OTG_VBUSVALID (1 << 31) - -/* CTRL5 bit definitions */ - -#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) -#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) -#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) -#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) -#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) -#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) -#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) -#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) -#define PERI_CTRL5_DBG_MUX (1 << 11) - -/* CTRL6 bit definitions */ - -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) - -/* CTRL8 bit definitions */ - -#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) -#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) -#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) -#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) -#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) -#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) -#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) -#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) -#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) -#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) - -/* CTRL9 bit definitions */ - -#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) -#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) -#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) -#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) - -/* CLK0 EN/DIS/STAT bit definitions */ - -#define PERI_CLK0_MMC0 (1 << 0) -#define PERI_CLK0_MMC1 (1 << 1) -#define PERI_CLK0_MMC2 (1 << 2) -#define PERI_CLK0_NANDC (1 << 3) -#define PERI_CLK0_USBOTG (1 << 4) -#define PERI_CLK0_PICOPHY (1 << 5) -#define PERI_CLK0_PLL (1 << 6) - -/* CLK1 EN/DIS/STAT bit definitions */ - -#define PERI_CLK1_HIFI (1 << 0) -#define PERI_CLK1_DIGACODEC (1 << 5) - -/* CLK2 EN/DIS/STAT bit definitions */ - -#define PERI_CLK2_IPF (1 << 0) -#define PERI_CLK2_SOCP (1 << 1) -#define PERI_CLK2_DMAC (1 << 2) -#define PERI_CLK2_SECENG (1 << 3) -#define PERI_CLK2_HPM0 (1 << 5) -#define PERI_CLK2_HPM1 (1 << 6) -#define PERI_CLK2_HPM2 (1 << 7) -#define PERI_CLK2_HPM3 (1 << 8) - -/* CLK8 EN/DIS/STAT bit definitions */ - -#define PERI_CLK8_RS0 (1 << 0) -#define PERI_CLK8_RS2 (1 << 1) -#define PERI_CLK8_RS3 (1 << 2) -#define PERI_CLK8_MS0 (1 << 3) -#define PERI_CLK8_MS2 (1 << 5) -#define PERI_CLK8_XG2RAM0 (1 << 6) -#define PERI_CLK8_X2SRAM (1 << 7) -#define PERI_CLK8_SRAM (1 << 8) -#define PERI_CLK8_ROM (1 << 9) -#define PERI_CLK8_HARQ (1 << 10) -#define PERI_CLK8_MMU (1 << 11) -#define PERI_CLK8_DDRC (1 << 12) -#define PERI_CLK8_DDRPHY (1 << 13) -#define PERI_CLK8_DDRPHY_REF (1 << 14) -#define PERI_CLK8_X2X_SYSNOC (1 << 15) -#define PERI_CLK8_X2X_CCPU (1 << 16) -#define PERI_CLK8_DDRT (1 << 17) -#define PERI_CLK8_DDRPACK_RS (1 << 18) - -/* CLK9 EN/DIS/STAT bit definitions */ - -#define PERI_CLK9_CARM_DAP (1 << 0) -#define PERI_CLK9_CARM_ATB (1 << 1) -#define PERI_CLK9_CARM_LBUS (1 << 2) -#define PERI_CLK9_CARM_KERNEL (1 << 3) - -/* CLK10 EN/DIS/STAT bit definitions */ - -#define PERI_CLK10_IPF_CCPU (1 << 0) -#define PERI_CLK10_SOCP_CCPU (1 << 1) -#define PERI_CLK10_SECENG_CCPU (1 << 2) -#define PERI_CLK10_HARQ_CCPU (1 << 3) -#define PERI_CLK10_IPF_MCU (1 << 16) -#define PERI_CLK10_SOCP_MCU (1 << 17) -#define PERI_CLK10_SECENG_MCU (1 << 18) -#define PERI_CLK10_HARQ_MCU (1 << 19) - -/* CLK12 EN/DIS/STAT bit definitions */ - -#define PERI_CLK12_HIFI_SRC (1 << 0) -#define PERI_CLK12_MMC0_SRC (1 << 1) -#define PERI_CLK12_MMC1_SRC (1 << 2) -#define PERI_CLK12_MMC2_SRC (1 << 3) -#define PERI_CLK12_SYSPLL_DIV (1 << 4) -#define PERI_CLK12_TPIU_SRC (1 << 5) -#define PERI_CLK12_MMC0_HF (1 << 6) -#define PERI_CLK12_MMC1_HF (1 << 7) -#define PERI_CLK12_PLL_TEST_SRC (1 << 8) -#define PERI_CLK12_CODEC_SOC (1 << 9) -#define PERI_CLK12_MEDIA (1 << 10) - -/* RST0 EN/DIS/STAT bit definitions */ - -#define PERI_RST0_MMC0 (1 << 0) -#define PERI_RST0_MMC1 (1 << 1) -#define PERI_RST0_MMC2 (1 << 2) -#define PERI_RST0_NANDC (1 << 3) -#define PERI_RST0_USBOTG_BUS (1 << 4) -#define PERI_RST0_POR_PICOPHY (1 << 5) -#define PERI_RST0_USBOTG (1 << 6) -#define PERI_RST0_USBOTG_32K (1 << 7) - -/* RST1 EN/DIS/STAT bit definitions */ - -#define PERI_RST1_HIFI (1 << 0) -#define PERI_RST1_DIGACODEC (1 << 5) - -/* RST2 EN/DIS/STAT bit definitions */ - -#define PERI_RST2_IPF (1 << 0) -#define PERI_RST2_SOCP (1 << 1) -#define PERI_RST2_DMAC (1 << 2) -#define PERI_RST2_SECENG (1 << 3) -#define PERI_RST2_ABB (1 << 4) -#define PERI_RST2_HPM0 (1 << 5) -#define PERI_RST2_HPM1 (1 << 6) -#define PERI_RST2_HPM2 (1 << 7) -#define PERI_RST2_HPM3 (1 << 8) - -/* RST3 EN/DIS/STAT bit definitions */ - -#define PERI_RST3_CSSYS (1 << 0) -#define PERI_RST3_I2C0 (1 << 1) -#define PERI_RST3_I2C1 (1 << 2) -#define PERI_RST3_I2C2 (1 << 3) -#define PERI_RST3_I2C3 (1 << 4) -#define PERI_RST3_UART1 (1 << 5) -#define PERI_RST3_UART2 (1 << 6) -#define PERI_RST3_UART3 (1 << 7) -#define PERI_RST3_UART4 (1 << 8) -#define PERI_RST3_SSP (1 << 9) -#define PERI_RST3_PWM (1 << 10) -#define PERI_RST3_BLPWM (1 << 11) -#define PERI_RST3_TSENSOR (1 << 12) -#define PERI_RST3_DAPB (1 << 18) -#define PERI_RST3_HKADC (1 << 19) -#define PERI_RST3_CODEC (1 << 20) - -/* RST8 EN/DIS/STAT bit definitions */ - -#define PERI_RST8_RS0 (1 << 0) -#define PERI_RST8_RS2 (1 << 1) -#define PERI_RST8_RS3 (1 << 2) -#define PERI_RST8_MS0 (1 << 3) -#define PERI_RST8_MS2 (1 << 5) -#define PERI_RST8_XG2RAM0 (1 << 6) -#define PERI_RST8_X2SRAM_TZMA (1 << 7) -#define PERI_RST8_SRAM (1 << 8) -#define PERI_RST8_HARQ (1 << 10) -#define PERI_RST8_DDRC (1 << 12) -#define PERI_RST8_DDRC_APB (1 << 13) -#define PERI_RST8_DDRPACK_APB (1 << 14) -#define PERI_RST8_DDRT (1 << 17) - -#endif /*__HI62220_H__*/ diff --git a/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h deleted file mode 100644 index 4b9a0d4..0000000 --- a/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h +++ /dev/null @@ -1,419 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __HI6220_ALWAYSON_H__ -#define __HI6220_ALWAYSON_H__ - -#define ALWAYSON_CTRL_BASE 0xF7800000 - -struct alwayson_sc_regs { - u32 ctrl0; /*0x0*/ - u32 ctrl1; - u32 ctrl2; - - u32 unknown; - - u32 stat0; /*0x10*/ - u32 stat1; - u32 mcu_imctrl; - u32 mcu_imstat; - - u32 unknown_1[9]; - - u32 secondary_int_en0; /*0x44*/ - u32 secondary_int_statr0; - u32 secondary_int_statm0; - - u32 unknown_2; - - u32 mcu_wkup_int_en6; /*0x54*/ - u32 mcu_wkup_int_statr6; - u32 mcu_wkup_int_statm6; - - u32 unknown_3; - - u32 mcu_wkup_int_en5; /*0x64*/ - u32 mcu_wkup_int_statr5; - u32 mcu_wkup_int_statm5; - - u32 unknown_4[9]; - - u32 mcu_wkup_int_en4; /*0x94*/ - u32 mcu_wkup_int_statr4; - u32 mcu_wkup_int_statm4; - - u32 unknown_5[2]; - - u32 mcu_wkup_int_en0; /*0xa8*/ - u32 mcu_wkup_int_statr0; - u32 mcu_wkup_int_statm0; - - u32 mcu_wkup_int_en1; /*0xb4*/ - u32 mcu_wkup_int_statr1; - u32 mcu_wkup_int_statm1; - - u32 unknown_6; - - u32 int_statr; /*0xc4*/ - u32 int_statm; - u32 int_clear; - - u32 int_en_set; /*0xd0*/ - u32 int_en_dis; - u32 int_en_stat; - - u32 unknown_7[2]; - - u32 int_statr1; /*0xc4*/ - u32 int_statm1; - u32 int_clear1; - - u32 int_en_set1; /*0xf0*/ - u32 int_en_dis1; - u32 int_en_stat1; - - u32 unknown_8[53]; - - u32 timer_en0; /*0x1d0*/ - u32 timer_en1; - - u32 unknown_9[6]; - - u32 timer_en4; /*0x1f0*/ - u32 timer_en5; - - u32 unknown_10[130]; - - u32 mcu_subsys_ctrl0; /*0x400*/ - u32 mcu_subsys_ctrl1; - u32 mcu_subsys_ctrl2; - u32 mcu_subsys_ctrl3; - u32 mcu_subsys_ctrl4; - u32 mcu_subsys_ctrl5; - u32 mcu_subsys_ctrl6; - u32 mcu_subsys_ctrl7; - - u32 unknown_10_1[8]; - - u32 mcu_subsys_stat0; /*0x440*/ - u32 mcu_subsys_stat1; - u32 mcu_subsys_stat2; - u32 mcu_subsys_stat3; - u32 mcu_subsys_stat4; - u32 mcu_subsys_stat5; - u32 mcu_subsys_stat6; - u32 mcu_subsys_stat7; - - u32 unknown_11[116]; - - u32 clk4_en; /*0x630*/ - u32 clk4_dis; - u32 clk4_stat; - - u32 clk5_en; /*0x63c*/ - u32 clk5_dis; - u32 clk5_stat; - - u32 unknown_12[42]; - - u32 rst4_en; /*0x6f0*/ - u32 rst4_dis; - u32 rst4_stat; - - u32 rst5_en; /*0x6fc*/ - u32 rst5_dis; - u32 rst5_stat; - - u32 unknown_13[62]; - - u32 pw_clk0_en; /*0x800*/ - u32 pw_clk0_dis; - u32 pw_clk0_stat; - - u32 unknown_13_1; - - u32 pw_rst0_en; /*0x810*/ - u32 pw_rst0_dis; - u32 pw_rst0_stat; - - u32 unknown_14; - - u32 pw_isoen0; /*0x820*/ - u32 pw_isodis0; - u32 pw_iso_stat0; - - u32 unknown_14_1; - - u32 pw_mtcmos_en0; /*0x830*/ - u32 pw_mtcmos_dis0; - u32 pw_mtcmos_stat0; - u32 pw_mtcmos_ack_stat0; - u32 pw_mtcmos_timeout_stat0; - - u32 unknown_14_2[3]; - - u32 pw_stat0; /*0x850*/ - u32 pw_stat1; - - u32 unknown_15[10]; - - u32 systest_stat; /*0x880*/ - - u32 unknown_16[3]; - - u32 systest_slicer_cnt0;/*0x890*/ - u32 systest_slicer_cnt1; - - u32 unknown_17[12]; - - u32 pw_ctrl1; /*0x8C8*/ - u32 pw_ctrl; - - u32 mcpu_voteen; - u32 mcpu_votedis; - u32 mcpu_votestat; - - u32 unknown_17_1; - - u32 mcpu_vote_msk0; /*0x8E0*/ - u32 mcpu_vote_msk1; - u32 mcpu_votestat0_msk; - u32 mcpu_votestat1_msk; - - u32 peri_voteen; /*0x8F0*/ - u32 peri_votedis; - u32 peri_votestat; - - u32 unknown_17_2; - - u32 peri_vote_msk0; /*0x900*/ - u32 peri_vote_msk1; - u32 peri_votestat0_msk; - u32 erpi_votestat1_msk; - u32 acpu_voteen; - u32 acpu_votedis; - u32 acpu_votestat; - - u32 unknown_18; - - u32 acpu_vote_msk0; /*0x920*/ - u32 acpu_vote_msk1; - u32 acpu_votestat0_msk; - u32 acpu_votestat1_msk; - u32 mcu_voteen; - u32 mcu_votedis; - u32 mcu_votestat; - - u32 unknown_18_1; - - u32 mcu_vote_msk0; /*0x940*/ - u32 mcu_vote_msk1; - u32 mcu_vote_votestat0_msk; - u32 mcu_vote_votestat1_msk; - - u32 unknown_18_1_2[4]; - - u32 mcu_vote_vote1en; /*0x960*/ - u32 mcu_vote_vote1dis; - u32 mcu_vote_vote1stat; - - u32 unknown_18_2; - - u32 mcu_vote_vote1_msk0;/*0x970*/ - u32 mcu_vote_vote1_msk1; - u32 mcu_vote_vote1stat0_msk; - u32 mcu_vote_vote1stat1_msk; - u32 mcu_vote_vote2en; - u32 mcu_vote_vote2dis; - u32 mcu_vote_vote2stat; - - u32 unknown_18_3; - - u32 mcu_vote2_msk0; /*0x990*/ - u32 mcu_vote2_msk1; - u32 mcu_vote2stat0_msk; - u32 mcu_vote2stat1_msk; - u32 vote_ctrl; - u32 vote_stat; /*0x9a4*/ - - u32 unknown_19[342]; - - u32 econum; /*0xf00*/ - - u32 unknown_20_1[3]; - - u32 scchipid; /*0xf10*/ - - u32 unknown_20_2[2]; - - u32 scsocid; /*0xf1c*/ - - u32 unknown_20[48]; - - u32 soc_fpga_rtl_def; /*0xfe0*/ - u32 soc_fpga_pr_def; - u32 soc_fpga_res_def0; - u32 soc_fpga_res_def1; /*0xfec*/ -}; - -/* ctrl0 bit definitions */ - -#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004 -#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007 - -/* ctrl1 bit definitions */ - -#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0) -#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1) -#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2) -#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3) -#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13) -#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15) -#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16) -#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17) -#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18) -#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19) -#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29) -#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31) - -/* ctrl2 bit definitions */ - -#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26) -#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27) -#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28) -#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29) -#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30) -#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31) - -/* stat0 bit definitions */ - -#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25) -#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26) -#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27) -#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28) -#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29) -#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30) -#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31) - -/* stat1 bit definitions */ - -#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0) -#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16) -#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17) -#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19) -#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20) -#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27) -#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28) -#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29) - -/* ctrl3 bit definitions */ - -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11) - -/* clk4_en bit definitions */ - -#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7) -#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8) -#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31) - -/* clk5_en bit definitions */ - -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0) -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3) -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16) -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19) - -/* rst4_dis bit definitions */ - -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7) -#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8) -#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29) -#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30) - -#define PCLK_TIMER1 (1 << 16) -#define PCLK_TIMER0 (1 << 15) - -#endif /* __HI6220_ALWAYSON_H__ */ diff --git a/arch/arm/include/asm/arch-hi6220/periph.h b/arch/arm/include/asm/arch-hi6220/periph.h deleted file mode 100644 index edec213..0000000 --- a/arch/arm/include/asm/arch-hi6220/periph.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - PERIPH_ID_UART0 = 36, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_SDMMC0 = 72, - PERIPH_ID_SDMMC1, - - PERIPH_ID_NONE = -1, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-hi6220/pinmux.h b/arch/arm/include/asm/arch-hi6220/pinmux.h deleted file mode 100644 index b4a9957..0000000 --- a/arch/arm/include/asm/arch-hi6220/pinmux.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __ASM_ARM_ARCH_PINMUX_H -#define __ASM_ARM_ARCH_PINMUX_H - -#include "periph.h" - - -/* iomg bit definition */ -#define MUX_M0 0 -#define MUX_M1 1 -#define MUX_M2 2 -#define MUX_M3 3 -#define MUX_M4 4 -#define MUX_M5 5 -#define MUX_M6 6 -#define MUX_M7 7 - -/* iocg bit definition */ -#define PULL_MASK (3) -#define PULL_DIS (0) -#define PULL_UP (1 << 0) -#define PULL_DOWN (1 << 1) - -/* drive strength definition */ -#define DRIVE_MASK (7 << 4) -#define DRIVE1_02MA (0 << 4) -#define DRIVE1_04MA (1 << 4) -#define DRIVE1_08MA (2 << 4) -#define DRIVE1_10MA (3 << 4) -#define DRIVE2_02MA (0 << 4) -#define DRIVE2_04MA (1 << 4) -#define DRIVE2_08MA (2 << 4) -#define DRIVE2_10MA (3 << 4) -#define DRIVE3_04MA (0 << 4) -#define DRIVE3_08MA (1 << 4) -#define DRIVE3_12MA (2 << 4) -#define DRIVE3_16MA (3 << 4) -#define DRIVE3_20MA (4 << 4) -#define DRIVE3_24MA (5 << 4) -#define DRIVE3_32MA (6 << 4) -#define DRIVE3_40MA (7 << 4) -#define DRIVE4_02MA (0 << 4) -#define DRIVE4_04MA (2 << 4) -#define DRIVE4_08MA (4 << 4) -#define DRIVE4_10MA (6 << 4) - -#define HI6220_PINMUX0_BASE 0xf7010000 -#define HI6220_PINMUX1_BASE 0xf7010800 - -#ifndef __ASSEMBLY__ - -/* maybe more registers, but highest used is 123 */ -#define REG_NUM 123 - -struct hi6220_pinmux0_regs { - uint32_t iomg[REG_NUM]; -}; - -struct hi6220_pinmux1_regs { - uint32_t iocfg[REG_NUM]; -}; - -#endif - -/** - * Configures the pinmux for a particular peripheral. - * - * This function will configure the peripheral pinmux along with - * pull-up/down and drive strength. - * - * @param peripheral peripheral to be configured - * @return 0 if ok, -1 on error (e.g. unsupported peripheral) - */ -int hi6220_pinmux_config(int peripheral); - -#endif diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h deleted file mode 100644 index 3a85492..0000000 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Freescale Semiconductor, Inc. - */ - -#define MXC_CPU_MX23 0x23 -#define MXC_CPU_MX25 0x25 -#define MXC_CPU_MX27 0x27 -#define MXC_CPU_MX28 0x28 -#define MXC_CPU_MX31 0x31 -#define MXC_CPU_MX35 0x35 -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SX 0x62 -#define MXC_CPU_MX6Q 0x63 -#define MXC_CPU_MX6UL 0x64 -#define MXC_CPU_MX6ULL 0x65 -#define MXC_CPU_MX6ULZ 0x6B -#define MXC_CPU_MX6SOLO 0x66 /* dummy */ -#define MXC_CPU_MX6SLL 0x67 -#define MXC_CPU_MX6D 0x6A -#define MXC_CPU_MX6DP 0x68 -#define MXC_CPU_MX6QP 0x69 -#define MXC_CPU_MX7S 0x71 /* dummy ID */ -#define MXC_CPU_MX7D 0x72 -#define MXC_CPU_IMX8MQ 0x82 -#define MXC_CPU_IMX8MM 0x85 /* dummy ID */ -#define MXC_CPU_IMX8MML 0x86 /* dummy ID */ -#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ -#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */ -#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ -#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ -#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ -#define MXC_CPU_IMX8QM 0x91 /* dummy ID */ -#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ -#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ -#define MXC_CPU_VF610 0xF6 /* dummy ID */ - -#define MXC_SOC_MX6 0x60 -#define MXC_SOC_MX7 0x70 -#define MXC_SOC_IMX8M 0x80 -#define MXC_SOC_IMX8 0x90 /* dummy */ -#define MXC_SOC_MX7ULP 0xE0 /* dummy */ - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_1_2 0x12 -#define CHIP_REV_1_5 0x15 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_1 0x21 -#define CHIP_REV_2_5 0x25 -#define CHIP_REV_3_0 0x30 - -#define CHIP_REV_A 0x0 -#define CHIP_REV_B 0x1 - -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 -#define BOARD_VER_OFFSET 0x8 - -#define CS0_128 0 -#define CS0_64M_CS1_64M 1 -#define CS0_64M_CS1_32M_CS2_32M 2 -#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 - -u32 get_imx_reset_cause(void); -ulong get_systemPLLCLK(void); -ulong get_FCLK(void); -ulong get_HCLK(void); -ulong get_BCLK(void); -ulong get_PERCLK1(void); -ulong get_PERCLK2(void); -ulong get_PERCLK3(void); diff --git a/arch/arm/include/asm/arch-imx8/boot0.h b/arch/arm/include/asm/arch-imx8/boot0.h deleted file mode 100644 index 5ce781a..0000000 --- a/arch/arm/include/asm/arch-imx8/boot0.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#if defined(CONFIG_SPL_BUILD) - /* - * We use absolute address not PC relative address to jump. - * When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000, - * our linker address for SPL is from 0x100000. So using absolute address can jump to - * the OCRAM address from the alias. - * The alias only map first 96KB of OCRAM, so this require the SPL size can't beyond 96KB. - * But when using SPL DM, the size increase significantly and may exceed 96KB. - * That's why we have to jump to OCRAM. - */ - - ldr x0, =reset - br x0 -#else - b reset -#endif diff --git a/arch/arm/include/asm/arch-imx8/clock.h b/arch/arm/include/asm/arch-imx8/clock.h deleted file mode 100644 index bea1571..0000000 --- a/arch/arm/include/asm/arch-imx8/clock.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __ASM_ARCH_IMX8_CLOCK_H__ -#define __ASM_ARCH_IMX8_CLOCK_H__ - -/* Mainly for compatible to imx common code. */ -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_AXI_CLK, - MXC_DDR_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_I2C_CLK, - MXC_FEC_CLK, -}; - -u32 mxc_get_clock(enum mxc_clock clk); - -#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/gpio.h b/arch/arm/include/asm/arch-imx8/gpio.h deleted file mode 100644 index 24cfde3..0000000 --- a/arch/arm/include/asm/arch-imx8/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __ASM_ARCH_IMX8_GPIO_H -#define __ASM_ARCH_IMX8_GPIO_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; /* data */ - u32 gpio_dir; /* direction */ - u32 gpio_psr; /* pad satus */ -}; -#endif - -/* IMX8 the GPIO index is from 0 not 1 */ -#define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31)) - -#endif /* __ASM_ARCH_IMX8_GPIO_H */ diff --git a/arch/arm/include/asm/arch-imx8/image.h b/arch/arm/include/asm/arch-imx8/image.h deleted file mode 100644 index c1e5700..0000000 --- a/arch/arm/include/asm/arch-imx8/image.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __CONTAINER_HEADER_H_ -#define __CONTAINER_HEADER_H_ - -#include <linux/sizes.h> -#include <linux/types.h> - -#define IV_MAX_LEN 32 -#define HASH_MAX_LEN 64 - -#define CONTAINER_HDR_ALIGNMENT 0x400 -#define CONTAINER_HDR_EMMC_OFFSET 0 -#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K -#define CONTAINER_HDR_QSPI_OFFSET SZ_4K -#define CONTAINER_HDR_NAND_OFFSET SZ_128M - -struct container_hdr { - u8 version; - u8 length_lsb; - u8 length_msb; - u8 tag; - u32 flags; - u16 sw_version; - u8 fuse_version; - u8 num_images; - u16 sig_blk_offset; - u16 reserved; -} __packed; - -struct boot_img_t { - u32 offset; - u32 size; - u64 dst; - u64 entry; - u32 hab_flags; - u32 meta; - u8 hash[HASH_MAX_LEN]; - u8 iv[IV_MAX_LEN]; -} __packed; - -struct signature_block_hdr { - u8 version; - u8 length_lsb; - u8 length_msb; - u8 tag; - u16 srk_table_offset; - u16 cert_offset; - u16 blob_offset; - u16 signature_offset; - u32 reserved; -} __packed; -#endif diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h deleted file mode 100644 index 6333ff4..0000000 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __ASM_ARCH_IMX8_REGS_H__ -#define __ASM_ARCH_IMX8_REGS_H__ - -#define ARCH_MXC - -#define LPUART_BASE 0x5A060000 - -#define GPT1_BASE_ADDR 0x5D140000 -#define SCU_LPUART_BASE 0x33220000 -#define GPIO1_BASE_ADDR 0x5D080000 -#define GPIO2_BASE_ADDR 0x5D090000 -#define GPIO3_BASE_ADDR 0x5D0A0000 -#define GPIO4_BASE_ADDR 0x5D0B0000 -#define GPIO5_BASE_ADDR 0x5D0C0000 -#define GPIO6_BASE_ADDR 0x5D0D0000 -#define GPIO7_BASE_ADDR 0x5D0E0000 -#define GPIO8_BASE_ADDR 0x5D0F0000 -#define LPI2C1_BASE_ADDR 0x5A800000 -#define LPI2C2_BASE_ADDR 0x5A810000 -#define LPI2C3_BASE_ADDR 0x5A820000 -#define LPI2C4_BASE_ADDR 0x5A830000 -#define LPI2C5_BASE_ADDR 0x5A840000 - -#ifdef CONFIG_IMX8QXP -#define LVDS0_PHYCTRL_BASE 0x56221000 -#define LVDS1_PHYCTRL_BASE 0x56241000 -#define MIPI0_SS_BASE 0x56220000 -#define MIPI1_SS_BASE 0x56240000 -#endif - -#define APBH_DMA_ARB_BASE_ADDR 0x5B810000 -#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR - -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) - -#define PASS_OVER_INFO_ADDR 0x0010fe00 - -#define USB_BASE_ADDR 0x5b0d0000 -#define USB_PHY0_BASE_ADDR 0x5b100000 - -#endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h deleted file mode 100644 index 2130298..0000000 --- a/arch/arm/include/asm/arch-imx8/imx8-pins.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __ASM_ARCH_IMX8_PINS_H__ -#define __ASM_ARCH_IMX8_PINS_H__ - -#if defined(CONFIG_IMX8QXP) -#include <dt-bindings/pinctrl/pads-imx8qxp.h> -#elif defined(CONFIG_IMX8QM) -#include <dt-bindings/pinctrl/pads-imx8qm.h> -#else -#error "No pin header" -#endif - -#endif /* __ASM_ARCH_IMX8_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/iomux.h b/arch/arm/include/asm/arch-imx8/iomux.h deleted file mode 100644 index bedd01b..0000000 --- a/arch/arm/include/asm/arch-imx8/iomux.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __ASM_ARCH_IMX8_IOMUX_H__ -#define __ASM_ARCH_IMX8_IOMUX_H__ - -/* - * We use 64bits value for iomux settings. - * High 32bits are used for padring register value, - * low 16bits are used for pin index. - */ -typedef u64 iomux_cfg_t; - -#define PADRING_IFMUX_EN_SHIFT 31 -#define PADRING_IFMUX_EN_MASK BIT(31) -#define PADRING_GP_EN_SHIFT 30 -#define PADRING_GP_EN_MASK BIT(30) -#define PADRING_IFMUX_SHIFT 27 -#define PADRING_IFMUX_MASK GENMASK(29, 27) -#define PADRING_CONFIG_SHIFT 25 -#define PADRING_LPCONFIG_SHIFT 23 -#define PADRING_PULL_SHIFT 5 -#define PADRING_DSE_SHIFT 0 - -#define MUX_PAD_CTRL_SHIFT 32 -#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT) -#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) -#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT) -#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT) -#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF) - -/* Valid mux alt0 to alt7 */ -#define MUX_MODE_ALT(x) (((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \ - MUX_MODE_MASK) - -void imx8_iomux_setup_pad(iomux_cfg_t pad); -void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count); -#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h deleted file mode 100644 index 1396008..0000000 --- a/arch/arm/include/asm/arch-imx8/power-domain.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017 NXP - */ - -#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H -#define _ASM_ARCH_IMX8_POWER_DOMAIN_H - -#include <asm/arch/sci/types.h> - -struct imx8_power_domain_platdata { - sc_rsrc_t resource_id; -}; - -#endif diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h deleted file mode 100644 index 8e1e9bb..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017-2018 NXP - * - */ - -#ifndef SC_RPC_H -#define SC_RPC_H - -/* Note: Check SCFW API Released DOC before you want to modify something */ -#define SC_RPC_VERSION 1U - -#define SC_RPC_MAX_MSG 8U - -#define RPC_VER(MSG) ((MSG)->version) -#define RPC_SIZE(MSG) ((MSG)->size) -#define RPC_SVC(MSG) ((MSG)->svc) -#define RPC_FUNC(MSG) ((MSG)->func) -#define RPC_R8(MSG) ((MSG)->func) -#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) -#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) -#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) -#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) -#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) -#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) - -#define SC_RPC_SVC_UNKNOWN 0U -#define SC_RPC_SVC_RETURN 1U -#define SC_RPC_SVC_PM 2U -#define SC_RPC_SVC_RM 3U -#define SC_RPC_SVC_TIMER 5U -#define SC_RPC_SVC_PAD 6U -#define SC_RPC_SVC_MISC 7U -#define SC_RPC_SVC_IRQ 8U -#define SC_RPC_SVC_SECO 9U -#define SC_RPC_SVC_ABORT 10U - - -/* Types */ - -struct sc_rpc_msg_s { - u8 version; - u8 size; - u8 svc; - u8 func; - union { - s32 i32[(SC_RPC_MAX_MSG - 1U)]; - s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U]; - s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U]; - u32 u32[(SC_RPC_MAX_MSG - 1U)]; - u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U]; - u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U]; - } DATA; -}; - -/* PM RPC */ -#define PM_FUNC_UNKNOWN 0 -#define PM_FUNC_SET_SYS_POWER_MODE 19U -#define PM_FUNC_SET_PARTITION_POWER_MODE 1U -#define PM_FUNC_GET_SYS_POWER_MODE 2U -#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U -#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U -#define PM_FUNC_REQ_LOW_POWER_MODE 16U -#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U -#define PM_FUNC_SET_CPU_RESUME_ADDR 17U -#define PM_FUNC_SET_CPU_RESUME 21U -#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U -#define PM_FUNC_SET_CLOCK_RATE 5U -#define PM_FUNC_GET_CLOCK_RATE 6U -#define PM_FUNC_CLOCK_ENABLE 7U -#define PM_FUNC_SET_CLOCK_PARENT 14U -#define PM_FUNC_GET_CLOCK_PARENT 15U -#define PM_FUNC_RESET 13U -#define PM_FUNC_RESET_REASON 10U -#define PM_FUNC_BOOT 8U -#define PM_FUNC_REBOOT 9U -#define PM_FUNC_REBOOT_PARTITION 12U -#define PM_FUNC_CPU_START 11U -#define PM_FUNC_IS_PARTITION_STARTED 24U - -/* MISC RPC */ -#define MISC_FUNC_UNKNOWN 0 -#define MISC_FUNC_SET_CONTROL 1U -#define MISC_FUNC_GET_CONTROL 2U -#define MISC_FUNC_SET_MAX_DMA_GROUP 4U -#define MISC_FUNC_SET_DMA_GROUP 5U -#define MISC_FUNC_SECO_IMAGE_LOAD 8U -#define MISC_FUNC_SECO_AUTHENTICATE 9U -#define MISC_FUNC_SECO_FUSE_WRITE 20U -#define MISC_FUNC_SECO_ENABLE_DEBUG 21U -#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U -#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U -#define MISC_FUNC_SECO_BUILD_INFO 24U -#define MISC_FUNC_DEBUG_OUT 10U -#define MISC_FUNC_WAVEFORM_CAPTURE 6U -#define MISC_FUNC_BUILD_INFO 15U -#define MISC_FUNC_UNIQUE_ID 19U -#define MISC_FUNC_SET_ARI 3U -#define MISC_FUNC_BOOT_STATUS 7U -#define MISC_FUNC_BOOT_DONE 14U -#define MISC_FUNC_OTP_FUSE_READ 11U -#define MISC_FUNC_OTP_FUSE_WRITE 17U -#define MISC_FUNC_SET_TEMP 12U -#define MISC_FUNC_GET_TEMP 13U -#define MISC_FUNC_GET_BOOT_DEV 16U -#define MISC_FUNC_GET_BUTTON_STATUS 18U - -/* PAD RPC */ -#define PAD_FUNC_UNKNOWN 0 -#define PAD_FUNC_SET_MUX 1U -#define PAD_FUNC_GET_MUX 6U -#define PAD_FUNC_SET_GP 2U -#define PAD_FUNC_GET_GP 7U -#define PAD_FUNC_SET_WAKEUP 4U -#define PAD_FUNC_GET_WAKEUP 9U -#define PAD_FUNC_SET_ALL 5U -#define PAD_FUNC_GET_ALL 10U -#define PAD_FUNC_SET 15U -#define PAD_FUNC_GET 16U -#define PAD_FUNC_SET_GP_28FDSOI 11U -#define PAD_FUNC_GET_GP_28FDSOI 12U -#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U -#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U -#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U -#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U - -/* RM RPC */ -#define RM_FUNC_UNKNOWN 0 -#define RM_FUNC_PARTITION_ALLOC 1U -#define RM_FUNC_SET_CONFIDENTIAL 31U -#define RM_FUNC_PARTITION_FREE 2U -#define RM_FUNC_GET_DID 26U -#define RM_FUNC_PARTITION_STATIC 3U -#define RM_FUNC_PARTITION_LOCK 4U -#define RM_FUNC_GET_PARTITION 5U -#define RM_FUNC_SET_PARENT 6U -#define RM_FUNC_MOVE_ALL 7U -#define RM_FUNC_ASSIGN_RESOURCE 8U -#define RM_FUNC_SET_RESOURCE_MOVABLE 9U -#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U -#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U -#define RM_FUNC_SET_MASTER_SID 11U -#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U -#define RM_FUNC_IS_RESOURCE_OWNED 13U -#define RM_FUNC_GET_RESOURCE_OWNER 33U -#define RM_FUNC_IS_RESOURCE_MASTER 14U -#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U -#define RM_FUNC_GET_RESOURCE_INFO 16U -#define RM_FUNC_MEMREG_ALLOC 17U -#define RM_FUNC_MEMREG_SPLIT 29U -#define RM_FUNC_MEMREG_FREE 18U -#define RM_FUNC_FIND_MEMREG 30U -#define RM_FUNC_ASSIGN_MEMREG 19U -#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U -#define RM_FUNC_IS_MEMREG_OWNED 21U -#define RM_FUNC_GET_MEMREG_INFO 22U -#define RM_FUNC_ASSIGN_PAD 23U -#define RM_FUNC_SET_PAD_MOVABLE 24U -#define RM_FUNC_IS_PAD_OWNED 25U -#define RM_FUNC_DUMP 27U - -/* SECO RPC */ -#define SECO_FUNC_UNKNOWN 0 -#define SECO_FUNC_IMAGE_LOAD 1U -#define SECO_FUNC_AUTHENTICATE 2U -#define SECO_FUNC_FORWARD_LIFECYCLE 3U -#define SECO_FUNC_RETURN_LIFECYCLE 4U -#define SECO_FUNC_COMMIT 5U -#define SECO_FUNC_ATTEST_MODE 6U -#define SECO_FUNC_ATTEST 7U -#define SECO_FUNC_GET_ATTEST_PKEY 8U -#define SECO_FUNC_GET_ATTEST_SIGN 9U -#define SECO_FUNC_ATTEST_VERIFY 10U -#define SECO_FUNC_GEN_KEY_BLOB 11U -#define SECO_FUNC_LOAD_KEY 12U -#define SECO_FUNC_GET_MP_KEY 13U -#define SECO_FUNC_UPDATE_MPMR 14U -#define SECO_FUNC_GET_MP_SIGN 15U -#define SECO_FUNC_BUILD_INFO 16U -#define SECO_FUNC_CHIP_INFO 17U -#define SECO_FUNC_ENABLE_DEBUG 18U -#define SECO_FUNC_GET_EVENT 19U -#define SECO_FUNC_FUSE_WRITE 20U - -#endif /* SC_RPC_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h deleted file mode 100644 index 14ee6f9..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef _SC_SCI_H -#define _SC_SCI_H - -#include <asm/arch/sci/types.h> -#include <asm/arch/sci/svc/misc/api.h> -#include <asm/arch/sci/svc/pad/api.h> -#include <asm/arch/sci/svc/pm/api.h> -#include <asm/arch/sci/svc/rm/api.h> -#include <asm/arch/sci/svc/seco/api.h> -#include <asm/arch/sci/rpc.h> -#include <dt-bindings/soc/imx_rsrc.h> -#include <linux/errno.h> - -static inline int sc_err_to_linux(sc_err_t err) -{ - int ret; - - switch (err) { - case SC_ERR_NONE: - return 0; - case SC_ERR_VERSION: - case SC_ERR_CONFIG: - case SC_ERR_PARM: - ret = -EINVAL; - break; - case SC_ERR_NOACCESS: - case SC_ERR_LOCKED: - case SC_ERR_UNAVAILABLE: - ret = -EACCES; - break; - case SC_ERR_NOTFOUND: - case SC_ERR_NOPOWER: - ret = -ENODEV; - break; - case SC_ERR_IPC: - ret = -EIO; - break; - case SC_ERR_BUSY: - ret = -EBUSY; - break; - case SC_ERR_FAIL: - ret = -EIO; - break; - default: - ret = 0; - break; - } - - debug("%s %d %d\n", __func__, err, ret); - - return ret; -} - -/* PM API*/ -int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_power_mode_t mode); -int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_power_mode_t *mode); -int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, - sc_pm_clock_rate_t *rate); -int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, - sc_pm_clock_rate_t *rate); -int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, - sc_bool_t enable, sc_bool_t autog); -int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, - sc_pm_clk_parent_t parent); -int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, - sc_faddr_t address); -sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); - -/* MISC API */ -int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, - sc_ctrl_t ctrl, u32 val); -int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, - u32 *val); -void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); -void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); -void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); -int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); -int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, - s16 *celsius, s8 *tenths); - -/* RM API */ -sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); -int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, - sc_faddr_t addr_end); -int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, - sc_rm_pt_t pt, sc_rm_perm_t perm); -int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, - sc_faddr_t *addr_end); -sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); -int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, - sc_bool_t isolated, sc_bool_t restricted, - sc_bool_t grant, sc_bool_t coherent); -int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); -int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); -int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); -int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); -int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); -sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); -int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, - sc_rm_pt_t *pt); - -/* PAD API */ -int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); - -/* SMMU API */ -int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); - -/* SECO API */ -int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, - sc_faddr_t addr); -int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); -int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, - u32 *uid_h); -void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); -int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); -int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, - sc_faddr_t export_addr, u16 max_size); - -#endif diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h deleted file mode 100644 index 3629eb6..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef SC_MISC_API_H -#define SC_MISC_API_H - -/* Defines for sc_misc_boot_status_t */ -#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ -#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ - -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ - -/* Defines for sc_misc_temp_t */ -#define SC_MISC_TEMP 0U /* Temp sensor */ -#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ -#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ - -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ -#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ -#define SC_MISC_REL_CONTAINER 2U /* Release container */ - -typedef u8 sc_misc_boot_status_t; -typedef u8 sc_misc_temp_t; - -#endif /* SC_MISC_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h deleted file mode 100644 index 905c568..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef SC_PAD_API_H -#define SC_PAD_API_H - -/* Defines for sc_pad_config_t */ -#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ -#define SC_PAD_CONFIG_OD 1U /* Open Drain */ -#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ -#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ - -/* Defines for sc_pad_iso_t */ -#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ -#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ -#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ -#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ - -/* Defines for sc_pad_28fdsoi_dse_t */ -#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */ -#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength dual volt */ -#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength dual volt */ - -/* Defines for sc_pad_28fdsoi_ps_t */ -#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ -#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ -#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ -#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ - -/* Defines for sc_pad_28fdsoi_pus_t */ -#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ -#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ -#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ -#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ - -/* Defines for sc_pad_wakeup_t */ -#define SC_PAD_WAKEUP_OFF 0U /* Off */ -#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ -#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ -#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ -#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ -#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ - -#endif /* SC_PAD_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h deleted file mode 100644 index 9008b85..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef SC_PM_API_H -#define SC_PM_API_H - -/* Defines for sc_pm_power_mode_t */ -#define SC_PM_PW_MODE_OFF 0U /* Power off */ -#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ -#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ -#define SC_PM_PW_MODE_ON 3U /* Power on */ - -/* Defines for sc_pm_clk_t */ -#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ -#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ -#define SC_PM_CLK_PER 2U /* Peripheral clock */ -#define SC_PM_CLK_PHY 3U /* Phy clock */ -#define SC_PM_CLK_MISC 4U /* Misc clock */ -#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ -#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ -#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ -#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ -#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ -#define SC_PM_CLK_CPU 2U /* CPU clock */ -#define SC_PM_CLK_PLL 4U /* PLL */ -#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ - -/* Defines for sc_pm_clk_mode_t */ -#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ -#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ -#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ -#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ -#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ -#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ - -typedef u8 sc_pm_power_mode_t; -typedef u8 sc_pm_clk_t; -typedef u8 sc_pm_clk_mode_t; -typedef u8 sc_pm_clk_parent_t; -typedef u32 sc_pm_clock_rate_t; - -#endif /* SC_PM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h deleted file mode 100644 index ed30388..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef SC_RM_API_H -#define SC_RM_API_H - -#include <asm/arch/sci/types.h> - -/* Defines for type widths */ -#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ -#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ -#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ -#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ -#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ -#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ - -/* Defines for ALL parameters */ -#define SC_RM_PT_ALL ((sc_rm_pt_t)UINT8_MAX) /* All partitions */ -#define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */ - -/* Defines for sc_rm_spa_t */ -#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ -#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ -#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ -#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ - -/* Defines for sc_rm_perm_t */ -#define SC_RM_PERM_NONE 0U /* No access */ -#define SC_RM_PERM_SEC_R 1U /* Secure RO */ -#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ -#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ -#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ -#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ -#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ -#define SC_RM_PERM_FULL 7U /* Full access */ - -/* Types */ - -/*! - * This type is used to declare a resource partition. - */ -typedef u8 sc_rm_pt_t; - -/*! - * This type is used to declare a memory region. - */ -typedef u8 sc_rm_mr_t; - -/*! - * This type is used to declare a resource domain ID used by the - * isolation HW. - */ -typedef u8 sc_rm_did_t; - -/*! - * This type is used to declare an SMMU StreamID. - */ -typedef u16 sc_rm_sid_t; - -/*! - * This type is a used to declare master transaction attributes. - */ -typedef u8 sc_rm_spa_t; - -typedef u8 sc_rm_perm_t; - -#endif /* SC_RM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h deleted file mode 100644 index 3ed0584..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef SC_SECO_API_H -#define SC_SECO_API_H - -/* Includes */ - -#include <asm/arch/sci/types.h> - -/* Defines */ -#define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */ -#define SC_SECO_VERIFY_IMAGE 1U /* Verify image */ -#define SC_SECO_REL_CONTAINER 2U /* Release container */ -#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ -#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ -#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ - -#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ -#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ -#define SC_SECO_RNG_STAT_READY 2U /* Initialized */ - -/* Types */ - -/*! - * This type is used to issue SECO authenticate commands. - */ -typedef u8 sc_seco_auth_cmd_t; - -/*! - * This type is used to return the RNG initialization status. - */ -typedef u32 sc_seco_rng_stat_t; - -#endif /* SC_SECO_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h deleted file mode 100644 index 9eadc88..0000000 --- a/arch/arm/include/asm/arch-imx8/sci/types.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef SC_TYPES_H -#define SC_TYPES_H - -/* Includes */ -#include <linux/types.h> - -/* Defines */ -/* - * This type is used to declare a handle for an IPC communication - * channel. Its meaning is specific to the IPC implementation. - */ -typedef u64 sc_ipc_t; - -/* Defines for common frequencies */ -#define SC_32KHZ 32768U /* 32KHz */ -#define SC_10MHZ 10000000U /* 10MHz */ -#define SC_20MHZ 20000000U /* 20MHz */ -#define SC_25MHZ 25000000U /* 25MHz */ -#define SC_27MHZ 27000000U /* 27MHz */ -#define SC_40MHZ 40000000U /* 40MHz */ -#define SC_45MHZ 45000000U /* 45MHz */ -#define SC_50MHZ 50000000U /* 50MHz */ -#define SC_60MHZ 60000000U /* 60MHz */ -#define SC_66MHZ 66666666U /* 66MHz */ -#define SC_74MHZ 74250000U /* 74.25MHz */ -#define SC_80MHZ 80000000U /* 80MHz */ -#define SC_83MHZ 83333333U /* 83MHz */ -#define SC_84MHZ 84375000U /* 84.37MHz */ -#define SC_100MHZ 100000000U /* 100MHz */ -#define SC_125MHZ 125000000U /* 125MHz */ -#define SC_133MHZ 133333333U /* 133MHz */ -#define SC_135MHZ 135000000U /* 135MHz */ -#define SC_150MHZ 150000000U /* 150MHz */ -#define SC_160MHZ 160000000U /* 160MHz */ -#define SC_166MHZ 166666666U /* 166MHz */ -#define SC_175MHZ 175000000U /* 175MHz */ -#define SC_180MHZ 180000000U /* 180MHz */ -#define SC_200MHZ 200000000U /* 200MHz */ -#define SC_250MHZ 250000000U /* 250MHz */ -#define SC_266MHZ 266666666U /* 266MHz */ -#define SC_300MHZ 300000000U /* 300MHz */ -#define SC_312MHZ 312500000U /* 312.5MHZ */ -#define SC_320MHZ 320000000U /* 320MHz */ -#define SC_325MHZ 325000000U /* 325MHz */ -#define SC_333MHZ 333333333U /* 333MHz */ -#define SC_350MHZ 350000000U /* 350MHz */ -#define SC_372MHZ 372000000U /* 372MHz */ -#define SC_375MHZ 375000000U /* 375MHz */ -#define SC_400MHZ 400000000U /* 400MHz */ -#define SC_500MHZ 500000000U /* 500MHz */ -#define SC_594MHZ 594000000U /* 594MHz */ -#define SC_625MHZ 625000000U /* 625MHz */ -#define SC_640MHZ 640000000U /* 640MHz */ -#define SC_650MHZ 650000000U /* 650MHz */ -#define SC_667MHZ 666666667U /* 667MHz */ -#define SC_675MHZ 675000000U /* 675MHz */ -#define SC_700MHZ 700000000U /* 700MHz */ -#define SC_720MHZ 720000000U /* 720MHz */ -#define SC_750MHZ 750000000U /* 750MHz */ -#define SC_800MHZ 800000000U /* 800MHz */ -#define SC_850MHZ 850000000U /* 850MHz */ -#define SC_900MHZ 900000000U /* 900MHz */ -#define SC_1000MHZ 1000000000U /* 1GHz */ -#define SC_1060MHZ 1060000000U /* 1.06GHz */ -#define SC_1188MHZ 1188000000U /* 1.188GHz */ -#define SC_1260MHZ 1260000000U /* 1.26GHz */ -#define SC_1280MHZ 1280000000U /* 1.28GHz */ -#define SC_1300MHZ 1300000000U /* 1.3GHz */ -#define SC_1400MHZ 1400000000U /* 1.4GHz */ -#define SC_1500MHZ 1500000000U /* 1.5GHz */ -#define SC_1600MHZ 1600000000U /* 1.6GHz */ -#define SC_1800MHZ 1800000000U /* 1.8GHz */ -#define SC_2000MHZ 2000000000U /* 2.0GHz */ -#define SC_2112MHZ 2112000000U /* 2.12GHz */ - -/* Defines for 24M related frequencies */ -#define SC_8MHZ 8000000U /* 8MHz */ -#define SC_12MHZ 12000000U /* 12MHz */ -#define SC_19MHZ 19800000U /* 19.8MHz */ -#define SC_24MHZ 24000000U /* 24MHz */ -#define SC_48MHZ 48000000U /* 48MHz */ -#define SC_120MHZ 120000000U /* 120MHz */ -#define SC_132MHZ 132000000U /* 132MHz */ -#define SC_144MHZ 144000000U /* 144MHz */ -#define SC_192MHZ 192000000U /* 192MHz */ -#define SC_211MHZ 211200000U /* 211.2MHz */ -#define SC_240MHZ 240000000U /* 240MHz */ -#define SC_264MHZ 264000000U /* 264MHz */ -#define SC_352MHZ 352000000U /* 352MHz */ -#define SC_360MHZ 360000000U /* 360MHz */ -#define SC_384MHZ 384000000U /* 384MHz */ -#define SC_396MHZ 396000000U /* 396MHz */ -#define SC_432MHZ 432000000U /* 432MHz */ -#define SC_480MHZ 480000000U /* 480MHz */ -#define SC_600MHZ 600000000U /* 600MHz */ -#define SC_744MHZ 744000000U /* 744MHz */ -#define SC_792MHZ 792000000U /* 792MHz */ -#define SC_864MHZ 864000000U /* 864MHz */ -#define SC_960MHZ 960000000U /* 960MHz */ -#define SC_1056MHZ 1056000000U /* 1056MHz */ -#define SC_1104MHZ 1104000000U /* 1104MHz */ -#define SC_1200MHZ 1200000000U /* 1.2GHz */ -#define SC_1464MHZ 1464000000U /* 1.464GHz */ -#define SC_2400MHZ 2400000000U /* 2.4GHz */ - -/* Defines for A/V related frequencies */ -#define SC_62MHZ 62937500U /* 62.9375MHz */ -#define SC_755MHZ 755250000U /* 755.25MHz */ - -/* Defines for type widths */ -#define SC_FADDR_W 36U /* Width of sc_faddr_t */ -#define SC_BOOL_W 1U /* Width of sc_bool_t */ -#define SC_ERR_W 4U /* Width of sc_err_t */ -#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ -#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ - -/* Defines for sc_bool_t */ -#define SC_FALSE ((sc_bool_t)0U) -#define SC_TRUE ((sc_bool_t)1U) - -/* Defines for sc_err_t */ -#define SC_ERR_NONE 0U /* Success */ -#define SC_ERR_VERSION 1U /* Incompatible API version */ -#define SC_ERR_CONFIG 2U /* Configuration error */ -#define SC_ERR_PARM 3U /* Bad parameter */ -#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ -#define SC_ERR_LOCKED 5U /* Permission error (locked) */ -#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ -#define SC_ERR_NOTFOUND 7U /* Not found */ -#define SC_ERR_NOPOWER 8U /* No power */ -#define SC_ERR_IPC 9U /* Generic IPC error */ -#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ -#define SC_ERR_FAIL 11U /* General I/O failure */ -#define SC_ERR_LAST 12U - -/* Defines for sc_ctrl_t. */ -#define SC_C_TEMP 0U -#define SC_C_TEMP_HI 1U -#define SC_C_TEMP_LOW 2U -#define SC_C_PXL_LINK_MST1_ADDR 3U -#define SC_C_PXL_LINK_MST2_ADDR 4U -#define SC_C_PXL_LINK_MST_ENB 5U -#define SC_C_PXL_LINK_MST1_ENB 6U -#define SC_C_PXL_LINK_MST2_ENB 7U -#define SC_C_PXL_LINK_SLV1_ADDR 8U -#define SC_C_PXL_LINK_SLV2_ADDR 9U -#define SC_C_PXL_LINK_MST_VLD 10U -#define SC_C_PXL_LINK_MST1_VLD 11U -#define SC_C_PXL_LINK_MST2_VLD 12U -#define SC_C_SINGLE_MODE 13U -#define SC_C_ID 14U -#define SC_C_PXL_CLK_POLARITY 15U -#define SC_C_LINESTATE 16U -#define SC_C_PCIE_G_RST 17U -#define SC_C_PCIE_BUTTON_RST 18U -#define SC_C_PCIE_PERST 19U -#define SC_C_PHY_RESET 20U -#define SC_C_PXL_LINK_RATE_CORRECTION 21U -#define SC_C_PANIC 22U -#define SC_C_PRIORITY_GROUP 23U -#define SC_C_TXCLK 24U -#define SC_C_CLKDIV 25U -#define SC_C_DISABLE_50 26U -#define SC_C_DISABLE_125 27U -#define SC_C_SEL_125 28U -#define SC_C_MODE 29U -#define SC_C_SYNC_CTRL0 30U -#define SC_C_KACHUNK_CNT 31U -#define SC_C_KACHUNK_SEL 32U -#define SC_C_SYNC_CTRL1 33U -#define SC_C_DPI_RESET 34U -#define SC_C_MIPI_RESET 35U -#define SC_C_DUAL_MODE 36U -#define SC_C_VOLTAGE 37U -#define SC_C_PXL_LINK_SEL 38U -#define SC_C_OFS_SEL 39U -#define SC_C_OFS_AUDIO 40U -#define SC_C_OFS_PERIPH 41U -#define SC_C_OFS_IRQ 42U -#define SC_C_RST0 43U -#define SC_C_RST1 44U -#define SC_C_SEL0 45U -#define SC_C_LAST 46U - -#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */ - -/* Types */ - -/* This type is used to store a boolean */ -typedef u8 sc_bool_t; - -/* This type is used to store a system (full-size) address. */ -typedef u64 sc_faddr_t; - -/* This type is used to indicate error response for most functions. */ -typedef u8 sc_err_t; - -/* - * This type is used to indicate a resource. Resources include peripherals - * and bus masters (but not memory regions). Note items from list should - * never be changed or removed (only added to at the end of the list). - */ -typedef u16 sc_rsrc_t; - -/* This type is used to indicate a control. */ -typedef u8 sc_ctrl_t; - -/* - * This type is used to indicate a pad. Valid values are SoC specific. - * - * Refer to the SoC [Pad List](@ref PADS) for valid pad values. - */ -typedef u16 sc_pad_t; - -#endif /* SC_TYPES_H */ diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h deleted file mode 100644 index 0e981ae..0000000 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#include <asm/arch/sci/sci.h> -#include <asm/mach-imx/sys_proto.h> -#include <linux/types.h> - -struct pass_over_info_t { - u16 barker; - u16 len; - u32 g_bt_cfg_shadow; - u32 card_address_mode; - u32 bad_block_count_met; - u32 g_ap_mu; -}; - -extern unsigned long boot_pointer[]; -void build_info(void); -enum boot_device get_boot_device(void); -int print_bootinfo(void); -int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate); diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h deleted file mode 100644 index dded6e0..0000000 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ /dev/null @@ -1,275 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - * - * Peng Fan <peng.fan at nxp.com> - */ - -#include <linux/bitops.h> - -#ifdef CONFIG_IMX8MQ -#include <asm/arch/clock_imx8mq.h> -#elif defined(CONFIG_IMX8MM) -#include <asm/arch/clock_imx8mm.h> -#else -#error "Error no clock.h" -#endif - -#define MHZ(X) ((X) * 1000000UL) - -/* Mainly for compatible to imx common code. */ -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_IPG_CLK, - MXC_CSPI_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_I2C_CLK, - MXC_UART_CLK, - MXC_QSPI_CLK, -}; - -enum clk_slice_type { - CORE_CLOCK_SLICE, - BUS_CLOCK_SLICE, - IP_CLOCK_SLICE, - AHB_CLOCK_SLICE, - IPG_CLOCK_SLICE, - CORE_SEL_CLOCK_SLICE, - DRAM_SEL_CLOCK_SLICE, -}; - -enum root_pre_div { - CLK_ROOT_PRE_DIV1 = 0, - CLK_ROOT_PRE_DIV2, - CLK_ROOT_PRE_DIV3, - CLK_ROOT_PRE_DIV4, - CLK_ROOT_PRE_DIV5, - CLK_ROOT_PRE_DIV6, - CLK_ROOT_PRE_DIV7, - CLK_ROOT_PRE_DIV8, -}; - -enum root_post_div { - CLK_ROOT_POST_DIV1 = 0, - CLK_ROOT_POST_DIV2, - CLK_ROOT_POST_DIV3, - CLK_ROOT_POST_DIV4, - CLK_ROOT_POST_DIV5, - CLK_ROOT_POST_DIV6, - CLK_ROOT_POST_DIV7, - CLK_ROOT_POST_DIV8, - CLK_ROOT_POST_DIV9, - CLK_ROOT_POST_DIV10, - CLK_ROOT_POST_DIV11, - CLK_ROOT_POST_DIV12, - CLK_ROOT_POST_DIV13, - CLK_ROOT_POST_DIV14, - CLK_ROOT_POST_DIV15, - CLK_ROOT_POST_DIV16, - CLK_ROOT_POST_DIV17, - CLK_ROOT_POST_DIV18, - CLK_ROOT_POST_DIV19, - CLK_ROOT_POST_DIV20, - CLK_ROOT_POST_DIV21, - CLK_ROOT_POST_DIV22, - CLK_ROOT_POST_DIV23, - CLK_ROOT_POST_DIV24, - CLK_ROOT_POST_DIV25, - CLK_ROOT_POST_DIV26, - CLK_ROOT_POST_DIV27, - CLK_ROOT_POST_DIV28, - CLK_ROOT_POST_DIV29, - CLK_ROOT_POST_DIV30, - CLK_ROOT_POST_DIV31, - CLK_ROOT_POST_DIV32, - CLK_ROOT_POST_DIV33, - CLK_ROOT_POST_DIV34, - CLK_ROOT_POST_DIV35, - CLK_ROOT_POST_DIV36, - CLK_ROOT_POST_DIV37, - CLK_ROOT_POST_DIV38, - CLK_ROOT_POST_DIV39, - CLK_ROOT_POST_DIV40, - CLK_ROOT_POST_DIV41, - CLK_ROOT_POST_DIV42, - CLK_ROOT_POST_DIV43, - CLK_ROOT_POST_DIV44, - CLK_ROOT_POST_DIV45, - CLK_ROOT_POST_DIV46, - CLK_ROOT_POST_DIV47, - CLK_ROOT_POST_DIV48, - CLK_ROOT_POST_DIV49, - CLK_ROOT_POST_DIV50, - CLK_ROOT_POST_DIV51, - CLK_ROOT_POST_DIV52, - CLK_ROOT_POST_DIV53, - CLK_ROOT_POST_DIV54, - CLK_ROOT_POST_DIV55, - CLK_ROOT_POST_DIV56, - CLK_ROOT_POST_DIV57, - CLK_ROOT_POST_DIV58, - CLK_ROOT_POST_DIV59, - CLK_ROOT_POST_DIV60, - CLK_ROOT_POST_DIV61, - CLK_ROOT_POST_DIV62, - CLK_ROOT_POST_DIV63, - CLK_ROOT_POST_DIV64, -}; - -struct clk_root_map { - enum clk_root_index entry; - enum clk_slice_type slice_type; - u32 slice_index; - u8 src_mux[8]; -}; - -struct ccm_ccgr { - u32 ccgr; - u32 ccgr_set; - u32 ccgr_clr; - u32 ccgr_tog; -}; - -struct ccm_root { - u32 target_root; - u32 target_root_set; - u32 target_root_clr; - u32 target_root_tog; - u32 misc; - u32 misc_set; - u32 misc_clr; - u32 misc_tog; - u32 nm_post; - u32 nm_post_root_set; - u32 nm_post_root_clr; - u32 nm_post_root_tog; - u32 nm_pre; - u32 nm_pre_root_set; - u32 nm_pre_root_clr; - u32 nm_pre_root_tog; - u32 db_post; - u32 db_post_root_set; - u32 db_post_root_clr; - u32 db_post_root_tog; - u32 db_pre; - u32 db_pre_root_set; - u32 db_pre_root_clr; - u32 db_pre_root_tog; - u32 reserved[4]; - u32 access_ctrl; - u32 access_ctrl_root_set; - u32 access_ctrl_root_clr; - u32 access_ctrl_root_tog; -}; - -struct ccm_reg { - u32 reserved_0[4096]; - struct ccm_ccgr ccgr_array[192]; - u32 reserved_1[3328]; - struct ccm_root core_root[5]; - u32 reserved_2[352]; - struct ccm_root bus_root[12]; - u32 reserved_3[128]; - struct ccm_root ahb_ipg_root[4]; - u32 reserved_4[384]; - struct ccm_root dram_sel; - struct ccm_root core_sel; - u32 reserved_5[448]; - struct ccm_root ip_root[78]; -}; - -enum enet_freq { - ENET_25MHZ = 0, - ENET_50MHZ, - ENET_125MHZ, -}; - -#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ - { \ - .clk = (_rate), \ - .alt_root_sel = (_m), \ - .alt_pre_div = (_p), \ - .apb_root_sel = (_s), \ - .apb_pre_div = (_k), \ - } - -struct dram_bypass_clk_setting { - ulong clk; - int alt_root_sel; - enum root_pre_div alt_pre_div; - int apb_root_sel; - enum root_pre_div apb_pre_div; -}; - -#define CCGR_CLK_ON_MASK 0x03 -#define CLK_SRC_ON_MASK 0x03 - -#define CLK_ROOT_ON BIT(28) -#define CLK_ROOT_OFF (0 << 28) -#define CLK_ROOT_ENABLE_MASK BIT(28) -#define CLK_ROOT_ENABLE_SHIFT 28 -#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24) - -/* For SEL, only use 1 bit */ -#define CLK_ROOT_SRC_MUX_MASK 0x07000000 -#define CLK_ROOT_SRC_MUX_SHIFT 24 -#define CLK_ROOT_SRC_0 0x00000000 -#define CLK_ROOT_SRC_1 0x01000000 -#define CLK_ROOT_SRC_2 0x02000000 -#define CLK_ROOT_SRC_3 0x03000000 -#define CLK_ROOT_SRC_4 0x04000000 -#define CLK_ROOT_SRC_5 0x05000000 -#define CLK_ROOT_SRC_6 0x06000000 -#define CLK_ROOT_SRC_7 0x07000000 - -#define CLK_ROOT_PRE_DIV_MASK (0x00070000) -#define CLK_ROOT_PRE_DIV_SHIFT 16 -#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000) - -#define CLK_ROOT_AUDO_SLOW_EN 0x1000 - -#define CLK_ROOT_AUDO_DIV_MASK 0x700 -#define CLK_ROOT_AUDO_DIV_SHIFT 0x8 -#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700) - -/* For CORE: mask is 0x7; For IPG: mask is 0x3 */ -#define CLK_ROOT_POST_DIV_MASK 0x3f -#define CLK_ROOT_CORE_POST_DIV_MASK 0x7 -#define CLK_ROOT_IPG_POST_DIV_MASK 0x3 -#define CLK_ROOT_POST_DIV_SHIFT 0 -#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) -#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 -#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000 -#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 - -void dram_pll_init(ulong pll_val); -void dram_enable_bypass(ulong clk_val); -void dram_disable_bypass(void); -u32 imx_get_fecclk(void); -u32 imx_get_uartclk(void); -int clock_init(void); -void init_clk_usdhc(u32 index); -void init_uart_clk(u32 index); -void init_wdog_clk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); -int clock_enable(enum clk_ccgr_index index, bool enable); -int clock_root_enabled(enum clk_root_index clock_id); -int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, - enum root_post_div post_div, enum clk_root_src clock_src); -int clock_set_target_val(enum clk_root_index clock_id, u32 val); -int clock_get_target_val(enum clk_root_index clock_id, u32 *val); -int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); -int clock_get_postdiv(enum clk_root_index clock_id, - enum root_post_div *post_div); -int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); -void mxs_set_lcdclk(u32 base_addr, u32 freq); -int set_clk_qspi(void); -void enable_ocotp_clk(unsigned char enable); -int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); -int set_clk_enet(enum enet_freq type); diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h deleted file mode 100644 index 305514a..0000000 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h +++ /dev/null @@ -1,387 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - * - * Peng Fan <peng.fan@nxp.com> - */ - -#ifndef _ASM_ARCH_IMX8MM_CLOCK_H -#define _ASM_ARCH_IMX8MM_CLOCK_H - -#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ - { \ - .rate = (_rate), \ - .mdiv = (_m), \ - .pdiv = (_p), \ - .sdiv = (_s), \ - .kdiv = (_k), \ - } - -#define LOCK_STATUS BIT(31) -#define LOCK_SEL_MASK BIT(29) -#define CLKE_MASK BIT(11) -#define RST_MASK BIT(9) -#define BYPASS_MASK BIT(4) -#define MDIV_SHIFT 12 -#define MDIV_MASK GENMASK(21, 12) -#define PDIV_SHIFT 4 -#define PDIV_MASK GENMASK(9, 4) -#define SDIV_SHIFT 0 -#define SDIV_MASK GENMASK(2, 0) -#define KDIV_SHIFT 0 -#define KDIV_MASK GENMASK(15, 0) - -struct imx_int_pll_rate_table { - u32 rate; - int mdiv; - int pdiv; - int sdiv; - int kdiv; -}; - -enum pll_clocks { - ANATOP_ARM_PLL, - ANATOP_VPU_PLL, - ANATOP_GPU_PLL, - ANATOP_SYSTEM_PLL1, - ANATOP_SYSTEM_PLL2, - ANATOP_SYSTEM_PLL3, - ANATOP_AUDIO_PLL1, - ANATOP_AUDIO_PLL2, - ANATOP_VIDEO_PLL, - ANATOP_DRAM_PLL, -}; - -enum clk_root_index { - ARM_A53_CLK_ROOT = 0, - ARM_M4_CLK_ROOT = 1, - VPU_A53_CLK_ROOT = 2, - GPU3D_CLK_ROOT = 3, - GPU2D_CLK_ROOT = 4, - MAIN_AXI_CLK_ROOT = 16, - ENET_AXI_CLK_ROOT = 17, - NAND_USDHC_BUS_CLK_ROOT = 18, - VPU_BUS_CLK_ROOT = 19, - DISPLAY_AXI_CLK_ROOT = 20, - DISPLAY_APB_CLK_ROOT = 21, - DISPLAY_RTRM_CLK_ROOT = 22, - USB_BUS_CLK_ROOT = 23, - GPU_AXI_CLK_ROOT = 24, - GPU_AHB_CLK_ROOT = 25, - NOC_CLK_ROOT = 26, - NOC_APB_CLK_ROOT = 27, - AHB_CLK_ROOT = 32, - IPG_CLK_ROOT = 33, - AUDIO_AHB_CLK_ROOT = 34, - MIPI_DSI_ESC_RX_CLK_ROOT = 36, - DRAM_SEL_CFG = 48, - CORE_SEL_CFG = 49, - DRAM_ALT_CLK_ROOT = 64, - DRAM_APB_CLK_ROOT = 65, - VPU_G1_CLK_ROOT = 66, - VPU_G2_CLK_ROOT = 67, - DISPLAY_DTRC_CLK_ROOT = 68, - DISPLAY_DC8000_CLK_ROOT = 69, - PCIE_CTRL_CLK_ROOT = 70, - PCIE_PHY_CLK_ROOT = 71, - PCIE_AUX_CLK_ROOT = 72, - DC_PIXEL_CLK_ROOT = 73, - LCDIF_PIXEL_CLK_ROOT = 74, - SAI1_CLK_ROOT = 75, - SAI2_CLK_ROOT = 76, - SAI3_CLK_ROOT = 77, - SAI4_CLK_ROOT = 78, - SAI5_CLK_ROOT = 79, - SAI6_CLK_ROOT = 80, - SPDIF1_CLK_ROOT = 81, - SPDIF2_CLK_ROOT = 82, - ENET_REF_CLK_ROOT = 83, - ENET_TIMER_CLK_ROOT = 84, - ENET_PHY_REF_CLK_ROOT = 85, - NAND_CLK_ROOT = 86, - QSPI_CLK_ROOT = 87, - USDHC1_CLK_ROOT = 88, - USDHC2_CLK_ROOT = 89, - I2C1_CLK_ROOT = 90, - I2C2_CLK_ROOT = 91, - I2C3_CLK_ROOT = 92, - I2C4_CLK_ROOT = 93, - UART1_CLK_ROOT = 94, - UART2_CLK_ROOT = 95, - UART3_CLK_ROOT = 96, - UART4_CLK_ROOT = 97, - USB_CORE_REF_CLK_ROOT = 98, - USB_PHY_REF_CLK_ROOT = 99, - GIC_CLK_ROOT = 100, - ECSPI1_CLK_ROOT = 101, - ECSPI2_CLK_ROOT = 102, - PWM1_CLK_ROOT = 103, - PWM2_CLK_ROOT = 104, - PWM3_CLK_ROOT = 105, - PWM4_CLK_ROOT = 106, - GPT1_CLK_ROOT = 107, - GPT2_CLK_ROOT = 108, - GPT3_CLK_ROOT = 109, - GPT4_CLK_ROOT = 110, - GPT5_CLK_ROOT = 111, - GPT6_CLK_ROOT = 112, - TRACE_CLK_ROOT = 113, - WDOG_CLK_ROOT = 114, - WRCLK_CLK_ROOT = 115, - IPP_DO_CLKO1 = 116, - IPP_DO_CLKO2 = 117, - MIPI_DSI_CORE_CLK_ROOT = 118, - MIPI_DSI_PHY_REF_CLK_ROOT = 119, - MIPI_DSI_DBI_CLK_ROOT = 120, - USDHC3_CLK_ROOT = 121, - MIPI_CSI1_CORE_CLK_ROOT = 122, - MIPI_CSI1_PHY_REF_CLK_ROOT = 123, - MIPI_CSI1_ESC_CLK_ROOT = 124, - MIPI_CSI2_CORE_CLK_ROOT = 125, - MIPI_CSI2_PHY_REF_CLK_ROOT = 126, - MIPI_CSI2_ESC_CLK_ROOT = 127, - PCIE2_CTRL_CLK_ROOT = 128, - PCIE2_PHY_CLK_ROOT = 129, - PCIE2_AUX_CLK_ROOT = 130, - ECSPI3_CLK_ROOT = 131, - PDM_CLK_ROOT = 132, - VPU_H1_CLK_ROOT = 133, - CLK_ROOT_MAX, -}; - -enum clk_root_src { - OSC_24M_CLK, - ARM_PLL_CLK, - DRAM_PLL1_CLK, - VIDEO_PLL2_CLK, - VPU_PLL_CLK, - GPU_PLL_CLK, - SYSTEM_PLL1_800M_CLK, - SYSTEM_PLL1_400M_CLK, - SYSTEM_PLL1_266M_CLK, - SYSTEM_PLL1_200M_CLK, - SYSTEM_PLL1_160M_CLK, - SYSTEM_PLL1_133M_CLK, - SYSTEM_PLL1_100M_CLK, - SYSTEM_PLL1_80M_CLK, - SYSTEM_PLL1_40M_CLK, - SYSTEM_PLL2_1000M_CLK, - SYSTEM_PLL2_500M_CLK, - SYSTEM_PLL2_333M_CLK, - SYSTEM_PLL2_250M_CLK, - SYSTEM_PLL2_200M_CLK, - SYSTEM_PLL2_166M_CLK, - SYSTEM_PLL2_125M_CLK, - SYSTEM_PLL2_100M_CLK, - SYSTEM_PLL2_50M_CLK, - SYSTEM_PLL3_CLK, - AUDIO_PLL1_CLK, - AUDIO_PLL2_CLK, - VIDEO_PLL_CLK, - OSC_32K_CLK, - EXT_CLK_1, - EXT_CLK_2, - EXT_CLK_3, - EXT_CLK_4, - OSC_HDMI_CLK -}; - -enum clk_ccgr_index { - CCGR_DVFS = 0, - CCGR_ANAMIX = 1, - CCGR_CPU = 2, - CCGR_CSU = 3, - CCGR_DEBUG = 4, - CCGR_DDR1 = 5, - CCGR_ECSPI1 = 7, - CCGR_ECSPI2 = 8, - CCGR_ECSPI3 = 9, - CCGR_ENET1 = 10, - CCGR_GPIO1 = 11, - CCGR_GPIO2 = 12, - CCGR_GPIO3 = 13, - CCGR_GPIO4 = 14, - CCGR_GPIO5 = 15, - CCGR_GPT1 = 16, - CCGR_GPT2 = 17, - CCGR_GPT3 = 18, - CCGR_GPT4 = 19, - CCGR_GPT5 = 20, - CCGR_GPT6 = 21, - CCGR_HS = 22, - CCGR_I2C1 = 23, - CCGR_I2C2 = 24, - CCGR_I2C3 = 25, - CCGR_I2C4 = 26, - CCGR_IOMUX = 27, - CCGR_IOMUX1 = 28, - CCGR_IOMUX2 = 29, - CCGR_IOMUX3 = 30, - CCGR_IOMUX4 = 31, - CCGR_SNVSMIX_IPG_CLK = 32, - CCGR_MU = 33, - CCGR_OCOTP = 34, - CCGR_OCRAM = 35, - CCGR_OCRAM_S = 36, - CCGR_PCIE = 37, - CCGR_PERFMON1 = 38, - CCGR_PERFMON2 = 39, - CCGR_PWM1 = 40, - CCGR_PWM2 = 41, - CCGR_PWM3 = 42, - CCGR_PWM4 = 43, - CCGR_QOS = 44, - CCGR_QOS_DISPMIX = 45, - CCGR_QOS_ETHENET = 46, - CCGR_QSPI = 47, - CCGR_RAWNAND = 48, - CCGR_RDC = 49, - CCGR_ROM = 50, - CCGR_SAI1 = 51, - CCGR_SAI2 = 52, - CCGR_SAI3 = 53, - CCGR_SAI4 = 54, - CCGR_SAI5 = 55, - CCGR_SAI6 = 56, - CCGR_SCTR = 57, - CCGR_SDMA1 = 58, - CCGR_SDMA2 = 59, - CCGR_SEC_DEBUG = 60, - CCGR_SEMA1 = 61, - CCGR_SEMA2 = 62, - CCGR_SIM_DISPLAY = 63, - CCGR_SIM_ENET = 64, - CCGR_SIM_M = 65, - CCGR_SIM_MAIN = 66, - CCGR_SIM_S = 67, - CCGR_SIM_WAKEUP = 68, - CCGR_SIM_HSIO = 69, - CCGR_SIM_VPU = 70, - CCGR_SNVS = 71, - CCGR_TRACE = 72, - CCGR_UART1 = 73, - CCGR_UART2 = 74, - CCGR_UART3 = 75, - CCGR_UART4 = 76, - CCGR_USB_MSCALE_PL301 = 77, - CCGR_GPU3D = 79, - CCGR_USDHC1 = 81, - CCGR_USDHC2 = 82, - CCGR_WDOG1 = 83, - CCGR_WDOG2 = 84, - CCGR_WDOG3 = 85, - CCGR_VPUG1 = 86, - CCGR_GPU_BUS = 87, - CCGR_VPUH1 = 89, - CCGR_VPUG2 = 90, - CCGR_PDM = 91, - CCGR_GIC = 92, - CCGR_DISPMIX = 93, - CCGR_USDHC3 = 94, - CCGR_SDMA3 = 95, - CCGR_XTAL = 96, - CCGR_PLL = 97, - CCGR_TEMP_SENSOR = 98, - CCGR_VPUMIX_BUS = 99, - CCGR_GPU2D = 102, - CCGR_MAX -}; - -enum clk_src_index { - CLK_SRC_CKIL_SYNC_REQ = 0, - CLK_SRC_ARM_PLL_EN = 1, - CLK_SRC_GPU_PLL_EN = 2, - CLK_SRC_VPU_PLL_EN = 3, - CLK_SRC_DRAM_PLL_EN = 4, - CLK_SRC_SYSTEM_PLL1_EN = 5, - CLK_SRC_SYSTEM_PLL2_EN = 6, - CLK_SRC_SYSTEM_PLL3_EN = 7, - CLK_SRC_AUDIO_PLL1_EN = 8, - CLK_SRC_AUDIO_PLL2_EN = 9, - CLK_SRC_VIDEO_PLL1_EN = 10, - CLK_SRC_RESERVED = 11, - CLK_SRC_ARM_PLL = 12, - CLK_SRC_GPU_PLL = 13, - CLK_SRC_VPU_PLL = 14, - CLK_SRC_DRAM_PLL = 15, - CLK_SRC_SYSTEM_PLL1_800M = 16, - CLK_SRC_SYSTEM_PLL1_400M = 17, - CLK_SRC_SYSTEM_PLL1_266M = 18, - CLK_SRC_SYSTEM_PLL1_200M = 19, - CLK_SRC_SYSTEM_PLL1_160M = 20, - CLK_SRC_SYSTEM_PLL1_133M = 21, - CLK_SRC_SYSTEM_PLL1_100M = 22, - CLK_SRC_SYSTEM_PLL1_80M = 23, - CLK_SRC_SYSTEM_PLL1_40M = 24, - CLK_SRC_SYSTEM_PLL2_1000M = 25, - CLK_SRC_SYSTEM_PLL2_500M = 26, - CLK_SRC_SYSTEM_PLL2_333M = 27, - CLK_SRC_SYSTEM_PLL2_250M = 28, - CLK_SRC_SYSTEM_PLL2_200M = 29, - CLK_SRC_SYSTEM_PLL2_166M = 30, - CLK_SRC_SYSTEM_PLL2_125M = 31, - CLK_SRC_SYSTEM_PLL2_100M = 32, - CLK_SRC_SYSTEM_PLL2_50M = 33, - CLK_SRC_SYSTEM_PLL3 = 34, - CLK_SRC_AUDIO_PLL1 = 35, - CLK_SRC_AUDIO_PLL2 = 36, - CLK_SRC_VIDEO_PLL1 = 37, -}; - -#define INTPLL_LOCK_MASK BIT(31) -#define INTPLL_LOCK_SEL_MASK BIT(29) -#define INTPLL_EXT_BYPASS_MASK BIT(28) -#define INTPLL_DIV20_CLKE_MASK BIT(27) -#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26) -#define INTPLL_DIV10_CLKE_MASK BIT(25) -#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24) -#define INTPLL_DIV8_CLKE_MASK BIT(23) -#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22) -#define INTPLL_DIV6_CLKE_MASK BIT(21) -#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20) -#define INTPLL_DIV5_CLKE_MASK BIT(19) -#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18) -#define INTPLL_DIV4_CLKE_MASK BIT(17) -#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16) -#define INTPLL_DIV3_CLKE_MASK BIT(15) -#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14) -#define INTPLL_DIV2_CLKE_MASK BIT(13) -#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12) -#define INTPLL_CLKE_MASK BIT(11) -#define INTPLL_CLKE_OVERRIDE_MASK BIT(10) -#define INTPLL_RST_MASK BIT(9) -#define INTPLL_RST_OVERRIDE_MASK BIT(8) -#define INTPLL_BYPASS_MASK BIT(4) -#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2) -#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0) - -#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12) -#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12)) -#define INTPLL_MAIN_DIV_SHIFT 12 -#define INTPLL_PRE_DIV_MASK GENMASK(9, 4) -#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4)) -#define INTPLL_PRE_DIV_SHIFT 4 -#define INTPLL_POST_DIV_MASK GENMASK(2, 0) -#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0)) -#define INTPLL_POST_DIV_SHIFT 0 - -#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4) -#define INTPLL_LOCK_CON_DLY_SHIFT 4 -#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2) -#define INTPLL_LOCK_CON_OUT_SHIFT 2 -#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0) -#define INTPLL_LOCK_CON_IN_SHIFT 0 - -#define INTPLL_LRD_EN_MASK BIT(21) -#define INTPLL_FOUT_MASK BIT(20) -#define INTPLL_AFC_SEL_MASK BIT(19) -#define INTPLL_PBIAS_CTRL_MASK BIT(18) -#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17) -#define INTPLL_AFCINIT_SEL_MASK BIT(16) -#define INTPLL_FSEL_MASK BIT(14) -#define INTPLL_FEED_EN_MASK BIT(13) -#define INTPLL_EXTAFC_MASK GENMASK(7, 3) -#define INTPLL_AFC_EN_MASK BIT(2) -#define INTPLL_ICP_MASK GENMASK(1, 0) - -#endif diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h deleted file mode 100644 index 9fa9eb2..0000000 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ /dev/null @@ -1,424 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - * - * Peng Fan <peng.fan@nxp.com> - */ - -#ifndef _ASM_ARCH_IMX8M_CLOCK_H -#define _ASM_ARCH_IMX8M_CLOCK_H - -enum pll_clocks { - ANATOP_ARM_PLL, - ANATOP_GPU_PLL, - ANATOP_SYSTEM_PLL1, - ANATOP_SYSTEM_PLL2, - ANATOP_SYSTEM_PLL3, - ANATOP_AUDIO_PLL1, - ANATOP_AUDIO_PLL2, - ANATOP_VIDEO_PLL1, - ANATOP_VIDEO_PLL2, - ANATOP_DRAM_PLL, -}; - -enum clk_root_index { - ARM_A53_CLK_ROOT = 0, - ARM_M4_CLK_ROOT = 1, - VPU_A53_CLK_ROOT = 2, - GPU_CORE_CLK_ROOT = 3, - GPU_SHADER_CLK_ROOT = 4, - MAIN_AXI_CLK_ROOT = 16, - ENET_AXI_CLK_ROOT = 17, - NAND_USDHC_BUS_CLK_ROOT = 18, - VPU_BUS_CLK_ROOT = 19, - DISPLAY_AXI_CLK_ROOT = 20, - DISPLAY_APB_CLK_ROOT = 21, - DISPLAY_RTRM_CLK_ROOT = 22, - USB_BUS_CLK_ROOT = 23, - GPU_AXI_CLK_ROOT = 24, - GPU_AHB_CLK_ROOT = 25, - NOC_CLK_ROOT = 26, - NOC_APB_CLK_ROOT = 27, - AHB_CLK_ROOT = 32, - IPG_CLK_ROOT = 33, - AUDIO_AHB_CLK_ROOT = 34, - MIPI_DSI_ESC_RX_CLK_ROOT = 36, - DRAM_SEL_CFG = 48, - CORE_SEL_CFG = 49, - DRAM_ALT_CLK_ROOT = 64, - DRAM_APB_CLK_ROOT = 65, - VPU_G1_CLK_ROOT = 66, - VPU_G2_CLK_ROOT = 67, - DISPLAY_DTRC_CLK_ROOT = 68, - DISPLAY_DC8000_CLK_ROOT = 69, - PCIE1_CTRL_CLK_ROOT = 70, - PCIE1_PHY_CLK_ROOT = 71, - PCIE1_AUX_CLK_ROOT = 72, - DC_PIXEL_CLK_ROOT = 73, - LCDIF_PIXEL_CLK_ROOT = 74, - SAI1_CLK_ROOT = 75, - SAI2_CLK_ROOT = 76, - SAI3_CLK_ROOT = 77, - SAI4_CLK_ROOT = 78, - SAI5_CLK_ROOT = 79, - SAI6_CLK_ROOT = 80, - SPDIF1_CLK_ROOT = 81, - SPDIF2_CLK_ROOT = 82, - ENET_REF_CLK_ROOT = 83, - ENET_TIMER_CLK_ROOT = 84, - ENET_PHY_REF_CLK_ROOT = 85, - NAND_CLK_ROOT = 86, - QSPI_CLK_ROOT = 87, - USDHC1_CLK_ROOT = 88, - USDHC2_CLK_ROOT = 89, - I2C1_CLK_ROOT = 90, - I2C2_CLK_ROOT = 91, - I2C3_CLK_ROOT = 92, - I2C4_CLK_ROOT = 93, - UART1_CLK_ROOT = 94, - UART2_CLK_ROOT = 95, - UART3_CLK_ROOT = 96, - UART4_CLK_ROOT = 97, - USB_CORE_REF_CLK_ROOT = 98, - USB_PHY_REF_CLK_ROOT = 99, - GIC_CLK_ROOT = 100, - ECSPI1_CLK_ROOT = 101, - ECSPI2_CLK_ROOT = 102, - PWM1_CLK_ROOT = 103, - PWM2_CLK_ROOT = 104, - PWM3_CLK_ROOT = 105, - PWM4_CLK_ROOT = 106, - GPT1_CLK_ROOT = 107, - GPT2_CLK_ROOT = 108, - GPT3_CLK_ROOT = 109, - GPT4_CLK_ROOT = 110, - GPT5_CLK_ROOT = 111, - GPT6_CLK_ROOT = 112, - TRACE_CLK_ROOT = 113, - WDOG_CLK_ROOT = 114, - WRCLK_CLK_ROOT = 115, - IPP_DO_CLKO1 = 116, - IPP_DO_CLKO2 = 117, - MIPI_DSI_CORE_CLK_ROOT = 118, - MIPI_DSI_PHY_REF_CLK_ROOT = 119, - MIPI_DSI_DBI_CLK_ROOT = 120, - OLD_MIPI_DSI_ESC_CLK_ROOT = 121, - MIPI_CSI1_CORE_CLK_ROOT = 122, - MIPI_CSI1_PHY_REF_CLK_ROOT = 123, - MIPI_CSI1_ESC_CLK_ROOT = 124, - MIPI_CSI2_CORE_CLK_ROOT = 125, - MIPI_CSI2_PHY_REF_CLK_ROOT = 126, - MIPI_CSI2_ESC_CLK_ROOT = 127, - PCIE2_CTRL_CLK_ROOT = 128, - PCIE2_PHY_CLK_ROOT = 129, - PCIE2_AUX_CLK_ROOT = 130, - ECSPI3_CLK_ROOT = 131, - OLD_MIPI_DSI_ESC_RX_ROOT = 132, - DISPLAY_HDMI_CLK_ROOT = 133, - CLK_ROOT_MAX, -}; - -enum clk_root_src { - OSC_25M_CLK, - ARM_PLL_CLK, - DRAM_PLL1_CLK, - VIDEO_PLL2_CLK, - VPU_PLL_CLK, - GPU_PLL_CLK, - SYSTEM_PLL1_800M_CLK, - SYSTEM_PLL1_400M_CLK, - SYSTEM_PLL1_266M_CLK, - SYSTEM_PLL1_200M_CLK, - SYSTEM_PLL1_160M_CLK, - SYSTEM_PLL1_133M_CLK, - SYSTEM_PLL1_100M_CLK, - SYSTEM_PLL1_80M_CLK, - SYSTEM_PLL1_40M_CLK, - SYSTEM_PLL2_1000M_CLK, - SYSTEM_PLL2_500M_CLK, - SYSTEM_PLL2_333M_CLK, - SYSTEM_PLL2_250M_CLK, - SYSTEM_PLL2_200M_CLK, - SYSTEM_PLL2_166M_CLK, - SYSTEM_PLL2_125M_CLK, - SYSTEM_PLL2_100M_CLK, - SYSTEM_PLL2_50M_CLK, - SYSTEM_PLL3_CLK, - AUDIO_PLL1_CLK, - AUDIO_PLL2_CLK, - VIDEO_PLL_CLK, - OSC_32K_CLK, - EXT_CLK_1, - EXT_CLK_2, - EXT_CLK_3, - EXT_CLK_4, - OSC_27M_CLK, -}; - -/* CCGR index */ -enum clk_ccgr_index { - CCGR_DVFS = 0, - CCGR_ANAMIX = 1, - CCGR_CPU = 2, - CCGR_CSU = 4, - CCGR_DRAM1 = 5, - CCGR_DRAM2_OBSOLETE = 6, - CCGR_ECSPI1 = 7, - CCGR_ECSPI2 = 8, - CCGR_ECSPI3 = 9, - CCGR_ENET1 = 10, - CCGR_GPIO1 = 11, - CCGR_GPIO2 = 12, - CCGR_GPIO3 = 13, - CCGR_GPIO4 = 14, - CCGR_GPIO5 = 15, - CCGR_GPT1 = 16, - CCGR_GPT2 = 17, - CCGR_GPT3 = 18, - CCGR_GPT4 = 19, - CCGR_GPT5 = 20, - CCGR_GPT6 = 21, - CCGR_HS = 22, - CCGR_I2C1 = 23, - CCGR_I2C2 = 24, - CCGR_I2C3 = 25, - CCGR_I2C4 = 26, - CCGR_IOMUX = 27, - CCGR_IOMUX1 = 28, - CCGR_IOMUX2 = 29, - CCGR_IOMUX3 = 30, - CCGR_IOMUX4 = 31, - CCGR_M4 = 32, - CCGR_MU = 33, - CCGR_OCOTP = 34, - CCGR_OCRAM = 35, - CCGR_OCRAM_S = 36, - CCGR_PCIE = 37, - CCGR_PERFMON1 = 38, - CCGR_PERFMON2 = 39, - CCGR_PWM1 = 40, - CCGR_PWM2 = 41, - CCGR_PWM3 = 42, - CCGR_PWM4 = 43, - CCGR_QOS = 44, - CCGR_DISMIX = 45, - CCGR_MEGAMIX = 46, - CCGR_QSPI = 47, - CCGR_RAWNAND = 48, - CCGR_RDC = 49, - CCGR_ROM = 50, - CCGR_SAI1 = 51, - CCGR_SAI2 = 52, - CCGR_SAI3 = 53, - CCGR_SAI4 = 54, - CCGR_SAI5 = 55, - CCGR_SAI6 = 56, - CCGR_SCTR = 57, - CCGR_SDMA1 = 58, - CCGR_SDMA2 = 59, - CCGR_SEC_DEBUG = 60, - CCGR_SEMA1 = 61, - CCGR_SEMA2 = 62, - CCGR_SIM_DISPLAY = 63, - CCGR_SIM_ENET = 64, - CCGR_SIM_M = 65, - CCGR_SIM_MAIN = 66, - CCGR_SIM_S = 67, - CCGR_SIM_WAKEUP = 68, - CCGR_SIM_USB = 69, - CCGR_SIM_VPU = 70, - CCGR_SNVS = 71, - CCGR_TRACE = 72, - CCGR_UART1 = 73, - CCGR_UART2 = 74, - CCGR_UART3 = 75, - CCGR_UART4 = 76, - CCGR_USB_CTRL1 = 77, - CCGR_USB_CTRL2 = 78, - CCGR_USB_PHY1 = 79, - CCGR_USB_PHY2 = 80, - CCGR_USDHC1 = 81, - CCGR_USDHC2 = 82, - CCGR_WDOG1 = 83, - CCGR_WDOG2 = 84, - CCGR_WDOG3 = 85, - CCGR_VA53 = 86, - CCGR_GPU = 87, - CCGR_HEVC = 88, - CCGR_AVC = 89, - CCGR_VP9 = 90, - CCGR_HEVC_INTER = 91, - CCGR_GIC = 92, - CCGR_DISPLAY = 93, - CCGR_HDMI = 94, - CCGR_HDMI_PHY = 95, - CCGR_XTAL = 96, - CCGR_PLL = 97, - CCGR_TSENSOR = 98, - CCGR_VPU_DEC = 99, - CCGR_PCIE2 = 100, - CCGR_MIPI_CSI1 = 101, - CCGR_MIPI_CSI2 = 102, - CCGR_MAX, -}; - -/* src index */ -enum clk_src_index { - CLK_SRC_CKIL_SYNC_REQ = 0, - CLK_SRC_ARM_PLL_EN = 1, - CLK_SRC_GPU_PLL_EN = 2, - CLK_SRC_VPU_PLL_EN = 3, - CLK_SRC_DRAM_PLL_EN = 4, - CLK_SRC_SYSTEM_PLL1_EN = 5, - CLK_SRC_SYSTEM_PLL2_EN = 6, - CLK_SRC_SYSTEM_PLL3_EN = 7, - CLK_SRC_AUDIO_PLL1_EN = 8, - CLK_SRC_AUDIO_PLL2_EN = 9, - CLK_SRC_VIDEO_PLL1_EN = 10, - CLK_SRC_VIDEO_PLL2_EN = 11, - CLK_SRC_ARM_PLL = 12, - CLK_SRC_GPU_PLL = 13, - CLK_SRC_VPU_PLL = 14, - CLK_SRC_DRAM_PLL = 15, - CLK_SRC_SYSTEM_PLL1_800M = 16, - CLK_SRC_SYSTEM_PLL1_400M = 17, - CLK_SRC_SYSTEM_PLL1_266M = 18, - CLK_SRC_SYSTEM_PLL1_200M = 19, - CLK_SRC_SYSTEM_PLL1_160M = 20, - CLK_SRC_SYSTEM_PLL1_133M = 21, - CLK_SRC_SYSTEM_PLL1_100M = 22, - CLK_SRC_SYSTEM_PLL1_80M = 23, - CLK_SRC_SYSTEM_PLL1_40M = 24, - CLK_SRC_SYSTEM_PLL2_1000M = 25, - CLK_SRC_SYSTEM_PLL2_500M = 26, - CLK_SRC_SYSTEM_PLL2_333M = 27, - CLK_SRC_SYSTEM_PLL2_250M = 28, - CLK_SRC_SYSTEM_PLL2_200M = 29, - CLK_SRC_SYSTEM_PLL2_166M = 30, - CLK_SRC_SYSTEM_PLL2_125M = 31, - CLK_SRC_SYSTEM_PLL2_100M = 32, - CLK_SRC_SYSTEM_PLL2_50M = 33, - CLK_SRC_SYSTEM_PLL3 = 34, - CLK_SRC_AUDIO_PLL1 = 35, - CLK_SRC_AUDIO_PLL2 = 36, - CLK_SRC_VIDEO_PLL1 = 37, - CLK_SRC_VIDEO_PLL2 = 38, - CLK_SRC_OSC_25M = 39, - CLK_SRC_OSC_27M = 40, -}; - -/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ -#define FRAC_PLL_LOCK_MASK BIT(31) -#define FRAC_PLL_CLKE_MASK BIT(21) -#define FRAC_PLL_PD_MASK BIT(19) -#define FRAC_PLL_REFCLK_SEL_MASK BIT(16) -#define FRAC_PLL_LOCK_SEL_MASK BIT(15) -#define FRAC_PLL_BYPASS_MASK BIT(14) -#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) -#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) -#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) -#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) -#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) -#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 -#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f -#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f) - -#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16) - -#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) -#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 -#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f -#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) - -/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ -#define SSCG_PLL_LOCK_MASK BIT(31) -#define SSCG_PLL_CLKE_MASK BIT(25) -#define SSCG_PLL_DIV2_CLKE_MASK BIT(23) -#define SSCG_PLL_DIV3_CLKE_MASK BIT(21) -#define SSCG_PLL_DIV4_CLKE_MASK BIT(19) -#define SSCG_PLL_DIV5_CLKE_MASK BIT(17) -#define SSCG_PLL_DIV6_CLKE_MASK BIT(15) -#define SSCG_PLL_DIV8_CLKE_MASK BIT(13) -#define SSCG_PLL_DIV10_CLKE_MASK BIT(11) -#define SSCG_PLL_DIV20_CLKE_MASK BIT(9) -#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) -#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) -#define SSCG_PLL_PLL3_CLKE_MASK BIT(9) -#define SSCG_PLL_PD_MASK BIT(7) -#define SSCG_PLL_BYPASS1_MASK BIT(5) -#define SSCG_PLL_BYPASS2_MASK BIT(4) -#define SSCG_PLL_LOCK_SEL_MASK BIT(3) -#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) -#define SSCG_PLL_REFCLK_SEL_MASK 0x3 -#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) - -#define SSCG_PLL_SSDS_MASK BIT(8) -#define SSCG_PLL_SSMD_MASK (0x7 << 5) -#define SSCG_PLL_SSMF_MASK (0xf << 1) -#define SSCG_PLL_SSE_MASK 0x1 - -#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) -#define SSCG_PLL_REF_DIVR1_SHIFT 25 -#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) -#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) -#define SSCG_PLL_REF_DIVR2_SHIFT 19 -#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) -#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) -#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 -#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ - SSCG_PLL_FEEDBACK_DIV_F1_MASK) -#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) -#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 -#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ - SSCG_PLL_FEEDBACK_DIV_F2_MASK) -#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) -#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 -#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ - SSCG_PLL_OUTPUT_DIV_VAL_MASK) -#define SSCG_PLL_FILTER_RANGE_MASK 0x1 - -#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) -#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) -#define HW_DIGPROG_MINOR_MASK 0xff - -#define HW_OSC_27M_CLKE_MASK BIT(4) -#define HW_OSC_25M_CLKE_MASK BIT(2) -#define HW_OSC_32K_SEL_MASK 0x1 -#define HW_OSC_32K_SEL_RTC 0x1 -#define HW_OSC_32K_SEL_25M_DIV800 0x0 - -#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) -#define HW_FRAC_ARM_PLL_DIV_SHIFT 20 -#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) -#define HW_FRAC_VPU_PLL_DIV_SHIFT 16 -#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) -#define HW_FRAC_GPU_PLL_DIV_SHIFT 12 -#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) -#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 -#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) -#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 -#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 -#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0 - -#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) -#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 -#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) -#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 -#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) -#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 -#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) -#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 -#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 -#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0 - -enum frac_pll_out_val { - FRAC_PLL_OUT_1000M, - FRAC_PLL_OUT_1600M, -}; -#endif diff --git a/arch/arm/include/asm/arch-imx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h deleted file mode 100644 index c42e668..0000000 --- a/arch/arm/include/asm/arch-imx8m/crm_regs.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H -#define _ASM_ARCH_IMX8M_CRM_REGS_H -/* Dummy header, some imx-common code needs this file */ -#endif diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h deleted file mode 100644 index 53d4625..0000000 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ /dev/null @@ -1,740 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __ASM_ARCH_IMX8M_DDR_H -#define __ASM_ARCH_IMX8M_DDR_H - -#include <asm/io.h> -#include <asm/types.h> -#include <asm/arch/ddr.h> - -#define DDRC_DDR_SS_GPR0 0x3d000000 -#define DDRC_IPS_BASE_ADDR_0 0x3f400000 -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) -#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) - -struct ddrc_freq { - u32 res0[8]; - u32 derateen; - u32 derateint; - u32 res1[10]; - u32 rfshctl0; - u32 res2[4]; - u32 rfshtmg; - u32 rfshtmg1; - u32 res3[28]; - u32 init3; - u32 init4; - u32 res; - u32 init6; - u32 init7; - u32 res4[4]; - u32 dramtmg0; - u32 dramtmg1; - u32 dramtmg2; - u32 dramtmg3; - u32 dramtmg4; - u32 dramtmg5; - u32 dramtmg6; - u32 dramtmg7; - u32 dramtmg8; - u32 dramtmg9; - u32 dramtmg10; - u32 dramtmg11; - u32 dramtmg12; - u32 dramtmg13; - u32 dramtmg14; - u32 dramtmg15; - u32 dramtmg16; - u32 dramtmg17; - u32 res5[10]; - u32 mramtmg0; - u32 mramtmg1; - u32 mramtmg4; - u32 mramtmg9; - u32 zqctl0; - u32 res6[3]; - u32 dfitmg0; - u32 dfitmg1; - u32 res7[7]; - u32 dfitmg2; - u32 dfitmg3; - u32 res8[33]; - u32 odtcfg; -}; - -struct imx8m_ddrc_regs { - u32 mstr; - u32 stat; - u32 mstr1; - u32 res1; - u32 mrctrl0; - u32 mrctrl1; - u32 mrstat; - u32 mrctrl2; - u32 derateen; - u32 derateint; - u32 mstr2; - u32 res2; - u32 pwrctl; - u32 pwrtmg; - u32 hwlpctl; - u32 hwffcctl; - u32 hwffcstat; - u32 res3[3]; - u32 rfshctl0; - u32 rfshctl1; - u32 rfshctl2; - u32 rfshctl4; - u32 rfshctl3; - u32 rfshtmg; - u32 rfshtmg1; - u32 res4; - u32 ecccfg0; - u32 ecccfg1; - u32 eccstat; - u32 eccclr; - u32 eccerrcnt; - u32 ecccaddr0; - u32 ecccaddr1; - u32 ecccsyn0; - u32 ecccsyn1; - u32 ecccsyn2; - u32 eccbitmask0; - u32 eccbitmask1; - u32 eccbitmask2; - u32 eccuaddr0; - u32 eccuaddr1; - u32 eccusyn0; - u32 eccusyn1; - u32 eccusyn2; - u32 eccpoisonaddr0; - u32 eccpoisonaddr1; - u32 crcparctl0; - u32 crcparctl1; - u32 crcparctl2; - u32 crcparstat; - u32 init0; - u32 init1; - u32 init2; - u32 init3; - u32 init4; - u32 init5; - u32 init6; - u32 init7; - u32 dimmctl; - u32 rankctl; - u32 res5; - u32 chctl; - u32 dramtmg0; - u32 dramtmg1; - u32 dramtmg2; - u32 dramtmg3; - u32 dramtmg4; - u32 dramtmg5; - u32 dramtmg6; - u32 dramtmg7; - u32 dramtmg8; - u32 dramtmg9; - u32 dramtmg10; - u32 dramtmg11; - u32 dramtmg12; - u32 dramtmg13; - u32 dramtmg14; - u32 dramtmg15; - u32 dramtmg16; - u32 dramtmg17; - u32 res6[10]; - u32 mramtmg0; - u32 mramtmg1; - u32 mramtmg4; - u32 mramtmg9; - u32 zqctl0; - u32 zqctl1; - u32 zqctl2; - u32 zqstat; - u32 dfitmg0; - u32 dfitmg1; - u32 dfilpcfg0; - u32 dfilpcfg1; - u32 dfiupd0; - u32 dfiupd1; - u32 dfiupd2; - u32 res7; - u32 dfimisc; - u32 dfitmg2; - u32 dfitmg3; - u32 dfistat; - u32 dbictl; - u32 dfiphymstr; - u32 res8[14]; - u32 addrmap0; - u32 addrmap1; - u32 addrmap2; - u32 addrmap3; - u32 addrmap4; - u32 addrmap5; - u32 addrmap6; - u32 addrmap7; - u32 addrmap8; - u32 addrmap9; - u32 addrmap10; - u32 addrmap11; - u32 res9[4]; - u32 odtcfg; - u32 odtmap; - u32 res10[2]; - u32 sched; - u32 sched1; - u32 sched2; - u32 perfhpr1; - u32 res11; - u32 perflpr1; - u32 res12; - u32 perfwr1; - u32 res13[4]; - u32 dqmap0; - u32 dqmap1; - u32 dqmap2; - u32 dqmap3; - u32 dqmap4; - u32 dqmap5; - u32 res14[26]; - u32 dbg0; - u32 dbg1; - u32 dbgcam; - u32 dbgcmd; - u32 dbgstat; - u32 res15[3]; - u32 swctl; - u32 swstat; - u32 res16[2]; - u32 ocparcfg0; - u32 ocparcfg1; - u32 ocparcfg2; - u32 ocparcfg3; - u32 ocparstat0; - u32 ocparstat1; - u32 ocparwlog0; - u32 ocparwlog1; - u32 ocparwlog2; - u32 ocparawlog0; - u32 ocparawlog1; - u32 ocparrlog0; - u32 ocparrlog1; - u32 ocpararlog0; - u32 ocpararlog1; - u32 poisoncfg; - u32 poisonstat; - u32 adveccindex; - union { - u32 adveccstat; - u32 eccapstat; - }; - u32 eccpoisonpat0; - u32 eccpoisonpat1; - u32 eccpoisonpat2; - u32 res17[6]; - u32 caparpoisonctl; - u32 caparpoisonstat; - u32 res18[2]; - u32 dynbsmstat; - u32 res19[18]; - u32 pstat; - u32 pccfg; - struct { - u32 pcfgr; - u32 pcfgw; - u32 pcfgc; - struct { - u32 pcfgidmaskch0; - u32 pcfidvaluech0; - } pcfgid[16]; - u32 pctrl; - u32 pcfgqos0; - u32 pcfgqos1; - u32 pcfgwqos0; - u32 pcfgwqos1; - u32 res[4]; - } pcfg[16]; - struct { - u32 sarbase; - u32 sarsize; - } sar[4]; - u32 sbrctl; - u32 sbrstat; - u32 sbrwdata0; - u32 sbrwdata1; - u32 pdch; - u32 res20[755]; - /* umctl2_regs_dch1 */ - u32 ch1_stat; - u32 res21[2]; - u32 ch1_mrctrl0; - u32 ch1_mrctrl1; - u32 ch1_mrstat; - u32 ch1_mrctrl2; - u32 res22[4]; - u32 ch1_pwrctl; - u32 ch1_pwrtmg; - u32 ch1_hwlpctl; - u32 res23[15]; - u32 ch1_eccstat; - u32 ch1_eccclr; - u32 ch1_eccerrcnt; - u32 ch1_ecccaddr0; - u32 ch1_ecccaddr1; - u32 ch1_ecccsyn0; - u32 ch1_ecccsyn1; - u32 ch1_ecccsyn2; - u32 ch1_eccbitmask0; - u32 ch1_eccbitmask1; - u32 ch1_eccbitmask2; - u32 ch1_eccuaddr0; - u32 ch1_eccuaddr1; - u32 ch1_eccusyn0; - u32 ch1_eccusyn1; - u32 ch1_eccusyn2; - u32 res24[2]; - u32 ch1_crcparctl0; - u32 res25[2]; - u32 ch1_crcparstat; - u32 res26[46]; - u32 ch1_zqctl2; - u32 ch1_zqstat; - u32 res27[11]; - u32 ch1_dfistat; - u32 res28[33]; - u32 ch1_odtmap; - u32 res29[47]; - u32 ch1_dbg1; - u32 ch1_dbgcam; - u32 ch1_dbgcmd; - u32 ch1_dbgstat; - u32 res30[123]; - /* umctl2_regs_freq1 */ - struct ddrc_freq freq1; - u32 res31[109]; - /* umctl2_regs_addrmap_alt */ - u32 addrmap0_alt; - u32 addrmap1_alt; - u32 addrmap2_alt; - u32 addrmap3_alt; - u32 addrmap4_alt; - u32 addrmap5_alt; - u32 addrmap6_alt; - u32 addrmap7_alt; - u32 addrmap8_alt; - u32 addrmap9_alt; - u32 addrmap10_alt; - u32 addrmap11_alt; - u32 res32[758]; - /* umctl2_regs_freq2 */ - struct ddrc_freq freq2; - u32 res33[879]; - /* umctl2_regs_freq3 */ - struct ddrc_freq freq3; -}; - -struct imx8m_ddrphy_regs { - u32 reg[0xf0000]; -}; - -/* PHY State */ -enum pstate { - PS0, - PS1, - PS2, - PS3, -}; - -enum msg_response { - TRAIN_SUCCESS = 0x7, - TRAIN_STREAM_START = 0x8, - TRAIN_FAIL = 0xff, -}; - -#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) -#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) -#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) -#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) -#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) -#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) -#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) -#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) -#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) -#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) -#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) -#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) -#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) -#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) -#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) -#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) -#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) -#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) -#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) -#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) -#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) -#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) -#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) -#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) -#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) -#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) -#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) -#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) -#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) -#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) -#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) -#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) -#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) -#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) -#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) -#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) -#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) -#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) -#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) -#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) -#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) -#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) -#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) -#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) -#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) -#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) -#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) -#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) -#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) -#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) -#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) -#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) -#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) -#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) -#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) -#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) -#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) -#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) -#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) -#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) -#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) -#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) -#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) -#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) -#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) -#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) -#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) -#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) -#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) -#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) -#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) -#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) -#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) -#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) -#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) -#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) -#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) -#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) -#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) -#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) -#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) -#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) -#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) -#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) -#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) -#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) -#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) -#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) -#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) -#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) -#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) -#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) -#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) -#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) -#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) -#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) -#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) -#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) -#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) -#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) -#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) -#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) -#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) -#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) -#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) -#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) -#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) -#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) -#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) -#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) -#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) -#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) -#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) -#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) -#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) -#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) -#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) -#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) -#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) -#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) -#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) -#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) -#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) -#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) -#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) -#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) -#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) -#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) -#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) -#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) -#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) -#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) -#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) -#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) -#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) -#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) -#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) -#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) -#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) -#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) -#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) -#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) -#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) -#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) - -#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) -#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) -#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) -#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) -#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) -#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) -#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) -#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) -#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) -#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) -#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) -#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) -#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) -#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) -#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) -#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) -#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) -#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) -#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) -#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) -#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) -#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) -#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) -#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) -#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) -#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) -#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) -#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) - -#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) -#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) -#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) -#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) -#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) -#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) -#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) -#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) -#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) -#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) -#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) -#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) -#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) -#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) -#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) -#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) -#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) -#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) -#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) -#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) -#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) -#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) -#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) -#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) -#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) -#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) -#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) -#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) -#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) -#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) -#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) -#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) - -#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) -#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) -#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) -#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) -#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) -#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) -#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) -#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) -#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) -#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) -#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) -#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) -#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) -#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) -#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) -#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) -#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) -#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) -#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) -#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) -#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) -#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) -#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) -#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) -#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) -#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) -#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) -#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) -#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) -#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) -#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) -#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) - -#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) -#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) -#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) -#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) -#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) -#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) -#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) -#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) -#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) -#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) -#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) -#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) -#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) -#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) -#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) -#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) -#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) -#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) -#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) -#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) -#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) -#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) -#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) -#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) -#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) - -#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) -#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) -#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) -#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) -#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) -#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) -#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) -#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) -#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) -#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) -#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) - -#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097) - -#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000)) -#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) -#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) -#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) -#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) -#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) -#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) -#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) -#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) -#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) -#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) -#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) -#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) -#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) -#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) -#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) -#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) -#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) -#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) -#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) -#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) -#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) -#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) -#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) -#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) - -/* user data type */ -enum fw_type { - FW_1D_IMAGE, - FW_2D_IMAGE, -}; - -struct dram_cfg_param { - unsigned int reg; - unsigned int val; -}; - -struct dram_fsp_msg { - unsigned int drate; - enum fw_type fw_type; - struct dram_cfg_param *fsp_cfg; - unsigned int fsp_cfg_num; -}; - -struct dram_timing_info { - /* umctl2 config */ - struct dram_cfg_param *ddrc_cfg; - unsigned int ddrc_cfg_num; - /* ddrphy config */ - struct dram_cfg_param *ddrphy_cfg; - unsigned int ddrphy_cfg_num; - /* ddr fsp train info */ - struct dram_fsp_msg *fsp_msg; - unsigned int fsp_msg_num; - /* ddr phy trained CSR */ - struct dram_cfg_param *ddrphy_trained_csr; - unsigned int ddrphy_trained_csr_num; - /* ddr phy PIE */ - struct dram_cfg_param *ddrphy_pie; - unsigned int ddrphy_pie_num; - /* initialized drate table */ - unsigned int fsp_table[4]; -}; - -extern struct dram_timing_info dram_timing; - -void ddr_load_train_firmware(enum fw_type type); -void ddr_init(struct dram_timing_info *timing_info); -void ddr_cfg_phy(struct dram_timing_info *timing_info); -void load_lpddr4_phy_pie(void); -void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); -void dram_config_save(struct dram_timing_info *info, unsigned long base); - -/* utils function for ddr phy training */ -void wait_ddrphy_training_complete(void); -void ddrphy_init_set_dfi_clk(unsigned int drate); -void ddrphy_init_read_msg_block(enum fw_type type); - -static inline void reg32_write(unsigned long addr, u32 val) -{ - writel(val, addr); -} - -static inline u32 reg32_read(unsigned long addr) -{ - return readl(addr); -} - -static inline void reg32setbit(unsigned long addr, u32 bit) -{ - setbits_le32(addr, (1 << bit)); -} - -#define dwc_ddrphy_apb_wr(addr, data) \ - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) -#define dwc_ddrphy_apb_rd(addr) \ - reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) - -extern struct dram_cfg_param ddrphy_trained_csr[]; -extern uint32_t ddrphy_trained_csr_num; - -#endif diff --git a/arch/arm/include/asm/arch-imx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h deleted file mode 100644 index 2d9fbcb..0000000 --- a/arch/arm/include/asm/arch-imx8m/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __ASM_ARCH_IMX8M_GPIO_H -#define __ASM_ARCH_IMX8M_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h deleted file mode 100644 index 62640d9..0000000 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ /dev/null @@ -1,308 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __ASM_ARCH_IMX8M_REGS_H__ -#define __ASM_ARCH_IMX8M_REGS_H__ - -#define ARCH_MXC - -#include <asm/mach-imx/regs-lcdif.h> - -#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 -#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 - -#define M4_BOOTROM_BASE_ADDR 0x007E0000 - -#define GPIO1_BASE_ADDR 0X30200000 -#define GPIO2_BASE_ADDR 0x30210000 -#define GPIO3_BASE_ADDR 0x30220000 -#define GPIO4_BASE_ADDR 0x30230000 -#define GPIO5_BASE_ADDR 0x30240000 -#define WDOG1_BASE_ADDR 0x30280000 -#define WDOG2_BASE_ADDR 0x30290000 -#define WDOG3_BASE_ADDR 0x302A0000 -#define IOMUXC_BASE_ADDR 0x30330000 -#define IOMUXC_GPR_BASE_ADDR 0x30340000 -#define OCOTP_BASE_ADDR 0x30350000 -#define ANATOP_BASE_ADDR 0x30360000 -#define CCM_BASE_ADDR 0x30380000 -#define SRC_BASE_ADDR 0x30390000 -#define GPC_BASE_ADDR 0x303A0000 - -#define SYSCNT_RD_BASE_ADDR 0x306A0000 -#define SYSCNT_CMP_BASE_ADDR 0x306B0000 -#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 - -#define UART1_BASE_ADDR 0x30860000 -#define UART3_BASE_ADDR 0x30880000 -#define UART2_BASE_ADDR 0x30890000 -#define I2C1_BASE_ADDR 0x30A20000 -#define I2C2_BASE_ADDR 0x30A30000 -#define I2C3_BASE_ADDR 0x30A40000 -#define I2C4_BASE_ADDR 0x30A50000 -#define UART4_BASE_ADDR 0x30A60000 -#define USDHC1_BASE_ADDR 0x30B40000 -#define USDHC2_BASE_ADDR 0x30B50000 -#ifdef CONFIG_IMX8MM -#define USDHC3_BASE_ADDR 0x30B60000 -#endif - -#define TZASC_BASE_ADDR 0x32F80000 - -#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ - 0x30320000 : 0x32e00000 - -#define SRC_IPS_BASE_ADDR 0x30390000 -#define SRC_DDRC_RCR_ADDR 0x30391000 -#define SRC_DDRC2_RCR_ADDR 0x30391004 - -#define DDRC_DDR_SS_GPR0 0x3d000000 -#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) -#define DDR_CSD1_BASE_ADDR 0x40000000 - -#if !defined(__ASSEMBLY__) -#include <asm/types.h> -#include <linux/bitops.h> -#include <stdbool.h> - -#define GPR_TZASC_EN BIT(0) -#define GPR_TZASC_EN_LOCK BIT(16) - -#define SRC_SCR_M4_ENABLE_OFFSET 3 -#define SRC_SCR_M4_ENABLE_MASK BIT(3) -#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 -#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) -#define SRC_DDR1_ENABLE_MASK 0x8F000000UL -#define SRC_DDR2_ENABLE_MASK 0x8F000000UL -#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3) -#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2) -#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) -#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) - -struct iomuxc_gpr_base_regs { - u32 gpr[47]; -}; - -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[3]; - u32 sw_sticky; - u32 rsvd4[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd5[3]; - u32 crc_value; - u32 rsvd6[3]; - u32 version; - u32 rsvd7[0xdb]; - - /* fuse banks */ - struct fuse_bank { - u32 fuse_regs[0x10]; - } bank[0]; -}; - -struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 uid_low; - u32 rsvd1[3]; - u32 uid_high; - u32 rsvd2[7]; -}; - -struct fuse_bank1_regs { - u32 tester3; - u32 rsvd0[3]; - u32 tester4; - u32 rsvd1[3]; - u32 tester5; - u32 rsvd2[3]; - u32 cfg0; - u32 rsvd3[3]; -}; - -#ifdef CONFIG_IMX8MQ -struct anamix_pll { - u32 audio_pll1_cfg0; - u32 audio_pll1_cfg1; - u32 audio_pll2_cfg0; - u32 audio_pll2_cfg1; - u32 video_pll_cfg0; - u32 video_pll_cfg1; - u32 gpu_pll_cfg0; - u32 gpu_pll_cfg1; - u32 vpu_pll_cfg0; - u32 vpu_pll_cfg1; - u32 arm_pll_cfg0; - u32 arm_pll_cfg1; - u32 sys_pll1_cfg0; - u32 sys_pll1_cfg1; - u32 sys_pll1_cfg2; - u32 sys_pll2_cfg0; - u32 sys_pll2_cfg1; - u32 sys_pll2_cfg2; - u32 sys_pll3_cfg0; - u32 sys_pll3_cfg1; - u32 sys_pll3_cfg2; - u32 video_pll2_cfg0; - u32 video_pll2_cfg1; - u32 video_pll2_cfg2; - u32 dram_pll_cfg0; - u32 dram_pll_cfg1; - u32 dram_pll_cfg2; - u32 digprog; - u32 osc_misc_cfg; - u32 pllout_monitor_cfg; - u32 frac_pllout_div_cfg; - u32 sscg_pllout_div_cfg; -}; -#else -struct anamix_pll { - u32 audio_pll1_gnrl_ctl; - u32 audio_pll1_fdiv_ctl0; - u32 audio_pll1_fdiv_ctl1; - u32 audio_pll1_sscg_ctl; - u32 audio_pll1_mnit_ctl; - u32 audio_pll2_gnrl_ctl; - u32 audio_pll2_fdiv_ctl0; - u32 audio_pll2_fdiv_ctl1; - u32 audio_pll2_sscg_ctl; - u32 audio_pll2_mnit_ctl; - u32 video_pll1_gnrl_ctl; - u32 video_pll1_fdiv_ctl0; - u32 video_pll1_fdiv_ctl1; - u32 video_pll1_sscg_ctl; - u32 video_pll1_mnit_ctl; - u32 reserved[5]; - u32 dram_pll_gnrl_ctl; - u32 dram_pll_fdiv_ctl0; - u32 dram_pll_fdiv_ctl1; - u32 dram_pll_sscg_ctl; - u32 dram_pll_mnit_ctl; - u32 gpu_pll_gnrl_ctl; - u32 gpu_pll_div_ctl; - u32 gpu_pll_locked_ctl1; - u32 gpu_pll_mnit_ctl; - u32 vpu_pll_gnrl_ctl; - u32 vpu_pll_div_ctl; - u32 vpu_pll_locked_ctl1; - u32 vpu_pll_mnit_ctl; - u32 arm_pll_gnrl_ctl; - u32 arm_pll_div_ctl; - u32 arm_pll_locked_ctl1; - u32 arm_pll_mnit_ctl; - u32 sys_pll1_gnrl_ctl; - u32 sys_pll1_div_ctl; - u32 sys_pll1_locked_ctl1; - u32 reserved2[24]; - u32 sys_pll1_mnit_ctl; - u32 sys_pll2_gnrl_ctl; - u32 sys_pll2_div_ctl; - u32 sys_pll2_locked_ctl1; - u32 sys_pll2_mnit_ctl; - u32 sys_pll3_gnrl_ctl; - u32 sys_pll3_div_ctl; - u32 sys_pll3_locked_ctl1; - u32 sys_pll3_mnit_ctl; - u32 anamix_misc_ctl; - u32 anamix_clk_mnit_ctl; - u32 reserved3[437]; - u32 digprog; -}; -#endif - -struct fuse_bank9_regs { - u32 mac_addr0; - u32 rsvd0[3]; - u32 mac_addr1; - u32 rsvd1[11]; -}; - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 a53rcr; - u32 a53rcr1; - u32 m4rcr; - u32 reserved1[4]; - u32 usbophy1_rcr; - u32 usbophy2_rcr; - u32 mipiphy_rcr; - u32 pciephy_rcr; - u32 hdmi_rcr; - u32 disp_rcr; - u32 reserved2[2]; - u32 gpu_rcr; - u32 vpu_rcr; - u32 pcie2_rcr; - u32 mipiphy1_rcr; - u32 mipiphy2_rcr; - u32 reserved3; - u32 sbmr1; - u32 srsr; - u32 reserved4[2]; - u32 sisr; - u32 simr; - u32 sbmr2; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 gpr8; - u32 gpr9; - u32 gpr10; - u32 reserved5[985]; - u32 ddr1_rcr; - u32 ddr2_rcr; -}; - -#define WDOG_WDT_MASK BIT(3) -#define WDOG_WDZST_MASK BIT(0) -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Miscellaneous Control */ -}; - -struct bootrom_sw_info { - u8 reserved_1; - u8 boot_dev_instance; - u8 boot_dev_type; - u8 reserved_2; - u32 core_freq; - u32 axi_freq; - u32 ddr_freq; - u32 tick_freq; - u32 reserved_3[3]; -}; - -#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\ - 0x000009e8) -#define ROM_SW_INFO_ADDR_A0 0x000009e8 - -#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \ - (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \ - (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0 -#endif -#endif diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h deleted file mode 100644 index 210e96e..0000000 --- a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h +++ /dev/null @@ -1,691 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __ASM_ARCH_IMX8MM_PINS_H__ -#define __ASM_ARCH_IMX8MM_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), - IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), - IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), - IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0), - IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), - - IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0), - IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), - IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), - IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), - IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0), - IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0), - IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), - IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), - - IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0), - IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), - IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), - IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), - IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), - IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), - IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), - IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), - IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), - IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), - IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), - IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), - IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), - IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), - IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), - IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), - IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), - IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), - IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), - IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), - IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), - IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), - IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0), - IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), - IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0), - IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), - IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0), - IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0), - IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0), - IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), - IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), - IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), - IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), - IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), - IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), - IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), - IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), - IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), - IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), - IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), - IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), - IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), - IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), - IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), - IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), - IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), - IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), - - IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), - IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), - IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), - IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), - IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), - IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), - IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), - IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), - IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), - IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), - IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), - IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), - IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), - IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), - IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), - IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), - IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), - IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), - IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), - IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), - IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), - IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), - IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), - IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), - IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), - IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), - IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), - IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), - IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), - IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), - IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), - IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), - IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), - IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), - IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), - IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), - IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), - IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), - IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), - IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), - IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), - IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), - IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), - IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), - IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), - IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), - IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), - IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), - IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), - IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), - IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), - - IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), - IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), - IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), - IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), - IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), -}; -#endif diff --git a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h deleted file mode 100644 index c71913f..0000000 --- a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h +++ /dev/null @@ -1,622 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 NXP - */ - -#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ -#define __ASM_ARCH_IMX8MQ_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), - IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), - - IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), - IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), - IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), - IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), - IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), - IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), - IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), - IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), - IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), - IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), - IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), - IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), - IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), - IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), - IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), - IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0), - IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), - IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), - IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), - IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), - IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), - IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), - IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), - IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), - IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), - IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), - IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), - IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), - IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), - IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), - IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), - IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), - IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), - IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), - IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), - IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), - IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), - IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), - IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), - IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), - IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), - IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), - IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), - IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), - IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), - IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), - IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), - IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), - IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), - IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), - IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), - IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), - IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), - IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0), - IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), - IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), - IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), - IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), - IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), - IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), - IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), - IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), - IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), - IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), - - IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), - IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), - IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0), - IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), -}; -#endif diff --git a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h deleted file mode 100644 index caf5baf..0000000 --- a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __LPDDR4_DEFINE_H_ -#define __LPDDR4_DEFINE_H_ - -#define LPDDR4_DVFS_DBI -#define DDR_ONE_RANK -/* #define LPDDR4_DBI_ON */ -#define DFI_BUG_WR -#define M845S_4GBx2 -#define PRETRAIN - -/* DRAM MR setting */ -#ifdef LPDDR4_DBI_ON -#define LPDDR4_MR3 0xf1 -#define LPDDR4_PHY_DMIPinPresent 0x1 -#else -#define LPDDR4_MR3 0x31 -#define LPDDR4_PHY_DMIPinPresent 0x0 -#endif - -#ifdef DDR_ONE_RANK -#define LPDDR4_CS 0x1 -#else -#define LPDDR4_CS 0x3 -#endif - -/* PHY training feature */ -#define LPDDR4_HDT_CTL_2D 0xC8 -#define LPDDR4_HDT_CTL_3200_1D 0xC8 -#define LPDDR4_HDT_CTL_400_1D 0xC8 -#define LPDDR4_HDT_CTL_100_1D 0xC8 - -/* 400/100 training seq */ -#define LPDDR4_TRAIN_SEQ_P2 0x121f -#define LPDDR4_TRAIN_SEQ_P1 0x121f -#define LPDDR4_TRAIN_SEQ_P0 0x121f -#define LPDDR4_TRAIN_SEQ_100 0x121f -#define LPDDR4_TRAIN_SEQ_400 0x121f - -/* 2D share & weight */ -#define LPDDR4_2D_WEIGHT 0x1f7f -#define LPDDR4_2D_SHARE 1 -#define LPDDR4_CATRAIN_3200_1d 0 -#define LPDDR4_CATRAIN_400 0 -#define LPDDR4_CATRAIN_100 0 -#define LPDDR4_CATRAIN_3200_2d 0 - -/* MRS parameter */ -/* for LPDDR4 Rtt */ -#define LPDDR4_RTT40 6 -#define LPDDR4_RTT48 5 -#define LPDDR4_RTT60 4 -#define LPDDR4_RTT80 3 -#define LPDDR4_RTT120 2 -#define LPDDR4_RTT240 1 -#define LPDDR4_RTT_DIS 0 - -/* for LPDDR4 Ron */ -#define LPDDR4_RON34 7 -#define LPDDR4_RON40 6 -#define LPDDR4_RON48 5 -#define LPDDR4_RON60 4 -#define LPDDR4_RON80 3 - -#define LPDDR4_PHY_ADDR_RON60 0x1 -#define LPDDR4_PHY_ADDR_RON40 0x3 -#define LPDDR4_PHY_ADDR_RON30 0x7 -#define LPDDR4_PHY_ADDR_RON24 0xf -#define LPDDR4_PHY_ADDR_RON20 0x1f - -/* for read channel */ -#define LPDDR4_RON LPDDR4_RON40 -#define LPDDR4_PHY_RTT 30 -#define LPDDR4_PHY_VREF_VALUE 17 - -/* for write channel */ -#define LPDDR4_PHY_RON 30 -#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 -#define LPDDR4_RTT_DQ LPDDR4_RTT40 -#define LPDDR4_RTT_CA LPDDR4_RTT40 -#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 -#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 -#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) -#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) -#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) -#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \ - (LPDDR4_RTT40)) -#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \ - (LPDDR4_RTT40)) - -#define LPDDR4_MR3_PU_CAL 1 - -#endif /* __LPDDR4_DEFINE_H__ */ diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h deleted file mode 100644 index 0f94945..0000000 --- a/arch/arm/include/asm/arch-imx8m/power-domain.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017 NXP - */ - -#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H -#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H - -struct imx8m_power_domain_platdata { - int resource_id; - int has_pd; - struct power_domain pd; -}; - -#endif diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h deleted file mode 100644 index d328542..0000000 --- a/arch/arm/include/asm/arch-imx8m/sys_proto.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 NXP - */ - -#ifndef __ARCH_IMX8M_SYS_PROTO_H -#define __ARCH_NMX8M_SYS_PROTO_H - -#include <asm/mach-imx/sys_proto.h> - -void set_wdog_reset(struct wdog_regs *wdog); -void enable_tzc380(void); -void restore_boot_params(void); -extern unsigned long rom_pointer[]; -enum boot_device get_boot_device(void); -bool is_usb_boot(void); -#endif diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h deleted file mode 100644 index 5ab48a9..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_CLK_H -#define _LPC32XX_CLK_H - -#include <asm/types.h> - -#define OSC_CLK_FREQUENCY 13000000 -#define RTC_CLK_FREQUENCY 32768 - -/* Clocking and Power Control Registers */ -struct clk_pm_regs { - u32 reserved0[5]; - u32 boot_map; /* Boot Map Control Register */ - u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */ - u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */ - /* Internal Start Signal Sources Registers */ - u32 start_er_int; /* Start Enable Register */ - u32 start_rsr_int; /* Start Raw Status Register */ - u32 start_sr_int; /* Start Status Register */ - u32 start_apr_int; /* Start Activation Polarity Register */ - /* Device Pin Start Signal Sources Registers */ - u32 start_er_pin; /* Start Enable Register */ - u32 start_rsr_pin; /* Start Raw Status Register */ - u32 start_sr_pin; /* Start Status Register */ - u32 start_apr_pin; /* Start Activation Polarity Register */ - /* Clock Control Registers */ - u32 hclkdiv_ctrl; /* HCLK Divider Control Register */ - u32 pwr_ctrl; /* Power Control Register */ - u32 pll397_ctrl; /* PLL397 Control Register */ - u32 osc_ctrl; /* Main Oscillator Control Register */ - u32 sysclk_ctrl; /* SYSCLK Control Register */ - u32 lcdclk_ctrl; /* LCD Clock Control Register */ - u32 hclkpll_ctrl; /* HCLK PLL Control Register */ - u32 reserved1; - u32 adclk_ctrl1; /* ADC Clock Control1 Register */ - u32 usb_ctrl; /* USB Control Register */ - u32 sdramclk_ctrl; /* SDRAM Clock Control Register */ - u32 ddr_lap_nom; /* DDR Calibration Nominal Value */ - u32 ddr_lap_count; /* DDR Calibration Measured Value */ - u32 ddr_cal_delay; /* DDR Calibration Delay Value */ - u32 ssp_ctrl; /* SSP Control Register */ - u32 i2s_ctrl; /* I2S Clock Control Register */ - u32 ms_ctrl; /* Memory Card Control Register */ - u32 reserved2[3]; - u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */ - u32 reserved3[4]; - u32 test_clk; /* Test Clock Selection Register */ - u32 sw_int; /* Software Interrupt Register */ - u32 i2cclk_ctrl; /* I2C Clock Control Register */ - u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */ - u32 adclk_ctrl; /* ADC Clock Control Register */ - u32 pwmclk_ctrl; /* PWM Clock Control Register */ - u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */ - u32 timclk_ctrl1; /* Motor and Timer Clock Control */ - u32 spi_ctrl; /* SPI Control Register */ - u32 flashclk_ctrl; /* NAND Flash Clock Control Register */ - u32 reserved4; - u32 u3clk; /* UART 3 Clock Control Register */ - u32 u4clk; /* UART 4 Clock Control Register */ - u32 u5clk; /* UART 5 Clock Control Register */ - u32 u6clk; /* UART 6 Clock Control Register */ - u32 irdaclk; /* IrDA Clock Control Register */ - u32 uartclk_ctrl; /* UART Clock Control Register */ - u32 dmaclk_ctrl; /* DMA Clock Control Register */ - u32 autoclk_ctrl; /* Autoclock Control Register */ -}; - -/* HCLK Divider Control Register bits */ -#define CLK_HCLK_DDRAM_MASK (0x3 << 7) -#define CLK_HCLK_DDRAM_HALF (0x2 << 7) -#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) -#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) -#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2) -#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2) -#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0) -#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) -#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) -#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) - -/* Power Control Register bits */ -#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) -#define CLK_PWR_EMC_SREFREQ (1 << 9) -#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) -#define CLK_PWR_SDRAM_SREFREQ (1 << 7) -#define CLK_PWR_HIGHCORE_LEVEL (1 << 5) -#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) -#define CLK_PWR_SYSCLKEN_CTRL (1 << 3) -#define CLK_PWR_NORMAL_RUN (1 << 2) -#define CLK_PWR_HIGHCORE_CTRL (1 << 1) -#define CLK_PWR_STOP_MODE (1 << 0) - -/* SYSCLK Control Register bits */ -#define CLK_SYSCLK_PLL397 (1 << 1) -#define CLK_SYSCLK_MUX (1 << 0) - -/* HCLK PLL Control Register bits */ -#define CLK_HCLK_PLL_OPERATING (1 << 16) -#define CLK_HCLK_PLL_BYPASS (1 << 15) -#define CLK_HCLK_PLL_DIRECT (1 << 14) -#define CLK_HCLK_PLL_FEEDBACK (1 << 13) -#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) -#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) -#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) -#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11) -#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11) -#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9) -#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9) -#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9) -#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9) -#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) -#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) -#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) -#define CLK_HCLK_PLL_LOCKED (1 << 0) - -/* Ethernet MAC Clock Control Register bits */ -#define CLK_MAC_RMII (0x3 << 3) -#define CLK_MAC_MII (0x1 << 3) -#define CLK_MAC_MASTER (1 << 2) -#define CLK_MAC_SLAVE (1 << 1) -#define CLK_MAC_REG (1 << 0) - -/* I2C Clock Control Register bits */ -#define CLK_I2C2_ENABLE (1 << 1) -#define CLK_I2C1_ENABLE (1 << 0) - -/* Timer Clock Control1 Register bits */ -#define CLK_TIMCLK_MOTOR (1 << 6) -#define CLK_TIMCLK_TIMER3 (1 << 5) -#define CLK_TIMCLK_TIMER2 (1 << 4) -#define CLK_TIMCLK_TIMER1 (1 << 3) -#define CLK_TIMCLK_TIMER0 (1 << 2) -#define CLK_TIMCLK_TIMER5 (1 << 1) -#define CLK_TIMCLK_TIMER4 (1 << 0) - -/* Timer Clock Control Register bits */ -#define CLK_TIMCLK_HSTIMER (1 << 1) -#define CLK_TIMCLK_WATCHDOG (1 << 0) - -/* UART Clock Control Register bits */ -#define CLK_UART(n) (1 << ((n) - 3)) - -/* UARTn Clock Select Registers bits */ -#define CLK_UART_HCLK (1 << 16) -#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) -#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0) - -/* DMA Clock Control Register bits */ -#define CLK_DMA_ENABLE (1 << 0) - -/* NAND Clock Control Register bits */ -#define CLK_NAND_SLC (1 << 0) -#define CLK_NAND_MLC (1 << 1) -#define CLK_NAND_SLC_SELECT (1 << 2) -#define CLK_NAND_MLC_INT (1 << 5) - -/* SSP Clock Control Register bits */ -#define CLK_SSP0_ENABLE_CLOCK (1 << 0) - -/* SDRAMCLK register bits */ -#define CLK_SDRAM_DDR_SEL (1 << 1) - -/* USB control register definitions */ -#define CLK_USBCTRL_PLL_STS (1 << 0) -#define CLK_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) -#define CLK_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) -#define CLK_USBCTRL_PLL_PWRUP (1 << 16) -#define CLK_USBCTRL_CLK_EN1 (1 << 17) -#define CLK_USBCTRL_CLK_EN2 (1 << 18) -#define CLK_USBCTRL_BUS_KEEPER (0x1 << 19) -#define CLK_USBCTRL_USBHSTND_EN (1 << 21) -#define CLK_USBCTRL_USBDVND_EN (1 << 22) -#define CLK_USBCTRL_HCLK_EN (1 << 24) - -unsigned int get_sys_clk_rate(void); -unsigned int get_hclk_pll_rate(void); -unsigned int get_hclk_clk_div(void); -unsigned int get_hclk_clk_rate(void); -unsigned int get_periph_clk_div(void); -unsigned int get_periph_clk_rate(void); -unsigned int get_sdram_clk_rate(void); - -#endif /* _LPC32XX_CLK_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h deleted file mode 100644 index 0836091..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common definitions for LPC32XX board configurations - * - * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_CONFIG_H -#define _LPC32XX_CONFIG_H - - -/* Basic CPU architecture */ - -/* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ - (CONFIG_SYS_LPC32XX_UART == 7) -#if !defined(CONFIG_LPC32XX_HSUART) -#define CONFIG_LPC32XX_HSUART -#endif -#endif - -#if !defined(CONFIG_SYS_NS16550_CLK) -#define CONFIG_SYS_NS16550_CLK 13000000 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } - -/* Ethernet */ -#define LPC32XX_ETH_BASE ETHERNET_BASE - -/* NAND */ -#if defined(CONFIG_NAND_LPC32XX_SLC) -#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 -#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 - -#if !defined(CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE -#endif - -#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#else -#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" -#endif - -#define CONFIG_SYS_NAND_ECCSIZE 0x100 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#endif /* CONFIG_NAND_LPC32XX_SLC */ - -/* NOR Flash */ - -/* USB OHCI */ -#if defined(CONFIG_USB_OHCI_LPC32XX) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" -#endif - -#endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h deleted file mode 100644 index 7e0b781..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_CPU_H -#define _LPC32XX_CPU_H - -/* LPC32XX Memory map */ - -/* AHB physical base addresses */ -#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ -#define SSP0_BASE 0x20084000 /* SSP0 registers base */ -#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ -#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ -#define DMA_BASE 0x31000000 /* DMA controller registers base */ -#define USB_BASE 0x31020000 /* USB registers base */ -#define LCD_BASE 0x31040000 /* LCD registers base */ -#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ -#define EMC_BASE 0x31080000 /* EMC configuration registers base */ - -/* FAB peripherals base addresses */ -#define CLK_PM_BASE 0x40004000 /* System control registers base */ -#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ -#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ -#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ -#define RTC_BASE 0x40024000 /* RTC registers base */ -#define GPIO_BASE 0x40028000 /* GPIO registers base */ -#define MUX_BASE 0x40028000 /* MUX registers base */ -#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ -#define TIMER0_BASE 0x40044000 /* Timer0 registers base */ -#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ -#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ - -/* APB peripherals base addresses */ -#define UART3_BASE 0x40080000 /* UART 3 registers base */ -#define UART4_BASE 0x40088000 /* UART 4 registers base */ -#define UART5_BASE 0x40090000 /* UART 5 registers base */ -#define UART6_BASE 0x40098000 /* UART 6 registers base */ -#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ -#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */ - -/* External SDRAM Memory Bank base addresses */ -#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ -#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ - -/* External Static Memory Bank base addresses */ -#define EMC_CS0_BASE 0xE0000000 -#define EMC_CS1_BASE 0xE1000000 -#define EMC_CS2_BASE 0xE2000000 -#define EMC_CS3_BASE 0xE3000000 - -#endif /* _LPC32XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/dma.h b/arch/arm/include/asm/arch-lpc32xx/dma.h deleted file mode 100644 index 8775491..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/dma.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LPC32xx DMA Controller Interface - * - * Copyright (C) 2008 by NXP Semiconductors - * @Author: Kevin Wells - * @Descr: Definitions for LPC3250 chip - * @References: NXP LPC3250 User's Guide - */ - -#ifndef _LPC32XX_DMA_H -#define _LPC32XX_DMA_H - -#include <common.h> - -/* - * DMA linked list structure used with a channel's LLI register; - * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3 - * tables 84, 85, 86 & 87 for details. - */ -struct lpc32xx_dmac_ll { - u32 dma_src; - u32 dma_dest; - u32 next_lli; - u32 next_ctrl; -}; - -/* control register definitions */ -#define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */ -#define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */ -#define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */ -#define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */ -#define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */ -#define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */ -#define DMAC_CHAN_DEST_BURST_1 0 -#define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */ -#define DMAC_CHAN_SRC_BURST_1 0 -#define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */ - -/* - * config_ch register definitions - * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller - * DMAC_DEST_PERIP: Macro for loading destination peripheral - * DMAC_SRC_PERIP: Macro for loading source peripheral - */ -#define DMAC_CHAN_FLOW_D_M2P (0x1 << 11) -#define DMAC_CHAN_FLOW_D_P2M (0x2 << 11) -#define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6) -#define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1) - -/* - * config_ch register definitions - * (source and destination peripheral ID numbers). - * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros. - */ -#define DMA_PERID_NAND1 1 - -/* Channel enable bit */ -#define DMAC_CHAN_ENABLE (1 << 0) - -int lpc32xx_dma_get_channel(void); -int lpc32xx_dma_start_xfer(unsigned int channel, - const struct lpc32xx_dmac_ll *desc, u32 config); -int lpc32xx_dma_wait_status(unsigned int channel); - -#endif /* _LPC32XX_DMA_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h deleted file mode 100644 index 20698a3..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/emc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_EMC_H -#define _LPC32XX_EMC_H - -#include <asm/types.h> - -/* EMC Registers */ -struct emc_regs { - u32 ctrl; /* Controls operation of the EMC */ - u32 status; /* Provides EMC status information */ - u32 config; /* Configures operation of the EMC */ - u32 reserved0[5]; - u32 control; /* Controls dyn memory operation */ - u32 refresh; /* Configures dyn memory refresh operation */ - u32 read_config; /* Configures the dyn memory read strategy */ - u32 reserved1; - u32 t_rp; /* Precharge command period */ - u32 t_ras; /* Active to precharge command period */ - u32 t_srex; /* Self-refresh exit time */ - u32 reserved2[2]; - u32 t_wr; /* Write recovery time */ - u32 t_rc; /* Active to active command period */ - u32 t_rfc; /* Auto-refresh period */ - u32 t_xsr; /* Exit self-refresh to active command time */ - u32 t_rrd; /* Active bank A to active bank B latency */ - u32 t_mrd; /* Load mode register to active command time */ - u32 t_cdlr; /* Last data in to read command time */ - u32 reserved3[8]; - u32 extended_wait; /* time for static memory rd/wr transfers */ - u32 reserved4[31]; - u32 config0; /* Configuration information for the SDRAM */ - u32 rascas0; /* RAS and CAS latencies for the SDRAM */ - u32 reserved5[6]; - u32 config1; /* Configuration information for the SDRAM */ - u32 rascas1; /* RAS and CAS latencies for the SDRAM */ - u32 reserved6[54]; - struct emc_stat_t { - u32 config; /* Static memory configuration */ - u32 waitwen; /* Delay from chip select to write enable */ - u32 waitoen; /* Delay to output enable */ - u32 waitrd; /* Delay to a read access */ - u32 waitpage; /* Delay for async page mode read */ - u32 waitwr; /* Delay to a write access */ - u32 waitturn; /* Number of bus turnaround cycles */ - u32 reserved; - } stat[4]; - u32 reserved7[96]; - struct emc_ahb_t { - u32 control; /* Control register for AHB */ - u32 status; /* Status register for AHB */ - u32 timeout; /* Timeout register for AHB */ - u32 reserved[5]; - } ahb[5]; -}; - -/* Static Memory Configuration Register bits */ -#define EMC_STAT_CONFIG_WP (1 << 20) -#define EMC_STAT_CONFIG_EW (1 << 8) -#define EMC_STAT_CONFIG_PB (1 << 7) -#define EMC_STAT_CONFIG_PC (1 << 6) -#define EMC_STAT_CONFIG_PM (1 << 3) -#define EMC_STAT_CONFIG_32BIT (2 << 0) -#define EMC_STAT_CONFIG_16BIT (1 << 0) -#define EMC_STAT_CONFIG_8BIT (0 << 0) - -/* Static Memory Delay Registers */ -#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) -#define EMC_STAT_WAITOEN(n) ((n) & 0x0F) -#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) -#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) -#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) -#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) - -/* EMC settings for DRAM */ -struct emc_dram_settings { - u32 cmddelay; - u32 config0; - u32 rascas0; - u32 rdconfig; - u32 trp; - u32 tras; - u32 tsrex; - u32 twr; - u32 trc; - u32 trfc; - u32 txsr; - u32 trrd; - u32 tmrd; - u32 tcdlr; - u32 refresh; - u32 mode; - u32 emode; -}; - -#endif /* _LPC32XX_EMC_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h deleted file mode 100644 index 93e7a88..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LPC32xx GPIO interface - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> - */ - -/** - * GPIO Register map for LPC32xx - */ - -struct gpio_regs { - u32 p3_inp_state; - u32 p3_outp_set; - u32 p3_outp_clr; - u32 p3_outp_state; - /* Watch out! the following are shared between p2 and p3 */ - u32 p2_p3_dir_set; - u32 p2_p3_dir_clr; - u32 p2_p3_dir_state; - /* Now back to 'one register for one port' */ - u32 p2_inp_state; - u32 p2_outp_set; - u32 p2_outp_clr; - u32 reserved1[6]; - u32 p0_inp_state; - u32 p0_outp_set; - u32 p0_outp_clr; - u32 p0_outp_state; - u32 p0_dir_set; - u32 p0_dir_clr; - u32 p0_dir_state; - u32 reserved2; - u32 p1_inp_state; - u32 p1_outp_set; - u32 p1_outp_clr; - u32 p1_outp_state; - u32 p1_dir_set; - u32 p1_dir_clr; - u32 p1_dir_state; -}; diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h deleted file mode 100644 index 762bbee..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LPC32xx GPIO interface macro for pin mapping. - * - * (C) Copyright 2015 DENX Software Engineering GmbH - * Written-by: Sylvain Lemieux <slemieux@@tycoint.com> - */ - -#ifndef _LPC32XX_GPIO_GRP_H -#define _LPC32XX_GPIO_GRP_H - -/* - * Macro to map the pin for the lpc32xx_gpio driver. - * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159; - * mapping is done per register, as group of 32. - * (see drivers/gpio/lpc32xx_gpio.c for details). - * - macros can be use with the following pins: - * P0.0 - P0.7 - * P1.0 - P1.23 - * P2.0 - P2.12 - * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28 - * P3 GPO_0 - GPO_23 - * P3 GPIO_0 - GPIO_5 (output register only) - */ -#define LPC32XX_GPIO_P0_GRP 0 -#define LPC32XX_GPIO_P1_GRP 32 -#define LPC32XX_GPIO_P2_GRP 64 -#define LPC32XX_GPO_P3_GRP 96 -#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25) -#define LPC32XX_GPI_P3_GRP 128 - -/* - * A specific GPIO can be selected with this macro - * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1) - * See the LPC32x0 User's guide for GPIO group numbers - */ -#define LPC32XX_GPIO(x, y) ((x) + (y)) - -#endif /* _LPC32XX_GPIO_GRP_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/i2c.h b/arch/arm/include/asm/arch-lpc32xx/i2c.h deleted file mode 100644 index 5301d4c..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/i2c.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef _LPC32XX_I2C_H -#define _LPC32XX_I2C_H - -#include <common.h> -#include <asm/types.h> - -/* i2c register set */ -struct lpc32xx_i2c_base { - union { - u32 rx; - u32 tx; - }; - u32 stat; - u32 ctrl; - u32 clk_hi; - u32 clk_lo; - u32 adr; - u32 rxfl; - u32 txfl; - u32 rxb; - u32 txb; - u32 stx; - u32 stxfl; -}; - -#ifdef CONFIG_DM_I2C -enum { - I2C_0, I2C_1, I2C_2, -}; - -struct lpc32xx_i2c_dev { - struct lpc32xx_i2c_base *base; - int index; - uint speed; -}; -#endif /* CONFIG_DM_I2C */ -#endif /* _LPC32XX_I2C_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h deleted file mode 100644 index d661e82..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/mux.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LPC32xx MUX interface - * - * (C) Copyright 2015 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> - */ - -/** - * MUX register map for LPC32xx - */ - -struct mux_regs { - u32 reserved1[10]; - u32 p2_mux_set; - u32 p2_mux_clr; - u32 p2_mux_state; - u32 reserved2[51]; - u32 p_mux_set; - u32 p_mux_clr; - u32 p_mux_state; - u32 reserved3; - u32 p3_mux_set; - u32 p3_mux_clr; - u32 p3_mux_state; - u32 reserved4; - u32 p0_mux_set; - u32 p0_mux_clr; - u32 p0_mux_state; - u32 reserved5; - u32 p1_mux_set; - u32 p1_mux_clr; - u32 p1_mux_state; -}; diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h deleted file mode 100644 index 4675dc3..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_SYS_PROTO_H -#define _LPC32XX_SYS_PROTO_H - -#include <asm/arch/emc.h> - -void lpc32xx_uart_init(unsigned int uart_id); -void lpc32xx_dma_init(void); -void lpc32xx_mac_init(void); -void lpc32xx_mlc_nand_init(void); -void lpc32xx_slc_nand_init(void); -void lpc32xx_i2c_init(unsigned int devnum); -void lpc32xx_ssp_init(void); -void lpc32xx_usb_init(void); -#if defined(CONFIG_SPL_BUILD) -void ddr_init(const struct emc_dram_settings *dram); -#endif -#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h deleted file mode 100644 index 302bd6b..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/timer.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_TIMER_H -#define _LPC32XX_TIMER_H - -#include <asm/types.h> - -/* Timer/Counter Registers */ -struct timer_regs { - u32 ir; /* Interrupt Register */ - u32 tcr; /* Timer Control Register */ - u32 tc; /* Timer Counter */ - u32 pr; /* Prescale Register */ - u32 pc; /* Prescale Counter */ - u32 mcr; /* Match Control Register */ - u32 mr[4]; /* Match Registers */ - u32 ccr; /* Capture Control Register */ - u32 cr[4]; /* Capture Registers */ - u32 emr; /* External Match Register */ - u32 reserved[12]; - u32 ctcr; /* Count Control Register */ -}; - -/* Timer/Counter Interrupt Register bits */ -#define TIMER_IR_CR(n) (1 << ((n) + 4)) -#define TIMER_IR_MR(n) (1 << (n)) - -/* Timer/Counter Timer Control Register bits */ -#define TIMER_TCR_COUNTER_RESET (1 << 1) -#define TIMER_TCR_COUNTER_ENABLE (1 << 0) -#define TIMER_TCR_COUNTER_DISABLE (0 << 0) - -/* Timer/Counter Match Control Register bits */ -#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) -#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) -#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) - -/* Timer/Counter Capture Control Register bits */ -#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) -#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) -#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) - -/* Timer/Counter External Match Register bits */ -#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) -#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) -#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) -#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) -#define TIMER_EMR_EM(n) (1 << (n)) - -/* Timer/Counter Count Control Register bits */ -#define TIMER_CTCR_INPUT(n) ((n) << 2) -#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) -#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) -#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) -#define TIMER_CTCR_MODE_TIMER (0x0 << 0) - -#endif /* _LPC32XX_TIMER_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h deleted file mode 100644 index 8ffd867..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/uart.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_UART_H -#define _LPC32XX_UART_H - -#include <asm/types.h> - -/* 14-clock UART Registers */ -struct hsuart_regs { - union { - u32 rx; /* Receiver FIFO */ - u32 tx; /* Transmitter FIFO */ - }; - u32 level; /* FIFO Level Register */ - u32 iir; /* Interrupt ID Register */ - u32 ctrl; /* Control Register */ - u32 rate; /* Rate Control Register */ -}; - -/* 14-clock UART Receiver FIFO Register bits */ -#define HSUART_RX_BREAK (1 << 10) -#define HSUART_RX_ERROR (1 << 9) -#define HSUART_RX_EMPTY (1 << 8) -#define HSUART_RX_DATA (0xff << 0) - -/* 14-clock UART Level Register bits */ -#define HSUART_LEVEL_TX (0xff << 8) -#define HSUART_LEVEL_RX (0xff << 0) - -/* 14-clock UART Interrupt Identification Register bits */ -#define HSUART_IIR_TX_INT_SET (1 << 6) -#define HSUART_IIR_RX_OE (1 << 5) -#define HSUART_IIR_BRK (1 << 4) -#define HSUART_IIR_FE (1 << 3) -#define HSUART_IIR_RX_TIMEOUT (1 << 2) -#define HSUART_IIR_RX_TRIG (1 << 1) -#define HSUART_IIR_TX (1 << 0) - -/* 14-clock UART Control Register bits */ -#define HSUART_CTRL_HRTS_INV (1 << 21) -#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19) -#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19) -#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19) -#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19) -#define HSUART_CTRL_HRTS_EN (1 << 18) -#define HSUART_CTRL_TMO_16 (0x3 << 16) -#define HSUART_CTRL_TMO_8 (0x2 << 16) -#define HSUART_CTRL_TMO_4 (0x1 << 16) -#define HSUART_CTRL_TMO_DISABLED (0x0 << 16) -#define HSUART_CTRL_HCTS_INV (1 << 15) -#define HSUART_CTRL_HCTS_EN (1 << 14) -#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) -#define HSUART_CTRL_HSU_BREAK (1 << 8) -#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7) -#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6) -#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5) -#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2) -#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0) -#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0) -#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0) -#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0) - -/* UART Control Registers */ -struct uart_ctrl_regs { - u32 ctrl; /* Control Register */ - u32 clkmode; /* Clock Mode Register */ - u32 loop; /* Loopback Control Register */ -}; - -/* UART Control Register bits */ -#define UART_CTRL_UART3_MD_CTRL (1 << 11) -#define UART_CTRL_HDPX_INV (1 << 10) -#define UART_CTRL_HDPX_EN (1 << 9) -#define UART_CTRL_UART6_IRDA (1 << 5) -#define UART_CTRL_IR_TX6_INV (1 << 4) -#define UART_CTRL_IR_RX6_INV (1 << 3) -#define UART_CTRL_IR_RX_LENGTH (1 << 2) -#define UART_CTRL_IR_TX_LENGTH (1 << 1) -#define UART_CTRL_UART5_USB_MODE (1 << 0) - -/* UART Clock Mode Register bits */ -#define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) -#define UART_CLKMODE_STAT (1 << 14) -#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) -#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) -#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) -#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) - -/* UART Loopback Control Register bits */ -#define UART_LOOPBACK(n) (1 << ((n) - 1)) - -#endif /* _LPC32XX_UART_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h deleted file mode 100644 index dd0fc16..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/wdt.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - */ - -#ifndef _LPC32XX_WDT_H -#define _LPC32XX_WDT_H - -#include <asm/types.h> - -/* Watchdog Timer Registers */ -struct wdt_regs { - u32 isr; /* Interrupt Status Register */ - u32 ctrl; /* Control Register */ - u32 counter; /* Counter Value Register */ - u32 mctrl; /* Match Control Register */ - u32 match0; /* Match 0 Register */ - u32 emr; /* External Match Control Register */ - u32 pulse; /* Reset Pulse Length Register */ - u32 res; /* Reset Source Register */ -}; - -/* Watchdog Timer Control Register bits */ -#define WDTIM_CTRL_PAUSE_EN (1 << 2) -#define WDTIM_CTRL_RESET_COUNT (1 << 1) -#define WDTIM_CTRL_COUNT_ENAB (1 << 0) - -/* Watchdog Timer Match Control Register bits */ -#define WDTIM_MCTRL_RESFRC2 (1 << 6) -#define WDTIM_MCTRL_RESFRC1 (1 << 5) -#define WDTIM_MCTRL_M_RES2 (1 << 4) -#define WDTIM_MCTRL_M_RES1 (1 << 3) -#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) -#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) -#define WDTIM_MCTRL_MR0_INT (1 << 0) - -#endif /* _LPC32XX_WDT_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h deleted file mode 100644 index bf67df5..0000000 --- a/arch/arm/include/asm/arch-ls102xa/clock.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - */ - -#ifndef __ASM_ARCH_LS102XA_CLOCK_H_ -#define __ASM_ARCH_LS102XA_CLOCK_H_ - -#include <common.h> - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_I2C_CLK, - MXC_DSPI_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -ulong get_ddr_freq(ulong); -uint get_svr(void); - -#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h deleted file mode 100644 index 9705378..0000000 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014, Freescale Semiconductor - */ - -#ifndef _ASM_ARMV7_LS102XA_CONFIG_ -#define _ASM_ARMV7_LS102XA_CONFIG_ - -#define OCRAM_BASE_ADDR 0x10000000 -#define OCRAM_SIZE 0x00010000 -#define OCRAM_BASE_S_ADDR 0x10010000 -#define OCRAM_S_SIZE 0x00010000 - -#define CONFIG_SYS_IMMR 0x01000000 -#define CONFIG_SYS_DCSRBAR 0x20000000 - -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) -#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) - -#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) -#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) -#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) -#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) -#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) -#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) - -#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 -#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 -#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) - -#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) - -#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) -#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) -#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) - -#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) - -#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) -#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) - -#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) - -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) - -#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL -#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL -#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL -#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ -/* - * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) - * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. - */ -#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ - CONFIG_SYS_PCIE1_VIRT_ADDR) -#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ - CONFIG_SYS_PCIE2_VIRT_ADDR) - -/* SATA */ -#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#ifdef CONFIG_DDR_SPD -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE -#endif - -#define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_ESDHC_BE -#define CONFIG_SYS_FSL_WDOG_BE -#define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_QSPI_BE -#define CONFIG_SYS_FSL_DCU_BE -#define CONFIG_SYS_FSL_SEC_MON_LE -#define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SFP_BE -#define CONFIG_SYS_FSL_SRK_LE - -#define DCU_LAYER_MAX_NUM 16 - -#ifdef CONFIG_ARCH_LS1021A -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#else -#error SoC not defined -#endif - -#define FSL_IFC_COMPAT "fsl,ifc" -#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" -#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" - -#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h deleted file mode 100644 index d99a6f3..0000000 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_SERDES_H -#define __FSL_SERDES_H - -#include <config.h> - -enum srds_prtcl { - /* - * Nobody will check whether the device 'NONE' has been configured, - * So use it to indicate if the serdes_prtcl_map has been initialized. - */ - NONE = 0, - PCIE1, - PCIE2, - SATA1, - SGMII_TSEC1, - SGMII_TSEC2, -}; - -enum srds { - FSL_SRDS_1 = 0, - FSL_SRDS_2 = 1, -}; - -int is_serdes_configured(enum srds_prtcl device); -void fsl_serdes_init(void); -const char *serdes_clock_to_string(u32 clock); - -int serdes_get_first_lane(u32 sd, enum srds_prtcl device); -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); - -#endif /* __FSL_SERDES_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h deleted file mode 100644 index dad181e..0000000 --- a/arch/arm/include/asm/arch-ls102xa/gpio.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -/* - * Dummy header file to enable CONFIG_OF_CONTROL. - * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. - * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable - * OF_CONTROL must have arch/gpio.h. - */ - -#ifndef __ASM_ARCH_LS102XA_GPIO_H_ -#define __ASM_ARCH_LS102XA_GPIO_H_ - -#endif diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h deleted file mode 100644 index f2ba182..0000000 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ /dev/null @@ -1,432 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_LS102XA_IMMAP_H_ -#define __ASM_ARCH_LS102XA_IMMAP_H_ -#include <fsl_immap.h> - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) -#define SVR_MIN(svr) (((svr) >> 0) & 0xf) -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) -#define IS_E_PROCESSOR(svr) (svr & 0x80000) -#define IS_SVR_REV(svr, maj, min) \ - ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) - -#define SOC_VER_SLS1020 0x00 -#define SOC_VER_LS1020 0x10 -#define SOC_VER_LS1021 0x11 -#define SOC_VER_LS1022 0x12 - -#define SOC_MAJOR_VER_1_0 0x1 -#define SOC_MAJOR_VER_2_0 0x2 - -#define CCSR_BRR_OFFSET 0xe4 -#define CCSR_SCRATCHRW1_OFFSET 0x200 - -#define RCWSR0_SYS_PLL_RAT_SHIFT 25 -#define RCWSR0_SYS_PLL_RAT_MASK 0x1f -#define RCWSR0_MEM_PLL_RAT_SHIFT 16 -#define RCWSR0_MEM_PLL_RAT_MASK 0x3f - -#define RCWSR4_SRDS1_PRTCL_SHIFT 24 -#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 - -#define TIMER_COMP_VAL 0xffffffffffffffffull -#define ARCH_TIMER_CTRL_ENABLE (1 << 0) -#define SYS_COUNTER_CTRL_ENABLE (1 << 24) - -#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 -#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 - -#define DCFG_DCSR_PORCR1 0 - -/* - * Define default values for some CCSR macros to make header files cleaner - * - * To completely disable CCSR relocation in a board header file, define - * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. - */ - -#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." -#endif - -#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 -#endif - -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR -#endif - -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf -#else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 -#endif -#endif - -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR -#endif - -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) - -struct sys_info { - unsigned long freq_processor[CONFIG_MAX_CPUS]; - unsigned long freq_systembus; - unsigned long freq_ddrbus; - unsigned long freq_localbus; -}; - -#define CCSR_DEVDISR1_QE 0x00000001 - -/* Device Configuration and Pin Control */ -struct ccsr_gur { - u32 porsr1; /* POR status 1 */ - u32 porsr2; /* POR status 2 */ - u8 res_008[0x20-0x8]; - u32 gpporcr1; /* General-purpose POR configuration */ - u32 gpporcr2; - u32 dcfg_fusesr; /* Fuse status register */ - u8 res_02c[0x70-0x2c]; - u32 devdisr; /* Device disable control */ - u32 devdisr2; /* Device disable control 2 */ - u32 devdisr3; /* Device disable control 3 */ - u32 devdisr4; /* Device disable control 4 */ - u32 devdisr5; /* Device disable control 5 */ - u8 res_084[0x94-0x84]; - u32 coredisru; /* uppper portion for support of 64 cores */ - u32 coredisrl; /* lower portion for support of 64 cores */ - u8 res_09c[0xa4-0x9c]; - u32 svr; /* System version */ - u8 res_0a8[0xb0-0xa8]; - u32 rstcr; /* Reset control */ - u32 rstrqpblsr; /* Reset request preboot loader status */ - u8 res_0b8[0xc0-0xb8]; - u32 rstrqmr1; /* Reset request mask */ - u8 res_0c4[0xc8-0xc4]; - u32 rstrqsr1; /* Reset request status */ - u8 res_0cc[0xd4-0xcc]; - u32 rstrqwdtmrl; /* Reset request WDT mask */ - u8 res_0d8[0xdc-0xd8]; - u32 rstrqwdtsrl; /* Reset request WDT status */ - u8 res_0e0[0xe4-0xe0]; - u32 brrl; /* Boot release */ - u8 res_0e8[0x100-0xe8]; - u32 rcwsr[16]; /* Reset control word status */ -#define RCW_SB_EN_REG_INDEX 7 -#define RCW_SB_EN_MASK 0x00200000 - u8 res_140[0x200-0x140]; - u32 scratchrw[4]; /* Scratch Read/Write */ - u8 res_210[0x300-0x210]; - u32 scratchw1r[4]; /* Scratch Read (Write once) */ - u8 res_310[0x400-0x310]; - u32 crstsr; - u8 res_404[0x550-0x404]; - u32 sataliodnr; - u8 res_554[0x604-0x554]; - u32 pamubypenr; - u32 dmacr1; - u8 res_60c[0x740-0x60c]; /* add more registers when needed */ - u32 tp_ityp[64]; /* Topology Initiator Type Register */ - struct { - u32 upper; - u32 lower; - } tp_cluster[1]; /* Core Cluster n Topology Register */ - u8 res_848[0xe60-0x848]; - u32 ddrclkdr; - u8 res_e60[0xe68-0xe64]; - u32 ifcclkdr; - u8 res_e68[0xe80-0xe6c]; - u32 sdhcpcr; -}; - -#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 -#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 -#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 -#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 -#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 -#define SCFG_PIXCLKCR_PXCKEN 0x80000000 -#define SCFG_QSPI_CLKSEL 0x50100000 -#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 -#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 -#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 -#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 -#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 -#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 -#define SCFG_ENDIANCR_LE 0x80000000 -#define SCFG_DPSLPCR_WDRR_EN 0x00000001 -#define SCFG_PMCINTECR_LPUART 0x40000000 -#define SCFG_PMCINTECR_FTM 0x20000000 -#define SCFG_PMCINTECR_GPIO 0x10000000 -#define SCFG_PMCINTECR_IRQ0 0x08000000 -#define SCFG_PMCINTECR_IRQ1 0x04000000 -#define SCFG_PMCINTECR_ETSECRXG0 0x00800000 -#define SCFG_PMCINTECR_ETSECRXG1 0x00400000 -#define SCFG_PMCINTECR_ETSECERRG0 0x00080000 -#define SCFG_PMCINTECR_ETSECERRG1 0x00040000 -#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 - -#define SCFG_BASE 0x01570000 -#define SCFG_USB3PRM1CR 0x070 -#define SCFG_USB_TXVREFTUNE 0x9 -#define SCFG_USB_SQRXTUNE_MASK 0x7 -#define SCFG_USB3PRM2CR 0x074 -#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00 -#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00 - -#define USB_PHY_BASE 0x08510000 -#define USB_PHY_RX_OVRD_IN_HI 0x200c -#define USB_PHY_RX_EQ_VAL_1 0x0000 -#define USB_PHY_RX_EQ_VAL_2 0x8000 -#define USB_PHY_RX_EQ_VAL_3 0x8004 -#define USB_PHY_RX_EQ_VAL_4 0x800C - -/* Supplemental Configuration Unit */ -struct ccsr_scfg { - u32 dpslpcr; - u32 resv0[2]; - u32 etsecclkdpslpcr; - u32 resv1[5]; - u32 fuseovrdcr; - u32 pixclkcr; - u32 resv2[5]; - u32 spimsicr; - u32 resv3[6]; - u32 pex1pmwrcr; - u32 pex1pmrdsr; - u32 resv4[3]; - u32 usb3prm1cr; - u32 usb4prm2cr; - u32 pex1rdmsgpldlsbsr; - u32 pex1rdmsgpldmsbsr; - u32 pex2rdmsgpldlsbsr; - u32 pex2rdmsgpldmsbsr; - u32 pex1rdmmsgrqsr; - u32 pex2rdmmsgrqsr; - u32 spimsiclrcr; - u32 pexmscportsr[2]; - u32 pex2pmwrcr; - u32 resv5[24]; - u32 mac1_streamid; - u32 mac2_streamid; - u32 mac3_streamid; - u32 pex1_streamid; - u32 pex2_streamid; - u32 dma_streamid; - u32 sata_streamid; - u32 usb3_streamid; - u32 qe_streamid; - u32 sdhc_streamid; - u32 adma_streamid; - u32 letechsftrstcr; - u32 core0_sft_rst; - u32 core1_sft_rst; - u32 resv6[1]; - u32 usb_hi_addr; - u32 etsecclkadjcr; - u32 sai_clk; - u32 resv7[1]; - u32 dcu_streamid; - u32 usb2_streamid; - u32 ftm_reset; - u32 altcbar; - u32 qspi_cfg; - u32 pmcintecr; - u32 pmcintlecr; - u32 pmcintsr; - u32 qos1; - u32 qos2; - u32 qos3; - u32 cci_cfg; - u32 endiancr; - u32 etsecdmamcr; - u32 usb3prm3cr; - u32 resv9[1]; - u32 debug_streamid; - u32 resv10[5]; - u32 snpcnfgcr; - u32 hrstcr; - u32 intpcr; - u32 resv12[20]; - u32 scfgrevcr; - u32 coresrencr; - u32 pex2pmrdsr; - u32 eddrtqcfg; - u32 ddrc2cr; - u32 ddrc3cr; - u32 ddrc4cr; - u32 ddrgcr; - u32 resv13[120]; - u32 qeioclkcr; - u32 etsecmcr; - u32 sdhciovserlcr; - u32 resv14[61]; - u32 sparecr[8]; - u32 resv15[248]; - u32 core0sftrstsr; - u32 clusterpmcr; -}; - -/* Clocking */ -struct ccsr_clk { - struct { - u32 clkcncsr; /* core cluster n clock control status */ - u8 res_004[0x1c]; - } clkcsr[2]; - u8 res_040[0x7c0]; /* 0x100 */ - struct { - u32 pllcngsr; - u8 res_804[0x1c]; - } pllcgsr[2]; - u8 res_840[0x1c0]; - u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ - u8 res_a04[0x1fc]; - u32 pllpgsr; /* 0xc00 Platform PLL General Status */ - u8 res_c04[0x1c]; - u32 plldgsr; /* 0xc20 DDR PLL General Status */ - u8 res_c24[0x3dc]; -}; - -/* System Counter */ -struct sctr_regs { - u32 cntcr; - u32 cntsr; - u32 cntcv1; - u32 cntcv2; - u32 resv1[4]; - u32 cntfid0; - u32 cntfid1; - u32 resv2[1002]; - u32 counterid[12]; -}; - -#define MAX_SERDES 1 -#define SRDS_MAX_LANES 4 -#define SRDS_MAX_BANK 2 - -#define SRDS_RSTCTL_RST 0x80000000 -#define SRDS_RSTCTL_RSTDONE 0x40000000 -#define SRDS_RSTCTL_RSTERR 0x20000000 -#define SRDS_RSTCTL_SWRST 0x10000000 -#define SRDS_RSTCTL_SDEN 0x00000020 -#define SRDS_RSTCTL_SDRST_B 0x00000040 -#define SRDS_RSTCTL_PLLRST_B 0x00000080 -#define SRDS_PLLCR0_POFF 0x80000000 -#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 -#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 -#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 -#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 -#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 -#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 -#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 -#define SRDS_PLLCR0_PLL_LCK 0x00800000 -#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 -#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 -#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 -#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 -#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 -#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 -#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 -#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 - -struct ccsr_serdes { - struct { - u32 rstctl; /* Reset Control Register */ - - u32 pllcr0; /* PLL Control Register 0 */ - - u32 pllcr1; /* PLL Control Register 1 */ - u32 res_0c; /* 0x00c */ - u32 pllcr3; - u32 pllcr4; - u8 res_18[0x20-0x18]; - } bank[2]; - u8 res_40[0x90-0x40]; - u32 srdstcalcr; /* 0x90 TX Calibration Control */ - u8 res_94[0xa0-0x94]; - u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ - u8 res_a4[0xb0-0xa4]; - u32 srdsgr0; /* 0xb0 General Register 0 */ - u8 res_b4[0xe0-0xb4]; - u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ - u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ - u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ - u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ - u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ - u8 res_f4[0x100-0xf4]; - struct { - u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ - u8 res_104[0x120-0x104]; - } srdslnpssr[4]; - u8 res_180[0x300-0x180]; - u32 srdspexeqcr; - u32 srdspexeqpcr[11]; - u8 res_330[0x400-0x330]; - u32 srdspexapcr; - u8 res_404[0x440-0x404]; - u32 srdspexbpcr; - u8 res_444[0x800-0x444]; - struct { - u32 gcr0; /* 0x800 General Control Register 0 */ - u32 gcr1; /* 0x804 General Control Register 1 */ - u32 gcr2; /* 0x808 General Control Register 2 */ - u32 sscr0; - u32 recr0; /* 0x810 Receive Equalization Control */ - u32 recr1; - u32 tecr0; /* 0x818 Transmit Equalization Control */ - u32 sscr1; - u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ - u8 res_824[0x83c-0x824]; - u32 tcsr3; - } lane[4]; /* Lane A, B, C, D, E, F, G, H */ - u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ -}; - -#define RCPM_POWMGTCSR 0x130 -#define RCPM_POWMGTCSR_SERDES_PW 0x80000000 -#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 -#define RCPM_POWMGTCSR_LPM20_ST 0x00000200 -#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 -#define RCPM_IPPDEXPCR0 0x140 -#define RCPM_IPPDEXPCR0_ETSEC 0x80000000 -#define RCPM_IPPDEXPCR0_GPIO 0x00000040 -#define RCPM_IPPDEXPCR1 0x144 -#define RCPM_IPPDEXPCR1_LPUART 0x40000000 -#define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 -#define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 -#define RCPM_NFIQOUTR 0x15c -#define RCPM_NIRQOUTR 0x16c -#define RCPM_DSIMSKR 0x18c -#define RCPM_CLPCL10SETR 0x1c4 -#define RCPM_CLPCL10SETR_C0 0x00000001 - -struct ccsr_rcpm { - u8 rev1[0x4c]; - u32 twaitsr; - u8 rev2[0xe0]; - u32 powmgtcsr; - u8 rev3[0xc]; - u32 ippdexpcr0; - u32 ippdexpcr1; - u8 rev4[0x14]; - u32 nfiqoutr; - u8 rev5[0xc]; - u32 nirqoutr; - u8 rev6[0x1c]; - u32 dsimskr; - u8 rev7[0x34]; - u32 clpcl10setr; -}; - -uint get_svr(void); - -#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h deleted file mode 100644 index 64853d8..0000000 --- a/arch/arm/include/asm/arch-ls102xa/imx-regs.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - */ - -#ifndef __ASM_ARCH_IMX_REGS_H__ -#define __ASM_ARCH_IMX_REGS_H__ - -#define I2C_QUIRK_REG /* enable 8-bit driver */ - -#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h deleted file mode 100644 index 5d6a4e7..0000000 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_LS102XA_DEVDIS_H_ -#define __FSL_LS102XA_DEVDIS_H_ - -#include <fsl_devdis.h> - -const struct devdis_table devdis_tbl[] = { - { "pbl", 0x0, 0x80000000 }, /* PBL */ - { "esdhc", 0x0, 0x20000000 }, /* eSDHC */ - { "qdma", 0x0, 0x800000 }, /* qDMA */ - { "edma", 0x0, 0x400000 }, /* eDMA */ - { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/ - { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */ - { "sata", 0x0, 0x8000 }, /* SATA */ - { "sec", 0x0, 0x200 }, /* SEC */ - { "dcu", 0x0, 0x2 }, /* Display controller Unit */ - { "qe", 0x0, 0x1 }, /* QUICC Engine */ - { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */ - { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */ - { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */ - { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */ - { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */ - { "duart1", 0x3, 0x20000000 }, /* DUART1 */ - { "duart2", 0x3, 0x10000000 }, /* DUART2 */ - { "qspi", 0x3, 0x8000000 }, /* QSPI */ - { "ddr", 0x4, 0x80000000 }, /* DDR */ - { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */ - { "ifc", 0x4, 0x800000 }, /* IFC */ - { "gpio", 0x4, 0x400000 }, /* GPIO */ - { "dbg", 0x4, 0x200000 }, /* DBG */ - { "can1", 0x4, 0x80000 }, /* FlexCAN1 */ - { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */ - { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */ - { "secmon", 0x4, 0x4000 }, /* Security Monitor */ - { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */ - { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */ - { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */ - { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */ - { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */ - { "asrc", 0x4, 0x20 }, /* ASRC */ - { "spdif", 0x4, 0x10 }, /* SPDIF */ - { "i2c1", 0x4, 0x4 }, /* I2C1 */ - { "lpuart1", 0x4, 0x2 }, /* LPUART1 */ - { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */ -}; - -#endif diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h deleted file mode 100644 index 1fde8bc..0000000 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_LS102XA_SOC_H -#define __FSL_LS102XA_SOC_H - -unsigned int get_soc_major_rev(void); -int arch_soc_init(void); -int ls102xa_smmu_stream_id_init(void); - -void erratum_a008850_post(void); - -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 -void erratum_a010315(void); -#endif - -#endif /* __FSL_LS102XA_SOC_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h deleted file mode 100644 index 93b0a26..0000000 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_LS102XA_STREAM_ID_H_ -#define __FSL_LS102XA_STREAM_ID_H_ - -#include <fsl_sec.h> - -#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ - { .compat = name, \ - .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ - } - -#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ - { .compat = name, \ - .id = { idA, idB }, .num_ids = 2, \ - .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ - } - -/* - * handle both old and new versioned SEC properties: - * "fsl,secX.Y" became "fsl,sec-vX.Y" during development - */ -#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \ - SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \ - offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \ - SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ - offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum) - -/* This is a bit evil since we treat rtic param as both a string & hex value */ -#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ - SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ - liodnA, \ - offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ - SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ - liodnA, \ - offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) - -#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ - SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ - offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, 0) - -struct liodn_id_table { - const char *compat; - u32 id[2]; - u8 num_ids; - phys_addr_t compat_offset; - unsigned long reg_offset; -}; - -struct smmu_stream_id { - uint16_t offset; - uint16_t stream_id; - char dev_name[32]; -}; - -void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size); -void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); -#endif diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h deleted file mode 100644 index b6daf32..0000000 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_NS_ACCESS_H_ -#define __FSL_NS_ACCESS_H_ - -enum csu_cslx_ind { - CSU_CSLX_PCIE2_IO = 0, - CSU_CSLX_PCIE1_IO, - CSU_CSLX_MG2TPR_IP, - CSU_CSLX_IFC_MEM, - CSU_CSLX_OCRAM, - CSU_CSLX_GIC, - CSU_CSLX_PCIE1, - CSU_CSLX_OCRAM2, - CSU_CSLX_QSPI_MEM, - CSU_CSLX_PCIE2, - CSU_CSLX_SATA, - CSU_CSLX_USB3, - CSU_CSLX_SERDES = 32, - CSU_CSLX_QDMA, - CSU_CSLX_LPUART2, - CSU_CSLX_LPUART1, - CSU_CSLX_LPUART4, - CSU_CSLX_LPUART3, - CSU_CSLX_LPUART6, - CSU_CSLX_LPUART5, - CSU_CSLX_DSPI2 = 40, - CSU_CSLX_DSPI1, - CSU_CSLX_QSPI, - CSU_CSLX_ESDHC, - CSU_CSLX_2D_ACE, - CSU_CSLX_IFC, - CSU_CSLX_I2C1, - CSU_CSLX_USB2, - CSU_CSLX_I2C3, - CSU_CSLX_I2C2, - CSU_CSLX_DUART2 = 50, - CSU_CSLX_DUART1, - CSU_CSLX_WDT2, - CSU_CSLX_WDT1, - CSU_CSLX_EDMA, - CSU_CSLX_SYS_CNT, - CSU_CSLX_DMA_MUX2, - CSU_CSLX_DMA_MUX1, - CSU_CSLX_DDR, - CSU_CSLX_QUICC, - CSU_CSLX_DCFG_CCU_RCPM = 60, - CSU_CSLX_SECURE_BOOTROM, - CSU_CSLX_SFP, - CSU_CSLX_TMU, - CSU_CSLX_SECURE_MONITOR, - CSU_CSLX_RESERVED0, - CSU_CSLX_ETSEC1, - CSU_CSLX_SEC5_5, - CSU_CSLX_ETSEC3, - CSU_CSLX_ETSEC2, - CSU_CSLX_GPIO2 = 70, - CSU_CSLX_GPIO1, - CSU_CSLX_GPIO4, - CSU_CSLX_GPIO3, - CSU_CSLX_PLATFORM_CONT, - CSU_CSLX_CSU, - CSU_CSLX_ASRC, - CSU_CSLX_SPDIF, - CSU_CSLX_FLEXCAN2, - CSU_CSLX_FLEXCAN1, - CSU_CSLX_FLEXCAN4 = 80, - CSU_CSLX_FLEXCAN3, - CSU_CSLX_SAI2, - CSU_CSLX_SAI1, - CSU_CSLX_SAI4, - CSU_CSLX_SAI3, - CSU_CSLX_FTM2, - CSU_CSLX_FTM1, - CSU_CSLX_FTM4, - CSU_CSLX_FTM3, - CSU_CSLX_FTM6 = 90, - CSU_CSLX_FTM5, - CSU_CSLX_FTM8, - CSU_CSLX_FTM7, - CSU_CSLX_EPU, - CSU_CSLX_COP_DCSR, - CSU_CSLX_DDI, - CSU_CSLX_GDI, - CSU_CSLX_RESERVED1, - CSU_CSLX_USB3_PHY = 116, - CSU_CSLX_RESERVED2, - CSU_CSLX_MAX, -}; - -#endif diff --git a/arch/arm/include/asm/arch-ls102xa/soc.h b/arch/arm/include/asm/arch-ls102xa/soc.h deleted file mode 100644 index e69de29..0000000 --- a/arch/arm/include/asm/arch-ls102xa/soc.h +++ /dev/null diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h deleted file mode 100644 index 990c74d..0000000 --- a/arch/arm/include/asm/arch-ls102xa/spl.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_SPL_H__ -#define __ASM_ARCH_SPL_H__ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 7 -#define BOOT_DEVICE_SPI 10 - -#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h b/arch/arm/include/asm/arch-mediatek/gpio.h deleted file mode 100644 index 4ea1020..0000000 --- a/arch/arm/include/asm/arch-mediatek/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef __MEDIATEK_GPIO_H -#define __MEDIATEK_GPIO_H - -#endif /* __MEDIATEK_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h deleted file mode 100644 index 2530e78..0000000 --- a/arch/arm/include/asm/arch-mediatek/misc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef __MEDIATEK_MISC_H_ -#define __MEDIATEK_MISC_H_ - -#define VER_BASE 0x08000000 -#define VER_SIZE 0x10 - -#define APHW_CODE 0x00 -#define APHW_SUBCODE 0x04 -#define APHW_VER 0x08 -#define APSW_VER 0x0c - -#endif /* __MEDIATEK_MISC_H_ */ diff --git a/arch/arm/include/asm/arch-mediatek/reset.h b/arch/arm/include/asm/arch-mediatek/reset.h deleted file mode 100644 index 9704666..0000000 --- a/arch/arm/include/asm/arch-mediatek/reset.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef __MEDIATEK_RESET_H -#define __MEDIATEK_RESET_H - -#include <dm.h> - -int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs); - -#endif /* __MEDIATEK_RESET_H */ diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h deleted file mode 100644 index d293f2a..0000000 --- a/arch/arm/include/asm/arch-meson/axg.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __AXG_H__ -#define __AXG_H__ - -#define AXG_AOBUS_BASE 0xff800000 -#define AXG_PERIPHS_BASE 0xff634400 -#define AXG_HIU_BASE 0xff63c000 -#define AXG_ETH_BASE 0xff3f0000 - -/* Always-On Peripherals registers */ -#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) - -#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) -#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) -#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) -#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) - -#define AXG_AO_BOOT_DEVICE 0xF -#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 -#define AXG_AO_MEM_SIZE_SHIFT 16 -#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 -#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 -#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF - -/* Peripherals registers */ -#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) - -#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) -#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) - -#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) -#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) -#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) -#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define AXG_ETH_REG_0_CLK_EN BIT(12) - -/* HIU registers */ -#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) - -#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - -#endif /* __AXG_H__ */ diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h deleted file mode 100644 index a90fe55..0000000 --- a/arch/arm/include/asm/arch-meson/boot.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __MESON_BOOT_H__ -#define __MESON_BOOT_H__ - -/* Boot device */ -#define BOOT_DEVICE_RESERVED 0 -#define BOOT_DEVICE_EMMC 1 -#define BOOT_DEVICE_NAND 2 -#define BOOT_DEVICE_SPI 3 -#define BOOT_DEVICE_SD 4 -#define BOOT_DEVICE_USB 5 - -int meson_get_boot_device(void); - -#endif /* __MESON_BOOT_H__ */ diff --git a/arch/arm/include/asm/arch-meson/clock-axg.h b/arch/arm/include/asm/arch-meson/clock-axg.h deleted file mode 100644 index 1ef88e4..0000000 --- a/arch/arm/include/asm/arch-meson/clock-axg.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 - AmLogic, Inc. - * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> - * Copyright 2018 - BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _ARCH_MESON_CLOCK_AXG_H_ -#define _ARCH_MESON_CLOCK_AXG_H_ - -/* - * Clock controller register offsets - * - * Register offsets from the data sheet are listed in comment blocks below. - * Those offsets must be multiplied by 4 before adding them to the base address - * to get the right value - */ -#define HHI_GP0_PLL_CNTL 0x40 -#define HHI_GP0_PLL_CNTL2 0x44 -#define HHI_GP0_PLL_CNTL3 0x48 -#define HHI_GP0_PLL_CNTL4 0x4c -#define HHI_GP0_PLL_CNTL5 0x50 -#define HHI_GP0_PLL_STS 0x54 -#define HHI_GP0_PLL_CNTL1 0x58 -#define HHI_HIFI_PLL_CNTL 0x80 -#define HHI_HIFI_PLL_CNTL2 0x84 -#define HHI_HIFI_PLL_CNTL3 0x88 -#define HHI_HIFI_PLL_CNTL4 0x8C -#define HHI_HIFI_PLL_CNTL5 0x90 -#define HHI_HIFI_PLL_STS 0x94 -#define HHI_HIFI_PLL_CNTL1 0x98 - -#define HHI_XTAL_DIVN_CNTL 0xbc -#define HHI_GCLK2_MPEG0 0xc0 -#define HHI_GCLK2_MPEG1 0xc4 -#define HHI_GCLK2_MPEG2 0xc8 -#define HHI_GCLK2_OTHER 0xd0 -#define HHI_GCLK2_AO 0xd4 -#define HHI_PCIE_PLL_CNTL 0xd8 -#define HHI_PCIE_PLL_CNTL1 0xdC -#define HHI_PCIE_PLL_CNTL2 0xe0 -#define HHI_PCIE_PLL_CNTL3 0xe4 -#define HHI_PCIE_PLL_CNTL4 0xe8 -#define HHI_PCIE_PLL_CNTL5 0xec -#define HHI_PCIE_PLL_CNTL6 0xf0 -#define HHI_PCIE_PLL_STS 0xf4 - -#define HHI_MEM_PD_REG0 0x100 -#define HHI_VPU_MEM_PD_REG0 0x104 -#define HHI_VIID_CLK_DIV 0x128 -#define HHI_VIID_CLK_CNTL 0x12c - -#define HHI_GCLK_MPEG0 0x140 -#define HHI_GCLK_MPEG1 0x144 -#define HHI_GCLK_MPEG2 0x148 -#define HHI_GCLK_OTHER 0x150 -#define HHI_GCLK_AO 0x154 -#define HHI_SYS_CPU_CLK_CNTL1 0x15c -#define HHI_SYS_CPU_RESET_CNTL 0x160 -#define HHI_VID_CLK_DIV 0x164 -#define HHI_SPICC_HCLK_CNTL 0x168 - -#define HHI_MPEG_CLK_CNTL 0x174 -#define HHI_VID_CLK_CNTL 0x17c -#define HHI_TS_CLK_CNTL 0x190 -#define HHI_VID_CLK_CNTL2 0x194 -#define HHI_SYS_CPU_CLK_CNTL0 0x19c -#define HHI_VID_PLL_CLK_DIV 0x1a0 -#define HHI_VPU_CLK_CNTL 0x1bC - -#define HHI_VAPBCLK_CNTL 0x1F4 - -#define HHI_GEN_CLK_CNTL 0x228 - -#define HHI_VDIN_MEAS_CLK_CNTL 0x250 -#define HHI_NAND_CLK_CNTL 0x25C -#define HHI_SD_EMMC_CLK_CNTL 0x264 - -#define HHI_MPLL_CNTL 0x280 -#define HHI_MPLL_CNTL2 0x284 -#define HHI_MPLL_CNTL3 0x288 -#define HHI_MPLL_CNTL4 0x28C -#define HHI_MPLL_CNTL5 0x290 -#define HHI_MPLL_CNTL6 0x294 -#define HHI_MPLL_CNTL7 0x298 -#define HHI_MPLL_CNTL8 0x29C -#define HHI_MPLL_CNTL9 0x2A0 -#define HHI_MPLL_CNTL10 0x2A4 - -#define HHI_MPLL3_CNTL0 0x2E0 -#define HHI_MPLL3_CNTL1 0x2E4 -#define HHI_PLL_TOP_MISC 0x2E8 - -#define HHI_SYS_PLL_CNTL1 0x2FC -#define HHI_SYS_PLL_CNTL 0x300 -#define HHI_SYS_PLL_CNTL2 0x304 -#define HHI_SYS_PLL_CNTL3 0x308 -#define HHI_SYS_PLL_CNTL4 0x30c -#define HHI_SYS_PLL_CNTL5 0x310 -#define HHI_SYS_PLL_STS 0x314 -#define HHI_DPLL_TOP_I 0x318 -#define HHI_DPLL_TOP2_I 0x31C - -#endif diff --git a/arch/arm/include/asm/arch-meson/clock-g12a.h b/arch/arm/include/asm/arch-meson/clock-g12a.h deleted file mode 100644 index d52e27e..0000000 --- a/arch/arm/include/asm/arch-meson/clock-g12a.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 - AmLogic, Inc. - * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> - * Copyright 2018 - BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _ARCH_MESON_CLOCK_G12A_H_ -#define _ARCH_MESON_CLOCK_G12A_H_ - -/* - * Clock controller register offsets - * - * Register offsets from the data sheet are listed in comment blocks below. - * Those offsets must be multiplied by 4 before adding them to the base address - * to get the right value - */ - -#define HHI_MIPI_CNTL0 0x000 -#define HHI_MIPI_CNTL1 0x004 -#define HHI_MIPI_CNTL2 0x008 -#define HHI_MIPI_STS 0x00C -#define HHI_GP0_PLL_CNTL0 0x040 -#define HHI_GP0_PLL_CNTL1 0x044 -#define HHI_GP0_PLL_CNTL2 0x048 -#define HHI_GP0_PLL_CNTL3 0x04C -#define HHI_GP0_PLL_CNTL4 0x050 -#define HHI_GP0_PLL_CNTL5 0x054 -#define HHI_GP0_PLL_CNTL6 0x058 -#define HHI_GP0_PLL_STS 0x05C -#define HHI_PCIE_PLL_CNTL0 0x098 -#define HHI_PCIE_PLL_CNTL1 0x09C -#define HHI_PCIE_PLL_CNTL2 0x0A0 -#define HHI_PCIE_PLL_CNTL3 0x0A4 -#define HHI_PCIE_PLL_CNTL4 0x0A8 -#define HHI_PCIE_PLL_CNTL5 0x0AC -#define HHI_PCIE_PLL_STS 0x0B8 -#define HHI_HIFI_PLL_CNTL0 0x0D8 -#define HHI_HIFI_PLL_CNTL1 0x0DC -#define HHI_HIFI_PLL_CNTL2 0x0E0 -#define HHI_HIFI_PLL_CNTL3 0x0E4 -#define HHI_HIFI_PLL_CNTL4 0x0E8 -#define HHI_HIFI_PLL_CNTL5 0x0EC -#define HHI_HIFI_PLL_CNTL6 0x0F0 -#define HHI_VIID_CLK_DIV 0x128 -#define HHI_VIID_CLK_CNTL 0x12C -#define HHI_GCLK_MPEG0 0x140 -#define HHI_GCLK_MPEG1 0x144 -#define HHI_GCLK_MPEG2 0x148 -#define HHI_GCLK_OTHER 0x150 -#define HHI_GCLK_OTHER2 0x154 -#define HHI_VID_CLK_DIV 0x164 -#define HHI_MPEG_CLK_CNTL 0x174 -#define HHI_AUD_CLK_CNTL 0x178 -#define HHI_VID_CLK_CNTL 0x17c -#define HHI_TS_CLK_CNTL 0x190 -#define HHI_VID_CLK_CNTL2 0x194 -#define HHI_SYS_CPU_CLK_CNTL0 0x19c -#define HHI_VID_PLL_CLK_DIV 0x1A0 -#define HHI_MALI_CLK_CNTL 0x1b0 -#define HHI_VPU_CLKC_CNTL 0x1b4 -#define HHI_VPU_CLK_CNTL 0x1bC -#define HHI_HDMI_CLK_CNTL 0x1CC -#define HHI_VDEC_CLK_CNTL 0x1E0 -#define HHI_VDEC2_CLK_CNTL 0x1E4 -#define HHI_VDEC3_CLK_CNTL 0x1E8 -#define HHI_VDEC4_CLK_CNTL 0x1EC -#define HHI_HDCP22_CLK_CNTL 0x1F0 -#define HHI_VAPBCLK_CNTL 0x1F4 -#define HHI_VPU_CLKB_CNTL 0x20C -#define HHI_GEN_CLK_CNTL 0x228 -#define HHI_VDIN_MEAS_CLK_CNTL 0x250 -#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 -#define HHI_NAND_CLK_CNTL 0x25C -#define HHI_SD_EMMC_CLK_CNTL 0x264 -#define HHI_MPLL_CNTL0 0x278 -#define HHI_MPLL_CNTL1 0x27C -#define HHI_MPLL_CNTL2 0x280 -#define HHI_MPLL_CNTL3 0x284 -#define HHI_MPLL_CNTL4 0x288 -#define HHI_MPLL_CNTL5 0x28c -#define HHI_MPLL_CNTL6 0x290 -#define HHI_MPLL_CNTL7 0x294 -#define HHI_MPLL_CNTL8 0x298 -#define HHI_FIX_PLL_CNTL0 0x2A0 -#define HHI_FIX_PLL_CNTL1 0x2A4 -#define HHI_FIX_PLL_CNTL3 0x2AC -#define HHI_SYS_PLL_CNTL0 0x2f4 -#define HHI_SYS_PLL_CNTL1 0x2f8 -#define HHI_SYS_PLL_CNTL2 0x2fc -#define HHI_SYS_PLL_CNTL3 0x300 -#define HHI_SYS_PLL_CNTL4 0x304 -#define HHI_SYS_PLL_CNTL5 0x308 -#define HHI_SYS_PLL_CNTL6 0x30c -#define HHI_HDMI_PLL_CNTL0 0x320 -#define HHI_HDMI_PLL_CNTL1 0x324 -#define HHI_HDMI_PLL_CNTL2 0x328 -#define HHI_HDMI_PLL_CNTL3 0x32c -#define HHI_HDMI_PLL_CNTL4 0x330 -#define HHI_HDMI_PLL_CNTL5 0x334 -#define HHI_HDMI_PLL_CNTL6 0x338 -#define HHI_SPICC_CLK_CNTL 0x3dc - -#endif diff --git a/arch/arm/include/asm/arch-meson/clock-gx.h b/arch/arm/include/asm/arch-meson/clock-gx.h deleted file mode 100644 index 13a2e76..0000000 --- a/arch/arm/include/asm/arch-meson/clock-gx.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 - AmLogic, Inc. - * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> - */ -#ifndef _ARCH_MESON_CLOCK_GX_H_ -#define _ARCH_MESON_CLOCK_GX_H_ - -/* - * Clock controller register offsets - * - * Register offsets from the data sheet are listed in comment blocks below. - * Those offsets must be multiplied by 4 before adding them to the base address - * to get the right value - */ -#define SCR 0x2C /* 0x0b offset in data sheet */ -#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ - -#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ -#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ -#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ -#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ -#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ -#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ - -#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ -#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ - -#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ -#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ -#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ -#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ -#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ - -#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ -#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ -#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ -#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ -#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ -#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ -#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ -#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ - -#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ -#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ -#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ -#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ -#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ -#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ -#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ -#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ -#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ - -#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ -#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ -#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ -#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ -#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ -#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ -#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ - -#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ -#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ -#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ -#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ -#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ - -#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ -#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ -#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ - -#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ -#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ -#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ -#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ -#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ -#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ -#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ -#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ -#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ -#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ - -#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ -#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ -#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ -#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ - -#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ -#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ -#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ -#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ -#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ -#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ -#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ -#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ -#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ -#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ -#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ -#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ - -#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ -#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ -#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ -#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ - -#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ -#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ -#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ - -ulong meson_measure_clk_rate(unsigned int clk); - -#endif diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h deleted file mode 100644 index f765cd7..0000000 --- a/arch/arm/include/asm/arch-meson/eth.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __MESON_ETH_H__ -#define __MESON_ETH_H__ - -#include <phy.h> - -enum { - /* Use Internal RMII PHY */ - MESON_USE_INTERNAL_RMII_PHY = 1, -}; - -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags); - -/* Generate an unique MAC address based on the HW serial */ -int meson_generate_serial_ethaddr(void); - -#endif /* __MESON_ETH_H__ */ diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h deleted file mode 100644 index b806667..0000000 --- a/arch/arm/include/asm/arch-meson/g12a.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __G12A_H__ -#define __G12A_H__ - -#define G12A_AOBUS_BASE 0xff800000 -#define G12A_PERIPHS_BASE 0xff634400 -#define G12A_HIU_BASE 0xff63c000 -#define G12A_ETH_PHY_BASE 0xff64c000 -#define G12A_ETH_BASE 0xff3f0000 - -/* Always-On Peripherals registers */ -#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) - -#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) -#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) -#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) -#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) - -#define G12A_AO_BOOT_DEVICE 0xF -#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 -#define G12A_AO_MEM_SIZE_SHIFT 16 -#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 -#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 -#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF - -/* Peripherals registers */ -#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) - -#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) -#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) - -#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) -#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) -#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) -#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define G12A_ETH_REG_0_CLK_EN BIT(12) - -#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) -#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) -#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) -#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) -#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) -#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) -#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) -#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) -#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) -#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) -#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) -#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) - -/* HIU registers */ -#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) - -#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - -#endif /* __G12A_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gpio.h b/arch/arm/include/asm/arch-meson/gpio.h deleted file mode 100644 index d0142f1..0000000 --- a/arch/arm/include/asm/arch-meson/gpio.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com> - */ - -#ifndef __ASM_ARCH_MESON_GPIO_H -#define __ASM_ARCH_MESON_GPIO_H - - -#endif /* __ASM_ARCH_MESON_GPIO_H */ diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h deleted file mode 100644 index b781ba9..0000000 --- a/arch/arm/include/asm/arch-meson/gx.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> - */ - -#ifndef __GX_H__ -#define __GX_H__ - -#define GX_FIRMWARE_MEM_SIZE 0x1000000 - -#define GX_AOBUS_BASE 0xc8100000 -#define GX_PERIPHS_BASE 0xc8834400 -#define GX_HIU_BASE 0xc883c000 -#define GX_ETH_BASE 0xc9410000 - -/* Always-On Peripherals registers */ -#define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2)) - -#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90) -#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93) -#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) -#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) - -#define GX_AO_BOOT_DEVICE 0xF -#define GX_AO_MEM_SIZE_MASK 0xFFFF0000 -#define GX_AO_MEM_SIZE_SHIFT 16 -#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 -#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16 -#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF - -/* Peripherals registers */ -#define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2)) - -/* GPIO registers 0 to 6 */ -#define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) -#define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0) -#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) -#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) - -#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50) -#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51) -#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56) -#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57) - -#define GX_ETH_REG_0_PHY_INTF BIT(0) -#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define GX_ETH_REG_0_PHY_CLK_EN BIT(10) -#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define GX_ETH_REG_0_CLK_EN BIT(12) - -/* HIU registers */ -#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2)) - -#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - -#endif /* __GX_H__ */ diff --git a/arch/arm/include/asm/arch-meson/i2c.h b/arch/arm/include/asm/arch-meson/i2c.h deleted file mode 100644 index aa474a0..0000000 --- a/arch/arm/include/asm/arch-meson/i2c.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com> - */ -#ifndef _MESON_I2C_H_ -#define _MESON_I2C_H_ - -#define MESON_I2C_CLK_RATE 167000000 - -#endif diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h deleted file mode 100644 index a65100a..0000000 --- a/arch/arm/include/asm/arch-meson/mem.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __MESON_MEM_H__ -#define __MESON_MEM_H__ - -/* Configure the reserved memory zones exported by the secure registers - * into EFI and DTB reserved memory entries. - */ -void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size); -void meson_init_reserved_memory(void *fdt); - -#endif /* __MESON_MEM_H__ */ diff --git a/arch/arm/include/asm/arch-meson/meson-vpu.h b/arch/arm/include/asm/arch-meson/meson-vpu.h deleted file mode 100644 index f31dfa6..0000000 --- a/arch/arm/include/asm/arch-meson/meson-vpu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Maxime Jourdan <mjourdan@baylibre.com> - */ - -#ifndef __MESON_VPU_H__ -#define __MESON_VPU_H__ - -/* Allow reserving the framebuffer memory region */ -void meson_vpu_rsv_fb(void *fdt); - -#endif /* __MESON_VPU_H__ */ diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h deleted file mode 100644 index e3a72c8..0000000 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Carlo Caione <carlo@caione.org> - */ - -#ifndef __SD_EMMC_H__ -#define __SD_EMMC_H__ - -#include <mmc.h> - -#define SDIO_PORT_A 0 -#define SDIO_PORT_B 1 -#define SDIO_PORT_C 2 - -#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ -#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ - -#define MESON_SD_EMMC_CLOCK 0x00 -#define CLK_MAX_DIV 63 -#define CLK_SRC_24M (0 << 6) -#define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) -#define CLK_ALWAYS_ON BIT(24) - -#define MESON_SD_EMMC_CFG 0x44 -#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) -#define CFG_BUS_WIDTH_1 0 -#define CFG_BUS_WIDTH_4 1 -#define CFG_BUS_WIDTH_8 2 -#define CFG_BL_LEN_MASK GENMASK(7, 4) -#define CFG_BL_LEN_SHIFT 4 -#define CFG_BL_LEN_512 (9 << 4) -#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) -#define CFG_RESP_TIMEOUT_256 (8 << 8) -#define CFG_RC_CC_MASK GENMASK(15, 12) -#define CFG_RC_CC_16 (4 << 12) -#define CFG_SDCLK_ALWAYS_ON BIT(18) -#define CFG_AUTO_CLK BIT(23) - -#define MESON_SD_EMMC_STATUS 0x48 -#define STATUS_MASK GENMASK(15, 0) -#define STATUS_ERR_MASK GENMASK(12, 0) -#define STATUS_RXD_ERR_MASK GENMASK(7, 0) -#define STATUS_TXD_ERR BIT(8) -#define STATUS_DESC_ERR BIT(9) -#define STATUS_RESP_ERR BIT(10) -#define STATUS_RESP_TIMEOUT BIT(11) -#define STATUS_DESC_TIMEOUT BIT(12) -#define STATUS_END_OF_CHAIN BIT(13) - -#define MESON_SD_EMMC_IRQ_EN 0x4c - -#define MESON_SD_EMMC_CMD_CFG 0x50 -#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) -#define CMD_CFG_BLOCK_MODE BIT(9) -#define CMD_CFG_R1B BIT(10) -#define CMD_CFG_END_OF_CHAIN BIT(11) -#define CMD_CFG_TIMEOUT_4S (12 << 12) -#define CMD_CFG_NO_RESP BIT(16) -#define CMD_CFG_DATA_IO BIT(18) -#define CMD_CFG_DATA_WR BIT(19) -#define CMD_CFG_RESP_NOCRC BIT(20) -#define CMD_CFG_RESP_128 BIT(21) -#define CMD_CFG_CMD_INDEX_SHIFT 24 -#define CMD_CFG_OWNER BIT(31) - -#define MESON_SD_EMMC_CMD_ARG 0x54 -#define MESON_SD_EMMC_CMD_DAT 0x58 -#define MESON_SD_EMMC_CMD_RSP 0x5c -#define MESON_SD_EMMC_CMD_RSP1 0x60 -#define MESON_SD_EMMC_CMD_RSP2 0x64 -#define MESON_SD_EMMC_CMD_RSP3 0x68 - -struct meson_mmc_platdata { - struct mmc_config cfg; - struct mmc mmc; - void *regbase; - void *w_buf; -}; - -#endif diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h deleted file mode 100644 index f3ae46a..0000000 --- a/arch/arm/include/asm/arch-meson/sm.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> - */ - -#ifndef __MESON_SM_H__ -#define __MESON_SM_H__ - -ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size); - -#define SM_SERIAL_SIZE 12 - -int meson_sm_get_serial(void *buffer, size_t size); - -enum { - REBOOT_REASON_COLD = 0, - REBOOT_REASON_NORMAL = 1, - REBOOT_REASON_RECOVERY = 2, - REBOOT_REASON_UPDATE = 3, - REBOOT_REASON_FASTBOOT = 4, - REBOOT_REASON_SUSPEND_OFF = 5, - REBOOT_REASON_HIBERNATE = 6, - REBOOT_REASON_BOOTLOADER = 7, - REBOOT_REASON_SHUTDOWN_REBOOT = 8, - REBOOT_REASON_RPMBP = 9, - REBOOT_REASON_CRASH_DUMP = 11, - REBOOT_REASON_KERNEL_PANIC = 12, - REBOOT_REASON_WATCHDOG_REBOOT = 13, -}; - -int meson_sm_get_reboot_reason(void); - -#endif /* __MESON_SM_H__ */ diff --git a/arch/arm/include/asm/arch-meson/usb.h b/arch/arm/include/asm/arch-meson/usb.h deleted file mode 100644 index b794b5c..0000000 --- a/arch/arm/include/asm/arch-meson/usb.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __MESON_USB_H__ -#define __MESON_USB_H__ - -int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode); - -#endif /* __MESON_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h deleted file mode 100644 index 58b6c32..0000000 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * Derived from drivers/spi/mpc8xxx_spi.c - */ - -#ifndef __KW_SPI_H__ -#define __KW_SPI_H__ - -/* SPI Registers on kirkwood SOC */ -struct kwspi_registers { - u32 ctrl; /* 0x10600 */ - u32 cfg; /* 0x10604 */ - u32 dout; /* 0x10608 */ - u32 din; /* 0x1060c */ - u32 irq_cause; /* 0x10610 */ - u32 irq_mask; /* 0x10614 */ - u32 timing1; /* 0x10618 */ - u32 timing2; /* 0x1061c */ - u32 dw_cfg; /* 0x10620 - Direct Write Configuration */ -}; - -/* Control Register */ -#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_CS_SHIFT 2 /* chip select shift */ -#define KWSPI_CS_MASK 0x7 /* chip select mask */ - -/* Configuration Register */ -#define KWSPI_CLKPRESCL_MASK 0x1f -#define KWSPI_CLKPRESCL_MIN 0x12 -#define KWSPI_XFERLEN_1BYTE 0 -#define KWSPI_XFERLEN_2BYTE (1 << 5) -#define KWSPI_XFERLEN_MASK (1 << 5) -#define KWSPI_ADRLEN_1BYTE 0 -#define KWSPI_ADRLEN_2BYTE (1 << 8) -#define KWSPI_ADRLEN_3BYTE (2 << 8) -#define KWSPI_ADRLEN_4BYTE (3 << 8) -#define KWSPI_ADRLEN_MASK (3 << 8) -#define KWSPI_CPOL (1 << 11) -#define KWSPI_CPHA (1 << 12) -#define KWSPI_TXLSBF (1 << 13) -#define KWSPI_RXLSBF (1 << 14) - -/* Timing Parameters 1 Register */ -#define KW_SPI_TMISO_SAMPLE_OFFSET 6 -#define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET) -#define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET) -#define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET) - -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ - -#define KWSPI_TIMEOUT 10000 - -#endif /* __KW_SPI_H__ */ diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h deleted file mode 100644 index 7eec731..0000000 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> - * - * Modified for mx25 by John Rigby <jrigby@gmail.com> - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_MX25_HCLK_FREQ -#define MXC_HCLK CONFIG_MX25_HCLK_FREQ -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_MX25_CLK32 -#define MXC_CLK32 CONFIG_MX25_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - /* PER clocks (do not change order) */ - MXC_CSI_CLK, - MXC_EPIT_CLK, - MXC_ESAI_CLK, - MXC_ESDHC1_CLK, - MXC_ESDHC2_CLK, - MXC_GPT_CLK, - MXC_I2C_CLK, - MXC_LCDC_CLK, - MXC_NFC_CLK, - MXC_OWIRE_CLK, - MXC_PWM_CLK, - MXC_SIM1_CLK, - MXC_SIM2_CLK, - MXC_SSI1_CLK, - MXC_SSI2_CLK, - MXC_UART_CLK, - /* Other clocks */ - MXC_ARM_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, - MXC_CLK_NUM -}; - -int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx25/gpio.h b/arch/arm/include/asm/arch-mx25/gpio.h deleted file mode 100644 index 1205695..0000000 --- a/arch/arm/include/asm/arch-mx25/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - */ - - -#ifndef __ASM_ARCH_MX25_GPIO_H -#define __ASM_ARCH_MX25_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h deleted file mode 100644 index 5d0974f..0000000 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ /dev/null @@ -1,534 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009, DENX Software Engineering - * Author: John Rigby <jcrigby@gmail.com - * - * Based on arch-mx31/imx-regs.h - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems <yanok@emcraft.com> - * and arch-mx27/imx-regs.h - * Copyright (C) 2007 Pengutronix, - * Sascha Hauer <s.hauer@pengutronix.de> - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems <yanok@emcraft.com> - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 mpctl; /* Core PLL Control */ - u32 upctl; /* USB PLL Control */ - u32 cctl; /* Clock Control */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 pcdr[4]; /* PER Clock Dividers */ - u32 rcsr; /* CCM Status */ - u32 crdr; /* CCM Reset and Debug */ - u32 dcvr0; /* DPTC Comparator Value 0 */ - u32 dcvr1; /* DPTC Comparator Value 1 */ - u32 dcvr2; /* DPTC Comparator Value 2 */ - u32 dcvr3; /* DPTC Comparator Value 3 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ - u32 ltbr1; /* Load Tracking Buffer 1 */ - u32 pcmr0; /* Power Management Control 0 */ - u32 pcmr1; /* Power Management Control 1 */ - u32 pcmr2; /* Power Management Control 2 */ - u32 mcr; /* Miscellaneous Control */ - u32 lpimr0; /* Low Power Interrupt Mask 0 */ - u32 lpimr1; /* Low Power Interrupt Mask 1 */ -}; - -/* Enhanced SDRAM Controller (ESDRAMC) registers */ -struct esdramc_regs { - u32 ctl0; /* control 0 */ - u32 cfg0; /* configuration 0 */ - u32 ctl1; /* control 1 */ - u32 cfg1; /* configuration 1 */ - u32 misc; /* miscellaneous */ - u32 pad[3]; - u32 cdly1; /* Delay Line 1 configuration debug */ - u32 cdly2; /* delay line 2 configuration debug */ - u32 cdly3; /* delay line 3 configuration debug */ - u32 cdly4; /* delay line 4 configuration debug */ - u32 cdly5; /* delay line 5 configuration debug */ - u32 cdlyl; /* delay line cycle length debug */ -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -/* Watchdog Timer (WDOG) registers */ -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Misc Control */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res1[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_25[0xa]; - u32 mac_addr[6]; -}; - -struct fuse_bank1_regs { - u32 fuse0_21[0x16]; - u32 usr5; - u32 fuse23_29[7]; - u32 usr6[2]; -}; - -/* Multi-Layer AHB Crossbar Switch (MAX) registers */ -struct max_regs { - u32 mpr0; - u32 pad00[3]; - u32 sgpcr0; - u32 pad01[59]; - u32 mpr1; - u32 pad02[3]; - u32 sgpcr1; - u32 pad03[59]; - u32 mpr2; - u32 pad04[3]; - u32 sgpcr2; - u32 pad05[59]; - u32 mpr3; - u32 pad06[3]; - u32 sgpcr3; - u32 pad07[59]; - u32 mpr4; - u32 pad08[3]; - u32 sgpcr4; - u32 pad09[251]; - u32 mgpcr0; - u32 pad10[63]; - u32 mgpcr1; - u32 pad11[63]; - u32 mgpcr2; - u32 pad12[63]; - u32 mgpcr3; - u32 pad13[63]; - u32 mgpcr4; -}; - -/* AHB <-> IP-Bus Interface (AIPS) */ -struct aips_regs { - u32 mpr_0_7; - u32 mpr_8_15; -}; -/* LCD controller registers */ -struct lcdc_regs { - u32 lssar; /* Screen Start Address */ - u32 lsr; /* Size */ - u32 lvpwr; /* Virtual Page Width */ - u32 lcpr; /* Cursor Position */ - u32 lcwhb; /* Cursor Width Height and Blink */ - u32 lccmr; /* Color Cursor Mapping */ - u32 lpcr; /* Panel Configuration */ - u32 lhcr; /* Horizontal Configuration */ - u32 lvcr; /* Vertical Configuration */ - u32 lpor; /* Panning Offset */ - u32 lscr; /* Sharp Configuration */ - u32 lpccr; /* PWM Contrast Control */ - u32 ldcr; /* DMA Control */ - u32 lrmcr; /* Refresh Mode Control */ - u32 licr; /* Interrupt Configuration */ - u32 lier; /* Interrupt Enable */ - u32 lisr; /* Interrupt Status */ - u32 res0[3]; - u32 lgwsar; /* Graphic Window Start Address */ - u32 lgwsr; /* Graphic Window Size */ - u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ - u32 lgwpor; /* Graphic Window Panning Offset */ - u32 lgwpr; /* Graphic Window Position */ - u32 lgwcr; /* Graphic Window Control */ - u32 lgwdcr; /* Graphic Window DMA Control */ - u32 res1[5]; - u32 lauscr; /* AUS Mode Control */ - u32 lausccr; /* AUS mode Cursor Control */ - u32 res2[31 + 64*7]; - u32 bglut; /* Background Lookup Table */ - u32 gwlut; /* Graphic Window Lookup Table */ -}; - -/* Wireless External Interface Module Registers */ -struct weim_regs { - u32 cscr0u; /* Chip Select 0 Upper Register */ - u32 cscr0l; /* Chip Select 0 Lower Register */ - u32 cscr0a; /* Chip Select 0 Addition Register */ - u32 pad0; - u32 cscr1u; /* Chip Select 1 Upper Register */ - u32 cscr1l; /* Chip Select 1 Lower Register */ - u32 cscr1a; /* Chip Select 1 Addition Register */ - u32 pad1; - u32 cscr2u; /* Chip Select 2 Upper Register */ - u32 cscr2l; /* Chip Select 2 Lower Register */ - u32 cscr2a; /* Chip Select 2 Addition Register */ - u32 pad2; - u32 cscr3u; /* Chip Select 3 Upper Register */ - u32 cscr3l; /* Chip Select 3 Lower Register */ - u32 cscr3a; /* Chip Select 3 Addition Register */ - u32 pad3; - u32 cscr4u; /* Chip Select 4 Upper Register */ - u32 cscr4l; /* Chip Select 4 Lower Register */ - u32 cscr4a; /* Chip Select 4 Addition Register */ - u32 pad4; - u32 cscr5u; /* Chip Select 5 Upper Register */ - u32 cscr5l; /* Chip Select 5 Lower Register */ - u32 cscr5a; /* Chip Select 5 Addition Register */ - u32 pad5; - u32 wcr; /* WEIM Configuration Register */ -}; - -/* Multi-Master Memory Interface */ -struct m3if_regs { - u32 ctl; /* Control Register */ - u32 wcfg0; /* Watermark Configuration Register 0 */ - u32 wcfg1; /* Watermark Configuration Register1 */ - u32 wcfg2; /* Watermark Configuration Register2 */ - u32 wcfg3; /* Watermark Configuration Register 3 */ - u32 wcfg4; /* Watermark Configuration Register 4 */ - u32 wcfg5; /* Watermark Configuration Register 5 */ - u32 wcfg6; /* Watermark Configuration Register 6 */ - u32 wcfg7; /* Watermark Configuration Register 7 */ - u32 wcsr; /* Watermark Control and Status Register */ - u32 scfg0; /* Snooping Configuration Register 0 */ - u32 scfg1; /* Snooping Configuration Register 1 */ - u32 scfg2; /* Snooping Configuration Register 2 */ - u32 ssr0; /* Snooping Status Register 0 */ - u32 ssr1; /* Snooping Status Register 1 */ - u32 res0; - u32 mlwe0; /* Master Lock WEIM CS0 Register */ - u32 mlwe1; /* Master Lock WEIM CS1 Register */ - u32 mlwe2; /* Master Lock WEIM CS2 Register */ - u32 mlwe3; /* Master Lock WEIM CS3 Register */ - u32 mlwe4; /* Master Lock WEIM CS4 Register */ - u32 mlwe5; /* Master Lock WEIM CS5 Register */ -}; - -/* Pulse width modulation */ -struct pwm_regs { - u32 cr; /* Control Register */ - u32 sr; /* Status Register */ - u32 ir; /* Interrupt Register */ - u32 sar; /* Sample Register */ - u32 pr; /* Period Register */ - u32 cnr; /* Counter Register */ -}; - -/* Enhanced Periodic Interrupt Timer */ -struct epit_regs { - u32 cr; /* Control register */ - u32 sr; /* Status register */ - u32 lr; /* Load register */ - u32 cmpr; /* Compare register */ - u32 cnr; /* Counter register */ -}; - -/* CSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 intr; - u32 dma; - u32 stat; - u32 period; - u32 test; -}; - -#endif - -#define ARCH_MXC - -/* AIPS 1 */ -#define IMX_AIPS1_BASE (0x43F00000) -#define IMX_MAX_BASE (0x43F04000) -#define IMX_CLKCTL_BASE (0x43F08000) -#define IMX_ETB_SLOT4_BASE (0x43F0C000) -#define IMX_ETB_SLOT5_BASE (0x43F10000) -#define IMX_ECT_CTIO_BASE (0x43F18000) -#define I2C1_BASE_ADDR (0x43F80000) -#define I2C3_BASE_ADDR (0x43F84000) -#define IMX_CAN1_BASE (0x43F88000) -#define IMX_CAN2_BASE (0x43F8C000) -#define UART1_BASE (0x43F90000) -#define UART2_BASE (0x43F94000) -#define I2C2_BASE_ADDR (0x43F98000) -#define IMX_OWIRE_BASE (0x43F9C000) -#define IMX_CSPI1_BASE (0x43FA4000) -#define IMX_KPP_BASE (0x43FA8000) -#define IMX_IOPADMUX_BASE (0x43FAC000) -#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE -#define IMX_IOPADCTL_BASE (0x43FAC22C) -#define IMX_IOPADGRPCTL_BASE (0x43FAC418) -#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) -#define IMX_AUDMUX_BASE (0x43FB0000) -#define IMX_ECT_IP1_BASE (0x43FB8000) -#define IMX_ECT_IP2_BASE (0x43FBC000) - -/* SPBA */ -#define IMX_SPBA_BASE (0x50000000) -#define IMX_CSPI3_BASE (0x50004000) -#define UART4_BASE (0x50008000) -#define UART3_BASE (0x5000C000) -#define IMX_CSPI2_BASE (0x50010000) -#define IMX_SSI2_BASE (0x50014000) -#define IMX_ESAI_BASE (0x50018000) -#define IMX_ATA_DMA_BASE (0x50020000) -#define IMX_SIM1_BASE (0x50024000) -#define IMX_SIM2_BASE (0x50028000) -#define UART5_BASE (0x5002C000) -#define IMX_TSC_BASE (0x50030000) -#define IMX_SSI1_BASE (0x50034000) -#define IMX_FEC_BASE (0x50038000) -#define IMX_SPBA_CTRL_BASE (0x5003C000) - -/* AIPS 2 */ -#define IMX_AIPS2_BASE (0x53F00000) -#define IMX_CCM_BASE (0x53F80000) -#define IMX_GPT4_BASE (0x53F84000) -#define IMX_GPT3_BASE (0x53F88000) -#define IMX_GPT2_BASE (0x53F8C000) -#define IMX_GPT1_BASE (0x53F90000) -#define IMX_EPIT1_BASE (0x53F94000) -#define IMX_EPIT2_BASE (0x53F98000) -#define IMX_GPIO4_BASE (0x53F9C000) -#define IMX_PWM2_BASE (0x53FA0000) -#define IMX_GPIO3_BASE (0x53FA4000) -#define IMX_PWM3_BASE (0x53FA8000) -#define IMX_SCC_BASE (0x53FAC000) -#define IMX_SCM_BASE (0x53FAE000) -#define IMX_SMN_BASE (0x53FAF000) -#define IMX_RNGD_BASE (0x53FB0000) -#define IMX_MMC_SDHC1_BASE (0x53FB4000) -#define IMX_MMC_SDHC2_BASE (0x53FB8000) -#define IMX_LCDC_BASE (0x53FBC000) -#define IMX_SLCDC_BASE (0x53FC0000) -#define IMX_PWM4_BASE (0x53FC8000) -#define IMX_GPIO1_BASE (0x53FCC000) -#define IMX_GPIO2_BASE (0x53FD0000) -#define IMX_SDMA_BASE (0x53FD4000) -#define IMX_WDT_BASE (0x53FDC000) -#define WDOG1_BASE_ADDR IMX_WDT_BASE -#define IMX_PWM1_BASE (0x53FE0000) -#define IMX_RTIC_BASE (0x53FEC000) -#define IMX_IIM_BASE (0x53FF0000) -#define IIM_BASE_ADDR IMX_IIM_BASE -#define IMX_USB_BASE (0x53FF4000) -/* - * This is in contradiction to the imx25 reference manual, which says that - * port 1's registers start at 0x53FF4200. The correct base address for - * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well. - */ -#define IMX_USB_PORT_OFFSET 0x400 -#define IMX_CSI_BASE (0x53FF8000) -#define IMX_DRYICE_BASE (0x53FFC000) - -#define IMX_ARM926_ROMPATCH (0x60000000) -#define IMX_ARM926_ASIC (0x68000000) - -/* 128K Internal Static RAM */ -#define IMX_RAM_BASE (0x78000000) -#define IMX_RAM_SIZE (128 * 1024) - -/* SDRAM BANKS */ -#define IMX_SDRAM_BANK0_BASE (0x80000000) -#define IMX_SDRAM_BANK1_BASE (0x90000000) - -#define IMX_WEIM_CS0 (0xA0000000) -#define IMX_WEIM_CS1 (0xA8000000) -#define IMX_WEIM_CS2 (0xB0000000) -#define IMX_WEIM_CS3 (0xB2000000) -#define IMX_WEIM_CS4 (0xB4000000) -#define IMX_ESDRAMC_BASE (0xB8001000) -#define IMX_WEIM_CTRL_BASE (0xB8002000) -#define IMX_M3IF_CTRL_BASE (0xB8003000) -#define IMX_EMI_CTRL_BASE (0xB8004000) - -/* NAND Flash Controller */ -#define IMX_NFC_BASE (0xBB000000) -#define NFC_BASE_ADDR IMX_NFC_BASE - -/* CCM bitfields */ -#define CCM_PLL_MFI_SHIFT 10 -#define CCM_PLL_MFI_MASK 0xf -#define CCM_PLL_MFN_SHIFT 0 -#define CCM_PLL_MFN_MASK 0x3ff -#define CCM_PLL_MFD_SHIFT 16 -#define CCM_PLL_MFD_MASK 0x3ff -#define CCM_PLL_PD_SHIFT 26 -#define CCM_PLL_PD_MASK 0xf -#define CCM_CCTL_ARM_DIV_SHIFT 30 -#define CCM_CCTL_ARM_DIV_MASK 3 -#define CCM_CCTL_AHB_DIV_SHIFT 28 -#define CCM_CCTL_AHB_DIV_MASK 3 -#define CCM_CCTL_ARM_SRC (1 << 14) -#define CCM_CGR1_GPT1 (1 << 19) -#define CCM_PERCLK_REG(clk) (clk / 4) -#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) -#define CCM_PERCLK_MASK 0x3f -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) -#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) -#define CCM_CRDR_BT_UART_SRC_SHIFT 29 -#define CCM_CRDR_BT_UART_SRC_MASK 7 - -/* ESDRAM Controller register bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -/* GPT bits */ -#define GPT_CTRL_SWR (1 << 15) /* Software reset */ -#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ -#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPT_CTRL_TEN 1 /* Timer enable */ - -/* WDOG enable */ -#define WCR_WDE 0x04 -#define WSR_UNLOCK1 0x5555 -#define WSR_UNLOCK2 0xAAAA - -/* MAX bits */ -#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) - -/* M3IF bits */ -#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) - -/* WEIM bits */ -/* 13 fields of the upper CS control register */ -#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ - cnc, wsc, ew, wws, edc) \ - ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ - (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ - (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) -/* 12 fields of the lower CS control register */ -#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ - csa, ebc, dsz, csn, psr, cre, wrap, csen) \ - ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ - (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ - (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) -/* 14 fields of the additional CS control register */ -#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ - wwu, age, cnc2, fce) \ - ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ - (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ - (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ - (age) << 2 | (cnc2) << 1 | (fce) << 0) - -/* Names used in GPIO driver */ -#define GPIO1_BASE_ADDR IMX_GPIO1_BASE -#define GPIO2_BASE_ADDR IMX_GPIO2_BASE -#define GPIO3_BASE_ADDR IMX_GPIO3_BASE -#define GPIO4_BASE_ADDR IMX_GPIO4_BASE - -/* - * CSPI register definitions - */ -#define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 - -#define MXC_SPI_BASE_ADDRESSES \ - IMX_CSPI1_BASE, \ - IMX_CSPI2_BASE, \ - IMX_CSPI3_BASE - -#endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h deleted file mode 100644 index 1ce7a85..0000000 --- a/arch/arm/include/asm/arch-mx25/iomux-mx25.h +++ /dev/null @@ -1,537 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on mainline Linux i.MX iomux-mx25.h file: - * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de> - * - * Based on Linux arch/arm/mach-mx25/mx25_pins.h: - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - */ - -#ifndef __IOMUX_MX25_H__ -#define __IOMUX_MX25_H__ - -#include <asm/mach-imx/iomux-v3.h> - -/* Pad control groupings */ -#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP -#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -/* - * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL), - - MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL), - MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL), - - MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL), - - MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL), - - MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL), - - MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL), - MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL), - MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL), - MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL), - MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL), - MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE), - MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE), - - MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL), - MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL), - MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL), - - MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL), - - MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL), - - MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL), - - MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL), - - MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL), - - MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL), - - MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE), - MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN), - MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL), - MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL), - MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL), - - /* - * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD - * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM - * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the SD1_CMD function doesn't enable the input path for - * this pin. - * This might have side effects for other hardware units that are connected to - * that pin and use the respective function as input. - */ - MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL), - MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE), - - MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL), - MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX25_H__ */ diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h deleted file mode 100644 index 68bddf4..0000000 --- a/arch/arm/include/asm/arch-mx25/macro.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Matthias Weisser <weisserm@arcor.de> - * - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby <jrigby@gmail.com> - * - * Common asm macros for imx25 - */ - -#ifndef __ASM_ARM_ARCH_MACRO_H__ -#define __ASM_ARM_ARCH_MACRO_H__ -#ifdef __ASSEMBLY__ - -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include <asm/macro.h> - -/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - * - * Default argument values: - * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to - * user-mode. - */ -.macro init_aips mpr=0x77777777 - ldr r0, =IMX_AIPS1_BASE - ldr r1, =\mpr - str r1, [r0, #AIPS_MPR_0_7] - str r1, [r0, #AIPS_MPR_8_15] - ldr r2, =IMX_AIPS2_BASE - str r1, [r2, #AIPS_MPR_0_7] - str r1, [r2, #AIPS_MPR_8_15] -.endm - -/* - * MAX (Multi-Layer AHB Crossbar Switch) setup - * - * Default argument values: - * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA - * - SGPCR: always park on last master - * - MGPCR: restore default values - */ -.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 - ldr r0, =IMX_MAX_BASE - ldr r1, =\mpr - str r1, [r0, #MAX_MPR0] /* for S0 */ - str r1, [r0, #MAX_MPR1] /* for S1 */ - str r1, [r0, #MAX_MPR2] /* for S2 */ - str r1, [r0, #MAX_MPR3] /* for S3 */ - str r1, [r0, #MAX_MPR4] /* for S4 */ - ldr r1, =\sgpcr - str r1, [r0, #MAX_SGPCR0] /* for S0 */ - str r1, [r0, #MAX_SGPCR1] /* for S1 */ - str r1, [r0, #MAX_SGPCR2] /* for S2 */ - str r1, [r0, #MAX_SGPCR3] /* for S3 */ - str r1, [r0, #MAX_SGPCR4] /* for S4 */ - ldr r1, =\mgpcr - str r1, [r0, #MAX_MGPCR0] /* for M0 */ - str r1, [r0, #MAX_MGPCR1] /* for M1 */ - str r1, [r0, #MAX_MGPCR2] /* for M2 */ - str r1, [r0, #MAX_MGPCR3] /* for M3 */ - str r1, [r0, #MAX_MGPCR4] /* for M4 */ -.endm - -/* - * M3IF setup - * - * Default argument values: - * - CTL: - * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 - * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 - * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 - * ------------ - * 0x00000001 - */ -.macro init_m3if ctl=0x00000001 - /* M3IF Control Register (M3IFCTL) */ - write32 IMX_M3IF_CTRL_BASE, \ctl -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/arch/arm/include/asm/arch-mx27/clock.h b/arch/arm/include/asm/arch-mx27/clock.h deleted file mode 100644 index ab96431..0000000 --- a/arch/arm/include/asm/arch-mx27/clock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -enum mxc_clock { - MXC_ARM_CLK, - MXC_I2C_CLK, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_FEC_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx27/gpio.h b/arch/arm/include/asm/arch-mx27/gpio.h deleted file mode 100644 index 9f342eb..0000000 --- a/arch/arm/include/asm/arch-mx27/gpio.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 - * Philippe Reynes <tremyfr@yahoo.fr> - */ - - -#ifndef __ASM_ARCH_MX27_GPIO_H -#define __ASM_ARCH_MX27_GPIO_H - -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dir; /* DDIR */ - u32 ocr1; - u32 ocr2; - u32 iconfa1; - u32 iconfa2; - u32 iconfb1; - u32 iconfb2; - u32 gpio_dr; /* DR */ - u32 gius; - u32 gpio_psr; /* SSR */ - u32 icr1; - u32 icr2; - u32 imr; - u32 isr; - u32 gpr; - u32 swr; - u32 puen; - u32 res[0x2f]; -}; - -/* This structure is used by the function imx_gpio_mode */ -struct gpio_port_regs { - struct gpio_regs port[6]; -}; - -/* - * GPIO Module and I/O Multiplexer - */ -#define PORTA 0 -#define PORTB 1 -#define PORTC 2 -#define PORTD 3 -#define PORTE 4 -#define PORTF 5 - -#define GPIO_PIN_MASK 0x1f -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) -#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) -#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) -#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) -#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) -#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) -#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) - -#endif diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h deleted file mode 100644 index d39f6b0..0000000 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ /dev/null @@ -1,480 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#include <asm/arch/regs-rtc.h> - -#ifndef __ASSEMBLY__ - -extern void imx_gpio_mode (int gpio_mode); - -#ifdef CONFIG_MXC_UART -extern void mx27_uart1_init_pins(void); -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -extern void mx27_fec_init_pins(void); -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MMC_MXC -extern void mx27_sd1_init_pins(void); -extern void mx27_sd2_init_pins(void); -#endif /* CONFIG_MMC_MXC */ - -/* AIPI */ -struct aipi_regs { - u32 psr0; - u32 psr1; -}; - -/* System Control */ -struct system_control_regs { - u32 res[5]; - u32 fmcr; - u32 gpcr; - u32 wbcr; - u32 dscr1; - u32 dscr2; - u32 dscr3; - u32 dscr4; - u32 dscr5; - u32 dscr6; - u32 dscr7; - u32 dscr8; - u32 dscr9; - u32 dscr10; - u32 dscr11; - u32 dscr12; - u32 dscr13; - u32 pscr; - u32 pmcr; - u32 res1; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; -}; - -/* Chip Select Registers */ -struct weim_regs { - u32 cs0u; /* Chip Select 0 Upper Register */ - u32 cs0l; /* Chip Select 0 Lower Register */ - u32 cs0a; /* Chip Select 0 Addition Register */ - u32 pad0; - u32 cs1u; /* Chip Select 1 Upper Register */ - u32 cs1l; /* Chip Select 1 Lower Register */ - u32 cs1a; /* Chip Select 1 Addition Register */ - u32 pad1; - u32 cs2u; /* Chip Select 2 Upper Register */ - u32 cs2l; /* Chip Select 2 Lower Register */ - u32 cs2a; /* Chip Select 2 Addition Register */ - u32 pad2; - u32 cs3u; /* Chip Select 3 Upper Register */ - u32 cs3l; /* Chip Select 3 Lower Register */ - u32 cs3a; /* Chip Select 3 Addition Register */ - u32 pad3; - u32 cs4u; /* Chip Select 4 Upper Register */ - u32 cs4l; /* Chip Select 4 Lower Register */ - u32 cs4a; /* Chip Select 4 Addition Register */ - u32 pad4; - u32 cs5u; /* Chip Select 5 Upper Register */ - u32 cs5l; /* Chip Select 5 Lower Register */ - u32 cs5a; /* Chip Select 5 Addition Register */ - u32 pad5; - u32 eim; /* WEIM Configuration Register */ -}; - -/* SDRAM Controller registers */ -struct esdramc_regs { -/* Enhanced SDRAM Control Register 0 */ - u32 esdctl0; -/* Enhanced SDRAM Configuration Register 0 */ - u32 esdcfg0; -/* Enhanced SDRAM Control Register 1 */ - u32 esdctl1; -/* Enhanced SDRAM Configuration Register 1 */ - u32 esdcfg1; -/* Enhanced SDRAM Miscellanious Register */ - u32 esdmisc; -}; - -/* Watchdog Registers*/ -struct wdog_regs { - u16 wcr; - u16 wsr; - u16 wstr; -}; - -/* PLL registers */ -struct pll_regs { - u32 cscr; /* Clock Source Control Register */ - u32 mpctl0; /* MCU PLL Control Register 0 */ - u32 mpctl1; /* MCU PLL Control Register 1 */ - u32 spctl0; /* System PLL Control Register 0 */ - u32 spctl1; /* System PLL Control Register 1 */ - u32 osc26mctl; /* Oscillator 26M Register */ - u32 pcdr0; /* Peripheral Clock Divider Register 0 */ - u32 pcdr1; /* Peripheral Clock Divider Register 1 */ - u32 pccr0; /* Peripheral Clock Control Register 0 */ - u32 pccr1; /* Peripheral Clock Control Register 1 */ - u32 ccsr; /* Clock Control Status Register */ -}; - -/* - * Definitions for the clocksource registers - */ -struct gpt_regs { - u32 gpt_tctl; - u32 gpt_tprer; - u32 gpt_tcmp; - u32 gpt_tcr; - u32 gpt_tcn; - u32 gpt_tstat; -}; - -/* IIM Control Registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[2]; -}; - -struct fuse_bank0_regs { - u32 fuse0_3[5]; - u32 mac_addr[6]; - u32 fuse10_31[0x16]; -}; - -#endif - -#define ARCH_MXC - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE) -#define UART1_BASE (0x0a000 + IMX_IO_BASE) -#define UART2_BASE (0x0b000 + IMX_IO_BASE) -#define UART3_BASE (0x0c000 + IMX_IO_BASE) -#define UART4_BASE (0x0d000 + IMX_IO_BASE) -#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) -#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) -#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) -#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) -#define IIM_BASE_ADDR IMX_IIM_BASE -#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) - -#define IMX_NFC_BASE (0xD8000000) -#define IMX_ESD_BASE (0xD8001000) -#define IMX_WEIM_BASE (0xD8002000) - -#define NFC_BASE_ADDR IMX_NFC_BASE - - -/* FMCR System Control bit definition*/ -#define UART4_RXD_CTL (1 << 25) -#define UART4_RTS_CTL (1 << 24) -#define KP_COL6_CTL (1 << 18) -#define KP_ROW7_CTL (1 << 17) -#define KP_ROW6_CTL (1 << 16) -#define PC_WAIT_B_CTL (1 << 14) -#define PC_READY_CTL (1 << 13) -#define PC_VS1_CTL (1 << 12) -#define PC_VS2_CTL (1 << 11) -#define PC_BVD1_CTL (1 << 10) -#define PC_BVD2_CTL (1 << 9) -#define IOS16_CTL (1 << 8) -#define NF_FMS (1 << 5) -#define NF_16BIT_SEL (1 << 4) -#define SLCDC_SEL (1 << 2) -#define SDCS1_SEL (1 << 1) -#define SDCS0_SEL (1 << 0) - - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_AHB_DIV -#define CSCR_ARM_DIV -#define CSCR_ARM_SRC_MPLL (1 << 15) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_MPLL_RESTART (1 << 18) -#define CSCR_SPLL_RESTART (1 << 19) -#define CSCR_MSHC_SEL (1 << 20) -#define CSCR_H264_SEL (1 << 21) -#define CSCR_SSI1_SEL (1 << 22) -#define CSCR_SSI2_SEL (1 << 23) -#define CSCR_SD_CNT -#define CSCR_USB_DIV -#define CSCR_UPDATE_DIS (1 << 31) - -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR0_SSI2_EN (1 << 0) -#define PCCR0_SSI1_EN (1 << 1) -#define PCCR0_SLCDC_EN (1 << 2) -#define PCCR0_SDHC3_EN (1 << 3) -#define PCCR0_SDHC2_EN (1 << 4) -#define PCCR0_SDHC1_EN (1 << 5) -#define PCCR0_SDC_EN (1 << 6) -#define PCCR0_SAHARA_EN (1 << 7) -#define PCCR0_RTIC_EN (1 << 8) -#define PCCR0_RTC_EN (1 << 9) -#define PCCR0_PWM_EN (1 << 11) -#define PCCR0_OWIRE_EN (1 << 12) -#define PCCR0_MSHC_EN (1 << 13) -#define PCCR0_LCDC_EN (1 << 14) -#define PCCR0_KPP_EN (1 << 15) -#define PCCR0_IIM_EN (1 << 16) -#define PCCR0_I2C2_EN (1 << 17) -#define PCCR0_I2C1_EN (1 << 18) -#define PCCR0_GPT6_EN (1 << 19) -#define PCCR0_GPT5_EN (1 << 20) -#define PCCR0_GPT4_EN (1 << 21) -#define PCCR0_GPT3_EN (1 << 22) -#define PCCR0_GPT2_EN (1 << 23) -#define PCCR0_GPT1_EN (1 << 24) -#define PCCR0_GPIO_EN (1 << 25) -#define PCCR0_FEC_EN (1 << 26) -#define PCCR0_EMMA_EN (1 << 27) -#define PCCR0_DMA_EN (1 << 28) -#define PCCR0_CSPI3_EN (1 << 29) -#define PCCR0_CSPI2_EN (1 << 30) -#define PCCR0_CSPI1_EN (1 << 31) - -#define PCCR1_MSHC_BAUDEN (1 << 2) -#define PCCR1_NFC_BAUDEN (1 << 3) -#define PCCR1_SSI2_BAUDEN (1 << 4) -#define PCCR1_SSI1_BAUDEN (1 << 5) -#define PCCR1_H264_BAUDEN (1 << 6) -#define PCCR1_PERCLK4_EN (1 << 7) -#define PCCR1_PERCLK3_EN (1 << 8) -#define PCCR1_PERCLK2_EN (1 << 9) -#define PCCR1_PERCLK1_EN (1 << 10) -#define PCCR1_HCLK_USB (1 << 11) -#define PCCR1_HCLK_SLCDC (1 << 12) -#define PCCR1_HCLK_SAHARA (1 << 13) -#define PCCR1_HCLK_RTIC (1 << 14) -#define PCCR1_HCLK_LCDC (1 << 15) -#define PCCR1_HCLK_H264 (1 << 16) -#define PCCR1_HCLK_FEC (1 << 17) -#define PCCR1_HCLK_EMMA (1 << 18) -#define PCCR1_HCLK_EMI (1 << 19) -#define PCCR1_HCLK_DMA (1 << 20) -#define PCCR1_HCLK_CSI (1 << 21) -#define PCCR1_HCLK_BROM (1 << 22) -#define PCCR1_HCLK_ATA (1 << 23) -#define PCCR1_WDT_EN (1 << 24) -#define PCCR1_USB_EN (1 << 25) -#define PCCR1_UART6_EN (1 << 26) -#define PCCR1_UART5_EN (1 << 27) -#define PCCR1_UART4_EN (1 << 28) -#define PCCR1_UART3_EN (1 << 29) -#define PCCR1_UART2_EN (1 << 30) -#define PCCR1_UART1_EN (1 << 31) - -/* SDRAM Controller registers bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) -#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) - -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) -#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) - -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) - -/* Clocksource Bitfields */ -#define TCTL_SWR (1 << 15) /* Software reset */ -#define TCTL_FRR (1 << 8) /* Freerun / restart */ -#define TCTL_CAP (3 << 6) /* Capture Edge */ -#define TCTL_OM (1 << 5) /* output mode */ -#define TCTL_IRQEN (1 << 4) /* interrupt enable */ -#define TCTL_CLKSOURCE 1 /* Clock source bit position */ -#define TCTL_TEN 1 /* Timer enable */ -#define TPRER_PRES 0xff /* Prescale */ -#define TSTAT_CAPT (1 << 1) /* Capture event */ -#define TSTAT_COMP 1 /* Compare event */ - -#define GPIO1_BASE_ADDR 0x10015000 -#define GPIO2_BASE_ADDR 0x10015100 -#define GPIO3_BASE_ADDR 0x10015200 -#define GPIO4_BASE_ADDR 0x10015300 -#define GPIO5_BASE_ADDR 0x10015400 -#define GPIO6_BASE_ADDR 0x10015500 - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -#define IIM_STAT_BUSY (1 << 7) -#define IIM_STAT_PRGD (1 << 1) -#define IIM_STAT_SNSD (1 << 0) -#define IIM_ERR_PRGE (1 << 7) -#define IIM_ERR_WPE (1 << 6) -#define IIM_ERR_OPE (1 << 5) -#define IIM_ERR_RPE (1 << 4) -#define IIM_ERR_WLRE (1 << 3) -#define IIM_ERR_SNSE (1 << 2) -#define IIM_ERR_PARITYE (1 << 1) - -#endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h deleted file mode 100644 index d7b5ca2..0000000 --- a/arch/arm/include/asm/arch-mx27/mxcmmc.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> - */ - -#ifndef ASM_ARCH_MXCMMC_H -#define ASM_ARCH_MXCMMC_H - -int mxc_mmc_init(bd_t *bis); - -#endif diff --git a/arch/arm/include/asm/arch-mx27/regs-rtc.h b/arch/arm/include/asm/arch-mx27/regs-rtc.h deleted file mode 100644 index d373ab1..0000000 --- a/arch/arm/include/asm/arch-mx27/regs-rtc.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX27 RTC Register Definitions - * - * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr> - */ - -#ifndef __MX27_REGS_RTC_H__ -#define __MX27_REGS_RTC_H__ - -#ifndef __ASSEMBLY__ -struct rtc_regs { - u32 hourmin; - u32 seconds; - u32 alrm_hm; - u32 alrm_sec; - u32 rtcctl; - u32 rtcisr; - u32 rtcienr; - u32 stpwch; - u32 dayr; - u32 dayalarm; -}; -#endif /* __ASSEMBLY__*/ - -#endif /* __MX28_REGS_RTC_H__ */ diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h deleted file mode 100644 index aafc2d6..0000000 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#define MXC_HCLK CONFIG_MX31_HCLK_FREQ - -#define MXC_CLK32 CONFIG_MX31_CLK32 - -enum mxc_clock { - MXC_ARM_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_CSPI_CLK, - MXC_UART_CLK, - MXC_IPU_CLK, - MXC_ESDHC_CLK, - MXC_I2C_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -extern u32 imx_get_uartclk(void); -extern void mx31_gpio_mux(unsigned long mode); -extern void mx31_set_pad(enum iomux_pins pin, u32 config); -extern void mx31_set_gpr(enum iomux_gp_func gp, char en); - -void mx31_uart1_hw_init(void); -void mx31_uart2_hw_init(void); -void mx31_spi2_hw_init(void); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h deleted file mode 100644 index 45e9fc6..0000000 --- a/arch/arm/include/asm/arch-mx31/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - */ - - -#ifndef __ASM_ARCH_MX31_GPIO_H -#define __ASM_ARCH_MX31_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h deleted file mode 100644 index 9e271d6..0000000 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ /dev/null @@ -1,926 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - */ - -#ifndef __ASM_ARCH_MX31_IMX_REGS_H -#define __ASM_ARCH_MX31_IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock control module registers */ -struct clock_control_regs { - u32 ccmr; - u32 pdr0; - u32 pdr1; - u32 rcsr; - u32 mpctl; - u32 upctl; - u32 spctl; - u32 cosr; - u32 cgr0; - u32 cgr1; - u32 cgr2; - u32 wimr0; - u32 ldc; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; - u32 ltr0; - u32 ltr1; - u32 ltr2; - u32 ltr3; - u32 ltbr0; - u32 ltbr1; - u32 pmcr0; - u32 pmcr1; - u32 pdr2; -}; - -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 intr; - u32 dma; - u32 stat; - u32 period; - u32 test; -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_5[6]; - u32 usr; - u32 fuse7_15[9]; -}; - -struct fuse_bank2_regs { - u32 fuse0; - u32 uid[8]; - u32 fuse9_15[7]; -}; - -struct iomuxc_regs { - u32 unused1; - u32 unused2; - u32 gpr; -}; - -struct mx3_cpu_type { - u8 srev; - u32 v; -}; - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323), - MX31_PIN_PWMO = IOMUX_PIN(9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN(8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGP_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* Bit definitions for RCSR register in CCM */ -#define CCM_RCSR_NF16B (1 << 31) -#define CCM_RCSR_NFMS (1 << 30) - -/* WEIM CS control registers */ -struct mx31_weim_cscr { - u32 upper; - u32 lower; - u32 additional; - u32 reserved; -}; - -struct mx31_weim { - struct mx31_weim_cscr cscr[6]; -}; - -/* ESD control registers */ -struct esdc_regs { - u32 ctl0; - u32 cfg0; - u32 ctl1; - u32 cfg1; - u32 misc; - u32 dly[5]; - u32 dlyl; -}; - -#endif - -#define ARCH_MXC - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -#define CCM_BASE 0x53f80000 -#define CCM_CCMR (CCM_BASE + 0x00) -#define CCM_PDR0 (CCM_BASE + 0x04) -#define CCM_PDR1 (CCM_BASE + 0x08) -#define CCM_RCSR (CCM_BASE + 0x0c) -#define CCM_MPCTL (CCM_BASE + 0x10) -#define CCM_UPCTL (CCM_BASE + 0x14) -#define CCM_SPCTL (CCM_BASE + 0x18) -#define CCM_COSR (CCM_BASE + 0x1C) -#define CCM_CGR0 (CCM_BASE + 0x20) -#define CCM_CGR1 (CCM_BASE + 0x24) -#define CCM_CGR2 (CCM_BASE + 0x28) - -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) -#define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) -#define CCMR_CKIH (2 << 1) - -#define MX31_IIM_BASE_ADDR 0x5001C000 -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR - -#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) -#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) -#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define PDR0_MCU_PODF(x) ((x) & 0x7) - -#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30) -#define PDR1_USB_PODF(x) (((x) & 0x7) << 27) -#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24) -#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18) -#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15) -#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9) -#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6) -#define PDR1_SSI1_PODF(x) ((x) & 0x3f) - -#define PLL_BRMO(x) (((x) & 0x1) << 31) -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) -#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) -#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) -#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) -#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) -#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3) -#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7) -#define GET_PDR0_MCU_PODF(x) ((x) & 0x7) - -#define GET_PLL_PD(x) (((x) >> 26) & 0xf) -#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff) -#define GET_PLL_MFI(x) (((x) >> 10) & 0xf) -#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) - - -#define WEIM_ESDCTL0 0xB8001000 -#define WEIM_ESDCFG0 0xB8001004 -#define WEIM_ESDCTL1 0xB8001008 -#define WEIM_ESDCFG1 0xB800100C -#define WEIM_ESDMISC 0xB8001010 - -#define UART1_BASE 0x43F90000 -#define UART2_BASE 0x43F94000 -#define UART3_BASE 0x5000C000 -#define UART4_BASE 0x43FB0000 -#define UART5_BASE 0x43FB4000 - -#define I2C1_BASE_ADDR 0x43f80000 -#define I2C1_CLK_OFFSET 26 -#define I2C2_BASE_ADDR 0x43F98000 -#define I2C2_CLK_OFFSET 28 -#define I2C3_BASE_ADDR 0x43f84000 -#define I2C3_CLK_OFFSET 30 - -#define ESDCTL_SDE (1 << 31) -#define ESDCTL_CMD_RW (0 << 28) -#define ESDCTL_CMD_PRECHARGE (1 << 28) -#define ESDCTL_CMD_AUTOREFRESH (2 << 28) -#define ESDCTL_CMD_LOADMODEREG (3 << 28) -#define ESDCTL_CMD_MANUALREFRESH (4 << 28) -#define ESDCTL_ROW_13 (2 << 24) -#define ESDCTL_ROW(x) ((x) << 24) -#define ESDCTL_COL_9 (1 << 20) -#define ESDCTL_COL(x) ((x) << 20) -#define ESDCTL_DSIZ(x) ((x) << 16) -#define ESDCTL_SREFR(x) ((x) << 13) -#define ESDCTL_PWDT(x) ((x) << 10) -#define ESDCTL_FP(x) ((x) << 8) -#define ESDCTL_BL(x) ((x) << 7) -#define ESDCTL_PRCT(x) ((x) << 0) - -#define ESDCTL_BASE_ADDR 0xB8001000 - -/* 13 fields of the upper CS control register */ -#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ - cnc, wsc, ew, wws, edc) \ - ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ - (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ - (wws) << 4 | (edc) << 0) -/* 12 fields of the lower CS control register */ -#define CSCR_L(oea, oen, ebwa, ebwn, \ - csa, ebc, dsz, csn, psr, cre, wrap, csen) \ - ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ - (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ - (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) -/* 14 fields of the additional CS control register */ -#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ - wwu, age, cnc2, fce) \ - ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ - (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ - (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ - (age) << 2 | (cnc2) << 1 | (fce) << 0) - -#define WEIM_BASE 0xb8002000 - -#define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) -#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) - -#define IPU_BASE 0x53fc0000 -#define IPU_CONF IPU_BASE - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_CSI_EN (1<<0) - -#define ARM_PPMRR 0x40000015 - -#define WDOG1_BASE_ADDR 0x53FDC000 - -/* - * GPIO - */ -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define GPIO_DR 0x00000000 /* data register */ -#define GPIO_GDIR 0x00000004 /* direction register */ -#define GPIO_PSR 0x00000008 /* pad status register */ - -/* - * Signal Multiplexing (IOMUX) - */ - -/* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) -#define MUX_CTL_OUT_ALT1 (2 << 4) -#define MUX_CTL_OUT_ALT2 (3 << 4) -#define MUX_CTL_OUT_ALT3 (4 << 4) -#define MUX_CTL_OUT_ALT4 (5 << 4) -#define MUX_CTL_OUT_ALT5 (6 << 4) -#define MUX_CTL_OUT_ALT6 (7 << 4) -#define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) -#define MUX_CTL_IN_FUNC (2 << 0) -#define MUX_CTL_IN_ALT1 (4 << 0) -#define MUX_CTL_IN_ALT2 (8 << 0) - -#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) -#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) -#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) -#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) - -/* Register offsets based on IOMUXC_BASE */ -/* 0x00 .. 0x7b */ -#define MUX_CTL_CSPI3_MISO 0x0c -#define MUX_CTL_CSPI3_SCLK 0x0d -#define MUX_CTL_CSPI3_SPI_RDY 0x0e -#define MUX_CTL_CSPI3_MOSI 0x13 - -#define MUX_CTL_SD1_DATA1 0x18 -#define MUX_CTL_SD1_DATA2 0x19 -#define MUX_CTL_SD1_DATA3 0x1a -#define MUX_CTL_SD1_CMD 0x1d -#define MUX_CTL_SD1_CLK 0x1e -#define MUX_CTL_SD1_DATA0 0x1f - -#define MUX_CTL_USBH2_DATA1 0x40 -#define MUX_CTL_USBH2_DIR 0x44 -#define MUX_CTL_USBH2_STP 0x45 -#define MUX_CTL_USBH2_NXT 0x46 -#define MUX_CTL_USBH2_DATA0 0x47 -#define MUX_CTL_USBH2_CLK 0x4B - -#define MUX_CTL_TXD2 0x70 -#define MUX_CTL_RTS2 0x71 -#define MUX_CTL_CTS2 0x72 -#define MUX_CTL_RXD2 0x77 - -#define MUX_CTL_RTS1 0x7c -#define MUX_CTL_CTS1 0x7d -#define MUX_CTL_DTR_DCE1 0x7e -#define MUX_CTL_DSR_DCE1 0x7f -#define MUX_CTL_CSPI2_SCLK 0x80 -#define MUX_CTL_CSPI2_SPI_RDY 0x81 -#define MUX_CTL_RXD1 0x82 -#define MUX_CTL_TXD1 0x83 -#define MUX_CTL_CSPI2_MISO 0x84 -#define MUX_CTL_CSPI2_SS0 0x85 -#define MUX_CTL_CSPI2_SS1 0x86 -#define MUX_CTL_CSPI2_SS2 0x87 -#define MUX_CTL_CSPI1_SS2 0x88 -#define MUX_CTL_CSPI1_SCLK 0x89 -#define MUX_CTL_CSPI1_SPI_RDY 0x8a -#define MUX_CTL_CSPI2_MOSI 0x8b -#define MUX_CTL_CSPI1_MOSI 0x8c -#define MUX_CTL_CSPI1_MISO 0x8d -#define MUX_CTL_CSPI1_SS0 0x8e -#define MUX_CTL_CSPI1_SS1 0x8f -#define MUX_CTL_STXD6 0x90 -#define MUX_CTL_SRXD6 0x91 -#define MUX_CTL_SCK6 0x92 -#define MUX_CTL_SFS6 0x93 - -#define MUX_CTL_STXD3 0x9C -#define MUX_CTL_SRXD3 0x9D -#define MUX_CTL_SCK3 0x9E -#define MUX_CTL_SFS3 0x9F - -#define MUX_CTL_NFC_WP 0xD0 -#define MUX_CTL_NFC_CE 0xD1 -#define MUX_CTL_NFC_RB 0xD2 -#define MUX_CTL_NFC_WE 0xD4 -#define MUX_CTL_NFC_RE 0xD5 -#define MUX_CTL_NFC_ALE 0xD6 -#define MUX_CTL_NFC_CLE 0xD7 - - -#define MUX_CTL_CAPTURE 0x150 -#define MUX_CTL_COMPARE 0x151 - -/* - * Helper macros for the MUX_[contact name]__[pin function] macros - */ -#define IOMUX_MODE_POS 9 -#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) - -/* - * These macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ -#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) -#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) -#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) -#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) - -#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) -#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) -#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) -#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) - -#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) -#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) -#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) -#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) -#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) -#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) -#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) -#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) -#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) - -/* PAD control registers for SDR/DDR */ -#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) -#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) -#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) -#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) -#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) -#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) -#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) -#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) -#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) -#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) -#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) -#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) -#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) -#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) -#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) -#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) -#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) -#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) -#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) -#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) -#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) -#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) -#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) -#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) -#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) -#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) -#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) -#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) -#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE 0x70000000 -#define CSD0_BASE 0x80000000 -#define CSD1_BASE 0x90000000 -#define CS0_BASE 0xA0000000 -#define CS1_BASE 0xA8000000 -#define CS2_BASE 0xB0000000 -#define CS3_BASE 0xB2000000 -#define CS4_BASE 0xB4000000 -#define CS4_PSRAM_BASE 0xB5000000 -#define CS5_BASE 0xB6000000 -#define PCMCIA_MEM_BASE 0xC0000000 - -/* - * NAND controller - */ -#define NFC_BASE_ADDR 0xB8000000 - -/* SD card controller */ -#define SDHC1_BASE_ADDR 0x50004000 -#define SDHC2_BASE_ADDR 0x50008000 - -/* - * Internal RAM (16KB) - */ -#define IRAM_BASE_ADDR 0x1FFFC000 -#define IRAM_SIZE (16 * 1024) - -#define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) -#define IMX_USB_PORT_OFFSET 0x200 - -/* - * CSPI register definitions - */ -#define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 8) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0x1f - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 - - -#define MXC_SPI_BASE_ADDRESSES \ - 0x43fa4000, \ - 0x50010000, \ - 0x53f84000, - -/* - * Generic timer support - */ -#ifdef CONFIG_MX31_CLK32 -#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 -#else -#define CONFIG_SYS_TIMER_RATE 32768 -#endif - -#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h deleted file mode 100644 index e408788..0000000 --- a/arch/arm/include/asm/arch-mx31/sys_proto.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at - */ - -#ifndef _MX31_SYS_PROTO_H_ -#define _MX31_SYS_PROTO_H_ - -#include <asm/mach-imx/sys_proto.h> - -struct mxc_weimcs { - u32 upper; - u32 lower; - u32 additional; -}; - -void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); -int mxc_mmc_init(bd_t *bis); -#endif diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h deleted file mode 100644 index 7885340..0000000 --- a/arch/arm/include/asm/arch-mx35/clock.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_MX35_HCLK_FREQ -#define MXC_HCLK CONFIG_MX35_HCLK_FREQ -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_MX35_CLK32 -#define MXC_CLK32 CONFIG_MX35_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_ESDHC1_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_USB_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, -}; - -enum mxc_main_clock { - CPU_CLK, - AHB_CLK, - IPG_CLK, - IPG_PER_CLK, - NFC_CLK, - USB_CLK, - HSP_CLK, -}; - -enum mxc_peri_clock { - UART1_BAUD, - UART2_BAUD, - UART3_BAUD, - SSI1_BAUD, - SSI2_BAUD, - CSI_BAUD, - MSHC_CLK, - ESDHC1_CLK, - ESDHC2_CLK, - ESDHC3_CLK, - SPDIF_CLK, - SPI1_CLK, - SPI2_CLK, -}; - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h deleted file mode 100644 index fc65a3a..0000000 --- a/arch/arm/include/asm/arch-mx35/crm_regs.h +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004-2009 Freescale Semiconductor, Inc. - */ - -#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ -#define __CPU_ARM1136_MX35_CRM_REGS_H__ - -/* Register bit definitions */ -#define MXC_CCM_CCMR_WFI (1 << 30) -#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) -#define MXC_CCM_CCMR_VSTBY (1 << 28) -#define MXC_CCM_CCMR_WBEN (1 << 27) -#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 -#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) -#define MXC_CCM_CCMR_ROMW_OFFSET 18 -#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 16 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) -#define MXC_CCM_CCMR_LPM_OFFSET 14 -#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) -#define MXC_CCM_CCMR_UPE (1 << 9) -#define MXC_CCM_CCMR_MPE (1 << 3) - -#define MXC_CCM_PDR0_PER_SEL (1 << 26) -#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) -#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 -#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) -#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 -#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) -#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) -#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) -#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 -#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) -#define MXC_CCM_PDR0_AUTO_CON 0x1 - -#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 -#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) -#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 -#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) -#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) - -#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 -#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) -#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 -#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 -#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR2_CSI_M_U (1 << 7) -#define MXC_CCM_PDR2_SSI_M_U (1 << 6) -#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 -#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) - -#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 -#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) -#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 -#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) -#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 14) -#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) - -#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 -#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) -#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) -#define MXC_CCM_PDR4_USB_M_U (1 << 9) - -/* Bit definitions for RCSR */ -#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) -#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) -#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) -#define MXC_CCM_RCSR_PAGE_512 (0 << 27) -#define MXC_CCM_RCSR_PAGE_2K (1 << 27) -#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) -#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) -#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) -#define MXC_CCM_RCSR_NF16B (1 << 14) -#define MXC_CCM_RCSR_NFC_4K (1 << 9) -#define MXC_CCM_RCSR_NFC_FMS (1 << 8) - -/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ -#define MXC_CCM_PCTL_BRM 0x80000000 -#define MXC_CCM_PCTL_PD_OFFSET 26 -#define MXC_CCM_PCTL_PD_MASK (0xF << 26) -#define MXC_CCM_PCTL_MFD_OFFSET 16 -#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) -#define MXC_CCM_PCTL_MFI_OFFSET 10 -#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) -#define MXC_CCM_PCTL_MFN_OFFSET 0 -#define MXC_CCM_PCTL_MFN_MASK 0x3FF - -/* Bit definitions for Audio clock mux register*/ -#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 -#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) -#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 -#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) -#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 -#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) -#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 -#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) - -/* Bit definitions for Clock gating Register*/ -#define MXC_CCM_CGR_CG_MASK 0x3 -#define MXC_CCM_CGR_CG_OFF 0x0 -#define MXC_CCM_CGR_CG_RUN_ON 0x1 -#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 -#define MXC_CCM_CGR_CG_ON 0x3 - -#define MXC_CCM_CGR0_ASRC_OFFSET 0 -#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) -#define MXC_CCM_CGR0_ATA_OFFSET 2 -#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) -#define MXC_CCM_CGR0_CAN1_OFFSET 6 -#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) -#define MXC_CCM_CGR0_CAN2_OFFSET 8 -#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) -#define MXC_CCM_CGR0_CSPI1_OFFSET 10 -#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) -#define MXC_CCM_CGR0_CSPI2_OFFSET 12 -#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) -#define MXC_CCM_CGR0_ECT_OFFSET 14 -#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) -#define MXC_CCM_CGR0_EDIO_OFFSET 16 -#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16) -#define MXC_CCM_CGR0_EMI_OFFSET 18 -#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) -#define MXC_CCM_CGR0_EPIT1_OFFSET 20 -#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) -#define MXC_CCM_CGR0_EPIT2_OFFSET 22 -#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) -#define MXC_CCM_CGR0_ESAI_OFFSET 24 -#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) -#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 -#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) -#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 -#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) -#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 -#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) - -#define MXC_CCM_CGR1_FEC_OFFSET 0 -#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) -#define MXC_CCM_CGR1_GPIO1_OFFSET 2 -#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) -#define MXC_CCM_CGR1_GPIO2_OFFSET 4 -#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) -#define MXC_CCM_CGR1_GPIO3_OFFSET 6 -#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) -#define MXC_CCM_CGR1_GPT_OFFSET 8 -#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) -#define MXC_CCM_CGR1_I2C1_OFFSET 10 -#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) -#define MXC_CCM_CGR1_I2C2_OFFSET 12 -#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) -#define MXC_CCM_CGR1_I2C3_OFFSET 14 -#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) -#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 -#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) -#define MXC_CCM_CGR1_IPU_OFFSET 18 -#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) -#define MXC_CCM_CGR1_KPP_OFFSET 20 -#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) -#define MXC_CCM_CGR1_MLB_OFFSET 22 -#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) -#define MXC_CCM_CGR1_MSHC_OFFSET 24 -#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) -#define MXC_CCM_CGR1_OWIRE_OFFSET 26 -#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) -#define MXC_CCM_CGR1_PWM_OFFSET 28 -#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) -#define MXC_CCM_CGR1_RNGC_OFFSET 30 -#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) - -#define MXC_CCM_CGR2_RTC_OFFSET 0 -#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) -#define MXC_CCM_CGR2_RTIC_OFFSET 2 -#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) -#define MXC_CCM_CGR2_SCC_OFFSET 4 -#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) -#define MXC_CCM_CGR2_SDMA_OFFSET 6 -#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) -#define MXC_CCM_CGR2_SPBA_OFFSET 8 -#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) -#define MXC_CCM_CGR2_SPDIF_OFFSET 10 -#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) -#define MXC_CCM_CGR2_SSI1_OFFSET 12 -#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) -#define MXC_CCM_CGR2_SSI2_OFFSET 14 -#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) -#define MXC_CCM_CGR2_UART1_OFFSET 16 -#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) -#define MXC_CCM_CGR2_UART2_OFFSET 18 -#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) -#define MXC_CCM_CGR2_UART3_OFFSET 20 -#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) -#define MXC_CCM_CGR2_USBOTG_OFFSET 22 -#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) -#define MXC_CCM_CGR2_WDOG_OFFSET 24 -#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) -#define MXC_CCM_CGR2_MAX_OFFSET 26 -#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) -#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) -#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 -#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) - -#define MXC_CCM_CGR3_CSI_OFFSET 0 -#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) -#define MXC_CCM_CGR3_IIM_OFFSET 2 -#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) -#define MXC_CCM_CGR3_GPU2D_OFFSET 4 -#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) - -#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F -#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 -#define MXC_CCM_COSR_CLKOEN (1 << 5) -#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) -#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 -#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) -#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 -#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) -#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 -#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) -#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 -#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) -#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 -#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) -#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) -#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 - -#endif diff --git a/arch/arm/include/asm/arch-mx35/gpio.h b/arch/arm/include/asm/arch-mx35/gpio.h deleted file mode 100644 index b3d3639..0000000 --- a/arch/arm/include/asm/arch-mx35/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - */ - - -#ifndef __ASM_ARCH_MX35_GPIO_H -#define __ASM_ARCH_MX35_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h deleted file mode 100644 index 8ee0754..0000000 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ /dev/null @@ -1,386 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX35_H -#define __ASM_ARCH_MX35_H - -#define ARCH_MXC - -/* - * IRAM - */ -#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define IRAM_SIZE 0x00020000 /* 128 KB */ - -#define LOW_LEVEL_SRAM_STACK 0x1001E000 - -/* - * AIPS 1 - */ -#define AIPS1_BASE_ADDR 0x43F00000 -#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR -#define MAX_BASE_ADDR 0x43F04000 -#define EVTMON_BASE_ADDR 0x43F08000 -#define CLKCTL_BASE_ADDR 0x43F0C000 -#define I2C1_BASE_ADDR 0x43F80000 -#define I2C3_BASE_ADDR 0x43F84000 -#define ATA_BASE_ADDR 0x43F8C000 -#define UART1_BASE 0x43F90000 -#define UART2_BASE 0x43F94000 -#define I2C2_BASE_ADDR 0x43F98000 -#define CSPI1_BASE_ADDR 0x43FA4000 -#define IOMUXC_BASE_ADDR 0x43FAC000 - -/* - * SPBA - */ -#define SPBA_BASE_ADDR 0x50000000 -#define UART3_BASE 0x5000C000 -#define CSPI2_BASE_ADDR 0x50010000 -#define ATA_DMA_BASE_ADDR 0x50020000 -#define FEC_BASE_ADDR 0x50038000 -#define SPBA_CTRL_BASE_ADDR 0x5003C000 - -/* - * AIPS 2 - */ -#define AIPS2_BASE_ADDR 0x53F00000 -#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR -#define CCM_BASE_ADDR 0x53F80000 -#define GPT1_BASE_ADDR 0x53F90000 -#define EPIT1_BASE_ADDR 0x53F94000 -#define EPIT2_BASE_ADDR 0x53F98000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define MMC_SDHC1_BASE_ADDR 0x53FB4000 -#define MMC_SDHC2_BASE_ADDR 0x53FB8000 -#define MMC_SDHC3_BASE_ADDR 0x53FBC000 -#define IPU_CTRL_BASE_ADDR 0x53FC0000 -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define SDMA_BASE_ADDR 0x53FD4000 -#define RTC_BASE_ADDR 0x53FD8000 -#define WDOG1_BASE_ADDR 0x53FDC000 -#define PWM_BASE_ADDR 0x53FE0000 -#define RTIC_BASE_ADDR 0x53FEC000 -#define IIM_BASE_ADDR 0x53FF0000 -#define IMX_USB_BASE 0x53FF4000 -#define IMX_USB_PORT_OFFSET 0x400 - -#define IMX_CCM_BASE CCM_BASE_ADDR - -/* - * ROMPATCH and AVIC - */ -#define ROMPATCH_BASE_ADDR 0x60000000 -#define AVIC_BASE_ADDR 0x68000000 - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define EXT_MEM_CTRL_BASE 0xB8000000 -#define ESDCTL_BASE_ADDR 0xB8001000 -#define WEIM_BASE_ADDR 0xB8002000 -#define WEIM_CTRL_CS0 WEIM_BASE_ADDR -#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) -#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) -#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) -#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) -#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) -#define M3IF_BASE_ADDR 0xB8003000 -#define EMI_BASE_ADDR 0xB8004000 - -#define NFC_BASE_ADDR 0xBB000000 - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE_ADDR 0x70000000 -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 -#define CS0_BASE_ADDR 0xA0000000 -#define CS1_BASE_ADDR 0xA8000000 -#define CS2_BASE_ADDR 0xB0000000 -#define CS3_BASE_ADDR 0xB2000000 -#define CS4_BASE_ADDR 0xB4000000 -#define CS5_BASE_ADDR 0xB6000000 - -/* - * IRQ Controller Register Definitions. - */ -#define AVIC_NIMASK 0x04 -#define AVIC_INTTYPEH 0x18 -#define AVIC_INTTYPEL 0x1C - -/* L210 */ -#define L2CC_BASE_ADDR 0x30000000 -#define L2_CACHE_LINE_SIZE 32 -#define L2_CACHE_CTL_REG 0x100 -#define L2_CACHE_AUX_CTL_REG 0x104 -#define L2_CACHE_SYNC_REG 0x730 -#define L2_CACHE_INV_LINE_REG 0x770 -#define L2_CACHE_INV_WAY_REG 0x77C -#define L2_CACHE_CLEAN_LINE_REG 0x7B0 -#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 -#define L2_CACHE_DBG_CTL_REG 0xF40 - -#define CLKMODE_AUTO 0 -#define CLKMODE_CONSUMER 1 - -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define _PLL_BRM(x) ((x) << 31) -#define _PLL_PD(x) (((x) - 1) << 26) -#define _PLL_MFD(x) (((x) - 1) << 16) -#define _PLL_MFI(x) ((x) << 10) -#define _PLL_MFN(x) (x) -#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ - (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ - _PLL_MFN(mfn)) - -#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) -#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) -#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) - -#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) -#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) -#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) - -#define IIM_SREV 0x24 -#define ROMPATCH_REV 0x40 - -#define IPU_CONF IPU_CTRL_BASE_ADDR - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_CSI_EN (1<<0) - -/* - * CSPI register definitions - */ -#define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 - -#define MXC_SPI_BASE_ADDRESSES \ - 0x43fa4000, \ - 0x50010000, - -#define GPIO_PORT_NUM 3 -#define GPIO_NUM_PIN 32 - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_2_0 0x20 - -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 ccmr; /* Control */ - u32 pdr0; /* Post divider 0 */ - u32 pdr1; /* Post divider 1 */ - u32 pdr2; /* Post divider 2 */ - u32 pdr3; /* Post divider 3 */ - u32 pdr4; /* Post divider 4 */ - u32 rcsr; /* CCM Status */ - u32 mpctl; /* Core PLL Control */ - u32 ppctl; /* Peripheral PLL Control */ - u32 acmr; /* Audio clock mux */ - u32 cosr; /* Clock out source */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 cgr3; /* Clock Gating Control 3 */ - u32 reserved; - u32 dcvr0; /* DPTC Comparator 0 */ - u32 dcvr1; /* DPTC Comparator 0 */ - u32 dcvr2; /* DPTC Comparator 0 */ - u32 dcvr3; /* DPTC Comparator 0 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res1[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_31[0x10]; -}; - -struct fuse_bank1_regs { - u32 fuse0_21[0x16]; - u32 usr; - u32 fuse23_31[9]; -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -/* CSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 intr; - u32 dma; - u32 stat; - u32 period; - u32 test; -}; - -struct esdc_regs { - u32 esdctl0; - u32 esdcfg0; - u32 esdctl1; - u32 esdcfg1; - u32 esdmisc; - u32 reserved[4]; - u32 esdcdly[5]; - u32 esdcdlyl; -}; - -#define ESDC_MISC_RST (1 << 1) -#define ESDC_MISC_MDDR_EN (1 << 2) -#define ESDC_MISC_MDDR_DL_RST (1 << 3) -#define ESDC_MISC_DDR_EN (1 << 8) -#define ESDC_MISC_DDR2_EN (1 << 9) - -/* Multi-Layer AHB Crossbar Switch (MAX) registers */ -struct max_regs { - u32 mpr0; - u32 pad00[3]; - u32 sgpcr0; - u32 pad01[59]; - u32 mpr1; - u32 pad02[3]; - u32 sgpcr1; - u32 pad03[59]; - u32 mpr2; - u32 pad04[3]; - u32 sgpcr2; - u32 pad05[59]; - u32 mpr3; - u32 pad06[3]; - u32 sgpcr3; - u32 pad07[59]; - u32 mpr4; - u32 pad08[3]; - u32 sgpcr4; - u32 pad09[251]; - u32 mgpcr0; - u32 pad10[63]; - u32 mgpcr1; - u32 pad11[63]; - u32 mgpcr2; - u32 pad12[63]; - u32 mgpcr3; - u32 pad13[63]; - u32 mgpcr4; - u32 pad14[63]; - u32 mgpcr5; -}; - -/* AHB <-> IP-Bus Interface (AIPS) */ -struct aips_regs { - u32 mpr_0_7; - u32 mpr_8_15; - u32 pad0[6]; - u32 pacr_0_7; - u32 pacr_8_15; - u32 pacr_16_23; - u32 pacr_24_31; - u32 pad1[4]; - u32 opacr_0_7; - u32 opacr_8_15; - u32 opacr_16_23; - u32 opacr_24_31; - u32 opacr_32_39; -}; - -/* - * NFMS bit in RCSR register for pagesize of nandflash - */ -#define NFMS_BIT 8 -#define NFMS_NF_DWIDTH 14 -#define NFMS_NF_PG_SZ 8 - -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) - -#endif - -/* - * Generic timer support - */ -#ifdef CONFIG_MX35_CLK32 -#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32 -#else -#define CONFIG_SYS_TIMER_RATE 32768 -#endif - -#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36) - -#endif /* __ASM_ARCH_MX35_H */ diff --git a/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/arch/arm/include/asm/arch-mx35/iomux-mx35.h deleted file mode 100644 index f519c69..0000000 --- a/arch/arm/include/asm/arch-mx35/iomux-mx35.h +++ /dev/null @@ -1,1259 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on mainline Linux i.MX iomux-mx35.h file: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - */ - -#ifndef __IOMUX_MX35_H__ -#define __IOMUX_MX35_H__ - -#include <asm/mach-imx/iomux-v3.h> - -/* - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL), - - MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL), - MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL), - MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL), - - MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL), - - MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL), - MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL), - - MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL), - MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL), - MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL), - - MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL), - - MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL), - - MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL), - MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL), - MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL), - MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL), - MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL), - MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL), - MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL), - MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL), - MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL), - MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL), - MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL), - MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL), - - MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL), - MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL), - MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL), - - MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL), - - MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL), - - MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL), - - MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL), - - MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL), - MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL), - MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL), - MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL), - - MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL), - MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL), - MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL), - MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL), - MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL), - - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL), - MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL), - MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL), - MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL), - - MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL), - MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL), - MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL), - - MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL), - - MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL), - MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL), - - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL), - MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL), - - MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL), - MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL), - MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL), - MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL), - MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL), - MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL), - MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL), - MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL), - MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL), - MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL), - MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL), - MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL), - MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL), - MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL), - MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL), - MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL), - MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL), - MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL), - MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL), - MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL), - MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL), - MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL), - MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL), - MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL), - MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL), - MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL), - MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL), - MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL), - MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL), - MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL), - MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL), - MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL), - MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL), - MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL), - MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL), - MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL), - MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL), - - MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL), - - MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL), - - MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL), - MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL), - - MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX35_H__ */ diff --git a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S deleted file mode 100644 index 4b1c9f8..0000000 --- a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include <asm/macro.h> - -/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - * - * Default argument values: - * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to - * user-mode. - * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for - * SDMA to access them. - */ -.macro init_aips mpr=0x77777777, opacr=0x00000000 - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =\mpr - str r1, [r0, #AIPS_MPR_0_7] - str r1, [r0, #AIPS_MPR_8_15] - ldr r2, =AIPS2_BASE_ADDR - str r1, [r2, #AIPS_MPR_0_7] - str r1, [r2, #AIPS_MPR_8_15] - - /* Did not change the AIPS control registers access type. */ - ldr r1, =\opacr - str r1, [r0, #AIPS_OPACR_0_7] - str r1, [r0, #AIPS_OPACR_8_15] - str r1, [r0, #AIPS_OPACR_16_23] - str r1, [r0, #AIPS_OPACR_24_31] - str r1, [r0, #AIPS_OPACR_32_39] - str r1, [r2, #AIPS_OPACR_0_7] - str r1, [r2, #AIPS_OPACR_8_15] - str r1, [r2, #AIPS_OPACR_16_23] - str r1, [r2, #AIPS_OPACR_24_31] - str r1, [r2, #AIPS_OPACR_32_39] -.endm - -/* - * MAX (Multi-Layer AHB Crossbar Switch) setup - * - * Default argument values: - * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 - * - SGPCR: always park on last master - * - MGPCR: restore default values - */ -.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 - ldr r0, =MAX_BASE_ADDR - ldr r1, =\mpr - str r1, [r0, #MAX_MPR0] /* for S0 */ - str r1, [r0, #MAX_MPR1] /* for S1 */ - str r1, [r0, #MAX_MPR2] /* for S2 */ - str r1, [r0, #MAX_MPR3] /* for S3 */ - str r1, [r0, #MAX_MPR4] /* for S4 */ - ldr r1, =\sgpcr - str r1, [r0, #MAX_SGPCR0] /* for S0 */ - str r1, [r0, #MAX_SGPCR1] /* for S1 */ - str r1, [r0, #MAX_SGPCR2] /* for S2 */ - str r1, [r0, #MAX_SGPCR3] /* for S3 */ - str r1, [r0, #MAX_SGPCR4] /* for S4 */ - ldr r1, =\mgpcr - str r1, [r0, #MAX_MGPCR0] /* for M0 */ - str r1, [r0, #MAX_MGPCR1] /* for M1 */ - str r1, [r0, #MAX_MGPCR2] /* for M2 */ - str r1, [r0, #MAX_MGPCR3] /* for M3 */ - str r1, [r0, #MAX_MGPCR4] /* for M4 */ - str r1, [r0, #MAX_MGPCR5] /* for M5 */ -.endm - -/* - * M3IF setup - * - * Default argument values: - * - CTL: - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 - * ------------ - * 0x00000040 - */ -.macro init_m3if ctl=0x00000040 - /* M3IF Control Register (M3IFCTL) */ - write32 M3IF_BASE_ADDR, \ctl -.endm - -.macro core_init - mrc p15, 0, r1, c1, c0, 0 - - /* Set branch prediction enable */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #7 - mcr p15, 0, r0, c1, c0, 1 - orr r1, r1, #1 << 11 - - /* Set unaligned access enable */ - orr r1, r1, #1 << 22 - - /* Set low int latency enable */ - orr r1, r1, #1 << 21 - - mcr p15, 0, r1, c1, c0, 0 - - mov r0, #0 - - mcr p15, 0, r0, c15, c2, 4 - - mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ - mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ - mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ - - /* Setup the Peripheral Port Memory Remap Register */ - ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ - mcr p15, 0, r0, c15, c2, 4 -.endm diff --git a/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/arch/arm/include/asm/arch-mx35/mmc_host_def.h deleted file mode 100644 index 81c19bb..0000000 --- a/arch/arm/include/asm/arch-mx35/mmc_host_def.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 - -#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h deleted file mode 100644 index 6e8b841..0000000 --- a/arch/arm/include/asm/arch-mx35/sys_proto.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ - -#ifndef _MX35_SYS_PROTO_H_ -#define _MX35_SYS_PROTO_H_ - -#include <asm/mach-imx/sys_proto.h> - -void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row, - u32 col, u32 dsize, u32 refresh); - -#endif diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h deleted file mode 100644 index 6f5ca58..0000000 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_SYS_MX5_HCLK -#define MXC_HCLK CONFIG_SYS_MX5_HCLK -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_SYS_MX5_CLK32 -#define MXC_CLK32 CONFIG_SYS_MX5_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_ESDHC4_CLK, - MXC_FEC_CLK, - MXC_SATA_CLK, - MXC_DDR_CLK, - MXC_NFC_CLK, - MXC_PERIPH_CLK, - MXC_I2C_CLK, - MXC_LDB_CLK, -}; - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); -int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); -void set_usb_phy_clk(void); -void enable_usb_phy1_clk(bool enable); -void enable_usb_phy2_clk(bool enable); -void set_usboh3_clk(void); -void enable_usboh3_clk(bool enable); -void mxc_set_sata_internal_clock(void); -int enable_i2c_clk(unsigned char enable, unsigned i2c_num); -void enable_nfc_clk(unsigned char enable); -void enable_efuse_prog_supply(bool enable); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h deleted file mode 100644 index 9d54ab7..0000000 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ /dev/null @@ -1,616 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ - -#define MXC_CCM_BASE CCM_BASE_ADDR - -/* DPLL register mapping structure */ -struct mxc_pll_reg { - u32 ctrl; - u32 config; - u32 op; - u32 mfd; - u32 mfn; - u32 mfn_minus; - u32 mfn_plus; - u32 hfs_op; - u32 hfs_mfd; - u32 hfs_mfn; - u32 mfn_togc; - u32 destat; -}; - -/* Register maping of CCM*/ -struct mxc_ccm_reg { - u32 ccr; /* 0x0000 */ - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; /* 0x0010*/ - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; /* 0x0020 */ - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; /* 0x0030 */ - u32 chsccdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; /* 0x0040 */ - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; /* 0x0050 */ - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; /* 0x0060 */ - u32 cgpr; - u32 CCGR0; - u32 CCGR1; - u32 CCGR2; /* 0x0070 */ - u32 CCGR3; - u32 CCGR4; - u32 CCGR5; - u32 CCGR6; /* 0x0080 */ -#ifdef CONFIG_MX53 - u32 CCGR7; /* 0x0084 */ -#endif - u32 cmeor; -}; - -/* Define the bits in register CCR */ -#define MXC_CCM_CCR_COSC_EN (0x1 << 12) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCR_FPM_MULT (0x1 << 11) -#endif -#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) -#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCR_FPM_EN (0x1 << 8) -#endif -#define MXC_CCM_CCR_OSCNT_OFFSET 0 -#define MXC_CCM_CCR_OSCNT_MASK 0xFF -#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) -#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) - -/* Define the bits in register CCSR */ -#if defined(CONFIG_MX51) -#define MXC_CCM_CCSR_LP_APM (0x1 << 9) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCSR_LP_APM (0x1 << 10) -#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) -#endif -#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7 -#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) -#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) -#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3) -#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5 -#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5) -#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) -#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3) -#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3 -#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3) -#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) -#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2) -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 -#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) -#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) -#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) -#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) -#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) -#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 -#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) -#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) -#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) -#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) -#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) -#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) -#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) -#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 -#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) -#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) -#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) -#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) -#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) -#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 -#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) -#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 -#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) -#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) -#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 -#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 -#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) -#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 -#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) -#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) -#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) -#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 - -/* Define the bits in register CSCMR2 */ -#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26 -#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26) -#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26) -#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7) - -#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5 - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 -#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 -#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) -#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 -#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 -#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) - -/* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) - -/* Define the bits in register CGPR */ -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) - -/* Define the bits in register CCGRx */ -#define MXC_CCM_CCGR_CG_MASK 0x3 -#define MXC_CCM_CCGR_CG_OFF 0x0 -#define MXC_CCM_CCGR_CG_RUN_ON 0x1 -#define MXC_CCM_CCGR_CG_ON 0x3 - -#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 -#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 -#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 -#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR0_TZIC_OFFSET 6 -#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR0_DAP_OFFSET 8 -#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR0_TPIU_OFFSET 10 -#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR0_CTI2_OFFSET 12 -#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR0_CTI3_OFFSET 14 -#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 -#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 -#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR0_ROMCP_OFFSET 20 -#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR0_ROM_OFFSET 22 -#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 -#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 -#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 -#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR0_IIM_OFFSET 30 -#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR1_TMAX1_OFFSET 0 -#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR1_TMAX2_OFFSET 2 -#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR1_TMAX3_OFFSET 4 -#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 -#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 -#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 -#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 -#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 -#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 -#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR1_I2C1_OFFSET 18 -#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR1_I2C2_OFFSET 20 -#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 -#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 -#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR1_I2C3_OFFSET 22 -#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) -#endif -#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 -#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 -#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR1_SCC_OFFSET 30 -#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) - -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 -#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) -#endif -#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 -#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 -#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 -#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 -#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 -#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 -#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 -#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 -#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 -#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 -#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR2_OWIRE_OFFSET 22 -#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR2_FEC_OFFSET 24 -#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 -#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 -#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR2_TVE_OFFSET 30 -#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 -#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 -#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 -#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 -#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 -#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 -#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 -#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 -#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 -#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 -#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 -#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 -#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 -#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 -#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 -#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 -#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR4_PATA_OFFSET 0 -#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 -#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 -#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR4_SATA_OFFSET 2 -#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 -#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 -#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 -#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 -#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) -#endif -#define MXC_CCM_CCGR4_SAHARA_OFFSET 14 -#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR4_RTIC_OFFSET 16 -#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 -#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 -#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 -#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 -#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 -#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR4_SRTC_OFFSET 28 -#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR4_SDMA_OFFSET 30 -#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR5_SPBA_OFFSET 0 -#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR5_GPU_OFFSET 2 -#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR5_GARB_OFFSET 4 -#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR5_VPU_OFFSET 6 -#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 -#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR5_IPU_OFFSET 10 -#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 -#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 -#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) -#endif -#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 -#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 -#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 -#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 -#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 -#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 -#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 -#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 -#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) -#endif -#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 -#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) - -#if defined(CONFIG_MX53) -#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 -#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR6_OCRAM_OFFSET 2 -#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) -#endif -#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 -#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 -#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 -#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 -#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) -#endif -#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 -#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 -#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR6_GPU2D_OFFSET 14 -#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) -#if defined(CONFIG_MX53) -#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 -#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 -#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 -#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 -#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 -#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 -#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 -#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 -#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 -#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 -#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR7_MLB_OFFSET 4 -#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 -#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 -#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 -#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 -#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 -#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) -#endif - -/* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) - -#define MXC_DPLLC_CTL_HFSM (1 << 7) -#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) - -#define MXC_DPLLC_OP_PDF_MASK 0xf -#define MXC_DPLLC_OP_MFI_OFFSET 4 -#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) -#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) -#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) - -#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff - -#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff - -#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/gpio.h b/arch/arm/include/asm/arch-mx5/gpio.h deleted file mode 100644 index dad40bd..0000000 --- a/arch/arm/include/asm/arch-mx5/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - */ - - -#ifndef __ASM_ARCH_MX5_GPIO_H -#define __ASM_ARCH_MX5_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h deleted file mode 100644 index fbb6e59..0000000 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ /dev/null @@ -1,562 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX5_IMX_REGS_H__ -#define __ASM_ARCH_MX5_IMX_REGS_H__ - -#define ARCH_MXC - -#if defined(CONFIG_MX51) -#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define IPU_SOC_BASE_ADDR 0x40000000 -#define IPU_SOC_OFFSET 0x1E000000 -#define SPBA0_BASE_ADDR 0x70000000 -#define AIPS1_BASE_ADDR 0x73F00000 -#define AIPS2_BASE_ADDR 0x83F00000 -#define CSD0_BASE_ADDR 0x90000000 -#define CSD1_BASE_ADDR 0xA0000000 -#define NFC_BASE_ADDR_AXI 0xCFFF0000 -#define CS1_BASE_ADDR 0xB8000000 -#elif defined(CONFIG_MX53) -#define IPU_SOC_BASE_ADDR 0x18000000 -#define IPU_SOC_OFFSET 0x06000000 -#define SPBA0_BASE_ADDR 0x50000000 -#define AIPS1_BASE_ADDR 0x53F00000 -#define AIPS2_BASE_ADDR 0x63F00000 -#define CSD0_BASE_ADDR 0x70000000 -#define CSD1_BASE_ADDR 0xB0000000 -#define NFC_BASE_ADDR_AXI 0xF7FF0000 -#define IRAM_BASE_ADDR 0xF8000000 -#define CS1_BASE_ADDR 0xF4000000 -#define SATA_BASE_ADDR 0x10000000 -#else -#error "CPU_TYPE not defined" -#endif - -#define IRAM_SIZE 0x00020000 /* 128 KB */ - -/* - * SPBA global module enabled #0 - */ -#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) -#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) -#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) -#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) -#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) -#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) -#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) -#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) -#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) -#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) -#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) -#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) -#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) -#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) -#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) -#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) -#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) -#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) -#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) -#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) -#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) -#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) -#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) -#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) -#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) -#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) -#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) -#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) - -#if defined(CONFIG_MX53) -#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) -#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) -#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) -#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) -#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) -#endif -/* - * AIPS 2 - */ -#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) -#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) -#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) -#ifdef CONFIG_MX53 -#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) -#endif -#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) -#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) -#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) -#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) -#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) -#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) -#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) -#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) -#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) -#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) -#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) -#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) -#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) -#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) -#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) -#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) -#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) -#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) -#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) -#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) -#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) -#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) -#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) -#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) -#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) -#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) -#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) -#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) -#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) - -#if defined(CONFIG_MX53) -#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) -#endif - -/* - * WEIM CSnGCR1 - */ -#define CSEN 1 -#define SWR (1 << 1) -#define SRD (1 << 2) -#define MUM (1 << 3) -#define WFL (1 << 4) -#define RFL (1 << 5) -#define CRE (1 << 6) -#define CREP (1 << 7) -#define BL(x) (((x) & 0x7) << 8) -#define WC (1 << 11) -#define BCD(x) (((x) & 0x3) << 12) -#define BCS(x) (((x) & 0x3) << 14) -#define DSZ(x) (((x) & 0x7) << 16) -#define SP (1 << 19) -#define CSREC(x) (((x) & 0x7) << 20) -#define AUS (1 << 23) -#define GBC(x) (((x) & 0x7) << 24) -#define WP (1 << 27) -#define PSZ(x) (((x) & 0x0f << 28) - -/* - * WEIM CSnGCR2 - */ -#define ADH(x) (((x) & 0x3)) -#define DAPS(x) (((x) & 0x0f << 4) -#define DAE (1 << 8) -#define DAP (1 << 9) -#define MUX16_BYP (1 << 12) - -/* - * WEIM CSnRCR1 - */ -#define RCSN(x) (((x) & 0x7)) -#define RCSA(x) (((x) & 0x7) << 4) -#define OEN(x) (((x) & 0x7) << 8) -#define OEA(x) (((x) & 0x7) << 12) -#define RADVN(x) (((x) & 0x7) << 16) -#define RAL (1 << 19) -#define RADVA(x) (((x) & 0x7) << 20) -#define RWSC(x) (((x) & 0x3f) << 24) - -/* - * WEIM CSnRCR2 - */ -#define RBEN(x) (((x) & 0x7)) -#define RBE (1 << 3) -#define RBEA(x) (((x) & 0x7) << 4) -#define RL(x) (((x) & 0x3) << 8) -#define PAT(x) (((x) & 0x7) << 12) -#define APR (1 << 15) - -/* - * WEIM CSnWCR1 - */ -#define WCSN(x) (((x) & 0x7)) -#define WCSA(x) (((x) & 0x7) << 3) -#define WEN(x) (((x) & 0x7) << 6) -#define WEA(x) (((x) & 0x7) << 9) -#define WBEN(x) (((x) & 0x7) << 12) -#define WBEA(x) (((x) & 0x7) << 15) -#define WADVN(x) (((x) & 0x7) << 18) -#define WADVA(x) (((x) & 0x7) << 21) -#define WWSC(x) (((x) & 0x3f) << 24) -#define WBED1 (1 << 30) -#define WAL (1 << 31) - -/* - * WEIM CSnWCR2 - */ -#define WBED 1 - -/* - * CSPI register definitions - */ -#define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_MODE_MASK (0xf << 4) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_PHA 0 /* SCLK phase control */ -#define MXC_CSPICON_POL 4 /* SCLK polarity */ -#define MXC_CSPICON_SSPOL 12 /* SS polarity */ -#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#define MXC_SPI_BASE_ADDRESSES \ - CSPI1_BASE_ADDR, \ - CSPI2_BASE_ADDR, \ - CSPI3_BASE_ADDR, - -/* - * Number of GPIO pins per port - */ -#define GPIO_NUM_PIN 32 - -#define IIM_SREV 0x24 -#define ROM_SI_REV 0x48 - -#define NFC_BUF_SIZE 0x1000 - -/* M4IF */ -#define M4IF_FBPM0 0x40 -#define M4IF_FIDBP 0x48 -#define M4IF_GENP_WEIM_MM_MASK 0x00000001 -#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 - -/* Assuming 24MHz input clock with doubler ON */ -/* MFI PDF */ -#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_864 (180 - 1) /* PL Dither mode */ -#define DP_MFN_864 180 -#define DP_MFN_800_DIT 60 /* PL Dither mode */ - -#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_850 (48 - 1) -#define DP_MFN_850 41 - -#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_800 (3 - 1) -#define DP_MFN_800 1 - -#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) -#define DP_MFD_700 (24 - 1) -#define DP_MFN_700 7 - -#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) -#define DP_MFD_665 (96 - 1) -#define DP_MFN_665 89 - -#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) -#define DP_MFD_532 (24 - 1) -#define DP_MFN_532 13 - -#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) -#define DP_MFD_400 (3 - 1) -#define DP_MFN_400 1 - -#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) -#define DP_MFD_455 (48 - 1) -#define DP_MFN_455 23 - -#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) -#define DP_MFD_216 (4 - 1) -#define DP_MFN_216 3 - -#define IMX_IIM_BASE (IIM_BASE_ADDR) - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -struct clkctl { - u32 ccr; - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; - u32 chsccdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; - u32 cgpr; - u32 ccgr0; - u32 ccgr1; - u32 ccgr2; - u32 ccgr3; - u32 ccgr4; - u32 ccgr5; - u32 ccgr6; -#if defined(CONFIG_MX53) - u32 ccgr7; -#endif - u32 cmeor; -}; - -/* DPLL registers */ -struct dpll { - u32 dp_ctl; - u32 dp_config; - u32 dp_op; - u32 dp_mfd; - u32 dp_mfn; - u32 dp_mfn_minus; - u32 dp_mfn_plus; - u32 dp_hfs_op; - u32 dp_hfs_mfd; - u32 dp_hfs_mfn; - u32 dp_mfn_togc; - u32 dp_destat; -}; -/* WEIM registers */ -struct weim { - u32 cs0gcr1; - u32 cs0gcr2; - u32 cs0rcr1; - u32 cs0rcr2; - u32 cs0wcr1; - u32 cs0wcr2; - u32 cs1gcr1; - u32 cs1gcr2; - u32 cs1rcr1; - u32 cs1rcr2; - u32 cs1wcr1; - u32 cs1wcr2; - u32 cs2gcr1; - u32 cs2gcr2; - u32 cs2rcr1; - u32 cs2rcr2; - u32 cs2wcr1; - u32 cs2wcr2; - u32 cs3gcr1; - u32 cs3gcr2; - u32 cs3rcr1; - u32 cs3rcr2; - u32 cs3wcr1; - u32 cs3wcr2; - u32 cs4gcr1; - u32 cs4gcr2; - u32 cs4rcr1; - u32 cs4rcr2; - u32 cs4wcr1; - u32 cs4wcr2; - u32 cs5gcr1; - u32 cs5gcr2; - u32 cs5rcr1; - u32 cs5rcr2; - u32 cs5wcr1; - u32 cs5wcr2; - u32 wcr; - u32 wiar; - u32 ear; -}; - -#if defined(CONFIG_MX51) -struct iomuxc { - u32 gpr[2]; - u32 omux0; - u32 omux1; - u32 omux2; - u32 omux3; - u32 omux4; -}; -#elif defined(CONFIG_MX53) -struct iomuxc { - u32 gpr[3]; - u32 omux0; - u32 omux1; - u32 omux2; - u32 omux3; - u32 omux4; -}; -#endif - -#define IOMUXC_GPR2_BITMAP_SPWG 0 -#define IOMUXC_GPR2_BITMAP_JEIDA 1 - -#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 -#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \ - IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \ - IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) - -#define IOMUXC_GPR2_DATA_WIDTH_18 0 -#define IOMUXC_GPR2_DATA_WIDTH_24 1 - -#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 -#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \ - IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \ - IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) - -#define IOMUXC_GPR2_MODE_DISABLED 0 -#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 -#define IOMUXC_GPR2_MODE_ENABLED_DI1 3 - -#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 -#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \ - IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \ - IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \ - IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr; - u32 srsr; - u32 reserved1[2]; - u32 sisr; - u32 simr; -}; - -struct srtc_regs { - u32 lpscmr; /* 0x00 */ - u32 lpsclr; /* 0x04 */ - u32 lpsar; /* 0x08 */ - u32 lpsmcr; /* 0x0c */ - u32 lpcr; /* 0x10 */ - u32 lpsr; /* 0x14 */ - u32 lppdr; /* 0x18 */ - u32 lpgr; /* 0x1c */ - u32 hpcmr; /* 0x20 */ - u32 hpclr; /* 0x24 */ - u32 hpamr; /* 0x28 */ - u32 hpalr; /* 0x2c */ - u32 hpcr; /* 0x30 */ - u32 hpisr; /* 0x34 */ - u32 hpienr; /* 0x38 */ -}; - -/* CSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 cfg; - u32 intr; - u32 dma; - u32 stat; - u32 period; -}; - -struct iim_regs { - u32 stat; - u32 statm; - u32 err; - u32 emask; - u32 fctl; - u32 ua; - u32 la; - u32 sdat; - u32 prev; - u32 srev; - u32 prg_p; - u32 scs0; - u32 scs1; - u32 scs2; - u32 scs3; - u32 res0[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; -#if defined(CONFIG_MX51) - } bank[4]; -#elif defined(CONFIG_MX53) - } bank[5]; -#endif -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_23[8]; -#if defined(CONFIG_MX51) - u32 imei[8]; -#elif defined(CONFIG_MX53) - u32 gp[8]; -#endif -}; - -struct fuse_bank1_regs { - u32 fuse0_8[9]; - u32 mac_addr[6]; - u32 fuse15_31[0x11]; -}; - -#if defined(CONFIG_MX53) -struct fuse_bank4_regs { - u32 fuse0_4[5]; - u32 gp[3]; - u32 fuse8_31[0x18]; -}; -#endif - -#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) -#define PWMCR_DOZEEN (1 << 24) -#define PWMCR_WAITEN (1 << 23) -#define PWMCR_DBGEN (1 << 22) -#define PWMCR_CLKSRC_IPG_HIGH (2 << 16) -#define PWMCR_CLKSRC_IPG (1 << 16) -#define PWMCR_EN (1 << 0) - -struct pwm_regs { - u32 cr; - u32 sr; - u32 ir; - u32 sar; - u32 pr; - u32 cnr; -}; - -#endif /* __ASSEMBLER__*/ - -#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h deleted file mode 100644 index 7f8a238..0000000 --- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h +++ /dev/null @@ -1,241 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * Copyright (C) 2009-2012 Genesi USA, Inc. - */ - -/* - * The vast majority of this file is taken from the Linux kernel at - * commit 5d23b39 - */ - -#ifndef __IOMUX_MX51_H__ -#define __IOMUX_MX51_H__ - -#include <asm/mach-imx/iomux-v3.h> - -/* Pad control groupings */ -#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ - PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_USBH_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) -#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SRE_FAST | PAD_CTL_DVS) -#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) - -#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) - -/* - * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL), - MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS), - MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL), - MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL), - MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL), - MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2), - MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2), - MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0 = IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1 = IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDCLK__DRAM_SDCLK = IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS0__DRAM_SDQS0 = IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS1__DRAM_SDQS1 = IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS2__DRAM_SDQS2 = IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS3__DRAM_SDQS3 = IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_CS0__DRAM_CS0 = IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_CS1__DRAM_CS1 = IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM0__DRAM_DQM0 = IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2), - MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2), - MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS5__FEC_TDATA2 = IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS6__FEC_TDATA3 = IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4), - MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D9__FEC_RDATA0 = IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4), - MX51_PAD_NANDF_D9__GPIO3_31 = IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_SS1__ECSPI1_SS1 = IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_RDY__ECSPI1_RDY = IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_RDY__GPIO4_26 = IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_D0_CS__GPIO3_3 = IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74C, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DISP2_DAT6__FEC_TDAT1 = IOMUX_PAD(0x774, 0x36C, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_DISP2_DAT7__FEC_TDAT2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_DISP2_DAT8__FEC_TDAT3 = IOMUX_PAD(0x77C, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37C, 2, 0x94c, 0x1, MX51_PAD_CTRL_2), - MX51_PAD_DISP2_DAT11__FEC_RXCLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 0x1, MX51_PAD_CTRL_2), - MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78C, 0x384, 2, 0x96c, 0x1, MX51_PAD_CTRL_4), - MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 0x1, MX51_PAD_CTRL_4), - MX51_PAD_DISP2_DAT14__FEC_RDAT0 = IOMUX_PAD(0x794, 0x38C, 2, 0x958, 0x1, MX51_PAD_CTRL_4), - MX51_PAD_DISP2_DAT15__FEC_TDAT0 = IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_PAD_CTRL_5), - MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), - MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), - MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDRAPUS = IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B1 = IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDRPUS = IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B2 = IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_PKEADDR = IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B4 = IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX51_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/arch/arm/include/asm/arch-mx5/iomux-mx53.h deleted file mode 100644 index cbc08b0..0000000 --- a/arch/arm/include/asm/arch-mx5/iomux-mx53.h +++ /dev/null @@ -1,1215 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on Freescale's Linux i.MX iomux-mx53.h file: - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __IOMUX_MX53_H__ -#define __IOMUX_MX53_H__ - -#include <asm/mach-imx/iomux-v3.h> - -/* Pad control groupings */ -#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) - -/* - * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode> - * If <padname> refers to a GPIO, it is named GPIO_<unit> - * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX53_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__GPIO4_5 = IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 = IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__FEC_TDATA_3 = IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__GPIO4_6 = IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__UART4_TXD_MUX = IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__FEC_RDATA_3 = IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__GPIO4_7 = IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__UART4_RXD_MUX = IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__FEC_TX_ER = IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__GPIO4_8 = IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__UART5_TXD_MUX = IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__FEC_RX_CLK = IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__USBPHY1_TXREADY = IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__GPIO4_9 = IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__UART5_RXD_MUX = IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__FEC_COL = IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__USBPHY1_RXVALID = IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__GPIO4_10 = IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__FEC_MDIO = IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__FEC_RDATA_2 = IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE = IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__GPIO4_11 = IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__FEC_MDC = IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__FEC_TDATA_2 = IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__USBPHY1_RXERROR = IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__GPIO4_12 = IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__USBOH3_H2_DP = IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__FEC_CRS = IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK = IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__GPIO4_13 = IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__USBOH3_H2_DM = IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__CCM_PLL4_BYP = IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 = IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__GPIO4_14 = IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__IPU_SISG_4 = IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 = IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__GPIO4_15 = IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__IPU_SISG_5 = IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID = IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK = IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__GPIO4_16 = IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR = IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 = IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID = IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 = IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__GPIO4_17 = IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 = IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__USBPHY1_BVALID = IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 = IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__GPIO4_18 = IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 = IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION = IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 = IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__GPIO4_19 = IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 = IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__USBPHY1_IDDIG = IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 = IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__GPIO4_20 = IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__ESDHC1_WP = IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 = IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT = IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 = IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__GPIO4_21 = IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__CSPI_SCLK = IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 = IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 = IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY = IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 = IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__GPIO4_22 = IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__CSPI_MOSI = IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 = IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL - = IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 = IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID = IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 = IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__GPIO4_23 = IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__CSPI_MISO = IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 = IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 = IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE = IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 = IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__GPIO4_24 = IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__CSPI_SS0 = IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 = IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 = IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR = IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 = IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__GPIO4_25 = IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__CSPI_SS1 = IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 = IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 = IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK = IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 = IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__GPIO4_26 = IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__CSPI_SS2 = IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 = IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 = IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 = IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 = IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__GPIO4_27 = IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__CSPI_SS3 = IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 = IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 = IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 = IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 = IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__GPIO4_28 = IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__CSPI_RDY = IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 = IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 = IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID = IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 = IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__GPIO4_29 = IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 = IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__USBPHY2_AVALID = IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 = IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__GPIO4_30 = IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 = IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 = IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 = IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__GPIO4_31 = IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP = IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 - = IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 = IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 = IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 = IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__GPIO5_5 = IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT = IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 - = IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 = IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 = IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 = IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__GPIO5_6 = IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK = IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 - = IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 = IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 = IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 = IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__GPIO5_7 = IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 - = IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 = IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 = IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 = IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__GPIO5_8 = IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 - = IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 = IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 = IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 = IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__GPIO5_9 = IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 - = IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 = IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 = IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 = IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__GPIO5_10 = IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 - = IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 = IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 = IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 = IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__GPIO5_11 = IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 - = IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 = IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 = IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__GPIO5_12 = IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 - = IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 = IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 = IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 = IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__GPIO5_13 = IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 - = IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 = IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 = IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 = IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__GPIO5_14 = IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 - = IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 = IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__SATA_PHY_TDI = IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 = IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__GPIO5_15 = IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 = IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__SATA_PHY_TDO = IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 = IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__GPIO5_16 = IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 = IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__SATA_PHY_TCK = IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 = IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__GPIO5_17 = IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 = IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__SATA_PHY_TMS = IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK = IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__GPIO5_18 = IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 = IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC = IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__GPIO5_19 = IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK = IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 = IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__TPIU_TRCTL = IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN = IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__GPIO5_20 = IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 = IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK = IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC = IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__GPIO5_21 = IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 = IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 = IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 = IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__GPIO5_22 = IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP = IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 = IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 = IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 = IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__GPIO5_23 = IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT = IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 = IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 = IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 = IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__GPIO5_24 = IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK = IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 = IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 = IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 = IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__GPIO5_25 = IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR = IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 = IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 = IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 = IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__GPIO5_26 = IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC = IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 = IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 = IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 = IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__GPIO5_27 = IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR = IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 = IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 = IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 = IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__GPIO5_28 = IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX = IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 = IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 = IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 = IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__GPIO5_29 = IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX = IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 = IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 = IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 = IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__GPIO5_30 = IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__UART4_TXD_MUX = IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 = IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 = IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 = IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 = IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__GPIO5_31 = IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__UART4_RXD_MUX = IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 = IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 = IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 = IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 = IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__GPIO6_0 = IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__UART5_TXD_MUX = IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 = IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 = IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 = IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 = IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__GPIO6_1 = IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__UART5_RXD_MUX = IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 = IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 = IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 = IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 = IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__GPIO6_2 = IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 = IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 = IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 = IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 = IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__GPIO6_3 = IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 = IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 = IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 = IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 = IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__GPIO6_4 = IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 = IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 = IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 = IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 = IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__GPIO6_5 = IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 = IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 = IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK = IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__EMI_WEIM_A_25 = IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__GPIO5_2 = IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__IPU_DI1_PIN12 = IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__CSPI_SS1 = IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL), - MX53_PAD_EIM_A25__IPU_DI0_D1_CS = IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__USBPHY1_BISTOK = IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 = IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__GPIO2_30 = IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS = IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D16__EMI_WEIM_D_16 = IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__GPIO3_16 = IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__IPU_DI0_PIN5 = IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK = IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL), - MX53_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D17__EMI_WEIM_D_17 = IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__GPIO3_17 = IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__IPU_DI0_PIN6 = IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN = IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL), - MX53_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__EMI_WEIM_D_18 = IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__GPIO3_18 = IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__IPU_DI0_PIN7 = IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO = IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL), - MX53_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__IPU_DI1_D0_CS = IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__EMI_WEIM_D_19 = IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__GPIO3_19 = IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__IPU_DI0_PIN8 = IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS = IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL), - MX53_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D19__USBOH3_USBH2_OC = IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__EMI_WEIM_D_20 = IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__GPIO3_20 = IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__IPU_DI0_PIN16 = IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__IPU_SER_DISP0_CS = IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__CSPI_SS0 = IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D20__USBOH3_USBH2_PWR = IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__EMI_WEIM_D_21 = IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__GPIO3_21 = IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__IPU_DI0_PIN17 = IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK = IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__CSPI_SCLK = IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D22__EMI_WEIM_D_22 = IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__GPIO3_22 = IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__IPU_DI0_PIN1 = IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN = IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__CSPI_MISO = IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__EMI_WEIM_D_23 = IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__GPIO3_23 = IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_DI0_D0_CS = IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_DI1_PIN2 = IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN = IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_DI1_PIN14 = IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 = IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__GPIO2_31 = IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__IPU_DI1_PIN3 = IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC = IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__IPU_DI1_PIN16 = IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__EMI_WEIM_D_24 = IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__GPIO3_24 = IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__UART3_TXD_MUX = IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D24__CSPI_SS2 = IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__EMI_WEIM_D_25 = IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__GPIO3_25 = IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__UART3_RXD_MUX = IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D25__CSPI_SS3 = IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__EMI_WEIM_D_26 = IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__GPIO3_26 = IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__UART2_TXD_MUX = IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D26__FIRI_RXD = IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_CSI0_D_1 = IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_DI1_PIN11 = IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_SISG_2 = IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 = IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__EMI_WEIM_D_27 = IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__GPIO3_27 = IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__UART2_RXD_MUX = IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D27__FIRI_TXD = IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_CSI0_D_0 = IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_DI1_PIN13 = IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_SISG_3 = IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 = IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__EMI_WEIM_D_28 = IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__GPIO3_28 = IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO = IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D28__CSPI_MOSI = IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D28__IPU_EXT_TRIG = IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__IPU_DI0_PIN13 = IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__EMI_WEIM_D_29 = IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__GPIO3_29 = IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS = IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__CSPI_SS0 = IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_DI1_PIN15 = IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_CSI1_VSYNC = IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_DI0_PIN14 = IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__EMI_WEIM_D_30 = IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__GPIO3_30 = IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D30__IPU_CSI0_D_3 = IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__IPU_DI0_PIN11 = IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 = IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__USBOH3_USBH2_OC = IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D31__EMI_WEIM_D_31 = IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__GPIO3_31 = IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D31__IPU_CSI0_D_2 = IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__IPU_DI0_PIN12 = IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 = IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__USBOH3_USBH2_PWR = IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__EMI_WEIM_A_24 = IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__GPIO5_4 = IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 = IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__IPU_CSI1_D_19 = IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__IPU_SISG_2 = IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__USBPHY2_BVALID = IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__EMI_WEIM_A_23 = IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__GPIO6_6 = IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 = IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__IPU_CSI1_D_18 = IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__IPU_SISG_3 = IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__USBPHY2_ENDSESSION = IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__EMI_WEIM_A_22 = IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 = IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__IPU_CSI1_D_17 = IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__SRC_BT_CFG1_7 = IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__EMI_WEIM_A_21 = IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__GPIO2_17 = IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 = IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__IPU_CSI1_D_16 = IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__SRC_BT_CFG1_6 = IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__EMI_WEIM_A_20 = IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__GPIO2_18 = IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 = IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__IPU_CSI1_D_15 = IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__SRC_BT_CFG1_5 = IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__EMI_WEIM_A_19 = IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__GPIO2_19 = IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 = IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__IPU_CSI1_D_14 = IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__SRC_BT_CFG1_4 = IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__EMI_WEIM_A_18 = IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__GPIO2_20 = IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 = IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__IPU_CSI1_D_13 = IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__SRC_BT_CFG1_3 = IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__EMI_WEIM_A_17 = IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__GPIO2_21 = IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 = IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__IPU_CSI1_D_12 = IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__SRC_BT_CFG1_2 = IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__EMI_WEIM_A_16 = IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__GPIO2_22 = IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK = IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK = IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__SRC_BT_CFG1_1 = IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 = IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__GPIO2_23 = IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__IPU_DI1_PIN5 = IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 = IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__GPIO2_24 = IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__IPU_DI1_PIN6 = IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__EMI_WEIM_OE = IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__GPIO2_25 = IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL), - MX53_PAD_EIM_OE__IPU_DI1_PIN7 = IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__USBPHY2_IDDIG = IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__EMI_WEIM_RW = IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__GPIO2_26 = IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL), - MX53_PAD_EIM_RW__IPU_DI1_PIN8 = IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT = IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__EMI_WEIM_LBA = IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__GPIO2_27 = IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__IPU_DI1_PIN17 = IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 = IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 = IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__GPIO2_28 = IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 = IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__IPU_CSI1_D_11 = IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__GPC_PMIC_RDY = IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 = IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 = IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__GPIO2_29 = IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 = IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__IPU_CSI1_D_10 = IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 = IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 = IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__GPIO3_0 = IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 = IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__IPU_CSI1_D_9 = IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 = IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 = IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__GPIO3_1 = IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 = IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__IPU_CSI1_D_8 = IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 = IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 = IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__GPIO3_2 = IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 = IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__IPU_CSI1_D_7 = IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 = IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 = IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__GPIO3_3 = IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 = IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__IPU_CSI1_D_6 = IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 = IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 = IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__GPIO3_4 = IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 = IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__IPU_CSI1_D_5 = IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 = IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 = IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__GPIO3_5 = IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 = IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__IPU_CSI1_D_4 = IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 = IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 = IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__GPIO3_6 = IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 = IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__IPU_CSI1_D_3 = IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 = IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 = IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__GPIO3_7 = IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 = IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__IPU_CSI1_D_2 = IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 = IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 = IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__GPIO3_8 = IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 = IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__IPU_CSI1_D_1 = IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 = IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 = IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__GPIO3_9 = IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 = IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__IPU_CSI1_D_0 = IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 = IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 = IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__GPIO3_10 = IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 = IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN = IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 = IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 = IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11 = IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__IPU_DI1_PIN2 = IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC = IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 = IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__GPIO3_12 = IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__IPU_DI1_PIN3 = IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC = IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 = IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13 = IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS = IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 = IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__GPIO3_14 = IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS = IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 = IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__GPIO3_15 = IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__IPU_DI1_PIN1 = IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__IPU_DI1_PIN4 = IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WE_B__GPIO6_12 = IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RE_B__GPIO6_13 = IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT = IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_WAIT__GPIO5_0 = IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B = IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX3_P__GPIO6_22 = IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX2_P__GPIO6_24 = IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_CLK_P__GPIO6_26 = IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX1_P__GPIO6_28 = IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX0_P__GPIO6_30 = IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX3_P__GPIO7_22 = IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_CLK_P__GPIO7_24 = IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX2_P__GPIO7_26 = IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX1_P__GPIO7_28 = IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX0_P__GPIO7_30 = IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_10__GPIO4_0 = IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_10__OSC32k_32K_OUT = IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_11__GPIO4_1 = IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_12__GPIO4_2 = IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_13__GPIO4_3 = IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_14__GPIO4_4 = IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE = IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CLE__GPIO6_7 = IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 = IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE = IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_ALE__GPIO6_8 = IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 = IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WP_B__GPIO6_9 = IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 = IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 = IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RB0__GPIO6_10 = IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 = IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 = IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS0__GPIO6_11 = IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 = IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 = IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__GPIO6_14 = IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__MLB_MLBCLK = IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 = IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 = IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__GPIO6_15 = IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__IPU_SISG_0 = IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__EMI_WEIM_CRE = IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK = IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__MLB_MLBSIG = IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 = IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 = IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__GPIO6_16 = IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__IPU_SISG_1 = IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 = IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__MLB_MLBDAT = IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 = IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__GPIO1_22 = IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__ESAI1_SCKR = IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__FEC_COL = IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 = IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 = IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK = IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__GPIO1_23 = IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 = IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__FEC_RX_ER = IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__GPIO1_24 = IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__FEC_RX_CLK = IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 = IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_CRS_DV__GPIO1_25 = IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__FEC_RDATA_1 = IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__GPIO1_26 = IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__ESAI1_FST = IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__MLB_MLBSIG = IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 = IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__FEC_RDATA_0 = IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__GPIO1_27 = IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__ESAI1_HCKT = IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__OSC32k_32K_OUT = IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TX_EN__GPIO1_28 = IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__FEC_TDATA_1 = IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__GPIO1_29 = IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__MLB_MLBCLK = IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK = IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__FEC_TDATA_0 = IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__GPIO1_30 = IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 = IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__GPIO1_31 = IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__MLB_MLBDAT = IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG = IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 = IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOW__PATA_DIOW = IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOW__GPIO6_17 = IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOW__UART1_TXD_MUX = IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 = IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMACK__PATA_DMACK = IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMACK__GPIO6_18 = IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMACK__UART1_RXD_MUX = IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 = IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__PATA_DMARQ = IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__GPIO7_0 = IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX = IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 = IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 = IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN = IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__GPIO7_1 = IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX = IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 = IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 = IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__PATA_INTRQ = IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__GPIO7_2 = IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__UART2_CTS = IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_INTRQ__CAN1_TXCAN = IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 = IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 = IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__PATA_DIOR = IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__GPIO7_3 = IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__UART2_RTS = IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DIOR__CAN1_RXCAN = IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 = IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B = IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__GPIO7_4 = IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__ESDHC3_CMD = IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_RESET_B__UART1_CTS = IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_RESET_B__CAN2_TXCAN = IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 = IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__PATA_IORDY = IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__GPIO7_5 = IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__ESDHC3_CLK = IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_IORDY__UART1_RTS = IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_IORDY__CAN2_RXCAN = IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 = IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__PATA_DA_0 = IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__GPIO7_6 = IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__ESDHC3_RST = IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__OWIRE_LINE = IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 = IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_1__PATA_DA_1 = IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_1__GPIO7_7 = IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_1__ESDHC4_CMD = IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DA_1__UART3_CTS = IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 = IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_2__PATA_DA_2 = IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_2__GPIO7_8 = IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_2__ESDHC4_CLK = IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DA_2__UART3_RTS = IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 = IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_0__PATA_CS_0 = IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_0__GPIO7_9 = IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_0__UART3_TXD_MUX = IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 = IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_1__PATA_CS_1 = IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_1__GPIO7_10 = IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_1__UART3_RXD_MUX = IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 = IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__PATA_DATA_0 = IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__GPIO2_0 = IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 = IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 = IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 = IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 = IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__PATA_DATA_1 = IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__GPIO2_1 = IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 = IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 = IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 = IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__PATA_DATA_2 = IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__GPIO2_2 = IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 = IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 = IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 = IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__PATA_DATA_3 = IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__GPIO2_3 = IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 = IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 = IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 = IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__PATA_DATA_4 = IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__GPIO2_4 = IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 = IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__ESDHC4_DAT4 = IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 = IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__PATA_DATA_5 = IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__GPIO2_5 = IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 = IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__ESDHC4_DAT5 = IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 = IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__PATA_DATA_6 = IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__GPIO2_6 = IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 = IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__ESDHC4_DAT6 = IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 = IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__PATA_DATA_7 = IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__GPIO2_7 = IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 = IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__ESDHC4_DAT7 = IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 = IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__PATA_DATA_8 = IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__GPIO2_8 = IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__ESDHC1_DAT4 = IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 = IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 = IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 = IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 = IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__PATA_DATA_9 = IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__GPIO2_9 = IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__ESDHC1_DAT5 = IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 = IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 = IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 = IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 = IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__PATA_DATA_10 = IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__GPIO2_10 = IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__ESDHC1_DAT6 = IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 = IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 = IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 = IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 = IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__PATA_DATA_11 = IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__GPIO2_11 = IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__ESDHC1_DAT7 = IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 = IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 = IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 = IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 = IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__PATA_DATA_12 = IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__GPIO2_12 = IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__ESDHC2_DAT4 = IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 = IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__ESDHC4_DAT0 = IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 = IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 = IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__PATA_DATA_13 = IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__GPIO2_13 = IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__ESDHC2_DAT5 = IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 = IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__ESDHC4_DAT1 = IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 = IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 = IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__PATA_DATA_14 = IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__GPIO2_14 = IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__ESDHC2_DAT6 = IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 = IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__ESDHC4_DAT2 = IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 = IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 = IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__PATA_DATA_15 = IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__GPIO2_15 = IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__ESDHC2_DAT7 = IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 = IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__ESDHC4_DAT3 = IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 = IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 = IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA0__GPIO1_16 = IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__GPT_CAPIN1 = IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__CSPI_MISO = IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__CCM_PLL3_BYP = IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA1__GPIO1_17 = IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__GPT_CAPIN2 = IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__CSPI_SS0 = IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__CCM_PLL4_BYP = IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_CMD__GPIO1_18 = IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__CSPI_MOSI = IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__CCM_PLL1_BYP = IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA2__GPIO1_19 = IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__GPT_CMPOUT2 = IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__PWM2_PWMO = IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__WDOG1_WDOG_B = IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__CSPI_SS1 = IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__CCM_PLL2_BYP = IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_CLK__GPIO1_20 = IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__OSC32k_32K_OUT = IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__CSPI_SCLK = IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA3__GPIO1_21 = IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__GPT_CMPOUT3 = IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__PWM1_PWMO = IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__WDOG2_WDOG_B = IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__CSPI_SS2 = IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 = IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_CLK__GPIO1_10 = IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__CSPI_SCLK = IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__SCC_RANDOM_V = IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_CMD__GPIO1_11 = IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__CSPI_MOSI = IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__SCC_RANDOM = IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA3__GPIO1_12 = IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__CSPI_SS2 = IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__SJC_DONE = IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA2__GPIO1_13 = IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__CSPI_SS1 = IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__SJC_FAIL = IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA1__GPIO1_14 = IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__CSPI_SS0 = IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__RTIC_SEC_VIO = IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA0__GPIO1_15 = IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__CSPI_MISO = IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__RTIC_DONE_INT = IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__GPIO1_0 = IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL), - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK = IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__SRTC_ALARM_DEB = IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__CSU_TD = IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_1__GPIO1_1 = IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK = IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__ESDHC1_CD = IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_9__GPIO1_9 = IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__ESDHC1_WP = IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_9__SCC_FAIL_STATE = IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_3__GPIO1_3 = IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_3__DPLLIP1_TOG_EN = IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_6__GPIO1_6 = IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__ESDHC2_LCTL = IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_2__GPIO1_2 = IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__ESDHC2_WP = IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_4__GPIO1_4 = IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__ESDHC2_CD = IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__SCC_SEC_STATE = IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_5__GPIO1_5 = IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_5__CCM_PLL1_BYP = IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_7__GPIO1_7 = IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__UART2_TXD_MUX = IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_GPIO_7__FIRI_RXD = IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__CCM_PLL2_BYP = IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_8__GPIO1_8 = IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL), - MX53_PAD_GPIO_8__UART2_RXD_MUX = IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL), - MX53_PAD_GPIO_8__FIRI_TXD = IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__CCM_PLL3_BYP = IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_16__GPIO7_11 = IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT = IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 = IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_17__GPIO7_12 = IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_17__GPC_PMIC_RDY = IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG = IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__IPU_SNOOP2 = IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__GPIO7_13 = IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__OWIRE_LINE = IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG = IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__ESDHC1_LCTL = IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX53_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h deleted file mode 100644 index c8aff2b..0000000 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ -#ifndef __SYS_PROTO_IMX5_ -#define __SYS_PROTO_IMX5_ - -#include <asm/mach-imx/sys_proto.h> - -#endif /* __SYS_PROTO_IMX5_ */ diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h deleted file mode 100644 index a9481a5..0000000 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_SYS_MX6_HCLK -#define MXC_HCLK CONFIG_SYS_MX6_HCLK -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_SYS_MX6_CLK32 -#define MXC_CLK32 CONFIG_SYS_MX6_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_PER_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_AXI_CLK, - MXC_EMI_SLOW_CLK, - MXC_DDR_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_ESDHC4_CLK, - MXC_SATA_CLK, - MXC_NFC_CLK, - MXC_I2C_CLK, -}; - -enum ldb_di_clock { - MXC_PLL5_CLK = 0, - MXC_PLL2_PFD0_CLK, - MXC_PLL2_PFD2_CLK, - MXC_MMDC_CH1_CLK, - MXC_PLL3_SW_CLK, -}; - -enum enet_freq { - ENET_25MHZ, - ENET_50MHZ, - ENET_100MHZ, - ENET_125MHZ, -}; - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); -void setup_gpmi_io_clk(u32 cfg); -void hab_caam_clock_enable(unsigned char enable); -void enable_ocotp_clk(unsigned char enable); -void enable_usboh3_clk(unsigned char enable); -void enable_uart_clk(unsigned char enable); -int enable_usdhc_clk(unsigned char enable, unsigned bus_num); -int enable_sata_clock(void); -void disable_sata_clock(void); -int enable_pcie_clock(void); -int enable_i2c_clk(unsigned char enable, unsigned i2c_num); -int enable_spi_clk(unsigned char enable, unsigned spi_num); -void enable_ipu_clock(void); -int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); -void enable_enet_clk(unsigned char enable); -int enable_lcdif_clock(u32 base_addr, bool enable); -void enable_qspi_clk(int qspi_num); -void enable_thermal_clk(void); -void mxs_set_lcdclk(u32 base_addr, u32 freq); -void select_ldb_di_clock_source(enum ldb_di_clock clk); -void enable_eim_clk(unsigned char enable); -int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h deleted file mode 100644 index 4174f24..0000000 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ /dev/null @@ -1,1309 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ -#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ - -#define CCM_CCOSR 0x020c4060 -#define CCM_CCGR0 0x020C4068 -#define CCM_CCGR1 0x020C406c -#define CCM_CCGR2 0x020C4070 -#define CCM_CCGR3 0x020C4074 -#define CCM_CCGR4 0x020C4078 -#define CCM_CCGR5 0x020C407c -#define CCM_CCGR6 0x020C4080 - -#define PMU_MISC2 0x020C8170 - -#ifndef __ASSEMBLY__ -struct mxc_ccm_reg { - u32 ccr; /* 0x0000 */ - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; /* 0x0010*/ - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; /* 0x0020 */ - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; /* 0x0030 */ - u32 chsccdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; /* 0x0040 */ - u32 resv0; - u32 cdhipr; - u32 cdcr; - u32 ctor; /* 0x0050 */ - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; /* 0x0060 */ - u32 cgpr; - u32 CCGR0; - u32 CCGR1; - u32 CCGR2; /* 0x0070 */ - u32 CCGR3; - u32 CCGR4; - u32 CCGR5; - u32 CCGR6; /* 0x0080 */ - u32 CCGR7; - u32 cmeor; - u32 resv[0xfdd]; - u32 analog_pll_sys; /* 0x4000 */ - u32 analog_pll_sys_set; - u32 analog_pll_sys_clr; - u32 analog_pll_sys_tog; - u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ - u32 analog_usb1_pll_480_ctrl_set; - u32 analog_usb1_pll_480_ctrl_clr; - u32 analog_usb1_pll_480_ctrl_tog; - u32 analog_reserved0[4]; - u32 analog_pll_528; /* 0x4030 */ - u32 analog_pll_528_set; - u32 analog_pll_528_clr; - u32 analog_pll_528_tog; - u32 analog_pll_528_ss; /* 0x4040 */ - u32 analog_reserved1[3]; - u32 analog_pll_528_num; /* 0x4050 */ - u32 analog_reserved2[3]; - u32 analog_pll_528_denom; /* 0x4060 */ - u32 analog_reserved3[3]; - u32 analog_pll_audio; /* 0x4070 */ - u32 analog_pll_audio_set; - u32 analog_pll_audio_clr; - u32 analog_pll_audio_tog; - u32 analog_pll_audio_num; /* 0x4080*/ - u32 analog_reserved4[3]; - u32 analog_pll_audio_denom; /* 0x4090 */ - u32 analog_reserved5[3]; - u32 analog_pll_video; /* 0x40a0 */ - u32 analog_pll_video_set; - u32 analog_pll_video_clr; - u32 analog_pll_video_tog; - u32 analog_pll_video_num; /* 0x40b0 */ - u32 analog_reserved6[3]; - u32 analog_pll_video_denom; /* 0x40c0 */ - u32 analog_reserved7[7]; - u32 analog_pll_enet; /* 0x40e0 */ - u32 analog_pll_enet_set; - u32 analog_pll_enet_clr; - u32 analog_pll_enet_tog; - u32 analog_pfd_480; /* 0x40f0 */ - u32 analog_pfd_480_set; - u32 analog_pfd_480_clr; - u32 analog_pfd_480_tog; - u32 analog_pfd_528; /* 0x4100 */ - u32 analog_pfd_528_set; - u32 analog_pfd_528_clr; - u32 analog_pfd_528_tog; - /* PMU Memory Map/Register Definition */ - u32 pmu_reg_1p1; - u32 pmu_reg_1p1_set; - u32 pmu_reg_1p1_clr; - u32 pmu_reg_1p1_tog; - u32 pmu_reg_3p0; - u32 pmu_reg_3p0_set; - u32 pmu_reg_3p0_clr; - u32 pmu_reg_3p0_tog; - u32 pmu_reg_2p5; - u32 pmu_reg_2p5_set; - u32 pmu_reg_2p5_clr; - u32 pmu_reg_2p5_tog; - u32 pmu_reg_core; - u32 pmu_reg_core_set; - u32 pmu_reg_core_clr; - u32 pmu_reg_core_tog; - u32 pmu_misc0; - u32 pmu_misc0_set; - u32 pmu_misc0_clr; - u32 pmu_misc0_tog; - u32 pmu_misc1; - u32 pmu_misc1_set; - u32 pmu_misc1_clr; - u32 pmu_misc1_tog; - u32 pmu_misc2; - u32 pmu_misc2_set; - u32 pmu_misc2_clr; - u32 pmu_misc2_tog; - /* TEMPMON Memory Map/Register Definition */ - u32 tempsense0; - u32 tempsense0_set; - u32 tempsense0_clr; - u32 tempsense0_tog; - u32 tempsense1; - u32 tempsense1_set; - u32 tempsense1_clr; - u32 tempsense1_tog; - /* USB Analog Memory Map/Register Definition */ - u32 usb1_vbus_detect; - u32 usb1_vbus_detect_set; - u32 usb1_vbus_detect_clr; - u32 usb1_vbus_detect_tog; - u32 usb1_chrg_detect; - u32 usb1_chrg_detect_set; - u32 usb1_chrg_detect_clr; - u32 usb1_chrg_detect_tog; - u32 usb1_vbus_det_stat; - u32 usb1_vbus_det_stat_set; - u32 usb1_vbus_det_stat_clr; - u32 usb1_vbus_det_stat_tog; - u32 usb1_chrg_det_stat; - u32 usb1_chrg_det_stat_set; - u32 usb1_chrg_det_stat_clr; - u32 usb1_chrg_det_stat_tog; - u32 usb1_loopback; - u32 usb1_loopback_set; - u32 usb1_loopback_clr; - u32 usb1_loopback_tog; - u32 usb1_misc; - u32 usb1_misc_set; - u32 usb1_misc_clr; - u32 usb1_misc_tog; - u32 usb2_vbus_detect; - u32 usb2_vbus_detect_set; - u32 usb2_vbus_detect_clr; - u32 usb2_vbus_detect_tog; - u32 usb2_chrg_detect; - u32 usb2_chrg_detect_set; - u32 usb2_chrg_detect_clr; - u32 usb2_chrg_detect_tog; - u32 usb2_vbus_det_stat; - u32 usb2_vbus_det_stat_set; - u32 usb2_vbus_det_stat_clr; - u32 usb2_vbus_det_stat_tog; - u32 usb2_chrg_det_stat; - u32 usb2_chrg_det_stat_set; - u32 usb2_chrg_det_stat_clr; - u32 usb2_chrg_det_stat_tog; - u32 usb2_loopback; - u32 usb2_loopback_set; - u32 usb2_loopback_clr; - u32 usb2_loopback_tog; - u32 usb2_misc; - u32 usb2_misc_set; - u32 usb2_misc_clr; - u32 usb2_misc_tog; - u32 digprog; - u32 reserved1[7]; - /* For i.MX 6SoloLite */ - u32 digprog_sololite; -}; -#endif - -/* Define the bits in register CCR */ -#define MXC_CCM_CCR_RBC_EN (1 << 27) -#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) -#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 -/* CCR_WB does not exist on i.MX6SX/UL */ -#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 -#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) -#define MXC_CCM_CCR_COSC_EN (1 << 12) -#ifdef CONFIG_MX6SX -#define MXC_CCM_CCR_OSCNT_MASK 0x7F -#else -#define MXC_CCM_CCR_OSCNT_MASK 0xFF -#endif -#define MXC_CCM_CCR_OSCNT_OFFSET 0 - -/* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) -#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) -/* Exists on i.MX6QP */ -#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) - -/* Define the bits in register CSR */ -#define MXC_CCM_CSR_COSC_READY (1 << 5) -#define MXC_CCM_CSR_REF_EN_B (1 << 0) - -/* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) -#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) -#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) -#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) -#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) -#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) -#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) -#define MXC_CCM_CCSR_STEP_SEL (1 << 8) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) -/* MMDC_CH0 not exists on i.MX6SX */ -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 -#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) -#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 -/* LCDIF on i.MX6SX/UL */ -#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) -#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 -#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 -#ifndef CONFIG_MX6SX -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#endif -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 -#ifndef CONFIG_MX6SX -#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) -#endif -#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 -/* Exists on i.MX6QP */ -#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 -/* QSPI1 exist on i.MX6SX/UL */ -#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) -#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 -#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) -#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 -/* LCFIF2_PODF on i.MX6SX */ -#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) -#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 -/* LCDIF_PIX_PODF on i.MX6SL */ -#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20) -#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20 -/* ACLK_EMI on i.MX6DQ/SDL/DQP */ -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 -/* CSCMR1_GPMI/BCH exist on i.MX6UL */ -#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) -#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) -#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) -#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) -#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) -#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 -/* QSPI1 exist on i.MX6SX/UL */ -#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) -#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 -/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ -#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) -#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 - -#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F - -/* Define the bits in register CSCMR2 */ -#ifdef CONFIG_MX6SX -#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) -#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 -#endif -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 -#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) -#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 - -#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 - -/* Define the bits in register CSCDR1 */ -#ifndef CONFIG_MX6SX -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 -#endif -/* CSCDR1_GPMI/BCH exist on i.MX6UL */ -#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 -#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 - -#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 -#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 -#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 -#ifndef CONFIG_MX6SX -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#endif -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 -/* UART_CLK_SEL exists on i.MX6SL/SX/QP */ -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) - -/* Define the bits in register CS1CDR */ -/* MX6UL, !MX6ULL */ -#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22 -#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16 -#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F -#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0 - -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 -#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 - -/* Define the bits in register CS2CDR */ -/* QSPI2 on i.MX6SX */ -#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) -#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 -#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) -#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) -#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 -#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) -#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 -#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) - -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) - -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) - -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ - MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ - MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ - MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ - MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) - -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 - -/* Define the bits in register CDCDR */ -#ifndef CONFIG_MX6SX -#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) -#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 -#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) -#endif -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 - -/* Define the bits in register CHSCCDR */ -/* i.MX6SX */ -#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) -#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 - -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 - -/* i.MX6ULL */ -#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9 - -#define CHSCCDR_CLK_SEL_LDB_DI0 3 -#define CHSCCDR_PODF_DIVIDE_BY_3 2 -#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 -/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ -#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) -/* LCDIF1 on i.MX6SX/UL */ -#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) -#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 -#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) -#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 -#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 -/* LCDIF2 on i.MX6SX */ -#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 -#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) -#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 -#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) -#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 - -/*LCD on i.MX6SL */ -#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6 -#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3) -#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3 - -/* All IPU2_DI1 are LCDIF1 on MX6SX */ -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 -/* All IPU2_DI0 are LCDIF2 on MX6SX */ -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 - -/* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 - -/* For i.MX6SL */ -#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16) -#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16 -#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14 - -/* Define the bits in register CDHIPR */ -#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) -#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) -#endif -#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) -#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) -#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) -#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 - -/* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) -#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) -#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) -#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) -#endif -#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) -#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) -#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) -#endif -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) -#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) -#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 -#define MXC_CCM_CLPCR_VSTBY (1 << 8) -#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) -#define MXC_CCM_CLPCR_SBYOS (1 << 6) -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 -#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) -#endif -#define MXC_CCM_CLPCR_LPM_MASK 0x3 -#define MXC_CCM_CLPCR_LPM_OFFSET 0 - -/* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) -#endif -#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) -#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CISR_COSC_READY (1 << 6) -#define MXC_CCM_CISR_LRF_PLL 1 - -/* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) -#endif -#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) -#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) -#define MXC_CCM_CIMR_MASK_LRF_PLL 1 - -/* Define the bits in register CCOSR */ -#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) -#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 -#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) -#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) -#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) -#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 -#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF -#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 - -/* Define the bits in registers CGPR */ -#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) -#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) -#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 - -/* Define the bits in registers CCGRx */ -#define MXC_CCM_CCGR_CG_MASK 3 - -/* i.MX 6ULL */ -#define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10 -#define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET) -#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12 -#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET) - -#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 -#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) -#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 -#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) -#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 -#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) -#define MXC_CCM_CCGR0_ASRC_OFFSET 6 -#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) -#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 -#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) -#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 -#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) -#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 -#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) -#define MXC_CCM_CCGR0_CAN1_OFFSET 14 -#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) -#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 -#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) -#define MXC_CCM_CCGR0_CAN2_OFFSET 18 -#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) -#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 -#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) -#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 -#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) -#define MXC_CCM_CCGR0_DCIC1_OFFSET 24 -#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) -#define MXC_CCM_CCGR0_DCIC2_OFFSET 26 -#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) -#ifdef CONFIG_MX6SX -#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 -#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) -#else -#define MXC_CCM_CCGR0_DTCP_OFFSET 28 -#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) -#endif - -#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 -#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 -#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 -#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 -#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 -#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) -/* CCGR1_ENET does not exist on i.MX6SX/UL */ -#define MXC_CCM_CCGR1_ENET_OFFSET 10 -#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) -#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 -#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) -#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 -#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) -#define MXC_CCM_CCGR1_ESAIS_OFFSET 16 -#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) -#ifdef CONFIG_MX6SX -#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 -#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) -#endif -#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 -#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) -#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 -#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CCGR1_GPU2D_OFFSET 24 -#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) -#endif -#define MXC_CCM_CCGR1_GPU3D_OFFSET 26 -#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) -#ifdef CONFIG_MX6SX -#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 -#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) -#define MXC_CCM_CCGR1_CANFD_OFFSET 30 -#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) -#endif - -#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 -#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) -/* i.MX6SX/UL */ -#define MXC_CCM_CCGR2_CSI_OFFSET 2 -#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) - -#ifndef CONFIG_MX6SX -#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 -#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) -#endif -#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 -#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) -#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 -#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) -#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 -#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) -#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 -#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) -#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 -#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) -#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 -#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) -#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 -#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) -#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 -#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) -#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 -#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) -/* i.MX6SX/UL LCD and PXP */ -#define MXC_CCM_CCGR2_LCD_OFFSET 28 -#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) -#define MXC_CCM_CCGR2_PXP_OFFSET 30 -#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) - -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) -#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 -#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) - -/* i.MX6ULL */ -#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0 -#define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET) -#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4 -#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET) - -/* Exist on i.MX6SX */ -#define MXC_CCM_CCGR3_M4_OFFSET 2 -#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) -/* i.MX6ULL */ -#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4 -#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET) -#define MXC_CCM_CCGR3_ENET_OFFSET 4 -#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) -#define MXC_CCM_CCGR3_QSPI_OFFSET 14 -#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) - -/* i.MX6SL */ -#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 -#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) -#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 -#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) - -#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 -#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) -#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 -#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) -#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 -#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) - -#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 -#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) -#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 -#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) -#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 -#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) -#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 -#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) - -/* QSPI1 exists on i.MX6SX/UL */ -#define MXC_CCM_CCGR3_QSPI1_OFFSET 14 -#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) - -#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 -#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) -#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 -#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) - -/* A7_CLKDIV/WDOG1 on i.MX6UL */ -#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 -#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) -#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 -#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) - -#define MXC_CCM_CCGR3_MLB_OFFSET 18 -#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) -#endif -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) - -#define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 -#define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) -#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 -#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) -#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 -#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) -/* AXI on i.MX6UL */ -#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 -#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) -#define MXC_CCM_CCGR3_OCRAM_OFFSET 28 -#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) - -/* GPIO4 on i.MX6UL/ULL */ -#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 -#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) - -#ifndef CONFIG_MX6SX -#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 -#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) -#endif - -/* i.MX6ULL */ -#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30 -#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET) - -#define MXC_CCM_CCGR4_PCIE_OFFSET 0 -#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) -/* QSPI2 on i.MX6SX */ -#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 -#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) -#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 -#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) -#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 -#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) -#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 -#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) -#define MXC_CCM_CCGR4_PWM1_OFFSET 16 -#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) -#define MXC_CCM_CCGR4_PWM2_OFFSET 18 -#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) -#define MXC_CCM_CCGR4_PWM3_OFFSET 20 -#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) -#define MXC_CCM_CCGR4_PWM4_OFFSET 22 -#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 -#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) - -#define MXC_CCM_CCGR5_ROM_OFFSET 0 -#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CCGR5_SATA_OFFSET 4 -#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) -#endif -#define MXC_CCM_CCGR5_SDMA_OFFSET 6 -#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) -#define MXC_CCM_CCGR5_SPBA_OFFSET 12 -#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) -#define MXC_CCM_CCGR5_SPDIF_OFFSET 14 -#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) -#define MXC_CCM_CCGR5_SSI1_OFFSET 18 -#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) -#define MXC_CCM_CCGR5_SSI2_OFFSET 20 -#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) -#define MXC_CCM_CCGR5_SSI3_OFFSET 22 -#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) -#define MXC_CCM_CCGR5_UART_OFFSET 24 -#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) -#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 -#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) -#ifdef CONFIG_MX6SX -#define MXC_CCM_CCGR5_SAI1_OFFSET 20 -#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) -#define MXC_CCM_CCGR5_SAI2_OFFSET 30 -#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) -#endif - -/* PRG_CLK0 exists on i.MX6QP */ -#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) - -#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 -#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) -#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 -#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) -#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 -#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) -#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6 -#define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET) -#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8 -#define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET) -/* i.MX6ULL */ -#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8 -#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET) -/* GPMI/BCH on i.MX6UL */ -#define MXC_CCM_CCGR6_BCH_OFFSET 6 -#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) -#define MXC_CCM_CCGR6_GPMI_OFFSET 8 -#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) - -#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 -#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) -#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 -#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) -#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 -#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) -/* i.MX6ULL */ -#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18 -#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET) -/* The following *CCGR6* exist only i.MX6SX */ -#define MXC_CCM_CCGR6_PWM8_OFFSET 16 -#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) -#define MXC_CCM_CCGR6_VADC_OFFSET 20 -#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) -#define MXC_CCM_CCGR6_GIS_OFFSET 22 -#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) -#define MXC_CCM_CCGR6_I2C4_OFFSET 24 -#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) -#define MXC_CCM_CCGR6_PWM5_OFFSET 26 -#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) -#define MXC_CCM_CCGR6_PWM6_OFFSET 28 -#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) -#define MXC_CCM_CCGR6_PWM7_OFFSET 30 -#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) -/* The two does not exist on i.MX6SX */ -#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 -#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) - -#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 -#define BP_ANADIG_PLL_SYS_RSVD0 20 -#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 -#define BF_ANADIG_PLL_SYS_RSVD0(v) \ - (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) -#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 -#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 -#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 -#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 -#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 -#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 -#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) - -#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 -#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 -#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ - (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 -#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 -#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 -#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 -#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 -#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 -#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C -#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ - (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) -#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 -#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 -#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) - -#define BM_ANADIG_PLL_528_LOCK 0x80000000 -#define BP_ANADIG_PLL_528_RSVD1 19 -#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 -#define BF_ANADIG_PLL_528_RSVD1(v) \ - (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) -#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_528_BYPASS 0x00010000 -#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_528_ENABLE 0x00002000 -#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_528_RSVD0 1 -#define BM_ANADIG_PLL_528_RSVD0 0x0000007E -#define BF_ANADIG_PLL_528_RSVD0(v) \ - (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) -#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 - -#define BP_ANADIG_PLL_528_SS_STOP 16 -#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 -#define BF_ANADIG_PLL_528_SS_STOP(v) \ - (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) -#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 -#define BP_ANADIG_PLL_528_SS_STEP 0 -#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF -#define BF_ANADIG_PLL_528_SS_STEP(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) - -#define BP_ANADIG_PLL_528_NUM_RSVD0 30 -#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) -#define BP_ANADIG_PLL_528_NUM_A 0 -#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_528_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) - -#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) -#define BP_ANADIG_PLL_528_DENOM_B 0 -#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_528_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) - -#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 -#define BP_ANADIG_PLL_AUDIO_RSVD0 22 -#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 -#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ - (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) -#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) -#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 -#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) - -#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 -#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) -#define BP_ANADIG_PLL_AUDIO_NUM_A 0 -#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) - -#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) -#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 -#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) - -#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 -#define BP_ANADIG_PLL_VIDEO_RSVD0 22 -#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 -#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ - (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) -#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 -#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) -#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 -#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) - -#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 -#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) -#define BP_ANADIG_PLL_VIDEO_NUM_A 0 -#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) - -#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) -#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 -#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) - -#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 -#define BP_ANADIG_PLL_ENET_RSVD1 21 -#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 -#define BF_ANADIG_PLL_ENET_RSVD1(v) \ - (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) -#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 -#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 -#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 -#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 -#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 -#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_ENET_RSVD0 2 -#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C -#define BF_ANADIG_PLL_ENET_RSVD0(v) \ - (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) -#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 -#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 -#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) - -/* ENET2 for i.MX6SX/UL */ -#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 -#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C -#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ - (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) - -#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_480_PFD3_FRAC 24 -#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ - (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) -#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_480_PFD2_FRAC 16 -#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ - (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) -#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_480_PFD1_FRAC 8 -#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ - (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) -#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_480_PFD0_FRAC 0 -#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ - (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) - -#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_528_PFD3_FRAC 24 -#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ - (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) -#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_528_PFD2_FRAC 16 -#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ - (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) -#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_528_PFD1_FRAC 8 -#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ - (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) -#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_528_PFD0_FRAC 0 -#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ - (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) - -#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 -#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60 -#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4 - -#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) -#define BP_PMU_MISC2_AUDIO_DIV_MSB 23 - -#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) -#define BP_PMU_MISC2_AUDIO_DIV_LSB 15 - -#define PMU_MISC2_AUDIO_DIV(v) \ - (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ - (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ - ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ - BP_PMU_MISC2_AUDIO_DIV_LSB)) - -#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h deleted file mode 100644 index b391319..0000000 --- a/arch/arm/include/asm/arch-mx6/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - */ - - -#ifndef __ASM_ARCH_MX6_GPIO_H -#define __ASM_ARCH_MX6_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif /* __ASM_ARCH_MX6_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h b/arch/arm/include/asm/arch-mx6/imx-rdc.h deleted file mode 100644 index ecdd64d..0000000 --- a/arch/arm/include/asm/arch-mx6/imx-rdc.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __IMX_RDC_H__ -#define __IMX_RDC_H__ - -#if defined(CONFIG_MX6SX) -#include "mx6sx_rdc.h" -#else -#error "Please select cpu" -#endif /* CONFIG_MX6SX */ - -#endif /* __IMX_RDC_H__*/ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h deleted file mode 100644 index 4f01b20..0000000 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ /dev/null @@ -1,1007 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MX6_IMX_REGS_H__ -#define __ASM_ARCH_MX6_IMX_REGS_H__ - -#define ARCH_MXC - -#define ROMCP_ARB_BASE_ADDR 0x00000000 -#define ROMCP_ARB_END_ADDR 0x000FFFFF - -#ifdef CONFIG_MX6SL -#define GPU_2D_ARB_BASE_ADDR 0x02200000 -#define GPU_2D_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF -#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00107FFF -#define GPU_ARB_BASE_ADDR 0x01800000 -#define GPU_ARB_END_ADDR 0x01803FFF -#define APBH_DMA_ARB_BASE_ADDR 0x01804000 -#define APBH_DMA_ARB_END_ADDR 0x0180BFFF -#define M4_BOOTROM_BASE_ADDR 0x007F8000 - -#elif !defined(CONFIG_MX6SLL) -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00103FFF -#define APBH_DMA_ARB_BASE_ADDR 0x00110000 -#define APBH_DMA_ARB_END_ADDR 0x00117FFF -#define HDMI_ARB_BASE_ADDR 0x00120000 -#define HDMI_ARB_END_ADDR 0x00128FFF -#define GPU_3D_ARB_BASE_ADDR 0x00130000 -#define GPU_3D_ARB_END_ADDR 0x00133FFF -#define GPU_2D_ARB_BASE_ADDR 0x00134000 -#define GPU_2D_ARB_END_ADDR 0x00137FFF -#define DTCP_ARB_BASE_ADDR 0x00138000 -#define DTCP_ARB_END_ADDR 0x0013BFFF -#endif /* CONFIG_MX6SL */ - -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) - -/* GPV - PL301 configuration ports */ -#if (defined(CONFIG_MX6SX) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ - defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) -#define GPV2_BASE_ADDR 0x00D00000 -#define GPV3_BASE_ADDR 0x00E00000 -#define GPV4_BASE_ADDR 0x00F00000 -#define GPV5_BASE_ADDR 0x01000000 -#define GPV6_BASE_ADDR 0x01100000 -#define PCIE_ARB_BASE_ADDR 0x08000000 -#define PCIE_ARB_END_ADDR 0x08FFFFFF - -#else -#define GPV2_BASE_ADDR 0x00200000 -#define GPV3_BASE_ADDR 0x00300000 -#define GPV4_BASE_ADDR 0x00800000 -#define PCIE_ARB_BASE_ADDR 0x01000000 -#define PCIE_ARB_END_ADDR 0x01FFFFFF -#endif - -#define IRAM_BASE_ADDR 0x00900000 -#define SCU_BASE_ADDR 0x00A00000 -#define IC_INTERFACES_BASE_ADDR 0x00A00100 -#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 -#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 -#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 -#define L2_PL310_BASE 0x00A02000 -#define GPV0_BASE_ADDR 0x00B00000 -#define GPV1_BASE_ADDR 0x00C00000 - -#define AIPS1_ARB_BASE_ADDR 0x02000000 -#define AIPS1_ARB_END_ADDR 0x020FFFFF -#define AIPS2_ARB_BASE_ADDR 0x02100000 -#define AIPS2_ARB_END_ADDR 0x021FFFFF -/* AIPS3 only on i.MX6SX */ -#define AIPS3_ARB_BASE_ADDR 0x02200000 -#define AIPS3_ARB_END_ADDR 0x022FFFFF -#ifdef CONFIG_MX6SX -#define WEIM_ARB_BASE_ADDR 0x50000000 -#define WEIM_ARB_END_ADDR 0x57FFFFFF -#define QSPI0_AMBA_BASE 0x60000000 -#define QSPI0_AMBA_END 0x6FFFFFFF -#define QSPI1_AMBA_BASE 0x70000000 -#define QSPI1_AMBA_END 0x7FFFFFFF -#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define WEIM_ARB_BASE_ADDR 0x50000000 -#define WEIM_ARB_END_ADDR 0x57FFFFFF -#define QSPI0_AMBA_BASE 0x60000000 -#define QSPI0_AMBA_END 0x6FFFFFFF -#elif !defined(CONFIG_MX6SLL) -#define SATA_ARB_BASE_ADDR 0x02200000 -#define SATA_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF -#define HSI_ARB_BASE_ADDR 0x02208000 -#define HSI_ARB_END_ADDR 0x0220BFFF -#define IPU1_ARB_BASE_ADDR 0x02400000 -#define IPU1_ARB_END_ADDR 0x027FFFFF -#define IPU2_ARB_BASE_ADDR 0x02800000 -#define IPU2_ARB_END_ADDR 0x02BFFFFF -#define WEIM_ARB_BASE_ADDR 0x08000000 -#define WEIM_ARB_END_ADDR 0x0FFFFFFF -#endif - -#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6SX) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define MMDC0_ARB_BASE_ADDR 0x80000000 -#define MMDC0_ARB_END_ADDR 0xFFFFFFFF -#define MMDC1_ARB_BASE_ADDR 0xC0000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF -#else -#define MMDC0_ARB_BASE_ADDR 0x10000000 -#define MMDC0_ARB_END_ADDR 0x7FFFFFFF -#define MMDC1_ARB_BASE_ADDR 0x80000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF -#endif - -#ifndef CONFIG_MX6SX -#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR -#define IPU_SOC_OFFSET 0x00200000 -#endif - -/* Defines for Blocks connected via AIPS (SkyBlue) */ -#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR -#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR -#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR -#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR -#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR -#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR - -#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) -#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) -#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) -#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) -#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) - -#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) - -#ifndef CONFIG_MX6SX -#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#endif -#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) -#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) -#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) - -#ifndef CONFIG_MX6SX -#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) -#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) -#endif -#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) - -#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) -#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) -#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) -#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) -#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) -#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) -#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) -/* QOSC on i.MX6SLL */ -#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) -#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) -#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) -#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) -#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) -#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) -#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) -#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) -#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) -#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) -#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) -#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) -#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) -#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) -#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) -#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) -#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) -#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) -#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) -#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) -#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) -#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) -#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) -#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#ifdef CONFIG_MX6SLL -#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) -#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) -#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) -#elif defined(CONFIG_MX6SL) -#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#elif defined(CONFIG_MX6SX) -#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) -#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) -#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) -#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) -#else -#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#endif - -#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) -#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) - -#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) -#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) -#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) -#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) -#if defined(CONFIG_MX6UL) -#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) -#else -#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) -#endif -#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) - -#define CONFIG_SYS_FSL_SEC_OFFSET 0 -#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ - CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 -#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ - CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - -#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) - -#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) -#ifdef CONFIG_MX6SL -#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) -#else -#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) -#endif - -#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) -#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) -#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) -#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) -#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) -#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) -#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) -#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) -#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) -/* i.MX6SL/SLL */ -#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) -#else -/* i.MX6SX */ -#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#endif -/* i.MX6DQ/SDL */ -#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) - -#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) -#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) -#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) -#ifdef CONFIG_MX6SLL -#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) -#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#endif -#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) -#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#ifdef CONFIG_MX6SX -#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#else -#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#endif -#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) -#elif defined(CONFIG_MX6SX) -#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) -#else -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) -#endif -#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) -#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) -#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) -#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) -#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) -#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) -#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) -#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) -/* i.MX6SLL */ -#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) - -#ifdef CONFIG_MX6SX -#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) -#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) -#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) -#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) -#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) -#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) -#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) -#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) -#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) -#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) -#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) -#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) -#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) -#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#endif - -#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000) - -/* Only for i.MX6SX */ -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) -#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) - -#if !(defined(CONFIG_MX6SX) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ - defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) -#define IRAM_SIZE 0x00040000 -#else -#define IRAM_SIZE 0x00020000 -#endif -#define FEC_QUIRK_ENET_MAC - -#include <asm/mach-imx/regs-lcdif.h> -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* only for i.MX6SX/UL */ -#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \ - MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) -#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \ - MX6SLL_LCDIF_BASE_ADDR : \ - (is_cpu_type(MXC_CPU_MX6SL)) ? \ - MX6SL_LCDIF_BASE_ADDR : \ - ((is_cpu_type(MXC_CPU_MX6UL)) ? \ - MX6UL_LCDIF1_BASE_ADDR : \ - ((is_mx6ull()) ? \ - MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) - - -extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); - -#define SRC_SCR_CORE_1_RESET_OFFSET 14 -#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) -#define SRC_SCR_CORE_2_RESET_OFFSET 15 -#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) -#define SRC_SCR_CORE_3_RESET_OFFSET 16 -#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) -#define SRC_SCR_CORE_1_ENABLE_OFFSET 22 -#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) -#define SRC_SCR_CORE_2_ENABLE_OFFSET 23 -#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) -#define SRC_SCR_CORE_3_ENABLE_OFFSET 24 -#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) - -struct rdc_regs { - u32 vir; /* Version information */ - u32 reserved1[8]; - u32 stat; /* Status */ - u32 intctrl; /* Interrupt and Control */ - u32 intstat; /* Interrupt Status */ - u32 reserved2[116]; - u32 mda[32]; /* Master Domain Assignment */ - u32 reserved3[96]; - u32 pdap[104]; /* Peripheral Domain Access Permissions */ - u32 reserved4[88]; - struct { - u32 mrsa; /* Memory Region Start Address */ - u32 mrea; /* Memory Region End Address */ - u32 mrc; /* Memory Region Control */ - u32 mrvs; /* Memory Region Violation Status */ - } mem_region[55]; -}; - -struct rdc_sema_regs { - u8 gate[64]; /* Gate */ - u16 rstgt; /* Reset Gate */ -}; - -/* WEIM registers */ -struct weim { - u32 cs0gcr1; - u32 cs0gcr2; - u32 cs0rcr1; - u32 cs0rcr2; - u32 cs0wcr1; - u32 cs0wcr2; - - u32 cs1gcr1; - u32 cs1gcr2; - u32 cs1rcr1; - u32 cs1rcr2; - u32 cs1wcr1; - u32 cs1wcr2; - - u32 cs2gcr1; - u32 cs2gcr2; - u32 cs2rcr1; - u32 cs2rcr2; - u32 cs2wcr1; - u32 cs2wcr2; - - u32 cs3gcr1; - u32 cs3gcr2; - u32 cs3rcr1; - u32 cs3rcr2; - u32 cs3wcr1; - u32 cs3wcr2; - - u32 unused[12]; - - u32 wcr; - u32 wiar; - u32 ear; -}; - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr1; - u32 srsr; - u32 reserved1[2]; - u32 sisr; - u32 simr; - u32 sbmr2; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 gpr8; - u32 gpr9; - u32 gpr10; -}; - -#define src_base ((struct src *)SRC_BASE_ADDR) - -#define SRC_M4_REG_OFFSET 0 -#define SRC_M4_ENABLE_OFFSET 22 -#define SRC_M4_ENABLE_MASK BIT(22) -#define SRC_M4C_NON_SCLR_RST_OFFSET 4 -#define SRC_M4C_NON_SCLR_RST_MASK BIT(4) - -/* GPR1 bitfields */ -#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) -#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) -#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) -#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) -#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) -#define IOMUXC_GPR1_DPI_OFF BIT(24) -#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) -#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 -#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) -#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) -#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) -#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) -#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) -#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) -#define IOMUXC_GPR1_USB_EXP_MODE BIT(15) -#define IOMUXC_GPR1_PCIE_INT BIT(14) -#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 -#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) -#define IOMUXC_GPR1_GINT BIT(12) -#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) -#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) -#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) -#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) -#define IOMUXC_GPR1_ACT_CS3 BIT(9) -#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) -#define IOMUXC_GPR1_ACT_CS2 BIT(6) -#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) -#define IOMUXC_GPR1_ACT_CS1 BIT(3) -#define IOMUXC_GPR1_ADDRS0_OFFSET (1) -#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) -#define IOMUXC_GPR1_ACT_CS0 BIT(0) - -/* GPR3 bitfields */ -#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 -#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) -#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 -#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 -#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 -#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 -#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 -#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) -#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 -#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) -#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 -#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 -#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 -#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 -#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 -#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) -#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 -#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) -#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 -#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) - -#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 -#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 -#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 -#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 - -#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 -#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) - -#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 -#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) - -#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 -#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) - -#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 -#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) - -/* gpr12 bitfields */ -#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) -#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) -#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) -#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) -#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) -#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) -#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) - -struct iomuxc { -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) - u8 reserved[0x4000]; -#endif - u32 gpr[14]; -}; - -struct gpc { - u32 cntr; - u32 pgr; - u32 imr1; - u32 imr2; - u32 imr3; - u32 imr4; - u32 isr1; - u32 isr2; - u32 isr3; - u32 isr4; -}; - -#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 -#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) -#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 -#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) - -#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 -#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) -#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) -#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) -#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 -#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 - -#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 -#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) - -#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 -#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) - -#define IOMUXC_GPR2_BITMAP_SPWG 0 -#define IOMUXC_GPR2_BITMAP_JEIDA 1 - -#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 -#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) - -#define IOMUXC_GPR2_DATA_WIDTH_18 0 -#define IOMUXC_GPR2_DATA_WIDTH_24 1 - -#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 -#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) - -#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 -#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) - -#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 -#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) - -#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 -#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) - -#define IOMUXC_GPR2_MODE_DISABLED 0 -#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 -#define IOMUXC_GPR2_MODE_ENABLED_DI1 3 - -#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 -#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) - -#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 -#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) - -/* ECSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 cfg; - u32 intr; - u32 dma; - u32 stat; - u32 period; -}; - -/* - * CSPI register definitions - */ -#define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_MODE_MASK (0xf << 4) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 -#define SPI_MAX_NUM 4 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_PHA 0 /* SCLK phase control */ -#define MXC_CSPICON_POL 4 /* SCLK polarity */ -#define MXC_CSPICON_SSPOL 12 /* SS polarity */ -#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define MXC_SPI_BASE_ADDRESSES \ - ECSPI1_BASE_ADDR, \ - ECSPI2_BASE_ADDR, \ - ECSPI3_BASE_ADDR, \ - ECSPI4_BASE_ADDR -#else -#define MXC_SPI_BASE_ADDRESSES \ - ECSPI1_BASE_ADDR, \ - ECSPI2_BASE_ADDR, \ - ECSPI3_BASE_ADDR, \ - ECSPI4_BASE_ADDR, \ - ECSPI5_BASE_ADDR -#endif - -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[3]; - u32 sw_sticky; - u32 rsvd4[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd5[3]; - u32 crc_value; - u32 rsvd6[3]; - u32 version; - u32 rsvd7[0xdb]; - - /* fuse banks */ - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[0]; -}; - -struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 uid_low; - u32 rsvd1[3]; - u32 uid_high; - u32 rsvd2[3]; - u32 cfg2; - u32 rsvd3[3]; - u32 cfg3; - u32 rsvd4[3]; - u32 cfg4; - u32 rsvd5[3]; - u32 cfg5; - u32 rsvd6[3]; - u32 cfg6; - u32 rsvd7[3]; -}; - -struct fuse_bank1_regs { - u32 mem0; - u32 rsvd0[3]; - u32 mem1; - u32 rsvd1[3]; - u32 mem2; - u32 rsvd2[3]; - u32 mem3; - u32 rsvd3[3]; - u32 mem4; - u32 rsvd4[3]; - u32 ana0; - u32 rsvd5[3]; - u32 ana1; - u32 rsvd6[3]; - u32 ana2; - u32 rsvd7[3]; -}; - -struct fuse_bank4_regs { - u32 sjc_resp_low; - u32 rsvd0[3]; - u32 sjc_resp_high; - u32 rsvd1[3]; - u32 mac_addr0; - u32 rsvd2[3]; - u32 mac_addr1; - u32 rsvd3[3]; - u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ - u32 rsvd4[7]; - u32 gp1; - u32 rsvd5[3]; - u32 gp2; - u32 rsvd6[3]; -}; - -struct aipstz_regs { - u32 mprot0; - u32 mprot1; - u32 rsvd[0xe]; - u32 opacr0; - u32 opacr1; - u32 opacr2; - u32 opacr3; - u32 opacr4; -}; - -struct anatop_regs { - u32 pll_sys; /* 0x000 */ - u32 pll_sys_set; /* 0x004 */ - u32 pll_sys_clr; /* 0x008 */ - u32 pll_sys_tog; /* 0x00c */ - u32 usb1_pll_480_ctrl; /* 0x010 */ - u32 usb1_pll_480_ctrl_set; /* 0x014 */ - u32 usb1_pll_480_ctrl_clr; /* 0x018 */ - u32 usb1_pll_480_ctrl_tog; /* 0x01c */ - u32 usb2_pll_480_ctrl; /* 0x020 */ - u32 usb2_pll_480_ctrl_set; /* 0x024 */ - u32 usb2_pll_480_ctrl_clr; /* 0x028 */ - u32 usb2_pll_480_ctrl_tog; /* 0x02c */ - u32 pll_528; /* 0x030 */ - u32 pll_528_set; /* 0x034 */ - u32 pll_528_clr; /* 0x038 */ - u32 pll_528_tog; /* 0x03c */ - u32 pll_528_ss; /* 0x040 */ - u32 rsvd0[3]; - u32 pll_528_num; /* 0x050 */ - u32 rsvd1[3]; - u32 pll_528_denom; /* 0x060 */ - u32 rsvd2[3]; - u32 pll_audio; /* 0x070 */ - u32 pll_audio_set; /* 0x074 */ - u32 pll_audio_clr; /* 0x078 */ - u32 pll_audio_tog; /* 0x07c */ - u32 pll_audio_num; /* 0x080 */ - u32 rsvd3[3]; - u32 pll_audio_denom; /* 0x090 */ - u32 rsvd4[3]; - u32 pll_video; /* 0x0a0 */ - u32 pll_video_set; /* 0x0a4 */ - u32 pll_video_clr; /* 0x0a8 */ - u32 pll_video_tog; /* 0x0ac */ - u32 pll_video_num; /* 0x0b0 */ - u32 rsvd5[3]; - u32 pll_video_denom; /* 0x0c0 */ - u32 rsvd6[3]; - u32 pll_mlb; /* 0x0d0 */ - u32 pll_mlb_set; /* 0x0d4 */ - u32 pll_mlb_clr; /* 0x0d8 */ - u32 pll_mlb_tog; /* 0x0dc */ - u32 pll_enet; /* 0x0e0 */ - u32 pll_enet_set; /* 0x0e4 */ - u32 pll_enet_clr; /* 0x0e8 */ - u32 pll_enet_tog; /* 0x0ec */ - u32 pfd_480; /* 0x0f0 */ - u32 pfd_480_set; /* 0x0f4 */ - u32 pfd_480_clr; /* 0x0f8 */ - u32 pfd_480_tog; /* 0x0fc */ - u32 pfd_528; /* 0x100 */ - u32 pfd_528_set; /* 0x104 */ - u32 pfd_528_clr; /* 0x108 */ - u32 pfd_528_tog; /* 0x10c */ - u32 reg_1p1; /* 0x110 */ - u32 reg_1p1_set; /* 0x114 */ - u32 reg_1p1_clr; /* 0x118 */ - u32 reg_1p1_tog; /* 0x11c */ - u32 reg_3p0; /* 0x120 */ - u32 reg_3p0_set; /* 0x124 */ - u32 reg_3p0_clr; /* 0x128 */ - u32 reg_3p0_tog; /* 0x12c */ - u32 reg_2p5; /* 0x130 */ - u32 reg_2p5_set; /* 0x134 */ - u32 reg_2p5_clr; /* 0x138 */ - u32 reg_2p5_tog; /* 0x13c */ - u32 reg_core; /* 0x140 */ - u32 reg_core_set; /* 0x144 */ - u32 reg_core_clr; /* 0x148 */ - u32 reg_core_tog; /* 0x14c */ - u32 ana_misc0; /* 0x150 */ - u32 ana_misc0_set; /* 0x154 */ - u32 ana_misc0_clr; /* 0x158 */ - u32 ana_misc0_tog; /* 0x15c */ - u32 ana_misc1; /* 0x160 */ - u32 ana_misc1_set; /* 0x164 */ - u32 ana_misc1_clr; /* 0x168 */ - u32 ana_misc1_tog; /* 0x16c */ - u32 ana_misc2; /* 0x170 */ - u32 ana_misc2_set; /* 0x174 */ - u32 ana_misc2_clr; /* 0x178 */ - u32 ana_misc2_tog; /* 0x17c */ - u32 tempsense0; /* 0x180 */ - u32 tempsense0_set; /* 0x184 */ - u32 tempsense0_clr; /* 0x188 */ - u32 tempsense0_tog; /* 0x18c */ - u32 tempsense1; /* 0x190 */ - u32 tempsense1_set; /* 0x194 */ - u32 tempsense1_clr; /* 0x198 */ - u32 tempsense1_tog; /* 0x19c */ - u32 usb1_vbus_detect; /* 0x1a0 */ - u32 usb1_vbus_detect_set; /* 0x1a4 */ - u32 usb1_vbus_detect_clr; /* 0x1a8 */ - u32 usb1_vbus_detect_tog; /* 0x1ac */ - u32 usb1_chrg_detect; /* 0x1b0 */ - u32 usb1_chrg_detect_set; /* 0x1b4 */ - u32 usb1_chrg_detect_clr; /* 0x1b8 */ - u32 usb1_chrg_detect_tog; /* 0x1bc */ - u32 usb1_vbus_det_stat; /* 0x1c0 */ - u32 usb1_vbus_det_stat_set; /* 0x1c4 */ - u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ - u32 usb1_vbus_det_stat_tog; /* 0x1cc */ - u32 usb1_chrg_det_stat; /* 0x1d0 */ - u32 usb1_chrg_det_stat_set; /* 0x1d4 */ - u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ - u32 usb1_chrg_det_stat_tog; /* 0x1dc */ - u32 usb1_loopback; /* 0x1e0 */ - u32 usb1_loopback_set; /* 0x1e4 */ - u32 usb1_loopback_clr; /* 0x1e8 */ - u32 usb1_loopback_tog; /* 0x1ec */ - u32 usb1_misc; /* 0x1f0 */ - u32 usb1_misc_set; /* 0x1f4 */ - u32 usb1_misc_clr; /* 0x1f8 */ - u32 usb1_misc_tog; /* 0x1fc */ - u32 usb2_vbus_detect; /* 0x200 */ - u32 usb2_vbus_detect_set; /* 0x204 */ - u32 usb2_vbus_detect_clr; /* 0x208 */ - u32 usb2_vbus_detect_tog; /* 0x20c */ - u32 usb2_chrg_detect; /* 0x210 */ - u32 usb2_chrg_detect_set; /* 0x214 */ - u32 usb2_chrg_detect_clr; /* 0x218 */ - u32 usb2_chrg_detect_tog; /* 0x21c */ - u32 usb2_vbus_det_stat; /* 0x220 */ - u32 usb2_vbus_det_stat_set; /* 0x224 */ - u32 usb2_vbus_det_stat_clr; /* 0x228 */ - u32 usb2_vbus_det_stat_tog; /* 0x22c */ - u32 usb2_chrg_det_stat; /* 0x230 */ - u32 usb2_chrg_det_stat_set; /* 0x234 */ - u32 usb2_chrg_det_stat_clr; /* 0x238 */ - u32 usb2_chrg_det_stat_tog; /* 0x23c */ - u32 usb2_loopback; /* 0x240 */ - u32 usb2_loopback_set; /* 0x244 */ - u32 usb2_loopback_clr; /* 0x248 */ - u32 usb2_loopback_tog; /* 0x24c */ - u32 usb2_misc; /* 0x250 */ - u32 usb2_misc_set; /* 0x254 */ - u32 usb2_misc_clr; /* 0x258 */ - u32 usb2_misc_tog; /* 0x25c */ - u32 digprog; /* 0x260 */ - u32 reserved1[7]; - u32 digprog_sololite; /* 0x280 */ -}; - -#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) -#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) -#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) -#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) -#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) -#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) - -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Miscellaneous Control */ -}; - -#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) -#define PWMCR_DOZEEN (1 << 24) -#define PWMCR_WAITEN (1 << 23) -#define PWMCR_DBGEN (1 << 22) -#define PWMCR_CLKSRC_IPG_HIGH (2 << 16) -#define PWMCR_CLKSRC_IPG (1 << 16) -#define PWMCR_EN (1 << 0) - -struct pwm_regs { - u32 cr; - u32 sr; - u32 ir; - u32 sar; - u32 pr; - u32 cnr; -}; - -/* - * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB - * If boot from the other mode, USB0_PWD will keep reset value - */ -#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) - -#endif /* __ASSEMBLER__*/ -#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h deleted file mode 100644 index bea0bbb..0000000 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __ASM_ARCH_IOMUX_H__ -#define __ASM_ARCH_IOMUX_H__ - -#define MX6_IOMUXC_GPR4 0x020e0010 -#define MX6_IOMUXC_GPR6 0x020e0018 -#define MX6_IOMUXC_GPR7 0x020e001c - -/* - * IOMUXC_GPR1 bit fields - */ -#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) -#define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) -#define IOMUXC_GPR1_OTG_ID_MASK (1<<13) -#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) -#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) - -#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29) - -/* - * IOMUXC_GPR5 bit fields - */ -#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) -#define IOMUXC_GPR5_PCIE_PERST (1 << 18) - -/* - * IOMUXC_GPR8 bit fields - */ -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 -#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) -#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 -#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) -#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 - -/* - * IOMUXC_GPR12 bit fields - */ -#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0) -#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) -#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) -#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) -#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) -#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) -#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) - -/* - * IOMUXC_GPR13 bit fields - */ -#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) -#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) -#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) -#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) -#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) -#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) -#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 -#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) -#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15) -#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14) -#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11) -#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7) -#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) -#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) - -#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) -#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) -#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ - | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) - -#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17) -#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13) -#define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \ - | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK) - -#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18) -#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14) -#define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \ - | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK) - -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) - -#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) - -#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) -#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) - -#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14) -#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14) - -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) - -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) - -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) - -#define IOMUXC_GPR13_SATA_PHY_1_FAST 0 -#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 -#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2 - -#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \ - |IOMUXC_GPR13_SATA_PHY_7_MASK \ - |IOMUXC_GPR13_SATA_PHY_6_MASK \ - |IOMUXC_GPR13_SATA_SPEED_MASK \ - |IOMUXC_GPR13_SATA_PHY_5_MASK \ - |IOMUXC_GPR13_SATA_PHY_4_MASK \ - |IOMUXC_GPR13_SATA_PHY_3_MASK \ - |IOMUXC_GPR13_SATA_PHY_2_MASK \ - |IOMUXC_GPR13_SATA_PHY_1_MASK) - -/* - * Setup RGMII voltage levels on iMX6 SoC - the - * - * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register - * - * 1P2V_IO - USB_HSIC, MIPI_HSI - * 1P5V_IO - ENET pins - */ -#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x020e0790 -#define DDR_SEL_1P2V_IO (0x2 << 18) -#define DDR_SEL_1P5V_IO (0x3 << 18) - -#endif /* __ASM_ARCH_IOMUX_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/litesom.h b/arch/arm/include/asm/arch-mx6/litesom.h deleted file mode 100644 index fcdfcab..0000000 --- a/arch/arm/include/asm/arch-mx6/litesom.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Grinn - */ - -#ifndef __ARCH_ARM_MX6UL_LITESOM_H__ -#define __ARCH_ARM_MX6UL_LITESOM_H__ - -int litesom_mmc_init(bd_t *bis); - -#ifdef CONFIG_SPL_BUILD -void litesom_init_f(void); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h deleted file mode 100644 index e0fadb9..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ /dev/null @@ -1,530 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices Inc. - */ -#ifndef __ASM_ARCH_MX6_DDR_H__ -#define __ASM_ARCH_MX6_DDR_H__ - -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_MX6Q -#include "mx6q-ddr.h" -#else -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -#include "mx6dl-ddr.h" -#else -#ifdef CONFIG_MX6SX -#include "mx6sx-ddr.h" -#else -#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#include "mx6ul-ddr.h" -#else -#ifdef CONFIG_MX6SL -#include "mx6sl-ddr.h" -#else -#error "Please select cpu" -#endif /* CONFIG_MX6SL */ -#endif /* CONFIG_MX6UL */ -#endif /* CONFIG_MX6SX */ -#endif /* CONFIG_MX6DL or CONFIG_MX6S */ -#endif /* CONFIG_MX6Q */ -#else - -enum { - DDR_TYPE_DDR3, - DDR_TYPE_LPDDR2, -}; - -/* MMDC P0/P1 Registers */ -struct mmdc_p_regs { - u32 mdctl; - u32 mdpdc; - u32 mdotc; - u32 mdcfg0; - u32 mdcfg1; - u32 mdcfg2; - u32 mdmisc; - u32 mdscr; - u32 mdref; - u32 res1[2]; - u32 mdrwd; - u32 mdor; - u32 mdmrr; - u32 mdcfg3lp; - u32 mdmr4; - u32 mdasp; - u32 res2[239]; - u32 maarcr; - u32 mapsr; - u32 maexidr0; - u32 maexidr1; - u32 madpcr0; - u32 madpcr1; - u32 madpsr0; - u32 madpsr1; - u32 madpsr2; - u32 madpsr3; - u32 madpsr4; - u32 madpsr5; - u32 masbs0; - u32 masbs1; - u32 res3[2]; - u32 magenp; - u32 res4[239]; - u32 mpzqhwctrl; - u32 mpzqswctrl; - u32 mpwlgcr; - u32 mpwldectrl0; - u32 mpwldectrl1; - u32 mpwldlst; - u32 mpodtctrl; - u32 mprddqby0dl; - u32 mprddqby1dl; - u32 mprddqby2dl; - u32 mprddqby3dl; - u32 mpwrdqby0dl; - u32 mpwrdqby1dl; - u32 mpwrdqby2dl; - u32 mpwrdqby3dl; - u32 mpdgctrl0; - u32 mpdgctrl1; - u32 mpdgdlst0; - u32 mprddlctl; - u32 mprddlst; - u32 mpwrdlctl; - u32 mpwrdlst; - u32 mpsdctrl; - u32 mpzqlp2ctl; - u32 mprddlhwctl; - u32 mpwrdlhwctl; - u32 mprddlhwst0; - u32 mprddlhwst1; - u32 mpwrdlhwst0; - u32 mpwrdlhwst1; - u32 mpwlhwerr; - u32 mpdghwst0; - u32 mpdghwst1; - u32 mpdghwst2; - u32 mpdghwst3; - u32 mppdcmpr1; - u32 mppdcmpr2; - u32 mpswdar0; - u32 mpswdrdr0; - u32 mpswdrdr1; - u32 mpswdrdr2; - u32 mpswdrdr3; - u32 mpswdrdr4; - u32 mpswdrdr5; - u32 mpswdrdr6; - u32 mpswdrdr7; - u32 mpmur0; - u32 mpwrcadl; - u32 mpdccr; -}; - -#define MX6SL_IOM_DDR_BASE 0x020e0300 -struct mx6sl_iomux_ddr_regs { - u32 dram_cas; - u32 dram_cs0_b; - u32 dram_cs1_b; - u32 dram_dqm0; - u32 dram_dqm1; - u32 dram_dqm2; - u32 dram_dqm3; - u32 dram_ras; - u32 dram_reset; - u32 dram_sdba0; - u32 dram_sdba1; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdcke1; - u32 dram_sdclk_0; - u32 dram_odt0; - u32 dram_odt1; - u32 dram_sdqs0; - u32 dram_sdqs1; - u32 dram_sdqs2; - u32 dram_sdqs3; - u32 dram_sdwe_b; -}; - -#define MX6SL_IOM_GRP_BASE 0x020e0500 -struct mx6sl_iomux_grp_regs { - u32 res1[43]; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 grp_ddrpke; - u32 grp_ddrpk; - u32 grp_ddrhys; - u32 grp_ddrmode; - u32 grp_b0ds; - u32 grp_ctlds; - u32 grp_b1ds; - u32 grp_ddr_type; - u32 grp_b2ds; - u32 grp_b3ds; -}; - -#define MX6UL_IOM_DDR_BASE 0x020e0200 -struct mx6ul_iomux_ddr_regs { - u32 res1[17]; - u32 dram_dqm0; - u32 dram_dqm1; - u32 dram_ras; - u32 dram_cas; - u32 dram_cs0; - u32 dram_cs1; - u32 dram_sdwe_b; - u32 dram_odt0; - u32 dram_odt1; - u32 dram_sdba0; - u32 dram_sdba1; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdcke1; - u32 dram_sdclk_0; - u32 dram_sdqs0; - u32 dram_sdqs1; - u32 dram_reset; -}; - -#define MX6UL_IOM_GRP_BASE 0x020e0400 -struct mx6ul_iomux_grp_regs { - u32 res1[36]; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 grp_b0ds; - u32 grp_ddrpk; - u32 grp_ctlds; - u32 grp_b1ds; - u32 grp_ddrhys; - u32 grp_ddrpke; - u32 grp_ddrmode; - u32 grp_ddr_type; -}; - -#define MX6SX_IOM_DDR_BASE 0x020e0200 -struct mx6sx_iomux_ddr_regs { - u32 res1[59]; - u32 dram_dqm0; - u32 dram_dqm1; - u32 dram_dqm2; - u32 dram_dqm3; - u32 dram_ras; - u32 dram_cas; - u32 res2[2]; - u32 dram_sdwe_b; - u32 dram_odt0; - u32 dram_odt1; - u32 dram_sdba0; - u32 dram_sdba1; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdcke1; - u32 dram_sdclk_0; - u32 dram_sdqs0; - u32 dram_sdqs1; - u32 dram_sdqs2; - u32 dram_sdqs3; - u32 dram_reset; -}; - -#define MX6SX_IOM_GRP_BASE 0x020e0500 -struct mx6sx_iomux_grp_regs { - u32 res1[61]; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 grp_ddrpke; - u32 grp_ddrpk; - u32 grp_ddrhys; - u32 grp_ddrmode; - u32 grp_b0ds; - u32 grp_b1ds; - u32 grp_ctlds; - u32 grp_ddr_type; - u32 grp_b2ds; - u32 grp_b3ds; -}; - -/* - * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) - */ -#define MX6DQ_IOM_DDR_BASE 0x020e0500 -struct mx6dq_iomux_ddr_regs { - u32 res1[3]; - u32 dram_sdqs5; - u32 dram_dqm5; - u32 dram_dqm4; - u32 dram_sdqs4; - u32 dram_sdqs3; - u32 dram_dqm3; - u32 dram_sdqs2; - u32 dram_dqm2; - u32 res2[16]; - u32 dram_cas; - u32 res3[2]; - u32 dram_ras; - u32 dram_reset; - u32 res4[2]; - u32 dram_sdclk_0; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdclk_1; - u32 dram_sdcke1; - u32 dram_sdodt0; - u32 dram_sdodt1; - u32 res5; - u32 dram_sdqs0; - u32 dram_dqm0; - u32 dram_sdqs1; - u32 dram_dqm1; - u32 dram_sdqs6; - u32 dram_dqm6; - u32 dram_sdqs7; - u32 dram_dqm7; -}; - -#define MX6DQ_IOM_GRP_BASE 0x020e0700 -struct mx6dq_iomux_grp_regs { - u32 res1[18]; - u32 grp_b7ds; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 res2; - u32 grp_ddrpke; - u32 res3[6]; - u32 grp_ddrmode; - u32 res4[3]; - u32 grp_b0ds; - u32 grp_b1ds; - u32 grp_ctlds; - u32 res5; - u32 grp_b2ds; - u32 grp_ddr_type; - u32 grp_b3ds; - u32 grp_b4ds; - u32 grp_b5ds; - u32 grp_b6ds; -}; - -#define MX6SDL_IOM_DDR_BASE 0x020e0400 -struct mx6sdl_iomux_ddr_regs { - u32 res1[25]; - u32 dram_cas; - u32 res2[2]; - u32 dram_dqm0; - u32 dram_dqm1; - u32 dram_dqm2; - u32 dram_dqm3; - u32 dram_dqm4; - u32 dram_dqm5; - u32 dram_dqm6; - u32 dram_dqm7; - u32 dram_ras; - u32 dram_reset; - u32 res3[2]; - u32 dram_sdba2; - u32 dram_sdcke0; - u32 dram_sdcke1; - u32 dram_sdclk_0; - u32 dram_sdclk_1; - u32 dram_sdodt0; - u32 dram_sdodt1; - u32 dram_sdqs0; - u32 dram_sdqs1; - u32 dram_sdqs2; - u32 dram_sdqs3; - u32 dram_sdqs4; - u32 dram_sdqs5; - u32 dram_sdqs6; - u32 dram_sdqs7; -}; - -#define MX6SDL_IOM_GRP_BASE 0x020e0700 -struct mx6sdl_iomux_grp_regs { - u32 res1[18]; - u32 grp_b7ds; - u32 grp_addds; - u32 grp_ddrmode_ctl; - u32 grp_ddrpke; - u32 res2[2]; - u32 grp_ddrmode; - u32 grp_b0ds; - u32 res3; - u32 grp_ctlds; - u32 grp_b1ds; - u32 grp_ddr_type; - u32 grp_b2ds; - u32 grp_b3ds; - u32 grp_b4ds; - u32 grp_b5ds; - u32 res4; - u32 grp_b6ds; -}; - -/* Device Information: Varies per DDR3 part number and speed grade */ -struct mx6_ddr3_cfg { - u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */ - u8 density; /* chip density (Gb) (1,2,4,8) */ - u8 width; /* bus width (bits) (4,8,16) */ - u8 banks; /* number of banks */ - u8 rowaddr; /* row address bits (11-16)*/ - u8 coladdr; /* col address bits (9-12) */ - u8 pagesz; /* page size (K) (1-2) */ - u16 trcd; /* tRCD=tRP=CL (ns*100) */ - u16 trcmin; /* tRC min (ns*100) */ - u16 trasmin; /* tRAS min (ns*100) */ - u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ -}; - -/* Device Information: Varies per LPDDR2 part number and speed grade */ -struct mx6_lpddr2_cfg { - u16 mem_speed; /* ie 800 for LPDDR2-800 */ - u8 density; /* chip density (Gb) (1,2,4,8) */ - u8 width; /* bus width (bits) (4,8,16) */ - u8 banks; /* number of banks */ - u8 rowaddr; /* row address bits (11-16)*/ - u8 coladdr; /* col address bits (9-12) */ - u16 trcd_lp; - u16 trppb_lp; - u16 trpab_lp; - u16 trcmin; /* tRC min (ns*100) */ - u16 trasmin; /* tRAS min (ns*100) */ -}; - -/* System Information: Varies per board design, layout, and term choices */ -struct mx6_ddr_sysinfo { - u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ - u8 cs_density; /* density per chip select (Gb) */ - u8 ncs; /* number chip selects used (1|2) */ - char cs1_mirror;/* enable address mirror (0|1) */ - char bi_on; /* Bank interleaving enable */ - u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */ - u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */ - u8 ralat; /* Read Additional Latency (0-7) */ - u8 walat; /* Write Additional Latency (0-3) */ - u8 mif3_mode; /* Command prediction working mode */ - u8 rst_to_cke; /* Time from SDE enable to CKE rise */ - u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ - u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ - u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */ - u8 refsel; /* REF_SEL field of register MDREF */ - u8 refr; /* REFR field of register MDREF */ -}; - -/* - * Board specific calibration: - * This includes write leveling calibration values as well as DQS gating - * and read/write delays. These values are board/layout/device specific. - * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2 - * (DOC-96412) to determine these values over a range of boards and - * temperatures. - */ -struct mx6_mmdc_calibration { - /* write leveling calibration */ - u32 p0_mpwldectrl0; - u32 p0_mpwldectrl1; - u32 p1_mpwldectrl0; - u32 p1_mpwldectrl1; - /* read DQS gating */ - u32 p0_mpdgctrl0; - u32 p0_mpdgctrl1; - u32 p1_mpdgctrl0; - u32 p1_mpdgctrl1; - /* read delay */ - u32 p0_mprddlctl; - u32 p1_mprddlctl; - /* write delay */ - u32 p0_mpwrdlctl; - u32 p1_mpwrdlctl; - /* lpddr2 zq hw calibration */ - u32 mpzqlp2ctl; -}; - -/* configure iomux (pinctl/padctl) */ -void mx6dq_dram_iocfg(unsigned width, - const struct mx6dq_iomux_ddr_regs *, - const struct mx6dq_iomux_grp_regs *); -void mx6sdl_dram_iocfg(unsigned width, - const struct mx6sdl_iomux_ddr_regs *, - const struct mx6sdl_iomux_grp_regs *); -void mx6sx_dram_iocfg(unsigned width, - const struct mx6sx_iomux_ddr_regs *, - const struct mx6sx_iomux_grp_regs *); -void mx6ul_dram_iocfg(unsigned width, - const struct mx6ul_iomux_ddr_regs *, - const struct mx6ul_iomux_grp_regs *); -void mx6sl_dram_iocfg(unsigned width, - const struct mx6sl_iomux_ddr_regs *, - const struct mx6sl_iomux_grp_regs *); - -#if defined(CONFIG_MX6_DDRCAL) -int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo); -int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo); -void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo, - struct mx6_mmdc_calibration *calib); -#endif - -/* configure mx6 mmdc registers */ -void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, - const struct mx6_mmdc_calibration *, - const void *); - -#endif /* CONFIG_SPL_BUILD */ - -#define MX6_MMDC_P0_MDCTL 0x021b0000 -#define MX6_MMDC_P0_MDPDC 0x021b0004 -#define MX6_MMDC_P0_MDOTC 0x021b0008 -#define MX6_MMDC_P0_MDCFG0 0x021b000c -#define MX6_MMDC_P0_MDCFG1 0x021b0010 -#define MX6_MMDC_P0_MDCFG2 0x021b0014 -#define MX6_MMDC_P0_MDMISC 0x021b0018 -#define MX6_MMDC_P0_MDSCR 0x021b001c -#define MX6_MMDC_P0_MDREF 0x021b0020 -#define MX6_MMDC_P0_MDRWD 0x021b002c -#define MX6_MMDC_P0_MDOR 0x021b0030 -#define MX6_MMDC_P0_MDASP 0x021b0040 -#define MX6_MMDC_P0_MAPSR 0x021b0404 -#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 -#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c -#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810 -#define MX6_MMDC_P0_MPODTCTRL 0x021b0818 -#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c -#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820 -#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824 -#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828 -#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c -#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 -#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 -#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 -#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C -#define MX6_MMDC_P0_MPMUR0 0x021b08b8 - -#define MX6_MMDC_P1_MDCTL 0x021b4000 -#define MX6_MMDC_P1_MDPDC 0x021b4004 -#define MX6_MMDC_P1_MDOTC 0x021b4008 -#define MX6_MMDC_P1_MDCFG0 0x021b400c -#define MX6_MMDC_P1_MDCFG1 0x021b4010 -#define MX6_MMDC_P1_MDCFG2 0x021b4014 -#define MX6_MMDC_P1_MDMISC 0x021b4018 -#define MX6_MMDC_P1_MDSCR 0x021b401c -#define MX6_MMDC_P1_MDREF 0x021b4020 -#define MX6_MMDC_P1_MDRWD 0x021b402c -#define MX6_MMDC_P1_MDOR 0x021b4030 -#define MX6_MMDC_P1_MDASP 0x021b4040 -#define MX6_MMDC_P1_MAPSR 0x021b4404 -#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800 -#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c -#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810 -#define MX6_MMDC_P1_MPODTCTRL 0x021b4818 -#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c -#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820 -#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824 -#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828 -#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c -#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 -#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 -#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 -#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C -#define MX6_MMDC_P1_MPMUR0 0x021b48b8 - -#endif /*__ASM_ARCH_MX6_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h deleted file mode 100644 index 9a99a6b..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices Inc. - */ -#ifndef __ASM_ARCH_MX6_PINS_H__ -#define __ASM_ARCH_MX6_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ - prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc) - -#ifdef CONFIG_MX6QDL -enum { -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6q_pins.h" -#undef MX6_PAD_DECL -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6dl_pins.h" -}; -#elif defined(CONFIG_MX6Q) -enum { -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6q_pins.h" -}; -#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -enum { -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6dl_pins.h" -}; -#elif defined(CONFIG_MX6SLL) -#include "mx6sll_pins.h" -#elif defined(CONFIG_MX6SL) -#include "mx6sl_pins.h" -#elif defined(CONFIG_MX6SX) -#include "mx6sx_pins.h" -#elif defined(CONFIG_MX6ULL) -#include "mx6ull_pins.h" -#elif defined(CONFIG_MX6UL) -#include "mx6ul_pins.h" -#else -#error "Please select cpu" -#endif /* CONFIG_MX6Q */ - -#endif /*__ASM_ARCH_MX6_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S deleted file mode 100644 index 7e61d22..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6_plugin.S +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include <config.h> - -#ifdef CONFIG_ROM_UNIFIED_SECTIONS -#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 -#else -#define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0 -#define ROM_VERSION_OFFSET 0x48 -#endif -#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4 -#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4 -#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 -#define ROM_VERSION_TO10 0x10 -#define ROM_VERSION_TO12 0x12 -#define ROM_VERSION_TO15 0x15 - -plugin_start: - - push {r0-r4, lr} - - imx6_ddr_setting - imx6_clock_gating - imx6_qos_setting - -/* - * The following is to fill in those arguments for this ROM function - * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) - * This function is used to copy data from the storage media into DDR. - * start - Initial (possibly partial) image load address on entry. - * Final image load address on exit. - * bytes - Initial (possibly partial) image size on entry. - * Final image size on exit. - * boot_data - Initial @ref ivt Boot Data load address. - */ - adr r0, boot_data2 - adr r1, image_len2 - adr r2, boot_data2 - -#ifdef CONFIG_NOR_BOOT -#ifdef CONFIG_MX6SX - ldr r3, =ROM_VERSION_OFFSET - ldr r4, [r3] - cmp r4, #ROM_VERSION_TO10 - bgt before_calling_rom___pu_irom_hwcnfg_setup - ldr r3, =0x00900b00 - ldr r4, =0x50000000 - str r4, [r3, #0x5c] -#else - ldr r3, =0x00900800 - ldr r4, =0x08000000 - str r4, [r3, #0xc0] -#endif -#endif - -/* - * check the _pu_irom_api_table for the address - */ -before_calling_rom___pu_irom_hwcnfg_setup: - ldr r3, =ROM_VERSION_OFFSET - ldr r4, [r3] -#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL) - ldr r3, =ROM_VERSION_TO12 - cmp r4, r3 - ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 - ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY -#elif defined(CONFIG_MX6Q) - ldr r3, =ROM_VERSION_TO15 - cmp r4, r3 - ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 - ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY -#else - ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY -#endif - ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] - blx r4 -after_calling_rom___pu_irom_hwcnfg_setup: - -/* - * ROM_API_HWCNFG_SETUP function enables MMU & Caches. - * Thus disable MMU & Caches. - */ - - mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/ - ands r0, r0, #0x1 /* check if MMU is enabled */ - beq mmu_disable_notreq /* exit if MMU is already disabled */ - - /* Disable caches, MMU */ - mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */ - bic r0, r0, #(1 << 2) /* disable D Cache */ - bic r0, r0, #0x1 /* clear bit 0 ; MMU off */ - - bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */ - bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */ - /* check enabled. */ - mcr p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */ - mov r0, r0 - mov r0, r0 - mov r0, r0 - mov r0, r0 - -mmu_disable_notreq: - NOP - -/* To return to ROM from plugin, we need to fill in these argument. - * Here is what need to do: - * Need to construct the paramters for this function before return to ROM: - * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) - */ - pop {r0-r4, lr} - push {r5} - ldr r5, boot_data2 - str r5, [r0] - ldr r5, image_len2 - str r5, [r1] - ldr r5, second_ivt_offset - str r5, [r2] - mov r0, #1 - pop {r5} - - /* return back to ROM code */ - bx lr - -/* make the following data right in the end of the output*/ -.ltorg - -#if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)) -#define FLASH_OFFSET 0x1000 -#else -#define FLASH_OFFSET 0x400 -#endif - -/* - * second_ivt_offset is the offset from the "second_ivt_header" to - * "image_copy_start", which involves FLASH_OFFSET, plus the first - * ivt_header, the plugin code size itself recorded by "ivt2_header" - */ - -second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) - -/* - * The following is the second IVT header plus the second boot data - */ -ivt2_header: .long 0x0 -app2_code_jump_v: .long 0x0 -reserv3: .long 0x0 -dcd2_ptr: .long 0x0 -boot_data2_ptr: .long 0x0 -self_ptr2: .long 0x0 -app_code_csf2: .long 0x0 -reserv4: .long 0x0 -boot_data2: .long 0x0 -image_len2: .long 0x0 -plugin2: .long 0x0 diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h deleted file mode 100644 index 2b2821d..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices Inc. - */ -#ifndef __ASM_ARCH_MX6DLS_DDR_H__ -#define __ASM_ARCH_MX6DLS_DDR_H__ - -#ifndef CONFIG_MX6DL -#ifndef CONFIG_MX6S -#error "wrong CPU" -#endif -#endif - -#define MX6_IOM_DRAM_DQM0 0x020e0470 -#define MX6_IOM_DRAM_DQM1 0x020e0474 -#define MX6_IOM_DRAM_DQM2 0x020e0478 -#define MX6_IOM_DRAM_DQM3 0x020e047c -#define MX6_IOM_DRAM_DQM4 0x020e0480 -#define MX6_IOM_DRAM_DQM5 0x020e0484 -#define MX6_IOM_DRAM_DQM6 0x020e0488 -#define MX6_IOM_DRAM_DQM7 0x020e048c - -#define MX6_IOM_DRAM_CAS 0x020e0464 -#define MX6_IOM_DRAM_RAS 0x020e0490 -#define MX6_IOM_DRAM_RESET 0x020e0494 -#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac -#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0 -#define MX6_IOM_DRAM_SDBA2 0x020e04a0 -#define MX6_IOM_DRAM_SDCKE0 0x020e04a4 -#define MX6_IOM_DRAM_SDCKE1 0x020e04a8 -#define MX6_IOM_DRAM_SDODT0 0x020e04b4 -#define MX6_IOM_DRAM_SDODT1 0x020e04b8 - -#define MX6_IOM_DRAM_SDQS0 0x020e04bc -#define MX6_IOM_DRAM_SDQS1 0x020e04c0 -#define MX6_IOM_DRAM_SDQS2 0x020e04c4 -#define MX6_IOM_DRAM_SDQS3 0x020e04c8 -#define MX6_IOM_DRAM_SDQS4 0x020e04cc -#define MX6_IOM_DRAM_SDQS5 0x020e04d0 -#define MX6_IOM_DRAM_SDQS6 0x020e04d4 -#define MX6_IOM_DRAM_SDQS7 0x020e04d8 - -#define MX6_IOM_GRP_B0DS 0x020e0764 -#define MX6_IOM_GRP_B1DS 0x020e0770 -#define MX6_IOM_GRP_B2DS 0x020e0778 -#define MX6_IOM_GRP_B3DS 0x020e077c -#define MX6_IOM_GRP_B4DS 0x020e0780 -#define MX6_IOM_GRP_B5DS 0x020e0784 -#define MX6_IOM_GRP_B6DS 0x020e078c -#define MX6_IOM_GRP_B7DS 0x020e0748 -#define MX6_IOM_GRP_ADDDS 0x020e074c -#define MX6_IOM_DDRMODE_CTL 0x020e0750 -#define MX6_IOM_GRP_DDRPKE 0x020e0754 -#define MX6_IOM_GRP_DDRMODE 0x020e0760 -#define MX6_IOM_GRP_CTLDS 0x020e076c -#define MX6_IOM_GRP_DDR_TYPE 0x020e0774 - -#endif /*__ASM_ARCH_MX6S_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h deleted file mode 100644 index c207a75..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ /dev/null @@ -1,1079 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__ -#define __ASM_ARCH_MX6_MX6DL_PINS_H__ - -MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0360, 0x004C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0360, 0x004C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0360, 0x004C, 2, 0x07F8, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0360, 0x004C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0360, 0x004C, 3, 0x08FC, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0360, 0x004C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0360, 0x004C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0364, 0x0050, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0364, 0x0050, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0364, 0x0050, 2, 0x0800, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0364, 0x0050, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0364, 0x0050, 3, 0x08FC, 1, 0) -MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0364, 0x0050, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0364, 0x0050, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0368, 0x0054, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0368, 0x0054, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0368, 0x0054, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0368, 0x0054, 3, 0x0914, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0368, 0x0054, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0368, 0x0054, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x036C, 0x0058, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x036C, 0x0058, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x036C, 0x0058, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x036C, 0x0058, 3, 0x0914, 1, 0) -MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x036C, 0x0058, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x036C, 0x0058, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0370, 0x005C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0370, 0x005C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0370, 0x005C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0370, 0x005C, 3, 0x091C, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0370, 0x005C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0370, 0x005C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0374, 0x0060, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0374, 0x0060, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0374, 0x0060, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0374, 0x0060, 3, 0x091C, 1, 0) -MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0374, 0x0060, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0374, 0x0060, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0378, 0x0064, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0378, 0x0064, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0378, 0x0064, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0378, 0x0064, 3, 0x0910, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0378, 0x0064, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0378, 0x0064, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x037C, 0x0068, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x037C, 0x0068, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x037C, 0x0068, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x037C, 0x0068, 3, 0x0910, 1, 0) -MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x037C, 0x0068, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x037C, 0x0068, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0380, 0x006C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0380, 0x006C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0380, 0x006C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0380, 0x006C, 3, 0x0918, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0380, 0x006C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0380, 0x006C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0384, 0x0070, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0384, 0x0070, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0384, 0x0070, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0384, 0x0070, 3, 0x0918, 1, 0) -MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0384, 0x0070, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0388, 0x0074, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0388, 0x0074, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0388, 0x0074, 2, 0x07D8, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0388, 0x0074, 3, 0x08C0, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0388, 0x0074, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0388, 0x0074, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0388, 0x0074, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x038C, 0x0078, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x038C, 0x0078, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x038C, 0x0078, 2, 0x07E0, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x038C, 0x0078, 3, 0x08CC, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x038C, 0x0078, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x038C, 0x0078, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x038C, 0x0078, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0390, 0x007C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0390, 0x007C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0390, 0x007C, 2, 0x07DC, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0390, 0x007C, 3, 0x08C4, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0390, 0x007C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0390, 0x007C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0390, 0x007C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0394, 0x0080, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0394, 0x0080, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0394, 0x0080, 2, 0x07E4, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0394, 0x0080, 3, 0x08D0, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0394, 0x0080, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0394, 0x0080, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0394, 0x0080, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0398, 0x0084, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0398, 0x0084, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0398, 0x0084, 2, 0x07F4, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0398, 0x0084, 3, 0x08C8, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0398, 0x0084, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0398, 0x0084, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x039C, 0x0088, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x039C, 0x0088, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x039C, 0x0088, 2, 0x07FC, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x039C, 0x0088, 3, 0x08D4, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x039C, 0x0088, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x039C, 0x0088, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x03A0, 0x008C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x03A0, 0x008C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x03A0, 0x008C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x03A0, 0x008C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x03A4, 0x0090, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x03A4, 0x0090, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x03A4, 0x0090, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x03A4, 0x0090, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x03A8, 0x0094, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x03A8, 0x0094, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x03A8, 0x0094, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x03AC, 0x0098, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x03AC, 0x0098, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x03AC, 0x0098, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x03AC, 0x0098, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK, 0x03B0, 0x009C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x03B0, 0x009C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN, 0x03B0, 0x009C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE, 0x03B4, 0x00A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__LCD_RD_E, 0x03B4, 0x00A0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC, 0x03B8, 0x00A4, 1, 0x08D8, 0, 0) -MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__LCD_RS, 0x03B8, 0x00A4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__LCD_CS, 0x03BC, 0x00A8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN4__LCD_BUSY, 0x03C0, 0x00AC, 1, 0x08D8, 1, 0) -MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x03C0, 0x00AC, 3, 0x092C, 0, 0) -MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__LCD_RESET, 0x03C0, 0x00AC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13, 0x03D8, 0x00C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x03D8, 0x00C4, 3, 0x07BC, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x03DC, 0x00C8, 3, 0x07B8, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x03E0, 0x00CC, 2, 0x07E8, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x03E0, 0x00CC, 3, 0x0804, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x03E4, 0x00D0, 2, 0x07FC, 1, 0) -MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x03E4, 0x00D0, 3, 0x07C0, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x03E4, 0x00D0, 4, 0x08E8, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x03E8, 0x00D4, 2, 0x07F8, 1, 0) -MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x03E8, 0x00D4, 3, 0x07B4, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x03E8, 0x00D4, 4, 0x08EC, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x03EC, 0x00D8, 2, 0x0800, 1, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x03EC, 0x00D8, 3, 0x07C4, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x03EC, 0x00D8, 4, 0x07A4, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x03F0, 0x00DC, 2, 0x07F4, 1, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 0x07B0, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x03F8, 0x00E4, 2, 0x07D8, 1, 0) -MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x03F8, 0x00E4, 3, 0x07A8, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x03FC, 0x00E8, 2, 0x07E0, 1, 0) -MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x03FC, 0x00E8, 3, 0x079C, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22, 0x0400, 0x00EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x0400, 0x00EC, 2, 0x07DC, 1, 0) -MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x0400, 0x00EC, 3, 0x07AC, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x0400, 0x00EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23, 0x0404, 0x00F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x0404, 0x00F0, 2, 0x07E4, 1, 0) -MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x0404, 0x00F0, 3, 0x0798, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x0404, 0x00F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03, 0x0408, 0x00F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0408, 0x00F4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0408, 0x00F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04, 0x040C, 0x00F8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x040C, 0x00F8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x040C, 0x00F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05, 0x0410, 0x00FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0410, 0x00FC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0410, 0x00FC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0410, 0x00FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06, 0x0414, 0x0100, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x0414, 0x0100, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x0414, 0x0100, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x0414, 0x0100, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07, 0x0418, 0x0104, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x0418, 0x0104, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x0418, 0x0104, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08, 0x041C, 0x0108, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x041C, 0x0108, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x041C, 0x0108, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x041C, 0x0108, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09, 0x0420, 0x010C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x0420, 0x010C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x0420, 0x010C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x0420, 0x010C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x04E0, 0x0110, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x04E0, 0x0110, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK, 0x04E0, 0x0110, 2, 0x08B8, 0, 0) -MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x04E0, 0x0110, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x04E0, 0x0110, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__EPDC_DATA00, 0x04E0, 0x0110, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x04E4, 0x0114, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x04E4, 0x0114, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12, 0x04E4, 0x0114, 2, 0x0890, 0, 0) -MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x04E4, 0x0114, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x04E4, 0x0114, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT, 0x04E4, 0x0114, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x04E8, 0x0118, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x04E8, 0x0118, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13, 0x04E8, 0x0118, 2, 0x0894, 0, 0) -MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x04E8, 0x0118, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x04E8, 0x0118, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0, 0x04E8, 0x0118, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x04EC, 0x011C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x04EC, 0x011C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14, 0x04EC, 0x011C, 2, 0x0898, 0, 0) -MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x04EC, 0x011C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x04EC, 0x011C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1, 0x04EC, 0x011C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x04F0, 0x0120, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x04F0, 0x0120, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15, 0x04F0, 0x0120, 2, 0x089C, 0, 0) -MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x04F0, 0x0120, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x04F0, 0x0120, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2, 0x04F0, 0x0120, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x04F4, 0x0124, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x04F4, 0x0124, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16, 0x04F4, 0x0124, 2, 0x08A0, 0, 0) -MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x04F4, 0x0124, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x04F4, 0x0124, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__EPDC_GDCLK, 0x04F4, 0x0124, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x04F8, 0x0128, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x04F8, 0x0128, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17, 0x04F8, 0x0128, 2, 0x08A4, 0, 0) -MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x04F8, 0x0128, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x04F8, 0x0128, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__EPDC_GDSP, 0x04F8, 0x0128, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x04FC, 0x012C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x04FC, 0x012C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18, 0x04FC, 0x012C, 2, 0x08A8, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x04FC, 0x012C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x04FC, 0x012C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x04FC, 0x012C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__EPDC_GDOE, 0x04FC, 0x012C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x0500, 0x0130, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x0500, 0x0130, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19, 0x0500, 0x0130, 2, 0x08AC, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x0500, 0x0130, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x0500, 0x0130, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x0500, 0x0130, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__EPDC_GDRL, 0x0500, 0x0130, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x0504, 0x0134, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x0504, 0x0134, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x0504, 0x0134, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x0504, 0x0134, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x0504, 0x0134, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x0504, 0x0134, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x0504, 0x0134, 6, 0x085C, 0, 0) -MX6_PAD_DECL(EIM_A25__EPDC_DATA15, 0x0504, 0x0134, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN, 0x0504, 0x0134, 9, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x0508, 0x0138, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x0508, 0x0138, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x0508, 0x0138, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9, 0x0508, 0x0138, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x050C, 0x013C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x050C, 0x013C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x050C, 0x013C, 2, 0x07F4, 2, 0) -MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x050C, 0x013C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__EPDC_DATA06, 0x050C, 0x013C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0510, 0x0140, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0510, 0x0140, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0510, 0x0140, 2, 0x07FC, 2, 0) -MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0510, 0x0140, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__EPDC_DATA08, 0x0510, 0x0140, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x0514, 0x0144, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x0514, 0x0144, 1, 0x07D8, 2, 0) -MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x0514, 0x0144, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18, 0x0514, 0x0144, 3, 0x08A8, 1, 0) -MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x0514, 0x0144, 4, 0x0864, 0, 0) -MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x0514, 0x0144, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0) -MX6_PAD_DECL(EIM_D16__EPDC_DATA10, 0x0514, 0x0144, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x0518, 0x0148, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x0518, 0x0148, 1, 0x07DC, 2, 0) -MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x0518, 0x0148, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK, 0x0518, 0x0148, 3, 0x08B8, 1, 0) -MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x0518, 0x0148, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x0518, 0x0148, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0) -MX6_PAD_DECL(EIM_D17__EPDC_VCOM0, 0x0518, 0x0148, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x051C, 0x014C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x051C, 0x014C, 1, 0x07E0, 2, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x051C, 0x014C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17, 0x051C, 0x014C, 3, 0x08A4, 1, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x051C, 0x014C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x051C, 0x014C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0) -MX6_PAD_DECL(EIM_D18__EPDC_VCOM1, 0x051C, 0x014C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x0520, 0x0150, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x0520, 0x0150, 1, 0x07E8, 1, 0) -MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x0520, 0x0150, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16, 0x0520, 0x0150, 3, 0x08A0, 1, 0) -MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x0520, 0x0150, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x0520, 0x0150, 4, 0x08F8, 0, 0) -MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x0520, 0x0150, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x0520, 0x0150, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EPDC_DATA12, 0x0520, 0x0150, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x0524, 0x0154, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x0524, 0x0154, 1, 0x0808, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x0524, 0x0154, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15, 0x0524, 0x0154, 3, 0x089C, 1, 0) -MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x0524, 0x0154, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x0524, 0x0154, 4, 0x08F8, 1, 0) -MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x0524, 0x0154, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x0524, 0x0154, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x0528, 0x0158, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x0528, 0x0158, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x0528, 0x0158, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11, 0x0528, 0x0158, 3, 0x088C, 0, 0) -MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x0528, 0x0158, 4, 0x0920, 0, 0) -MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x0528, 0x0158, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0) -MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x0528, 0x0158, 7, 0x08F0, 0, 0) -MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x052C, 0x015C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x052C, 0x015C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x052C, 0x015C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10, 0x052C, 0x015C, 3, 0x0888, 0, 0) -MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x052C, 0x015C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x052C, 0x015C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x052C, 0x015C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__EPDC_SDCE6, 0x052C, 0x015C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x0530, 0x0160, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x0530, 0x0160, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x0530, 0x0160, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x0530, 0x0160, 2, 0x0908, 0, 0) -MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x0530, 0x0160, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN, 0x0530, 0x0160, 4, 0x08B0, 0, 0) -MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x0530, 0x0160, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x0530, 0x0160, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x0530, 0x0160, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__EPDC_DATA11, 0x0530, 0x0160, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x0534, 0x0164, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x0534, 0x0164, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x0534, 0x0164, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x0534, 0x0164, 2, 0x090C, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x0534, 0x0164, 3, 0x07EC, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x0534, 0x0164, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x0534, 0x0164, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x0534, 0x0164, 6, 0x07BC, 1, 0) -MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x0534, 0x0164, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__EPDC_SDCE7, 0x0534, 0x0164, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x0538, 0x0168, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x0538, 0x0168, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x0538, 0x0168, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x0538, 0x0168, 2, 0x090C, 1, 0) -MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x0538, 0x0168, 3, 0x07F0, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x0538, 0x0168, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x0538, 0x0168, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x0538, 0x0168, 6, 0x07B8, 1, 0) -MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x0538, 0x0168, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__EPDC_SDCE8, 0x0538, 0x0168, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x053C, 0x016C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x053C, 0x016C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x053C, 0x016C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14, 0x053C, 0x016C, 3, 0x0898, 1, 0) -MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x053C, 0x016C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x053C, 0x016C, 4, 0x0904, 0, 0) -MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x053C, 0x016C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x053C, 0x016C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x053C, 0x016C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__EPDC_SDOED, 0x053C, 0x016C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x0540, 0x0170, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x0540, 0x0170, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x0540, 0x0170, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13, 0x0540, 0x0170, 3, 0x0894, 1, 0) -MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x0540, 0x0170, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x0540, 0x0170, 4, 0x0904, 1, 0) -MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x0540, 0x0170, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x0540, 0x0170, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x0540, 0x0170, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__EPDC_SDOE, 0x0540, 0x0170, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x0544, 0x0174, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0) -MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x0544, 0x0174, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12, 0x0544, 0x0174, 3, 0x0890, 1, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x0544, 0x0174, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x0544, 0x0174, 4, 0x0900, 0, 0) -MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x0544, 0x0174, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x0544, 0x0174, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x0544, 0x0174, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3, 0x0544, 0x0174, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x0548, 0x0178, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x0548, 0x0178, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x0548, 0x0178, 2, 0x0808, 1, 0) -MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x0548, 0x0178, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x0548, 0x0178, 4, 0x0900, 1, 0) -MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x0548, 0x0178, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC, 0x0548, 0x0178, 6, 0x08BC, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x0548, 0x0178, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE, 0x0548, 0x0178, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x054C, 0x017C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x054C, 0x017C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x054C, 0x017C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x054C, 0x017C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x054C, 0x017C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x054C, 0x017C, 4, 0x0908, 1, 0) -MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x054C, 0x017C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x054C, 0x017C, 6, 0x0924, 0, 0) -MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ, 0x054C, 0x017C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x0550, 0x0180, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x0550, 0x0180, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x0550, 0x0180, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x0550, 0x0180, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x0550, 0x0180, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x0550, 0x0180, 4, 0x0908, 2, 0) -MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x0550, 0x0180, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x0550, 0x0180, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P, 0x0550, 0x0180, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN, 0x0550, 0x0180, 9, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0554, 0x0184, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0554, 0x0184, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09, 0x0554, 0x0184, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0554, 0x0184, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0554, 0x0184, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N, 0x0554, 0x0184, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x0558, 0x0188, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x0558, 0x0188, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08, 0x0558, 0x0188, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x0558, 0x0188, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x0558, 0x0188, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__EPDC_SDLE, 0x0558, 0x0188, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x055C, 0x018C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x055C, 0x018C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN, 0x055C, 0x018C, 2, 0x08B0, 1, 0) -MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x055C, 0x018C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x055C, 0x018C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__EPDC_DATA01, 0x055C, 0x018C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0560, 0x0190, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0560, 0x0190, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC, 0x0560, 0x0190, 2, 0x08B4, 0, 0) -MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0560, 0x0190, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0560, 0x0190, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__EPDC_DATA03, 0x0560, 0x0190, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0564, 0x0194, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0564, 0x0194, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC, 0x0564, 0x0194, 2, 0x08BC, 1, 0) -MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0564, 0x0194, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0564, 0x0194, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__EPDC_DATA02, 0x0564, 0x0194, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x0568, 0x0198, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x0568, 0x0198, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x0568, 0x0198, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x0568, 0x0198, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__EPDC_DATA13, 0x0568, 0x0198, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x056C, 0x019C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x056C, 0x019C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x056C, 0x019C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x056C, 0x019C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__EPDC_DATA14, 0x056C, 0x019C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0570, 0x01A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0570, 0x01A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0570, 0x01A0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0570, 0x01A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0570, 0x01A0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__EPDC_DATA09, 0x0570, 0x01A0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0574, 0x01A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0574, 0x01A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07, 0x0574, 0x01A4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0574, 0x01A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0574, 0x01A4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__EPDC_BDR0, 0x0574, 0x01A4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0578, 0x01A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0578, 0x01A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06, 0x0578, 0x01A8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0578, 0x01A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0578, 0x01A8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__EPDC_BDR1, 0x0578, 0x01A8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x057C, 0x01AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x057C, 0x01AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05, 0x057C, 0x01AC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x057C, 0x01AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x057C, 0x01AC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0, 0x057C, 0x01AC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x0580, 0x01B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x0580, 0x01B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04, 0x0580, 0x01B0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x0580, 0x01B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x0580, 0x01B0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1, 0x0580, 0x01B0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0584, 0x01B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0584, 0x01B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03, 0x0584, 0x01B4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0584, 0x01B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0584, 0x01B4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2, 0x0584, 0x01B4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0588, 0x01B8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0588, 0x01B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02, 0x0588, 0x01B8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0588, 0x01B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0588, 0x01B8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3, 0x0588, 0x01B8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x058C, 0x01BC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x058C, 0x01BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01, 0x058C, 0x01BC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x058C, 0x01BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x058C, 0x01BC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4, 0x058C, 0x01BC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x0590, 0x01C0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x0590, 0x01C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00, 0x0590, 0x01C0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x0590, 0x01C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x0590, 0x01C0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5, 0x0590, 0x01C0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0594, 0x01C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0594, 0x01C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11, 0x0594, 0x01C4, 2, 0x088C, 1, 0) -MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0594, 0x01C4, 4, 0x07D4, 0, 0) -MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0594, 0x01C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0594, 0x01C4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM, 0x0594, 0x01C4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0598, 0x01C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0598, 0x01C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10, 0x0598, 0x01C8, 2, 0x0888, 1, 0) -MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0598, 0x01C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0598, 0x01C8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR, 0x0598, 0x01C8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x059C, 0x01CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x059C, 0x01CC, 1, 0x07E4, 2, 0) -MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19, 0x059C, 0x01CC, 3, 0x08AC, 1, 0) -MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x059C, 0x01CC, 4, 0x0860, 0, 0) -MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x059C, 0x01CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0) -MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x059C, 0x01CC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__EPDC_DATA05, 0x059C, 0x01CC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x05A0, 0x01D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x05A0, 0x01D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x05A0, 0x01D0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x05A0, 0x01D0, 2, 0x0908, 3, 0) -MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x05A0, 0x01D0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC, 0x05A0, 0x01D0, 4, 0x08B4, 1, 0) -MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x05A0, 0x01D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x05A0, 0x01D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x05A0, 0x01D0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0, 0x05A0, 0x01D0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN, 0x05A0, 0x01D0, 9, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x05A4, 0x01D4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x05A4, 0x01D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x05A4, 0x01D4, 2, 0x0804, 1, 0) -MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x05A4, 0x01D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x05A4, 0x01D4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__EPDC_DATA04, 0x05A4, 0x01D4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x05A8, 0x01D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x05A8, 0x01D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x05A8, 0x01D8, 2, 0x07F8, 2, 0) -MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x05A8, 0x01D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ, 0x05A8, 0x01D8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__EIM_RW, 0x05AC, 0x01DC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x05AC, 0x01DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x05AC, 0x01DC, 2, 0x0800, 2, 0) -MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x05AC, 0x01DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x05AC, 0x01DC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__EPDC_DATA07, 0x05AC, 0x01DC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x05B0, 0x01E0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x05B0, 0x01E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x05B0, 0x01E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x05B0, 0x01E0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x05B4, 0x01E4, 1, 0x0828, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x05B4, 0x01E4, 2, 0x0840, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x05B4, 0x01E4, 3, 0x08F4, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x05B4, 0x01E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x05B8, 0x01E8, 0, 0x08E0, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x05B8, 0x01E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x05B8, 0x01E8, 2, 0x0858, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x05B8, 0x01E8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x05B8, 0x01E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x05BC, 0x01EC, 1, 0x0810, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x05C4, 0x01F4, 0, 0x0790, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x05C4, 0x01F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x05C4, 0x01F4, 2, 0x0834, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x05C4, 0x01F4, 3, 0x08F0, 1, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x05C4, 0x01F4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x05C4, 0x01F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x05C8, 0x01F8, 1, 0x0818, 0, 0) -MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x05C8, 0x01F8, 2, 0x0838, 0, 0) -MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x05CC, 0x01FC, 0, 0x08E4, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x05CC, 0x01FC, 1, 0x081C, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x05CC, 0x01FC, 2, 0x0830, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x05D0, 0x0200, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x05D0, 0x0200, 2, 0x0850, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x05D0, 0x0200, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL, 0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x05D4, 0x0204, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x05D4, 0x0204, 2, 0x0854, 0, 0) -MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x05D4, 0x0204, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x05D8, 0x0208, 0, 0x08DC, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x05D8, 0x0208, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x05D8, 0x0208, 2, 0x084C, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x05D8, 0x0208, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x05D8, 0x0208, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__I2C4_SDA, 0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0) -MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05DC, 0x020C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05DC, 0x020C, 2, 0x08C0, 1, 0) -MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05DC, 0x020C, 3, 0x0794, 0, 0) -MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05DC, 0x020C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05DC, 0x020C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05DC, 0x020C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05E0, 0x0210, 0, 0x083C, 1, 0) -MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05E0, 0x0210, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05E0, 0x0210, 2, 0x08CC, 1, 0) -MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05E0, 0x0210, 3, 0x0790, 1, 0) -MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05E0, 0x0210, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) -MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0) -MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) -MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0) -MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x05E4, 0x0214, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x05E8, 0x0218, 0, 0x0844, 0, 0) -MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x05E8, 0x0218, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x05E8, 0x0218, 2, 0x07D4, 1, 0) -MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x05E8, 0x0218, 3, 0x08E8, 1, 0) -MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x05E8, 0x0218, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x05E8, 0x0218, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x05EC, 0x021C, 0, 0x0848, 0, 0) -MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x05EC, 0x021C, 1, 0x0814, 0, 0) -MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x05EC, 0x021C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x05EC, 0x021C, 3, 0x08EC, 1, 0) -MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x05EC, 0x021C, 4, 0x0794, 1, 0) -MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x05EC, 0x021C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x05EC, 0x021C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x05F0, 0x0220, 0, 0x08C0, 2, 0) -MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x05F0, 0x0220, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x05F0, 0x0220, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x05F0, 0x0220, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x05F0, 0x0220, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x05F0, 0x0220, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x05F0, 0x0220, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x05F4, 0x0224, 0, 0x0830, 1, 0) -MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x05F4, 0x0224, 2, 0x08D0, 1, 0) -MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x05F4, 0x0224, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__SD2_WP, 0x05F4, 0x0224, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x05F4, 0x0224, 7, 0x08E0, 1, 0) -MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05F8, 0x0228, 0, 0x0834, 1, 0) -MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0) -MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05F8, 0x0228, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05F8, 0x0228, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05F8, 0x0228, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05F8, 0x0228, 6, 0x0924, 1, 0) -MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05F8, 0x0228, 7, 0x08DC, 1, 0) -MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x05FC, 0x022C, 0, 0x0838, 1, 0) -MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x05FC, 0x022C, 2, 0x08C8, 1, 0) -MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x05FC, 0x022C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x05FC, 0x022C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x0600, 0x0230, 0, 0x084C, 1, 0) -MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x0600, 0x0230, 2, 0x08D4, 1, 0) -MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x0600, 0x0230, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x0600, 0x0230, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0) -MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x0600, 0x0230, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0604, 0x0234, 0, 0x0840, 1, 0) -MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0) -MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0604, 0x0234, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0604, 0x0234, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0604, 0x0234, 7, 0x08E4, 1, 0) -MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0608, 0x0238, 0, 0x0854, 1, 0) -MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0608, 0x0238, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0608, 0x0238, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0608, 0x0238, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0608, 0x0238, 4, 0x0904, 2, 0) -MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0608, 0x0238, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0608, 0x0238, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0608, 0x0238, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__I2C4_SCL, 0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0) -MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x060C, 0x023C, 0, 0x0858, 1, 0) -MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x060C, 0x023C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x060C, 0x023C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x060C, 0x023C, 3, 0x07C8, 0, 0) -MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x060C, 0x023C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x060C, 0x023C, 4, 0x0904, 3, 0) -MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x060C, 0x023C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x060C, 0x023C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x060C, 0x023C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__I2C4_SDA, 0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0) -MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x0610, 0x0240, 0, 0x082C, 1, 0) -MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x0610, 0x0240, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x0610, 0x0240, 2, 0x08C4, 1, 0) -MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x0610, 0x0240, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x0610, 0x0240, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x0610, 0x0240, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__SD1_WP, 0x0610, 0x0240, 6, 0x092C, 1, 0) -MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x062C, 0x0244, 0, 0x07D8, 3, 0) -MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x062C, 0x0244, 1, 0x0824, 0, 0) -MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x062C, 0x0244, 2, 0x07C0, 1, 0) -MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x062C, 0x0244, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x062C, 0x0244, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x062C, 0x0244, 4, 0x0914, 2, 0) -MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x062C, 0x0244, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x062C, 0x0244, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x0630, 0x0248, 0, 0x07DC, 3, 0) -MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x0630, 0x0248, 1, 0x0810, 1, 0) -MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x0630, 0x0248, 2, 0x07C4, 1, 0) -MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x0630, 0x0248, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x0630, 0x0248, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x0630, 0x0248, 4, 0x091C, 2, 0) -MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x0630, 0x0248, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x0630, 0x0248, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x0634, 0x024C, 0, 0x07E8, 2, 0) -MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x0634, 0x024C, 1, 0x0820, 0, 0) -MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x0634, 0x024C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x0634, 0x024C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x0634, 0x024C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x0634, 0x024C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x0634, 0x024C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x0638, 0x0250, 0, 0x07F0, 1, 0) -MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x0638, 0x0250, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x0638, 0x0250, 2, 0x0860, 1, 0) -MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x0638, 0x0250, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0) -MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x0638, 0x0250, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x0638, 0x0250, 6, 0x08F0, 3, 0) -MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x063C, 0x0254, 0, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x063C, 0x0254, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x063C, 0x0254, 2, 0x0920, 1, 0) -MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x063C, 0x0254, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x063C, 0x0254, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x063C, 0x0254, 4, 0x0918, 2, 0) -MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x063C, 0x0254, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x0640, 0x0258, 0, 0x07E0, 3, 0) -MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x0640, 0x0258, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x0640, 0x0258, 2, 0x07B4, 1, 0) -MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x0640, 0x0258, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x0640, 0x0258, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x0640, 0x0258, 4, 0x0914, 3, 0) -MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x0640, 0x0258, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x0640, 0x0258, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x0644, 0x025C, 0, 0x07E4, 3, 0) -MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x0644, 0x025C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x0644, 0x025C, 2, 0x07B0, 1, 0) -MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x0644, 0x025C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x0644, 0x025C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x0644, 0x025C, 4, 0x091C, 3, 0) -MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x0644, 0x025C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x0644, 0x025C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x0648, 0x0260, 0, 0x07EC, 1, 0) -MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x0648, 0x0260, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x0648, 0x0260, 2, 0x07C8, 1, 0) -MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x0648, 0x0260, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x0648, 0x0260, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x0648, 0x0260, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x0648, 0x0260, 6, 0x085C, 1, 0) -MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x064C, 0x0264, 1, 0x0794, 2, 0) -MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x064C, 0x0264, 2, 0x0864, 1, 0) -MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x064C, 0x0264, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0) -MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x064C, 0x0264, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x064C, 0x0264, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x0650, 0x0268, 0, 0x07CC, 0, 0) -MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x0650, 0x0268, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x0650, 0x0268, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x0650, 0x0268, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x0650, 0x0268, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x0650, 0x0268, 4, 0x0918, 3, 0) -MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x0650, 0x0268, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x0654, 0x026C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x0654, 0x026C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x0654, 0x026C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x0658, 0x0270, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x0658, 0x0270, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x065C, 0x0274, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x065C, 0x0274, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x0660, 0x0278, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x0660, 0x0278, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x0660, 0x0278, 2, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x0660, 0x0278, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x0664, 0x027C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x0664, 0x027C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x0664, 0x027C, 2, 0x0844, 1, 0) -MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x0664, 0x027C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x0664, 0x027C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x0664, 0x027C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x0668, 0x0280, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x0668, 0x0280, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x0668, 0x0280, 2, 0x0848, 1, 0) -MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x0668, 0x0280, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x0668, 0x0280, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__I2C4_SDA, 0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0) -MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x066C, 0x0284, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x066C, 0x0284, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x066C, 0x0284, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x0670, 0x0288, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x0670, 0x0288, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x0670, 0x0288, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x0674, 0x028C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x0674, 0x028C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x0674, 0x028C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x0678, 0x0290, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x0678, 0x0290, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x0678, 0x0290, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x067C, 0x0294, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x067C, 0x0294, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x067C, 0x0294, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x0680, 0x0298, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x0680, 0x0298, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x0680, 0x0298, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x0684, 0x029C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x0684, 0x029C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x0684, 0x029C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0688, 0x02A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0688, 0x02A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0688, 0x02A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x068C, 0x02A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x068C, 0x02A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x0690, 0x02A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x0690, 0x02A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL, 0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0) -MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0694, 0x02AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0694, 0x02AC, 1, 0x0818, 1, 0) -MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0694, 0x02AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x0698, 0x02B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x0698, 0x02B0, 1, 0x081C, 1, 0) -MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x0698, 0x02B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x069C, 0x02B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x069C, 0x02B4, 1, 0x0820, 1, 0) -MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x069C, 0x02B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x06A0, 0x02B8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x06A0, 0x02B8, 1, 0x0824, 1, 0) -MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x06A4, 0x02BC, 1, 0x0828, 1, 0) -MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) -MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x06A8, 0x02C0, 1, 0x0814, 1, 0) -MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x06B0, 0x02C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) -MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0) -MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) -MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x06C0, 0x02D8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x06C4, 0x02DC, 0, 0x0928, 1, 0) -MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x06C4, 0x02DC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x06C8, 0x02E0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x06C8, 0x02E0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x06CC, 0x02E4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x06D0, 0x02E8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x06D4, 0x02EC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x06D8, 0x02F0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x06D8, 0x02F0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x06DC, 0x02F4, 0, 0x0930, 1, 0) -MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x06DC, 0x02F4, 2, 0x08C0, 3, 0) -MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x06DC, 0x02F4, 3, 0x07A4, 1, 0) -MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x06E0, 0x02F8, 2, 0x08CC, 2, 0) -MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x06E0, 0x02F8, 3, 0x07A0, 1, 0) -MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x06E4, 0x02FC, 3, 0x0798, 1, 0) -MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x06E4, 0x02FC, 4, 0x08D4, 2, 0) -MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x06E4, 0x02FC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x06E8, 0x0300, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x06E8, 0x0300, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x06E8, 0x0300, 3, 0x07AC, 1, 0) -MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x06E8, 0x0300, 4, 0x08C8, 2, 0) -MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x06E8, 0x0300, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x06EC, 0x0304, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x06EC, 0x0304, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x06EC, 0x0304, 3, 0x079C, 1, 0) -MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x06EC, 0x0304, 4, 0x08D0, 2, 0) -MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x06EC, 0x0304, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x06F0, 0x0308, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x06F0, 0x0308, 2, 0x08C4, 2, 0) -MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x06F0, 0x0308, 3, 0x07A8, 1, 0) -MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x06F0, 0x0308, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06F4, 0x030C, 0, 0x0934, 1, 0) -MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06F4, 0x030C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06F4, 0x030C, 1, 0x0900, 2, 0) -MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06F4, 0x030C, 2, 0x07C8, 2, 0) -MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06F4, 0x030C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06F8, 0x0310, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06F8, 0x0310, 1, 0x0900, 3, 0) -MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06F8, 0x0310, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06F8, 0x0310, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06FC, 0x0314, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06FC, 0x0314, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06FC, 0x0314, 1, 0x08F8, 2, 0) -MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06FC, 0x0314, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06FC, 0x0314, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x0700, 0x0318, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x0700, 0x0318, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x0700, 0x0318, 1, 0x08F8, 3, 0) -MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x0700, 0x0318, 2, 0x07CC, 1, 0) -MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x0700, 0x0318, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x0704, 0x031C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x0704, 0x031C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x0708, 0x0320, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x0708, 0x0320, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x0708, 0x0320, 1, 0x0908, 4, 0) -MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x0708, 0x0320, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x070C, 0x0324, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x070C, 0x0324, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x070C, 0x0324, 1, 0x0904, 4, 0) -MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x070C, 0x0324, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0710, 0x0328, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0710, 0x0328, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0710, 0x0328, 1, 0x0904, 5, 0) -MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0710, 0x0328, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0714, 0x032C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0714, 0x032C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0714, 0x032C, 1, 0x08FC, 2, 0) -MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0714, 0x032C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0718, 0x0330, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0718, 0x0330, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0718, 0x0330, 1, 0x08FC, 3, 0) -MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0718, 0x0330, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x071C, 0x0334, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x071C, 0x0334, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x071C, 0x0334, 1, 0x0908, 5, 0) -MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x071C, 0x0334, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x0720, 0x0338, 0, 0x0938, 1, 0) -MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x0720, 0x0338, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x0720, 0x0338, 2, 0x090C, 2, 0) -MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x0720, 0x0338, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x0724, 0x033C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x0724, 0x033C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x0724, 0x033C, 2, 0x090C, 3, 0) -MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x0724, 0x033C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0728, 0x0340, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0728, 0x0340, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0728, 0x0340, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x072C, 0x0344, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x072C, 0x0344, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x072C, 0x0344, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x0730, 0x0348, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x0730, 0x0348, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0734, 0x034C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0734, 0x034C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0738, 0x0350, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0738, 0x0350, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0738, 0x0350, 2, 0x0904, 6, 0) -MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0738, 0x0350, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x073C, 0x0354, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x073C, 0x0354, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x073C, 0x0354, 2, 0x0900, 4, 0) -MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x073C, 0x0354, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x0740, 0x0358, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x0740, 0x0358, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x0740, 0x0358, 2, 0x0900, 5, 0) -MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x0740, 0x0358, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0744, 0x035C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0744, 0x035C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0744, 0x035C, 2, 0x0904, 7, 0) -MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0744, 0x035C, 5, 0x0000, 0, 0) - -#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h deleted file mode 100644 index c76a920..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices Inc. - */ -#ifndef __ASM_ARCH_MX6Q_DDR_H__ -#define __ASM_ARCH_MX6Q_DDR_H__ - -#ifndef CONFIG_MX6Q -#error "wrong CPU" -#endif - -#define MX6_IOM_DRAM_DQM0 0x020e05ac -#define MX6_IOM_DRAM_DQM1 0x020e05b4 -#define MX6_IOM_DRAM_DQM2 0x020e0528 -#define MX6_IOM_DRAM_DQM3 0x020e0520 -#define MX6_IOM_DRAM_DQM4 0x020e0514 -#define MX6_IOM_DRAM_DQM5 0x020e0510 -#define MX6_IOM_DRAM_DQM6 0x020e05bc -#define MX6_IOM_DRAM_DQM7 0x020e05c4 - -#define MX6_IOM_DRAM_CAS 0x020e056c -#define MX6_IOM_DRAM_RAS 0x020e0578 -#define MX6_IOM_DRAM_RESET 0x020e057c -#define MX6_IOM_DRAM_SDCLK_0 0x020e0588 -#define MX6_IOM_DRAM_SDCLK_1 0x020e0594 -#define MX6_IOM_DRAM_SDBA2 0x020e058c -#define MX6_IOM_DRAM_SDCKE0 0x020e0590 -#define MX6_IOM_DRAM_SDCKE1 0x020e0598 -#define MX6_IOM_DRAM_SDODT0 0x020e059c -#define MX6_IOM_DRAM_SDODT1 0x020e05a0 - -#define MX6_IOM_DRAM_SDQS0 0x020e05a8 -#define MX6_IOM_DRAM_SDQS1 0x020e05b0 -#define MX6_IOM_DRAM_SDQS2 0x020e0524 -#define MX6_IOM_DRAM_SDQS3 0x020e051c -#define MX6_IOM_DRAM_SDQS4 0x020e0518 -#define MX6_IOM_DRAM_SDQS5 0x020e050c -#define MX6_IOM_DRAM_SDQS6 0x020e05b8 -#define MX6_IOM_DRAM_SDQS7 0x020e05c0 - -#define MX6_IOM_GRP_B0DS 0x020e0784 -#define MX6_IOM_GRP_B1DS 0x020e0788 -#define MX6_IOM_GRP_B2DS 0x020e0794 -#define MX6_IOM_GRP_B3DS 0x020e079c -#define MX6_IOM_GRP_B4DS 0x020e07a0 -#define MX6_IOM_GRP_B5DS 0x020e07a4 -#define MX6_IOM_GRP_B6DS 0x020e07a8 -#define MX6_IOM_GRP_B7DS 0x020e0748 -#define MX6_IOM_GRP_ADDDS 0x020e074c -#define MX6_IOM_DDRMODE_CTL 0x020e0750 -#define MX6_IOM_GRP_DDRPKE 0x020e0758 -#define MX6_IOM_GRP_DDRMODE 0x020e0774 -#define MX6_IOM_GRP_CTLDS 0x020e078c -#define MX6_IOM_GRP_DDR_TYPE 0x020e0798 - -#endif /*__ASM_ARCH_MX6Q_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h deleted file mode 100644 index dce13d0..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ /dev/null @@ -1,1035 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Auto Generate file, please don't edit it - */ - -#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__ -#define __ASM_ARCH_MX6_MX6Q_PINS_H__ - -MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x0360, 0x004C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0, 0x0360, 0x004C, 1, 0x0834, 0, 0) -MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x0360, 0x004C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x0360, 0x004C, 3, 0x07C8, 0, 0) -MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x0360, 0x004C, 4, 0x08F0, 0, 0) -MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x0360, 0x004C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x0364, 0x0050, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1, 0x0364, 0x0050, 1, 0x0838, 0, 0) -MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x0364, 0x0050, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x0364, 0x0050, 3, 0x07B8, 0, 0) -MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x0364, 0x0050, 4, 0x08F8, 0, 0) -MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x0364, 0x0050, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x0368, 0x0054, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO, 0x0368, 0x0054, 1, 0x082C, 0, 0) -MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x0368, 0x0054, 3, 0x07B4, 0, 0) -MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x0368, 0x0054, 4, 0x08FC, 0, 0) -MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x0368, 0x0054, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x0368, 0x0054, 6, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x036C, 0x0058, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x036C, 0x0058, 2, 0x0918, 0, 0) -MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x036C, 0x0058, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x036C, 0x0058, 7, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x0370, 0x005C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x0370, 0x005C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x0374, 0x0060, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x0374, 0x0060, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x0378, 0x0064, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x0378, 0x0064, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x037C, 0x0068, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x037C, 0x0068, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x0380, 0x006C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x0380, 0x006C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0384, 0x0070, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0, 0) -MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0) -MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) -MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x0390, 0x007C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0, 0) -MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x0390, 0x007C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x0394, 0x0080, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0, 0) -MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x0394, 0x0080, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x0398, 0x0084, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0, 0) -MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x0398, 0x0084, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x039C, 0x0088, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x039C, 0x0088, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x039C, 0x0088, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x039C, 0x0088, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x039C, 0x0088, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x039C, 0x0088, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x039C, 0x0088, 6, 0x088C, 0, 0) -MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x03A0, 0x008C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x03A0, 0x008C, 1, 0x0800, 0, 0) -MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19, 0x03A0, 0x008C, 3, 0x08D4, 0, 0) -MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x03A0, 0x008C, 4, 0x0890, 0, 0) -MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x03A0, 0x008C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x03A0, 0x008C, 22, 0x08A0, 0, 0) -MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x03A0, 0x008C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x03A4, 0x0090, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x03A4, 0x0090, 1, 0x07F4, 0, 0) -MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x03A4, 0x0090, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18, 0x03A4, 0x0090, 3, 0x08D0, 0, 0) -MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x03A4, 0x0090, 4, 0x0894, 0, 0) -MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x03A4, 0x0090, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x03A4, 0x0090, 22, 0x08A4, 0, 0) -MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x03A8, 0x0094, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x03A8, 0x0094, 1, 0x07F8, 0, 0) -MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x03A8, 0x0094, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK, 0x03A8, 0x0094, 3, 0x08E0, 0, 0) -MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x03A8, 0x0094, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x03A8, 0x0094, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x03A8, 0x0094, 22, 0x08A8, 0, 0) -MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x03AC, 0x0098, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x03AC, 0x0098, 1, 0x07FC, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x03AC, 0x0098, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17, 0x03AC, 0x0098, 3, 0x08CC, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x03AC, 0x0098, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x03AC, 0x0098, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x03AC, 0x0098, 22, 0x08AC, 0, 0) -MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x03B0, 0x009C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x03B0, 0x009C, 1, 0x0804, 0, 0) -MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x03B0, 0x009C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16, 0x03B0, 0x009C, 3, 0x08C8, 0, 0) -MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x03B0, 0x009C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x03B0, 0x009C, 4, 0x091C, 0, 0) -MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x03B0, 0x009C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x03B0, 0x009C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x03B4, 0x00A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x03B4, 0x00A0, 1, 0x0824, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15, 0x03B4, 0x00A0, 3, 0x08C4, 0, 0) -MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x03B4, 0x00A0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x03B4, 0x00A0, 4, 0x091C, 1, 0) -MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x03B4, 0x00A0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x03B8, 0x00A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x03B8, 0x00A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11, 0x03B8, 0x00A4, 3, 0x08B4, 0, 0) -MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x03B8, 0x00A4, 4, 0x0944, 0, 0) -MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x03B8, 0x00A4, 22, 0x0898, 0, 0) -MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x03B8, 0x00A4, 7, 0x0914, 0, 0) -MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x03BC, 0x00A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10, 0x03BC, 0x00A8, 3, 0x08B0, 0, 0) -MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x03BC, 0x00A8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x03BC, 0x00A8, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x03C0, 0x00AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x03C0, 0x00AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x03C0, 0x00AC, 2, 0x092C, 0, 0) -MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x03C0, 0x00AC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN, 0x03C0, 0x00AC, 4, 0x08D8, 0, 0) -MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x03C0, 0x00AC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x03C0, 0x00AC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x03C4, 0x00B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x03C4, 0x00B0, 2, 0x092C, 1, 0) -MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x03C4, 0x00B0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC, 0x03C4, 0x00B0, 4, 0x08DC, 0, 0) -MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x03C4, 0x00B0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x03C4, 0x00B0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x03C8, 0x00B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x03C8, 0x00B4, 2, 0x0930, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x03C8, 0x00B4, 3, 0x0808, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x03C8, 0x00B4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x03C8, 0x00B4, 6, 0x07D8, 0, 0) -MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x03C8, 0x00B4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x03CC, 0x00B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x03CC, 0x00B8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x03CC, 0x00B8, 2, 0x0930, 1, 0) -MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x03CC, 0x00B8, 3, 0x080C, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x03CC, 0x00B8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x03CC, 0x00B8, 6, 0x07D4, 0, 0) -MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x03CC, 0x00B8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x03D0, 0x00BC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x03D0, 0x00BC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14, 0x03D0, 0x00BC, 3, 0x08C0, 0, 0) -MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x03D0, 0x00BC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x03D0, 0x00BC, 4, 0x0928, 0, 0) -MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x03D0, 0x00BC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x03D0, 0x00BC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x03D4, 0x00C0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x03D4, 0x00C0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13, 0x03D4, 0x00C0, 3, 0x08BC, 0, 0) -MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x03D4, 0x00C0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x03D4, 0x00C0, 4, 0x0928, 1, 0) -MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x03D4, 0x00C0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x03D4, 0x00C0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x03D8, 0x00C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x03D8, 0x00C4, 17, 0x089C, 0, 0) -MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x03D8, 0x00C4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12, 0x03D8, 0x00C4, 3, 0x08B8, 0, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x03D8, 0x00C4, 4, 0x0924, 0, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x03D8, 0x00C4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x03D8, 0x00C4, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x03D8, 0x00C4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x03DC, 0x00C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x03DC, 0x00C8, 2, 0x0824, 1, 0) -MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x03DC, 0x00C8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x03DC, 0x00C8, 4, 0x0924, 1, 0) -MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC, 0x03DC, 0x00C8, 6, 0x08E4, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x03DC, 0x00C8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x03E0, 0x00CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x03E0, 0x00CC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x03E0, 0x00CC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x03E0, 0x00CC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x03E0, 0x00CC, 4, 0x092C, 2, 0) -MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x03E0, 0x00CC, 6, 0x0948, 0, 0) -MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x03E4, 0x00D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x03E4, 0x00D0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x03E4, 0x00D0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x03E4, 0x00D0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x03E4, 0x00D0, 4, 0x092C, 3, 0) -MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x03E4, 0x00D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x03E8, 0x00D4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19, 0x03E8, 0x00D4, 2, 0x08D4, 1, 0) -MX6_PAD_DECL(EIM_A24__IPU2_SISG2, 0x03E8, 0x00D4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x03E8, 0x00D4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x03E8, 0x00D4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x03EC, 0x00D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18, 0x03EC, 0x00D8, 2, 0x08D0, 1, 0) -MX6_PAD_DECL(EIM_A23__IPU2_SISG3, 0x03EC, 0x00D8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x03EC, 0x00D8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x03F0, 0x00DC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17, 0x03F0, 0x00DC, 2, 0x08CC, 1, 0) -MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16, 0x03F4, 0x00E0, 2, 0x08C8, 1, 0) -MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x03F4, 0x00E0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x03F8, 0x00E4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15, 0x03F8, 0x00E4, 2, 0x08C4, 1, 0) -MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x03F8, 0x00E4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x03FC, 0x00E8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14, 0x03FC, 0x00E8, 2, 0x08C0, 1, 0) -MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x03FC, 0x00E8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x0400, 0x00EC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x0400, 0x00EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13, 0x0400, 0x00EC, 2, 0x08BC, 1, 0) -MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x0400, 0x00EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x0400, 0x00EC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x0404, 0x00F0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x0404, 0x00F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12, 0x0404, 0x00F0, 2, 0x08B8, 1, 0) -MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x0404, 0x00F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x0404, 0x00F0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x0408, 0x00F4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x0408, 0x00F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK, 0x0408, 0x00F4, 2, 0x08E0, 1, 0) -MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x0408, 0x00F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x0408, 0x00F4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x040C, 0x00F8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x040C, 0x00F8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x040C, 0x00F8, 2, 0x0810, 0, 0) -MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x040C, 0x00F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0410, 0x00FC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0410, 0x00FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0410, 0x00FC, 2, 0x0818, 0, 0) -MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0410, 0x00FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x0414, 0x0100, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x0414, 0x0100, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x0414, 0x0100, 2, 0x0814, 0, 0) -MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x0414, 0x0100, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x0418, 0x0104, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x0418, 0x0104, 2, 0x081C, 0, 0) -MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x0418, 0x0104, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x0418, 0x0104, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x041C, 0x0108, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x041C, 0x0108, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x041C, 0x0108, 2, 0x0820, 0, 0) -MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x041C, 0x0108, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x041C, 0x0108, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0420, 0x010C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0420, 0x010C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11, 0x0420, 0x010C, 2, 0x08B4, 1, 0) -MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0420, 0x010C, 4, 0x07F0, 0, 0) -MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0420, 0x010C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0420, 0x010C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0424, 0x0110, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0424, 0x0110, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10, 0x0424, 0x0110, 2, 0x08B0, 1, 0) -MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0424, 0x0110, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0424, 0x0110, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0428, 0x0114, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0428, 0x0114, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09, 0x0428, 0x0114, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0428, 0x0114, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0428, 0x0114, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x042C, 0x0118, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x042C, 0x0118, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08, 0x042C, 0x0118, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x042C, 0x0118, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x042C, 0x0118, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0430, 0x011C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0430, 0x011C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07, 0x0430, 0x011C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0430, 0x011C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0430, 0x011C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0434, 0x0120, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0434, 0x0120, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06, 0x0434, 0x0120, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0434, 0x0120, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0434, 0x0120, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x0438, 0x0124, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x0438, 0x0124, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05, 0x0438, 0x0124, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x0438, 0x0124, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x0438, 0x0124, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x043C, 0x0128, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x043C, 0x0128, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04, 0x043C, 0x0128, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x043C, 0x0128, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x043C, 0x0128, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0440, 0x012C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0440, 0x012C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03, 0x0440, 0x012C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0440, 0x012C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0440, 0x012C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0444, 0x0130, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0444, 0x0130, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02, 0x0444, 0x0130, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0444, 0x0130, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0444, 0x0130, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x0448, 0x0134, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x0448, 0x0134, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01, 0x0448, 0x0134, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x0448, 0x0134, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x0448, 0x0134, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x044C, 0x0138, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x044C, 0x0138, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00, 0x044C, 0x0138, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x044C, 0x0138, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x044C, 0x0138, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x0450, 0x013C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x0450, 0x013C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN, 0x0450, 0x013C, 2, 0x08D8, 1, 0) -MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x0450, 0x013C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x0450, 0x013C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0454, 0x0140, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0454, 0x0140, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC, 0x0454, 0x0140, 2, 0x08DC, 1, 0) -MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0454, 0x0140, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0454, 0x0140, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0458, 0x0144, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0458, 0x0144, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC, 0x0458, 0x0144, 2, 0x08E4, 1, 0) -MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0458, 0x0144, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0458, 0x0144, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x045C, 0x0148, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x045C, 0x0148, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x045C, 0x0148, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x045C, 0x0148, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x0460, 0x014C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x0460, 0x014C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x0460, 0x014C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x0460, 0x014C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0464, 0x0150, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0464, 0x0150, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0464, 0x0150, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0464, 0x0150, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0464, 0x0150, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x0468, 0x0154, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x0468, 0x0154, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x0468, 0x0154, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x0468, 0x0154, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x046C, 0x0158, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x046C, 0x0158, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x0470, 0x015C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x0474, 0x0160, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x0474, 0x0160, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02, 0x0478, 0x0164, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x0478, 0x0164, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x0478, 0x0164, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03, 0x047C, 0x0168, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x047C, 0x0168, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x047C, 0x0168, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x0480, 0x016C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04, 0x0480, 0x016C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x0480, 0x016C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x0480, 0x016C, 3, 0x094C, 0, 0) -MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00, 0x0484, 0x0170, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x0484, 0x0170, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x0484, 0x0170, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01, 0x0488, 0x0174, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x0488, 0x0174, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x0488, 0x0174, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02, 0x048C, 0x0178, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x048C, 0x0178, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x048C, 0x0178, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03, 0x0490, 0x017C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0490, 0x017C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0490, 0x017C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04, 0x0494, 0x0180, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x0494, 0x0180, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x0494, 0x0180, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05, 0x0498, 0x0184, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0498, 0x0184, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0498, 0x0184, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0498, 0x0184, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06, 0x049C, 0x0188, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x049C, 0x0188, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x049C, 0x0188, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x049C, 0x0188, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07, 0x04A0, 0x018C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x04A0, 0x018C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x04A0, 0x018C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08, 0x04A4, 0x0190, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x04A4, 0x0190, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x04A4, 0x0190, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x04A4, 0x0190, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09, 0x04A8, 0x0194, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x04A8, 0x0194, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x04A8, 0x0194, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x04A8, 0x0194, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10, 0x04AC, 0x0198, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x04AC, 0x0198, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11, 0x04B0, 0x019C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x04B0, 0x019C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12, 0x04B4, 0x01A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x04B4, 0x01A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13, 0x04B8, 0x01A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x04B8, 0x01A4, 3, 0x07D8, 1, 0) -MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x04B8, 0x01A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14, 0x04BC, 0x01A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x04BC, 0x01A8, 3, 0x07D4, 1, 0) -MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x04BC, 0x01A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15, 0x04C0, 0x01AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x04C0, 0x01AC, 2, 0x0804, 1, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x04C0, 0x01AC, 3, 0x0820, 1, 0) -MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x04C0, 0x01AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16, 0x04C4, 0x01B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x04C4, 0x01B0, 2, 0x0818, 1, 0) -MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x04C4, 0x01B0, 3, 0x07DC, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x04C4, 0x01B0, 4, 0x090C, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x04C4, 0x01B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17, 0x04C8, 0x01B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x04C8, 0x01B4, 2, 0x0814, 1, 0) -MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x04C8, 0x01B4, 3, 0x07D0, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x04C8, 0x01B4, 4, 0x0910, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x04C8, 0x01B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18, 0x04CC, 0x01B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x04CC, 0x01B8, 2, 0x081C, 1, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x04CC, 0x01B8, 3, 0x07E0, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x04CC, 0x01B8, 4, 0x07C0, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x04CC, 0x01B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x04CC, 0x01B8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19, 0x04D0, 0x01BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x04D0, 0x01BC, 2, 0x0810, 1, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x04D0, 0x01BC, 3, 0x07CC, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x04D0, 0x01BC, 4, 0x07BC, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x04D0, 0x01BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x04D0, 0x01BC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20, 0x04D4, 0x01C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x04D4, 0x01C0, 2, 0x07F4, 1, 0) -MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x04D4, 0x01C0, 3, 0x07C4, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x04D4, 0x01C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21, 0x04D8, 0x01C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x04D8, 0x01C4, 2, 0x07FC, 1, 0) -MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x04D8, 0x01C4, 3, 0x07B8, 1, 0) -MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x04D8, 0x01C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22, 0x04DC, 0x01C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x04DC, 0x01C8, 2, 0x07F8, 1, 0) -MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x04DC, 0x01C8, 3, 0x07C8, 1, 0) -MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x04DC, 0x01C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23, 0x04E0, 0x01CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x04E0, 0x01CC, 2, 0x0800, 1, 0) -MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x04E0, 0x01CC, 3, 0x07B4, 1, 0) -MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x04E0, 0x01CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x04EC, 0x01D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x04EC, 0x01D8, 2, 0x0864, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x04EC, 0x01D8, 3, 0x0914, 1, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x04EC, 0x01D8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x04EC, 0x01D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x04F0, 0x01DC, 1, 0x0858, 1, 0) -MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x04F0, 0x01DC, 2, 0x0870, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x04F0, 0x01DC, 3, 0x0918, 1, 0) -MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x04F0, 0x01DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x04F4, 0x01E0, 0, 0x0908, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x04F4, 0x01E0, 1, 0x084C, 1, 0) -MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x04F4, 0x01E0, 2, 0x0860, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x04F4, 0x01E0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x04F4, 0x01E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x04F8, 0x01E4, 1, 0x0848, 1, 0) -MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x04F8, 0x01E4, 2, 0x0868, 0, 0) -MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x04F8, 0x01E4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x04F8, 0x01E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x04FC, 0x01E8, 2, 0x0880, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x04FC, 0x01E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x0500, 0x01EC, 0, 0x0900, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x0500, 0x01EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x0500, 0x01EC, 2, 0x087C, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x0500, 0x01EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x0500, 0x01EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x0504, 0x01F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x0504, 0x01F0, 2, 0x0884, 0, 0) -MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x0504, 0x01F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x0508, 0x01F4, 0, 0x0904, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x0508, 0x01F4, 2, 0x0888, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x0508, 0x01F4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x0508, 0x01F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x05C8, 0x01F8, 0, 0x07F4, 2, 0) -MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x05C8, 0x01F8, 1, 0x0854, 1, 0) -MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x05C8, 0x01F8, 2, 0x07DC, 1, 0) -MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x05C8, 0x01F8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x05C8, 0x01F8, 4, 0x0938, 0, 0) -MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x05C8, 0x01F8, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x05CC, 0x01FC, 0, 0x07FC, 2, 0) -MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x05CC, 0x01FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x05CC, 0x01FC, 2, 0x07D0, 1, 0) -MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x05CC, 0x01FC, 4, 0x0938, 1, 0) -MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x05CC, 0x01FC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x05D0, 0x0200, 0, 0x07F8, 2, 0) -MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x05D0, 0x0200, 1, 0x0840, 1, 0) -MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x05D0, 0x0200, 2, 0x07E0, 1, 0) -MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x05D0, 0x0200, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x05D0, 0x0200, 4, 0x0940, 0, 0) -MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x05D0, 0x0200, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x05D0, 0x0200, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x05D4, 0x0204, 0, 0x0800, 2, 0) -MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x05D4, 0x0204, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x05D4, 0x0204, 2, 0x07CC, 1, 0) -MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x05D4, 0x0204, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x05D4, 0x0204, 4, 0x0940, 1, 0) -MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x05D4, 0x0204, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x05D4, 0x0204, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x05D8, 0x0208, 0, 0x0804, 2, 0) -MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x05D8, 0x0208, 1, 0x0850, 1, 0) -MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x05D8, 0x0208, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x05D8, 0x0208, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x05D8, 0x0208, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x05D8, 0x0208, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x05DC, 0x020C, 0, 0x0808, 1, 0) -MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x05DC, 0x020C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x05DC, 0x020C, 2, 0x07E4, 0, 0) -MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x05DC, 0x020C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x05DC, 0x020C, 6, 0x088C, 1, 0) -MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x05E0, 0x0210, 0, 0x080C, 1, 0) -MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x05E0, 0x0210, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x05E0, 0x0210, 2, 0x0890, 1, 0) -MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x05E0, 0x0210, 20, 0x08A0, 1, 0) -MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x05E0, 0x0210, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x05E0, 0x0210, 6, 0x0914, 2, 0) -MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x05E4, 0x0214, 1, 0x07B0, 0, 0) -MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x05E4, 0x0214, 2, 0x0894, 1, 0) -MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x05E4, 0x0214, 20, 0x08A4, 1, 0) -MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x05E4, 0x0214, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x05E4, 0x0214, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x05E8, 0x0218, 0, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x05E8, 0x0218, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x05E8, 0x0218, 2, 0x0944, 1, 0) -MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x05E8, 0x0218, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x05E8, 0x0218, 4, 0x093C, 0, 0) -MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x05E8, 0x0218, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x05EC, 0x021C, 0, 0x07E8, 0, 0) -MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x05EC, 0x021C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x05EC, 0x021C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x05EC, 0x021C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x05EC, 0x021C, 4, 0x093C, 1, 0) -MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x05EC, 0x021C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05F0, 0x0220, 0, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05F0, 0x0220, 2, 0x08E8, 0, 0) -MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05F0, 0x0220, 3, 0x07B0, 1, 0) -MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05F0, 0x0220, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05F0, 0x0220, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05F0, 0x0220, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05F0, 0x0220, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05F4, 0x0224, 0, 0x086C, 1, 0) -MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05F4, 0x0224, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05F4, 0x0224, 2, 0x08F4, 0, 0) -MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05F4, 0x0224, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05F4, 0x0224, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05F4, 0x0224, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05F4, 0x0224, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x05F8, 0x0228, 0, 0x085C, 1, 0) -MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x05F8, 0x0228, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x05F8, 0x0228, 2, 0x08EC, 0, 0) -MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x05F8, 0x0228, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x05F8, 0x0228, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x05F8, 0x0228, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__SD1_WP, 0x05F8, 0x0228, 6, 0x094C, 1, 0) -MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05FC, 0x022C, 0, 0x0864, 1, 0) -MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05FC, 0x022C, 18, 0x08A8, 1, 0) -MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05FC, 0x022C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05FC, 0x022C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05FC, 0x022C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05FC, 0x022C, 6, 0x0948, 1, 0) -MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05FC, 0x022C, 7, 0x0900, 1, 0) -MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0600, 0x0230, 0, 0x0870, 1, 0) -MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0600, 0x0230, 18, 0x08AC, 1, 0) -MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0600, 0x0230, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0600, 0x0230, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0600, 0x0230, 7, 0x0908, 1, 0) -MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x0604, 0x0234, 0, 0x0860, 1, 0) -MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x0604, 0x0234, 2, 0x08F8, 1, 0) -MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x0604, 0x0234, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__SD2_WP, 0x0604, 0x0234, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x0604, 0x0234, 7, 0x0904, 1, 0) -MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x0608, 0x0238, 0, 0x0868, 1, 0) -MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x0608, 0x0238, 2, 0x08F0, 1, 0) -MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x0608, 0x0238, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x0608, 0x0238, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x060C, 0x023C, 0, 0x087C, 1, 0) -MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x060C, 0x023C, 2, 0x08FC, 1, 0) -MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x060C, 0x023C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x060C, 0x023C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x060C, 0x023C, 22, 0x08A8, 2, 0) -MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x060C, 0x023C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0610, 0x0240, 0, 0x0884, 1, 0) -MX6_PAD_DECL(GPIO_7__ECSPI5_RDY, 0x0610, 0x0240, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0610, 0x0240, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0610, 0x0240, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0610, 0x0240, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0610, 0x0240, 4, 0x0928, 2, 0) -MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0610, 0x0240, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0610, 0x0240, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0610, 0x0240, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x0614, 0x0244, 0, 0x0888, 1, 0) -MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x0614, 0x0244, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x0614, 0x0244, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x0614, 0x0244, 3, 0x07E4, 1, 0) -MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x0614, 0x0244, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x0614, 0x0244, 4, 0x0928, 3, 0) -MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x0614, 0x0244, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) -MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0) -MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) -MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x0618, 0x0248, 22, 0x08AC, 2, 0) -MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x0618, 0x0248, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x061C, 0x024C, 0, 0x0874, 0, 0) -MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x061C, 0x024C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x061C, 0x024C, 2, 0x07F0, 1, 0) -MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x061C, 0x024C, 3, 0x090C, 1, 0) -MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x061C, 0x024C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x061C, 0x024C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x0620, 0x0250, 0, 0x0878, 0, 0) -MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x0620, 0x0250, 1, 0x0844, 1, 0) -MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x0620, 0x0250, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x0620, 0x0250, 3, 0x0910, 1, 0) -MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x0620, 0x0250, 4, 0x07B0, 2, 0) -MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x0620, 0x0250, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x0620, 0x0250, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x0624, 0x0254, 0, 0x08E8, 1, 0) -MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x0624, 0x0254, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x0624, 0x0254, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x0624, 0x0254, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x0624, 0x0254, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x0624, 0x0254, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x0624, 0x0254, 6, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x0628, 0x0258, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x0628, 0x0258, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x062C, 0x025C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x062C, 0x025C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x062C, 0x025C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x062C, 0x025C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x0630, 0x0260, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x0630, 0x0260, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x0630, 0x0260, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x0634, 0x0264, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x0634, 0x0264, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x0634, 0x0264, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0638, 0x0268, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0638, 0x0268, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0638, 0x0268, 2, 0x07F4, 3, 0) -MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0638, 0x0268, 3, 0x08E8, 2, 0) -MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0638, 0x0268, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0638, 0x0268, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0638, 0x0268, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x063C, 0x026C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x063C, 0x026C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x063C, 0x026C, 2, 0x07FC, 3, 0) -MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x063C, 0x026C, 3, 0x08F4, 1, 0) -MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x063C, 0x026C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x063C, 0x026C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x063C, 0x026C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0640, 0x0270, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0640, 0x0270, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0640, 0x0270, 2, 0x07F8, 3, 0) -MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0640, 0x0270, 3, 0x08EC, 1, 0) -MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0640, 0x0270, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0640, 0x0270, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0640, 0x0270, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0644, 0x0274, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0644, 0x0274, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0644, 0x0274, 2, 0x0800, 3, 0) -MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0644, 0x0274, 3, 0x08F8, 2, 0) -MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0644, 0x0274, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0644, 0x0274, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0644, 0x0274, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0648, 0x0278, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0648, 0x0278, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0648, 0x0278, 2, 0x0810, 2, 0) -MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0648, 0x0278, 3, 0x08F0, 2, 0) -MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0648, 0x0278, 20, 0x089C, 1, 0) -MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0648, 0x0278, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0648, 0x0278, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x064C, 0x027C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x064C, 0x027C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x064C, 0x027C, 2, 0x0818, 2, 0) -MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x064C, 0x027C, 3, 0x08FC, 2, 0) -MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x064C, 0x027C, 20, 0x0898, 1, 0) -MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x064C, 0x027C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x064C, 0x027C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0650, 0x0280, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0650, 0x0280, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0650, 0x0280, 2, 0x0814, 2, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0650, 0x0280, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0650, 0x0280, 3, 0x0920, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0650, 0x0280, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0650, 0x0280, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0654, 0x0284, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0654, 0x0284, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0654, 0x0284, 2, 0x081C, 2, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0654, 0x0284, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0654, 0x0284, 3, 0x0920, 1, 0) -MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0654, 0x0284, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0654, 0x0284, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0658, 0x0288, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0658, 0x0288, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0658, 0x0288, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0658, 0x0288, 3, 0x0938, 2, 0) -MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0658, 0x0288, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0658, 0x0288, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x065C, 0x028C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x065C, 0x028C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x065C, 0x028C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x065C, 0x028C, 3, 0x0938, 3, 0) -MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x065C, 0x028C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x065C, 0x028C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0660, 0x0290, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0660, 0x0290, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0660, 0x0290, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0660, 0x0290, 3, 0x0940, 2, 0) -MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0660, 0x0290, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0660, 0x0290, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0664, 0x0294, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0664, 0x0294, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0664, 0x0294, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0664, 0x0294, 3, 0x0940, 3, 0) -MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0664, 0x0294, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0664, 0x0294, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0668, 0x0298, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0668, 0x0298, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0668, 0x0298, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0668, 0x0298, 3, 0x0934, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0668, 0x0298, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0668, 0x0298, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x066C, 0x029C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x066C, 0x029C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x066C, 0x029C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x066C, 0x029C, 3, 0x0934, 1, 0) -MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x066C, 0x029C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x066C, 0x029C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0670, 0x02A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0670, 0x02A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0670, 0x02A0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0670, 0x02A0, 3, 0x093C, 2, 0) -MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0670, 0x02A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0670, 0x02A0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0674, 0x02A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0674, 0x02A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0674, 0x02A4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0674, 0x02A4, 3, 0x093C, 3, 0) -MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0674, 0x02A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0690, 0x02A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0690, 0x02A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0690, 0x02A8, 1, 0x0920, 2, 0) -MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0690, 0x02A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0694, 0x02AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0694, 0x02AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0694, 0x02AC, 1, 0x0920, 3, 0) -MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0694, 0x02AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0698, 0x02B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0698, 0x02B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0698, 0x02B0, 1, 0x0928, 4, 0) -MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0698, 0x02B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) -MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) -MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06A4, 0x02BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06A4, 0x02BC, 1, 0x0924, 3, 0) -MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06A4, 0x02BC, 2, 0x07E4, 2, 0) -MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06A8, 0x02C0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06A8, 0x02C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06A8, 0x02C0, 1, 0x091C, 2, 0) -MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06A8, 0x02C0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x06AC, 0x02C4, 1, 0x091C, 3, 0) -MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x06AC, 0x02C4, 2, 0x07E8, 1, 0) -MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x06B4, 0x02CC, 1, 0x092C, 4, 0) -MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x06B8, 0x02D0, 1, 0x092C, 5, 0) -MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5, 0x06C4, 0x02DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x06C8, 0x02E0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01, 0x06C8, 0x02E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x06D0, 0x02E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x06D4, 0x02EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x06D4, 0x02EC, 2, 0x0874, 1, 0) -MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x06D8, 0x02F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0) -MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) -MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x06E0, 0x02F8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x06E0, 0x02F8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x06E0, 0x02F8, 2, 0x0930, 3, 0) -MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x06E4, 0x02FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x06E8, 0x0300, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x06E8, 0x0300, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x06E8, 0x0300, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x06EC, 0x0304, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x06EC, 0x0304, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x06EC, 0x0304, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x06F0, 0x0308, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x06F0, 0x0308, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x06F0, 0x0308, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x06F4, 0x030C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x06F4, 0x030C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x06F4, 0x030C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x06F8, 0x0310, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x06F8, 0x0310, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x06F8, 0x0310, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x06FC, 0x0314, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x06FC, 0x0314, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x06FC, 0x0314, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0700, 0x0318, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0700, 0x0318, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0700, 0x0318, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0704, 0x031C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0704, 0x031C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0704, 0x031C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x0708, 0x0320, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x0708, 0x0320, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x0708, 0x0320, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x070C, 0x0324, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x070C, 0x0324, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x070C, 0x0324, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0710, 0x0328, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0710, 0x0328, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0714, 0x032C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0714, 0x032C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0714, 0x032C, 2, 0x0928, 6, 0) -MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0714, 0x032C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x0718, 0x0330, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x0718, 0x0330, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x0718, 0x0330, 2, 0x0924, 4, 0) -MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x0718, 0x0330, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x071C, 0x0334, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x071C, 0x0334, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x071C, 0x0334, 2, 0x0924, 5, 0) -MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x071C, 0x0334, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0720, 0x0338, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0720, 0x0338, 2, 0x0928, 7, 0) -MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0720, 0x0338, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x0724, 0x033C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0, 0x0724, 0x033C, 1, 0x0834, 1, 0) -MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x0724, 0x033C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x0724, 0x033C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x0724, 0x033C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x0728, 0x0340, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO, 0x0728, 0x0340, 1, 0x082C, 1, 0) -MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x0728, 0x0340, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x0728, 0x0340, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x072C, 0x0344, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2, 0x072C, 0x0344, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x072C, 0x0344, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) -MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x0730, 0x0348, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x0734, 0x034C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1, 0x0734, 0x034C, 1, 0x0838, 1, 0) -MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x0734, 0x034C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x0734, 0x034C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x0734, 0x034C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x0734, 0x034C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x0734, 0x034C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK, 0x0738, 0x0350, 1, 0x0828, 0, 0) -MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x0738, 0x0350, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x0738, 0x0350, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0) -MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) -MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) -MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) -MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) -MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) -MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x0740, 0x0358, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x0744, 0x035C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3, 0x0744, 0x035C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x0744, 0x035C, 2, 0x08EC, 2, 0) -MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x0744, 0x035C, 3, 0x07C4, 1, 0) -MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x0744, 0x035C, 5, 0x0000, 0, 0) - -#endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h deleted file mode 100644 index d397c8a..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX6SL_DDR_H__ -#define __ASM_ARCH_MX6SL_DDR_H__ - -#ifndef CONFIG_MX6SL -#error "wrong CPU" -#endif - -#define MX6_IOM_DRAM_CAS_B 0x020e0300 -#define MX6_IOM_DRAM_CS0_B 0x020e0304 -#define MX6_IOM_DRAM_CS1_B 0x020e0308 - -#define MX6_IOM_DRAM_DQM0 0x020e030c -#define MX6_IOM_DRAM_DQM1 0x020e0310 -#define MX6_IOM_DRAM_DQM2 0x020e0314 -#define MX6_IOM_DRAM_DQM3 0x020e0318 - -#define MX6_IOM_DRAM_RAS_B 0x020e031c -#define MX6_IOM_DRAM_RESET 0x020e0320 - -#define MX6_IOM_DRAM_SDBA0 0x020e0324 -#define MX6_IOM_DRAM_SDBA1 0x020e0328 -#define MX6_IOM_DRAM_SDBA2 0x020e032c - -#define MX6_IOM_DRAM_SDCKE0 0x020e0330 -#define MX6_IOM_DRAM_SDCKE1 0x020e0334 - -#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338 - -#define MX6_IOM_DRAM_ODT0 0x020e033c -#define MX6_IOM_DRAM_ODT1 0x020e0340 - -#define MX6_IOM_DRAM_SDQS0_P 0x020e0344 -#define MX6_IOM_DRAM_SDQS1_P 0x020e0348 -#define MX6_IOM_DRAM_SDQS2_P 0x020e034c -#define MX6_IOM_DRAM_SDQS3_P 0x020e0350 - -#define MX6_IOM_DRAM_SDWE_B 0x020e0354 - -#endif /*__ASM_ARCH_MX6SL_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h deleted file mode 100644 index 01b14d7..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__ -#define __ASM_ARCH_MX6_MX6SL_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0), - MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), - MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), - MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT5__GPIO_5_9 = IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0), - MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0), - MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0), - MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0), - MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), - MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), - - MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0), - MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0), - MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0), - MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0), - MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0), - MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0), - MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0), - MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0), - MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), - MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), - - MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), - - MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0), - MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0), - MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), -}; -#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sll_pins.h b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h deleted file mode 100644 index e4bd4ef..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6sll_pins.h +++ /dev/null @@ -1,1018 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 - 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX6SLL_PINS_H__ -#define __ASM_ARCH_IMX6SLL_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0), - MX6_PAD_WDOG_B__WDOG1_RESET_B_DEB = IOMUX_PAD(0x02DC, 0x0014, 1, 0x0000, 0, 0), - MX6_PAD_WDOG_B__UART5_RI_B = IOMUX_PAD(0x02DC, 0x0014, 2, 0x0000, 0, 0), - MX6_PAD_WDOG_B__GPIO3_IO18 = IOMUX_PAD(0x02DC, 0x0014, 5, 0x0000, 0, 0), - - MX6_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x02E0, 0x0018, 0, 0x0000, 0, 0), - MX6_PAD_REF_CLK_24M__I2C3_SCL = IOMUX_PAD(0x02E0, 0x0018, IOMUX_CONFIG_SION | 1, 0x068C, 0, 0), - MX6_PAD_REF_CLK_24M__PWM3_OUT = IOMUX_PAD(0x02E0, 0x0018, 2, 0x0000, 0, 0), - MX6_PAD_REF_CLK_24M__USB_OTG2_ID = IOMUX_PAD(0x02E0, 0x0018, 3, 0x0560, 0, 0), - MX6_PAD_REF_CLK_24M__CCM_PMIC_READY = IOMUX_PAD(0x02E0, 0x0018, 4, 0x05AC, 0, 0), - MX6_PAD_REF_CLK_24M__GPIO3_IO21 = IOMUX_PAD(0x02E0, 0x0018, 5, 0x0000, 0, 0), - MX6_PAD_REF_CLK_24M__SD3_WP = IOMUX_PAD(0x02E0, 0x0018, 6, 0x0794, 0, 0), - - MX6_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x02E4, 0x001C, 0, 0x0000, 0, 0), - MX6_PAD_REF_CLK_32K__I2C3_SDA = IOMUX_PAD(0x02E4, 0x001C, IOMUX_CONFIG_SION | 1, 0x0690, 0, 0), - MX6_PAD_REF_CLK_32K__PWM4_OUT = IOMUX_PAD(0x02E4, 0x001C, 2, 0x0000, 0, 0), - MX6_PAD_REF_CLK_32K__USB_OTG1_ID = IOMUX_PAD(0x02E4, 0x001C, 3, 0x055C, 0, 0), - MX6_PAD_REF_CLK_32K__SD1_LCTL = IOMUX_PAD(0x02E4, 0x001C, 4, 0x0000, 0, 0), - MX6_PAD_REF_CLK_32K__GPIO3_IO22 = IOMUX_PAD(0x02E4, 0x001C, 5, 0x0000, 0, 0), - MX6_PAD_REF_CLK_32K__SD3_CD_B = IOMUX_PAD(0x02E4, 0x001C, 6, 0x0780, 0, 0), - - MX6_PAD_PWM1__PWM1_OUT = IOMUX_PAD(0x02E8, 0x0020, 0, 0x0000, 0, 0), - MX6_PAD_PWM1__CCM_CLKO = IOMUX_PAD(0x02E8, 0x0020, 1, 0x0000, 0, 0), - MX6_PAD_PWM1__AUDIO_CLK_OUT = IOMUX_PAD(0x02E8, 0x0020, 2, 0x0000, 0, 0), - MX6_PAD_PWM1__CSI_MCLK = IOMUX_PAD(0x02E8, 0x0020, 4, 0x0000, 0, 0), - MX6_PAD_PWM1__GPIO3_IO23 = IOMUX_PAD(0x02E8, 0x0020, 5, 0x0000, 0, 0), - MX6_PAD_PWM1__EPIT1_OUT = IOMUX_PAD(0x02E8, 0x0020, 6, 0x0000, 0, 0), - - MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x02EC, 0x0024, 0, 0x06A0, 0, 0), - MX6_PAD_KEY_COL0__I2C2_SCL = IOMUX_PAD(0x02EC, 0x0024, IOMUX_CONFIG_SION | 1, 0x0684, 0, 0), - MX6_PAD_KEY_COL0__LCD_DATA00 = IOMUX_PAD(0x02EC, 0x0024, 2, 0x06D8, 0, 0), - MX6_PAD_KEY_COL0__SD1_CD_B = IOMUX_PAD(0x02EC, 0x0024, 4, 0x0770, 1, 0), - MX6_PAD_KEY_COL0__GPIO3_IO24 = IOMUX_PAD(0x02EC, 0x0024, 5, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x02F0, 0x0028, 0, 0x06C0, 0, 0), - MX6_PAD_KEY_ROW0__I2C2_SDA = IOMUX_PAD(0x02F0, 0x0028, IOMUX_CONFIG_SION | 1, 0x0688, 0, 0), - MX6_PAD_KEY_ROW0__LCD_DATA01 = IOMUX_PAD(0x02F0, 0x0028, 2, 0x06DC, 0, 0), - MX6_PAD_KEY_ROW0__SD1_WP = IOMUX_PAD(0x02F0, 0x0028, 4, 0x0774, 1, 0), - MX6_PAD_KEY_ROW0__GPIO3_IO25 = IOMUX_PAD(0x02F0, 0x0028, 5, 0x0000, 0, 0), - - MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x02F4, 0x002C, 0, 0x06A4, 0, 0), - MX6_PAD_KEY_COL1__ECSPI4_MOSI = IOMUX_PAD(0x02F4, 0x002C, 1, 0x0658, 1, 0), - MX6_PAD_KEY_COL1__LCD_DATA02 = IOMUX_PAD(0x02F4, 0x002C, 2, 0x06E0, 0, 0), - MX6_PAD_KEY_COL1__SD3_DATA4 = IOMUX_PAD(0x02F4, 0x002C, 4, 0x0784, 0, 0), - MX6_PAD_KEY_COL1__GPIO3_IO26 = IOMUX_PAD(0x02F4, 0x002C, 5, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x02F8, 0x0030, 0, 0x06C4, 0, 0), - MX6_PAD_KEY_ROW1__ECSPI4_MISO = IOMUX_PAD(0x02F8, 0x0030, 1, 0x0654, 1, 0), - MX6_PAD_KEY_ROW1__LCD_DATA03 = IOMUX_PAD(0x02F8, 0x0030, 2, 0x06E4, 0, 0), - MX6_PAD_KEY_ROW1__CSI_FIELD = IOMUX_PAD(0x02F8, 0x0030, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SD3_DATA5 = IOMUX_PAD(0x02F8, 0x0030, 4, 0x0788, 0, 0), - MX6_PAD_KEY_ROW1__GPIO3_IO27 = IOMUX_PAD(0x02F8, 0x0030, 5, 0x0000, 0, 0), - - MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x02FC, 0x0034, 0, 0x06A8, 0, 0), - MX6_PAD_KEY_COL2__ECSPI4_SS0 = IOMUX_PAD(0x02FC, 0x0034, 1, 0x065C, 1, 0), - MX6_PAD_KEY_COL2__LCD_DATA04 = IOMUX_PAD(0x02FC, 0x0034, 2, 0x06E8, 0, 0), - MX6_PAD_KEY_COL2__CSI_DATA12 = IOMUX_PAD(0x02FC, 0x0034, 3, 0x05B8, 1, 0), - MX6_PAD_KEY_COL2__SD3_DATA6 = IOMUX_PAD(0x02FC, 0x0034, 4, 0x078C, 0, 0), - MX6_PAD_KEY_COL2__GPIO3_IO28 = IOMUX_PAD(0x02FC, 0x0034, 5, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0300, 0x0038, 0, 0x06C8, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI4_SCLK = IOMUX_PAD(0x0300, 0x0038, 1, 0x0650, 1, 0), - MX6_PAD_KEY_ROW2__LCD_DATA05 = IOMUX_PAD(0x0300, 0x0038, 2, 0x06EC, 0, 0), - MX6_PAD_KEY_ROW2__CSI_DATA13 = IOMUX_PAD(0x0300, 0x0038, 3, 0x05BC, 1, 0), - MX6_PAD_KEY_ROW2__SD3_DATA7 = IOMUX_PAD(0x0300, 0x0038, 4, 0x0790, 0, 0), - MX6_PAD_KEY_ROW2__GPIO3_IO29 = IOMUX_PAD(0x0300, 0x0038, 5, 0x0000, 0, 0), - - MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0304, 0x003C, 0, 0x06AC, 0, 0), - MX6_PAD_KEY_COL3__AUD6_RXFS = IOMUX_PAD(0x0304, 0x003C, 1, 0x05A0, 1, 0), - MX6_PAD_KEY_COL3__LCD_DATA06 = IOMUX_PAD(0x0304, 0x003C, 2, 0x06F0, 0, 0), - MX6_PAD_KEY_COL3__CSI_DATA14 = IOMUX_PAD(0x0304, 0x003C, 3, 0x05C0, 1, 0), - MX6_PAD_KEY_COL3__GPIO3_IO30 = IOMUX_PAD(0x0304, 0x003C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SD1_RESET = IOMUX_PAD(0x0304, 0x003C, 6, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x0308, 0x0040, 0, 0x06CC, 1, 0), - MX6_PAD_KEY_ROW3__AUD6_RXC = IOMUX_PAD(0x0308, 0x0040, 1, 0x059C, 1, 0), - MX6_PAD_KEY_ROW3__LCD_DATA07 = IOMUX_PAD(0x0308, 0x0040, 2, 0x06F4, 1, 0), - MX6_PAD_KEY_ROW3__CSI_DATA15 = IOMUX_PAD(0x0308, 0x0040, 3, 0x05C4, 2, 0), - MX6_PAD_KEY_ROW3__GPIO3_IO31 = IOMUX_PAD(0x0308, 0x0040, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x0308, 0x0040, 6, 0x0000, 0, 0), - - MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x030C, 0x0044, 0, 0x06B0, 1, 0), - MX6_PAD_KEY_COL4__AUD6_RXD = IOMUX_PAD(0x030C, 0x0044, 1, 0x0594, 1, 0), - MX6_PAD_KEY_COL4__LCD_DATA08 = IOMUX_PAD(0x030C, 0x0044, 2, 0x06F8, 1, 0), - MX6_PAD_KEY_COL4__CSI_DATA16 = IOMUX_PAD(0x030C, 0x0044, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__GPIO4_IO00 = IOMUX_PAD(0x030C, 0x0044, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USB_OTG1_PWR = IOMUX_PAD(0x030C, 0x0044, 6, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0310, 0x0048, 0, 0x06D0, 1, 0), - MX6_PAD_KEY_ROW4__AUD6_TXC = IOMUX_PAD(0x0310, 0x0048, 1, 0x05A4, 1, 0), - MX6_PAD_KEY_ROW4__LCD_DATA09 = IOMUX_PAD(0x0310, 0x0048, 2, 0x06FC, 1, 0), - MX6_PAD_KEY_ROW4__CSI_DATA17 = IOMUX_PAD(0x0310, 0x0048, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__GPIO4_IO01 = IOMUX_PAD(0x0310, 0x0048, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USB_OTG1_OC = IOMUX_PAD(0x0310, 0x0048, 6, 0x076C, 2, 0), - - MX6_PAD_KEY_COL5__KEY_COL5 = IOMUX_PAD(0x0314, 0x004C, 0, 0x0694, 1, 0), - MX6_PAD_KEY_COL5__AUD6_TXFS = IOMUX_PAD(0x0314, 0x004C, 1, 0x05A8, 1, 0), - MX6_PAD_KEY_COL5__LCD_DATA10 = IOMUX_PAD(0x0314, 0x004C, 2, 0x0700, 0, 0), - MX6_PAD_KEY_COL5__CSI_DATA18 = IOMUX_PAD(0x0314, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL5__GPIO4_IO02 = IOMUX_PAD(0x0314, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL5__USB_OTG2_PWR = IOMUX_PAD(0x0314, 0x004C, 6, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW5__KEY_ROW5 = IOMUX_PAD(0x0318, 0x0050, 0, 0x06B4, 2, 0), - MX6_PAD_KEY_ROW5__AUD6_TXD = IOMUX_PAD(0x0318, 0x0050, 1, 0x0598, 1, 0), - MX6_PAD_KEY_ROW5__LCD_DATA11 = IOMUX_PAD(0x0318, 0x0050, 2, 0x0704, 1, 0), - MX6_PAD_KEY_ROW5__CSI_DATA19 = IOMUX_PAD(0x0318, 0x0050, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW5__GPIO4_IO03 = IOMUX_PAD(0x0318, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW5__USB_OTG2_OC = IOMUX_PAD(0x0318, 0x0050, 6, 0x0768, 3, 0), - - MX6_PAD_KEY_COL6__KEY_COL6 = IOMUX_PAD(0x031C, 0x0054, 0, 0x0698, 2, 0), - MX6_PAD_KEY_COL6__UART4_DCE_RX = IOMUX_PAD(0x031C, 0x0054, 1, 0x075C, 2, 0), - MX6_PAD_KEY_COL6__UART4_DTE_TX = IOMUX_PAD(0x031C, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL6__LCD_DATA12 = IOMUX_PAD(0x031C, 0x0054, 2, 0x0708, 1, 0), - MX6_PAD_KEY_COL6__CSI_DATA20 = IOMUX_PAD(0x031C, 0x0054, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL6__GPIO4_IO04 = IOMUX_PAD(0x031C, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL6__SD3_RESET = IOMUX_PAD(0x031C, 0x0054, 6, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW6__KEY_ROW6 = IOMUX_PAD(0x0320, 0x0058, 0, 0x06B8, 2, 0), - MX6_PAD_KEY_ROW6__UART4_DCE_TX = IOMUX_PAD(0x0320, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW6__UART4_DTE_RX = IOMUX_PAD(0x0320, 0x0058, 1, 0x075C, 3, 0), - MX6_PAD_KEY_ROW6__LCD_DATA13 = IOMUX_PAD(0x0320, 0x0058, 2, 0x070C, 1, 0), - MX6_PAD_KEY_ROW6__CSI_DATA21 = IOMUX_PAD(0x0320, 0x0058, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW6__GPIO4_IO05 = IOMUX_PAD(0x0320, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW6__SD3_VSELECT = IOMUX_PAD(0x0320, 0x0058, 6, 0x0000, 0, 0), - - MX6_PAD_KEY_COL7__KEY_COL7 = IOMUX_PAD(0x0324, 0x005C, 0, 0x069C, 2, 0), - MX6_PAD_KEY_COL7__UART4_DCE_RTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0758, 2, 0), - MX6_PAD_KEY_COL7__UART4_DTE_CTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL7__LCD_DATA14 = IOMUX_PAD(0x0324, 0x005C, 2, 0x0710, 1, 0), - MX6_PAD_KEY_COL7__CSI_DATA22 = IOMUX_PAD(0x0324, 0x005C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL7__GPIO4_IO06 = IOMUX_PAD(0x0324, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL7__SD1_WP = IOMUX_PAD(0x0324, 0x005C, 6, 0x0774, 3, 0), - - MX6_PAD_KEY_ROW7__KEY_ROW7 = IOMUX_PAD(0x0328, 0x0060, 0, 0x06BC, 2, 0), - MX6_PAD_KEY_ROW7__UART4_DCE_CTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW7__UART4_DTE_RTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0758, 3, 0), - MX6_PAD_KEY_ROW7__LCD_DATA15 = IOMUX_PAD(0x0328, 0x0060, 2, 0x0714, 1, 0), - MX6_PAD_KEY_ROW7__CSI_DATA23 = IOMUX_PAD(0x0328, 0x0060, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW7__GPIO4_IO07 = IOMUX_PAD(0x0328, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW7__SD1_CD_B = IOMUX_PAD(0x0328, 0x0060, 6, 0x0770, 3, 0), - - MX6_PAD_EPDC_DATA00__EPDC_DATA00 = IOMUX_PAD(0x032C, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA00__ECSPI4_MOSI = IOMUX_PAD(0x032C, 0x0064, 1, 0x0658, 2, 0), - MX6_PAD_EPDC_DATA00__LCD_DATA24 = IOMUX_PAD(0x032C, 0x0064, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA00__CSI_DATA00 = IOMUX_PAD(0x032C, 0x0064, 3, 0x05C8, 2, 0), - MX6_PAD_EPDC_DATA00__GPIO1_IO07 = IOMUX_PAD(0x032C, 0x0064, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA01__EPDC_DATA01 = IOMUX_PAD(0x0330, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA01__ECSPI4_MISO = IOMUX_PAD(0x0330, 0x0068, 1, 0x0654, 2, 0), - MX6_PAD_EPDC_DATA01__LCD_DATA25 = IOMUX_PAD(0x0330, 0x0068, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA01__CSI_DATA01 = IOMUX_PAD(0x0330, 0x0068, 3, 0x05CC, 2, 0), - MX6_PAD_EPDC_DATA01__GPIO1_IO08 = IOMUX_PAD(0x0330, 0x0068, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA02__EPDC_DATA02 = IOMUX_PAD(0x0334, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA02__ECSPI4_SS0 = IOMUX_PAD(0x0334, 0x006C, 1, 0x065C, 2, 0), - MX6_PAD_EPDC_DATA02__LCD_DATA26 = IOMUX_PAD(0x0334, 0x006C, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA02__CSI_DATA02 = IOMUX_PAD(0x0334, 0x006C, 3, 0x05D0, 2, 0), - MX6_PAD_EPDC_DATA02__GPIO1_IO09 = IOMUX_PAD(0x0334, 0x006C, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA03__EPDC_DATA03 = IOMUX_PAD(0x0338, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA03__ECSPI4_SCLK = IOMUX_PAD(0x0338, 0x0070, 1, 0x0650, 2, 0), - MX6_PAD_EPDC_DATA03__LCD_DATA27 = IOMUX_PAD(0x0338, 0x0070, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA03__CSI_DATA03 = IOMUX_PAD(0x0338, 0x0070, 3, 0x05D4, 2, 0), - MX6_PAD_EPDC_DATA03__GPIO1_IO10 = IOMUX_PAD(0x0338, 0x0070, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA04__EPDC_DATA04 = IOMUX_PAD(0x033C, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA04__ECSPI4_SS1 = IOMUX_PAD(0x033C, 0x0074, 1, 0x0660, 1, 0), - MX6_PAD_EPDC_DATA04__LCD_DATA28 = IOMUX_PAD(0x033C, 0x0074, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA04__CSI_DATA04 = IOMUX_PAD(0x033C, 0x0074, 3, 0x05D8, 2, 0), - MX6_PAD_EPDC_DATA04__GPIO1_IO11 = IOMUX_PAD(0x033C, 0x0074, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA05__EPDC_DATA05 = IOMUX_PAD(0x0340, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA05__ECSPI4_SS2 = IOMUX_PAD(0x0340, 0x0078, 1, 0x0664, 1, 0), - MX6_PAD_EPDC_DATA05__LCD_DATA29 = IOMUX_PAD(0x0340, 0x0078, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA05__CSI_DATA05 = IOMUX_PAD(0x0340, 0x0078, 3, 0x05DC, 2, 0), - MX6_PAD_EPDC_DATA05__GPIO1_IO12 = IOMUX_PAD(0x0340, 0x0078, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA06__EPDC_DATA06 = IOMUX_PAD(0x0344, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA06__ECSPI4_SS3 = IOMUX_PAD(0x0344, 0x007C, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA06__LCD_DATA30 = IOMUX_PAD(0x0344, 0x007C, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA06__CSI_DATA06 = IOMUX_PAD(0x0344, 0x007C, 3, 0x05E0, 2, 0), - MX6_PAD_EPDC_DATA06__GPIO1_IO13 = IOMUX_PAD(0x0344, 0x007C, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA07__EPDC_DATA07 = IOMUX_PAD(0x0348, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA07__ECSPI4_RDY = IOMUX_PAD(0x0348, 0x0080, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA07__LCD_DATA31 = IOMUX_PAD(0x0348, 0x0080, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA07__CSI_DATA07 = IOMUX_PAD(0x0348, 0x0080, 3, 0x05E4, 2, 0), - MX6_PAD_EPDC_DATA07__GPIO1_IO14 = IOMUX_PAD(0x0348, 0x0080, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA08__EPDC_DATA08 = IOMUX_PAD(0x034C, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA08__ECSPI3_MOSI = IOMUX_PAD(0x034C, 0x0084, 1, 0x063C, 2, 0), - MX6_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 = IOMUX_PAD(0x034C, 0x0084, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA08__GPIO1_IO15 = IOMUX_PAD(0x034C, 0x0084, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA09__EPDC_DATA09 = IOMUX_PAD(0x0350, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA09__ECSPI3_MISO = IOMUX_PAD(0x0350, 0x0088, 1, 0x0638, 2, 0), - MX6_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 = IOMUX_PAD(0x0350, 0x0088, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA09__GPIO1_IO16 = IOMUX_PAD(0x0350, 0x0088, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x0354, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA10__ECSPI3_SS0 = IOMUX_PAD(0x0354, 0x008C, 1, 0x0648, 2, 0), - MX6_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 = IOMUX_PAD(0x0354, 0x008C, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA10__GPIO1_IO17 = IOMUX_PAD(0x0354, 0x008C, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x0358, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA11__ECSPI3_SCLK = IOMUX_PAD(0x0358, 0x0090, 1, 0x0630, 2, 0), - MX6_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0358, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA11__GPIO1_IO18 = IOMUX_PAD(0x0358, 0x0090, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x035C, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA12__UART2_DCE_RX = IOMUX_PAD(0x035C, 0x0094, 1, 0x074C, 4, 0), - MX6_PAD_EPDC_DATA12__UART2_DTE_TX = IOMUX_PAD(0x035C, 0x0094, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA12__EPDC_PWR_COM = IOMUX_PAD(0x035C, 0x0094, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA12__GPIO1_IO19 = IOMUX_PAD(0x035C, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA12__ECSPI3_SS1 = IOMUX_PAD(0x035C, 0x0094, 6, 0x064C, 1, 0), - - MX6_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x0360, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA13__UART2_DCE_TX = IOMUX_PAD(0x0360, 0x0098, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA13__UART2_DTE_RX = IOMUX_PAD(0x0360, 0x0098, 1, 0x074C, 5, 0), - MX6_PAD_EPDC_DATA13__EPDC_PWR_IRQ = IOMUX_PAD(0x0360, 0x0098, 2, 0x0668, 0, 0), - MX6_PAD_EPDC_DATA13__GPIO1_IO20 = IOMUX_PAD(0x0360, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA13__ECSPI3_SS2 = IOMUX_PAD(0x0360, 0x0098, 6, 0x0640, 1, 0), - - MX6_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x0364, 0x009C, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA14__UART2_DCE_RTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0748, 4, 0), - MX6_PAD_EPDC_DATA14__UART2_DTE_CTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA14__EPDC_PWR_STAT = IOMUX_PAD(0x0364, 0x009C, 2, 0x066C, 0, 0), - MX6_PAD_EPDC_DATA14__GPIO1_IO21 = IOMUX_PAD(0x0364, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA14__ECSPI3_SS3 = IOMUX_PAD(0x0364, 0x009C, 6, 0x0644, 1, 0), - - MX6_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x0368, 0x00A0, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA15__UART2_DCE_CTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA15__UART2_DTE_RTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0748, 5, 0), - MX6_PAD_EPDC_DATA15__EPDC_PWR_WAKE = IOMUX_PAD(0x0368, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA15__GPIO1_IO22 = IOMUX_PAD(0x0368, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_DATA15__ECSPI3_RDY = IOMUX_PAD(0x0368, 0x00A0, 6, 0x0634, 1, 0), - - MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P = IOMUX_PAD(0x036C, 0x00A4, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI = IOMUX_PAD(0x036C, 0x00A4, 1, 0x0624, 2, 0), - MX6_PAD_EPDC_SDCLK__I2C2_SCL = IOMUX_PAD(0x036C, 0x00A4, IOMUX_CONFIG_SION | 2, 0x0684, 2, 0), - MX6_PAD_EPDC_SDCLK__CSI_DATA08 = IOMUX_PAD(0x036C, 0x00A4, 3, 0x05E8, 2, 0), - MX6_PAD_EPDC_SDCLK__GPIO1_IO23 = IOMUX_PAD(0x036C, 0x00A4, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0370, 0x00A8, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDLE__ECSPI2_MISO = IOMUX_PAD(0x0370, 0x00A8, 1, 0x0620, 2, 0), - MX6_PAD_EPDC_SDLE__I2C2_SDA = IOMUX_PAD(0x0370, 0x00A8, IOMUX_CONFIG_SION | 2, 0x0688, 2, 0), - MX6_PAD_EPDC_SDLE__CSI_DATA09 = IOMUX_PAD(0x0370, 0x00A8, 3, 0x05EC, 2, 0), - MX6_PAD_EPDC_SDLE__GPIO1_IO24 = IOMUX_PAD(0x0370, 0x00A8, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0374, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDOE__ECSPI2_SS0 = IOMUX_PAD(0x0374, 0x00AC, 1, 0x0628, 1, 0), - MX6_PAD_EPDC_SDOE__CSI_DATA10 = IOMUX_PAD(0x0374, 0x00AC, 3, 0x05B0, 2, 0), - MX6_PAD_EPDC_SDOE__GPIO1_IO25 = IOMUX_PAD(0x0374, 0x00AC, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x0378, 0x00B0, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK = IOMUX_PAD(0x0378, 0x00B0, 1, 0x061C, 2, 0), - MX6_PAD_EPDC_SDSHR__EPDC_SDCE4 = IOMUX_PAD(0x0378, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_SDSHR__CSI_DATA11 = IOMUX_PAD(0x0378, 0x00B0, 3, 0x05B4, 2, 0), - MX6_PAD_EPDC_SDSHR__GPIO1_IO26 = IOMUX_PAD(0x0378, 0x00B0, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x037C, 0x00B4, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE0__ECSPI2_SS1 = IOMUX_PAD(0x037C, 0x00B4, 1, 0x062C, 1, 0), - MX6_PAD_EPDC_SDCE0__PWM3_OUT = IOMUX_PAD(0x037C, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE0__GPIO1_IO27 = IOMUX_PAD(0x037C, 0x00B4, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x0380, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE1__WDOG2_B = IOMUX_PAD(0x0380, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE1__PWM4_OUT = IOMUX_PAD(0x0380, 0x00B8, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE1__GPIO1_IO28 = IOMUX_PAD(0x0380, 0x00B8, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x0384, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE2__I2C3_SCL = IOMUX_PAD(0x0384, 0x00BC, IOMUX_CONFIG_SION | 1, 0x068C, 2, 0), - MX6_PAD_EPDC_SDCE2__PWM1_OUT = IOMUX_PAD(0x0384, 0x00BC, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE2__GPIO1_IO29 = IOMUX_PAD(0x0384, 0x00BC, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0388, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE3__I2C3_SDA = IOMUX_PAD(0x0388, 0x00C0, IOMUX_CONFIG_SION | 1, 0x0690, 2, 0), - MX6_PAD_EPDC_SDCE3__PWM2_OUT = IOMUX_PAD(0x0388, 0x00C0, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_SDCE3__GPIO1_IO30 = IOMUX_PAD(0x0388, 0x00C0, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x038C, 0x00C4, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_GDCLK__ECSPI2_SS2 = IOMUX_PAD(0x038C, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_GDCLK__CSI_PIXCLK = IOMUX_PAD(0x038C, 0x00C4, 3, 0x05F4, 2, 0), - MX6_PAD_EPDC_GDCLK__GPIO1_IO31 = IOMUX_PAD(0x038C, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_GDCLK__SD2_RESET = IOMUX_PAD(0x038C, 0x00C4, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0390, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_GDOE__ECSPI2_SS3 = IOMUX_PAD(0x0390, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_GDOE__CSI_HSYNC = IOMUX_PAD(0x0390, 0x00C8, 3, 0x05F0, 2, 0), - MX6_PAD_EPDC_GDOE__GPIO2_IO00 = IOMUX_PAD(0x0390, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_GDOE__SD2_VSELECT = IOMUX_PAD(0x0390, 0x00C8, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x0394, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_GDRL__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_GDRL__CSI_MCLK = IOMUX_PAD(0x0394, 0x00CC, 3, 0x0000, 0, 0), - MX6_PAD_EPDC_GDRL__GPIO2_IO01 = IOMUX_PAD(0x0394, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_GDRL__SD2_WP = IOMUX_PAD(0x0394, 0x00CC, 6, 0x077C, 2, 0), - - MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0398, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_GDSP__PWM4_OUT = IOMUX_PAD(0x0398, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_EPDC_GDSP__CSI_VSYNC = IOMUX_PAD(0x0398, 0x00D0, 3, 0x05F8, 2, 0), - MX6_PAD_EPDC_GDSP__GPIO2_IO02 = IOMUX_PAD(0x0398, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_GDSP__SD2_CD_B = IOMUX_PAD(0x0398, 0x00D0, 6, 0x0778, 2, 0), - - MX6_PAD_EPDC_VCOM0__EPDC_VCOM0 = IOMUX_PAD(0x039C, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_VCOM0__AUD5_RXFS = IOMUX_PAD(0x039C, 0x00D4, 1, 0x0588, 1, 0), - MX6_PAD_EPDC_VCOM0__UART3_DCE_RX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0754, 4, 0), - MX6_PAD_EPDC_VCOM0__UART3_DTE_TX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_VCOM0__GPIO2_IO03 = IOMUX_PAD(0x039C, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_VCOM0__EPDC_SDCE5 = IOMUX_PAD(0x039C, 0x00D4, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_VCOM1__EPDC_VCOM1 = IOMUX_PAD(0x03A0, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_VCOM1__AUD5_RXD = IOMUX_PAD(0x03A0, 0x00D8, 1, 0x057C, 1, 0), - MX6_PAD_EPDC_VCOM1__UART3_DCE_TX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_VCOM1__UART3_DTE_RX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0754, 5, 0), - MX6_PAD_EPDC_VCOM1__GPIO2_IO04 = IOMUX_PAD(0x03A0, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_VCOM1__EPDC_SDCE6 = IOMUX_PAD(0x03A0, 0x00D8, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x03A4, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_BDR0__UART3_DCE_RTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0750, 2, 0), - MX6_PAD_EPDC_BDR0__UART3_DTE_CTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_BDR0__GPIO2_IO05 = IOMUX_PAD(0x03A4, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_BDR0__EPDC_SDCE7 = IOMUX_PAD(0x03A4, 0x00DC, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x03A8, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_BDR1__UART3_DCE_CTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0000, 0, 0), - MX6_PAD_EPDC_BDR1__UART3_DTE_RTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0750, 3, 0), - MX6_PAD_EPDC_BDR1__GPIO2_IO06 = IOMUX_PAD(0x03A8, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_BDR1__EPDC_SDCE8 = IOMUX_PAD(0x03A8, 0x00E0, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03AC, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_CTRL0__AUD5_RXC = IOMUX_PAD(0x03AC, 0x00E4, 1, 0x0584, 1, 0), - MX6_PAD_EPDC_PWR_CTRL0__LCD_DATA16 = IOMUX_PAD(0x03AC, 0x00E4, 2, 0x0718, 1, 0), - MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 = IOMUX_PAD(0x03AC, 0x00E4, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03B0, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_CTRL1__AUD5_TXFS = IOMUX_PAD(0x03B0, 0x00E8, 1, 0x0590, 1, 0), - MX6_PAD_EPDC_PWR_CTRL1__LCD_DATA17 = IOMUX_PAD(0x03B0, 0x00E8, 2, 0x071C, 1, 0), - MX6_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 = IOMUX_PAD(0x03B0, 0x00E8, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03B4, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_CTRL2__AUD5_TXD = IOMUX_PAD(0x03B4, 0x00EC, 1, 0x0580, 1, 0), - MX6_PAD_EPDC_PWR_CTRL2__LCD_DATA18 = IOMUX_PAD(0x03B4, 0x00EC, 2, 0x0720, 1, 0), - MX6_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 = IOMUX_PAD(0x03B4, 0x00EC, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03B8, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_CTRL3__AUD5_TXC = IOMUX_PAD(0x03B8, 0x00F0, 1, 0x058C, 1, 0), - MX6_PAD_EPDC_PWR_CTRL3__LCD_DATA19 = IOMUX_PAD(0x03B8, 0x00F0, 2, 0x0724, 1, 0), - MX6_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 = IOMUX_PAD(0x03B8, 0x00F0, 5, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x03BC, 0x00F4, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_COM__LCD_DATA20 = IOMUX_PAD(0x03BC, 0x00F4, 2, 0x0728, 1, 0), - MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID = IOMUX_PAD(0x03BC, 0x00F4, 4, 0x055C, 4, 0), - MX6_PAD_EPDC_PWR_COM__GPIO2_IO11 = IOMUX_PAD(0x03BC, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_COM__SD3_RESET = IOMUX_PAD(0x03BC, 0x00F4, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ = IOMUX_PAD(0x03C0, 0x00F8, 0, 0x0668, 1, 0), - MX6_PAD_EPDC_PWR_IRQ__LCD_DATA21 = IOMUX_PAD(0x03C0, 0x00F8, 2, 0x072C, 1, 0), - MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID = IOMUX_PAD(0x03C0, 0x00F8, 4, 0x0560, 3, 0), - MX6_PAD_EPDC_PWR_IRQ__GPIO2_IO12 = IOMUX_PAD(0x03C0, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_IRQ__SD3_VSELECT = IOMUX_PAD(0x03C0, 0x00F8, 6, 0x0000, 0, 0), - - MX6_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x03C4, 0x00FC, 0, 0x066C, 1, 0), - MX6_PAD_EPDC_PWR_STAT__LCD_DATA22 = IOMUX_PAD(0x03C4, 0x00FC, 2, 0x0730, 1, 0), - MX6_PAD_EPDC_PWR_STAT__ARM_EVENTI = IOMUX_PAD(0x03C4, 0x00FC, 4, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 = IOMUX_PAD(0x03C4, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_STAT__SD3_WP = IOMUX_PAD(0x03C4, 0x00FC, 6, 0x0794, 2, 0), - - MX6_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE = IOMUX_PAD(0x03C8, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_WAKE__LCD_DATA23 = IOMUX_PAD(0x03C8, 0x0100, 2, 0x0734, 1, 0), - MX6_PAD_EPDC_PWR_WAKE__ARM_EVENTO = IOMUX_PAD(0x03C8, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 = IOMUX_PAD(0x03C8, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_PWR_WAKE__SD3_CD_B = IOMUX_PAD(0x03C8, 0x0100, 6, 0x0780, 2, 0), - - MX6_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x03CC, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__LCD_WR_RWN = IOMUX_PAD(0x03CC, 0x0104, 2, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__PWM4_OUT = IOMUX_PAD(0x03CC, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__GPIO2_IO15 = IOMUX_PAD(0x03CC, 0x0104, 5, 0x0000, 0, 0), - - MX6_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x03D0, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__LCD_RD_E = IOMUX_PAD(0x03D0, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__UART2_DCE_RX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__UART2_DTE_TX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__GPIO2_IO16 = IOMUX_PAD(0x03D0, 0x0108, 5, 0x0000, 0, 0), - - MX6_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x03D4, 0x010C, 0, 0x06D4, 0, 0), - MX6_PAD_LCD_HSYNC__LCD_CS = IOMUX_PAD(0x03D4, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__UART2_DCE_TX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__UART2_DTE_RX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x074C, 1, 0), - MX6_PAD_LCD_HSYNC__GPIO2_IO17 = IOMUX_PAD(0x03D4, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__ARM_TRACE_CLK = IOMUX_PAD(0x03D4, 0x010C, 6, 0x0000, 0, 0), - - MX6_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x03D8, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__LCD_RS = IOMUX_PAD(0x03D8, 0x0110, 2, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__UART2_DCE_RTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0748, 0, 0), - MX6_PAD_LCD_VSYNC__UART2_DTE_CTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__GPIO2_IO18 = IOMUX_PAD(0x03D8, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__ARM_TRACE_CTL = IOMUX_PAD(0x03D8, 0x0110, 6, 0x0000, 0, 0), - - MX6_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x03DC, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__LCD_BUSY = IOMUX_PAD(0x03DC, 0x0114, 2, 0x06D4, 1, 0), - MX6_PAD_LCD_RESET__UART2_DCE_CTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__UART2_DTE_RTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0748, 1, 0), - MX6_PAD_LCD_RESET__GPIO2_IO19 = IOMUX_PAD(0x03DC, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__CCM_PMIC_READY = IOMUX_PAD(0x03DC, 0x0114, 6, 0x05AC, 2, 0), - - MX6_PAD_LCD_DATA00__LCD_DATA00 = IOMUX_PAD(0x03E0, 0x0118, 0, 0x06D8, 1, 0), - MX6_PAD_LCD_DATA00__ECSPI1_MOSI = IOMUX_PAD(0x03E0, 0x0118, 1, 0x0608, 0, 0), - MX6_PAD_LCD_DATA00__USB_OTG2_ID = IOMUX_PAD(0x03E0, 0x0118, 2, 0x0560, 2, 0), - MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03E0, 0x0118, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__UART5_DTR_B = IOMUX_PAD(0x03E0, 0x0118, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__GPIO2_IO20 = IOMUX_PAD(0x03E0, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__ARM_TRACE00 = IOMUX_PAD(0x03E0, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__SRC_BOOT_CFG00 = IOMUX_PAD(0x03E0, 0x0118, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA01__LCD_DATA01 = IOMUX_PAD(0x03E4, 0x011C, 0, 0x06DC, 1, 0), - MX6_PAD_LCD_DATA01__ECSPI1_MISO = IOMUX_PAD(0x03E4, 0x011C, 1, 0x0604, 0, 0), - MX6_PAD_LCD_DATA01__USB_OTG1_ID = IOMUX_PAD(0x03E4, 0x011C, 2, 0x055C, 3, 0), - MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03E4, 0x011C, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__AUD4_RXFS = IOMUX_PAD(0x03E4, 0x011C, 4, 0x0570, 0, 0), - MX6_PAD_LCD_DATA01__GPIO2_IO21 = IOMUX_PAD(0x03E4, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__ARM_TRACE01 = IOMUX_PAD(0x03E4, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__SRC_BOOT_CFG01 = IOMUX_PAD(0x03E4, 0x011C, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA02__LCD_DATA02 = IOMUX_PAD(0x03E8, 0x0120, 0, 0x06E0, 1, 0), - MX6_PAD_LCD_DATA02__ECSPI1_SS0 = IOMUX_PAD(0x03E8, 0x0120, 1, 0x0614, 0, 0), - MX6_PAD_LCD_DATA02__EPIT2_OUT = IOMUX_PAD(0x03E8, 0x0120, 2, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03E8, 0x0120, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__AUD4_RXC = IOMUX_PAD(0x03E8, 0x0120, 4, 0x056C, 0, 0), - MX6_PAD_LCD_DATA02__GPIO2_IO22 = IOMUX_PAD(0x03E8, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__ARM_TRACE02 = IOMUX_PAD(0x03E8, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__SRC_BOOT_CFG02 = IOMUX_PAD(0x03E8, 0x0120, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA03__LCD_DATA03 = IOMUX_PAD(0x03EC, 0x0124, 0, 0x06E4, 1, 0), - MX6_PAD_LCD_DATA03__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x0124, 1, 0x05FC, 0, 0), - MX6_PAD_LCD_DATA03__UART5_DSR_B = IOMUX_PAD(0x03EC, 0x0124, 2, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03EC, 0x0124, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__AUD4_RXD = IOMUX_PAD(0x03EC, 0x0124, 4, 0x0564, 0, 0), - MX6_PAD_LCD_DATA03__GPIO2_IO23 = IOMUX_PAD(0x03EC, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__ARM_TRACE03 = IOMUX_PAD(0x03EC, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__SRC_BOOT_CFG03 = IOMUX_PAD(0x03EC, 0x0124, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA04__LCD_DATA04 = IOMUX_PAD(0x03F0, 0x0128, 0, 0x06E8, 1, 0), - MX6_PAD_LCD_DATA04__ECSPI1_SS1 = IOMUX_PAD(0x03F0, 0x0128, 1, 0x060C, 1, 0), - MX6_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x03F0, 0x0128, 2, 0x05F8, 0, 0), - MX6_PAD_LCD_DATA04__WDOG2_RESET_B_DEB = IOMUX_PAD(0x03F0, 0x0128, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__AUD4_TXC = IOMUX_PAD(0x03F0, 0x0128, 4, 0x0574, 0, 0), - MX6_PAD_LCD_DATA04__GPIO2_IO24 = IOMUX_PAD(0x03F0, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__ARM_TRACE04 = IOMUX_PAD(0x03F0, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__SRC_BOOT_CFG04 = IOMUX_PAD(0x03F0, 0x0128, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA05__LCD_DATA05 = IOMUX_PAD(0x03F4, 0x012C, 0, 0x06EC, 1, 0), - MX6_PAD_LCD_DATA05__ECSPI1_SS2 = IOMUX_PAD(0x03F4, 0x012C, 1, 0x0610, 1, 0), - MX6_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x03F4, 0x012C, 2, 0x05F0, 0, 0), - MX6_PAD_LCD_DATA05__AUD4_TXFS = IOMUX_PAD(0x03F4, 0x012C, 4, 0x0578, 0, 0), - MX6_PAD_LCD_DATA05__GPIO2_IO25 = IOMUX_PAD(0x03F4, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__ARM_TRACE05 = IOMUX_PAD(0x03F4, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__SRC_BOOT_CFG05 = IOMUX_PAD(0x03F4, 0x012C, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA06__LCD_DATA06 = IOMUX_PAD(0x03F8, 0x0130, 0, 0x06F0, 1, 0), - MX6_PAD_LCD_DATA06__ECSPI1_SS3 = IOMUX_PAD(0x03F8, 0x0130, 1, 0x0618, 0, 0), - MX6_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x03F8, 0x0130, 2, 0x05F4, 0, 0), - MX6_PAD_LCD_DATA06__AUD4_TXD = IOMUX_PAD(0x03F8, 0x0130, 4, 0x0568, 0, 0), - MX6_PAD_LCD_DATA06__GPIO2_IO26 = IOMUX_PAD(0x03F8, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__ARM_TRACE06 = IOMUX_PAD(0x03F8, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__SRC_BOOT_CFG06 = IOMUX_PAD(0x03F8, 0x0130, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA07__LCD_DATA07 = IOMUX_PAD(0x03FC, 0x0134, 0, 0x06F4, 0, 0), - MX6_PAD_LCD_DATA07__ECSPI1_RDY = IOMUX_PAD(0x03FC, 0x0134, 1, 0x0600, 0, 0), - MX6_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x03FC, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__AUDIO_CLK_OUT = IOMUX_PAD(0x03FC, 0x0134, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__GPIO2_IO27 = IOMUX_PAD(0x03FC, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__ARM_TRACE07 = IOMUX_PAD(0x03FC, 0x0134, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__SRC_BOOT_CFG07 = IOMUX_PAD(0x03FC, 0x0134, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA08__LCD_DATA08 = IOMUX_PAD(0x0400, 0x0138, 0, 0x06F8, 0, 0), - MX6_PAD_LCD_DATA08__KEY_COL0 = IOMUX_PAD(0x0400, 0x0138, 1, 0x06A0, 1, 0), - MX6_PAD_LCD_DATA08__CSI_DATA09 = IOMUX_PAD(0x0400, 0x0138, 2, 0x05EC, 0, 0), - MX6_PAD_LCD_DATA08__ECSPI2_SCLK = IOMUX_PAD(0x0400, 0x0138, 4, 0x061C, 0, 0), - MX6_PAD_LCD_DATA08__GPIO2_IO28 = IOMUX_PAD(0x0400, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__ARM_TRACE08 = IOMUX_PAD(0x0400, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__SRC_BOOT_CFG08 = IOMUX_PAD(0x0400, 0x0138, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA09__LCD_DATA09 = IOMUX_PAD(0x0404, 0x013C, 0, 0x06FC, 0, 0), - MX6_PAD_LCD_DATA09__KEY_ROW0 = IOMUX_PAD(0x0404, 0x013C, 1, 0x06C0, 1, 0), - MX6_PAD_LCD_DATA09__CSI_DATA08 = IOMUX_PAD(0x0404, 0x013C, 2, 0x05E8, 0, 0), - MX6_PAD_LCD_DATA09__ECSPI2_MOSI = IOMUX_PAD(0x0404, 0x013C, 4, 0x0624, 0, 0), - MX6_PAD_LCD_DATA09__GPIO2_IO29 = IOMUX_PAD(0x0404, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__ARM_TRACE09 = IOMUX_PAD(0x0404, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__SRC_BOOT_CFG09 = IOMUX_PAD(0x0404, 0x013C, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0408, 0x0140, 0, 0x0700, 1, 0), - MX6_PAD_LCD_DATA10__KEY_COL1 = IOMUX_PAD(0x0408, 0x0140, 1, 0x06A4, 1, 0), - MX6_PAD_LCD_DATA10__CSI_DATA07 = IOMUX_PAD(0x0408, 0x0140, 2, 0x05E4, 0, 0), - MX6_PAD_LCD_DATA10__ECSPI2_MISO = IOMUX_PAD(0x0408, 0x0140, 4, 0x0620, 0, 0), - MX6_PAD_LCD_DATA10__GPIO2_IO30 = IOMUX_PAD(0x0408, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__ARM_TRACE10 = IOMUX_PAD(0x0408, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0408, 0x0140, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x040C, 0x0144, 0, 0x0704, 0, 0), - MX6_PAD_LCD_DATA11__KEY_ROW1 = IOMUX_PAD(0x040C, 0x0144, 1, 0x06C4, 1, 0), - MX6_PAD_LCD_DATA11__CSI_DATA06 = IOMUX_PAD(0x040C, 0x0144, 2, 0x05E0, 0, 0), - MX6_PAD_LCD_DATA11__ECSPI2_SS1 = IOMUX_PAD(0x040C, 0x0144, 4, 0x062C, 0, 0), - MX6_PAD_LCD_DATA11__GPIO2_IO31 = IOMUX_PAD(0x040C, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__ARM_TRACE11 = IOMUX_PAD(0x040C, 0x0144, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x040C, 0x0144, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0410, 0x0148, 0, 0x0708, 0, 0), - MX6_PAD_LCD_DATA12__KEY_COL2 = IOMUX_PAD(0x0410, 0x0148, 1, 0x06A8, 1, 0), - MX6_PAD_LCD_DATA12__CSI_DATA05 = IOMUX_PAD(0x0410, 0x0148, 2, 0x05DC, 0, 0), - MX6_PAD_LCD_DATA12__UART5_DCE_RTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0760, 0, 0), - MX6_PAD_LCD_DATA12__UART5_DTE_CTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__GPIO3_IO00 = IOMUX_PAD(0x0410, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__ARM_TRACE12 = IOMUX_PAD(0x0410, 0x0148, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0410, 0x0148, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x0414, 0x014C, 0, 0x070C, 0, 0), - MX6_PAD_LCD_DATA13__KEY_ROW2 = IOMUX_PAD(0x0414, 0x014C, 1, 0x06C8, 1, 0), - MX6_PAD_LCD_DATA13__CSI_DATA04 = IOMUX_PAD(0x0414, 0x014C, 2, 0x05D8, 0, 0), - MX6_PAD_LCD_DATA13__UART5_DCE_CTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__UART5_DTE_RTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0760, 1, 0), - MX6_PAD_LCD_DATA13__GPIO3_IO01 = IOMUX_PAD(0x0414, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__ARM_TRACE13 = IOMUX_PAD(0x0414, 0x014C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0414, 0x014C, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0418, 0x0150, 0, 0x0710, 0, 0), - MX6_PAD_LCD_DATA14__KEY_COL3 = IOMUX_PAD(0x0418, 0x0150, 1, 0x06AC, 1, 0), - MX6_PAD_LCD_DATA14__CSI_DATA03 = IOMUX_PAD(0x0418, 0x0150, 2, 0x05D4, 0, 0), - MX6_PAD_LCD_DATA14__UART5_DCE_RX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0764, 0, 0), - MX6_PAD_LCD_DATA14__UART5_DTE_TX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__GPIO3_IO02 = IOMUX_PAD(0x0418, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__ARM_TRACE14 = IOMUX_PAD(0x0418, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0418, 0x0150, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x041C, 0x0154, 0, 0x0714, 0, 0), - MX6_PAD_LCD_DATA15__KEY_ROW3 = IOMUX_PAD(0x041C, 0x0154, 1, 0x06CC, 0, 0), - MX6_PAD_LCD_DATA15__CSI_DATA02 = IOMUX_PAD(0x041C, 0x0154, 2, 0x05D0, 0, 0), - MX6_PAD_LCD_DATA15__UART5_DCE_TX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__UART5_DTE_RX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0764, 1, 0), - MX6_PAD_LCD_DATA15__GPIO3_IO03 = IOMUX_PAD(0x041C, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__ARM_TRACE15 = IOMUX_PAD(0x041C, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x041C, 0x0154, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0420, 0x0158, 0, 0x0718, 0, 0), - MX6_PAD_LCD_DATA16__KEY_COL4 = IOMUX_PAD(0x0420, 0x0158, 1, 0x06B0, 0, 0), - MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x0420, 0x0158, 2, 0x05CC, 0, 0), - MX6_PAD_LCD_DATA16__I2C2_SCL = IOMUX_PAD(0x0420, 0x0158, IOMUX_CONFIG_SION | 4, 0x0684, 1, 0), - MX6_PAD_LCD_DATA16__GPIO3_IO04 = IOMUX_PAD(0x0420, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__SRC_BOOT_CFG24 = IOMUX_PAD(0x0420, 0x0158, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x0424, 0x015C, 0, 0x071C, 0, 0), - MX6_PAD_LCD_DATA17__KEY_ROW4 = IOMUX_PAD(0x0424, 0x015C, 1, 0x06D0, 0, 0), - MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x0424, 0x015C, 2, 0x05C8, 0, 0), - MX6_PAD_LCD_DATA17__I2C2_SDA = IOMUX_PAD(0x0424, 0x015C, IOMUX_CONFIG_SION | 4, 0x0688, 1, 0), - MX6_PAD_LCD_DATA17__GPIO3_IO05 = IOMUX_PAD(0x0424, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__SRC_BOOT_CFG25 = IOMUX_PAD(0x0424, 0x015C, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0428, 0x0160, 0, 0x0720, 0, 0), - MX6_PAD_LCD_DATA18__KEY_COL5 = IOMUX_PAD(0x0428, 0x0160, 1, 0x0694, 2, 0), - MX6_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0428, 0x0160, 2, 0x05C4, 1, 0), - MX6_PAD_LCD_DATA18__GPT_CAPTURE1 = IOMUX_PAD(0x0428, 0x0160, 4, 0x0670, 1, 0), - MX6_PAD_LCD_DATA18__GPIO3_IO06 = IOMUX_PAD(0x0428, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__SRC_BOOT_CFG26 = IOMUX_PAD(0x0428, 0x0160, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x042C, 0x0164, 0, 0x0724, 0, 0), - MX6_PAD_LCD_DATA19__KEY_ROW5 = IOMUX_PAD(0x042C, 0x0164, 1, 0x06B4, 1, 0), - MX6_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x042C, 0x0164, 2, 0x05C0, 2, 0), - MX6_PAD_LCD_DATA19__GPT_CAPTURE2 = IOMUX_PAD(0x042C, 0x0164, 4, 0x0674, 1, 0), - MX6_PAD_LCD_DATA19__GPIO3_IO07 = IOMUX_PAD(0x042C, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__SRC_BOOT_CFG27 = IOMUX_PAD(0x042C, 0x0164, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0430, 0x0168, 0, 0x0728, 0, 0), - MX6_PAD_LCD_DATA20__KEY_COL6 = IOMUX_PAD(0x0430, 0x0168, 1, 0x0698, 1, 0), - MX6_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0430, 0x0168, 2, 0x05BC, 2, 0), - MX6_PAD_LCD_DATA20__GPT_COMPARE1 = IOMUX_PAD(0x0430, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__GPIO3_IO08 = IOMUX_PAD(0x0430, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__SRC_BOOT_CFG28 = IOMUX_PAD(0x0430, 0x0168, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x0434, 0x016C, 0, 0x072C, 0, 0), - MX6_PAD_LCD_DATA21__KEY_ROW6 = IOMUX_PAD(0x0434, 0x016C, 1, 0x06B8, 1, 0), - MX6_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x0434, 0x016C, 2, 0x05B8, 2, 0), - MX6_PAD_LCD_DATA21__GPT_COMPARE2 = IOMUX_PAD(0x0434, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__GPIO3_IO09 = IOMUX_PAD(0x0434, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__SRC_BOOT_CFG29 = IOMUX_PAD(0x0434, 0x016C, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0438, 0x0170, 0, 0x0730, 0, 0), - MX6_PAD_LCD_DATA22__KEY_COL7 = IOMUX_PAD(0x0438, 0x0170, 1, 0x069C, 1, 0), - MX6_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0438, 0x0170, 2, 0x05B4, 1, 0), - MX6_PAD_LCD_DATA22__GPT_COMPARE3 = IOMUX_PAD(0x0438, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__GPIO3_IO10 = IOMUX_PAD(0x0438, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__SRC_BOOT_CFG30 = IOMUX_PAD(0x0438, 0x0170, 7, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x043C, 0x0174, 0, 0x0734, 0, 0), - MX6_PAD_LCD_DATA23__KEY_ROW7 = IOMUX_PAD(0x043C, 0x0174, 1, 0x06BC, 1, 0), - MX6_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x043C, 0x0174, 2, 0x05B0, 1, 0), - MX6_PAD_LCD_DATA23__GPT_CLKIN = IOMUX_PAD(0x043C, 0x0174, 4, 0x0678, 1, 0), - MX6_PAD_LCD_DATA23__GPIO3_IO11 = IOMUX_PAD(0x043C, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__SRC_BOOT_CFG31 = IOMUX_PAD(0x043C, 0x0174, 7, 0x0000, 0, 0), - - MX6_PAD_AUD_RXFS__AUD3_RXFS = IOMUX_PAD(0x0440, 0x0178, 0, 0x0000, 0, 0), - MX6_PAD_AUD_RXFS__I2C1_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 1, 0x067C, 1, 0), - MX6_PAD_AUD_RXFS__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0754, 0, 0), - MX6_PAD_AUD_RXFS__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_AUD_RXFS__I2C3_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 4, 0x068C, 1, 0), - MX6_PAD_AUD_RXFS__GPIO1_IO00 = IOMUX_PAD(0x0440, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_AUD_RXFS__ECSPI3_SS0 = IOMUX_PAD(0x0440, 0x0178, 6, 0x0648, 0, 0), - MX6_PAD_AUD_RXFS__MBIST_BEND = IOMUX_PAD(0x0440, 0x0178, 7, 0x0000, 0, 0), - - MX6_PAD_AUD_RXC__AUD3_RXC = IOMUX_PAD(0x0444, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_AUD_RXC__I2C1_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 1, 0x0680, 1, 0), - MX6_PAD_AUD_RXC__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_AUD_RXC__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0754, 1, 0), - MX6_PAD_AUD_RXC__I2C3_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 4, 0x0690, 1, 0), - MX6_PAD_AUD_RXC__GPIO1_IO01 = IOMUX_PAD(0x0444, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_AUD_RXC__ECSPI3_SS1 = IOMUX_PAD(0x0444, 0x017C, 6, 0x064C, 0, 0), - - MX6_PAD_AUD_RXD__AUD3_RXD = IOMUX_PAD(0x0448, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_AUD_RXD__ECSPI3_MOSI = IOMUX_PAD(0x0448, 0x0180, 1, 0x063C, 0, 0), - MX6_PAD_AUD_RXD__UART4_DCE_RX = IOMUX_PAD(0x0448, 0x0180, 2, 0x075C, 0, 0), - MX6_PAD_AUD_RXD__UART4_DTE_TX = IOMUX_PAD(0x0448, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_AUD_RXD__SD1_LCTL = IOMUX_PAD(0x0448, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_AUD_RXD__GPIO1_IO02 = IOMUX_PAD(0x0448, 0x0180, 5, 0x0000, 0, 0), - - MX6_PAD_AUD_TXC__AUD3_TXC = IOMUX_PAD(0x044C, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_AUD_TXC__ECSPI3_MISO = IOMUX_PAD(0x044C, 0x0184, 1, 0x0638, 0, 0), - MX6_PAD_AUD_TXC__UART4_DCE_TX = IOMUX_PAD(0x044C, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_AUD_TXC__UART4_DTE_RX = IOMUX_PAD(0x044C, 0x0184, 2, 0x075C, 1, 0), - MX6_PAD_AUD_TXC__SD2_LCTL = IOMUX_PAD(0x044C, 0x0184, 4, 0x0000, 0, 0), - MX6_PAD_AUD_TXC__GPIO1_IO03 = IOMUX_PAD(0x044C, 0x0184, 5, 0x0000, 0, 0), - - MX6_PAD_AUD_TXFS__AUD3_TXFS = IOMUX_PAD(0x0450, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_AUD_TXFS__PWM3_OUT = IOMUX_PAD(0x0450, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_AUD_TXFS__UART4_DCE_RTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0758, 0, 0), - MX6_PAD_AUD_TXFS__UART4_DTE_CTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_AUD_TXFS__SD3_LCTL = IOMUX_PAD(0x0450, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_AUD_TXFS__GPIO1_IO04 = IOMUX_PAD(0x0450, 0x0188, 5, 0x0000, 0, 0), - - MX6_PAD_AUD_TXD__AUD3_TXD = IOMUX_PAD(0x0454, 0x018C, 0, 0x0000, 0, 0), - MX6_PAD_AUD_TXD__ECSPI3_SCLK = IOMUX_PAD(0x0454, 0x018C, 1, 0x0630, 0, 0), - MX6_PAD_AUD_TXD__UART4_DCE_CTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_AUD_TXD__UART4_DTE_RTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0758, 1, 0), - MX6_PAD_AUD_TXD__GPIO1_IO05 = IOMUX_PAD(0x0454, 0x018C, 5, 0x0000, 0, 0), - - MX6_PAD_AUD_MCLK__AUDIO_CLK_OUT = IOMUX_PAD(0x0458, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_AUD_MCLK__PWM4_OUT = IOMUX_PAD(0x0458, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_AUD_MCLK__ECSPI3_RDY = IOMUX_PAD(0x0458, 0x0190, 2, 0x0634, 0, 0), - MX6_PAD_AUD_MCLK__WDOG2_RESET_B_DEB = IOMUX_PAD(0x0458, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_AUD_MCLK__GPIO1_IO06 = IOMUX_PAD(0x0458, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_AUD_MCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0458, 0x0190, 6, 0x073C, 1, 0), - - MX6_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0744, 0, 0), - - MX6_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_UART1_RXD__PWM1_OUT = IOMUX_PAD(0x045C, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_UART1_RXD__UART4_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 2, 0x075C, 4, 0), - MX6_PAD_UART1_RXD__UART4_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_UART1_RXD__UART5_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0764, 6, 0), - MX6_PAD_UART1_RXD__UART5_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_UART1_RXD__GPIO3_IO16 = IOMUX_PAD(0x045C, 0x0194, 5, 0x0000, 0, 0), - - MX6_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0000, 0, 0), - - MX6_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0744, 1, 0), - MX6_PAD_UART1_TXD__PWM2_OUT = IOMUX_PAD(0x0460, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_UART1_TXD__UART4_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 2, 0x0000, 0, 0), - MX6_PAD_UART1_TXD__UART4_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 2, 0x075C, 5, 0), - MX6_PAD_UART1_TXD__UART5_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_UART1_TXD__UART5_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0764, 7, 0), - MX6_PAD_UART1_TXD__GPIO3_IO17 = IOMUX_PAD(0x0460, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_UART1_TXD__UART5_DCD_B = IOMUX_PAD(0x0460, 0x0198, 7, 0x0000, 0, 0), - - MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0464, 0x019C, IOMUX_CONFIG_SION | 0, 0x067C, 0, 0), - MX6_PAD_I2C1_SCL__UART1_DCE_RTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0740, 0, 0), - MX6_PAD_I2C1_SCL__UART1_DTE_CTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_I2C1_SCL__ECSPI3_SS2 = IOMUX_PAD(0x0464, 0x019C, 2, 0x0640, 0, 0), - MX6_PAD_I2C1_SCL__SD3_RESET = IOMUX_PAD(0x0464, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_I2C1_SCL__GPIO3_IO12 = IOMUX_PAD(0x0464, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_I2C1_SCL__ECSPI1_SS1 = IOMUX_PAD(0x0464, 0x019C, 6, 0x060C, 0, 0), - - MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0468, 0x01A0, IOMUX_CONFIG_SION | 0, 0x0680, 0, 0), - MX6_PAD_I2C1_SDA__UART1_DCE_CTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_I2C1_SDA__UART1_DTE_RTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0740, 1, 0), - MX6_PAD_I2C1_SDA__ECSPI3_SS3 = IOMUX_PAD(0x0468, 0x01A0, 2, 0x0644, 0, 0), - MX6_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x0468, 0x01A0, 4, 0x0000, 0, 0), - MX6_PAD_I2C1_SDA__GPIO3_IO13 = IOMUX_PAD(0x0468, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_I2C1_SDA__ECSPI1_SS2 = IOMUX_PAD(0x0468, 0x01A0, 6, 0x0610, 0, 0), - - MX6_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x046C, 0x01A4, IOMUX_CONFIG_SION | 0, 0x0684, 3, 0), - MX6_PAD_I2C2_SCL__AUD4_RXFS = IOMUX_PAD(0x046C, 0x01A4, 1, 0x0570, 2, 0), - MX6_PAD_I2C2_SCL__SPDIF_IN = IOMUX_PAD(0x046C, 0x01A4, 2, 0x0738, 2, 0), - MX6_PAD_I2C2_SCL__SD3_WP = IOMUX_PAD(0x046C, 0x01A4, 4, 0x0794, 3, 0), - MX6_PAD_I2C2_SCL__GPIO3_IO14 = IOMUX_PAD(0x046C, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_I2C2_SCL__ECSPI1_RDY = IOMUX_PAD(0x046C, 0x01A4, 6, 0x0600, 1, 0), - - MX6_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0470, 0x01A8, IOMUX_CONFIG_SION | 0, 0x0688, 3, 0), - MX6_PAD_I2C2_SDA__AUD4_RXC = IOMUX_PAD(0x0470, 0x01A8, 1, 0x056C, 2, 0), - MX6_PAD_I2C2_SDA__SPDIF_OUT = IOMUX_PAD(0x0470, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_I2C2_SDA__SD3_CD_B = IOMUX_PAD(0x0470, 0x01A8, 4, 0x0780, 3, 0), - MX6_PAD_I2C2_SDA__GPIO3_IO15 = IOMUX_PAD(0x0470, 0x01A8, 5, 0x0000, 0, 0), - - MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0474, 0x01AC, 0, 0x05FC, 1, 0), - MX6_PAD_ECSPI1_SCLK__AUD4_TXD = IOMUX_PAD(0x0474, 0x01AC, 1, 0x0568, 1, 0), - MX6_PAD_ECSPI1_SCLK__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0764, 2, 0), - MX6_PAD_ECSPI1_SCLK__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI1_SCLK__EPDC_VCOM0 = IOMUX_PAD(0x0474, 0x01AC, 3, 0x0000, 0, 0), - MX6_PAD_ECSPI1_SCLK__SD2_RESET = IOMUX_PAD(0x0474, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 = IOMUX_PAD(0x0474, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_ECSPI1_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0474, 0x01AC, 6, 0x0768, 1, 0), - - MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0478, 0x01B0, 0, 0x0608, 1, 0), - MX6_PAD_ECSPI1_MOSI__AUD4_TXC = IOMUX_PAD(0x0478, 0x01B0, 1, 0x0574, 1, 0), - MX6_PAD_ECSPI1_MOSI__UART5_DCE_TX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI1_MOSI__UART5_DTE_RX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0764, 3, 0), - MX6_PAD_ECSPI1_MOSI__EPDC_VCOM1 = IOMUX_PAD(0x0478, 0x01B0, 3, 0x0000, 0, 0), - MX6_PAD_ECSPI1_MOSI__SD2_VSELECT = IOMUX_PAD(0x0478, 0x01B0, 4, 0x0000, 0, 0), - MX6_PAD_ECSPI1_MOSI__GPIO4_IO09 = IOMUX_PAD(0x0478, 0x01B0, 5, 0x0000, 0, 0), - - MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x047C, 0x01B4, 0, 0x0604, 1, 0), - MX6_PAD_ECSPI1_MISO__AUD4_TXFS = IOMUX_PAD(0x047C, 0x01B4, 1, 0x0578, 1, 0), - MX6_PAD_ECSPI1_MISO__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0760, 2, 0), - MX6_PAD_ECSPI1_MISO__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI1_MISO__EPDC_BDR0 = IOMUX_PAD(0x047C, 0x01B4, 3, 0x0000, 0, 0), - MX6_PAD_ECSPI1_MISO__SD2_WP = IOMUX_PAD(0x047C, 0x01B4, 4, 0x077C, 0, 0), - MX6_PAD_ECSPI1_MISO__GPIO4_IO10 = IOMUX_PAD(0x047C, 0x01B4, 5, 0x0000, 0, 0), - - MX6_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0480, 0x01B8, 0, 0x0614, 1, 0), - MX6_PAD_ECSPI1_SS0__AUD4_RXD = IOMUX_PAD(0x0480, 0x01B8, 1, 0x0564, 1, 0), - MX6_PAD_ECSPI1_SS0__UART5_DCE_CTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI1_SS0__UART5_DTE_RTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0760, 3, 0), - MX6_PAD_ECSPI1_SS0__EPDC_BDR1 = IOMUX_PAD(0x0480, 0x01B8, 3, 0x0000, 0, 0), - MX6_PAD_ECSPI1_SS0__SD2_CD_B = IOMUX_PAD(0x0480, 0x01B8, 4, 0x0778, 0, 0), - MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0480, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_ECSPI1_SS0__USB_OTG2_PWR = IOMUX_PAD(0x0480, 0x01B8, 6, 0x0000, 0, 0), - - MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0484, 0x01BC, 0, 0x061C, 1, 0), - MX6_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0484, 0x01BC, 1, 0x073C, 2, 0), - MX6_PAD_ECSPI2_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0754, 2, 0), - MX6_PAD_ECSPI2_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK = IOMUX_PAD(0x0484, 0x01BC, 3, 0x05F4, 1, 0), - MX6_PAD_ECSPI2_SCLK__SD1_RESET = IOMUX_PAD(0x0484, 0x01BC, 4, 0x0000, 0, 0), - MX6_PAD_ECSPI2_SCLK__GPIO4_IO12 = IOMUX_PAD(0x0484, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0484, 0x01BC, 6, 0x0768, 2, 0), - - MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0488, 0x01C0, 0, 0x0624, 1, 0), - MX6_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0488, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_ECSPI2_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI2_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0754, 3, 0), - MX6_PAD_ECSPI2_MOSI__CSI_HSYNC = IOMUX_PAD(0x0488, 0x01C0, 3, 0x05F0, 1, 0), - MX6_PAD_ECSPI2_MOSI__SD1_VSELECT = IOMUX_PAD(0x0488, 0x01C0, 4, 0x0000, 0, 0), - MX6_PAD_ECSPI2_MOSI__GPIO4_IO13 = IOMUX_PAD(0x0488, 0x01C0, 5, 0x0000, 0, 0), - - MX6_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x048C, 0x01C4, 0, 0x0620, 1, 0), - MX6_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 = IOMUX_PAD(0x048C, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_ECSPI2_MISO__UART3_DCE_RTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0750, 0, 0), - MX6_PAD_ECSPI2_MISO__UART3_DTE_CTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI2_MISO__CSI_MCLK = IOMUX_PAD(0x048C, 0x01C4, 3, 0x0000, 0, 0), - MX6_PAD_ECSPI2_MISO__SD1_WP = IOMUX_PAD(0x048C, 0x01C4, 4, 0x0774, 2, 0), - MX6_PAD_ECSPI2_MISO__GPIO4_IO14 = IOMUX_PAD(0x048C, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_ECSPI2_MISO__USB_OTG1_OC = IOMUX_PAD(0x048C, 0x01C4, 6, 0x076C, 1, 0), - - MX6_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0490, 0x01C8, 0, 0x0628, 0, 0), - MX6_PAD_ECSPI2_SS0__ECSPI1_SS3 = IOMUX_PAD(0x0490, 0x01C8, 1, 0x0618, 1, 0), - MX6_PAD_ECSPI2_SS0__UART3_DCE_CTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0000, 0, 0), - MX6_PAD_ECSPI2_SS0__UART3_DTE_RTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0750, 1, 0), - MX6_PAD_ECSPI2_SS0__CSI_VSYNC = IOMUX_PAD(0x0490, 0x01C8, 3, 0x05F8, 1, 0), - MX6_PAD_ECSPI2_SS0__SD1_CD_B = IOMUX_PAD(0x0490, 0x01C8, 4, 0x0770, 2, 0), - MX6_PAD_ECSPI2_SS0__GPIO4_IO15 = IOMUX_PAD(0x0490, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_ECSPI2_SS0__USB_OTG1_PWR = IOMUX_PAD(0x0490, 0x01C8, 6, 0x0000, 0, 0), - - MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0494, 0x01CC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__KEY_COL0 = IOMUX_PAD(0x0494, 0x01CC, 2, 0x06A0, 2, 0), - MX6_PAD_SD1_CLK__EPDC_SDCE4 = IOMUX_PAD(0x0494, 0x01CC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO5_IO15 = IOMUX_PAD(0x0494, 0x01CC, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0498, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__KEY_ROW0 = IOMUX_PAD(0x0498, 0x01D0, 2, 0x06C0, 2, 0), - MX6_PAD_SD1_CMD__EPDC_SDCE5 = IOMUX_PAD(0x0498, 0x01D0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO5_IO14 = IOMUX_PAD(0x0498, 0x01D0, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x049C, 0x01D4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__KEY_COL1 = IOMUX_PAD(0x049C, 0x01D4, 2, 0x06A4, 2, 0), - MX6_PAD_SD1_DATA0__EPDC_SDCE6 = IOMUX_PAD(0x049C, 0x01D4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__GPIO5_IO11 = IOMUX_PAD(0x049C, 0x01D4, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x04A0, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__KEY_ROW1 = IOMUX_PAD(0x04A0, 0x01D8, 2, 0x06C4, 2, 0), - MX6_PAD_SD1_DATA1__EPDC_SDCE7 = IOMUX_PAD(0x04A0, 0x01D8, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__GPIO5_IO08 = IOMUX_PAD(0x04A0, 0x01D8, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x04A4, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__KEY_COL2 = IOMUX_PAD(0x04A4, 0x01DC, 2, 0x06A8, 2, 0), - MX6_PAD_SD1_DATA2__EPDC_SDCE8 = IOMUX_PAD(0x04A4, 0x01DC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__GPIO5_IO13 = IOMUX_PAD(0x04A4, 0x01DC, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x04A8, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__KEY_ROW2 = IOMUX_PAD(0x04A8, 0x01E0, 2, 0x06C8, 2, 0), - MX6_PAD_SD1_DATA3__EPDC_SDCE9 = IOMUX_PAD(0x04A8, 0x01E0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__GPIO5_IO06 = IOMUX_PAD(0x04A8, 0x01E0, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA4__SD1_DATA4 = IOMUX_PAD(0x04AC, 0x01E4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA4__KEY_COL3 = IOMUX_PAD(0x04AC, 0x01E4, 2, 0x06AC, 2, 0), - MX6_PAD_SD1_DATA4__EPDC_SDCLK_N = IOMUX_PAD(0x04AC, 0x01E4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA4__UART4_DCE_RX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x075C, 6, 0), - MX6_PAD_SD1_DATA4__UART4_DTE_TX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA4__GPIO5_IO12 = IOMUX_PAD(0x04AC, 0x01E4, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA5__SD1_DATA5 = IOMUX_PAD(0x04B0, 0x01E8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA5__KEY_ROW3 = IOMUX_PAD(0x04B0, 0x01E8, 2, 0x06CC, 2, 0), - MX6_PAD_SD1_DATA5__EPDC_SDOED = IOMUX_PAD(0x04B0, 0x01E8, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA5__UART4_DCE_TX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA5__UART4_DTE_RX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x075C, 7, 0), - MX6_PAD_SD1_DATA5__GPIO5_IO09 = IOMUX_PAD(0x04B0, 0x01E8, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA6__SD1_DATA6 = IOMUX_PAD(0x04B4, 0x01EC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA6__KEY_COL4 = IOMUX_PAD(0x04B4, 0x01EC, 2, 0x06B0, 2, 0), - MX6_PAD_SD1_DATA6__EPDC_SDOEZ = IOMUX_PAD(0x04B4, 0x01EC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA6__UART4_DCE_RTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0758, 4, 0), - MX6_PAD_SD1_DATA6__UART4_DTE_CTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA6__GPIO5_IO07 = IOMUX_PAD(0x04B4, 0x01EC, 5, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA7__SD1_DATA7 = IOMUX_PAD(0x04B8, 0x01F0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA7__KEY_ROW4 = IOMUX_PAD(0x04B8, 0x01F0, 2, 0x06D0, 2, 0), - MX6_PAD_SD1_DATA7__CCM_PMIC_READY = IOMUX_PAD(0x04B8, 0x01F0, 3, 0x05AC, 3, 0), - MX6_PAD_SD1_DATA7__UART4_DCE_CTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA7__UART4_DTE_RTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0758, 5, 0), - MX6_PAD_SD1_DATA7__GPIO5_IO10 = IOMUX_PAD(0x04B8, 0x01F0, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_RESET__SD2_RESET = IOMUX_PAD(0x04BC, 0x01F4, 0, 0x0000, 0, 0), - MX6_PAD_SD2_RESET__WDOG2_B = IOMUX_PAD(0x04BC, 0x01F4, 2, 0x0000, 0, 0), - MX6_PAD_SD2_RESET__SPDIF_OUT = IOMUX_PAD(0x04BC, 0x01F4, 3, 0x0000, 0, 0), - MX6_PAD_SD2_RESET__CSI_MCLK = IOMUX_PAD(0x04BC, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_SD2_RESET__GPIO4_IO27 = IOMUX_PAD(0x04BC, 0x01F4, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x04C0, 0x01F8, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x04C0, 0x01F8, 1, 0x0570, 1, 0), - MX6_PAD_SD2_CLK__ECSPI3_SCLK = IOMUX_PAD(0x04C0, 0x01F8, 2, 0x0630, 1, 0), - MX6_PAD_SD2_CLK__CSI_DATA00 = IOMUX_PAD(0x04C0, 0x01F8, 3, 0x05C8, 1, 0), - MX6_PAD_SD2_CLK__GPIO5_IO05 = IOMUX_PAD(0x04C0, 0x01F8, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x04C4, 0x01FC, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x04C4, 0x01FC, 1, 0x056C, 1, 0), - MX6_PAD_SD2_CMD__ECSPI3_SS0 = IOMUX_PAD(0x04C4, 0x01FC, 2, 0x0648, 1, 0), - MX6_PAD_SD2_CMD__CSI_DATA01 = IOMUX_PAD(0x04C4, 0x01FC, 3, 0x05CC, 1, 0), - MX6_PAD_SD2_CMD__EPIT1_OUT = IOMUX_PAD(0x04C4, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__GPIO5_IO04 = IOMUX_PAD(0x04C4, 0x01FC, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x04C8, 0x0200, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__AUD4_RXD = IOMUX_PAD(0x04C8, 0x0200, 1, 0x0564, 2, 0), - MX6_PAD_SD2_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04C8, 0x0200, 2, 0x063C, 1, 0), - MX6_PAD_SD2_DATA0__CSI_DATA02 = IOMUX_PAD(0x04C8, 0x0200, 3, 0x05D0, 1, 0), - MX6_PAD_SD2_DATA0__UART5_DCE_RTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0760, 4, 0), - MX6_PAD_SD2_DATA0__UART5_DTE_CTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__GPIO5_IO01 = IOMUX_PAD(0x04C8, 0x0200, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x04CC, 0x0204, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__AUD4_TXC = IOMUX_PAD(0x04CC, 0x0204, 1, 0x0574, 2, 0), - MX6_PAD_SD2_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04CC, 0x0204, 2, 0x0638, 1, 0), - MX6_PAD_SD2_DATA1__CSI_DATA03 = IOMUX_PAD(0x04CC, 0x0204, 3, 0x05D4, 1, 0), - MX6_PAD_SD2_DATA1__UART5_DCE_CTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__UART5_DTE_RTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0760, 5, 0), - MX6_PAD_SD2_DATA1__GPIO4_IO30 = IOMUX_PAD(0x04CC, 0x0204, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x04D0, 0x0208, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA2__AUD4_TXFS = IOMUX_PAD(0x04D0, 0x0208, 1, 0x0578, 2, 0), - MX6_PAD_SD2_DATA2__CSI_DATA04 = IOMUX_PAD(0x04D0, 0x0208, 3, 0x05D8, 1, 0), - MX6_PAD_SD2_DATA2__UART5_DCE_RX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0764, 4, 0), - MX6_PAD_SD2_DATA2__UART5_DTE_TX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DATA2__GPIO5_IO03 = IOMUX_PAD(0x04D0, 0x0208, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x04D4, 0x020C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA3__AUD4_TXD = IOMUX_PAD(0x04D4, 0x020C, 1, 0x0568, 2, 0), - MX6_PAD_SD2_DATA3__CSI_DATA05 = IOMUX_PAD(0x04D4, 0x020C, 3, 0x05DC, 1, 0), - MX6_PAD_SD2_DATA3__UART5_DCE_TX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DATA3__UART5_DTE_RX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0764, 5, 0), - MX6_PAD_SD2_DATA3__GPIO4_IO28 = IOMUX_PAD(0x04D4, 0x020C, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA4__SD2_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA4__SD3_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 1, 0x0784, 1, 0), - MX6_PAD_SD2_DATA4__UART2_DCE_RX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x074C, 2, 0), - MX6_PAD_SD2_DATA4__UART2_DTE_TX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DATA4__CSI_DATA06 = IOMUX_PAD(0x04D8, 0x0210, 3, 0x05E0, 1, 0), - MX6_PAD_SD2_DATA4__SPDIF_OUT = IOMUX_PAD(0x04D8, 0x0210, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DATA4__GPIO5_IO02 = IOMUX_PAD(0x04D8, 0x0210, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA5__SD2_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA5__SD3_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 1, 0x0788, 1, 0), - MX6_PAD_SD2_DATA5__UART2_DCE_TX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DATA5__UART2_DTE_RX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x074C, 3, 0), - MX6_PAD_SD2_DATA5__CSI_DATA07 = IOMUX_PAD(0x04DC, 0x0214, 3, 0x05E4, 1, 0), - MX6_PAD_SD2_DATA5__SPDIF_IN = IOMUX_PAD(0x04DC, 0x0214, 4, 0x0738, 1, 0), - MX6_PAD_SD2_DATA5__GPIO4_IO31 = IOMUX_PAD(0x04DC, 0x0214, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA6__SD2_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA6__SD3_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 1, 0x078C, 1, 0), - MX6_PAD_SD2_DATA6__UART2_DCE_RTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0748, 2, 0), - MX6_PAD_SD2_DATA6__UART2_DTE_CTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DATA6__CSI_DATA08 = IOMUX_PAD(0x04E0, 0x0218, 3, 0x05E8, 1, 0), - MX6_PAD_SD2_DATA6__SD2_WP = IOMUX_PAD(0x04E0, 0x0218, 4, 0x077C, 1, 0), - MX6_PAD_SD2_DATA6__GPIO4_IO29 = IOMUX_PAD(0x04E0, 0x0218, 5, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA7__SD2_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA7__SD3_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 1, 0x0790, 1, 0), - MX6_PAD_SD2_DATA7__UART2_DCE_CTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DATA7__UART2_DTE_RTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0748, 3, 0), - MX6_PAD_SD2_DATA7__CSI_DATA09 = IOMUX_PAD(0x04E4, 0x021C, 3, 0x05EC, 1, 0), - MX6_PAD_SD2_DATA7__SD2_CD_B = IOMUX_PAD(0x04E4, 0x021C, 4, 0x0778, 1, 0), - MX6_PAD_SD2_DATA7__GPIO5_IO00 = IOMUX_PAD(0x04E4, 0x021C, 5, 0x0000, 0, 0), - - MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x04E8, 0x0220, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__AUD5_RXFS = IOMUX_PAD(0x04E8, 0x0220, 1, 0x0588, 0, 0), - MX6_PAD_SD3_CLK__KEY_COL5 = IOMUX_PAD(0x04E8, 0x0220, 2, 0x0694, 0, 0), - MX6_PAD_SD3_CLK__CSI_DATA10 = IOMUX_PAD(0x04E8, 0x0220, 3, 0x05B0, 0, 0), - MX6_PAD_SD3_CLK__WDOG1_RESET_B_DEB = IOMUX_PAD(0x04E8, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO5_IO18 = IOMUX_PAD(0x04E8, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USB_OTG1_PWR = IOMUX_PAD(0x04E8, 0x0220, 6, 0x0000, 0, 0), - - MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x04EC, 0x0224, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__AUD5_RXC = IOMUX_PAD(0x04EC, 0x0224, 1, 0x0584, 0, 0), - MX6_PAD_SD3_CMD__KEY_ROW5 = IOMUX_PAD(0x04EC, 0x0224, 2, 0x06B4, 0, 0), - MX6_PAD_SD3_CMD__CSI_DATA11 = IOMUX_PAD(0x04EC, 0x0224, 3, 0x05B4, 0, 0), - MX6_PAD_SD3_CMD__USB_OTG2_ID = IOMUX_PAD(0x04EC, 0x0224, 4, 0x0560, 1, 0), - MX6_PAD_SD3_CMD__GPIO5_IO21 = IOMUX_PAD(0x04EC, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USB_OTG2_PWR = IOMUX_PAD(0x04EC, 0x0224, 6, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x04F0, 0x0228, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__AUD5_RXD = IOMUX_PAD(0x04F0, 0x0228, 1, 0x057C, 0, 0), - MX6_PAD_SD3_DATA0__KEY_COL6 = IOMUX_PAD(0x04F0, 0x0228, 2, 0x0698, 0, 0), - MX6_PAD_SD3_DATA0__CSI_DATA12 = IOMUX_PAD(0x04F0, 0x0228, 3, 0x05B8, 0, 0), - MX6_PAD_SD3_DATA0__USB_OTG1_ID = IOMUX_PAD(0x04F0, 0x0228, 4, 0x055C, 1, 0), - MX6_PAD_SD3_DATA0__GPIO5_IO19 = IOMUX_PAD(0x04F0, 0x0228, 5, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x04F4, 0x022C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__AUD5_TXC = IOMUX_PAD(0x04F4, 0x022C, 1, 0x058C, 0, 0), - MX6_PAD_SD3_DATA1__KEY_ROW6 = IOMUX_PAD(0x04F4, 0x022C, 2, 0x06B8, 0, 0), - MX6_PAD_SD3_DATA1__CSI_DATA13 = IOMUX_PAD(0x04F4, 0x022C, 3, 0x05BC, 0, 0), - MX6_PAD_SD3_DATA1__SD1_VSELECT = IOMUX_PAD(0x04F4, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__GPIO5_IO20 = IOMUX_PAD(0x04F4, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__JTAG_DE_B = IOMUX_PAD(0x04F4, 0x022C, 6, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x04F8, 0x0230, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__AUD5_TXFS = IOMUX_PAD(0x04F8, 0x0230, 1, 0x0590, 0, 0), - MX6_PAD_SD3_DATA2__KEY_COL7 = IOMUX_PAD(0x04F8, 0x0230, 2, 0x069C, 0, 0), - MX6_PAD_SD3_DATA2__CSI_DATA14 = IOMUX_PAD(0x04F8, 0x0230, 3, 0x05C0, 0, 0), - MX6_PAD_SD3_DATA2__EPIT1_OUT = IOMUX_PAD(0x04F8, 0x0230, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__GPIO5_IO16 = IOMUX_PAD(0x04F8, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__USB_OTG2_OC = IOMUX_PAD(0x04F8, 0x0230, 6, 0x0768, 0, 0), - - MX6_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x04FC, 0x0234, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__AUD5_TXD = IOMUX_PAD(0x04FC, 0x0234, 1, 0x0580, 0, 0), - MX6_PAD_SD3_DATA3__KEY_ROW7 = IOMUX_PAD(0x04FC, 0x0234, 2, 0x06BC, 0, 0), - MX6_PAD_SD3_DATA3__CSI_DATA15 = IOMUX_PAD(0x04FC, 0x0234, 3, 0x05C4, 0, 0), - MX6_PAD_SD3_DATA3__EPIT2_OUT = IOMUX_PAD(0x04FC, 0x0234, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__GPIO5_IO17 = IOMUX_PAD(0x04FC, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04FC, 0x0234, 6, 0x076C, 0, 0), - - MX6_PAD_GPIO4_IO20__SD1_STROBE = IOMUX_PAD(0x0500, 0x0238, 0, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO20__AUD6_RXFS = IOMUX_PAD(0x0500, 0x0238, 2, 0x05A0, 0, 0), - MX6_PAD_GPIO4_IO20__ECSPI4_SS0 = IOMUX_PAD(0x0500, 0x0238, 3, 0x065C, 0, 0), - MX6_PAD_GPIO4_IO20__GPT_CAPTURE1 = IOMUX_PAD(0x0500, 0x0238, 4, 0x0670, 0, 0), - MX6_PAD_GPIO4_IO20__GPIO4_IO20 = IOMUX_PAD(0x0500, 0x0238, 5, 0x0000, 0, 0), - - MX6_PAD_GPIO4_IO21__SD2_STROBE = IOMUX_PAD(0x0504, 0x023C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO21__AUD6_RXC = IOMUX_PAD(0x0504, 0x023C, 2, 0x059C, 0, 0), - MX6_PAD_GPIO4_IO21__ECSPI4_SCLK = IOMUX_PAD(0x0504, 0x023C, 3, 0x0650, 0, 0), - MX6_PAD_GPIO4_IO21__GPT_CAPTURE2 = IOMUX_PAD(0x0504, 0x023C, 4, 0x0674, 0, 0), - MX6_PAD_GPIO4_IO21__GPIO4_IO21 = IOMUX_PAD(0x0504, 0x023C, 5, 0x0000, 0, 0), - - MX6_PAD_GPIO4_IO19__SD3_STROBE = IOMUX_PAD(0x0508, 0x0240, 0, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO19__AUD6_RXD = IOMUX_PAD(0x0508, 0x0240, 2, 0x0594, 0, 0), - MX6_PAD_GPIO4_IO19__ECSPI4_MOSI = IOMUX_PAD(0x0508, 0x0240, 3, 0x0658, 0, 0), - MX6_PAD_GPIO4_IO19__GPT_COMPARE1 = IOMUX_PAD(0x0508, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO19__GPIO4_IO19 = IOMUX_PAD(0x0508, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO25__AUD6_TXC = IOMUX_PAD(0x050C, 0x0244, 2, 0x05A4, 0, 0), - MX6_PAD_GPIO4_IO25__ECSPI4_MISO = IOMUX_PAD(0x050C, 0x0244, 3, 0x0654, 0, 0), - MX6_PAD_GPIO4_IO25__GPT_COMPARE2 = IOMUX_PAD(0x050C, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO25__GPIO4_IO25 = IOMUX_PAD(0x050C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO18__AUD6_TXFS = IOMUX_PAD(0x0510, 0x0248, 2, 0x05A8, 0, 0), - MX6_PAD_GPIO4_IO18__ECSPI4_SS1 = IOMUX_PAD(0x0510, 0x0248, 3, 0x0660, 0, 0), - MX6_PAD_GPIO4_IO18__GPT_COMPARE3 = IOMUX_PAD(0x0510, 0x0248, 4, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO18__GPIO4_IO18 = IOMUX_PAD(0x0510, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO24__AUD6_TXD = IOMUX_PAD(0x0514, 0x024C, 2, 0x0598, 0, 0), - MX6_PAD_GPIO4_IO24__ECSPI4_SS2 = IOMUX_PAD(0x0514, 0x024C, 3, 0x0664, 0, 0), - MX6_PAD_GPIO4_IO24__GPT_CLKIN = IOMUX_PAD(0x0514, 0x024C, 4, 0x0678, 0, 0), - MX6_PAD_GPIO4_IO24__GPIO4_IO24 = IOMUX_PAD(0x0514, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO23__AUDIO_CLK_OUT = IOMUX_PAD(0x0518, 0x0250, 2, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO23__SD1_RESET = IOMUX_PAD(0x0518, 0x0250, 3, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO23__SD3_RESET = IOMUX_PAD(0x0518, 0x0250, 4, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO23__GPIO4_IO23 = IOMUX_PAD(0x0518, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO17__USB_OTG1_ID = IOMUX_PAD(0x051C, 0x0254, 2, 0x055C, 2, 0), - MX6_PAD_GPIO4_IO17__SD1_VSELECT = IOMUX_PAD(0x051C, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO17__SD3_VSELECT = IOMUX_PAD(0x051C, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO17__GPIO4_IO17 = IOMUX_PAD(0x051C, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO22__SPDIF_IN = IOMUX_PAD(0x0520, 0x0258, 2, 0x0738, 0, 0), - MX6_PAD_GPIO4_IO22__SD1_WP = IOMUX_PAD(0x0520, 0x0258, 3, 0x0774, 0, 0), - MX6_PAD_GPIO4_IO22__SD3_WP = IOMUX_PAD(0x0520, 0x0258, 4, 0x0794, 1, 0), - MX6_PAD_GPIO4_IO22__GPIO4_IO22 = IOMUX_PAD(0x0520, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO16__SPDIF_OUT = IOMUX_PAD(0x0524, 0x025C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO16__SD1_CD_B = IOMUX_PAD(0x0524, 0x025C, 3, 0x0770, 0, 0), - MX6_PAD_GPIO4_IO16__SD3_CD_B = IOMUX_PAD(0x0524, 0x025C, 4, 0x0780, 1, 0), - MX6_PAD_GPIO4_IO16__GPIO4_IO16 = IOMUX_PAD(0x0524, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO26__WDOG1_B = IOMUX_PAD(0x0528, 0x0260, 2, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO26__PWM4_OUT = IOMUX_PAD(0x0528, 0x0260, 3, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO26__CCM_PMIC_READY = IOMUX_PAD(0x0528, 0x0260, 4, 0x05AC, 1, 0), - MX6_PAD_GPIO4_IO26__GPIO4_IO26 = IOMUX_PAD(0x0528, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_GPIO4_IO26__SPDIF_EXT_CLK = IOMUX_PAD(0x0528, 0x0260, 6, 0x073C, 0, 0), -}; -#endif /* __ASM_ARCH_IMX6SLL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h deleted file mode 100644 index 5ad93ed..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX6SX_DDR_H__ -#define __ASM_ARCH_MX6SX_DDR_H__ - -#ifndef CONFIG_MX6SX -#error "wrong CPU" -#endif - -#define MX6_IOM_DRAM_DQM0 0x020e02ec -#define MX6_IOM_DRAM_DQM1 0x020e02f0 -#define MX6_IOM_DRAM_DQM2 0x020e02f4 -#define MX6_IOM_DRAM_DQM3 0x020e02f8 - -#define MX6_IOM_DRAM_RAS 0x020e02fc -#define MX6_IOM_DRAM_CAS 0x020e0300 -#define MX6_IOM_DRAM_SDODT0 0x020e0310 -#define MX6_IOM_DRAM_SDODT1 0x020e0314 -#define MX6_IOM_DRAM_SDBA2 0x020e0320 -#define MX6_IOM_DRAM_SDCKE0 0x020e0324 -#define MX6_IOM_DRAM_SDCKE1 0x020e0328 -#define MX6_IOM_DRAM_SDCLK_0 0x020e032c -#define MX6_IOM_DRAM_RESET 0x020e0340 - -#define MX6_IOM_DRAM_SDQS0 0x020e0330 -#define MX6_IOM_DRAM_SDQS1 0x020e0334 -#define MX6_IOM_DRAM_SDQS2 0x020e0338 -#define MX6_IOM_DRAM_SDQS3 0x020e033c - -#define MX6_IOM_GRP_ADDDS 0x020e05f4 -#define MX6_IOM_DDRMODE_CTL 0x020e05f8 -#define MX6_IOM_GRP_DDRPKE 0x020e05fc -#define MX6_IOM_GRP_DDRMODE 0x020e0608 -#define MX6_IOM_GRP_B0DS 0x020e060c -#define MX6_IOM_GRP_B1DS 0x020e0610 -#define MX6_IOM_GRP_CTLDS 0x020e0614 -#define MX6_IOM_GRP_DDR_TYPE 0x020e0618 -#define MX6_IOM_GRP_B2DS 0x020e061c -#define MX6_IOM_GRP_B3DS 0x020e0620 - -#endif /*__ASM_ARCH_MX6SX_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h deleted file mode 100644 index a18e08f..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ /dev/null @@ -1,1674 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MX6_MX6_PINS_H__ -#define __ASM_ARCH_MX6_MX6_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - MX6_PAD_GPIO1_IO00__I2C1_SCL = IOMUX_PAD(0x035C, 0x0014, IOMUX_CONFIG_SION | 0, 0x07A8, 1, 0), - MX6_PAD_GPIO1_IO00__USDHC1_VSELECT = IOMUX_PAD(0x035C, 0x0014, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__SPDIF_LOCK = IOMUX_PAD(0x035C, 0x0014, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__CCM_WAIT = IOMUX_PAD(0x035C, 0x0014, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x0014, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__GPIO1_IO_0 = IOMUX_PAD(0x035C, 0x0014, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 = IOMUX_PAD(0x035C, 0x0014, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__PHY_DTB_1 = IOMUX_PAD(0x035C, 0x0014, 7, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO01__I2C1_SDA = IOMUX_PAD(0x0360, 0x0018, IOMUX_CONFIG_SION | 0, 0x07AC, 1, 0), - MX6_PAD_GPIO1_IO01__USDHC1_RESET_B = IOMUX_PAD(0x0360, 0x0018, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__SPDIF_SR_CLK = IOMUX_PAD(0x0360, 0x0018, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__CCM_STOP = IOMUX_PAD(0x0360, 0x0018, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__WDOG3_WDOG_B = IOMUX_PAD(0x0360, 0x0018, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__GPIO1_IO_1 = IOMUX_PAD(0x0360, 0x0018, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL = IOMUX_PAD(0x0360, 0x0018, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__PHY_DTB_0 = IOMUX_PAD(0x0360, 0x0018, 7, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO02__I2C2_SCL = IOMUX_PAD(0x0364, 0x001C, IOMUX_CONFIG_SION | 0, 0x07B0, 1, 0), - MX6_PAD_GPIO1_IO02__USDHC1_CD_B = IOMUX_PAD(0x0364, 0x001C, 1, 0x0864, 1, 0), - MX6_PAD_GPIO1_IO02__CSI2_MCLK = IOMUX_PAD(0x0364, 0x001C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0364, 0x001C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0364, 0x001C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__GPIO1_IO_2 = IOMUX_PAD(0x0364, 0x001C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__CCM_REF_EN_B = IOMUX_PAD(0x0364, 0x001C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__PHY_TDI = IOMUX_PAD(0x0364, 0x001C, 7, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO03__I2C2_SDA = IOMUX_PAD(0x0368, 0x0020, IOMUX_CONFIG_SION | 0, 0x07B4, 1, 0), - MX6_PAD_GPIO1_IO03__USDHC1_WP = IOMUX_PAD(0x0368, 0x0020, 1, 0x0868, 1, 0), - MX6_PAD_GPIO1_IO03__ENET1_REF_CLK_25M = IOMUX_PAD(0x0368, 0x0020, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK = IOMUX_PAD(0x0368, 0x0020, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__WDOG2_WDOG_B = IOMUX_PAD(0x0368, 0x0020, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__GPIO1_IO_3 = IOMUX_PAD(0x0368, 0x0020, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__CCM_PLL3_BYP = IOMUX_PAD(0x0368, 0x0020, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__PHY_TCK = IOMUX_PAD(0x0368, 0x0020, 7, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO04__UART1_TX = IOMUX_PAD(0x036C, 0x0024, 0, 0x0830, 0, 0), - MX6_PAD_GPIO1_IO04__USDHC2_RESET_B = IOMUX_PAD(0x036C, 0x0024, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__ENET1_MDC = IOMUX_PAD(0x036C, 0x0024, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__OSC32K_32K_OUT = IOMUX_PAD(0x036C, 0x0024, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__ENET2_REF_CLK2 = IOMUX_PAD(0x036C, 0x0024, 4, 0x076C, 0, 0), - MX6_PAD_GPIO1_IO04__GPIO1_IO_4 = IOMUX_PAD(0x036C, 0x0024, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__CCM_PLL2_BYP = IOMUX_PAD(0x036C, 0x0024, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__PHY_TMS = IOMUX_PAD(0x036C, 0x0024, 7, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO05__UART1_RX = IOMUX_PAD(0x0370, 0x0028, 0, 0x0830, 1, 0), - MX6_PAD_GPIO1_IO05__USDHC2_VSELECT = IOMUX_PAD(0x0370, 0x0028, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__ENET1_MDIO = IOMUX_PAD(0x0370, 0x0028, 2, 0x0764, 0, 0), - MX6_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0370, 0x0028, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__ENET1_REF_CLK1 = IOMUX_PAD(0x0370, 0x0028, 4, 0x0760, 0, 0), - MX6_PAD_GPIO1_IO05__GPIO1_IO_5 = IOMUX_PAD(0x0370, 0x0028, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__SRC_TESTER_ACK = IOMUX_PAD(0x0370, 0x0028, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__PHY_TDO = IOMUX_PAD(0x0370, 0x0028, 7, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO06__UART2_TX = IOMUX_PAD(0x0374, 0x002C, 0, 0x0838, 0, 0), - MX6_PAD_GPIO1_IO06__USDHC2_CD_B = IOMUX_PAD(0x0374, 0x002C, 1, 0x086C, 1, 0), - MX6_PAD_GPIO1_IO06__ENET2_MDC = IOMUX_PAD(0x0374, 0x002C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__CSI1_MCLK = IOMUX_PAD(0x0374, 0x002C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__UART1_RTS_B = IOMUX_PAD(0x0374, 0x002C, 4, 0x082C, 0, 0), - MX6_PAD_GPIO1_IO06__GPIO1_IO_6 = IOMUX_PAD(0x0374, 0x002C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__SRC_ANY_PU_RESET = IOMUX_PAD(0x0374, 0x002C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x0374, 0x002C, 7, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO07__UART2_RX = IOMUX_PAD(0x0378, 0x0030, 0, 0x0838, 1, 0), - MX6_PAD_GPIO1_IO07__USDHC2_WP = IOMUX_PAD(0x0378, 0x0030, 1, 0x0870, 1, 0), - MX6_PAD_GPIO1_IO07__ENET2_MDIO = IOMUX_PAD(0x0378, 0x0030, 2, 0x0770, 0, 0), - MX6_PAD_GPIO1_IO07__AUDMUX_MCLK = IOMUX_PAD(0x0378, 0x0030, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__UART1_CTS_B = IOMUX_PAD(0x0378, 0x0030, 4, 0x082C, 1, 0), - MX6_PAD_GPIO1_IO07__GPIO1_IO_7 = IOMUX_PAD(0x0378, 0x0030, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__SRC_EARLY_RESET = IOMUX_PAD(0x0378, 0x0030, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__DCIC2_OUT = IOMUX_PAD(0x0378, 0x0030, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__VDEC_DEBUG_44 = IOMUX_PAD(0x0378, 0x0030, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO08__USB_OTG1_OC = IOMUX_PAD(0x037C, 0x0034, 0, 0x0860, 0, 0), - MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x037C, 0x0034, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x037C, 0x0034, 2, 0x081C, 0, 0), - MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x037C, 0x0034, 3, 0x069C, 1, 0), - MX6_PAD_GPIO1_IO08__UART2_RTS_B = IOMUX_PAD(0x037C, 0x0034, 4, 0x0834, 0, 0), - MX6_PAD_GPIO1_IO08__GPIO1_IO_8 = IOMUX_PAD(0x037C, 0x0034, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__SRC_SYSTEM_RESET = IOMUX_PAD(0x037C, 0x0034, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__DCIC1_OUT = IOMUX_PAD(0x037C, 0x0034, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__VDEC_DEBUG_43 = IOMUX_PAD(0x037C, 0x0034, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO09__USB_OTG1_PWR = IOMUX_PAD(0x0380, 0x0038, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__WDOG2_WDOG_B = IOMUX_PAD(0x0380, 0x0038, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0380, 0x0038, 2, 0x0820, 0, 0), - MX6_PAD_GPIO1_IO09__CCM_OUT0 = IOMUX_PAD(0x0380, 0x0038, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__UART2_CTS_B = IOMUX_PAD(0x0380, 0x0038, 4, 0x0834, 1, 0), - MX6_PAD_GPIO1_IO09__GPIO1_IO_9 = IOMUX_PAD(0x0380, 0x0038, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__SRC_INT_BOOT = IOMUX_PAD(0x0380, 0x0038, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 = IOMUX_PAD(0x0380, 0x0038, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__VDEC_DEBUG_42 = IOMUX_PAD(0x0380, 0x0038, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID = IOMUX_PAD(0x0384, 0x003C, 0, 0x0624, 0, 0), - MX6_PAD_GPIO1_IO10__SPDIF_EXT_CLK = IOMUX_PAD(0x0384, 0x003C, 1, 0x0828, 0, 0), - MX6_PAD_GPIO1_IO10__PWM1_OUT = IOMUX_PAD(0x0384, 0x003C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO10__CCM_OUT1 = IOMUX_PAD(0x0384, 0x003C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO10__CSI1_FIELD = IOMUX_PAD(0x0384, 0x003C, 4, 0x070C, 1, 0), - MX6_PAD_GPIO1_IO10__GPIO1_IO_10 = IOMUX_PAD(0x0384, 0x003C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO10__CSU_CSU_INT_DEB = IOMUX_PAD(0x0384, 0x003C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 = IOMUX_PAD(0x0384, 0x003C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO10__VDEC_DEBUG_41 = IOMUX_PAD(0x0384, 0x003C, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO11__USB_OTG2_OC = IOMUX_PAD(0x0388, 0x0040, 0, 0x085C, 0, 0), - MX6_PAD_GPIO1_IO11__SPDIF_IN = IOMUX_PAD(0x0388, 0x0040, 1, 0x0824, 2, 0), - MX6_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x0388, 0x0040, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO11__CCM_CLKO1 = IOMUX_PAD(0x0388, 0x0040, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO11__MLB_DATA = IOMUX_PAD(0x0388, 0x0040, 4, 0x07EC, 0, 0), - MX6_PAD_GPIO1_IO11__GPIO1_IO_11 = IOMUX_PAD(0x0388, 0x0040, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0388, 0x0040, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 = IOMUX_PAD(0x0388, 0x0040, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO11__VDEC_DEBUG_40 = IOMUX_PAD(0x0388, 0x0040, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO12__USB_OTG2_PWR = IOMUX_PAD(0x038C, 0x0044, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO12__SPDIF_OUT = IOMUX_PAD(0x038C, 0x0044, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO12__PWM3_OUT = IOMUX_PAD(0x038C, 0x0044, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO12__CCM_CLKO2 = IOMUX_PAD(0x038C, 0x0044, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO12__MLB_CLK = IOMUX_PAD(0x038C, 0x0044, 4, 0x07E8, 0, 0), - MX6_PAD_GPIO1_IO12__GPIO1_IO_12 = IOMUX_PAD(0x038C, 0x0044, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x038C, 0x0044, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 = IOMUX_PAD(0x038C, 0x0044, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO12__VDEC_DEBUG_39 = IOMUX_PAD(0x038C, 0x0044, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO13__WDOG1_WDOG_ANY = IOMUX_PAD(0x0390, 0x0048, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO13__ANATOP_OTG2_ID = IOMUX_PAD(0x0390, 0x0048, 1, 0x0628, 0, 0), - MX6_PAD_GPIO1_IO13__PWM4_OUT = IOMUX_PAD(0x0390, 0x0048, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO13__CCM_OUT2 = IOMUX_PAD(0x0390, 0x0048, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO13__MLB_SIG = IOMUX_PAD(0x0390, 0x0048, 4, 0x07F0, 0, 0), - MX6_PAD_GPIO1_IO13__GPIO1_IO_13 = IOMUX_PAD(0x0390, 0x0048, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0390, 0x0048, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 = IOMUX_PAD(0x0390, 0x0048, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO13__VDEC_DEBUG_38 = IOMUX_PAD(0x0390, 0x0048, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA00__CSI1_DATA_2 = IOMUX_PAD(0x0394, 0x004C, 0, 0x06A8, 0, 0), - MX6_PAD_CSI_DATA00__ESAI_TX_CLK = IOMUX_PAD(0x0394, 0x004C, 1, 0x078C, 1, 0), - MX6_PAD_CSI_DATA00__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0394, 0x004C, 2, 0x0684, 1, 0), - MX6_PAD_CSI_DATA00__I2C1_SCL = IOMUX_PAD(0x0394, 0x004C, IOMUX_CONFIG_SION | 3, 0x07A8, 0, 0), - MX6_PAD_CSI_DATA00__UART6_RI_B = IOMUX_PAD(0x0394, 0x004C, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__GPIO1_IO_14 = IOMUX_PAD(0x0394, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__WEIM_DATA_23 = IOMUX_PAD(0x0394, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__SAI1_TX_BCLK = IOMUX_PAD(0x0394, 0x004C, 7, 0x0800, 0, 0), - MX6_PAD_CSI_DATA00__VADC_DATA_4 = IOMUX_PAD(0x0394, 0x004C, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__MMDC_DEBUG_37 = IOMUX_PAD(0x0394, 0x004C, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA01__CSI1_DATA_3 = IOMUX_PAD(0x0398, 0x0050, 0, 0x06AC, 0, 0), - MX6_PAD_CSI_DATA01__ESAI_TX_FS = IOMUX_PAD(0x0398, 0x0050, 1, 0x077C, 1, 0), - MX6_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0398, 0x0050, 2, 0x0688, 1, 0), - MX6_PAD_CSI_DATA01__I2C1_SDA = IOMUX_PAD(0x0398, 0x0050, IOMUX_CONFIG_SION | 3, 0x07AC, 0, 0), - MX6_PAD_CSI_DATA01__UART6_DSR_B = IOMUX_PAD(0x0398, 0x0050, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__GPIO1_IO_15 = IOMUX_PAD(0x0398, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__WEIM_DATA_22 = IOMUX_PAD(0x0398, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0050, 7, 0x0804, 0, 0), - MX6_PAD_CSI_DATA01__VADC_DATA_5 = IOMUX_PAD(0x0398, 0x0050, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__MMDC_DEBUG_38 = IOMUX_PAD(0x0398, 0x0050, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA02__CSI1_DATA_4 = IOMUX_PAD(0x039C, 0x0054, 0, 0x06B0, 0, 0), - MX6_PAD_CSI_DATA02__ESAI_RX_CLK = IOMUX_PAD(0x039C, 0x0054, 1, 0x0788, 1, 0), - MX6_PAD_CSI_DATA02__AUDMUX_AUD6_RXC = IOMUX_PAD(0x039C, 0x0054, 2, 0x067C, 1, 0), - MX6_PAD_CSI_DATA02__KPP_COL_5 = IOMUX_PAD(0x039C, 0x0054, 3, 0x07C8, 0, 0), - MX6_PAD_CSI_DATA02__UART6_DTR_B = IOMUX_PAD(0x039C, 0x0054, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__GPIO1_IO_16 = IOMUX_PAD(0x039C, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__WEIM_DATA_21 = IOMUX_PAD(0x039C, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__SAI1_RX_BCLK = IOMUX_PAD(0x039C, 0x0054, 7, 0x07F4, 0, 0), - MX6_PAD_CSI_DATA02__VADC_DATA_6 = IOMUX_PAD(0x039C, 0x0054, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__MMDC_DEBUG_39 = IOMUX_PAD(0x039C, 0x0054, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA03__CSI1_DATA_5 = IOMUX_PAD(0x03A0, 0x0058, 0, 0x06B4, 0, 0), - MX6_PAD_CSI_DATA03__ESAI_RX_FS = IOMUX_PAD(0x03A0, 0x0058, 1, 0x0778, 1, 0), - MX6_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x03A0, 0x0058, 2, 0x0680, 1, 0), - MX6_PAD_CSI_DATA03__KPP_ROW_5 = IOMUX_PAD(0x03A0, 0x0058, 3, 0x07D4, 0, 0), - MX6_PAD_CSI_DATA03__UART6_DCD_B = IOMUX_PAD(0x03A0, 0x0058, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__GPIO1_IO_17 = IOMUX_PAD(0x03A0, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__WEIM_DATA_20 = IOMUX_PAD(0x03A0, 0x0058, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__SAI1_RX_SYNC = IOMUX_PAD(0x03A0, 0x0058, 7, 0x07FC, 0, 0), - MX6_PAD_CSI_DATA03__VADC_DATA_7 = IOMUX_PAD(0x03A0, 0x0058, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__MMDC_DEBUG_40 = IOMUX_PAD(0x03A0, 0x0058, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA04__CSI1_DATA_6 = IOMUX_PAD(0x03A4, 0x005C, 0, 0x06B8, 0, 0), - MX6_PAD_CSI_DATA04__ESAI_TX1 = IOMUX_PAD(0x03A4, 0x005C, 1, 0x0794, 1, 0), - MX6_PAD_CSI_DATA04__SPDIF_OUT = IOMUX_PAD(0x03A4, 0x005C, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__KPP_COL_6 = IOMUX_PAD(0x03A4, 0x005C, 3, 0x07CC, 0, 0), - MX6_PAD_CSI_DATA04__UART6_RX = IOMUX_PAD(0x03A4, 0x005C, 4, 0x0858, 0, 0), - MX6_PAD_CSI_DATA04__GPIO1_IO_18 = IOMUX_PAD(0x03A4, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__WEIM_DATA_19 = IOMUX_PAD(0x03A4, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__PWM5_OUT = IOMUX_PAD(0x03A4, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__VADC_DATA_8 = IOMUX_PAD(0x03A4, 0x005C, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__MMDC_DEBUG_41 = IOMUX_PAD(0x03A4, 0x005C, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA05__CSI1_DATA_7 = IOMUX_PAD(0x03A8, 0x0060, 0, 0x06BC, 0, 0), - MX6_PAD_CSI_DATA05__ESAI_TX4_RX1 = IOMUX_PAD(0x03A8, 0x0060, 1, 0x07A0, 1, 0), - MX6_PAD_CSI_DATA05__SPDIF_IN = IOMUX_PAD(0x03A8, 0x0060, 2, 0x0824, 1, 0), - MX6_PAD_CSI_DATA05__KPP_ROW_6 = IOMUX_PAD(0x03A8, 0x0060, 3, 0x07D8, 0, 0), - MX6_PAD_CSI_DATA05__UART6_TX = IOMUX_PAD(0x03A8, 0x0060, 4, 0x0858, 1, 0), - MX6_PAD_CSI_DATA05__GPIO1_IO_19 = IOMUX_PAD(0x03A8, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__WEIM_DATA_18 = IOMUX_PAD(0x03A8, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__PWM6_OUT = IOMUX_PAD(0x03A8, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__VADC_DATA_9 = IOMUX_PAD(0x03A8, 0x0060, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__MMDC_DEBUG_42 = IOMUX_PAD(0x03A8, 0x0060, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA06__CSI1_DATA_8 = IOMUX_PAD(0x03AC, 0x0064, 0, 0x06C0, 0, 0), - MX6_PAD_CSI_DATA06__ESAI_TX2_RX3 = IOMUX_PAD(0x03AC, 0x0064, 1, 0x0798, 1, 0), - MX6_PAD_CSI_DATA06__I2C4_SCL = IOMUX_PAD(0x03AC, 0x0064, IOMUX_CONFIG_SION | 2, 0x07C0, 2, 0), - MX6_PAD_CSI_DATA06__KPP_COL_7 = IOMUX_PAD(0x03AC, 0x0064, 3, 0x07D0, 0, 0), - MX6_PAD_CSI_DATA06__UART6_RTS_B = IOMUX_PAD(0x03AC, 0x0064, 4, 0x0854, 0, 0), - MX6_PAD_CSI_DATA06__GPIO1_IO_20 = IOMUX_PAD(0x03AC, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__WEIM_DATA_17 = IOMUX_PAD(0x03AC, 0x0064, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__DCIC2_OUT = IOMUX_PAD(0x03AC, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__VADC_DATA_10 = IOMUX_PAD(0x03AC, 0x0064, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__MMDC_DEBUG_43 = IOMUX_PAD(0x03AC, 0x0064, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA07__CSI1_DATA_9 = IOMUX_PAD(0x03B0, 0x0068, 0, 0x06C4, 0, 0), - MX6_PAD_CSI_DATA07__ESAI_TX3_RX2 = IOMUX_PAD(0x03B0, 0x0068, 1, 0x079C, 1, 0), - MX6_PAD_CSI_DATA07__I2C4_SDA = IOMUX_PAD(0x03B0, 0x0068, IOMUX_CONFIG_SION | 2, 0x07C4, 2, 0), - MX6_PAD_CSI_DATA07__KPP_ROW_7 = IOMUX_PAD(0x03B0, 0x0068, 3, 0x07DC, 0, 0), - MX6_PAD_CSI_DATA07__UART6_CTS_B = IOMUX_PAD(0x03B0, 0x0068, 4, 0x0854, 1, 0), - MX6_PAD_CSI_DATA07__GPIO1_IO_21 = IOMUX_PAD(0x03B0, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__WEIM_DATA_16 = IOMUX_PAD(0x03B0, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__DCIC1_OUT = IOMUX_PAD(0x03B0, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__VADC_DATA_11 = IOMUX_PAD(0x03B0, 0x0068, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__MMDC_DEBUG_44 = IOMUX_PAD(0x03B0, 0x0068, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_HSYNC__CSI1_HSYNC = IOMUX_PAD(0x03B4, 0x006C, 0, 0x0700, 0, 0), - MX6_PAD_CSI_HSYNC__ESAI_TX0 = IOMUX_PAD(0x03B4, 0x006C, 1, 0x0790, 1, 0), - MX6_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD = IOMUX_PAD(0x03B4, 0x006C, 2, 0x0678, 1, 0), - MX6_PAD_CSI_HSYNC__UART4_RTS_B = IOMUX_PAD(0x03B4, 0x006C, 3, 0x0844, 2, 0), - MX6_PAD_CSI_HSYNC__MQS_LEFT = IOMUX_PAD(0x03B4, 0x006C, 4, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__GPIO1_IO_22 = IOMUX_PAD(0x03B4, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__WEIM_DATA_25 = IOMUX_PAD(0x03B4, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__SAI1_TX_DATA_0 = IOMUX_PAD(0x03B4, 0x006C, 7, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__VADC_DATA_2 = IOMUX_PAD(0x03B4, 0x006C, 8, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__MMDC_DEBUG_35 = IOMUX_PAD(0x03B4, 0x006C, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_MCLK__CSI1_MCLK = IOMUX_PAD(0x03B8, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__ESAI_TX_HF_CLK = IOMUX_PAD(0x03B8, 0x0070, 1, 0x0784, 1, 0), - MX6_PAD_CSI_MCLK__OSC32K_32K_OUT = IOMUX_PAD(0x03B8, 0x0070, 2, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__UART4_RX = IOMUX_PAD(0x03B8, 0x0070, 3, 0x0848, 2, 0), - MX6_PAD_CSI_MCLK__ANATOP_32K_OUT = IOMUX_PAD(0x03B8, 0x0070, 4, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__GPIO1_IO_23 = IOMUX_PAD(0x03B8, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__WEIM_DATA_26 = IOMUX_PAD(0x03B8, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__CSI1_FIELD = IOMUX_PAD(0x03B8, 0x0070, 7, 0x070C, 0, 0), - MX6_PAD_CSI_MCLK__VADC_DATA_1 = IOMUX_PAD(0x03B8, 0x0070, 8, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__MMDC_DEBUG_34 = IOMUX_PAD(0x03B8, 0x0070, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_PIXCLK__CSI1_PIXCLK = IOMUX_PAD(0x03BC, 0x0074, 0, 0x0704, 0, 0), - MX6_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK = IOMUX_PAD(0x03BC, 0x0074, 1, 0x0780, 1, 0), - MX6_PAD_CSI_PIXCLK__AUDMUX_MCLK = IOMUX_PAD(0x03BC, 0x0074, 2, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__UART4_TX = IOMUX_PAD(0x03BC, 0x0074, 3, 0x0848, 3, 0), - MX6_PAD_CSI_PIXCLK__ANATOP_24M_OUT = IOMUX_PAD(0x03BC, 0x0074, 4, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__GPIO1_IO_24 = IOMUX_PAD(0x03BC, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__WEIM_DATA_27 = IOMUX_PAD(0x03BC, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK = IOMUX_PAD(0x03BC, 0x0074, 7, 0x0784, 2, 0), - MX6_PAD_CSI_PIXCLK__VADC_CLK = IOMUX_PAD(0x03BC, 0x0074, 8, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__MMDC_DEBUG_33 = IOMUX_PAD(0x03BC, 0x0074, 9, 0x0000, 0, 0), - - MX6_PAD_CSI_VSYNC__CSI1_VSYNC = IOMUX_PAD(0x03C0, 0x0078, 0, 0x0708, 0, 0), - MX6_PAD_CSI_VSYNC__ESAI_TX5_RX0 = IOMUX_PAD(0x03C0, 0x0078, 1, 0x07A4, 1, 0), - MX6_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x0078, 2, 0x0674, 1, 0), - MX6_PAD_CSI_VSYNC__UART4_CTS_B = IOMUX_PAD(0x03C0, 0x0078, 3, 0x0844, 3, 0), - MX6_PAD_CSI_VSYNC__MQS_RIGHT = IOMUX_PAD(0x03C0, 0x0078, 4, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__GPIO1_IO_25 = IOMUX_PAD(0x03C0, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__WEIM_DATA_24 = IOMUX_PAD(0x03C0, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__SAI1_RX_DATA_0 = IOMUX_PAD(0x03C0, 0x0078, 7, 0x07F8, 0, 0), - MX6_PAD_CSI_VSYNC__VADC_DATA_3 = IOMUX_PAD(0x03C0, 0x0078, 8, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__MMDC_DEBUG_36 = IOMUX_PAD(0x03C0, 0x0078, 9, 0x0000, 0, 0), - - MX6_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x03C4, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_COL__ENET2_MDC = IOMUX_PAD(0x03C4, 0x007C, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_COL__AUDMUX_AUD4_TXC = IOMUX_PAD(0x03C4, 0x007C, 2, 0x0654, 1, 0), - MX6_PAD_ENET1_COL__UART1_RI_B = IOMUX_PAD(0x03C4, 0x007C, 3, 0x0000, 0, 0), - MX6_PAD_ENET1_COL__SPDIF_EXT_CLK = IOMUX_PAD(0x03C4, 0x007C, 4, 0x0828, 1, 0), - MX6_PAD_ENET1_COL__GPIO2_IO_0 = IOMUX_PAD(0x03C4, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_COL__CSI2_DATA_23 = IOMUX_PAD(0x03C4, 0x007C, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_COL__LCDIF2_DATA_16 = IOMUX_PAD(0x03C4, 0x007C, 7, 0x0000, 0, 0), - MX6_PAD_ENET1_COL__VDEC_DEBUG_37 = IOMUX_PAD(0x03C4, 0x007C, 8, 0x0000, 0, 0), - MX6_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 = IOMUX_PAD(0x03C4, 0x007C, 9, 0x0000, 0, 0), - - MX6_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x03C8, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_CRS__ENET2_MDIO = IOMUX_PAD(0x03C8, 0x0080, 1, 0x0770, 1, 0), - MX6_PAD_ENET1_CRS__AUDMUX_AUD4_TXD = IOMUX_PAD(0x03C8, 0x0080, 2, 0x0648, 1, 0), - MX6_PAD_ENET1_CRS__UART1_DCD_B = IOMUX_PAD(0x03C8, 0x0080, 3, 0x0000, 0, 0), - MX6_PAD_ENET1_CRS__SPDIF_LOCK = IOMUX_PAD(0x03C8, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_CRS__GPIO2_IO_1 = IOMUX_PAD(0x03C8, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_CRS__CSI2_DATA_22 = IOMUX_PAD(0x03C8, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_CRS__LCDIF2_DATA_17 = IOMUX_PAD(0x03C8, 0x0080, 7, 0x0000, 0, 0), - MX6_PAD_ENET1_CRS__VDEC_DEBUG_36 = IOMUX_PAD(0x03C8, 0x0080, 8, 0x0000, 0, 0), - MX6_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 = IOMUX_PAD(0x03C8, 0x0080, 9, 0x0000, 0, 0), - - MX6_PAD_ENET1_MDC__ENET1_MDC = IOMUX_PAD(0x03CC, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_MDC__ENET2_MDC = IOMUX_PAD(0x03CC, 0x0084, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x03CC, 0x0084, 2, 0x0638, 1, 0), - MX6_PAD_ENET1_MDC__ANATOP_24M_OUT = IOMUX_PAD(0x03CC, 0x0084, 3, 0x0000, 0, 0), - MX6_PAD_ENET1_MDC__EPIT2_OUT = IOMUX_PAD(0x03CC, 0x0084, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_MDC__GPIO2_IO_2 = IOMUX_PAD(0x03CC, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_MDC__USB_OTG1_PWR = IOMUX_PAD(0x03CC, 0x0084, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_MDC__PWM7_OUT = IOMUX_PAD(0x03CC, 0x0084, 7, 0x0000, 0, 0), - - MX6_PAD_ENET1_MDIO__ENET1_MDIO = IOMUX_PAD(0x03D0, 0x0088, 0, 0x0764, 1, 0), - MX6_PAD_ENET1_MDIO__ENET2_MDIO = IOMUX_PAD(0x03D0, 0x0088, 1, 0x0770, 2, 0), - MX6_PAD_ENET1_MDIO__AUDMUX_MCLK = IOMUX_PAD(0x03D0, 0x0088, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_MDIO__OSC32K_32K_OUT = IOMUX_PAD(0x03D0, 0x0088, 3, 0x0000, 0, 0), - MX6_PAD_ENET1_MDIO__EPIT1_OUT = IOMUX_PAD(0x03D0, 0x0088, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_MDIO__GPIO2_IO_3 = IOMUX_PAD(0x03D0, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_MDIO__USB_OTG1_OC = IOMUX_PAD(0x03D0, 0x0088, 6, 0x0860, 1, 0), - MX6_PAD_ENET1_MDIO__PWM8_OUT = IOMUX_PAD(0x03D0, 0x0088, 7, 0x0000, 0, 0), - - MX6_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x03D4, 0x008C, 0, 0x0768, 0, 0), - MX6_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M = IOMUX_PAD(0x03D4, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x03D4, 0x008C, 2, 0x0658, 1, 0), - MX6_PAD_ENET1_RX_CLK__UART1_DSR_B = IOMUX_PAD(0x03D4, 0x008C, 3, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_CLK__SPDIF_OUT = IOMUX_PAD(0x03D4, 0x008C, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_CLK__GPIO2_IO_4 = IOMUX_PAD(0x03D4, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_CLK__CSI2_DATA_21 = IOMUX_PAD(0x03D4, 0x008C, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 = IOMUX_PAD(0x03D4, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 = IOMUX_PAD(0x03D4, 0x008C, 8, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 = IOMUX_PAD(0x03D4, 0x008C, 9, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x03D8, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x03D8, 0x0090, 1, 0x0760, 1, 0), - MX6_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD = IOMUX_PAD(0x03D8, 0x0090, 2, 0x0644, 1, 0), - MX6_PAD_ENET1_TX_CLK__UART1_DTR_B = IOMUX_PAD(0x03D8, 0x0090, 3, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x03D8, 0x0090, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__GPIO2_IO_5 = IOMUX_PAD(0x03D8, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__CSI2_DATA_20 = IOMUX_PAD(0x03D8, 0x0090, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 = IOMUX_PAD(0x03D8, 0x0090, 7, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 = IOMUX_PAD(0x03D8, 0x0090, 8, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 = IOMUX_PAD(0x03D8, 0x0090, 9, 0x0000, 0, 0), - - MX6_PAD_ENET2_COL__ENET2_COL = IOMUX_PAD(0x03DC, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_COL__ENET1_MDC = IOMUX_PAD(0x03DC, 0x0094, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_COL__AUDMUX_AUD4_RXC = IOMUX_PAD(0x03DC, 0x0094, 2, 0x064C, 1, 0), - MX6_PAD_ENET2_COL__UART1_RX = IOMUX_PAD(0x03DC, 0x0094, 3, 0x0830, 2, 0), - MX6_PAD_ENET2_COL__SPDIF_IN = IOMUX_PAD(0x03DC, 0x0094, 4, 0x0824, 3, 0), - MX6_PAD_ENET2_COL__GPIO2_IO_6 = IOMUX_PAD(0x03DC, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_COL__ANATOP_OTG1_ID = IOMUX_PAD(0x03DC, 0x0094, 6, 0x0624, 1, 0), - MX6_PAD_ENET2_COL__LCDIF2_DATA_20 = IOMUX_PAD(0x03DC, 0x0094, 7, 0x0000, 0, 0), - MX6_PAD_ENET2_COL__VDEC_DEBUG_33 = IOMUX_PAD(0x03DC, 0x0094, 8, 0x0000, 0, 0), - MX6_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 = IOMUX_PAD(0x03DC, 0x0094, 9, 0x0000, 0, 0), - - MX6_PAD_ENET2_CRS__ENET2_CRS = IOMUX_PAD(0x03E0, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_CRS__ENET1_MDIO = IOMUX_PAD(0x03E0, 0x0098, 1, 0x0764, 2, 0), - MX6_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x03E0, 0x0098, 2, 0x0650, 1, 0), - MX6_PAD_ENET2_CRS__UART1_TX = IOMUX_PAD(0x03E0, 0x0098, 3, 0x0830, 3, 0), - MX6_PAD_ENET2_CRS__MLB_SIG = IOMUX_PAD(0x03E0, 0x0098, 4, 0x07F0, 1, 0), - MX6_PAD_ENET2_CRS__GPIO2_IO_7 = IOMUX_PAD(0x03E0, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_CRS__ANATOP_OTG2_ID = IOMUX_PAD(0x03E0, 0x0098, 6, 0x0628, 1, 0), - MX6_PAD_ENET2_CRS__LCDIF2_DATA_21 = IOMUX_PAD(0x03E0, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_ENET2_CRS__VDEC_DEBUG_32 = IOMUX_PAD(0x03E0, 0x0098, 8, 0x0000, 0, 0), - MX6_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 = IOMUX_PAD(0x03E0, 0x0098, 9, 0x0000, 0, 0), - - MX6_PAD_ENET2_RX_CLK__ENET2_RX_CLK = IOMUX_PAD(0x03E4, 0x009C, 0, 0x0774, 0, 0), - MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M = IOMUX_PAD(0x03E4, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_CLK__I2C3_SCL = IOMUX_PAD(0x03E4, 0x009C, IOMUX_CONFIG_SION | 2, 0x07B8, 1, 0), - MX6_PAD_ENET2_RX_CLK__UART1_RTS_B = IOMUX_PAD(0x03E4, 0x009C, 3, 0x082C, 2, 0), - MX6_PAD_ENET2_RX_CLK__MLB_DATA = IOMUX_PAD(0x03E4, 0x009C, 4, 0x07EC, 1, 0), - MX6_PAD_ENET2_RX_CLK__GPIO2_IO_8 = IOMUX_PAD(0x03E4, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_CLK__USB_OTG2_OC = IOMUX_PAD(0x03E4, 0x009C, 6, 0x085C, 1, 0), - MX6_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 = IOMUX_PAD(0x03E4, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 = IOMUX_PAD(0x03E4, 0x009C, 8, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 = IOMUX_PAD(0x03E4, 0x009C, 9, 0x0000, 0, 0), - - MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x03E8, 0x00A0, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x03E8, 0x00A0, 1, 0x076C, 1, 0), - MX6_PAD_ENET2_TX_CLK__I2C3_SDA = IOMUX_PAD(0x03E8, 0x00A0, IOMUX_CONFIG_SION | 2, 0x07BC, 1, 0), - MX6_PAD_ENET2_TX_CLK__UART1_CTS_B = IOMUX_PAD(0x03E8, 0x00A0, 3, 0x082C, 3, 0), - MX6_PAD_ENET2_TX_CLK__MLB_CLK = IOMUX_PAD(0x03E8, 0x00A0, 4, 0x07E8, 1, 0), - MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 = IOMUX_PAD(0x03E8, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__USB_OTG2_PWR = IOMUX_PAD(0x03E8, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 = IOMUX_PAD(0x03E8, 0x00A0, 7, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 = IOMUX_PAD(0x03E8, 0x00A0, 8, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 = IOMUX_PAD(0x03E8, 0x00A0, 9, 0x0000, 0, 0), - - MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x03EC, 0x00A4, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__USDHC3_CD_B = IOMUX_PAD(0x03EC, 0x00A4, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART6_RTS_B = IOMUX_PAD(0x03EC, 0x00A4, 2, 0x0854, 2, 0), - MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x00A4, 3, 0x0710, 0, 0), - MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x03EC, 0x00A4, 4, 0x066C, 0, 0), - MX6_PAD_KEY_COL0__GPIO2_IO_10 = IOMUX_PAD(0x03EC, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03EC, 0x00A4, 6, 0x0820, 1, 0), - MX6_PAD_KEY_COL0__SAI2_TX_BCLK = IOMUX_PAD(0x03EC, 0x00A4, 7, 0x0814, 0, 0), - MX6_PAD_KEY_COL0__VADC_DATA_0 = IOMUX_PAD(0x03EC, 0x00A4, 8, 0x0000, 0, 0), - - MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x03F0, 0x00A8, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC3_RESET_B = IOMUX_PAD(0x03F0, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART6_TX = IOMUX_PAD(0x03F0, 0x00A8, 2, 0x0858, 2, 0), - MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x03F0, 0x00A8, 3, 0x0714, 0, 0), - MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x03F0, 0x00A8, 4, 0x0670, 0, 0), - MX6_PAD_KEY_COL1__GPIO2_IO_11 = IOMUX_PAD(0x03F0, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC3_RESET = IOMUX_PAD(0x03F0, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__SAI2_TX_SYNC = IOMUX_PAD(0x03F0, 0x00A8, 7, 0x0818, 0, 0), - - MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x03F4, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USDHC4_CD_B = IOMUX_PAD(0x03F4, 0x00AC, 1, 0x0874, 1, 0), - MX6_PAD_KEY_COL2__UART5_RTS_B = IOMUX_PAD(0x03F4, 0x00AC, 2, 0x084C, 2, 0), - MX6_PAD_KEY_COL2__CAN1_TX = IOMUX_PAD(0x03F4, 0x00AC, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__CANFD_TX1 = IOMUX_PAD(0x03F4, 0x00AC, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO2_IO_12 = IOMUX_PAD(0x03F4, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__WEIM_DATA_30 = IOMUX_PAD(0x03F4, 0x00AC, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ECSPI1_RDY = IOMUX_PAD(0x03F4, 0x00AC, 7, 0x0000, 0, 0), - - MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x03F8, 0x00B0, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__USDHC4_LCTL = IOMUX_PAD(0x03F8, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__UART5_TX = IOMUX_PAD(0x03F8, 0x00B0, 2, 0x0850, 2, 0), - MX6_PAD_KEY_COL3__CAN2_TX = IOMUX_PAD(0x03F8, 0x00B0, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__CANFD_TX2 = IOMUX_PAD(0x03F8, 0x00B0, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__GPIO2_IO_13 = IOMUX_PAD(0x03F8, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__WEIM_DATA_28 = IOMUX_PAD(0x03F8, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__ECSPI1_SS2 = IOMUX_PAD(0x03F8, 0x00B0, 7, 0x0000, 0, 0), - - MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), - MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), - MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__WEIM_CRE = IOMUX_PAD(0x03FC, 0x00B4, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__SAI2_RX_BCLK = IOMUX_PAD(0x03FC, 0x00B4, 7, 0x0808, 0, 0), - - MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0400, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__USDHC3_WP = IOMUX_PAD(0x0400, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART6_CTS_B = IOMUX_PAD(0x0400, 0x00B8, 2, 0x0854, 3, 0), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0400, 0x00B8, 3, 0x0718, 0, 0), - MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0400, 0x00B8, 4, 0x0660, 0, 0), - MX6_PAD_KEY_ROW0__GPIO2_IO_15 = IOMUX_PAD(0x0400, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x0400, 0x00B8, 6, 0x081C, 1, 0), - MX6_PAD_KEY_ROW0__SAI2_TX_DATA_0 = IOMUX_PAD(0x0400, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__GPU_IDLE = IOMUX_PAD(0x0400, 0x00B8, 8, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0404, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__USDHC4_VSELECT = IOMUX_PAD(0x0404, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART6_RX = IOMUX_PAD(0x0404, 0x00BC, 2, 0x0858, 3, 0), - MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00BC, 3, 0x071C, 0, 0), - MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0404, 0x00BC, 4, 0x065C, 0, 0), - MX6_PAD_KEY_ROW1__GPIO2_IO_16 = IOMUX_PAD(0x0404, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__WEIM_DATA_31 = IOMUX_PAD(0x0404, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SAI2_RX_DATA_0 = IOMUX_PAD(0x0404, 0x00BC, 7, 0x080C, 0, 0), - MX6_PAD_KEY_ROW1__M4_NMI = IOMUX_PAD(0x0404, 0x00BC, 8, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x0408, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__USDHC4_WP = IOMUX_PAD(0x0408, 0x00C0, 1, 0x0878, 1, 0), - MX6_PAD_KEY_ROW2__UART5_CTS_B = IOMUX_PAD(0x0408, 0x00C0, 2, 0x084C, 3, 0), - MX6_PAD_KEY_ROW2__CAN1_RX = IOMUX_PAD(0x0408, 0x00C0, 3, 0x068C, 1, 0), - MX6_PAD_KEY_ROW2__CANFD_RX1 = IOMUX_PAD(0x0408, 0x00C0, 4, 0x0694, 1, 0), - MX6_PAD_KEY_ROW2__GPIO2_IO_17 = IOMUX_PAD(0x0408, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__WEIM_DATA_29 = IOMUX_PAD(0x0408, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI1_SS3 = IOMUX_PAD(0x0408, 0x00C0, 7, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x040C, 0x00C4, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__USDHC3_LCTL = IOMUX_PAD(0x040C, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__UART5_RX = IOMUX_PAD(0x040C, 0x00C4, 2, 0x0850, 3, 0), - MX6_PAD_KEY_ROW3__CAN2_RX = IOMUX_PAD(0x040C, 0x00C4, 3, 0x0690, 1, 0), - MX6_PAD_KEY_ROW3__CANFD_RX2 = IOMUX_PAD(0x040C, 0x00C4, 4, 0x0698, 1, 0), - MX6_PAD_KEY_ROW3__GPIO2_IO_18 = IOMUX_PAD(0x040C, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__WEIM_DTACK_B = IOMUX_PAD(0x040C, 0x00C4, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__ECSPI1_SS1 = IOMUX_PAD(0x040C, 0x00C4, 7, 0x0000, 0, 0), - - MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0), - MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), - MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), - MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0410, 0x00C8, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__SAI2_RX_SYNC = IOMUX_PAD(0x0410, 0x00C8, 7, 0x0810, 0, 0), - - MX6_PAD_LCD1_CLK__LCDIF1_CLK = IOMUX_PAD(0x0414, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_CLK__LCDIF1_WR_RWN = IOMUX_PAD(0x0414, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_CLK__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0414, 0x00CC, 2, 0x0634, 1, 0), - MX6_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0414, 0x00CC, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_CLK__CSI1_DATA_16 = IOMUX_PAD(0x0414, 0x00CC, 4, 0x06DC, 0, 0), - MX6_PAD_LCD1_CLK__GPIO3_IO_0 = IOMUX_PAD(0x0414, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_CLK__USDHC1_WP = IOMUX_PAD(0x0414, 0x00CC, 6, 0x0868, 0, 0), - MX6_PAD_LCD1_CLK__SIM_M_HADDR_16 = IOMUX_PAD(0x0414, 0x00CC, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_CLK__VADC_TEST_0 = IOMUX_PAD(0x0414, 0x00CC, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0414, 0x00CC, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 = IOMUX_PAD(0x0418, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__WEIM_CS1_B = IOMUX_PAD(0x0418, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__M4_TRACE_0 = IOMUX_PAD(0x0418, 0x00D0, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__KITTEN_TRACE_0 = IOMUX_PAD(0x0418, 0x00D0, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__CSI1_DATA_20 = IOMUX_PAD(0x0418, 0x00D0, 4, 0x06EC, 0, 0), - MX6_PAD_LCD1_DATA00__GPIO3_IO_1 = IOMUX_PAD(0x0418, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__SRC_BT_CFG_0 = IOMUX_PAD(0x0418, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__SIM_M_HADDR_21 = IOMUX_PAD(0x0418, 0x00D0, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__VADC_TEST_5 = IOMUX_PAD(0x0418, 0x00D0, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA00__MMDC_DEBUG_5 = IOMUX_PAD(0x0418, 0x00D0, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 = IOMUX_PAD(0x041C, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__WEIM_CS2_B = IOMUX_PAD(0x041C, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__M4_TRACE_1 = IOMUX_PAD(0x041C, 0x00D4, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__KITTEN_TRACE_1 = IOMUX_PAD(0x041C, 0x00D4, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__CSI1_DATA_21 = IOMUX_PAD(0x041C, 0x00D4, 4, 0x06F0, 0, 0), - MX6_PAD_LCD1_DATA01__GPIO3_IO_2 = IOMUX_PAD(0x041C, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__SRC_BT_CFG_1 = IOMUX_PAD(0x041C, 0x00D4, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__SIM_M_HADDR_22 = IOMUX_PAD(0x041C, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__VADC_TEST_6 = IOMUX_PAD(0x041C, 0x00D4, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA01__MMDC_DEBUG_6 = IOMUX_PAD(0x041C, 0x00D4, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 = IOMUX_PAD(0x0420, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__WEIM_CS3_B = IOMUX_PAD(0x0420, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__M4_TRACE_2 = IOMUX_PAD(0x0420, 0x00D8, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__KITTEN_TRACE_2 = IOMUX_PAD(0x0420, 0x00D8, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__CSI1_DATA_22 = IOMUX_PAD(0x0420, 0x00D8, 4, 0x06F4, 0, 0), - MX6_PAD_LCD1_DATA02__GPIO3_IO_3 = IOMUX_PAD(0x0420, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__SRC_BT_CFG_2 = IOMUX_PAD(0x0420, 0x00D8, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__SIM_M_HADDR_23 = IOMUX_PAD(0x0420, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__VADC_TEST_7 = IOMUX_PAD(0x0420, 0x00D8, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA02__MMDC_DEBUG_7 = IOMUX_PAD(0x0420, 0x00D8, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 = IOMUX_PAD(0x0424, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 = IOMUX_PAD(0x0424, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__M4_TRACE_3 = IOMUX_PAD(0x0424, 0x00DC, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__KITTEN_TRACE_3 = IOMUX_PAD(0x0424, 0x00DC, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__CSI1_DATA_23 = IOMUX_PAD(0x0424, 0x00DC, 4, 0x06F8, 0, 0), - MX6_PAD_LCD1_DATA03__GPIO3_IO_4 = IOMUX_PAD(0x0424, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__SRC_BT_CFG_3 = IOMUX_PAD(0x0424, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__SIM_M_HADDR_24 = IOMUX_PAD(0x0424, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__VADC_TEST_8 = IOMUX_PAD(0x0424, 0x00DC, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA03__MMDC_DEBUG_8 = IOMUX_PAD(0x0424, 0x00DC, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 = IOMUX_PAD(0x0428, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 = IOMUX_PAD(0x0428, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA04__KITTEN_TRACE_4 = IOMUX_PAD(0x0428, 0x00E0, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA04__CSI1_VSYNC = IOMUX_PAD(0x0428, 0x00E0, 4, 0x0708, 1, 0), - MX6_PAD_LCD1_DATA04__GPIO3_IO_5 = IOMUX_PAD(0x0428, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA04__SRC_BT_CFG_4 = IOMUX_PAD(0x0428, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA04__SIM_M_HADDR_25 = IOMUX_PAD(0x0428, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA04__VADC_TEST_9 = IOMUX_PAD(0x0428, 0x00E0, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA04__MMDC_DEBUG_9 = IOMUX_PAD(0x0428, 0x00E0, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 = IOMUX_PAD(0x042C, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA05__WEIM_ADDR_26 = IOMUX_PAD(0x042C, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA05__KITTEN_TRACE_5 = IOMUX_PAD(0x042C, 0x00E4, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA05__CSI1_HSYNC = IOMUX_PAD(0x042C, 0x00E4, 4, 0x0700, 1, 0), - MX6_PAD_LCD1_DATA05__GPIO3_IO_6 = IOMUX_PAD(0x042C, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA05__SRC_BT_CFG_5 = IOMUX_PAD(0x042C, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA05__SIM_M_HADDR_26 = IOMUX_PAD(0x042C, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA05__VADC_TEST_10 = IOMUX_PAD(0x042C, 0x00E4, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA05__MMDC_DEBUG_10 = IOMUX_PAD(0x042C, 0x00E4, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 = IOMUX_PAD(0x0430, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA06__WEIM_EB_B_2 = IOMUX_PAD(0x0430, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA06__KITTEN_TRACE_6 = IOMUX_PAD(0x0430, 0x00E8, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA06__CSI1_PIXCLK = IOMUX_PAD(0x0430, 0x00E8, 4, 0x0704, 1, 0), - MX6_PAD_LCD1_DATA06__GPIO3_IO_7 = IOMUX_PAD(0x0430, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA06__SRC_BT_CFG_6 = IOMUX_PAD(0x0430, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA06__SIM_M_HADDR_27 = IOMUX_PAD(0x0430, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA06__VADC_TEST_11 = IOMUX_PAD(0x0430, 0x00E8, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA06__MMDC_DEBUG_11 = IOMUX_PAD(0x0430, 0x00E8, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 = IOMUX_PAD(0x0434, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__WEIM_EB_B_3 = IOMUX_PAD(0x0434, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__KITTEN_TRACE_7 = IOMUX_PAD(0x0434, 0x00EC, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__CSI1_MCLK = IOMUX_PAD(0x0434, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__GPIO3_IO_8 = IOMUX_PAD(0x0434, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__SRC_BT_CFG_7 = IOMUX_PAD(0x0434, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__SIM_M_HADDR_28 = IOMUX_PAD(0x0434, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__VADC_TEST_12 = IOMUX_PAD(0x0434, 0x00EC, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA07__MMDC_DEBUG_12 = IOMUX_PAD(0x0434, 0x00EC, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 = IOMUX_PAD(0x0438, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA08__WEIM_AD_8 = IOMUX_PAD(0x0438, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA08__KITTEN_TRACE_8 = IOMUX_PAD(0x0438, 0x00F0, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA08__CSI1_DATA_9 = IOMUX_PAD(0x0438, 0x00F0, 4, 0x06C4, 1, 0), - MX6_PAD_LCD1_DATA08__GPIO3_IO_9 = IOMUX_PAD(0x0438, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA08__SRC_BT_CFG_8 = IOMUX_PAD(0x0438, 0x00F0, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA08__SIM_M_HADDR_29 = IOMUX_PAD(0x0438, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA08__VADC_TEST_13 = IOMUX_PAD(0x0438, 0x00F0, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA08__MMDC_DEBUG_13 = IOMUX_PAD(0x0438, 0x00F0, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 = IOMUX_PAD(0x043C, 0x00F4, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA09__WEIM_AD_9 = IOMUX_PAD(0x043C, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA09__KITTEN_TRACE_9 = IOMUX_PAD(0x043C, 0x00F4, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA09__CSI1_DATA_8 = IOMUX_PAD(0x043C, 0x00F4, 4, 0x06C0, 1, 0), - MX6_PAD_LCD1_DATA09__GPIO3_IO_10 = IOMUX_PAD(0x043C, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA09__SRC_BT_CFG_9 = IOMUX_PAD(0x043C, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA09__SIM_M_HADDR_30 = IOMUX_PAD(0x043C, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA09__VADC_TEST_14 = IOMUX_PAD(0x043C, 0x00F4, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA09__MMDC_DEBUG_14 = IOMUX_PAD(0x043C, 0x00F4, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 = IOMUX_PAD(0x0440, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA10__WEIM_AD_10 = IOMUX_PAD(0x0440, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA10__KITTEN_TRACE_10 = IOMUX_PAD(0x0440, 0x00F8, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA10__CSI1_DATA_7 = IOMUX_PAD(0x0440, 0x00F8, 4, 0x06BC, 1, 0), - MX6_PAD_LCD1_DATA10__GPIO3_IO_11 = IOMUX_PAD(0x0440, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0440, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA10__SIM_M_HADDR_31 = IOMUX_PAD(0x0440, 0x00F8, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA10__VADC_TEST_15 = IOMUX_PAD(0x0440, 0x00F8, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA10__MMDC_DEBUG_15 = IOMUX_PAD(0x0440, 0x00F8, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 = IOMUX_PAD(0x0444, 0x00FC, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA11__WEIM_AD_11 = IOMUX_PAD(0x0444, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA11__KITTEN_TRACE_11 = IOMUX_PAD(0x0444, 0x00FC, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA11__CSI1_DATA_6 = IOMUX_PAD(0x0444, 0x00FC, 4, 0x06B8, 1, 0), - MX6_PAD_LCD1_DATA11__GPIO3_IO_12 = IOMUX_PAD(0x0444, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0444, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA11__SIM_M_HBURST_0 = IOMUX_PAD(0x0444, 0x00FC, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA11__VADC_TEST_16 = IOMUX_PAD(0x0444, 0x00FC, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA11__MMDC_DEBUG_16 = IOMUX_PAD(0x0444, 0x00FC, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 = IOMUX_PAD(0x0448, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA12__WEIM_AD_12 = IOMUX_PAD(0x0448, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA12__KITTEN_TRACE_12 = IOMUX_PAD(0x0448, 0x0100, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA12__CSI1_DATA_5 = IOMUX_PAD(0x0448, 0x0100, 4, 0x06B4, 1, 0), - MX6_PAD_LCD1_DATA12__GPIO3_IO_13 = IOMUX_PAD(0x0448, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0448, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA12__SIM_M_HBURST_1 = IOMUX_PAD(0x0448, 0x0100, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA12__VADC_TEST_17 = IOMUX_PAD(0x0448, 0x0100, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA12__MMDC_DEBUG_17 = IOMUX_PAD(0x0448, 0x0100, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 = IOMUX_PAD(0x044C, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA13__WEIM_AD_13 = IOMUX_PAD(0x044C, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA13__KITTEN_TRACE_13 = IOMUX_PAD(0x044C, 0x0104, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA13__CSI1_DATA_4 = IOMUX_PAD(0x044C, 0x0104, 4, 0x06B0, 1, 0), - MX6_PAD_LCD1_DATA13__GPIO3_IO_14 = IOMUX_PAD(0x044C, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA13__SRC_BT_CFG_13 = IOMUX_PAD(0x044C, 0x0104, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA13__SIM_M_HBURST_2 = IOMUX_PAD(0x044C, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA13__VADC_TEST_18 = IOMUX_PAD(0x044C, 0x0104, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA13__MMDC_DEBUG_18 = IOMUX_PAD(0x044C, 0x0104, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 = IOMUX_PAD(0x0450, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA14__WEIM_AD_14 = IOMUX_PAD(0x0450, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA14__KITTEN_TRACE_14 = IOMUX_PAD(0x0450, 0x0108, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA14__CSI1_DATA_3 = IOMUX_PAD(0x0450, 0x0108, 4, 0x06AC, 1, 0), - MX6_PAD_LCD1_DATA14__GPIO3_IO_15 = IOMUX_PAD(0x0450, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0450, 0x0108, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA14__SIM_M_HMASTLOCK = IOMUX_PAD(0x0450, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA14__VADC_TEST_19 = IOMUX_PAD(0x0450, 0x0108, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA14__MMDC_DEBUG_19 = IOMUX_PAD(0x0450, 0x0108, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 = IOMUX_PAD(0x0454, 0x010C, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA15__WEIM_AD_15 = IOMUX_PAD(0x0454, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA15__KITTEN_TRACE_15 = IOMUX_PAD(0x0454, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA15__CSI1_DATA_2 = IOMUX_PAD(0x0454, 0x010C, 4, 0x06A8, 1, 0), - MX6_PAD_LCD1_DATA15__GPIO3_IO_16 = IOMUX_PAD(0x0454, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0454, 0x010C, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA15__SIM_M_HPROT_0 = IOMUX_PAD(0x0454, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA15__VDEC_DEBUG_0 = IOMUX_PAD(0x0454, 0x010C, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA15__MMDC_DEBUG_20 = IOMUX_PAD(0x0454, 0x010C, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 = IOMUX_PAD(0x0458, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 = IOMUX_PAD(0x0458, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__M4_TRACE_CLK = IOMUX_PAD(0x0458, 0x0110, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__KITTEN_TRACE_CLK = IOMUX_PAD(0x0458, 0x0110, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__CSI1_DATA_1 = IOMUX_PAD(0x0458, 0x0110, 4, 0x06A4, 0, 0), - MX6_PAD_LCD1_DATA16__GPIO3_IO_17 = IOMUX_PAD(0x0458, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__SRC_BT_CFG_24 = IOMUX_PAD(0x0458, 0x0110, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__SIM_M_HPROT_1 = IOMUX_PAD(0x0458, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__VDEC_DEBUG_1 = IOMUX_PAD(0x0458, 0x0110, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA16__MMDC_DEBUG_21 = IOMUX_PAD(0x0458, 0x0110, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 = IOMUX_PAD(0x045C, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 = IOMUX_PAD(0x045C, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA17__KITTEN_TRACE_CTL = IOMUX_PAD(0x045C, 0x0114, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA17__CSI1_DATA_0 = IOMUX_PAD(0x045C, 0x0114, 4, 0x06A0, 0, 0), - MX6_PAD_LCD1_DATA17__GPIO3_IO_18 = IOMUX_PAD(0x045C, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA17__SRC_BT_CFG_25 = IOMUX_PAD(0x045C, 0x0114, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA17__SIM_M_HPROT_2 = IOMUX_PAD(0x045C, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA17__VDEC_DEBUG_2 = IOMUX_PAD(0x045C, 0x0114, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA17__MMDC_DEBUG_22 = IOMUX_PAD(0x045C, 0x0114, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 = IOMUX_PAD(0x0460, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 = IOMUX_PAD(0x0460, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__M4_EVENTO = IOMUX_PAD(0x0460, 0x0118, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__KITTEN_EVENTO = IOMUX_PAD(0x0460, 0x0118, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__CSI1_DATA_15 = IOMUX_PAD(0x0460, 0x0118, 4, 0x06D8, 0, 0), - MX6_PAD_LCD1_DATA18__GPIO3_IO_19 = IOMUX_PAD(0x0460, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__SRC_BT_CFG_26 = IOMUX_PAD(0x0460, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__SIM_M_HPROT_3 = IOMUX_PAD(0x0460, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__VDEC_DEBUG_3 = IOMUX_PAD(0x0460, 0x0118, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA18__MMDC_DEBUG_23 = IOMUX_PAD(0x0460, 0x0118, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 = IOMUX_PAD(0x0464, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 = IOMUX_PAD(0x0464, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA19__M4_TRACE_SWO = IOMUX_PAD(0x0464, 0x011C, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA19__CSI1_DATA_14 = IOMUX_PAD(0x0464, 0x011C, 4, 0x06D4, 0, 0), - MX6_PAD_LCD1_DATA19__GPIO3_IO_20 = IOMUX_PAD(0x0464, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA19__SRC_BT_CFG_27 = IOMUX_PAD(0x0464, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA19__SIM_M_HREADYOUT = IOMUX_PAD(0x0464, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA19__VDEC_DEBUG_4 = IOMUX_PAD(0x0464, 0x011C, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA19__MMDC_DEBUG_24 = IOMUX_PAD(0x0464, 0x011C, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 = IOMUX_PAD(0x0468, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 = IOMUX_PAD(0x0468, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__PWM8_OUT = IOMUX_PAD(0x0468, 0x0120, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0468, 0x0120, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__CSI1_DATA_13 = IOMUX_PAD(0x0468, 0x0120, 4, 0x06D0, 0, 0), - MX6_PAD_LCD1_DATA20__GPIO3_IO_21 = IOMUX_PAD(0x0468, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__SRC_BT_CFG_28 = IOMUX_PAD(0x0468, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__SIM_M_HRESP = IOMUX_PAD(0x0468, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__VDEC_DEBUG_5 = IOMUX_PAD(0x0468, 0x0120, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA20__MMDC_DEBUG_25 = IOMUX_PAD(0x0468, 0x0120, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 = IOMUX_PAD(0x046C, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 = IOMUX_PAD(0x046C, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__PWM7_OUT = IOMUX_PAD(0x046C, 0x0124, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x046C, 0x0124, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__CSI1_DATA_12 = IOMUX_PAD(0x046C, 0x0124, 4, 0x06CC, 0, 0), - MX6_PAD_LCD1_DATA21__GPIO3_IO_22 = IOMUX_PAD(0x046C, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__SRC_BT_CFG_29 = IOMUX_PAD(0x046C, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__SIM_M_HSIZE_0 = IOMUX_PAD(0x046C, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__VDEC_DEBUG_6 = IOMUX_PAD(0x046C, 0x0124, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA21__MMDC_DEBUG_26 = IOMUX_PAD(0x046C, 0x0124, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 = IOMUX_PAD(0x0470, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 = IOMUX_PAD(0x0470, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__PWM6_OUT = IOMUX_PAD(0x0470, 0x0128, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0470, 0x0128, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__CSI1_DATA_11 = IOMUX_PAD(0x0470, 0x0128, 4, 0x06C8, 0, 0), - MX6_PAD_LCD1_DATA22__GPIO3_IO_23 = IOMUX_PAD(0x0470, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__SRC_BT_CFG_30 = IOMUX_PAD(0x0470, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__SIM_M_HSIZE_1 = IOMUX_PAD(0x0470, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__VDEC_DEBUG_7 = IOMUX_PAD(0x0470, 0x0128, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA22__MMDC_DEBUG_27 = IOMUX_PAD(0x0470, 0x0128, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 = IOMUX_PAD(0x0474, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 = IOMUX_PAD(0x0474, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__PWM5_OUT = IOMUX_PAD(0x0474, 0x012C, 2, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0474, 0x012C, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__CSI1_DATA_10 = IOMUX_PAD(0x0474, 0x012C, 4, 0x06FC, 0, 0), - MX6_PAD_LCD1_DATA23__GPIO3_IO_24 = IOMUX_PAD(0x0474, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__SRC_BT_CFG_31 = IOMUX_PAD(0x0474, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__SIM_M_HSIZE_2 = IOMUX_PAD(0x0474, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__VDEC_DEBUG_8 = IOMUX_PAD(0x0474, 0x012C, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_DATA23__MMDC_DEBUG_28 = IOMUX_PAD(0x0474, 0x012C, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE = IOMUX_PAD(0x0478, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_ENABLE__LCDIF1_RD_E = IOMUX_PAD(0x0478, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0478, 0x0130, 2, 0x063C, 1, 0), - MX6_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0478, 0x0130, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_ENABLE__CSI1_DATA_17 = IOMUX_PAD(0x0478, 0x0130, 4, 0x06E0, 0, 0), - MX6_PAD_LCD1_ENABLE__GPIO3_IO_25 = IOMUX_PAD(0x0478, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_ENABLE__USDHC1_CD_B = IOMUX_PAD(0x0478, 0x0130, 6, 0x0864, 0, 0), - MX6_PAD_LCD1_ENABLE__SIM_M_HADDR_17 = IOMUX_PAD(0x0478, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_ENABLE__VADC_TEST_1 = IOMUX_PAD(0x0478, 0x0130, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_ENABLE__MMDC_DEBUG_1 = IOMUX_PAD(0x0478, 0x0130, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC = IOMUX_PAD(0x047C, 0x0134, 0, 0x07E0, 0, 0), - MX6_PAD_LCD1_HSYNC__LCDIF1_RS = IOMUX_PAD(0x047C, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD = IOMUX_PAD(0x047C, 0x0134, 2, 0x0630, 1, 0), - MX6_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x047C, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_HSYNC__CSI1_DATA_18 = IOMUX_PAD(0x047C, 0x0134, 4, 0x06E4, 0, 0), - MX6_PAD_LCD1_HSYNC__GPIO3_IO_26 = IOMUX_PAD(0x047C, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_HSYNC__USDHC2_WP = IOMUX_PAD(0x047C, 0x0134, 6, 0x0870, 0, 0), - MX6_PAD_LCD1_HSYNC__SIM_M_HADDR_18 = IOMUX_PAD(0x047C, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_HSYNC__VADC_TEST_2 = IOMUX_PAD(0x047C, 0x0134, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_HSYNC__MMDC_DEBUG_2 = IOMUX_PAD(0x047C, 0x0134, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_RESET__LCDIF1_RESET = IOMUX_PAD(0x0480, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_RESET__LCDIF1_CS = IOMUX_PAD(0x0480, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_LCD1_RESET__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0480, 0x0138, 2, 0x062C, 1, 0), - MX6_PAD_LCD1_RESET__KITTEN_EVENTI = IOMUX_PAD(0x0480, 0x0138, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_RESET__M4_EVENTI = IOMUX_PAD(0x0480, 0x0138, 4, 0x0000, 0, 0), - MX6_PAD_LCD1_RESET__GPIO3_IO_27 = IOMUX_PAD(0x0480, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_RESET__CCM_PMIC_RDY = IOMUX_PAD(0x0480, 0x0138, 6, 0x069C, 0, 0), - MX6_PAD_LCD1_RESET__SIM_M_HADDR_20 = IOMUX_PAD(0x0480, 0x0138, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_RESET__VADC_TEST_4 = IOMUX_PAD(0x0480, 0x0138, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_RESET__MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x0138, 9, 0x0000, 0, 0), - - MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC = IOMUX_PAD(0x0484, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_LCD1_VSYNC__LCDIF1_BUSY = IOMUX_PAD(0x0484, 0x013C, 1, 0x07E0, 1, 0), - MX6_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0484, 0x013C, 2, 0x0640, 1, 0), - MX6_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0484, 0x013C, 3, 0x0000, 0, 0), - MX6_PAD_LCD1_VSYNC__CSI1_DATA_19 = IOMUX_PAD(0x0484, 0x013C, 4, 0x06E8, 0, 0), - MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 = IOMUX_PAD(0x0484, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_LCD1_VSYNC__USDHC2_CD_B = IOMUX_PAD(0x0484, 0x013C, 6, 0x086C, 0, 0), - MX6_PAD_LCD1_VSYNC__SIM_M_HADDR_19 = IOMUX_PAD(0x0484, 0x013C, 7, 0x0000, 0, 0), - MX6_PAD_LCD1_VSYNC__VADC_TEST_3 = IOMUX_PAD(0x0484, 0x013C, 8, 0x0000, 0, 0), - MX6_PAD_LCD1_VSYNC__MMDC_DEBUG_3 = IOMUX_PAD(0x0484, 0x013C, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0488, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__I2C3_SDA = IOMUX_PAD(0x0488, 0x0140, IOMUX_CONFIG_SION | 1, 0x07BC, 0, 0), - MX6_PAD_NAND_ALE__QSPI2_A_SS0_B = IOMUX_PAD(0x0488, 0x0140, 2, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__ECSPI2_SS0 = IOMUX_PAD(0x0488, 0x0140, 3, 0x072C, 0, 0), - MX6_PAD_NAND_ALE__ESAI_TX3_RX2 = IOMUX_PAD(0x0488, 0x0140, 4, 0x079C, 0, 0), - MX6_PAD_NAND_ALE__GPIO4_IO_0 = IOMUX_PAD(0x0488, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__WEIM_CS0_B = IOMUX_PAD(0x0488, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__TPSMP_HDATA_0 = IOMUX_PAD(0x0488, 0x0140, 7, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x0488, 0x0140, 8, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0488, 0x0140, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x048C, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__USDHC2_VSELECT = IOMUX_PAD(0x048C, 0x0144, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 = IOMUX_PAD(0x048C, 0x0144, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC = IOMUX_PAD(0x048C, 0x0144, 3, 0x0654, 0, 0), - MX6_PAD_NAND_CE0_B__ESAI_TX_CLK = IOMUX_PAD(0x048C, 0x0144, 4, 0x078C, 0, 0), - MX6_PAD_NAND_CE0_B__GPIO4_IO_1 = IOMUX_PAD(0x048C, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__WEIM_LBA_B = IOMUX_PAD(0x048C, 0x0144, 6, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__TPSMP_HDATA_3 = IOMUX_PAD(0x048C, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x048C, 0x0144, 8, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x048C, 0x0144, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0490, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__USDHC3_RESET_B = IOMUX_PAD(0x0490, 0x0148, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 = IOMUX_PAD(0x0490, 0x0148, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0490, 0x0148, 3, 0x0648, 0, 0), - MX6_PAD_NAND_CE1_B__ESAI_TX0 = IOMUX_PAD(0x0490, 0x0148, 4, 0x0790, 0, 0), - MX6_PAD_NAND_CE1_B__GPIO4_IO_2 = IOMUX_PAD(0x0490, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__WEIM_OE = IOMUX_PAD(0x0490, 0x0148, 6, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__TPSMP_HDATA_4 = IOMUX_PAD(0x0490, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0490, 0x0148, 8, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0490, 0x0148, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0494, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__I2C3_SCL = IOMUX_PAD(0x0494, 0x014C, IOMUX_CONFIG_SION | 1, 0x07B8, 0, 0), - MX6_PAD_NAND_CLE__QSPI2_A_SCLK = IOMUX_PAD(0x0494, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__ECSPI2_SCLK = IOMUX_PAD(0x0494, 0x014C, 3, 0x0720, 0, 0), - MX6_PAD_NAND_CLE__ESAI_TX2_RX3 = IOMUX_PAD(0x0494, 0x014C, 4, 0x0798, 0, 0), - MX6_PAD_NAND_CLE__GPIO4_IO_3 = IOMUX_PAD(0x0494, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__WEIM_BCLK = IOMUX_PAD(0x0494, 0x014C, 6, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__TPSMP_CLK = IOMUX_PAD(0x0494, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x0494, 0x014C, 8, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0494, 0x014C, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0498, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__USDHC1_DATA4 = IOMUX_PAD(0x0498, 0x0150, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 = IOMUX_PAD(0x0498, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__ECSPI5_MISO = IOMUX_PAD(0x0498, 0x0150, 3, 0x0754, 0, 0), - MX6_PAD_NAND_DATA00__ESAI_RX_CLK = IOMUX_PAD(0x0498, 0x0150, 4, 0x0788, 0, 0), - MX6_PAD_NAND_DATA00__GPIO4_IO_4 = IOMUX_PAD(0x0498, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__WEIM_AD_0 = IOMUX_PAD(0x0498, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__TPSMP_HDATA_7 = IOMUX_PAD(0x0498, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x0498, 0x0150, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x0498, 0x0150, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x049C, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__USDHC1_DATA5 = IOMUX_PAD(0x049C, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 = IOMUX_PAD(0x049C, 0x0154, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__ECSPI5_MOSI = IOMUX_PAD(0x049C, 0x0154, 3, 0x0758, 0, 0), - MX6_PAD_NAND_DATA01__ESAI_RX_FS = IOMUX_PAD(0x049C, 0x0154, 4, 0x0778, 0, 0), - MX6_PAD_NAND_DATA01__GPIO4_IO_5 = IOMUX_PAD(0x049C, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__WEIM_AD_1 = IOMUX_PAD(0x049C, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__TPSMP_HDATA_8 = IOMUX_PAD(0x049C, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x049C, 0x0154, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x049C, 0x0154, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x04A0, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__USDHC1_DATA6 = IOMUX_PAD(0x04A0, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__QSPI2_B_SCLK = IOMUX_PAD(0x04A0, 0x0158, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__ECSPI5_SCLK = IOMUX_PAD(0x04A0, 0x0158, 3, 0x0750, 0, 0), - MX6_PAD_NAND_DATA02__ESAI_TX_HF_CLK = IOMUX_PAD(0x04A0, 0x0158, 4, 0x0784, 0, 0), - MX6_PAD_NAND_DATA02__GPIO4_IO_6 = IOMUX_PAD(0x04A0, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__WEIM_AD_2 = IOMUX_PAD(0x04A0, 0x0158, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__TPSMP_HDATA_9 = IOMUX_PAD(0x04A0, 0x0158, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x04A0, 0x0158, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x04A0, 0x0158, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x04A4, 0x015C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__USDHC1_DATA7 = IOMUX_PAD(0x04A4, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B = IOMUX_PAD(0x04A4, 0x015C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__ECSPI5_SS0 = IOMUX_PAD(0x04A4, 0x015C, 3, 0x075C, 0, 0), - MX6_PAD_NAND_DATA03__ESAI_RX_HF_CLK = IOMUX_PAD(0x04A4, 0x015C, 4, 0x0780, 0, 0), - MX6_PAD_NAND_DATA03__GPIO4_IO_7 = IOMUX_PAD(0x04A4, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__WEIM_AD_3 = IOMUX_PAD(0x04A4, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__TPSMP_HDATA_10 = IOMUX_PAD(0x04A4, 0x015C, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x04A4, 0x015C, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x04A4, 0x015C, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x04A8, 0x0160, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x04A8, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__QSPI2_B_SS1_B = IOMUX_PAD(0x04A8, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__UART3_RTS_B = IOMUX_PAD(0x04A8, 0x0160, 3, 0x083C, 0, 0), - MX6_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04A8, 0x0160, 4, 0x0650, 0, 0), - MX6_PAD_NAND_DATA04__GPIO4_IO_8 = IOMUX_PAD(0x04A8, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__WEIM_AD_4 = IOMUX_PAD(0x04A8, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__TPSMP_HDATA_11 = IOMUX_PAD(0x04A8, 0x0160, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x04A8, 0x0160, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x04A8, 0x0160, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x04AC, 0x0164, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x04AC, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__QSPI2_B_DQS = IOMUX_PAD(0x04AC, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__UART3_CTS_B = IOMUX_PAD(0x04AC, 0x0164, 3, 0x083C, 1, 0), - MX6_PAD_NAND_DATA05__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04AC, 0x0164, 4, 0x064C, 0, 0), - MX6_PAD_NAND_DATA05__GPIO4_IO_9 = IOMUX_PAD(0x04AC, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__WEIM_AD_5 = IOMUX_PAD(0x04AC, 0x0164, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__TPSMP_HDATA_12 = IOMUX_PAD(0x04AC, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x04AC, 0x0164, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x04AC, 0x0164, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x04B0, 0x0168, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x04B0, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__QSPI2_A_SS1_B = IOMUX_PAD(0x04B0, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__UART3_RX = IOMUX_PAD(0x04B0, 0x0168, 3, 0x0840, 0, 0), - MX6_PAD_NAND_DATA06__PWM3_OUT = IOMUX_PAD(0x04B0, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__GPIO4_IO_10 = IOMUX_PAD(0x04B0, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__WEIM_AD_6 = IOMUX_PAD(0x04B0, 0x0168, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__TPSMP_HDATA_13 = IOMUX_PAD(0x04B0, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x04B0, 0x0168, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x04B0, 0x0168, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x04B4, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x04B4, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__QSPI2_A_DQS = IOMUX_PAD(0x04B4, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__UART3_TX = IOMUX_PAD(0x04B4, 0x016C, 3, 0x0840, 1, 0), - MX6_PAD_NAND_DATA07__PWM4_OUT = IOMUX_PAD(0x04B4, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__GPIO4_IO_11 = IOMUX_PAD(0x04B4, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__WEIM_AD_7 = IOMUX_PAD(0x04B4, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__TPSMP_HDATA_14 = IOMUX_PAD(0x04B4, 0x016C, 7, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x04B4, 0x016C, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x04B4, 0x016C, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x04B8, 0x0170, 0, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__USDHC2_RESET_B = IOMUX_PAD(0x04B8, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 = IOMUX_PAD(0x04B8, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04B8, 0x0170, 3, 0x0658, 0, 0), - MX6_PAD_NAND_RE_B__ESAI_TX_FS = IOMUX_PAD(0x04B8, 0x0170, 4, 0x077C, 0, 0), - MX6_PAD_NAND_RE_B__GPIO4_IO_12 = IOMUX_PAD(0x04B8, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__WEIM_RW = IOMUX_PAD(0x04B8, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__TPSMP_HDATA_5 = IOMUX_PAD(0x04B8, 0x0170, 7, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x04B8, 0x0170, 8, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x04B8, 0x0170, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x04BC, 0x0174, 0, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__USDHC1_VSELECT = IOMUX_PAD(0x04BC, 0x0174, 1, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 = IOMUX_PAD(0x04BC, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x0174, 3, 0x0724, 0, 0), - MX6_PAD_NAND_READY_B__ESAI_TX1 = IOMUX_PAD(0x04BC, 0x0174, 4, 0x0794, 0, 0), - MX6_PAD_NAND_READY_B__GPIO4_IO_13 = IOMUX_PAD(0x04BC, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__WEIM_EB_B_1 = IOMUX_PAD(0x04BC, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__TPSMP_HDATA_2 = IOMUX_PAD(0x04BC, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x04BC, 0x0174, 8, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x04BC, 0x0174, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x04C0, 0x0178, 0, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__USDHC4_VSELECT = IOMUX_PAD(0x04C0, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 = IOMUX_PAD(0x04C0, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04C0, 0x0178, 3, 0x0644, 0, 0), - MX6_PAD_NAND_WE_B__ESAI_TX5_RX0 = IOMUX_PAD(0x04C0, 0x0178, 4, 0x07A4, 0, 0), - MX6_PAD_NAND_WE_B__GPIO4_IO_14 = IOMUX_PAD(0x04C0, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__WEIM_WAIT = IOMUX_PAD(0x04C0, 0x0178, 6, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__TPSMP_HDATA_6 = IOMUX_PAD(0x04C0, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x04C0, 0x0178, 8, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x04C0, 0x0178, 9, 0x0000, 0, 0), - - MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x04C4, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x04C4, 0x017C, 1, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 = IOMUX_PAD(0x04C4, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x017C, 3, 0x0728, 0, 0), - MX6_PAD_NAND_WP_B__ESAI_TX4_RX1 = IOMUX_PAD(0x04C4, 0x017C, 4, 0x07A0, 0, 0), - MX6_PAD_NAND_WP_B__GPIO4_IO_15 = IOMUX_PAD(0x04C4, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__WEIM_EB_B_0 = IOMUX_PAD(0x04C4, 0x017C, 6, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__TPSMP_HDATA_1 = IOMUX_PAD(0x04C4, 0x017C, 7, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x04C4, 0x017C, 8, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x04C4, 0x017C, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 = IOMUX_PAD(0x04C8, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA0__USB_OTG2_OC = IOMUX_PAD(0x04C8, 0x0180, 1, 0x085C, 2, 0), - MX6_PAD_QSPI1A_DATA0__ECSPI1_MOSI = IOMUX_PAD(0x04C8, 0x0180, 2, 0x0718, 1, 0), - MX6_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 = IOMUX_PAD(0x04C8, 0x0180, 3, 0x07A0, 2, 0), - MX6_PAD_QSPI1A_DATA0__CSI1_DATA_14 = IOMUX_PAD(0x04C8, 0x0180, 4, 0x06D4, 1, 0), - MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 = IOMUX_PAD(0x04C8, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6 = IOMUX_PAD(0x04C8, 0x0180, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 = IOMUX_PAD(0x04C8, 0x0180, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x04C8, 0x0180, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 = IOMUX_PAD(0x04CC, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID = IOMUX_PAD(0x04CC, 0x0184, 1, 0x0624, 2, 0), - MX6_PAD_QSPI1A_DATA1__ECSPI1_MISO = IOMUX_PAD(0x04CC, 0x0184, 2, 0x0714, 1, 0), - MX6_PAD_QSPI1A_DATA1__ESAI_TX1 = IOMUX_PAD(0x04CC, 0x0184, 3, 0x0794, 2, 0), - MX6_PAD_QSPI1A_DATA1__CSI1_DATA_13 = IOMUX_PAD(0x04CC, 0x0184, 4, 0x06D0, 1, 0), - MX6_PAD_QSPI1A_DATA1__GPIO4_IO_17 = IOMUX_PAD(0x04CC, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5 = IOMUX_PAD(0x04CC, 0x0184, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 = IOMUX_PAD(0x04CC, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x04CC, 0x0184, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 = IOMUX_PAD(0x04D0, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA2__USB_OTG1_PWR = IOMUX_PAD(0x04D0, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA2__ECSPI5_SS1 = IOMUX_PAD(0x04D0, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA2__ESAI_TX_CLK = IOMUX_PAD(0x04D0, 0x0188, 3, 0x078C, 2, 0), - MX6_PAD_QSPI1A_DATA2__CSI1_DATA_12 = IOMUX_PAD(0x04D0, 0x0188, 4, 0x06CC, 1, 0), - MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 = IOMUX_PAD(0x04D0, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4 = IOMUX_PAD(0x04D0, 0x0188, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 = IOMUX_PAD(0x04D0, 0x0188, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x04D0, 0x0188, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 = IOMUX_PAD(0x04D4, 0x018C, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04D4, 0x018C, 1, 0x0860, 2, 0), - MX6_PAD_QSPI1A_DATA3__ECSPI5_SS2 = IOMUX_PAD(0x04D4, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA3__ESAI_TX0 = IOMUX_PAD(0x04D4, 0x018C, 3, 0x0790, 2, 0), - MX6_PAD_QSPI1A_DATA3__CSI1_DATA_11 = IOMUX_PAD(0x04D4, 0x018C, 4, 0x06C8, 1, 0), - MX6_PAD_QSPI1A_DATA3__GPIO4_IO_19 = IOMUX_PAD(0x04D4, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3 = IOMUX_PAD(0x04D4, 0x018C, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 = IOMUX_PAD(0x04D4, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x04D4, 0x018C, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_DQS__QSPI1_A_DQS = IOMUX_PAD(0x04D8, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DQS__CAN2_TX = IOMUX_PAD(0x04D8, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DQS__CANFD_TX2 = IOMUX_PAD(0x04D8, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DQS__ECSPI5_MOSI = IOMUX_PAD(0x04D8, 0x0190, 3, 0x0758, 1, 0), - MX6_PAD_QSPI1A_DQS__CSI1_DATA_15 = IOMUX_PAD(0x04D8, 0x0190, 4, 0x06D8, 1, 0), - MX6_PAD_QSPI1A_DQS__GPIO4_IO_20 = IOMUX_PAD(0x04D8, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DQS__WEIM_DATA_7 = IOMUX_PAD(0x04D8, 0x0190, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DQS__SIM_M_HADDR_13 = IOMUX_PAD(0x04D8, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x04D8, 0x0190, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK = IOMUX_PAD(0x04DC, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID = IOMUX_PAD(0x04DC, 0x0194, 1, 0x0628, 2, 0), - MX6_PAD_QSPI1A_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x04DC, 0x0194, 2, 0x0710, 1, 0), - MX6_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 = IOMUX_PAD(0x04DC, 0x0194, 3, 0x0798, 2, 0), - MX6_PAD_QSPI1A_SCLK__CSI1_DATA_1 = IOMUX_PAD(0x04DC, 0x0194, 4, 0x06A4, 1, 0), - MX6_PAD_QSPI1A_SCLK__GPIO4_IO_21 = IOMUX_PAD(0x04DC, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 = IOMUX_PAD(0x04DC, 0x0194, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 = IOMUX_PAD(0x04DC, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x04DC, 0x0194, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B = IOMUX_PAD(0x04E0, 0x0198, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS0_B__USB_OTG2_PWR = IOMUX_PAD(0x04E0, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS0_B__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x0198, 2, 0x071C, 1, 0), - MX6_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 = IOMUX_PAD(0x04E0, 0x0198, 3, 0x079C, 2, 0), - MX6_PAD_QSPI1A_SS0_B__CSI1_DATA_0 = IOMUX_PAD(0x04E0, 0x0198, 4, 0x06A0, 1, 0), - MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 = IOMUX_PAD(0x04E0, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 = IOMUX_PAD(0x04E0, 0x0198, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 = IOMUX_PAD(0x04E0, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x04E0, 0x0198, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B = IOMUX_PAD(0x04E4, 0x019C, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS1_B__CAN1_RX = IOMUX_PAD(0x04E4, 0x019C, 1, 0x068C, 2, 0), - MX6_PAD_QSPI1A_SS1_B__CANFD_RX1 = IOMUX_PAD(0x04E4, 0x019C, 2, 0x0694, 2, 0), - MX6_PAD_QSPI1A_SS1_B__ECSPI5_MISO = IOMUX_PAD(0x04E4, 0x019C, 3, 0x0754, 1, 0), - MX6_PAD_QSPI1A_SS1_B__CSI1_DATA_10 = IOMUX_PAD(0x04E4, 0x019C, 4, 0x06FC, 1, 0), - MX6_PAD_QSPI1A_SS1_B__GPIO4_IO_23 = IOMUX_PAD(0x04E4, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2 = IOMUX_PAD(0x04E4, 0x019C, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 = IOMUX_PAD(0x04E4, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x04E4, 0x019C, 9, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 = IOMUX_PAD(0x04E8, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA0__UART3_CTS_B = IOMUX_PAD(0x04E8, 0x01A0, 1, 0x083C, 4, 0), - MX6_PAD_QSPI1B_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04E8, 0x01A0, 2, 0x0738, 1, 0), - MX6_PAD_QSPI1B_DATA0__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01A0, 3, 0x0778, 2, 0), - MX6_PAD_QSPI1B_DATA0__CSI1_DATA_22 = IOMUX_PAD(0x04E8, 0x01A0, 4, 0x06F4, 1, 0), - MX6_PAD_QSPI1B_DATA0__GPIO4_IO_24 = IOMUX_PAD(0x04E8, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 = IOMUX_PAD(0x04E8, 0x01A0, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 = IOMUX_PAD(0x04E8, 0x01A0, 7, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 = IOMUX_PAD(0x04EC, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA1__UART3_RTS_B = IOMUX_PAD(0x04EC, 0x01A4, 1, 0x083C, 5, 0), - MX6_PAD_QSPI1B_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04EC, 0x01A4, 2, 0x0734, 1, 0), - MX6_PAD_QSPI1B_DATA1__ESAI_RX_CLK = IOMUX_PAD(0x04EC, 0x01A4, 3, 0x0788, 2, 0), - MX6_PAD_QSPI1B_DATA1__CSI1_DATA_21 = IOMUX_PAD(0x04EC, 0x01A4, 4, 0x06F0, 1, 0), - MX6_PAD_QSPI1B_DATA1__GPIO4_IO_25 = IOMUX_PAD(0x04EC, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 = IOMUX_PAD(0x04EC, 0x01A4, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 = IOMUX_PAD(0x04EC, 0x01A4, 7, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 = IOMUX_PAD(0x04F0, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA2__I2C2_SDA = IOMUX_PAD(0x04F0, 0x01A8, IOMUX_CONFIG_SION | 1, 0x07B4, 2, 0), - MX6_PAD_QSPI1B_DATA2__ECSPI5_RDY = IOMUX_PAD(0x04F0, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 = IOMUX_PAD(0x04F0, 0x01A8, 3, 0x07A4, 2, 0), - MX6_PAD_QSPI1B_DATA2__CSI1_DATA_20 = IOMUX_PAD(0x04F0, 0x01A8, 4, 0x06EC, 1, 0), - MX6_PAD_QSPI1B_DATA2__GPIO4_IO_26 = IOMUX_PAD(0x04F0, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 = IOMUX_PAD(0x04F0, 0x01A8, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 = IOMUX_PAD(0x04F0, 0x01A8, 7, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 = IOMUX_PAD(0x04F4, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA3__I2C2_SCL = IOMUX_PAD(0x04F4, 0x01AC, IOMUX_CONFIG_SION | 1, 0x07B0, 2, 0), - MX6_PAD_QSPI1B_DATA3__ECSPI5_SS3 = IOMUX_PAD(0x04F4, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA3__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01AC, 3, 0x077C, 2, 0), - MX6_PAD_QSPI1B_DATA3__CSI1_DATA_19 = IOMUX_PAD(0x04F4, 0x01AC, 4, 0x06E8, 1, 0), - MX6_PAD_QSPI1B_DATA3__GPIO4_IO_27 = IOMUX_PAD(0x04F4, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 = IOMUX_PAD(0x04F4, 0x01AC, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 = IOMUX_PAD(0x04F4, 0x01AC, 7, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_DQS__QSPI1_B_DQS = IOMUX_PAD(0x04F8, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DQS__CAN1_TX = IOMUX_PAD(0x04F8, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DQS__CANFD_TX1 = IOMUX_PAD(0x04F8, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DQS__ECSPI5_SS0 = IOMUX_PAD(0x04F8, 0x01B0, 3, 0x075C, 1, 0), - MX6_PAD_QSPI1B_DQS__CSI1_DATA_23 = IOMUX_PAD(0x04F8, 0x01B0, 4, 0x06F8, 1, 0), - MX6_PAD_QSPI1B_DQS__GPIO4_IO_28 = IOMUX_PAD(0x04F8, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DQS__WEIM_DATA_15 = IOMUX_PAD(0x04F8, 0x01B0, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_DQS__SIM_M_HADDR_15 = IOMUX_PAD(0x04F8, 0x01B0, 7, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK = IOMUX_PAD(0x04FC, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SCLK__UART3_RX = IOMUX_PAD(0x04FC, 0x01B4, 1, 0x0840, 4, 0), - MX6_PAD_QSPI1B_SCLK__ECSPI3_SCLK = IOMUX_PAD(0x04FC, 0x01B4, 2, 0x0730, 1, 0), - MX6_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK = IOMUX_PAD(0x04FC, 0x01B4, 3, 0x0780, 2, 0), - MX6_PAD_QSPI1B_SCLK__CSI1_DATA_16 = IOMUX_PAD(0x04FC, 0x01B4, 4, 0x06DC, 1, 0), - MX6_PAD_QSPI1B_SCLK__GPIO4_IO_29 = IOMUX_PAD(0x04FC, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8 = IOMUX_PAD(0x04FC, 0x01B4, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 = IOMUX_PAD(0x04FC, 0x01B4, 7, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B = IOMUX_PAD(0x0500, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SS0_B__UART3_TX = IOMUX_PAD(0x0500, 0x01B8, 1, 0x0840, 5, 0), - MX6_PAD_QSPI1B_SS0_B__ECSPI3_SS0 = IOMUX_PAD(0x0500, 0x01B8, 2, 0x073C, 1, 0), - MX6_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK = IOMUX_PAD(0x0500, 0x01B8, 3, 0x0784, 3, 0), - MX6_PAD_QSPI1B_SS0_B__CSI1_DATA_17 = IOMUX_PAD(0x0500, 0x01B8, 4, 0x06E0, 1, 0), - MX6_PAD_QSPI1B_SS0_B__GPIO4_IO_30 = IOMUX_PAD(0x0500, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9 = IOMUX_PAD(0x0500, 0x01B8, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 = IOMUX_PAD(0x0500, 0x01B8, 7, 0x0000, 0, 0), - - MX6_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B = IOMUX_PAD(0x0504, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SS1_B__CAN2_RX = IOMUX_PAD(0x0504, 0x01BC, 1, 0x0690, 2, 0), - MX6_PAD_QSPI1B_SS1_B__CANFD_RX2 = IOMUX_PAD(0x0504, 0x01BC, 2, 0x0698, 2, 0), - MX6_PAD_QSPI1B_SS1_B__ECSPI5_SCLK = IOMUX_PAD(0x0504, 0x01BC, 3, 0x0750, 1, 0), - MX6_PAD_QSPI1B_SS1_B__CSI1_DATA_18 = IOMUX_PAD(0x0504, 0x01BC, 4, 0x06E4, 1, 0), - MX6_PAD_QSPI1B_SS1_B__GPIO4_IO_31 = IOMUX_PAD(0x0504, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 = IOMUX_PAD(0x0504, 0x01BC, 6, 0x0000, 0, 0), - MX6_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 = IOMUX_PAD(0x0504, 0x01BC, 7, 0x0000, 0, 0), - - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 = IOMUX_PAD(0x0508, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD0__GPIO5_IO_0 = IOMUX_PAD(0x0508, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD0__CSI2_DATA_10 = IOMUX_PAD(0x0508, 0x01C0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD0__ANATOP_TESTI_0 = IOMUX_PAD(0x0508, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER = IOMUX_PAD(0x0508, 0x01C0, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 = IOMUX_PAD(0x0508, 0x01C0, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 = IOMUX_PAD(0x050C, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD1__GPIO5_IO_1 = IOMUX_PAD(0x050C, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD1__CSI2_DATA_11 = IOMUX_PAD(0x050C, 0x01C4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD1__ANATOP_TESTI_1 = IOMUX_PAD(0x050C, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER = IOMUX_PAD(0x050C, 0x01C4, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 = IOMUX_PAD(0x050C, 0x01C4, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 = IOMUX_PAD(0x0510, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD2__GPIO5_IO_2 = IOMUX_PAD(0x0510, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD2__CSI2_DATA_12 = IOMUX_PAD(0x0510, 0x01C8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD2__ANATOP_TESTI_2 = IOMUX_PAD(0x0510, 0x01C8, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER = IOMUX_PAD(0x0510, 0x01C8, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 = IOMUX_PAD(0x0510, 0x01C8, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 = IOMUX_PAD(0x0514, 0x01CC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD3__GPIO5_IO_3 = IOMUX_PAD(0x0514, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD3__CSI2_DATA_13 = IOMUX_PAD(0x0514, 0x01CC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD3__ANATOP_TESTI_3 = IOMUX_PAD(0x0514, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER = IOMUX_PAD(0x0514, 0x01CC, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 = IOMUX_PAD(0x0514, 0x01CC, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN = IOMUX_PAD(0x0518, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_RX_CTL__GPIO5_IO_4 = IOMUX_PAD(0x0518, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_RX_CTL__CSI2_DATA_14 = IOMUX_PAD(0x0518, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 = IOMUX_PAD(0x0518, 0x01D0, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER = IOMUX_PAD(0x0518, 0x01D0, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 = IOMUX_PAD(0x0518, 0x01D0, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK = IOMUX_PAD(0x051C, 0x01D4, 0, 0x0768, 1, 0), - MX6_PAD_RGMII1_RXC__ENET1_RX_ER = IOMUX_PAD(0x051C, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII1_RXC__GPIO5_IO_5 = IOMUX_PAD(0x051C, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_RXC__CSI2_DATA_15 = IOMUX_PAD(0x051C, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_RXC__ANATOP_TESTO_1 = IOMUX_PAD(0x051C, 0x01D4, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER = IOMUX_PAD(0x051C, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 = IOMUX_PAD(0x051C, 0x01D4, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 = IOMUX_PAD(0x0520, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD0__SAI2_RX_SYNC = IOMUX_PAD(0x0520, 0x01D8, 2, 0x0810, 1, 0), - MX6_PAD_RGMII1_TD0__GPIO5_IO_6 = IOMUX_PAD(0x0520, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD0__CSI2_DATA_16 = IOMUX_PAD(0x0520, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD0__ANATOP_TESTO_2 = IOMUX_PAD(0x0520, 0x01D8, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER = IOMUX_PAD(0x0520, 0x01D8, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 = IOMUX_PAD(0x0520, 0x01D8, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 = IOMUX_PAD(0x0524, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD1__SAI2_RX_BCLK = IOMUX_PAD(0x0524, 0x01DC, 2, 0x0808, 1, 0), - MX6_PAD_RGMII1_TD1__GPIO5_IO_7 = IOMUX_PAD(0x0524, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD1__CSI2_DATA_17 = IOMUX_PAD(0x0524, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD1__ANATOP_TESTO_3 = IOMUX_PAD(0x0524, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER = IOMUX_PAD(0x0524, 0x01DC, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 = IOMUX_PAD(0x0524, 0x01DC, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 = IOMUX_PAD(0x0528, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD2__SAI2_TX_SYNC = IOMUX_PAD(0x0528, 0x01E0, 2, 0x0818, 1, 0), - MX6_PAD_RGMII1_TD2__GPIO5_IO_8 = IOMUX_PAD(0x0528, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD2__CSI2_DATA_18 = IOMUX_PAD(0x0528, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD2__ANATOP_TESTO_4 = IOMUX_PAD(0x0528, 0x01E0, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER = IOMUX_PAD(0x0528, 0x01E0, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 = IOMUX_PAD(0x0528, 0x01E0, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 = IOMUX_PAD(0x052C, 0x01E4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD3__SAI2_TX_BCLK = IOMUX_PAD(0x052C, 0x01E4, 2, 0x0814, 1, 0), - MX6_PAD_RGMII1_TD3__GPIO5_IO_9 = IOMUX_PAD(0x052C, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD3__CSI2_DATA_19 = IOMUX_PAD(0x052C, 0x01E4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD3__ANATOP_TESTO_5 = IOMUX_PAD(0x052C, 0x01E4, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER = IOMUX_PAD(0x052C, 0x01E4, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 = IOMUX_PAD(0x052C, 0x01E4, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN = IOMUX_PAD(0x0530, 0x01E8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 = IOMUX_PAD(0x0530, 0x01E8, 2, 0x080C, 1, 0), - MX6_PAD_RGMII1_TX_CTL__GPIO5_IO_10 = IOMUX_PAD(0x0530, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_TX_CTL__CSI2_DATA_0 = IOMUX_PAD(0x0530, 0x01E8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 = IOMUX_PAD(0x0530, 0x01E8, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER = IOMUX_PAD(0x0530, 0x01E8, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 = IOMUX_PAD(0x0530, 0x01E8, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x0534, 0x01EC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII1_TXC__ENET1_TX_ER = IOMUX_PAD(0x0534, 0x01EC, 1, 0x0000, 0, 0), - MX6_PAD_RGMII1_TXC__SAI2_TX_DATA_0 = IOMUX_PAD(0x0534, 0x01EC, 2, 0x0000, 0, 0), - MX6_PAD_RGMII1_TXC__GPIO5_IO_11 = IOMUX_PAD(0x0534, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII1_TXC__CSI2_DATA_1 = IOMUX_PAD(0x0534, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII1_TXC__ANATOP_TESTO_7 = IOMUX_PAD(0x0534, 0x01EC, 7, 0x0000, 0, 0), - MX6_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER = IOMUX_PAD(0x0534, 0x01EC, 8, 0x0000, 0, 0), - MX6_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 = IOMUX_PAD(0x0534, 0x01EC, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 = IOMUX_PAD(0x0538, 0x01F0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD0__PWM4_OUT = IOMUX_PAD(0x0538, 0x01F0, 2, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD0__GPIO5_IO_12 = IOMUX_PAD(0x0538, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD0__CSI2_DATA_2 = IOMUX_PAD(0x0538, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD0__ANATOP_TESTO_8 = IOMUX_PAD(0x0538, 0x01F0, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD0__VDEC_DEBUG_18 = IOMUX_PAD(0x0538, 0x01F0, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 = IOMUX_PAD(0x0538, 0x01F0, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 = IOMUX_PAD(0x053C, 0x01F4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD1__PWM3_OUT = IOMUX_PAD(0x053C, 0x01F4, 2, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD1__GPIO5_IO_13 = IOMUX_PAD(0x053C, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD1__CSI2_DATA_3 = IOMUX_PAD(0x053C, 0x01F4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD1__ANATOP_TESTO_9 = IOMUX_PAD(0x053C, 0x01F4, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD1__VDEC_DEBUG_19 = IOMUX_PAD(0x053C, 0x01F4, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 = IOMUX_PAD(0x053C, 0x01F4, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 = IOMUX_PAD(0x0540, 0x01F8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD2__PWM2_OUT = IOMUX_PAD(0x0540, 0x01F8, 2, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD2__GPIO5_IO_14 = IOMUX_PAD(0x0540, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD2__CSI2_DATA_4 = IOMUX_PAD(0x0540, 0x01F8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD2__ANATOP_TESTO_10 = IOMUX_PAD(0x0540, 0x01F8, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD2__VDEC_DEBUG_20 = IOMUX_PAD(0x0540, 0x01F8, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 = IOMUX_PAD(0x0540, 0x01F8, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 = IOMUX_PAD(0x0544, 0x01FC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD3__PWM1_OUT = IOMUX_PAD(0x0544, 0x01FC, 2, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD3__GPIO5_IO_15 = IOMUX_PAD(0x0544, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD3__CSI2_DATA_5 = IOMUX_PAD(0x0544, 0x01FC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD3__ANATOP_TESTO_11 = IOMUX_PAD(0x0544, 0x01FC, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD3__VDEC_DEBUG_21 = IOMUX_PAD(0x0544, 0x01FC, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 = IOMUX_PAD(0x0544, 0x01FC, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN = IOMUX_PAD(0x0548, 0x0200, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_RX_CTL__GPIO5_IO_16 = IOMUX_PAD(0x0548, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_RX_CTL__CSI2_DATA_6 = IOMUX_PAD(0x0548, 0x0200, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 = IOMUX_PAD(0x0548, 0x0200, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 = IOMUX_PAD(0x0548, 0x0200, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 = IOMUX_PAD(0x0548, 0x0200, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK = IOMUX_PAD(0x054C, 0x0204, 0, 0x0774, 1, 0), - MX6_PAD_RGMII2_RXC__ENET2_RX_ER = IOMUX_PAD(0x054C, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_RGMII2_RXC__GPIO5_IO_17 = IOMUX_PAD(0x054C, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_RXC__CSI2_DATA_7 = IOMUX_PAD(0x054C, 0x0204, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_RXC__ANATOP_TESTO_13 = IOMUX_PAD(0x054C, 0x0204, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_RXC__VDEC_DEBUG_23 = IOMUX_PAD(0x054C, 0x0204, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 = IOMUX_PAD(0x054C, 0x0204, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 = IOMUX_PAD(0x0550, 0x0208, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD0__SAI1_RX_SYNC = IOMUX_PAD(0x0550, 0x0208, 2, 0x07FC, 1, 0), - MX6_PAD_RGMII2_TD0__PWM8_OUT = IOMUX_PAD(0x0550, 0x0208, 3, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD0__GPIO5_IO_18 = IOMUX_PAD(0x0550, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD0__CSI2_DATA_8 = IOMUX_PAD(0x0550, 0x0208, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD0__ANATOP_TESTO_14 = IOMUX_PAD(0x0550, 0x0208, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD0__VDEC_DEBUG_24 = IOMUX_PAD(0x0550, 0x0208, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 = IOMUX_PAD(0x0550, 0x0208, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 = IOMUX_PAD(0x0554, 0x020C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD1__SAI1_RX_BCLK = IOMUX_PAD(0x0554, 0x020C, 2, 0x07F4, 1, 0), - MX6_PAD_RGMII2_TD1__PWM7_OUT = IOMUX_PAD(0x0554, 0x020C, 3, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD1__GPIO5_IO_19 = IOMUX_PAD(0x0554, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD1__CSI2_DATA_9 = IOMUX_PAD(0x0554, 0x020C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD1__ANATOP_TESTO_15 = IOMUX_PAD(0x0554, 0x020C, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD1__VDEC_DEBUG_25 = IOMUX_PAD(0x0554, 0x020C, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 = IOMUX_PAD(0x0554, 0x020C, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 = IOMUX_PAD(0x0558, 0x0210, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD2__SAI1_TX_SYNC = IOMUX_PAD(0x0558, 0x0210, 2, 0x0804, 1, 0), - MX6_PAD_RGMII2_TD2__PWM6_OUT = IOMUX_PAD(0x0558, 0x0210, 3, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD2__GPIO5_IO_20 = IOMUX_PAD(0x0558, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD2__CSI2_VSYNC = IOMUX_PAD(0x0558, 0x0210, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD2__SJC_FAIL = IOMUX_PAD(0x0558, 0x0210, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD2__VDEC_DEBUG_26 = IOMUX_PAD(0x0558, 0x0210, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 = IOMUX_PAD(0x0558, 0x0210, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 = IOMUX_PAD(0x055C, 0x0214, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD3__SAI1_TX_BCLK = IOMUX_PAD(0x055C, 0x0214, 2, 0x0800, 1, 0), - MX6_PAD_RGMII2_TD3__PWM5_OUT = IOMUX_PAD(0x055C, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD3__GPIO5_IO_21 = IOMUX_PAD(0x055C, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD3__CSI2_HSYNC = IOMUX_PAD(0x055C, 0x0214, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD3__SJC_JTAG_ACT = IOMUX_PAD(0x055C, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD3__VDEC_DEBUG_27 = IOMUX_PAD(0x055C, 0x0214, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 = IOMUX_PAD(0x055C, 0x0214, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN = IOMUX_PAD(0x0560, 0x0218, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 = IOMUX_PAD(0x0560, 0x0218, 2, 0x07F8, 1, 0), - MX6_PAD_RGMII2_TX_CTL__GPIO5_IO_22 = IOMUX_PAD(0x0560, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_TX_CTL__CSI2_FIELD = IOMUX_PAD(0x0560, 0x0218, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_TX_CTL__SJC_DE_B = IOMUX_PAD(0x0560, 0x0218, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 = IOMUX_PAD(0x0560, 0x0218, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 = IOMUX_PAD(0x0560, 0x0218, 9, 0x0000, 0, 0), - - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC = IOMUX_PAD(0x0564, 0x021C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII2_TXC__ENET2_TX_ER = IOMUX_PAD(0x0564, 0x021C, 1, 0x0000, 0, 0), - MX6_PAD_RGMII2_TXC__SAI1_TX_DATA_0 = IOMUX_PAD(0x0564, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_RGMII2_TXC__GPIO5_IO_23 = IOMUX_PAD(0x0564, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII2_TXC__CSI2_PIXCLK = IOMUX_PAD(0x0564, 0x021C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII2_TXC__SJC_DONE = IOMUX_PAD(0x0564, 0x021C, 7, 0x0000, 0, 0), - MX6_PAD_RGMII2_TXC__VDEC_DEBUG_29 = IOMUX_PAD(0x0564, 0x021C, 8, 0x0000, 0, 0), - MX6_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 = IOMUX_PAD(0x0564, 0x021C, 9, 0x0000, 0, 0), - - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0568, 0x0220, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0568, 0x0220, 1, 0x0668, 1, 0), - MX6_PAD_SD1_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x0568, 0x0220, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPT_CLK = IOMUX_PAD(0x0568, 0x0220, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0568, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO6_IO_0 = IOMUX_PAD(0x0568, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x0568, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__CCM_OUT1 = IOMUX_PAD(0x0568, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__VADC_ADC_PROC_CLK = IOMUX_PAD(0x0568, 0x0220, 8, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__MMDC_DEBUG_45 = IOMUX_PAD(0x0568, 0x0220, 9, 0x0000, 0, 0), - - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x056C, 0x0224, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__AUDMUX_AUD5_RXC = IOMUX_PAD(0x056C, 0x0224, 1, 0x0664, 1, 0), - MX6_PAD_SD1_CMD__WDOG1_WDOG_B = IOMUX_PAD(0x056C, 0x0224, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x056C, 0x0224, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x056C, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO6_IO_1 = IOMUX_PAD(0x056C, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x056C, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__CCM_CLKO1 = IOMUX_PAD(0x056C, 0x0224, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__VADC_EXT_SYSCLK = IOMUX_PAD(0x056C, 0x0224, 8, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__MMDC_DEBUG_46 = IOMUX_PAD(0x056C, 0x0224, 9, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0570, 0x0228, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0570, 0x0228, 1, 0x065C, 1, 0), - MX6_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x0570, 0x0228, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__GPT_CAPTURE1 = IOMUX_PAD(0x0570, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__UART2_RX = IOMUX_PAD(0x0570, 0x0228, 4, 0x0838, 2, 0), - MX6_PAD_SD1_DATA0__GPIO6_IO_2 = IOMUX_PAD(0x0570, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0570, 0x0228, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__CCM_OUT2 = IOMUX_PAD(0x0570, 0x0228, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__VADC_CLAMP_UP = IOMUX_PAD(0x0570, 0x0228, 8, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__MMDC_DEBUG_48 = IOMUX_PAD(0x0570, 0x0228, 9, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0574, 0x022C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__AUDMUX_AUD5_TXC = IOMUX_PAD(0x0574, 0x022C, 1, 0x066C, 1, 0), - MX6_PAD_SD1_DATA1__PWM4_OUT = IOMUX_PAD(0x0574, 0x022C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__GPT_CAPTURE2 = IOMUX_PAD(0x0574, 0x022C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__UART2_TX = IOMUX_PAD(0x0574, 0x022C, 4, 0x0838, 3, 0), - MX6_PAD_SD1_DATA1__GPIO6_IO_3 = IOMUX_PAD(0x0574, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0574, 0x022C, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__CCM_CLKO2 = IOMUX_PAD(0x0574, 0x022C, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__VADC_CLAMP_DOWN = IOMUX_PAD(0x0574, 0x022C, 8, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__MMDC_DEBUG_47 = IOMUX_PAD(0x0574, 0x022C, 9, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0578, 0x0230, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x0578, 0x0230, 1, 0x0670, 1, 0), - MX6_PAD_SD1_DATA2__PWM3_OUT = IOMUX_PAD(0x0578, 0x0230, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__GPT_COMPARE2 = IOMUX_PAD(0x0578, 0x0230, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__UART2_CTS_B = IOMUX_PAD(0x0578, 0x0230, 4, 0x0834, 2, 0), - MX6_PAD_SD1_DATA2__GPIO6_IO_4 = IOMUX_PAD(0x0578, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0578, 0x0230, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__CCM_OUT0 = IOMUX_PAD(0x0578, 0x0230, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__VADC_EXT_PD_N = IOMUX_PAD(0x0578, 0x0230, 8, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x057C, 0x0234, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__AUDMUX_AUD5_TXD = IOMUX_PAD(0x057C, 0x0234, 1, 0x0660, 1, 0), - MX6_PAD_SD1_DATA3__AUDMUX_AUD5_RXD = IOMUX_PAD(0x057C, 0x0234, 2, 0x065C, 2, 0), - MX6_PAD_SD1_DATA3__GPT_COMPARE3 = IOMUX_PAD(0x057C, 0x0234, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__UART2_RTS_B = IOMUX_PAD(0x057C, 0x0234, 4, 0x0834, 3, 0), - MX6_PAD_SD1_DATA3__GPIO6_IO_5 = IOMUX_PAD(0x057C, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__ECSPI4_SS1 = IOMUX_PAD(0x057C, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__CCM_PMIC_RDY = IOMUX_PAD(0x057C, 0x0234, 7, 0x069C, 2, 0), - MX6_PAD_SD1_DATA3__VADC_RST_N = IOMUX_PAD(0x057C, 0x0234, 8, 0x0000, 0, 0), - - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0580, 0x0238, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0580, 0x0238, 1, 0x0680, 2, 0), - MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x0580, 0x0238, 2, 0x07C8, 1, 0), - MX6_PAD_SD2_CLK__ECSPI4_SCLK = IOMUX_PAD(0x0580, 0x0238, 3, 0x0740, 1, 0), - MX6_PAD_SD2_CLK__MLB_SIG = IOMUX_PAD(0x0580, 0x0238, 4, 0x07F0, 2, 0), - MX6_PAD_SD2_CLK__GPIO6_IO_6 = IOMUX_PAD(0x0580, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0580, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__WDOG1_WDOG_ANY = IOMUX_PAD(0x0580, 0x0238, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 = IOMUX_PAD(0x0580, 0x0238, 8, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__MMDC_DEBUG_29 = IOMUX_PAD(0x0580, 0x0238, 9, 0x0000, 0, 0), - - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0584, 0x023C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__AUDMUX_AUD6_RXC = IOMUX_PAD(0x0584, 0x023C, 1, 0x067C, 2, 0), - MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0584, 0x023C, 2, 0x07D4, 1, 0), - MX6_PAD_SD2_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0584, 0x023C, 3, 0x0748, 1, 0), - MX6_PAD_SD2_CMD__MLB_CLK = IOMUX_PAD(0x0584, 0x023C, 4, 0x07E8, 2, 0), - MX6_PAD_SD2_CMD__GPIO6_IO_7 = IOMUX_PAD(0x0584, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x0584, 0x023C, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__WDOG3_WDOG_B = IOMUX_PAD(0x0584, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 = IOMUX_PAD(0x0584, 0x023C, 8, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__MMDC_DEBUG_30 = IOMUX_PAD(0x0584, 0x023C, 9, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0588, 0x0240, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0588, 0x0240, 1, 0x0674, 2, 0), - MX6_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x0588, 0x0240, 2, 0x07DC, 1, 0), - MX6_PAD_SD2_DATA0__PWM1_OUT = IOMUX_PAD(0x0588, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0588, 0x0240, IOMUX_CONFIG_SION | 4, 0x07C4, 3, 0), - MX6_PAD_SD2_DATA0__GPIO6_IO_8 = IOMUX_PAD(0x0588, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__ECSPI4_SS3 = IOMUX_PAD(0x0588, 0x0240, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__UART4_RX = IOMUX_PAD(0x0588, 0x0240, 7, 0x0848, 4, 0), - MX6_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 = IOMUX_PAD(0x0588, 0x0240, 8, 0x0000, 0, 0), - MX6_PAD_SD2_DATA0__MMDC_DEBUG_50 = IOMUX_PAD(0x0588, 0x0240, 9, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x058C, 0x0244, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x058C, 0x0244, 1, 0x0684, 2, 0), - MX6_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x058C, 0x0244, 2, 0x07D0, 1, 0), - MX6_PAD_SD2_DATA1__PWM2_OUT = IOMUX_PAD(0x058C, 0x0244, 3, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x058C, 0x0244, IOMUX_CONFIG_SION | 4, 0x07C0, 3, 0), - MX6_PAD_SD2_DATA1__GPIO6_IO_9 = IOMUX_PAD(0x058C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__ECSPI4_SS2 = IOMUX_PAD(0x058C, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__UART4_TX = IOMUX_PAD(0x058C, 0x0244, 7, 0x0848, 5, 0), - MX6_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 = IOMUX_PAD(0x058C, 0x0244, 8, 0x0000, 0, 0), - MX6_PAD_SD2_DATA1__MMDC_DEBUG_49 = IOMUX_PAD(0x058C, 0x0244, 9, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0590, 0x0248, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0590, 0x0248, 1, 0x0688, 2, 0), - MX6_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x0590, 0x0248, 2, 0x07D8, 1, 0), - MX6_PAD_SD2_DATA2__ECSPI4_SS0 = IOMUX_PAD(0x0590, 0x0248, 3, 0x074C, 1, 0), - MX6_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x0590, 0x0248, 4, 0x081C, 2, 0), - MX6_PAD_SD2_DATA2__GPIO6_IO_10 = IOMUX_PAD(0x0590, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DATA2__SPDIF_OUT = IOMUX_PAD(0x0590, 0x0248, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DATA2__UART6_RX = IOMUX_PAD(0x0590, 0x0248, 7, 0x0858, 4, 0), - MX6_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 = IOMUX_PAD(0x0590, 0x0248, 8, 0x0000, 0, 0), - MX6_PAD_SD2_DATA2__MMDC_DEBUG_32 = IOMUX_PAD(0x0590, 0x0248, 9, 0x0000, 0, 0), - - MX6_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0594, 0x024C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DATA3__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0594, 0x024C, 1, 0x0678, 2, 0), - MX6_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x0594, 0x024C, 2, 0x07CC, 1, 0), - MX6_PAD_SD2_DATA3__ECSPI4_MISO = IOMUX_PAD(0x0594, 0x024C, 3, 0x0744, 1, 0), - MX6_PAD_SD2_DATA3__MLB_DATA = IOMUX_PAD(0x0594, 0x024C, 4, 0x07EC, 2, 0), - MX6_PAD_SD2_DATA3__GPIO6_IO_11 = IOMUX_PAD(0x0594, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DATA3__SPDIF_IN = IOMUX_PAD(0x0594, 0x024C, 6, 0x0824, 4, 0), - MX6_PAD_SD2_DATA3__UART6_TX = IOMUX_PAD(0x0594, 0x024C, 7, 0x0858, 5, 0), - MX6_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 = IOMUX_PAD(0x0594, 0x024C, 8, 0x0000, 0, 0), - MX6_PAD_SD2_DATA3__MMDC_DEBUG_31 = IOMUX_PAD(0x0594, 0x024C, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0598, 0x0250, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART4_CTS_B = IOMUX_PAD(0x0598, 0x0250, 1, 0x0844, 0, 0), - MX6_PAD_SD3_CLK__ECSPI4_SCLK = IOMUX_PAD(0x0598, 0x0250, 2, 0x0740, 0, 0), - MX6_PAD_SD3_CLK__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0598, 0x0250, 3, 0x0680, 0, 0), - MX6_PAD_SD3_CLK__LCDIF2_VSYNC = IOMUX_PAD(0x0598, 0x0250, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO7_IO_0 = IOMUX_PAD(0x0598, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__LCDIF2_BUSY = IOMUX_PAD(0x0598, 0x0250, 6, 0x07E4, 0, 0), - MX6_PAD_SD3_CLK__TPSMP_HDATA_29 = IOMUX_PAD(0x0598, 0x0250, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x0598, 0x0250, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x059C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART4_TX = IOMUX_PAD(0x059C, 0x0254, 1, 0x0848, 0, 0), - MX6_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x059C, 0x0254, 2, 0x0748, 0, 0), - MX6_PAD_SD3_CMD__AUDMUX_AUD6_RXC = IOMUX_PAD(0x059C, 0x0254, 3, 0x067C, 0, 0), - MX6_PAD_SD3_CMD__LCDIF2_HSYNC = IOMUX_PAD(0x059C, 0x0254, 4, 0x07E4, 1, 0), - MX6_PAD_SD3_CMD__GPIO7_IO_1 = IOMUX_PAD(0x059C, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__LCDIF2_RS = IOMUX_PAD(0x059C, 0x0254, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__TPSMP_HDATA_28 = IOMUX_PAD(0x059C, 0x0254, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x059C, 0x0254, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x05A0, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__I2C4_SCL = IOMUX_PAD(0x05A0, 0x0258, IOMUX_CONFIG_SION | 1, 0x07C0, 0, 0), - MX6_PAD_SD3_DATA0__ECSPI2_SS1 = IOMUX_PAD(0x05A0, 0x0258, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x05A0, 0x0258, 3, 0x0674, 0, 0), - MX6_PAD_SD3_DATA0__LCDIF2_DATA_1 = IOMUX_PAD(0x05A0, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__GPIO7_IO_2 = IOMUX_PAD(0x05A0, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__DCIC1_OUT = IOMUX_PAD(0x05A0, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__TPSMP_HDATA_30 = IOMUX_PAD(0x05A0, 0x0258, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__GPU_DEBUG_0 = IOMUX_PAD(0x05A0, 0x0258, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x05A0, 0x0258, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x05A4, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__I2C4_SDA = IOMUX_PAD(0x05A4, 0x025C, IOMUX_CONFIG_SION | 1, 0x07C4, 0, 0), - MX6_PAD_SD3_DATA1__ECSPI2_SS2 = IOMUX_PAD(0x05A4, 0x025C, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x05A4, 0x025C, 3, 0x0684, 0, 0), - MX6_PAD_SD3_DATA1__LCDIF2_DATA_0 = IOMUX_PAD(0x05A4, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__GPIO7_IO_3 = IOMUX_PAD(0x05A4, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__DCIC2_OUT = IOMUX_PAD(0x05A4, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__TPSMP_HDATA_31 = IOMUX_PAD(0x05A4, 0x025C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__GPU_DEBUG_1 = IOMUX_PAD(0x05A4, 0x025C, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x05A4, 0x025C, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x05A8, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__UART4_RTS_B = IOMUX_PAD(0x05A8, 0x0260, 1, 0x0844, 1, 0), - MX6_PAD_SD3_DATA2__ECSPI4_SS0 = IOMUX_PAD(0x05A8, 0x0260, 2, 0x074C, 0, 0), - MX6_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x05A8, 0x0260, 3, 0x0688, 0, 0), - MX6_PAD_SD3_DATA2__LCDIF2_CLK = IOMUX_PAD(0x05A8, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__GPIO7_IO_4 = IOMUX_PAD(0x05A8, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__LCDIF2_WR_RWN = IOMUX_PAD(0x05A8, 0x0260, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__TPSMP_HDATA_26 = IOMUX_PAD(0x05A8, 0x0260, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__GPU_DEBUG_2 = IOMUX_PAD(0x05A8, 0x0260, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x05A8, 0x0260, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x05AC, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__UART4_RX = IOMUX_PAD(0x05AC, 0x0264, 1, 0x0848, 1, 0), - MX6_PAD_SD3_DATA3__ECSPI4_MISO = IOMUX_PAD(0x05AC, 0x0264, 2, 0x0744, 0, 0), - MX6_PAD_SD3_DATA3__AUDMUX_AUD6_TXD = IOMUX_PAD(0x05AC, 0x0264, 3, 0x0678, 0, 0), - MX6_PAD_SD3_DATA3__LCDIF2_ENABLE = IOMUX_PAD(0x05AC, 0x0264, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__GPIO7_IO_5 = IOMUX_PAD(0x05AC, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__LCDIF2_RD_E = IOMUX_PAD(0x05AC, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__TPSMP_HDATA_27 = IOMUX_PAD(0x05AC, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__GPU_DEBUG_3 = IOMUX_PAD(0x05AC, 0x0264, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x05AC, 0x0264, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA4__USDHC3_DATA4 = IOMUX_PAD(0x05B0, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA4__CAN2_RX = IOMUX_PAD(0x05B0, 0x0268, 1, 0x0690, 0, 0), - MX6_PAD_SD3_DATA4__CANFD_RX2 = IOMUX_PAD(0x05B0, 0x0268, 2, 0x0698, 0, 0), - MX6_PAD_SD3_DATA4__UART3_RX = IOMUX_PAD(0x05B0, 0x0268, 3, 0x0840, 2, 0), - MX6_PAD_SD3_DATA4__LCDIF2_DATA_3 = IOMUX_PAD(0x05B0, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA4__GPIO7_IO_6 = IOMUX_PAD(0x05B0, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x05B0, 0x0268, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA4__TPSMP_HTRANS_1 = IOMUX_PAD(0x05B0, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA4__GPU_DEBUG_4 = IOMUX_PAD(0x05B0, 0x0268, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x05B0, 0x0268, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA5__USDHC3_DATA5 = IOMUX_PAD(0x05B4, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__CAN1_TX = IOMUX_PAD(0x05B4, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__CANFD_TX1 = IOMUX_PAD(0x05B4, 0x026C, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__UART3_TX = IOMUX_PAD(0x05B4, 0x026C, 3, 0x0840, 3, 0), - MX6_PAD_SD3_DATA5__LCDIF2_DATA_2 = IOMUX_PAD(0x05B4, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__GPIO7_IO_7 = IOMUX_PAD(0x05B4, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x05B4, 0x026C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__SIM_M_HWRITE = IOMUX_PAD(0x05B4, 0x026C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__GPU_DEBUG_5 = IOMUX_PAD(0x05B4, 0x026C, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x05B4, 0x026C, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA6__USDHC3_DATA6 = IOMUX_PAD(0x05B8, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__CAN2_TX = IOMUX_PAD(0x05B8, 0x0270, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__CANFD_TX2 = IOMUX_PAD(0x05B8, 0x0270, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__UART3_RTS_B = IOMUX_PAD(0x05B8, 0x0270, 3, 0x083C, 2, 0), - MX6_PAD_SD3_DATA6__LCDIF2_DATA_4 = IOMUX_PAD(0x05B8, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__GPIO7_IO_8 = IOMUX_PAD(0x05B8, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x05B8, 0x0270, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__TPSMP_HTRANS_0 = IOMUX_PAD(0x05B8, 0x0270, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__GPU_DEBUG_7 = IOMUX_PAD(0x05B8, 0x0270, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x05B8, 0x0270, 9, 0x0000, 0, 0), - - MX6_PAD_SD3_DATA7__USDHC3_DATA7 = IOMUX_PAD(0x05BC, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DATA7__CAN1_RX = IOMUX_PAD(0x05BC, 0x0274, 1, 0x068C, 0, 0), - MX6_PAD_SD3_DATA7__CANFD_RX1 = IOMUX_PAD(0x05BC, 0x0274, 2, 0x0694, 0, 0), - MX6_PAD_SD3_DATA7__UART3_CTS_B = IOMUX_PAD(0x05BC, 0x0274, 3, 0x083C, 3, 0), - MX6_PAD_SD3_DATA7__LCDIF2_DATA_5 = IOMUX_PAD(0x05BC, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DATA7__GPIO7_IO_9 = IOMUX_PAD(0x05BC, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x05BC, 0x0274, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DATA7__TPSMP_HDATA_DIR = IOMUX_PAD(0x05BC, 0x0274, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DATA7__GPU_DEBUG_6 = IOMUX_PAD(0x05BC, 0x0274, 8, 0x0000, 0, 0), - MX6_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x05BC, 0x0274, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x05C0, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__RAWNAND_DATA15 = IOMUX_PAD(0x05C0, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__ECSPI2_MISO = IOMUX_PAD(0x05C0, 0x0278, 2, 0x0724, 1, 0), - MX6_PAD_SD4_CLK__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x05C0, 0x0278, 3, 0x0638, 0, 0), - MX6_PAD_SD4_CLK__LCDIF2_DATA_13 = IOMUX_PAD(0x05C0, 0x0278, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__GPIO6_IO_12 = IOMUX_PAD(0x05C0, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__ECSPI3_SS2 = IOMUX_PAD(0x05C0, 0x0278, 6, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__TPSMP_HDATA_20 = IOMUX_PAD(0x05C0, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__VDEC_DEBUG_12 = IOMUX_PAD(0x05C0, 0x0278, 8, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x05C0, 0x0278, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x05C4, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__RAWNAND_DATA14 = IOMUX_PAD(0x05C4, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__ECSPI2_MOSI = IOMUX_PAD(0x05C4, 0x027C, 2, 0x0728, 1, 0), - MX6_PAD_SD4_CMD__AUDMUX_AUD3_RXC = IOMUX_PAD(0x05C4, 0x027C, 3, 0x0634, 0, 0), - MX6_PAD_SD4_CMD__LCDIF2_DATA_14 = IOMUX_PAD(0x05C4, 0x027C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__GPIO6_IO_13 = IOMUX_PAD(0x05C4, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__ECSPI3_SS1 = IOMUX_PAD(0x05C4, 0x027C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__TPSMP_HDATA_19 = IOMUX_PAD(0x05C4, 0x027C, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__VDEC_DEBUG_11 = IOMUX_PAD(0x05C4, 0x027C, 8, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x05C4, 0x027C, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA0__USDHC4_DATA0 = IOMUX_PAD(0x05C8, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA0__RAWNAND_DATA10 = IOMUX_PAD(0x05C8, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA0__ECSPI2_SS0 = IOMUX_PAD(0x05C8, 0x0280, 2, 0x072C, 1, 0), - MX6_PAD_SD4_DATA0__AUDMUX_AUD3_RXD = IOMUX_PAD(0x05C8, 0x0280, 3, 0x062C, 0, 0), - MX6_PAD_SD4_DATA0__LCDIF2_DATA_12 = IOMUX_PAD(0x05C8, 0x0280, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA0__GPIO6_IO_14 = IOMUX_PAD(0x05C8, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA0__ECSPI3_SS3 = IOMUX_PAD(0x05C8, 0x0280, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DATA0__TPSMP_HDATA_21 = IOMUX_PAD(0x05C8, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA0__VDEC_DEBUG_13 = IOMUX_PAD(0x05C8, 0x0280, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA0__SDMA_DEBUG_MODE = IOMUX_PAD(0x05C8, 0x0280, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA1__USDHC4_DATA1 = IOMUX_PAD(0x05CC, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA1__RAWNAND_DATA11 = IOMUX_PAD(0x05CC, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA1__ECSPI2_SCLK = IOMUX_PAD(0x05CC, 0x0284, 2, 0x0720, 1, 0), - MX6_PAD_SD4_DATA1__AUDMUX_AUD3_TXC = IOMUX_PAD(0x05CC, 0x0284, 3, 0x063C, 0, 0), - MX6_PAD_SD4_DATA1__LCDIF2_DATA_11 = IOMUX_PAD(0x05CC, 0x0284, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA1__GPIO6_IO_15 = IOMUX_PAD(0x05CC, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA1__ECSPI3_RDY = IOMUX_PAD(0x05CC, 0x0284, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DATA1__TPSMP_HDATA_22 = IOMUX_PAD(0x05CC, 0x0284, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA1__VDEC_DEBUG_14 = IOMUX_PAD(0x05CC, 0x0284, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x05CC, 0x0284, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA2__USDHC4_DATA2 = IOMUX_PAD(0x05D0, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__RAWNAND_DATA12 = IOMUX_PAD(0x05D0, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__I2C2_SDA = IOMUX_PAD(0x05D0, 0x0288, IOMUX_CONFIG_SION | 2, 0x07B4, 0, 0), - MX6_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x05D0, 0x0288, 3, 0x0640, 0, 0), - MX6_PAD_SD4_DATA2__LCDIF2_DATA_10 = IOMUX_PAD(0x05D0, 0x0288, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__GPIO6_IO_16 = IOMUX_PAD(0x05D0, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__ECSPI2_SS3 = IOMUX_PAD(0x05D0, 0x0288, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__TPSMP_HDATA_23 = IOMUX_PAD(0x05D0, 0x0288, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__VDEC_DEBUG_15 = IOMUX_PAD(0x05D0, 0x0288, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x05D0, 0x0288, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA3__USDHC4_DATA3 = IOMUX_PAD(0x05D4, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__RAWNAND_DATA13 = IOMUX_PAD(0x05D4, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__I2C2_SCL = IOMUX_PAD(0x05D4, 0x028C, IOMUX_CONFIG_SION | 2, 0x07B0, 0, 0), - MX6_PAD_SD4_DATA3__AUDMUX_AUD3_TXD = IOMUX_PAD(0x05D4, 0x028C, 3, 0x0630, 0, 0), - MX6_PAD_SD4_DATA3__LCDIF2_DATA_9 = IOMUX_PAD(0x05D4, 0x028C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__GPIO6_IO_17 = IOMUX_PAD(0x05D4, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__ECSPI2_RDY = IOMUX_PAD(0x05D4, 0x028C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__TPSMP_HDATA_24 = IOMUX_PAD(0x05D4, 0x028C, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__VDEC_DEBUG_16 = IOMUX_PAD(0x05D4, 0x028C, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x05D4, 0x028C, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA4__USDHC4_DATA4 = IOMUX_PAD(0x05D8, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA4__RAWNAND_DATA09 = IOMUX_PAD(0x05D8, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA4__UART5_RX = IOMUX_PAD(0x05D8, 0x0290, 2, 0x0850, 0, 0), - MX6_PAD_SD4_DATA4__ECSPI3_SCLK = IOMUX_PAD(0x05D8, 0x0290, 3, 0x0730, 0, 0), - MX6_PAD_SD4_DATA4__LCDIF2_DATA_8 = IOMUX_PAD(0x05D8, 0x0290, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA4__GPIO6_IO_18 = IOMUX_PAD(0x05D8, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA4__SPDIF_OUT = IOMUX_PAD(0x05D8, 0x0290, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DATA4__TPSMP_HDATA_16 = IOMUX_PAD(0x05D8, 0x0290, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA4__USB_OTG_HOST_MODE = IOMUX_PAD(0x05D8, 0x0290, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x05D8, 0x0290, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA5__USDHC4_DATA5 = IOMUX_PAD(0x05DC, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA5__RAWNAND_CE2_B = IOMUX_PAD(0x05DC, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA5__UART5_TX = IOMUX_PAD(0x05DC, 0x0294, 2, 0x0850, 1, 0), - MX6_PAD_SD4_DATA5__ECSPI3_MOSI = IOMUX_PAD(0x05DC, 0x0294, 3, 0x0738, 0, 0), - MX6_PAD_SD4_DATA5__LCDIF2_DATA_7 = IOMUX_PAD(0x05DC, 0x0294, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA5__GPIO6_IO_19 = IOMUX_PAD(0x05DC, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA5__SPDIF_IN = IOMUX_PAD(0x05DC, 0x0294, 6, 0x0824, 0, 0), - MX6_PAD_SD4_DATA5__TPSMP_HDATA_17 = IOMUX_PAD(0x05DC, 0x0294, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA5__VDEC_DEBUG_9 = IOMUX_PAD(0x05DC, 0x0294, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x05DC, 0x0294, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA6__USDHC4_DATA6 = IOMUX_PAD(0x05E0, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA6__RAWNAND_CE3_B = IOMUX_PAD(0x05E0, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA6__UART5_RTS_B = IOMUX_PAD(0x05E0, 0x0298, 2, 0x084C, 0, 0), - MX6_PAD_SD4_DATA6__ECSPI3_MISO = IOMUX_PAD(0x05E0, 0x0298, 3, 0x0734, 0, 0), - MX6_PAD_SD4_DATA6__LCDIF2_DATA_6 = IOMUX_PAD(0x05E0, 0x0298, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA6__GPIO6_IO_20 = IOMUX_PAD(0x05E0, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA6__USDHC4_WP = IOMUX_PAD(0x05E0, 0x0298, 6, 0x0878, 0, 0), - MX6_PAD_SD4_DATA6__TPSMP_HDATA_18 = IOMUX_PAD(0x05E0, 0x0298, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA6__VDEC_DEBUG_10 = IOMUX_PAD(0x05E0, 0x0298, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x05E0, 0x0298, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_DATA7__USDHC4_DATA7 = IOMUX_PAD(0x05E4, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DATA7__RAWNAND_DATA08 = IOMUX_PAD(0x05E4, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA7__UART5_CTS_B = IOMUX_PAD(0x05E4, 0x029C, 2, 0x084C, 1, 0), - MX6_PAD_SD4_DATA7__ECSPI3_SS0 = IOMUX_PAD(0x05E4, 0x029C, 3, 0x073C, 0, 0), - MX6_PAD_SD4_DATA7__LCDIF2_DATA_15 = IOMUX_PAD(0x05E4, 0x029C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DATA7__GPIO6_IO_21 = IOMUX_PAD(0x05E4, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DATA7__USDHC4_CD_B = IOMUX_PAD(0x05E4, 0x029C, 6, 0x0874, 0, 0), - MX6_PAD_SD4_DATA7__TPSMP_HDATA_15 = IOMUX_PAD(0x05E4, 0x029C, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DATA7__USB_OTG_PWR_WAKE = IOMUX_PAD(0x05E4, 0x029C, 8, 0x0000, 0, 0), - MX6_PAD_SD4_DATA7__SDMA_DEBUG_YIELD = IOMUX_PAD(0x05E4, 0x029C, 9, 0x0000, 0, 0), - - MX6_PAD_SD4_RESET_B__USDHC4_RESET_B = IOMUX_PAD(0x05E8, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__RAWNAND_DQS = IOMUX_PAD(0x05E8, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__USDHC4_RESET = IOMUX_PAD(0x05E8, 0x02A0, 2, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__AUDMUX_MCLK = IOMUX_PAD(0x05E8, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__LCDIF2_RESET = IOMUX_PAD(0x05E8, 0x02A0, 4, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__GPIO6_IO_22 = IOMUX_PAD(0x05E8, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__LCDIF2_CS = IOMUX_PAD(0x05E8, 0x02A0, 6, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__TPSMP_HDATA_25 = IOMUX_PAD(0x05E8, 0x02A0, 7, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__VDEC_DEBUG_17 = IOMUX_PAD(0x05E8, 0x02A0, 8, 0x0000, 0, 0), - MX6_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x05E8, 0x02A0, 9, 0x0000, 0, 0), - - MX6_PAD_USB_H_DATA__USB_H_DATA = IOMUX_PAD(0x05EC, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_USB_H_DATA__PWM2_OUT = IOMUX_PAD(0x05EC, 0x02A4, 1, 0x0000, 0, 0), - MX6_PAD_USB_H_DATA__ANATOP_24M_OUT = IOMUX_PAD(0x05EC, 0x02A4, 2, 0x0000, 0, 0), - MX6_PAD_USB_H_DATA__I2C4_SDA = IOMUX_PAD(0x05EC, 0x02A4, IOMUX_CONFIG_SION | 3, 0x07C4, 1, 0), - MX6_PAD_USB_H_DATA__WDOG3_WDOG_B = IOMUX_PAD(0x05EC, 0x02A4, 4, 0x0000, 0, 0), - MX6_PAD_USB_H_DATA__GPIO7_IO_10 = IOMUX_PAD(0x05EC, 0x02A4, 5, 0x0000, 0, 0), - - MX6_PAD_USB_H_STROBE__USB_H_STROBE = IOMUX_PAD(0x05F0, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_USB_H_STROBE__PWM1_OUT = IOMUX_PAD(0x05F0, 0x02A8, 1, 0x0000, 0, 0), - MX6_PAD_USB_H_STROBE__ANATOP_32K_OUT = IOMUX_PAD(0x05F0, 0x02A8, 2, 0x0000, 0, 0), - MX6_PAD_USB_H_STROBE__I2C4_SCL = IOMUX_PAD(0x05F0, 0x02A8, IOMUX_CONFIG_SION | 3, 0x07C0, 1, 0), - MX6_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x05F0, 0x02A8, 4, 0x0000, 0, 0), - MX6_PAD_USB_H_STROBE__GPIO7_IO_11 = IOMUX_PAD(0x05F0, 0x02A8, 5, 0x0000, 0, 0), -}; -#endif /* __ASM_ARCH_MX6_ MX6_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h deleted file mode 100644 index 7ff2016..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __MX6SX_RDC_H__ -#define __MX6SX_RDC_H__ - -#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ - -enum { - RDC_PER_PWM1 = 0, - RDC_PER_PWM2, - RDC_PER_PWM3, - RDC_PER_PWM4, - RDC_PER_CAN1, - RDC_PER_CAN2, - RDC_PER_GPT, - RDC_PER_GPIO1, - RDC_PER_GPIO2, - RDC_PER_GPIO3, - RDC_PER_GPIO4, - RDC_PER_GPIO5, - RDC_PER_GPIO6, - RDC_PER_GPIO7, - RDC_PER_KPP, - RDC_PER_WDOG1, - RDC_PER_WODG2, - RDC_PER_CCM, - RDC_PER_ANATOPDIG, - RDC_PER_SNVSHP, - RDC_PER_EPIT1, - RDC_PER_EPIT2, - RDC_PER_SRC, - RDC_PER_GPC, - RDC_PER_IOMUXC, - RDC_PER_IOMUXCGPR, - RDC_PER_CANFD1, - RDC_PER_SDMA, - RDC_PER_CANFD2, - RDC_PER_SEMA1, - RDC_PER_SEMA2, - RDC_PER_RDC, - RDC_PER_AIPSTZ1_GE1, - RDC_PER_AIPSTZ2_GE2, - RDC_PER_USBO2H_PL301, - RDC_PER_USBO2H_USB, - RDC_PER_ENET1, - RDC_PER_MLB25, - RDC_PER_USDHC1, - RDC_PER_USDHC2, - RDC_PER_USDHC3, - RDC_PER_USDHC4, - RDC_PER_I2C1, - RDC_PER_I2C2, - RDC_PER_I2C3, - RDC_PER_ROMCP, - RDC_PER_MMDC, - RDC_PER_ENET2, - RDC_PER_EIM, - RDC_PER_OCOTP, - RDC_PER_CSU, - RDC_PER_PERFMON1, - RDC_PER_PERFMON2, - RDC_PER_AXIMON, - RDC_PER_TZASC1, - RDC_PER_SAI1, - RDC_PER_AUDMUX, - RDC_PER_SAI2, - RDC_PER_QSPI1, - RDC_PER_QSPI2, - RDC_PER_UART2, - RDC_PER_UART3, - RDC_PER_UART4, - RDC_PER_UART5, - RDC_PER_I2C4, - RDC_PER_QOSC, - RDC_PER_CAAM, - RDC_PER_DAP, - RDC_PER_ADC1, - RDC_PER_ADC2, - RDC_PER_WDOG3, - RDC_PER_ECSPI5, - RDC_PER_SEMA4, - RDC_PER_MUPORT1, - RDC_PER_CANFD_CPU, - RDC_PER_MUPORT2, - RDC_PER_UART6, - RDC_PER_PWM5, - RDC_PER_PWM6, - RDC_PER_PWM7, - RDC_PER_PWM8, - RDC_PER_AIPSTZ3_GE0, - RDC_PER_AIPSTZ3_GE1, - RDC_PER_RESERVED1, - RDC_PER_SPDIF, - RDC_PER_ECSPI1, - RDC_PER_ECSPI2, - RDC_PER_ECSPI3, - RDC_PER_ECSPI4, - RDC_PER_RESERVED2, - RDC_PER_RESERVED3, - RDC_PER_UART1, - RDC_PER_ESAI, - RDC_PER_SSI1, - RDC_PER_SSI2, - RDC_PER_SSI3, - RDC_PER_ASRC, - RDC_PER_RESERVED4, - RDC_PER_SPBA_MA, - RDC_PER_GIS, - RDC_PER_DCIC1, - RDC_PER_DCIC2, - RDC_PER_CSI1, - RDC_PER_PXP, - RDC_PER_CSI2, - RDC_PER_LCDIF1, - RDC_PER_LCDIF2, - RDC_PER_VADC, - RDC_PER_VDEC, - RDC_PER_SPBA_DISPLAYMIX, -}; - -enum { - RDC_MA_A9_L2CACHE = 0, - RDC_MA_M4, - RDC_MA_GPU, - RDC_MA_CSI1, - RDC_MA_CSI2, - RDC_MA_LCDIF1, - RDC_MA_LCDIF2, - RDC_MA_PXP, - RDC_MA_PCIE_CTRL, - RDC_MA_DAP, - RDC_MA_CAAM, - RDC_MA_SDMA_PERI, - RDC_MA_SDMA_BURST, - RDC_MA_APBHDMA, - RDC_MA_RAWNAND, - RDC_MA_USDHC1, - RDC_MA_USDHC2, - RDC_MA_USDHC3, - RDC_MA_USDHC4, - RDC_MA_USB, - RDC_MA_MLB, - RDC_MA_TEST, - RDC_MA_ENET1_TX, - RDC_MA_ENET1_RX, - RDC_MA_ENET2_TX, - RDC_MA_ENET2_RX, - RDC_MA_SDMA, -}; - -#endif /* __MX6SX_RDC_H__*/ diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h deleted file mode 100644 index 9977958..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX6UL_DDR_H__ -#define __ASM_ARCH_MX6UL_DDR_H__ - -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#error "wrong CPU" -#endif - -#define MX6_IOM_DRAM_DQM0 0x020e0244 -#define MX6_IOM_DRAM_DQM1 0x020e0248 - -#define MX6_IOM_DRAM_RAS 0x020e024c -#define MX6_IOM_DRAM_CAS 0x020e0250 -#define MX6_IOM_DRAM_CS0 0x020e0254 -#define MX6_IOM_DRAM_CS1 0x020e0258 -#define MX6_IOM_DRAM_SDWE_B 0x020e025c -#define MX6_IOM_DRAM_SDODT0 0x020e0260 -#define MX6_IOM_DRAM_SDODT1 0x020e0264 -#define MX6_IOM_DRAM_SDBA0 0x020e0268 -#define MX6_IOM_DRAM_SDBA1 0x020e026c -#define MX6_IOM_DRAM_SDBA2 0x020e0270 -#define MX6_IOM_DRAM_SDCKE0 0x020e0274 -#define MX6_IOM_DRAM_SDCKE1 0x020e0278 -#define MX6_IOM_DRAM_SDCLK_0 0x020e027c -#define MX6_IOM_DRAM_SDQS0 0x020e0280 -#define MX6_IOM_DRAM_SDQS1 0x020e0284 -#define MX6_IOM_DRAM_RESET 0x020e0288 - -#define MX6_IOM_GRP_ADDDS 0x020e0490 -#define MX6_IOM_DDRMODE_CTL 0x020e0494 -#define MX6_IOM_GRP_B0DS 0x020e0498 -#define MX6_IOM_GRP_DDRPK 0x020e049c -#define MX6_IOM_GRP_CTLDS 0x020e04a0 -#define MX6_IOM_GRP_B1DS 0x020e04a4 -#define MX6_IOM_GRP_DDRHYS 0x020e04a8 -#define MX6_IOM_GRP_DDRPKE 0x020e04ac -#define MX6_IOM_GRP_DDRMODE 0x020e04b0 -#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4 - -#endif /*__ASM_ARCH_MX6SX_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h deleted file mode 100644 index 031b4a0..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h +++ /dev/null @@ -1,1064 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX6UL_PINS_H__ -#define __ASM_ARCH_IMX6UL_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - - MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0), - MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0), - /* - * The TAMPER Pin can be used for GPIO, which depends on - * fusemap TAMPER_PIN_DISABLE[1:0] settings. - */ - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0), - - MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0), - MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0), - MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0), - - MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0), - MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0), - MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0), - MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0), - MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0), - MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0), - MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), - MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), - MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0), - MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0), - MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0), - MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0), - MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0), - MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0), - MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0), - MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0), - MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0), - MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0), - - MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), - MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), - MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), - MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0), - MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), - MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0), - - MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0), - MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0), - MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0), - MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0), - MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0), - MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0), - MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0), - MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0), - - MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0), - MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0), - MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0), - MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0), - MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0), - MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0), - MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0), - MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0), - MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0), - - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0), - - MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0), - MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0), - MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0), - MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0), - MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0), - MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0), - - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0), - - MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0), - MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0), - MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0), - MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0), - - MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0), - - MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0), - MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0), - MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0), - MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0), - MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0), - - MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0), - - MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0), - MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0), - MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0), - - MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0), - - MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0), - MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0), - MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0), - MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0), - MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0), - MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0), - - MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0), - - MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0), - MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0), - MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0), - MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0), - - MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0), - - MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0), - MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0), - MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0), - - MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0), - - MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0), - MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0), - MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0), - - MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0), - - MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0), - MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0), - MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0), - MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0), - - MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0), - - MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0), - MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0), - MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0), - - MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0), - - MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0), - MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0), - MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0), - - MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0), - - MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0), - MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0), - MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0), - - MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0), - - MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0), - MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0), - MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0), - MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0), - - MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0), - - MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0), - MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0), - MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0), - MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0), - - MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), - - MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), - MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), - MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), - MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0), - - MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0), - - MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0), - MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0), - MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0), - - MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0), - MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0), - MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0), - MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0), - MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0), - MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0), - MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0), - MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), - MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), - MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0), - MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), - MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), - MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), - MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0), - MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0), - MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0), - MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0), - MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0), - MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0), - MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0), - MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0), - MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0), - MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0), - MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0), - - MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0), - MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0), - MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0), - - MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0), - MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0), - MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0), - MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), - MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0), - MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), - - MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0), - MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0), - MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), - - MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), - MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0), - MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), - - MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0), - MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0), - MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), - MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0), - MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), - - MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0), - MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0), - MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0), - MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), - - MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), - MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0), - MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0), - MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0), - MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0), - MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0), - MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), - MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0), - MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0), - MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), - MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0), - MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0), - MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__CA7_MX6UL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), - MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), - - MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), - MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), - - MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), - MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), - - MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), - MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), - - MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), - MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), - MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), - MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), - MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), - MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), - MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), - MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), - MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), - MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0), - - MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), - MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), - MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0), - - MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), - MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), - MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), - MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), - MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), - MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), - MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), - - MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), - MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), - - MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), - MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), - MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), - - MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), - MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), - MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), - - MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__CA7_MX6UL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0), - MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0), - MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0), - - MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0), - MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0), - - MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0), - MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0), - MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0), - - MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0), - MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0), - MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0), - MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), - - MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0), - MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0), - MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0), - - MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0), - MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0), - MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0), - - MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0), - MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0), - MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0), - MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0), - MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0), - MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0), - MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0), - MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0), - MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0), - MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0), - MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0), - MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0), - MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0), - MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0), - MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0), - - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0), - MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0), - MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0), - MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0), - MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0), - MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0), - - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0), - MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0), - MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0), - MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0), - MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0), - - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0), - MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0), - MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0), - MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0), - - MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0), - MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0), - MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0), - MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0), - MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0), - - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0), - MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0), - - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0), - MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0), - MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0), - - MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0), - MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0), - - MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0), - MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0), - MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0), - MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0), - MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0), - MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0), - - MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0), - MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0), - MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0), - - MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0), - MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0), - MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0), - - MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0), - MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0), - MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0), - MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0), - MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0), - MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0), - MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0), - MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0), - MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0), - MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0), - MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0), - MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0), - - MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0), - MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0), - MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0), - MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0), - - MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0), - MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0), - MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0), - MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0), - MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0), - MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0), - MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0), - MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0), - MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), - MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), - MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0), - MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0), - MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0), - - MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0), - MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0), - MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0), - MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0), - MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0), - - MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0), - MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0), - MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0), - MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0), - MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0), - - MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0), - MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0), - MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0), - MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0), - MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0), - MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0), - MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0), - MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0), -}; -#endif /* __ASM_ARCH_IMX6UL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h deleted file mode 100644 index de4a1ab..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h +++ /dev/null @@ -1,1064 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX6ULL_PINS_H__ -#define __ASM_ARCH_IMX6ULL_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - - /* - * The TAMPER Pin can be used for GPIO, which depends on - * TAMPER_PIN_DISABLE[1:0] settings. - */ - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x0068, 0x0024, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x006C, 0x0028, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x0070, 0x002C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - - MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0), - MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0), - MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0), - - MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0), - MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0), - MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0), - MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0), - MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0), - MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0), - MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), - MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), - - MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), - MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0), - MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0), - MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0), - MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0), - MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0), - MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0), - MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0), - MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0), - MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0), - MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0), - - MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), - MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), - MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), - MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0), - MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), - MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0), - - MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0), - MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0), - MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0), - MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0), - MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0), - MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0), - MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0), - MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0), - - MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0), - MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0), - MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0), - MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0), - MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0), - MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0), - MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0), - - MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0), - MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0), - MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0), - MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0), - - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0), - - MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0), - MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0), - MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0), - MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0), - MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0), - MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0), - - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0), - - MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0), - MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0), - MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0), - MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0), - - MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0), - - MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0), - MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0), - MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0), - MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0), - MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0), - - MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0), - - MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0), - MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0), - MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0), - - MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0), - - MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0), - MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0), - MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0), - MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0), - MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0), - MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0), - - MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0), - - MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0), - MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0), - MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0), - MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0), - - MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0), - - MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0), - MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0), - MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0), - - MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0), - - MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0), - MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0), - MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0), - MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0), - - MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0), - - MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0), - MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0), - MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0), - MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0), - MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0), - - MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0), - - MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0), - MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0), - MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0), - - MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0), - - MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0), - MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0), - MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0), - - MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0), - - MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0), - MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0), - MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0), - - MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0), - - MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0), - MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0), - MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0), - MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0), - - MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0), - - MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0), - MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0), - MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0), - MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0), - - MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), - - MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), - MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), - MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), - MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0), - - MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 7, 0), - - MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0), - MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0), - MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0), - - MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0), - MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0), - MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0), - MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0), - MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0), - MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0), - MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0), - MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), - MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), - MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0), - MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), - MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), - MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), - MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0), - MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0), - MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0), - MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0), - MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0), - MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0), - MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0), - MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0), - MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0), - - MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0), - MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0), - MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0), - - MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0), - MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0), - MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0), - - MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0), - MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0), - MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0), - MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), - MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0), - MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), - - MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0), - MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0), - MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), - - MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), - MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0), - MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), - - MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0), - MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0), - MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), - - MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), - MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0), - MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), - - MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0), - MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0), - MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0), - MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), - - MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), - MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0), - MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0), - MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0), - MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0), - MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0), - MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), - MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0), - MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0), - MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), - MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0), - MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0), - MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__CA7_MX6ULL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), - MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), - - MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), - MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), - - MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), - MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), - - MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), - MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), - - MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), - MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), - MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), - MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), - MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), - MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), - MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), - MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), - MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), - MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0), - - MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), - MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), - MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0), - - MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), - MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), - MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), - MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), - MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0), - - MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), - MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), - MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), - - MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), - MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), - - MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), - MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), - MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), - - MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), - MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), - MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), - - MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__CA7_MX6ULL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0), - MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0), - MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0), - - MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0), - MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0), - - MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0), - MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0), - MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0), - - MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0), - MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0), - MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0), - MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), - - MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0), - MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0), - MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0), - - MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0), - MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0), - MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0), - - MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0), - MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0), - MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0), - MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0), - MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0), - MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0), - MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0), - MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0), - MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0), - MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0), - MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0), - MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0), - MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0), - MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0), - MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0), - - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0), - MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0), - MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0), - MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0), - MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0), - MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0), - - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0), - MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0), - MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0), - MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0), - MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0), - - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0), - MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0), - MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0), - MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0), - - MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0), - MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0), - MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0), - - MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0), - MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0), - MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0), - - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0), - MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0), - - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0), - MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0), - MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0), - - MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0), - MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0), - - MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0), - MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0), - MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0), - MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0), - - MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0), - MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0), - MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0), - - MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0), - MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0), - MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0), - - MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0), - MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0), - MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0), - - MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0), - MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0), - MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0), - MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0), - MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0), - MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0), - MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0), - MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0), - MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0), - MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0), - MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0), - MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0), - MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0), - - MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0), - MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0), - MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0), - MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0), - - MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0), - MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0), - MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0), - MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0), - MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0), - MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0), - MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0), - MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0), - MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), - MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), - MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0), - MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0), - MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0), - MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0), - - MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0), - MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0), - MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0), - MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0), - MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0), - - MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0), - MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0), - MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0), - MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0), - MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0), - - MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0), - MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0), - MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0), - MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0), - MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0), - - MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0), - MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0), - MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0), - MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0), -}; -#endif /* __ASM_ARCH_IMX6ULL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h deleted file mode 100644 index 71ad0e3..0000000 --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ /dev/null @@ -1,1057 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __MXC_HDMI_H__ -#define __MXC_HDMI_H__ - -#ifdef CONFIG_IMX_HDMI -void imx_enable_hdmi_phy(void); -void imx_setup_hdmi(void); -#endif - -/* - * Hdmi controller registers - */ -struct hdmi_regs { - /*Identification Registers */ - u8 design_id; /* 0x000 */ - u8 revision_id; /* 0x001 */ - u8 product_id0; /* 0x002 */ - u8 product_id1; /* 0x003 */ - u8 config0_id; /* 0x004 */ - u8 config1_id; /* 0x005 */ - u8 config2_id; /* 0x006 */ - u8 config3_id; /* 0x007 */ - u8 reserved1[0xf8]; - /* Interrupt Registers */ - u8 ih_fc_stat0; /* 0x100 */ - u8 ih_fc_stat1; /* 0x101 */ - u8 ih_fc_stat2; /* 0x102 */ - u8 ih_as_stat0; /* 0x103 */ - u8 ih_phy_stat0; /* 0x104 */ - u8 ih_i2cm_stat0; /* 0x105 */ - u8 ih_cec_stat0; /* 0x106 */ - u8 ih_vp_stat0; /* 0x107 */ - u8 ih_i2cmphy_stat0; /* 0x108 */ - u8 ih_ahbdmaaud_stat0; /* 0x109 */ - u8 reserved2[0x76]; - u8 ih_mute_fc_stat0; /* 0x180 */ - u8 ih_mute_fc_stat1; /* 0x181 */ - u8 ih_mute_fc_stat2; /* 0x182 */ - u8 ih_mute_as_stat0; /* 0x183 */ - u8 ih_mute_phy_stat0; /* 0x184 */ - u8 ih_mute_i2cm_stat0; /* 0x185 */ - u8 ih_mute_cec_stat0; /* 0x186 */ - u8 ih_mute_vp_stat0; /* 0x187 */ - u8 ih_mute_i2cmphy_stat0; /* 0x188 */ - u8 ih_mute_ahbdmaaud_stat0; /* 0x189 */ - u8 reserved3[0x75]; - u8 ih_mute; /* 0x1ff */ - /* Video Sample Registers */ - u8 tx_invid0; /* 0x200 */ - u8 tx_instuffing; /* 0x201 */ - u8 tx_gydata0; /* 0x202 */ - u8 tx_gydata1; /* 0x203 */ - u8 tx_rcrdata0; /* 0x204 */ - u8 tx_rcrdata1; /* 0x205 */ - u8 tx_bcbdata0; /* 0x206 */ - u8 tx_bcbdata1; /* 0x207 */ - u8 reserved4[0x5f8]; - /* Video Packetizer Registers */ - u8 vp_status; /* 0x800 */ - u8 vp_pr_cd; /* 0x801 */ - u8 vp_stuff; /* 0x802 */ - u8 vp_remap; /* 0x803 */ - u8 vp_conf; /* 0x804 */ - u8 vp_stat; /* 0x805 */ - u8 vp_int; /* 0x806 */ - u8 vp_mask; /* 0x807 */ - u8 vp_pol; /* 0x808 */ - u8 reserved5[0x7f7]; - /* Frame Composer Registers */ - u8 fc_invidconf; /* 0x1000 */ - u8 fc_inhactv0; /* 0x1001 */ - u8 fc_inhactv1; /* 0x1002 */ - u8 fc_inhblank0; /* 0x1003 */ - u8 fc_inhblank1; /* 0x1004 */ - u8 fc_invactv0; /* 0x1005 */ - u8 fc_invactv1; /* 0x1006 */ - u8 fc_invblank; /* 0x1007 */ - u8 fc_hsyncindelay0; /* 0x1008 */ - u8 fc_hsyncindelay1; /* 0x1009 */ - u8 fc_hsyncinwidth0; /* 0x100a */ - u8 fc_hsyncinwidth1; /* 0x100b */ - u8 fc_vsyncindelay; /* 0x100c */ - u8 fc_vsyncinwidth; /* 0x100d */ - u8 fc_infreq0; /* 0x100e */ - u8 fc_infreq1; /* 0x100f */ - u8 fc_infreq2; /* 0x1010 */ - u8 fc_ctrldur; /* 0x1011 */ - u8 fc_exctrldur; /* 0x1012 */ - u8 fc_exctrlspac; /* 0x1013 */ - u8 fc_ch0pream; /* 0x1014 */ - u8 fc_ch1pream; /* 0x1015 */ - u8 fc_ch2pream; /* 0x1016 */ - u8 fc_aviconf3; /* 0x1017 */ - u8 fc_gcp; /* 0x1018 */ - u8 fc_aviconf0; /* 0x1019 */ - u8 fc_aviconf1; /* 0x101a */ - u8 fc_aviconf2; /* 0x101b */ - u8 fc_avivid; /* 0x101c */ - u8 fc_avietb0; /* 0x101d */ - u8 fc_avietb1; /* 0x101e */ - u8 fc_avisbb0; /* 0x101f */ - u8 fc_avisbb1; /* 0x1020 */ - u8 fc_avielb0; /* 0x1021 */ - u8 fc_avielb1; /* 0x1022 */ - u8 fc_avisrb0; /* 0x1023 */ - u8 fc_avisrb1; /* 0x1024 */ - u8 fc_audiconf0; /* 0x1025 */ - u8 fc_audiconf1; /* 0x1026 */ - u8 fc_audiconf2; /* 0x1027 */ - u8 fc_audiconf3; /* 0x1028 */ - u8 fc_vsdieeeid0; /* 0x1029 */ - u8 fc_vsdsize; /* 0x102a */ - u8 reserved6[5]; - u8 fc_vsdieeeid1; /* 0x1030 */ - u8 fc_vsdieeeid2; /* 0x1031 */ - u8 fc_vsdpayload0; /* 0x1032 */ - u8 fc_vsdpayload1; /* 0x1033 */ - u8 fc_vsdpayload2; /* 0x1034 */ - u8 fc_vsdpayload3; /* 0x1035 */ - u8 fc_vsdpayload4; /* 0x1036 */ - u8 fc_vsdpayload5; /* 0x1037 */ - u8 fc_vsdpayload6; /* 0x1038 */ - u8 fc_vsdpayload7; /* 0x1039 */ - u8 fc_vsdpayload8; /* 0x103a */ - u8 fc_vsdpayload9; /* 0x103b */ - u8 fc_vsdpayload10; /* 0x103c */ - u8 fc_vsdpayload11; /* 0x103d */ - u8 fc_vsdpayload12; /* 0x103e */ - u8 fc_vsdpayload13; /* 0x103f */ - u8 fc_vsdpayload14; /* 0x1040 */ - u8 fc_vsdpayload15; /* 0x1041 */ - u8 fc_vsdpayload16; /* 0x1042 */ - u8 fc_vsdpayload17; /* 0x1043 */ - u8 fc_vsdpayload18; /* 0x1044 */ - u8 fc_vsdpayload19; /* 0x1045 */ - u8 fc_vsdpayload20; /* 0x1046 */ - u8 fc_vsdpayload21; /* 0x1047 */ - u8 fc_vsdpayload22; /* 0x1048 */ - u8 fc_vsdpayload23; /* 0x1049 */ - u8 fc_spdvendorname0; /* 0x104a */ - u8 fc_spdvendorname1; /* 0x104b */ - u8 fc_spdvendorname2; /* 0x104c */ - u8 fc_spdvendorname3; /* 0x104d */ - u8 fc_spdvendorname4; /* 0x104e */ - u8 fc_spdvendorname5; /* 0x104f */ - u8 fc_spdvendorname6; /* 0x1050 */ - u8 fc_spdvendorname7; /* 0x1051 */ - u8 fc_sdpproductname0; /* 0x1052 */ - u8 fc_sdpproductname1; /* 0x1053 */ - u8 fc_sdpproductname2; /* 0x1054 */ - u8 fc_sdpproductname3; /* 0x1055 */ - u8 fc_sdpproductname4; /* 0x1056 */ - u8 fc_sdpproductname5; /* 0x1057 */ - u8 fc_sdpproductname6; /* 0x1058 */ - u8 fc_sdpproductname7; /* 0x1059 */ - u8 fc_sdpproductname8; /* 0x105a */ - u8 fc_sdpproductname9; /* 0x105b */ - u8 fc_sdpproductname10; /* 0x105c */ - u8 fc_sdpproductname11; /* 0x105d */ - u8 fc_sdpproductname12; /* 0x105e */ - u8 fc_sdpproductname13; /* 0x105f */ - u8 fc_sdpproductname14; /* 0x1060 */ - u8 fc_spdproductname15; /* 0x1061 */ - u8 fc_spddeviceinf; /* 0x1062 */ - u8 fc_audsconf; /* 0x1063 */ - u8 fc_audsstat; /* 0x1064 */ - u8 reserved7[0xb]; - u8 fc_datach0fill; /* 0x1070 */ - u8 fc_datach1fill; /* 0x1071 */ - u8 fc_datach2fill; /* 0x1072 */ - u8 fc_ctrlqhigh; /* 0x1073 */ - u8 fc_ctrlqlow; /* 0x1074 */ - u8 fc_acp0; /* 0x1075 */ - u8 fc_acp28; /* 0x1076 */ - u8 fc_acp27; /* 0x1077 */ - u8 fc_acp26; /* 0x1078 */ - u8 fc_acp25; /* 0x1079 */ - u8 fc_acp24; /* 0x107a */ - u8 fc_acp23; /* 0x107b */ - u8 fc_acp22; /* 0x107c */ - u8 fc_acp21; /* 0x107d */ - u8 fc_acp20; /* 0x107e */ - u8 fc_acp19; /* 0x107f */ - u8 fc_acp18; /* 0x1080 */ - u8 fc_acp17; /* 0x1081 */ - u8 fc_acp16; /* 0x1082 */ - u8 fc_acp15; /* 0x1083 */ - u8 fc_acp14; /* 0x1084 */ - u8 fc_acp13; /* 0x1085 */ - u8 fc_acp12; /* 0x1086 */ - u8 fc_acp11; /* 0x1087 */ - u8 fc_acp10; /* 0x1088 */ - u8 fc_acp9; /* 0x1089 */ - u8 fc_acp8; /* 0x108a */ - u8 fc_acp7; /* 0x108b */ - u8 fc_acp6; /* 0x108c */ - u8 fc_acp5; /* 0x108d */ - u8 fc_acp4; /* 0x108e */ - u8 fc_acp3; /* 0x108f */ - u8 fc_acp2; /* 0x1090 */ - u8 fc_acp1; /* 0x1091 */ - u8 fc_iscr1_0; /* 0x1092 */ - u8 fc_iscr1_16; /* 0x1093 */ - u8 fc_iscr1_15; /* 0x1094 */ - u8 fc_iscr1_14; /* 0x1095 */ - u8 fc_iscr1_13; /* 0x1096 */ - u8 fc_iscr1_12; /* 0x1097 */ - u8 fc_iscr1_11; /* 0x1098 */ - u8 fc_iscr1_10; /* 0x1099 */ - u8 fc_iscr1_9; /* 0x109a */ - u8 fc_iscr1_8; /* 0x109b */ - u8 fc_iscr1_7; /* 0x109c */ - u8 fc_iscr1_6; /* 0x109d */ - u8 fc_iscr1_5; /* 0x109e */ - u8 fc_iscr1_4; /* 0x109f */ - u8 fc_iscr1_3; /* 0x10a0 */ - u8 fc_iscr1_2; /* 0x10a1 */ - u8 fc_iscr1_1; /* 0x10a2 */ - u8 fc_iscr2_15; /* 0x10a3 */ - u8 fc_iscr2_14; /* 0x10a4 */ - u8 fc_iscr2_13; /* 0x10a5 */ - u8 fc_iscr2_12; /* 0x10a6 */ - u8 fc_iscr2_11; /* 0x10a7 */ - u8 fc_iscr2_10; /* 0x10a8 */ - u8 fc_iscr2_9; /* 0x10a9 */ - u8 fc_iscr2_8; /* 0x10aa */ - u8 fc_iscr2_7; /* 0x10ab */ - u8 fc_iscr2_6; /* 0x10ac */ - u8 fc_iscr2_5; /* 0x10ad */ - u8 fc_iscr2_4; /* 0x10ae */ - u8 fc_iscr2_3; /* 0x10af */ - u8 fc_iscr2_2; /* 0x10b0 */ - u8 fc_iscr2_1; /* 0x10b1 */ - u8 fc_iscr2_0; /* 0x10b2 */ - u8 fc_datauto0; /* 0x10b3 */ - u8 fc_datauto1; /* 0x10b4 */ - u8 fc_datauto2; /* 0x10b5 */ - u8 fc_datman; /* 0x10b6 */ - u8 fc_datauto3; /* 0x10b7 */ - u8 fc_rdrb0; /* 0x10b8 */ - u8 fc_rdrb1; /* 0x10b9 */ - u8 fc_rdrb2; /* 0x10ba */ - u8 fc_rdrb3; /* 0x10bb */ - u8 fc_rdrb4; /* 0x10bc */ - u8 fc_rdrb5; /* 0x10bd */ - u8 fc_rdrb6; /* 0x10be */ - u8 fc_rdrb7; /* 0x10bf */ - u8 reserved8[0x10]; - u8 fc_stat0; /* 0x10d0 */ - u8 fc_int0; /* 0x10d1 */ - u8 fc_mask0; /* 0x10d2 */ - u8 fc_pol0; /* 0x10d3 */ - u8 fc_stat1; /* 0x10d4 */ - u8 fc_int1; /* 0x10d5 */ - u8 fc_mask1; /* 0x10d6 */ - u8 fc_pol1; /* 0x10d7 */ - u8 fc_stat2; /* 0x10d8 */ - u8 fc_int2; /* 0x10d9 */ - u8 fc_mask2; /* 0x10da */ - u8 fc_pol2; /* 0x10db */ - u8 reserved9[0x4]; - u8 fc_prconf; /* 0x10e0 */ - u8 reserved10[0x1f]; - u8 fc_gmd_stat; /* 0x1100 */ - u8 fc_gmd_en; /* 0x1101 */ - u8 fc_gmd_up; /* 0x1102 */ - u8 fc_gmd_conf; /* 0x1103 */ - u8 fc_gmd_hb; /* 0x1104 */ - u8 fc_gmd_pb0; /* 0x1105 */ - u8 fc_gmd_pb1; /* 0x1106 */ - u8 fc_gmd_pb2; /* 0x1107 */ - u8 fc_gmd_pb3; /* 0x1108 */ - u8 fc_gmd_pb4; /* 0x1109 */ - u8 fc_gmd_pb5; /* 0x110a */ - u8 fc_gmd_pb6; /* 0x110b */ - u8 fc_gmd_pb7; /* 0x110c */ - u8 fc_gmd_pb8; /* 0x110d */ - u8 fc_gmd_pb9; /* 0x110e */ - u8 fc_gmd_pb10; /* 0x110f */ - u8 fc_gmd_pb11; /* 0x1110 */ - u8 fc_gmd_pb12; /* 0x1111 */ - u8 fc_gmd_pb13; /* 0x1112 */ - u8 fc_gmd_pb14; /* 0x1113 */ - u8 fc_gmd_pb15; /* 0x1114 */ - u8 fc_gmd_pb16; /* 0x1115 */ - u8 fc_gmd_pb17; /* 0x1116 */ - u8 fc_gmd_pb18; /* 0x1117 */ - u8 fc_gmd_pb19; /* 0x1118 */ - u8 fc_gmd_pb20; /* 0x1119 */ - u8 fc_gmd_pb21; /* 0x111a */ - u8 fc_gmd_pb22; /* 0x111b */ - u8 fc_gmd_pb23; /* 0x111c */ - u8 fc_gmd_pb24; /* 0x111d */ - u8 fc_gmd_pb25; /* 0x111e */ - u8 fc_gmd_pb26; /* 0x111f */ - u8 fc_gmd_pb27; /* 0x1120 */ - u8 reserved11[0xdf]; - u8 fc_dbgforce; /* 0x1200 */ - u8 fc_dbgaud0ch0; /* 0x1201 */ - u8 fc_dbgaud1ch0; /* 0x1202 */ - u8 fc_dbgaud2ch0; /* 0x1203 */ - u8 fc_dbgaud0ch1; /* 0x1204 */ - u8 fc_dbgaud1ch1; /* 0x1205 */ - u8 fc_dbgaud2ch1; /* 0x1206 */ - u8 fc_dbgaud0ch2; /* 0x1207 */ - u8 fc_dbgaud1ch2; /* 0x1208 */ - u8 fc_dbgaud2ch2; /* 0x1209 */ - u8 fc_dbgaud0ch3; /* 0x120a */ - u8 fc_dbgaud1ch3; /* 0x120b */ - u8 fc_dbgaud2ch3; /* 0x120c */ - u8 fc_dbgaud0ch4; /* 0x120d */ - u8 fc_dbgaud1ch4; /* 0x120e */ - u8 fc_dbgaud2ch4; /* 0x120f */ - u8 fc_dbgaud0ch5; /* 0x1210 */ - u8 fc_dbgaud1ch5; /* 0x1211 */ - u8 fc_dbgaud2ch5; /* 0x1212 */ - u8 fc_dbgaud0ch6; /* 0x1213 */ - u8 fc_dbgaud1ch6; /* 0x1214 */ - u8 fc_dbgaud2ch6; /* 0x1215 */ - u8 fc_dbgaud0ch7; /* 0x1216 */ - u8 fc_dbgaud1ch7; /* 0x1217 */ - u8 fc_dbgaud2ch7; /* 0x1218 */ - u8 fc_dbgtmds0; /* 0x1219 */ - u8 fc_dbgtmds1; /* 0x121a */ - u8 fc_dbgtmds2; /* 0x121b */ - u8 reserved12[0x1de4]; - /* Hdmi Source Phy Registers */ - u8 phy_conf0; /* 0x3000 */ - u8 phy_tst0; /* 0x3001 */ - u8 phy_tst1; /* 0x3002 */ - u8 phy_tst2; /* 0x3003 */ - u8 phy_stat0; /* 0x3004 */ - u8 phy_int0; /* 0x3005 */ - u8 phy_mask0; /* 0x3006 */ - u8 phy_pol0; /* 0x3007 */ - u8 reserved13[0x18]; - /* Hdmi Master Phy Registers */ - u8 phy_i2cm_slave_addr; /* 0x3020 */ - u8 phy_i2cm_address_addr; /* 0x3021 */ - u8 phy_i2cm_datao_1_addr; /* 0x3022 */ - u8 phy_i2cm_datao_0_addr; /* 0x3023 */ - u8 phy_i2cm_datai_1_addr; /* 0x3024 */ - u8 phy_i2cm_datai_0_addr; /* 0x3025 */ - u8 phy_i2cm_operation_addr; /* 0x3026 */ - u8 phy_i2cm_int_addr; /* 0x3027 */ - u8 phy_i2cm_ctlint_addr; /* 0x3028 */ - u8 phy_i2cm_div_addr; /* 0x3029 */ - u8 phy_i2cm_softrstz_addr; /* 0x302a */ - u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */ - u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */ - u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */ - u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */ - u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */ - u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */ - u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */ - u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */ - u8 reserved14[0xcd]; - /* Audio Sampler Registers */ - u8 aud_conf0; /* 0x3100 */ - u8 aud_conf1; /* 0x3101 */ - u8 aud_int; /* 0x3102 */ - u8 aud_conf2; /* 0x3103 */ - u8 reserved15[0xfc]; - u8 aud_n1; /* 0x3200 */ - u8 aud_n2; /* 0x3201 */ - u8 aud_n3; /* 0x3202 */ - u8 aud_cts1; /* 0x3203 */ - u8 aud_cts2; /* 0x3204 */ - u8 aud_cts3; /* 0x3205 */ - u8 aud_inputclkfs; /* 0x3206 */ - u8 reserved16[0xfb]; - u8 aud_spdifint; /* 0x3302 */ - u8 reserved17[0xfd]; - u8 aud_conf0_hbr; /* 0x3400 */ - u8 aud_hbr_status; /* 0x3401 */ - u8 aud_hbr_int; /* 0x3402 */ - u8 aud_hbr_pol; /* 0x3403 */ - u8 aud_hbr_mask; /* 0x3404 */ - u8 reserved18[0xfb]; - /* - * Generic Parallel Audio Interface Registers - * Not used as GPAUD interface is not enabled in hw - */ - u8 gp_conf0; /* 0x3500 */ - u8 gp_conf1; /* 0x3501 */ - u8 gp_conf2; /* 0x3502 */ - u8 gp_stat; /* 0x3503 */ - u8 gp_int; /* 0x3504 */ - u8 gp_mask; /* 0x3505 */ - u8 gp_pol; /* 0x3506 */ - u8 reserved19[0xf9]; - /* Audio DMA Registers */ - u8 ahb_dma_conf0; /* 0x3600 */ - u8 ahb_dma_start; /* 0x3601 */ - u8 ahb_dma_stop; /* 0x3602 */ - u8 ahb_dma_thrsld; /* 0x3603 */ - u8 ahb_dma_straddr0; /* 0x3604 */ - u8 ahb_dma_straddr1; /* 0x3605 */ - u8 ahb_dma_straddr2; /* 0x3606 */ - u8 ahb_dma_straddr3; /* 0x3607 */ - u8 ahb_dma_stpaddr0; /* 0x3608 */ - u8 ahb_dma_stpaddr1; /* 0x3609 */ - u8 ahb_dma_stpaddr2; /* 0x360a */ - u8 ahb_dma_stpaddr3; /* 0x360b */ - u8 ahb_dma_bstaddr0; /* 0x360c */ - u8 ahb_dma_bstaddr1; /* 0x360d */ - u8 ahb_dma_bstaddr2; /* 0x360e */ - u8 ahb_dma_bstaddr3; /* 0x360f */ - u8 ahb_dma_mblength0; /* 0x3610 */ - u8 ahb_dma_mblength1; /* 0x3611 */ - u8 ahb_dma_stat; /* 0x3612 */ - u8 ahb_dma_int; /* 0x3613 */ - u8 ahb_dma_mask; /* 0x3614 */ - u8 ahb_dma_pol; /* 0x3615 */ - u8 ahb_dma_conf1; /* 0x3616 */ - u8 ahb_dma_buffstat; /* 0x3617 */ - u8 ahb_dma_buffint; /* 0x3618 */ - u8 ahb_dma_buffmask; /* 0x3619 */ - u8 ahb_dma_buffpol; /* 0x361a */ - u8 reserved20[0x9e5]; - /* Main Controller Registers */ - u8 mc_sfrdiv; /* 0x4000 */ - u8 mc_clkdis; /* 0x4001 */ - u8 mc_swrstz; /* 0x4002 */ - u8 mc_opctrl; /* 0x4003 */ - u8 mc_flowctrl; /* 0x4004 */ - u8 mc_phyrstz; /* 0x4005 */ - u8 mc_lockonclock; /* 0x4006 */ - u8 mc_heacphy_rst; /* 0x4007 */ - u8 reserved21[0xf8]; - /* Colorspace Converter Registers */ - u8 csc_cfg; /* 0x4100 */ - u8 csc_scale; /* 0x4101 */ - u8 csc_coef_a1_msb; /* 0x4102 */ - u8 csc_coef_a1_lsb; /* 0x4103 */ - u8 csc_coef_a2_msb; /* 0x4104 */ - u8 csc_coef_a2_lsb; /* 0x4105 */ - u8 csc_coef_a3_msb; /* 0x4106 */ - u8 csc_coef_a3_lsb; /* 0x4107 */ - u8 csc_coef_a4_msb; /* 0x4108 */ - u8 csc_coef_a4_lsb; /* 0x4109 */ - u8 csc_coef_b1_msb; /* 0x410a */ - u8 csc_coef_b1_lsb; /* 0x410b */ - u8 csc_coef_b2_msb; /* 0x410c */ - u8 csc_coef_b2_lsb; /* 0x410d */ - u8 csc_coef_b3_msb; /* 0x410e */ - u8 csc_coef_b3_lsb; /* 0x410f */ - u8 csc_coef_b4_msb; /* 0x4110 */ - u8 csc_coef_b4_lsb; /* 0x4111 */ - u8 csc_coef_c1_msb; /* 0x4112 */ - u8 csc_coef_c1_lsb; /* 0x4113 */ - u8 csc_coef_c2_msb; /* 0x4114 */ - u8 csc_coef_c2_lsb; /* 0x4115 */ - u8 csc_coef_c3_msb; /* 0x4116 */ - u8 csc_coef_c3_lsb; /* 0x4117 */ - u8 csc_coef_c4_msb; /* 0x4118 */ - u8 csc_coef_c4_lsb; /* 0x4119 */ - u8 reserved22[0xee6]; - /* HDCP Encryption Engine Registers */ - u8 a_hdcpcfg0; /* 0x5000 */ - u8 a_hdcpcfg1; /* 0x5001 */ - u8 a_hdcpobs0; /* 0x5002 */ - u8 a_hdcpobs1; /* 0x5003 */ - u8 a_hdcpobs2; /* 0x5004 */ - u8 a_hdcpobs3; /* 0x5005 */ - u8 a_apiintclr; /* 0x5006 */ - u8 a_apiintstat; /* 0x5007 */ - u8 a_apiintmsk; /* 0x5008 */ - u8 a_vidpolcfg; /* 0x5009 */ - u8 a_oesswcfg; /* 0x500a */ - u8 a_timer1setup0; /* 0x500b */ - u8 a_timer1setup1; /* 0x500c */ - u8 a_timer2setup0; /* 0x500d */ - u8 a_timer2setup1; /* 0x500e */ - u8 a_100mscfg; /* 0x500f */ - u8 a_2scfg0; /* 0x5010 */ - u8 a_2scfg1; /* 0x5011 */ - u8 a_5scfg0; /* 0x5012 */ - u8 a_5scfg1; /* 0x5013 */ - u8 a_srmverlsb; /* 0x5014 */ - u8 a_srmvermsb; /* 0x5015 */ - u8 a_srmctrl; /* 0x5016 */ - u8 a_sfrsetup; /* 0x5017 */ - u8 a_i2chsetup; /* 0x5018 */ - u8 a_intsetup; /* 0x5019 */ - u8 a_presetup; /* 0x501a */ - u8 reserved23[0x5]; - u8 a_srm_base; /* 0x5020 */ - u8 reserved24[0x2cdf]; - /* CEC Engine Registers */ - u8 cec_ctrl; /* 0x7d00 */ - u8 cec_stat; /* 0x7d01 */ - u8 cec_mask; /* 0x7d02 */ - u8 cec_polarity; /* 0x7d03 */ - u8 cec_int; /* 0x7d04 */ - u8 cec_addr_l; /* 0x7d05 */ - u8 cec_addr_h; /* 0x7d06 */ - u8 cec_tx_cnt; /* 0x7d07 */ - u8 cec_rx_cnt; /* 0x7d08 */ - u8 reserved25[0x7]; - u8 cec_tx_data0; /* 0x7d10 */ - u8 cec_tx_data1; /* 0x7d11 */ - u8 cec_tx_data2; /* 0x7d12 */ - u8 cec_tx_data3; /* 0x7d13 */ - u8 cec_tx_data4; /* 0x7d14 */ - u8 cec_tx_data5; /* 0x7d15 */ - u8 cec_tx_data6; /* 0x7d16 */ - u8 cec_tx_data7; /* 0x7d17 */ - u8 cec_tx_data8; /* 0x7d18 */ - u8 cec_tx_data9; /* 0x7d19 */ - u8 cec_tx_data10; /* 0x7d1a */ - u8 cec_tx_data11; /* 0x7d1b */ - u8 cec_tx_data12; /* 0x7d1c */ - u8 cec_tx_data13; /* 0x7d1d */ - u8 cec_tx_data14; /* 0x7d1e */ - u8 cec_tx_data15; /* 0x7d1f */ - u8 cec_rx_data0; /* 0x7d20 */ - u8 cec_rx_data1; /* 0x7d21 */ - u8 cec_rx_data2; /* 0x7d22 */ - u8 cec_rx_data3; /* 0x7d23 */ - u8 cec_rx_data4; /* 0x7d24 */ - u8 cec_rx_data5; /* 0x7d25 */ - u8 cec_rx_data6; /* 0x7d26 */ - u8 cec_rx_data7; /* 0x7d27 */ - u8 cec_rx_data8; /* 0x7d28 */ - u8 cec_rx_data9; /* 0x7d29 */ - u8 cec_rx_data10; /* 0x7d2a */ - u8 cec_rx_data11; /* 0x7d2b */ - u8 cec_rx_data12; /* 0x7d2c */ - u8 cec_rx_data13; /* 0x7d2d */ - u8 cec_rx_data14; /* 0x7d2e */ - u8 cec_rx_data15; /* 0x7d2f */ - u8 cec_lock; /* 0x7d30 */ - u8 cec_wkupctrl; /* 0x7d31 */ - u8 reserved26[0xce]; - /* I2C Master Registers (E-DDC) */ - u8 i2cm_slave; /* 0x7e00 */ - u8 i2cmess; /* 0x7e01 */ - u8 i2cm_datao; /* 0x7e02 */ - u8 i2cm_datai; /* 0x7e03 */ - u8 i2cm_operation; /* 0x7e04 */ - u8 i2cm_int; /* 0x7e05 */ - u8 i2cm_ctlint; /* 0x7e06 */ - u8 i2cm_div; /* 0x7e07 */ - u8 i2cm_segaddr; /* 0x7e08 */ - u8 i2cm_softrstz; /* 0x7e09 */ - u8 i2cm_segptr; /* 0x7e0a */ - u8 i2cm_ss_scl_hcnt_1_addr; /* 0x7e0b */ - u8 i2cm_ss_scl_hcnt_0_addr; /* 0x7e0c */ - u8 i2cm_ss_scl_lcnt_1_addr; /* 0x7e0d */ - u8 i2cm_ss_scl_lcnt_0_addr; /* 0x7e0e */ - u8 i2cm_fs_scl_hcnt_1_addr; /* 0x7e0f */ - u8 i2cm_fs_scl_hcnt_0_addr; /* 0x7e10 */ - u8 i2cm_fs_scl_lcnt_1_addr; /* 0x7e11 */ - u8 i2cm_fs_scl_lcnt_0_addr; /* 0x7e12 */ - u8 reserved27[0x1ed]; - /* Random Number Generator Registers (RNG) */ - u8 rng_base; /* 0x8000 */ -}; - -/* - * Register field definitions - */ -enum { -/* IH_FC_INT2 field values */ - HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, - HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_FC_STAT2 field values */ - HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_PHY_STAT0 field values */ - HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, - HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, - HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, - HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, - HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, - HDMI_IH_PHY_STAT0_HPD = 0x1, - -/* IH_MUTE_I2CMPHY_STAT0 field values */ - HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, - HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, - -/* IH_AHBDMAAUD_STAT0 field values */ - HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, - HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, - HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, - HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, - HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, - HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, - -/* IH_MUTE_FC_STAT2 field values */ - HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_MUTE_AHBDMAAUD_STAT0 field values */ - HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, - -/* IH_MUTE field values */ - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, - -/* TX_INVID0 field values */ - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, - HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, - HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, - -/* TX_INSTUFFING field values */ - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, - -/* VP_PR_CD field values */ - HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, - HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, - -/* VP_STUFF field values */ - HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, - HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, - HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, - HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, - HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, - HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, - HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, - HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, - HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, - HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, - HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, - HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, - -/* VP_CONF field values */ - HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, - HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, - HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, - HDMI_VP_CONF_PP_EN_ENMASK = 0x20, - HDMI_VP_CONF_PP_EN_ENABLE = 0x20, - HDMI_VP_CONF_PP_EN_DISABLE = 0x00, - HDMI_VP_CONF_PR_EN_MASK = 0x10, - HDMI_VP_CONF_PR_EN_ENABLE = 0x10, - HDMI_VP_CONF_PR_EN_DISABLE = 0x00, - HDMI_VP_CONF_YCC422_EN_MASK = 0x8, - HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, - HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, - HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, - HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, - HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, - HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, - HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, - HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, - -/* VP_REMAP field values */ - HDMI_VP_REMAP_MASK = 0x3, - HDMI_VP_REMAP_YCC422_24bit = 0x2, - HDMI_VP_REMAP_YCC422_20bit = 0x1, - HDMI_VP_REMAP_YCC422_16bit = 0x0, - -/* FC_INVIDCONF field values */ - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, - HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, - -/* FC_AUDICONF0 field values */ - HDMI_FC_AUDICONF0_CC_OFFSET = 4, - HDMI_FC_AUDICONF0_CC_MASK = 0x70, - HDMI_FC_AUDICONF0_CT_OFFSET = 0, - HDMI_FC_AUDICONF0_CT_MASK = 0xF, - -/* FC_AUDICONF1 field values */ - HDMI_FC_AUDICONF1_SS_OFFSET = 3, - HDMI_FC_AUDICONF1_SS_MASK = 0x18, - HDMI_FC_AUDICONF1_SF_OFFSET = 0, - HDMI_FC_AUDICONF1_SF_MASK = 0x7, - -/* FC_AUDICONF3 field values */ - HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, - HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, - HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, - HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, - HDMI_FC_AUDICONF3_LSV_OFFSET = 0, - HDMI_FC_AUDICONF3_LSV_MASK = 0xF, - -/* FC_AUDSCHNLS0 field values */ - HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, - HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, - HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, - HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, - -/* FC_AUDSCHNLS3-6 field values */ - HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, - HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, - HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, - HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, - HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, - HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, - HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, - HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, - - HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, - HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, - HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, - HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, - HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, - HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, - HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, - HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, - -/* HDMI_FC_AUDSCHNLS7 field values */ - HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, - HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, - -/* HDMI_FC_AUDSCHNLS8 field values */ - HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, - HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, - HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, - HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, - -/* FC_AUDSCONF field values */ - HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, - HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, - -/* FC_STAT2 field values */ - HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_INT2 field values */ - HDMI_FC_INT2_OVERFLOW_MASK = 0x03, - HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_MASK2 field values */ - HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, - HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_PRCONF field values */ - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, - -/* FC_AVICONF0-FC_AVICONF3 field values */ - HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, - HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, - HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, - HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, - HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, - HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, - HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, - HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, - HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, - HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, - - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, - HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, - HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, - HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, - HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, - HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, - - HDMI_FC_AVICONF2_SCALING_MASK = 0x03, - HDMI_FC_AVICONF2_SCALING_NONE = 0x00, - HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, - HDMI_FC_AVICONF2_SCALING_VERT = 0x02, - HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, - HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, - HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, - HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, - HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, - HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, - HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, - HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, - - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, - HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, - HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, - HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, - -/* FC_DBGFORCE field values */ - HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, - HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, - -/* PHY_CONF0 field values */ - HDMI_PHY_CONF0_PDZ_MASK = 0x80, - HDMI_PHY_CONF0_PDZ_OFFSET = 7, - HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, - HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, - HDMI_PHY_CONF0_SPARECTRL = 0x20, - HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, - HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, - HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, - HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, - HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, - HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, - HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, - HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, - HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, - -/* PHY_TST0 field values */ - HDMI_PHY_TST0_TSTCLR_MASK = 0x20, - HDMI_PHY_TST0_TSTCLR_OFFSET = 5, - HDMI_PHY_TST0_TSTEN_MASK = 0x10, - HDMI_PHY_TST0_TSTEN_OFFSET = 4, - HDMI_PHY_TST0_TSTCLK_MASK = 0x1, - HDMI_PHY_TST0_TSTCLK_OFFSET = 0, - -/* PHY_STAT0 field values */ - HDMI_PHY_RX_SENSE3 = 0x80, - HDMI_PHY_RX_SENSE2 = 0x40, - HDMI_PHY_RX_SENSE1 = 0x20, - HDMI_PHY_RX_SENSE0 = 0x10, - HDMI_PHY_HPD = 0x02, - HDMI_PHY_TX_PHY_LOCK = 0x01, - -/* Convenience macro RX_SENSE | HPD */ - HDMI_DVI_STAT = 0xF2, - -/* PHY_I2CM_SLAVE_ADDR field values */ - HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, - HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, - -/* PHY_I2CM_OPERATION_ADDR field values */ - HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, - HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, - -/* HDMI_PHY_I2CM_INT_ADDR */ - HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, - HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, - -/* HDMI_PHY_I2CM_CTLINT_ADDR */ - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, - -/* AUD_CTS3 field values */ - HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, - HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, - HDMI_AUD_CTS3_N_SHIFT_1 = 0, - HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, - HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, - HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, - HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, - HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, - /* note that the CTS3 MANUAL bit has been removed - from our part. Can't set it, will read as 0. */ - HDMI_AUD_CTS3_CTS_MANUAL = 0x10, - HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, - -/* AHB_DMA_CONF0 field values */ - HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, - HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, - HDMI_AHB_DMA_CONF0_HBR = 0x10, - HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, - HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, - HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, - HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, - HDMI_AHB_DMA_CONF0_INCR4 = 0x0, - HDMI_AHB_DMA_CONF0_INCR8 = 0x2, - HDMI_AHB_DMA_CONF0_INCR16 = 0x4, - HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, - -/* HDMI_AHB_DMA_START field values */ - HDMI_AHB_DMA_START_START_OFFSET = 0, - HDMI_AHB_DMA_START_START_MASK = 0x01, - -/* HDMI_AHB_DMA_STOP field values */ - HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, - HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, - -/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ - HDMI_AHB_DMA_DONE = 0x80, - HDMI_AHB_DMA_RETRY_SPLIT = 0x40, - HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, - HDMI_AHB_DMA_ERROR = 0x10, - HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, - HDMI_AHB_DMA_FIFO_FULL = 0x02, - HDMI_AHB_DMA_FIFO_EMPTY = 0x01, - -/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */ - HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, - HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, - -/* MC_CLKDIS field values */ - HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, - HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, - HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, - HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, - HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, - HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, - HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, - -/* MC_SWRSTZ field values */ - HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, - -/* MC_FLOWCTRL field values */ - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, - -/* MC_PHYRSTZ field values */ - HDMI_MC_PHYRSTZ_ASSERT = 0x0, - HDMI_MC_PHYRSTZ_DEASSERT = 0x1, - -/* MC_HEACPHY_RST field values */ - HDMI_MC_HEACPHY_RST_ASSERT = 0x1, - HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, - -/* CSC_CFG field values */ - HDMI_CSC_CFG_INTMODE_MASK = 0x30, - HDMI_CSC_CFG_INTMODE_OFFSET = 4, - HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, - HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, - HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, - HDMI_CSC_CFG_DECMODE_MASK = 0x3, - HDMI_CSC_CFG_DECMODE_OFFSET = 0, - HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, - -/* CSC_SCALE field values */ - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, - HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, - -/* A_HDCPCFG0 field values */ - HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80, - HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80, - HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00, - HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40, - HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40, - HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00, - HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20, - HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20, - HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00, - HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10, - HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10, - HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00, - HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8, - HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8, - HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0, - HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4, - HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4, - HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0, - HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2, - HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2, - HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0, - HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1, - HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1, - HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0, - -/* A_HDCPCFG1 field values */ - HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8, - HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8, - HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0, - HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1, - HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0, - -/* A_VIDPOLCFG field values */ - HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60, - HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5, - HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10, - HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10, - HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0, - HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8, - HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8, - HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0, - HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, - HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, - HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, -}; - -#endif /* __MXC_HDMI_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h deleted file mode 100644 index b55a54c..0000000 --- a/arch/arm/include/asm/arch-mx6/opos6ul.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Armadeus Systems - */ - -#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__ -#define __ARCH_ARM_MX6UL_OPOS6UL_H__ - -int opos6ul_board_late_init(void); - -#endif diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h deleted file mode 100644 index 4bf7dff..0000000 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - */ - -#ifndef __SYS_PROTO_IMX6_ -#define __SYS_PROTO_IMX6_ - -#include <asm/mach-imx/sys_proto.h> -#include <asm/arch/iomux.h> - -#define USBPHY_PWD 0x00000000 - -#define USBPHY_PWD_RXPWDRX (1 << 20) /* receiver block power down */ - -#define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \ - USBPHY_PWD_RXPWDRX)) - -int imx6_pcie_toggle_power(void); -int imx6_pcie_toggle_reset(void); - -/** - * iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins - * - * @param io_vol - the voltage IO level of pins - */ -static inline void iomuxc_set_rgmii_io_voltage(int io_vol) -{ - __raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII); -} - -#endif /* __SYS_PROTO_IMX6_ */ diff --git a/arch/arm/include/asm/arch-mx7/clock.h b/arch/arm/include/asm/arch-mx7/clock.h deleted file mode 100644 index 984bd3f..0000000 --- a/arch/arm/include/asm/arch-mx7/clock.h +++ /dev/null @@ -1,365 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * Author: - * Peng Fan <Peng.Fan@freescale.com> - */ - -#ifndef _ASM_ARCH_CLOCK_H -#define _ASM_ARCH_CLOCK_H - -#include <common.h> -#include <asm/arch/crm_regs.h> - -#ifdef CONFIG_SYS_MX7_HCLK -#define MXC_HCLK CONFIG_SYS_MX7_HCLK -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_SYS_MX7_CLK32 -#define MXC_CLK32 CONFIG_SYS_MX7_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -/* Mainly for compatible to imx common code. */ -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_AXI_CLK, - MXC_DDR_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_I2C_CLK, -}; - -/* PLL supported by i.mx7d */ -enum pll_clocks { - PLL_CORE, /* Core PLL */ - PLL_SYS, /* System PLL*/ - PLL_ENET, /* Enet PLL */ - PLL_AUDIO, /* Audio PLL */ - PLL_VIDEO, /* Video PLL*/ - PLL_DDR, /* Dram PLL */ - PLL_USB, /* USB PLL, fixed at 480MHZ */ -}; - -/* clk src for clock root gen */ -enum clk_root_src { - OSC_24M_CLK, - - PLL_ARM_MAIN_800M_CLK, - - PLL_SYS_MAIN_480M_CLK, - PLL_SYS_MAIN_240M_CLK, - PLL_SYS_MAIN_120M_CLK, - PLL_SYS_PFD0_392M_CLK, - PLL_SYS_PFD0_196M_CLK, - PLL_SYS_PFD1_332M_CLK, - PLL_SYS_PFD1_166M_CLK, - PLL_SYS_PFD2_270M_CLK, - PLL_SYS_PFD2_135M_CLK, - PLL_SYS_PFD3_CLK, - PLL_SYS_PFD4_CLK, - PLL_SYS_PFD5_CLK, - PLL_SYS_PFD6_CLK, - PLL_SYS_PFD7_CLK, - - PLL_ENET_MAIN_500M_CLK, - PLL_ENET_MAIN_250M_CLK, - PLL_ENET_MAIN_125M_CLK, - PLL_ENET_MAIN_100M_CLK, - PLL_ENET_MAIN_50M_CLK, - PLL_ENET_MAIN_40M_CLK, - PLL_ENET_MAIN_25M_CLK, - - PLL_DRAM_MAIN_1066M_CLK, - PLL_DRAM_MAIN_533M_CLK, - - PLL_AUDIO_MAIN_CLK, - PLL_VIDEO_MAIN_CLK, - - PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */ - - EXT_CLK_1, - EXT_CLK_2, - EXT_CLK_3, - EXT_CLK_4, - - REF_1M_CLK, - OSC_32K_CLK, -}; - -/* - * Clock root index - */ -enum clk_root_index { - ARM_A7_CLK_ROOT = 0, - ARM_M4_CLK_ROOT = 1, - ARM_M0_CLK_ROOT = 2, - MAIN_AXI_CLK_ROOT = 16, - DISP_AXI_CLK_ROOT = 17, - ENET_AXI_CLK_ROOT = 18, - NAND_USDHC_BUS_CLK_ROOT = 19, - AHB_CLK_ROOT = 32, - DRAM_PHYM_CLK_ROOT = 48, - DRAM_CLK_ROOT = 49, - DRAM_PHYM_ALT_CLK_ROOT = 64, - DRAM_ALT_CLK_ROOT = 65, - USB_HSIC_CLK_ROOT = 66, - PCIE_CTRL_CLK_ROOT = 67, - PCIE_PHY_CLK_ROOT = 68, - EPDC_PIXEL_CLK_ROOT = 69, - LCDIF_PIXEL_CLK_ROOT = 70, - MIPI_DSI_EXTSER_CLK_ROOT = 71, - MIPI_CSI_WARP_CLK_ROOT = 72, - MIPI_DPHY_REF_CLK_ROOT = 73, - SAI1_CLK_ROOT = 74, - SAI2_CLK_ROOT = 75, - SAI3_CLK_ROOT = 76, - SPDIF_CLK_ROOT = 77, - ENET1_REF_CLK_ROOT = 78, - ENET1_TIME_CLK_ROOT = 79, - ENET2_REF_CLK_ROOT = 80, - ENET2_TIME_CLK_ROOT = 81, - ENET_PHY_REF_CLK_ROOT = 82, - EIM_CLK_ROOT = 83, - NAND_CLK_ROOT = 84, - QSPI_CLK_ROOT = 85, - USDHC1_CLK_ROOT = 86, - USDHC2_CLK_ROOT = 87, - USDHC3_CLK_ROOT = 88, - CAN1_CLK_ROOT = 89, - CAN2_CLK_ROOT = 90, - I2C1_CLK_ROOT = 91, - I2C2_CLK_ROOT = 92, - I2C3_CLK_ROOT = 93, - I2C4_CLK_ROOT = 94, - UART1_CLK_ROOT = 95, - UART2_CLK_ROOT = 96, - UART3_CLK_ROOT = 97, - UART4_CLK_ROOT = 98, - UART5_CLK_ROOT = 99, - UART6_CLK_ROOT = 100, - UART7_CLK_ROOT = 101, - ECSPI1_CLK_ROOT = 102, - ECSPI2_CLK_ROOT = 103, - ECSPI3_CLK_ROOT = 104, - ECSPI4_CLK_ROOT = 105, - PWM1_CLK_ROOT = 106, - PWM2_CLK_ROOT = 107, - PWM3_CLK_ROOT = 108, - PWM4_CLK_ROOT = 109, - FLEXTIMER1_CLK_ROOT = 110, - FLEXTIMER2_CLK_ROOT = 111, - SIM1_CLK_ROOT = 112, - SIM2_CLK_ROOT = 113, - GPT1_CLK_ROOT = 114, - GPT2_CLK_ROOT = 115, - GPT3_CLK_ROOT = 116, - GPT4_CLK_ROOT = 117, - TRACE_CLK_ROOT = 118, - WDOG_CLK_ROOT = 119, - CSI_MCLK_CLK_ROOT = 120, - AUDIO_MCLK_CLK_ROOT = 121, - WRCLK_CLK_ROOT = 122, - IPP_DO_CLKO1 = 123, - IPP_DO_CLKO2 = 124, - - CLK_ROOT_MAX, -}; - -#if (CONFIG_CONS_INDEX == 0) -#define UART_CLK_ROOT UART1_CLK_ROOT -#elif (CONFIG_CONS_INDEX == 1) -#define UART_CLK_ROOT UART2_CLK_ROOT -#elif (CONFIG_CONS_INDEX == 2) -#define UART_CLK_ROOT UART3_CLK_ROOT -#elif (CONFIG_CONS_INDEX == 3) -#define UART_CLK_ROOT UART4_CLK_ROOT -#elif (CONFIG_CONS_INDEX == 4) -#define UART_CLK_ROOT UART5_CLK_ROOT -#elif (CONFIG_CONS_INDEX == 5) -#define UART_CLK_ROOT UART6_CLK_ROOT -#elif (CONFIG_CONS_INDEX == 6) -#define UART_CLK_ROOT UART7_CLK_ROOT -#else -#error "Invalid IMX UART ID for serial console is defined" -#endif - -struct clk_root_setting { - enum clk_root_index root; - u32 setting; -}; - -/* - * CCGR mapping - */ -enum clk_ccgr_index { - CCGR_CPU = 0, - CCGR_M4 = 1, - CCGR_SIM_MAIN = 4, - CCGR_SIM_DISPLAY = 5, - CCGR_SIM_ENET = 6, - CCGR_SIM_M = 7, - CCGR_SIM_S = 8, - CCGR_SIM_WAKEUP = 9, - CCGR_IPMUX1 = 10, - CCGR_IPMUX2 = 11, - CCGR_IPMUX3 = 12, - CCGR_ROM = 16, - CCGR_OCRAM = 17, - CCGR_OCRAM_S = 18, - CCGR_DRAM = 19, - CCGR_RAWNAND = 20, - CCGR_QSPI = 21, - CCGR_WEIM = 22, - CCGR_ADC = 32, - CCGR_ANATOP = 33, - CCGR_SCTR = 34, - CCGR_OCOTP = 35, - CCGR_CAAM = 36, - CCGR_SNVS = 37, - CCGR_RDC = 38, - CCGR_MU = 39, - CCGR_HS = 40, - CCGR_DVFS = 41, - CCGR_QOS = 42, - CCGR_QOS_DISPMIX = 43, - CCGR_QOS_MEGAMIX = 44, - CCGR_CSU = 45, - CCGR_DBGMON = 46, - CCGR_DEBUG = 47, - CCGR_TRACE = 48, - CCGR_SEC_DEBUG = 49, - CCGR_SEMA1 = 64, - CCGR_SEMA2 = 65, - CCGR_PERFMON1 = 68, - CCGR_PERFMON2 = 69, - CCGR_SDMA = 72, - CCGR_CSI = 73, - CCGR_EPDC = 74, - CCGR_LCDIF = 75, - CCGR_PXP = 76, - CCGR_PCIE = 96, - CCGR_MIPI_CSI = 100, - CCGR_MIPI_DSI = 101, - CCGR_MIPI_MEM_PHY = 102, - CCGR_USB_CTRL = 104, - CCGR_USB_HSIC = 105, - CCGR_USB_PHY1 = 106, - CCGR_USB_PHY2 = 107, - CCGR_USDHC1 = 108, - CCGR_USDHC2 = 109, - CCGR_USDHC3 = 110, - CCGR_ENET1 = 112, - CCGR_ENET2 = 113, - CCGR_CAN1 = 116, - CCGR_CAN2 = 117, - CCGR_ECSPI1 = 120, - CCGR_ECSPI2 = 121, - CCGR_ECSPI3 = 122, - CCGR_ECSPI4 = 123, - CCGR_GPT1 = 124, - CCGR_GPT2 = 125, - CCGR_GPT3 = 126, - CCGR_GPT4 = 127, - CCGR_FTM1 = 128, - CCGR_FTM2 = 129, - CCGR_PWM1 = 132, - CCGR_PWM2 = 133, - CCGR_PWM3 = 134, - CCGR_PWM4 = 135, - CCGR_I2C1 = 136, - CCGR_I2C2 = 137, - CCGR_I2C3 = 138, - CCGR_I2C4 = 139, - CCGR_SAI1 = 140, - CCGR_SAI2 = 141, - CCGR_SAI3 = 142, - CCGR_SIM1 = 144, - CCGR_SIM2 = 145, - CCGR_UART1 = 148, - CCGR_UART2 = 149, - CCGR_UART3 = 150, - CCGR_UART4 = 151, - CCGR_UART5 = 152, - CCGR_UART6 = 153, - CCGR_UART7 = 154, - CCGR_WDOG1 = 156, - CCGR_WDOG2 = 157, - CCGR_WDOG3 = 158, - CCGR_WDOG4 = 159, - CCGR_GPIO1 = 160, - CCGR_GPIO2 = 161, - CCGR_GPIO3 = 162, - CCGR_GPIO4 = 163, - CCGR_GPIO5 = 164, - CCGR_GPIO6 = 165, - CCGR_GPIO7 = 166, - CCGR_IOMUX = 168, - CCGR_IOMUX_LPSR = 169, - CCGR_KPP = 170, - - CCGR_SKIP, - CCGR_MAX, -}; - -/* Clock root channel */ -enum clk_root_type { - CCM_CORE_CHANNEL, - CCM_BUS_CHANNEL, - CCM_AHB_CHANNEL, - CCM_DRAM_PHYM_CHANNEL, - CCM_DRAM_CHANNEL, - CCM_IP_CHANNEL, -}; - -#include <asm/arch/clock_slice.h> - -/* - * entry: the clock root index - * type: ccm channel - * src_mux: each entry corresponding to the clock src, detailed info in CCM RM - */ -struct clk_root_map { - enum clk_root_index entry; - enum clk_root_type type; - uint8_t src_mux[8]; -}; - -enum enet_freq { - ENET_25MHZ, - ENET_50MHZ, - ENET_125MHZ, -}; - -u32 get_root_clk(enum clk_root_index clock_id); -u32 mxc_get_clock(enum mxc_clock clk); -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -void clock_init(void); -#ifdef CONFIG_SYS_I2C_MXC -int enable_i2c_clk(unsigned char enable, unsigned i2c_num); -#endif -#ifdef CONFIG_FEC_MXC -int set_clk_enet(enum enet_freq type); -#endif -int set_clk_qspi(void); -int set_clk_nand(void); -#ifdef CONFIG_MXC_OCOTP -void enable_ocotp_clk(unsigned char enable); -#endif -void enable_usboh3_clk(unsigned char enable); -#ifdef CONFIG_IMX_HAB -void hab_caam_clock_enable(unsigned char enable); -#endif -void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq); -void enable_thermal_clk(void); -#endif diff --git a/arch/arm/include/asm/arch-mx7/clock_slice.h b/arch/arm/include/asm/arch-mx7/clock_slice.h deleted file mode 100644 index 9a7c1f8..0000000 --- a/arch/arm/include/asm/arch-mx7/clock_slice.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - * - * Author: - * Peng Fan <Peng.Fan@freescale.com> - */ - -#ifndef _ASM_ARCH_CLOCK_SLICE_H -#define _ASM_ARCH_CLOCK_SLICE_H - -enum root_pre_div { - CLK_ROOT_PRE_DIV1 = 0, - CLK_ROOT_PRE_DIV2, - CLK_ROOT_PRE_DIV3, - CLK_ROOT_PRE_DIV4, - CLK_ROOT_PRE_DIV5, - CLK_ROOT_PRE_DIV6, - CLK_ROOT_PRE_DIV7, - CLK_ROOT_PRE_DIV8, -}; - -enum root_post_div { - CLK_ROOT_POST_DIV1 = 0, - CLK_ROOT_POST_DIV2, - CLK_ROOT_POST_DIV3, - CLK_ROOT_POST_DIV4, - CLK_ROOT_POST_DIV5, - CLK_ROOT_POST_DIV6, - CLK_ROOT_POST_DIV7, - CLK_ROOT_POST_DIV8, - CLK_ROOT_POST_DIV9, - CLK_ROOT_POST_DIV10, - CLK_ROOT_POST_DIV11, - CLK_ROOT_POST_DIV12, - CLK_ROOT_POST_DIV13, - CLK_ROOT_POST_DIV14, - CLK_ROOT_POST_DIV15, - CLK_ROOT_POST_DIV16, - CLK_ROOT_POST_DIV17, - CLK_ROOT_POST_DIV18, - CLK_ROOT_POST_DIV19, - CLK_ROOT_POST_DIV20, - CLK_ROOT_POST_DIV21, - CLK_ROOT_POST_DIV22, - CLK_ROOT_POST_DIV23, - CLK_ROOT_POST_DIV24, - CLK_ROOT_POST_DIV25, - CLK_ROOT_POST_DIV26, - CLK_ROOT_POST_DIV27, - CLK_ROOT_POST_DIV28, - CLK_ROOT_POST_DIV29, - CLK_ROOT_POST_DIV30, - CLK_ROOT_POST_DIV31, - CLK_ROOT_POST_DIV32, - CLK_ROOT_POST_DIV33, - CLK_ROOT_POST_DIV34, - CLK_ROOT_POST_DIV35, - CLK_ROOT_POST_DIV36, - CLK_ROOT_POST_DIV37, - CLK_ROOT_POST_DIV38, - CLK_ROOT_POST_DIV39, - CLK_ROOT_POST_DIV40, - CLK_ROOT_POST_DIV41, - CLK_ROOT_POST_DIV42, - CLK_ROOT_POST_DIV43, - CLK_ROOT_POST_DIV44, - CLK_ROOT_POST_DIV45, - CLK_ROOT_POST_DIV46, - CLK_ROOT_POST_DIV47, - CLK_ROOT_POST_DIV48, - CLK_ROOT_POST_DIV49, - CLK_ROOT_POST_DIV50, - CLK_ROOT_POST_DIV51, - CLK_ROOT_POST_DIV52, - CLK_ROOT_POST_DIV53, - CLK_ROOT_POST_DIV54, - CLK_ROOT_POST_DIV55, - CLK_ROOT_POST_DIV56, - CLK_ROOT_POST_DIV57, - CLK_ROOT_POST_DIV58, - CLK_ROOT_POST_DIV59, - CLK_ROOT_POST_DIV60, - CLK_ROOT_POST_DIV61, - CLK_ROOT_POST_DIV62, - CLK_ROOT_POST_DIV63, - CLK_ROOT_POST_DIV64, -}; - -enum root_auto_div { - CLK_ROOT_AUTO_DIV1 = 0, - CLK_ROOT_AUTO_DIV2, - CLK_ROOT_AUTO_DIV4, - CLK_ROOT_AUTO_DIV8, - CLK_ROOT_AUTO_DIV16, -}; - -int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src); -int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); -int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div); -int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); -int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div); -int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div); -int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, - int auto_en); -int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, - int *auto_en); -int clock_get_target_val(enum clk_root_index clock_id, u32 *val); -int clock_set_target_val(enum clk_root_index clock_id, u32 val); -int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, - enum root_post_div post_div, enum clk_root_src clock_src); -int clock_root_enabled(enum clk_root_index clock_id); - -int clock_enable(enum clk_ccgr_index index, bool enable); -#endif diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h deleted file mode 100644 index f3515fa..0000000 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ /dev/null @@ -1,2817 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * Author: - * Peng Fan <Peng.Fan@freescale.com> - */ - -#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__ -#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__ - -#include <asm/arch/imx-regs.h> -#include <asm/io.h> - -#define CCM_GPR0_OFFSET 0x0 -#define CCM_OBSERVE0_OFFSET 0x0400 -#define CCM_SCTRL0_OFFSET 0x0800 -#define CCM_CCGR0_OFFSET 0x4000 -#define CCM_ROOT0_TARGET_OFFSET 0x8000 - -#ifndef __ASSEMBLY__ - -struct mxc_ccm_ccgr { - uint32_t ccgr; - uint32_t ccgr_set; - uint32_t ccgr_clr; - uint32_t ccgr_tog; -}; - -struct mxc_ccm_root_slice { - uint32_t target_root; - uint32_t target_root_set; - uint32_t target_root_clr; - uint32_t target_root_tog; - uint32_t reserved_0[4]; - uint32_t post; - uint32_t post_root_set; - uint32_t post_root_clr; - uint32_t post_root_tog; - uint32_t pre; - uint32_t pre_root_set; - uint32_t pre_root_clr; - uint32_t pre_root_tog; - uint32_t reserved_1[12]; - uint32_t access_ctrl; - uint32_t access_ctrl_root_set; - uint32_t access_ctrl_root_clr; - uint32_t access_ctrl_root_tog; -}; - -/** CCM - Peripheral register structure */ -struct mxc_ccm_reg { - uint32_t gpr0; - uint32_t gpr0_set; - uint32_t gpr0_clr; - uint32_t gpr0_tog; - uint32_t reserved_0[4092]; - struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ - uint32_t reserved_1[3332]; - struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ - -}; - -struct mxc_ccm_anatop_reg { - uint32_t ctrl_24m; /* offset 0x0000 */ - uint32_t ctrl_24m_set; - uint32_t ctrl_24m_clr; - uint32_t ctrl_24m_tog; - uint32_t rcosc_config0; /* offset 0x0010 */ - uint32_t rcosc_config0_set; - uint32_t rcosc_config0_clr; - uint32_t rcosc_config0_tog; - uint32_t rcosc_config1; /* offset 0x0020 */ - uint32_t rcosc_config1_set; - uint32_t rcosc_config1_clr; - uint32_t rcosc_config1_tog; - uint32_t rcosc_config2; /* offset 0x0030 */ - uint32_t rcosc_config2_set; - uint32_t rcosc_config2_clr; - uint32_t rcosc_config2_tog; - uint8_t reserved_0[16]; - uint32_t osc_32k; /* offset 0x0050 */ - uint32_t osc_32k_set; - uint32_t osc_32k_clr; - uint32_t osc_32k_tog; - uint32_t pll_arm; /* offset 0x0060 */ - uint32_t pll_arm_set; - uint32_t pll_arm_clr; - uint32_t pll_arm_tog; - uint32_t pll_ddr; /* offset 0x0070 */ - uint32_t pll_ddr_set; - uint32_t pll_ddr_clr; - uint32_t pll_ddr_tog; - uint32_t pll_ddr_ss; /* offset 0x0080 */ - uint8_t reserved_1[12]; - uint32_t pll_ddr_num; /* offset 0x0090 */ - uint8_t reserved_2[12]; - uint32_t pll_ddr_denom; /* offset 0x00a0 */ - uint8_t reserved_3[12]; - uint32_t pll_480; /* offset 0x00b0 */ - uint32_t pll_480_set; - uint32_t pll_480_clr; - uint32_t pll_480_tog; - uint32_t pfd_480a; /* offset 0x00c0 */ - uint32_t pfd_480a_set; - uint32_t pfd_480a_clr; - uint32_t pfd_480a_tog; - uint32_t pfd_480b; /* offset 0x00d0 */ - uint32_t pfd_480b_set; - uint32_t pfd_480b_clr; - uint32_t pfd_480b_tog; - uint32_t pll_enet; /* offset 0x00e0 */ - uint32_t pll_enet_set; - uint32_t pll_enet_clr; - uint32_t pll_enet_tog; - uint32_t pll_audio; /* offset 0x00f0 */ - uint32_t pll_audio_set; - uint32_t pll_audio_clr; - uint32_t pll_audio_tog; - uint32_t pll_audio_ss; /* offset 0x0100 */ - uint8_t reserved_4[12]; - uint32_t pll_audio_num; /* offset 0x0110 */ - uint8_t reserved_5[12]; - uint32_t pll_audio_denom; /* offset 0x0120 */ - uint8_t reserved_6[12]; - uint32_t pll_video; /* offset 0x0130 */ - uint32_t pll_video_set; - uint32_t pll_video_clr; - uint32_t pll_video_tog; - uint32_t pll_video_ss; /* offset 0x0140 */ - uint8_t reserved_7[12]; - uint32_t pll_video_num; /* offset 0x0150 */ - uint8_t reserved_8[12]; - uint32_t pll_video_denom; /* offset 0x0160 */ - uint8_t reserved_9[12]; - uint32_t clk_misc0; /* offset 0x0170 */ - uint32_t clk_misc0_set; - uint32_t clk_misc0_clr; - uint32_t clk_misc0_tog; - uint32_t clk_rsvd; /* offset 0x0180 */ - uint8_t reserved_10[124]; - uint32_t reg_1p0a; /* offset 0x0200 */ - uint32_t reg_1p0a_set; - uint32_t reg_1p0a_clr; - uint32_t reg_1p0a_tog; - uint32_t reg_1p0d; /* offsest 0x0210 */ - uint32_t reg_1p0d_set; - uint32_t reg_1p0d_clr; - uint32_t reg_1p0d_tog; - uint32_t reg_hsic_1p2; /* offset 0x0220 */ - uint32_t reg_hsic_1p2_set; - uint32_t reg_hsic_1p2_clr; - uint32_t reg_hsic_1p2_tog; - uint32_t reg_lpsr_1p0; /* offset 0x0230 */ - uint32_t reg_lpsr_1p0_set; - uint32_t reg_lpsr_1p0_clr; - uint32_t reg_lpsr_1p0_tog; - uint32_t reg_3p0; /* offset 0x0240 */ - uint32_t reg_3p0_set; - uint32_t reg_3p0_clr; - uint32_t reg_3p0_tog; - uint32_t reg_snvs; /* offset 0x0250 */ - uint32_t reg_snvs_set; - uint32_t reg_snvs_clr; - uint32_t reg_snvs_tog; - uint32_t analog_debug_misc0; /* offset 0x0260 */ - uint32_t analog_debug_misc0_set; - uint32_t analog_debug_misc0_clr; - uint32_t analog_debug_misc0_tog; - uint32_t ref; /* offset 0x0270 */ - uint32_t ref_set; - uint32_t ref_clr; - uint32_t ref_tog; - uint8_t reserved_11[128]; - uint32_t tempsense0; /* offset 0x0300 */ - uint32_t tempsense0_set; - uint32_t tempsense0_clr; - uint32_t tempsense0_tog; - uint32_t tempsense1; /* offset 0x0310 */ - uint32_t tempsense1_set; - uint32_t tempsense1_clr; - uint32_t tempsense1_tog; - uint32_t tempsense_trim; /* offset 0x0320 */ - uint32_t tempsense_trim_set; - uint32_t tempsense_trim_clr; - uint32_t tempsense_trim_tog; - uint32_t lowpwr_ctrl; /* offset 0x0330 */ - uint32_t lowpwr_ctrl_set; - uint32_t lowpwr_ctrl_clr; - uint32_t lowpwr_ctrl_tog; - uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */ - uint32_t snvs_tamper_offset_ctrl_set; - uint32_t snvs_tamper_offset_ctrl_clr; - uint32_t snvs_tamper_offset_ctrl_tog; - uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */ - uint32_t snvs_tamper_pull_ctrl_set; - uint32_t snvs_tamper_pull_ctrl_clr; - uint32_t snvs_tamper_pull_ctrl_tog; - uint32_t snvs_test; /* offset 0x0360 */ - uint32_t snvs_test_set; - uint32_t snvs_test_clr; - uint32_t snvs_test_tog; - uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */ - uint32_t snvs_tamper_trim_ctrl_set; - uint32_t snvs_tamper_trim_ctrl_ctrl; - uint32_t snvs_tamper_trim_ctrl_tog; - uint32_t snvs_misc_ctrl; /* offset 0x0380 */ - uint32_t snvs_misc_ctrl_set; - uint32_t snvs_misc_ctrl_clr; - uint32_t snvs_misc_ctrl_tog; - uint8_t reserved_12[112]; - uint32_t misc; /* offset 0x0400 */ - uint8_t reserved_13[252]; - uint32_t adc0; /* offset 0x0500 */ - uint8_t reserved_14[12]; - uint32_t adc1; /* offset 0x0510 */ - uint8_t reserved_15[748]; - uint32_t digprog; /* offset 0x0800 */ -}; -#endif - -#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17) - -#define ANADIG_PLL_LOCK 0x80000000 - -#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12) -#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12) -#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20) -#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) -#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) - - -#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f -#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B -#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 -#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014 - -/* PLL_ARM Bit Fields */ -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80 -#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100 -#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200 -#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400 -#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800 -#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000 -#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000 -#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000 -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000 -#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000 -#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 -#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000 -#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 -#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000 -#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 -#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000 -#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 -#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000 -#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000 -#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 - -/* PLL_DDR Bit Fields */ -#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F -#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80 -#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100 -#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200 -#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400 -#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800 -#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000 -#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 -#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000 -#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000 -#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000 -#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000 -#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000 -#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000 -#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 -#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000 -#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 -#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000 -#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 -#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000 -#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 -#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000 -#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 - -/* PLL_480 Bit Fields */ -#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1 -#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE -#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 -#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10 -#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 -#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20 -#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 -#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40 -#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 -#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80 -#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100 -#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200 -#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400 -#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800 -#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000 -#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000 -#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000 -#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000 -#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000 -#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 -#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000 -#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 -#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000 -#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 -#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000 -#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 -#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000 -#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 -#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000 -#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 -#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000 -#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 -#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000 -#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000 -#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 -#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000 -#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 -#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000 -#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 -#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000 -#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 -#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000 -#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 -#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000 -#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 - -/* PFD_480A Bit Fields */ -#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F -#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 -#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40 -#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 -#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80 -#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 -#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00 -#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 -#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000 -#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 -#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000 -#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 -#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000 -#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 -#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000 -#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 -#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000 -#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 -#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000 -#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 -#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000 -#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 -#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000 -#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 -/* PFD_480B Bit Fields */ -#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F -#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 -#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40 -#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 -#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80 -#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 -#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00 -#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 -#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000 -#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 -#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000 -#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 -#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000 -#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 -#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000 -#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 -#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000 -#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 -#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000 -#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 -#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000 -#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 -#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000 -#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 - -/* PLL_ENET Bit Fields */ -#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1 -#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 -#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2 -#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 -#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4 -#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 -#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8 -#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 -#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10 -#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 -#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20 -#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000 -#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 -#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000 -#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000 -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000 -#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000 -#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000 -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000 -#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 -#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000 -#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 - -/* PLL_AUDIO Bit Fields */ -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK) -#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 -/* PLL_AUDIO_SET Bit Fields */ -#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 -/* PLL_AUDIO_CLR Bit Fields */ -#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 -/* PLL_AUDIO_TOG Bit Fields */ -#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 -/* PLL_AUDIO_SS Bit Fields */ -#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu -#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0 -#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK) -#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u -#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15 -#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u -#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16 -#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK) -/* PLL_AUDIO_NUM Bit Fields */ -#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu -#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 -#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) -#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u -#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30 -#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK) -/* PLL_AUDIO_DENOM Bit Fields */ -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 -#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) -#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u -#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30 -#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK) -/* PLL_VIDEO Bit Fields */ -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK) -#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 -/* PLL_VIDEO_SET Bit Fields */ -#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 -/* PLL_VIDEO_CLR Bit Fields */ -#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 -/* PLL_VIDEO_TOG Bit Fields */ -#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu -#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 -#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u -#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7 -#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u -#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8 -#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u -#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9 -#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u -#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10 -#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u -#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11 -#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u -#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 -#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u -#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13 -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 -#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u -#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17 -#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u -#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 -#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u -#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19 -#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u -#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21 -#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u -#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22 -#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u -#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24 -#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u -#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25 -#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u -#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 -/* PLL_VIDEO_SS Bit Fields */ -#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu -#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0 -#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK) -#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u -#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15 -#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u -#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16 -#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK) -/* PLL_VIDEO_NUM Bit Fields */ -#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu -#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 -#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) -#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u -#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30 -#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK) -/* PLL_VIDEO_DENOM Bit Fields */ -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 -#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) -#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u -#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30 -#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK) -/* CLK_MISC0 Bit Fields */ -#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu -#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0 -#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u -#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5 -#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u -#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6 -#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u -#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7 -#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u -#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8 -#define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK) -/* CLK_MISC0_SET Bit Fields */ -#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu -#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0 -#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u -#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5 -#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u -#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6 -#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u -#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7 -#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u -#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8 -#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK) -/* CLK_MISC0_CLR Bit Fields */ -#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu -#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0 -#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u -#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5 -#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u -#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6 -#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u -#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7 -#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u -#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8 -#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK) -/* CLK_MISC0_TOG Bit Fields */ -#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu -#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0 -#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u -#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5 -#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u -#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6 -#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u -#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7 -#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u -#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8 -#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK) - -/* REG_1P0A Bit Fields */ -#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK) -#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK) -#define PMU_REG_1P0A_RSVD0_MASK 0xE000u -#define PMU_REG_1P0A_RSVD0_SHIFT 13 -#define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK) -#define PMU_REG_1P0A_BO_MASK 0x10000u -#define PMU_REG_1P0A_BO_SHIFT 16 -#define PMU_REG_1P0A_OK_MASK 0x20000u -#define PMU_REG_1P0A_OK_SHIFT 17 -#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0A_REG_TEST_SHIFT 20 -#define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK) -#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u -#define PMU_REG_1P0A_RSVD1_SHIFT 24 -#define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK) -/* REG_1P0A_SET Bit Fields */ -#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK) -#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK) -#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u -#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13 -#define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK) -#define PMU_REG_1P0A_SET_BO_MASK 0x10000u -#define PMU_REG_1P0A_SET_BO_SHIFT 16 -#define PMU_REG_1P0A_SET_OK_MASK 0x20000u -#define PMU_REG_1P0A_SET_OK_SHIFT 17 -#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20 -#define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK) -#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u -#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24 -#define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK) -/* REG_1P0A_CLR Bit Fields */ -#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK) -#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u -#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13 -#define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK) -#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u -#define PMU_REG_1P0A_CLR_BO_SHIFT 16 -#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u -#define PMU_REG_1P0A_CLR_OK_SHIFT 17 -#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20 -#define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK) -#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u -#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24 -#define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK) -/* REG_1P0A_TOG Bit Fields */ -#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK) -#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u -#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13 -#define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK) -#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u -#define PMU_REG_1P0A_TOG_BO_SHIFT 16 -#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u -#define PMU_REG_1P0A_TOG_OK_SHIFT 17 -#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20 -#define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK) -#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u -#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24 -#define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK) -/* REG_1P0D Bit Fields */ -#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK) -#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK) -#define PMU_REG_1P0D_RSVD0_MASK 0xE000u -#define PMU_REG_1P0D_RSVD0_SHIFT 13 -#define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK) -#define PMU_REG_1P0D_BO_MASK 0x10000u -#define PMU_REG_1P0D_BO_SHIFT 16 -#define PMU_REG_1P0D_OK_MASK 0x20000u -#define PMU_REG_1P0D_OK_SHIFT 17 -#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0D_REG_TEST_SHIFT 20 -#define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK) -#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u -#define PMU_REG_1P0D_RSVD1_SHIFT 24 -#define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK) -#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u -#define PMU_REG_1P0D_OVERRIDE_SHIFT 31 -/* REG_1P0D_SET Bit Fields */ -#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK) -#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK) -#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u -#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13 -#define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK) -#define PMU_REG_1P0D_SET_BO_MASK 0x10000u -#define PMU_REG_1P0D_SET_BO_SHIFT 16 -#define PMU_REG_1P0D_SET_OK_MASK 0x20000u -#define PMU_REG_1P0D_SET_OK_SHIFT 17 -#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20 -#define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK) -#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u -#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24 -#define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK) -#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u -#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31 -/* REG_1P0D_CLR Bit Fields */ -#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK) -#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u -#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13 -#define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK) -#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u -#define PMU_REG_1P0D_CLR_BO_SHIFT 16 -#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u -#define PMU_REG_1P0D_CLR_OK_SHIFT 17 -#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20 -#define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK) -#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u -#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24 -#define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK) -#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u -#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31 -/* REG_1P0D_TOG Bit Fields */ -#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u -#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1 -#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u -#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4 -#define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK) -#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u -#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13 -#define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK) -#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u -#define PMU_REG_1P0D_TOG_BO_SHIFT 16 -#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u -#define PMU_REG_1P0D_TOG_OK_SHIFT 17 -#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u -#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20 -#define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK) -#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u -#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24 -#define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK) -#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u -#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31 -/* REG_HSIC_1P2 Bit Fields */ -#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u -#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1 -#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u -#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4 -#define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK) -#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK) -#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u -#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13 -#define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK) -#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u -#define PMU_REG_HSIC_1P2_BO_SHIFT 16 -#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u -#define PMU_REG_HSIC_1P2_OK_SHIFT 17 -#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u -#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20 -#define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK) -#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u -#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24 -#define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK) -#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u -#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31 -/* REG_HSIC_1P2_SET Bit Fields */ -#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u -#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1 -#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u -#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4 -#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK) -#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK) -#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u -#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13 -#define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK) -#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u -#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16 -#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u -#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17 -#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u -#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20 -#define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK) -#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u -#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24 -#define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK) -#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u -#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31 -/* REG_HSIC_1P2_CLR Bit Fields */ -#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u -#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1 -#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u -#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4 -#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK) -#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u -#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13 -#define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK) -#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u -#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16 -#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u -#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17 -#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u -#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20 -#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK) -#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u -#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24 -#define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK) -#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u -#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31 -/* REG_HSIC_1P2_TOG Bit Fields */ -#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u -#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1 -#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u -#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4 -#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK) -#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u -#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13 -#define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK) -#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u -#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16 -#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u -#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17 -#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u -#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20 -#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK) -#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u -#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24 -#define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK) -#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u -#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31 -/* REG_LPSR_1P0 Bit Fields */ -#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u -#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1 -#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u -#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4 -#define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK) -#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK) -#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u -#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13 -#define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK) -#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u -#define PMU_REG_LPSR_1P0_BO_SHIFT 16 -#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u -#define PMU_REG_LPSR_1P0_OK_SHIFT 17 -#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u -#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20 -#define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK) -#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u -#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24 -#define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK) -/* REG_LPSR_1P0_SET Bit Fields */ -#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u -#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1 -#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u -#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4 -#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK) -#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK) -#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u -#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13 -#define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK) -#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u -#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16 -#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u -#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17 -#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u -#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20 -#define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK) -#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u -#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24 -#define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK) -/* REG_LPSR_1P0_CLR Bit Fields */ -#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u -#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1 -#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u -#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4 -#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK) -#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u -#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13 -#define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK) -#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u -#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16 -#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u -#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17 -#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u -#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20 -#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK) -#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u -#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24 -#define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK) -/* REG_LPSR_1P0_TOG Bit Fields */ -#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u -#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1 -#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u -#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3 -#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u -#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4 -#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK) -#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u -#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7 -#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u -#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13 -#define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK) -#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u -#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16 -#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u -#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17 -#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u -#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18 -#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u -#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19 -#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u -#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20 -#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK) -#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u -#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 -#define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK) -/* REG_3P0 Bit Fields */ -#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_RSVD0_MASK 0x8u -#define PMU_REG_3P0_RSVD0_SHIFT 3 -#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) -#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_RSVD1_SHIFT 13 -#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK) -#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK) -#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_RSVD2_SHIFT 22 -#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK) -/* REG_3P0_SET Bit Fields */ -#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u -#define PMU_REG_3P0_SET_RSVD0_SHIFT 3 -#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK) -#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_SET_RSVD1_SHIFT 13 -#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK) -#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK) -#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_SET_RSVD2_SHIFT 22 -#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK) -/* REG_3P0_CLR Bit Fields */ -#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u -#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 -#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK) -#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 -#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK) -#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK) -#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 -#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK) -/* REG_3P0_TOG Bit Fields */ -#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u -#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 -#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK) -#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 -#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK) -#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK) -#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 -#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK) -/* REF Bit Fields */ -#define PMU_REF_REFTOP_PWD_MASK 0x1u -#define PMU_REF_REFTOP_PWD_SHIFT 0 -#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u -#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1 -#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u -#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2 -#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u -#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3 -#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u -#define PMU_REF_REFTOP_VBGADJ_SHIFT 4 -#define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK) -#define PMU_REF_REFTOP_VBGUP_MASK 0x80u -#define PMU_REF_REFTOP_VBGUP_SHIFT 7 -#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u -#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8 -#define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK) -#define PMU_REF_LPBG_SEL_MASK 0x400u -#define PMU_REF_LPBG_SEL_SHIFT 10 -#define PMU_REF_LPBG_TEST_MASK 0x800u -#define PMU_REF_LPBG_TEST_SHIFT 11 -#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u -#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12 -#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u -#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13 -#define PMU_REF_RSVD1_MASK 0xFFFFC000u -#define PMU_REF_RSVD1_SHIFT 14 -#define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK) -/* REF_SET Bit Fields */ -#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u -#define PMU_REF_SET_REFTOP_PWD_SHIFT 0 -#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u -#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1 -#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u -#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2 -#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u -#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3 -#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u -#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4 -#define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK) -#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u -#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7 -#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u -#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8 -#define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK) -#define PMU_REF_SET_LPBG_SEL_MASK 0x400u -#define PMU_REF_SET_LPBG_SEL_SHIFT 10 -#define PMU_REF_SET_LPBG_TEST_MASK 0x800u -#define PMU_REF_SET_LPBG_TEST_SHIFT 11 -#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u -#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12 -#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u -#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13 -#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u -#define PMU_REF_SET_RSVD1_SHIFT 14 -#define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK) -/* REF_CLR Bit Fields */ -#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u -#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0 -#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u -#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1 -#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u -#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2 -#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u -#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3 -#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u -#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4 -#define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK) -#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u -#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7 -#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u -#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8 -#define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK) -#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u -#define PMU_REF_CLR_LPBG_SEL_SHIFT 10 -#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u -#define PMU_REF_CLR_LPBG_TEST_SHIFT 11 -#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u -#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12 -#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u -#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13 -#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u -#define PMU_REF_CLR_RSVD1_SHIFT 14 -#define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK) -/* REF_TOG Bit Fields */ -#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u -#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0 -#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u -#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1 -#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u -#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2 -#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u -#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3 -#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u -#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4 -#define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK) -#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u -#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7 -#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u -#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8 -#define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK) -#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u -#define PMU_REF_TOG_LPBG_SEL_SHIFT 10 -#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u -#define PMU_REF_TOG_LPBG_TEST_SHIFT 11 -#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u -#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12 -#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u -#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13 -#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u -#define PMU_REF_TOG_RSVD1_SHIFT 14 -#define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK) -/* LOWPWR_CTRL Bit Fields */ -#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u -#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0 -#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK) -#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu -#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2 -#define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK) -#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u -#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 -#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u -#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 -#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u -#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 -#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u -#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 -#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u -#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12 -#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u -#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13 -#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u -#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14 -#define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK) -#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u -#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24 -#define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK) -/* LOWPWR_CTRL_SET Bit Fields */ -#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u -#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0 -#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK) -#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu -#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2 -#define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK) -#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u -#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 -#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u -#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 -#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u -#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 -#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u -#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 -#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u -#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12 -#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u -#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13 -#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u -#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14 -#define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK) -#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u -#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24 -#define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK) -/* LOWPWR_CTRL_CLR Bit Fields */ -#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u -#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0 -#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK) -#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu -#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2 -#define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK) -#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u -#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 -#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u -#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 -#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u -#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 -#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u -#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 -#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u -#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12 -#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u -#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13 -#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u -#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14 -#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK) -#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u -#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24 -#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK) -/* LOWPWR_CTRL_TOG Bit Fields */ -#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u -#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0 -#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK) -#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu -#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2 -#define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK) -#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u -#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 -#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u -#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 -#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u -#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 -#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u -#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 -#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u -#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12 -#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u -#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13 -#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u -#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14 -#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK) -#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u -#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 -#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) - - -/* HW_ANADIG_TEMPSENSE0 Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK) -/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK) -/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK) -/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27 -#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK) -/* HW_ANADIG_TEMPSENSE1 Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK) -/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK) -/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) -/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16 -#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) -/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK) -/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK) -/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK) -/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */ -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK) -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 -#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) - - -#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) -#define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) -#define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i)) -#define CCM_CCGR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i)) -#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) - -#define CCM_GPR_SET(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4) -#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) -#define CCM_SCTRL_SET(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) -#define CCM_CCGR_SET(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) -#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) - -#define CCM_GPR_CLR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8) -#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) -#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) -#define CCM_CCGR_CLR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) -#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) - -#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12) -#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) -#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) -#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) -#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) - -#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) -#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i)) -#define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i)) -#define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i)) -#define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i)) - -#define HW_CCM_GPR_RD(i) readl(CCM_GPR(i)) -#define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i)) -#define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i)) -#define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i)) -#define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i)) - -#define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i)) -#define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i)) -#define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i)) -#define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i)) -#define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i)) - -#define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i)) -#define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i)) -#define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i)) -#define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i)) -#define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i)) - -#define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i)) -#define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i)) -#define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i)) -#define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i)) -#define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i)) - -#define CCM_CLK_ON_MSK 0x03 -#define CCM_CLK_ON_N_N 0x00 /* Domain clocks not needed */ -#define CCM_CLK_ON_R_W 0x02 /* Domain clocks needed when in RUN and WAIT */ - -/* CCGR Mapping */ -#define CCGR_IDX_DDR 19 /* CCM_CCGR19 */ - -#define CCM_ROOT_TGT_POST_DIV_SHIFT 0 -#define CCM_ROOT_TGT_PRE_DIV_SHIFT 15 -#define CCM_ROOT_TGT_MUX_SHIFT 24 -#define CCM_ROOT_TGT_ENABLE_SHIFT 28 -#define CCM_ROOT_TGT_POST_DIV_MSK 0x3F -#define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT) -#define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT) -#define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT) - -#define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK) -#define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK) -#define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK) - -/* - * Field values definition for clock slice TARGET register - */ - -#define CLK_ROOT_ON 0x10000000 -#define CLK_ROOT_OFF 0x0 -#define CLK_ROOT_ENABLE_MASK 0x10000000 -#define CLK_ROOT_ENABLE_SHIFT 28 - -#define CLK_ROOT_ALT0 0x00000000 -#define CLK_ROOT_ALT1 0x01000000 -#define CLK_ROOT_ALT2 0x02000000 -#define CLK_ROOT_ALT3 0x03000000 -#define CLK_ROOT_ALT4 0x04000000 -#define CLK_ROOT_ALT5 0x05000000 -#define CLK_ROOT_ALT6 0x06000000 -#define CLK_ROOT_ALT7 0x07000000 - - -#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 -#define CLK_ROOT_POST_DIV_MASK 0x0000003f -#define CLK_ROOT_POST_DIV_SHIFT 0 -#define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK) - -#define CLK_ROOT_AUTO_DIV_MASK 0x00000700 -#define CLK_ROOT_AUTO_DIV_SHIFT 8 -#define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK) - -#define CLK_ROOT_AUTO_EN_MASK 0x00001000 -#define CLK_ROOT_AUTO_EN 0x00001000 - -#define CLK_ROOT_PRE_DIV_MASK 0x00070000 -#define CLK_ROOT_PRE_DIV_SHIFT 16 -#define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK) - -#define CLK_ROOT_MUX_MASK 0x07000000 -#define CLK_ROOT_MUX_SHIFT 24 - -#define CLK_ROOT_EN_MASK 0x10000000 - -#define CLK_ROOT_AUTO_ON 0x00001000 -#define CLK_ROOT_AUTO_OFF 0x0 - -/* ARM_A7_CLK_ROOT */ -#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000 -#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000 -#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 -#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 -#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* ARM_M4_CLK_ROOT */ -#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 -#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 -#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000 -#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* ARM_M0_CLK_ROOT */ -#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 -#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000 -#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000 -#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* MAIN_AXI_CLK_ROOT */ -#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 -#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 -#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 -#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 - -/* DISP_AXI_CLK_ROOT */ -#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 -#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000 -#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 -#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 -#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 - -/* ENET_AXI_CLK_ROOT */ -#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 - -/* NAND_USDHC_BUS_CLK_ROOT */ -#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000 -#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 -#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000 -#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 -#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 -#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 - -/* AHB_CLK_ROOT */ -#define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 -#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 -#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 - -/* DRAM_PHYM_CLK_ROOT */ -#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 -#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000 - -/* DRAM_CLK_ROOT */ -#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 -#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000 - -/* DRAM_PHYM_ALT_CLK_ROOT */ -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 - -/* DRAM_ALT_CLK_ROOT */ -#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 -#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 -#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 -#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000 -#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 -#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000 -#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 - -/* USB_HSIC_CLK_ROOT */ -#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 -#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000 -#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 -#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000 -#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 -#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000 - -/* PCIE_CTRL_CLK_ROOT */ -#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 -#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 -#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000 -#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 -#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000 -#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 -#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000 - -/* PCIE_PHY_CLK_ROOT */ -#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000 -#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 -#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 -#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 -#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 -#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 - -/* EPDC_PIXEL_CLK_ROOT */ -#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 -#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 -#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 -#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 -#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000 -#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 - -/* LCDIF_PIXEL_CLK_ROOT */ -#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 -#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 -#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 -#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000 - -/* MIPI_DSI_EXTSER_CLK_ROOT */ -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 -#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 - -/* MIPI_CSI_WARP_CLK_ROOT */ -#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 -#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 -#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 -#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 -#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 -#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 -#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 - -/* MIPI_DPHY_REF_CLK_ROOT */ -#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000 -#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000 -#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 - -/* SAI1_CLK_ROOT */ -#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 -#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 -#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 - -/* SAI2_CLK_ROOT */ -#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 -#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 -#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 - -/* SAI3_CLK_ROOT */ -#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 -#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 -#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 - -/* SPDIF_CLK_ROOT */ -#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 -#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 -#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 - -/* ENET1_REF_CLK_ROOT */ -#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 - -/* ENET1_TIME_CLK_ROOT */ -#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 -#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 -#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 -#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 -#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 - -/* ENET2_REF_CLK_ROOT */ -#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 -#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 -#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 -#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 - -/* ENET2_TIME_CLK_ROOT */ -#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 -#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 -#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 -#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 -#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 - -/* ENET_PHY_REF_CLK_ROOT */ -#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 - -/* EIM_CLK_ROOT */ -#define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000 -#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000 -#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 -#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* NAND_CLK_ROOT */ -#define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 -#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 -#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 -#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 -#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 -#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 - -/* QSPI_CLK_ROOT */ -#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 -#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 -#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 -#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 -#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 - -/* USDHC1_CLK_ROOT */ -#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 -#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 -#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 -#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 -#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 - -/* USDHC2_CLK_ROOT */ -#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 -#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 -#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 -#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 -#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 - -/* USDHC3_CLK_ROOT */ -#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 -#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 -#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 -#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 -#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 - -/* CAN1_CLK_ROOT */ -#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 -#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 -#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 -#define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 -#define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 - -/* CAN2_CLK_ROOT */ -#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 -#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 -#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 -#define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 -#define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 - -/* I2C1_CLK_ROOT */ -#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 -#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 -#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 - -/* I2C2_CLK_ROOT */ -#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 -#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 -#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 - -/* I2C3_CLK_ROOT */ -#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 -#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 -#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 - -/* I2C4_CLK_ROOT */ -#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 -#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 -#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 -#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 -#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 - -/* UART1_CLK_ROOT */ -#define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 -#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 - -/* UART2_CLK_ROOT */ -#define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 -#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 - -/* UART3_CLK_ROOT */ -#define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 -#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 - -/* UART4_CLK_ROOT */ -#define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 -#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 - -/* UART5_CLK_ROOT */ -#define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 -#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 - -/* UART6_CLK_ROOT */ -#define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 -#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 - -/* UART7_CLK_ROOT */ -#define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 -#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 -#define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 -#define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 - -/* ECSPI1_CLK_ROOT */ -#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 -#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 -#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* ECSPI2_CLK_ROOT */ -#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 -#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 -#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* ECSPI3_CLK_ROOT */ -#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 -#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 -#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* ECSPI4_CLK_ROOT */ -#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 -#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 -#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 -#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 -#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 -#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* PWM1_CLK_ROOT */ -#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 -#define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 - -/* PWM2_CLK_ROOT */ -#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 -#define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 - -/* PWM3_CLK_ROOT */ -#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 -#define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 - -/* PWM4_CLK_ROOT */ -#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 -#define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 - -/* FLEXTIMER1_CLK_ROOT */ -#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 -#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 - -/* FLEXTIMER2_CLK_ROOT */ -#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 -#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 -#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 -#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 - -/* SIM1_CLK_ROOT */ -#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 -#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 - -/* SIM2_CLK_ROOT */ -#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 -#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 -#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 - -/* GPT1_CLK_ROOT */ -#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 -#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 -#define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000 - -/* GPT2_CLK_ROOT */ -#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 -#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 -#define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 - -/* GPT3_CLK_ROOT */ -#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 -#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 -#define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 - -/* GPT4_CLK_ROOT */ -#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 -#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 -#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 -#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 -#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 -#define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 -#define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 - -/* TRACE_CLK_ROOT */ -#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 -#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 -#define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 -#define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 - -/* WDOG_CLK_ROOT */ -#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000 -#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 -#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 -#define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 - -/* CSI_MCLK_CLK_ROOT */ -#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 -#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* AUDIO_MCLK_CLK_ROOT */ -#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 -#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 -#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 -#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 -#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 - -/* WRCLK_CLK_ROOT */ -#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 -#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 -#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 -#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 -#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 -#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000 -#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000 -#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000 - -/* IPP_DO_CLKO1 */ -#define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000 -#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000 -#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 -#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 -#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000 -#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000 -#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 -#define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000 - -/* IPP_DO_CLKO2 */ -#define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000 -#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 -#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 -#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000 -#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000 -#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 -#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 -#define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000 - -#endif diff --git a/arch/arm/include/asm/arch-mx7/gpio.h b/arch/arm/include/asm/arch-mx7/gpio.h deleted file mode 100644 index 1da66a4..0000000 --- a/arch/arm/include/asm/arch-mx7/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX7_GPIO_H -#define __ASM_ARCH_MX7_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif /* __ASM_ARCH_MX7_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx7/imx-rdc.h b/arch/arm/include/asm/arch-mx7/imx-rdc.h deleted file mode 100644 index 3512ddb..0000000 --- a/arch/arm/include/asm/arch-mx7/imx-rdc.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __IMX_RDC_H__ -#define __IMX_RDC_H__ - -#if defined(CONFIG_MX7D) -#include "mx7d_rdc.h" -#else -#error "Please select cpu" -#endif /* CONFIG_MX7D */ - -#endif /* __IMX_RDC_H__*/ diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h deleted file mode 100644 index 6336514..0000000 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ /dev/null @@ -1,1227 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MX7_IMX_REGS_H__ -#define __ASM_ARCH_MX7_IMX_REGS_H__ - -#define ARCH_MXC - -#define ROM_SW_INFO_ADDR 0x000001E8 -#define ROMCP_ARB_BASE_ADDR 0x00000000 -#define ROMCP_ARB_END_ADDR 0x00017FFF -#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00107FFF -#define GIC400_ARB_BASE_ADDR 0x31000000 -#define GIC400_ARB_END_ADDR 0x31007FFF -#define APBH_DMA_ARB_BASE_ADDR 0x33000000 -#define APBH_DMA_ARB_END_ADDR 0x33007FFF -#define M4_BOOTROM_BASE_ADDR 0x00180000 - -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) - -/* GPV - PL301 configuration ports */ -#define GPV0_BASE_ADDR 0x32000000 -#define GPV1_BASE_ADDR 0x32100000 -#define GPV2_BASE_ADDR 0x32200000 -#define GPV3_BASE_ADDR 0x32300000 -#define GPV4_BASE_ADDR 0x32400000 -#define GPV5_BASE_ADDR 0x32500000 -#define GPV6_BASE_ADDR 0x32600000 -#define GPV7_BASE_ADDR 0x32700000 - -#define OCRAM_ARB_BASE_ADDR 0x00900000 -#define OCRAM_ARB_END_ADDR 0x0091FFFF -#define OCRAM_EPDC_BASE_ADDR 0x00920000 -#define OCRAM_EPDC_END_ADDR 0x0093FFFF -#define OCRAM_PXP_BASE_ADDR 0x00940000 -#define OCRAM_PXP_END_ADDR 0x00947FFF -#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR -#define IRAM_SIZE 0x00020000 - -#define AIPS1_ARB_BASE_ADDR 0x30000000 -#define AIPS1_ARB_END_ADDR 0x303FFFFF -#define AIPS2_ARB_BASE_ADDR 0x30400000 -#define AIPS2_ARB_END_ADDR 0x307FFFFF -#define AIPS3_ARB_BASE_ADDR 0x30800000 -#define AIPS3_ARB_END_ADDR 0x30BFFFFF - -#define WEIM_ARB_BASE_ADDR 0x28000000 -#define WEIM_ARB_END_ADDR 0x2FFFFFFF - -#define QSPI0_ARB_BASE_ADDR 0x60000000 -#define QSPI0_ARB_END_ADDR 0x6FFFFFFF -#define PCIE_ARB_BASE_ADDR 0x40000000 -#define PCIE_ARB_END_ADDR 0x4FFFFFFF -#define PCIE_REG_BASE_ADDR 0x33800000 -#define PCIE_REG_END_ADDR 0x33803FFF - -#define MMDC0_ARB_BASE_ADDR 0x80000000 -#define MMDC0_ARB_END_ADDR 0xBFFFFFFF -#define MMDC1_ARB_BASE_ADDR 0xC0000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF - -/* Cortex-A9 MPCore private memory region */ -#define ARM_PERIPHBASE 0x31000000 -#define SCU_BASE_ADDR ARM_PERIPHBASE -#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) -#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) - - -/* Defines for Blocks connected via AIPS (SkyBlue) */ -#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR -#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR -#define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR - -/* DAP base-address */ -#define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR - -/* AIPS_TZ#1- On Platform */ -#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) -/* AIPS_TZ#1- Off Platform */ -#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) - -#define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR -#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) -#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) -#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) -#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) -#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) -#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) -#define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) -#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) -#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) -#define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) -#define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) -#define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) -#define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) -#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR -#define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) -#define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) -#define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) -#define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) -#define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) -#define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) -#define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR -#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) -#define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) -#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) -#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) -#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) -#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) -#define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) -#define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) -#define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) -#define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) -#define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) - -/* AIPS_TZ#2- On Platform */ -#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) -/* AIPS_TZ#2- Off Platform */ -#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) -#define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) -#define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) -#define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) -#define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) -#define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) -#define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) -#define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) -#define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) -#define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) -#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) -#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) -#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) -#define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) -#define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) -#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR -#define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) -#define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) -#define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) -#define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) -#define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) -#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) -#define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) -#define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) -#define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) -#define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) -#define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) -#define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) - -/* AIPS_TZ#3 - Global enable (0) */ -#define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) -#define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) -#define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) -#define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) -#define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) -#define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) -#define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) -#define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) -#define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) -#define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) -#define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) - -/* AIPS_TZ#3- On Platform */ -#define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) -/* AIPS_TZ#3- Off Platform */ -#define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) -#define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR -#define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) -#define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) -#define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) -#define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) -#define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) -#define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) -#define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) -#define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) -#define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) -#define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) -#define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) -#define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) -#define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) -#define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) -#define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) -#define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) -#define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) -#define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) -#define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) -#define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) -#define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) -#define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) -#define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) -#define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) -#define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) -#define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) -#define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) -#define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) - -#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR -#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR -#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR - -#define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR -#define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR - -#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR -#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR - -#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR -#define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR -#define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR -#define RDC_BASE_ADDR RDC_IPS_BASE_ADDR - -#define FEC_QUIRK_ENET_MAC -#define SNVS_LPGPR 0x68 -#define CONFIG_SYS_FSL_SEC_OFFSET 0 -#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ - CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ - CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/mach-imx/regs-lcdif.h> -#include <asm/types.h> - -extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 a7rcr0; - u32 a7rcr1; - u32 m4rcr; - u32 reserved1; - u32 ercr; - u32 reserved2; - u32 hsicphy_rcr; - u32 usbophy1_rcr; - u32 usbophy2_rcr; - u32 mipiphy_rcr; - u32 pciephy_rcr; - u32 reserved3[10]; - u32 sbmr1; - u32 srsr; - u32 reserved4[2]; - u32 sisr; - u32 simr; - u32 sbmr2; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 gpr8; - u32 gpr9; - u32 gpr10; - u32 reserved5[985]; - u32 ddrc_rcr; -}; - -#define src_base ((struct src *)SRC_BASE_ADDR) - -#define SRC_M4_REG_OFFSET 0xC -#define SRC_M4C_NON_SCLR_RST_OFFSET 0 -#define SRC_M4C_NON_SCLR_RST_MASK BIT(0) -#define SRC_M4_ENABLE_OFFSET 3 -#define SRC_M4_ENABLE_MASK BIT(3) - -#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 -#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1) - -/* GPR0 Bit Fields */ -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u -#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 -#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7) -#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7 -/* GPR1 Bit Fields */ -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK) -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK) -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK) -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK) -#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u -#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 -#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u -#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 -#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u -#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 -#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u -#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 -#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u -#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 -#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u -#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 -#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u -#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 -#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u -#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 -#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u -#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 -#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u -#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 -#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) -#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u -#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 -/* GPR2 Bit Fields */ -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 -#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u -#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 -#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK) -#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u -#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 -#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u -#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 -#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u -#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 -/* GPR3 Bit Fields */ -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 -/* GPR4 Bit Fields */ -#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u -#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 -#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u -#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 -#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u -#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 -#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u -#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 -#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u -#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 -#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u -#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 -#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u -#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 -#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u -#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 -#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u -#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 -#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u -#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 -#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u -#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 -#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u -#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 -#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u -#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 -#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u -#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 -#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u -#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 -#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u -#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK) -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK) -/* GPR5 Bit Fields */ -#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u -#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 -#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u -#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 -#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u -#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 -#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u -#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 -#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u -#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 -#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u -#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 -#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u -#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 -#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u -#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 -#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u -#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 -#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u -#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 -#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u -#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 -/* GPR6 Bit Fields */ -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 -/* GPR7 Bit Fields */ -#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u -#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 -#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u -#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 -#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u -#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 -#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u -#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 -#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u -#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 -#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK) -#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u -#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 -#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u -#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 -#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u -#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 -#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u -#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 -#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u -#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 -#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK) -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 -/* GPR8 Bit Fields */ -#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u -#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 -#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK) -#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u -#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 -/* GPR9 Bit Fields */ -#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u -#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 -#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu -#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 -#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK) -/* GPR10 Bit Fields */ -#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u -#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 -#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u -#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 -#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u -#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK) -/* GPR11 Bit Fields */ -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK) -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) -/* GPR12 Bit Fields */ -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK) -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK) -/* GPR13 Bit Fields */ -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK) -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 -/* GPR14 Bit Fields */ -#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u -#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 -#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u -#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 -/* GPR15 Bit Fields */ -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK) -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK) -/* GPR16 Bit Fields */ -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u -#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 -#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u -#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 -#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 -#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 -#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 -#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 -/* GPR17 Bit Fields */ -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK) -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK) -/* GPR18 Bit Fields */ -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 -#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 -#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 -/* GPR19 Bit Fields */ -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK) -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 -#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u -#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 -/* GPR20 Bit Fields */ -#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu -#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 -#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK) -#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u -#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 -#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK) -#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 -#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK) -#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 -#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 -#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 -#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK) -/* GPR21 Bit Fields */ -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK) -#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u -#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 -#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u -#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 -/* GPR22 Bit Fields */ -#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u -#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 -#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK) -#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u -#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 -#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u -#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 -#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u -#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 -#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u -#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 -#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u -#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 -#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u -#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 -#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u -#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 - -#define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4) -#define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4) -#define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4) - -struct iomuxc { - u32 gpr[23]; - /* mux and pad registers */ -}; - -struct iomuxc_gpr_base_regs { - u32 gpr[23]; /* 0x000 */ -}; - -/* ECSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 cfg; - u32 intr; - u32 dma; - u32 stat; - u32 period; -}; - -/* - * CSPI register definitions - */ -#define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_MODE_MASK (0xf << 4) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_PHA 0 /* SCLK phase control */ -#define MXC_CSPICON_POL 4 /* SCLK polarity */ -#define MXC_CSPICON_SSPOL 12 /* SS polarity */ -#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ - -#define MXC_SPI_BASE_ADDRESSES \ - ECSPI1_BASE_ADDR, \ - ECSPI2_BASE_ADDR, \ - ECSPI3_BASE_ADDR, \ - ECSPI4_BASE_ADDR - -#define CSU_INIT_SEC_LEVEL0 0x00FF00FF -#define CSU_NUM_REGS 64 - -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data0; - u32 rsvd1[3]; - u32 data1; - u32 rsvd2[3]; - u32 data2; - u32 rsvd3[3]; - u32 data3; - u32 rsvd4[3]; - u32 read_ctrl; - u32 rsvd5[3]; - u32 read_fuse_data0; - u32 rsvd6[3]; - u32 read_fuse_data1; - u32 rsvd7[3]; - u32 read_fuse_data2; - u32 rsvd8[3]; - u32 read_fuse_data3; - u32 rsvd9[3]; - u32 sw_sticky; - u32 rsvd10[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd11[3]; - u32 crc_value; - u32 rsvd12[3]; - u32 version; - u32 rsvd13[0xc3]; - - struct fuse_bank { /* offset 0x400 */ - u32 fuse_regs[0x10]; - } bank[16]; -}; - -struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 tester0; - u32 rsvd1[3]; - u32 tester1; - u32 rsvd2[3]; - u32 tester2; - u32 rsvd3[3]; -}; - -struct fuse_bank1_regs { - u32 tester3; - u32 rsvd0[3]; - u32 tester4; - u32 rsvd1[3]; - u32 tester5; - u32 rsvd2[3]; - u32 cfg0; - u32 rsvd3[3]; -}; - -struct fuse_bank2_regs { - u32 cfg1; - u32 rsvd0[3]; - u32 cfg2; - u32 rsvd1[3]; - u32 cfg3; - u32 rsvd2[3]; - u32 cfg4; - u32 rsvd3[3]; -}; - -struct fuse_bank3_regs { - u32 mem_trim0; - u32 rsvd0[3]; - u32 mem_trim1; - u32 rsvd1[3]; - u32 ana0; - u32 rsvd2[3]; - u32 ana1; - u32 rsvd3[3]; -}; - -struct fuse_bank8_regs { - u32 sjc_resp_low; - u32 rsvd0[3]; - u32 sjc_resp_high; - u32 rsvd1[3]; - u32 usb_id; - u32 rsvd2[3]; - u32 field_return; - u32 rsvd3[3]; -}; - -struct fuse_bank9_regs { - u32 mac_addr0; - u32 rsvd0[3]; - u32 mac_addr1; - u32 rsvd1[3]; - u32 mac_addr2; - u32 rsvd2[7]; -}; - -struct aipstz_regs { - u32 mprot0; - u32 mprot1; - u32 rsvd[0xe]; - u32 opacr0; - u32 opacr1; - u32 opacr2; - u32 opacr3; - u32 opacr4; -}; - -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Miscellaneous Control */ -}; - -struct dbg_monitor_regs { - u32 ctrl[4]; /* Control */ - u32 master_en[4]; /* Master enable */ - u32 irq[4]; /* IRQ */ - u32 trap_addr_low[4]; /* Trap address low */ - u32 trap_addr_high[4]; /* Trap address high */ - u32 trap_id[4]; /* Trap ID */ - u32 snvs_addr[4]; /* SNVS address */ - u32 snvs_data[4]; /* SNVS data */ - u32 snvs_info[4]; /* SNVS info */ - u32 version[4]; /* Version */ -}; - -struct rdc_regs { - u32 vir; /* Version information */ - u32 reserved1[8]; - u32 stat; /* Status */ - u32 intctrl; /* Interrupt and Control */ - u32 intstat; /* Interrupt Status */ - u32 reserved2[116]; - u32 mda[27]; /* Master Domain Assignment */ - u32 reserved3[101]; - u32 pdap[118]; /* Peripheral Domain Access Permissions */ - u32 reserved4[138]; - struct { - u32 mrsa; /* Memory Region Start Address */ - u32 mrea; /* Memory Region End Address */ - u32 mrc; /* Memory Region Control */ - u32 mrvs; /* Memory Region Violation Status */ - } mem_region[52]; -}; - -struct rdc_sema_regs { - u8 gate[64]; /* Gate */ - u16 rstgt; /* Reset Gate */ -}; - -#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR - -#define LCDIF_CTRL_SFTRST (1 << 31) -#define LCDIF_CTRL_CLKGATE (1 << 30) -#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) -#define LCDIF_CTRL_READ_WRITEB (1 << 28) -#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) -#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) -#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) -#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 -#define LCDIF_CTRL_DVI_MODE (1 << 20) -#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) -#define LCDIF_CTRL_VSYNC_MODE (1 << 18) -#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) -#define LCDIF_CTRL_DATA_SELECT (1 << 16) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) -#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) -#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 -#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) -#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) -#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) -#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) -#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) -#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) -#define LCDIF_CTRL_RUN (1 << 0) - -#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) -#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) -#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) -#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) -#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) -#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) -#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) -#define LCDIF_CTRL1_MODE86 (1 << 1) -#define LCDIF_CTRL1_RESET (1 << 0) - -#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) -#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 -#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) -#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) -#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) -#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) -#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) -#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 -#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) -#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 - -#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) -#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 -#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) -#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 - -#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff -#define LCDIF_CUR_BUF_ADDR_OFFSET 0 - -#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff -#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 - -#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) -#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 -#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) -#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 -#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) -#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 -#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) -#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 - -#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) -#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) -#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) -#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) -#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) -#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) -#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) -#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 - -#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff -#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 - -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 -#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff -#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 - -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) -#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 - -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 - - -extern void check_cpu_temperature(void); - -extern void pcie_power_up(void); -extern void pcie_power_off(void); - -/* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB - * If boot from the other mode, USB0_PWD will keep reset value - */ -#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ - readl(USBOTG2_IPS_BASE_ADDR + 0x158)) -#define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) - -struct bootrom_sw_info { - u8 reserved_1; - u8 boot_dev_instance; - u8 boot_dev_type; - u8 reserved_2; - u32 arm_core_freq; - u32 axi_freq; - u32 ddr_freq; - u32 gpt1_freq; - u32 reserved_3[3]; -}; - -#endif /* __ASSEMBLER__*/ -#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h deleted file mode 100644 index 3c07904..0000000 --- a/arch/arm/include/asm/arch-mx7/mx7-ddr.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * DDR controller registers of the i.MX7 architecture - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach <uri.mashiach@compulab.co.il> - */ - -#ifndef __ASM_ARCH_MX7_DDR_H__ -#define __ASM_ARCH_MX7_DDR_H__ - -/* DDRC Registers (DDRC_IPS_BASE_ADDR) */ -struct ddrc { - u32 mstr; /* 0x0000 */ - u32 reserved1[0x18]; - u32 rfshtmg; /* 0x0064 */ - u32 reserved2[0x1a]; - u32 init0; /* 0x00d0 */ - u32 init1; /* 0x00d4 */ - u32 reserved3; - u32 init3; /* 0x00dc */ - u32 init4; /* 0x00e0 */ - u32 init5; /* 0x00e4 */ - u32 reserved4[0x03]; - u32 rankctl; /* 0x00f4 */ - u32 reserved5[0x02]; - u32 dramtmg0; /* 0x0100 */ - u32 dramtmg1; /* 0x0104 */ - u32 dramtmg2; /* 0x0108 */ - u32 dramtmg3; /* 0x010c */ - u32 dramtmg4; /* 0x0110 */ - u32 dramtmg5; /* 0x0114 */ - u32 reserved6[0x02]; - u32 dramtmg8; /* 0x0120 */ - u32 reserved7[0x17]; - u32 zqctl0; /* 0x0180 */ - u32 reserved8[0x03]; - u32 dfitmg0; /* 0x0190 */ - u32 dfitmg1; /* 0x0194 */ - u32 reserved9[0x02]; - u32 dfiupd0; /* 0x01a0 */ - u32 dfiupd1; /* 0x01a4 */ - u32 dfiupd2; /* 0x01a8 */ - u32 reserved10[0x15]; - u32 addrmap0; /* 0x0200 */ - u32 addrmap1; /* 0x0204 */ - u32 addrmap2; /* 0x0208 */ - u32 addrmap3; /* 0x020c */ - u32 addrmap4; /* 0x0210 */ - u32 addrmap5; /* 0x0214 */ - u32 addrmap6; /* 0x0218 */ - u32 reserved12[0x09]; - u32 odtcfg; /* 0x0240 */ - u32 odtmap; /* 0x0244 */ -}; - -/* DDRC_MSTR fields */ -#define MSTR_DATA_BUS_WIDTH_MASK 0x3 << 12 -#define MSTR_DATA_BUS_WIDTH_SHIFT 12 -#define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24 -#define MSTR_DATA_ACTIVE_RANKS_SHIFT 24 -/* DDRC_ADDRMAP1 fields */ -#define ADDRMAP1_BANK_B0_MASK 0x1f << 0 -#define ADDRMAP1_BANK_B0_SHIFT 0 -#define ADDRMAP1_BANK_B1_MASK 0x1f << 8 -#define ADDRMAP1_BANK_B1_SHIFT 8 -#define ADDRMAP1_BANK_B2_MASK 0x1f << 16 -#define ADDRMAP1_BANK_B2_SHIFT 16 -/* DDRC_ADDRMAP2 fields */ -#define ADDRMAP2_COL_B2_MASK 0xF << 0 -#define ADDRMAP2_COL_B2_SHIFT 0 -#define ADDRMAP2_COL_B3_MASK 0xF << 8 -#define ADDRMAP2_COL_B3_SHIFT 8 -#define ADDRMAP2_COL_B4_MASK 0xF << 16 -#define ADDRMAP2_COL_B4_SHIFT 16 -#define ADDRMAP2_COL_B5_MASK 0xF << 24 -#define ADDRMAP2_COL_B5_SHIFT 24 -/* DDRC_ADDRMAP3 fields */ -#define ADDRMAP3_COL_B6_MASK 0xF << 0 -#define ADDRMAP3_COL_B6_SHIFT 0 -#define ADDRMAP3_COL_B7_MASK 0xF << 8 -#define ADDRMAP3_COL_B7_SHIFT 8 -#define ADDRMAP3_COL_B8_MASK 0xF << 16 -#define ADDRMAP3_COL_B8_SHIFT 16 -#define ADDRMAP3_COL_B9_MASK 0xF << 24 -#define ADDRMAP3_COL_B9_SHIFT 24 -/* DDRC_ADDRMAP4 fields */ -#define ADDRMAP4_COL_B10_MASK 0xF << 0 -#define ADDRMAP4_COL_B10_SHIFT 0 -#define ADDRMAP4_COL_B11_MASK 0xF << 8 -#define ADDRMAP4_COL_B11_SHIFT 8 -/* DDRC_ADDRMAP5 fields */ -#define ADDRMAP5_ROW_B0_MASK 0xF << 0 -#define ADDRMAP5_ROW_B0_SHIFT 0 -#define ADDRMAP5_ROW_B1_MASK 0xF << 8 -#define ADDRMAP5_ROW_B1_SHIFT 8 -#define ADDRMAP5_ROW_B2_10_MASK 0xF << 16 -#define ADDRMAP5_ROW_B2_10_SHIFT 16 -#define ADDRMAP5_ROW_B11_MASK 0xF << 24 -#define ADDRMAP5_ROW_B11_SHIFT 24 -/* DDRC_ADDRMAP6 fields */ -#define ADDRMAP6_ROW_B12_MASK 0xF << 0 -#define ADDRMAP6_ROW_B12_SHIFT 0 -#define ADDRMAP6_ROW_B13_MASK 0xF << 8 -#define ADDRMAP6_ROW_B13_SHIFT 8 -#define ADDRMAP6_ROW_B14_MASK 0xF << 16 -#define ADDRMAP6_ROW_B14_SHIFT 16 -#define ADDRMAP6_ROW_B15_MASK 0xF << 24 -#define ADDRMAP6_ROW_B15_SHIFT 24 - -/* DDRC_MP Registers */ -#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc) -struct ddrc_mp { - u32 reserved1[0x25]; - u32 pctrl_0; /* 0x0094 */ -}; - -/* DDR_PHY registers */ -struct ddr_phy { - u32 phy_con0; /* 0x0000 */ - u32 phy_con1; /* 0x0004 */ - u32 reserved1[0x02]; - u32 phy_con4; /* 0x0010 */ - u32 reserved2; - u32 offset_lp_con0; /* 0x0018 */ - u32 reserved3; - u32 offset_rd_con0; /* 0x0020 */ - u32 reserved4[0x03]; - u32 offset_wr_con0; /* 0x0030 */ - u32 reserved5[0x07]; - u32 cmd_sdll_con0; /* 0x0050 */ - u32 reserved6[0x12]; - u32 drvds_con0; /* 0x009c */ - u32 reserved7[0x04]; - u32 mdll_con0; /* 0x00b0 */ - u32 reserved8[0x03]; - u32 zq_con0; /* 0x00c0 */ -}; - -#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24) - -#define MX7_CAL_VAL_MAX 5 -/* Calibration parameters */ -struct mx7_calibration { - int num_val; /* Number of calibration values */ - u32 values[MX7_CAL_VAL_MAX]; /* calibration values */ -}; - -void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, - struct ddr_phy *ddr_phy_regs_val, - struct mx7_calibration *calib_param); - -#endif /*__ASM_ARCH_MX7_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/mx7-pins.h b/arch/arm/include/asm/arch-mx7/mx7-pins.h deleted file mode 100644 index bc99a86..0000000 --- a/arch/arm/include/asm/arch-mx7/mx7-pins.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ -#ifndef __ASM_ARCH_MX7_PINS_H__ -#define __ASM_ARCH_MX7_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -#if defined(CONFIG_MX7D) -#include "mx7d_pins.h" -#elif defined(CONFIG_MX7S) -#include "mx7s_pins.h" -#else -#error "Please select cpu" -#endif /* CONFIG_MX7D */ - -#endif /*__ASM_ARCH_MX7_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/mx7_plugin.S b/arch/arm/include/asm/arch-mx7/mx7_plugin.S deleted file mode 100644 index c7a84e8..0000000 --- a/arch/arm/include/asm/arch-mx7/mx7_plugin.S +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include <config.h> - -#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 -#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 - -plugin_start: - - push {r0-r4, lr} - - imx7_ddr_setting - imx7_clock_gating - imx7_qos_setting - -/* - * Check if we are in USB serial download mode and immediately return to ROM - * Need to check USB CTRL clock firstly, then check the USBx_nASYNCLISTADDR - */ - ldr r0, =0x30384680 - ldr r1, [r0] - cmp r1, #0 - beq normal_boot - - ldr r0, =0x30B10158 - ldr r1, [r0] - cmp r1, #0 - beq normal_boot - - pop {r0-r4, lr} - bx lr - -normal_boot: - -/* - * The following is to fill in those arguments for this ROM function - * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) - * This function is used to copy data from the storage media into DDR. - * start - Initial (possibly partial) image load address on entry. - * Final image load address on exit. - * bytes - Initial (possibly partial) image size on entry. - * Final image size on exit. - * boot_data - Initial @ref ivt Boot Data load address. - */ - adr r0, boot_data2 - adr r1, image_len2 - adr r2, boot_data2 - -/* - * check the _pu_irom_api_table for the address - */ -before_calling_rom___pu_irom_hwcnfg_setup: - ldr r3, =ROM_VERSION_OFFSET - ldr r4, [r3] - ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY - ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] - blx r4 -after_calling_rom___pu_irom_hwcnfg_setup: - - -/* To return to ROM from plugin, we need to fill in these argument. - * Here is what need to do: - * Need to construct the paramters for this function before return to ROM: - * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) - */ - pop {r0-r4, lr} - push {r5} - ldr r5, boot_data2 - str r5, [r0] - ldr r5, image_len2 - str r5, [r1] - ldr r5, second_ivt_offset - str r5, [r2] - mov r0, #1 - pop {r5} - - /* return back to ROM code */ - bx lr - -/* make the following data right in the end of the output*/ -.ltorg - -#define FLASH_OFFSET 0x400 - -/* - * second_ivt_offset is the offset from the "second_ivt_header" to - * "image_copy_start", which involves FLASH_OFFSET, plus the first - * ivt_header, the plugin code size itself recorded by "ivt2_header" - */ - -second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) - -/* - * The following is the second IVT header plus the second boot data - */ -ivt2_header: .long 0x0 -app2_code_jump_v: .long 0x0 -reserv3: .long 0x0 -dcd2_ptr: .long 0x0 -boot_data2_ptr: .long 0x0 -self_ptr2: .long 0x0 -app_code_csf2: .long 0x0 -reserv4: .long 0x0 -boot_data2: .long 0x0 -image_len2: .long 0x0 -plugin2: .long 0x0 diff --git a/arch/arm/include/asm/arch-mx7/mx7d_pins.h b/arch/arm/include/asm/arch-mx7/mx7d_pins.h deleted file mode 100644 index d54680f..0000000 --- a/arch/arm/include/asm/arch-mx7/mx7d_pins.h +++ /dev/null @@ -1,1307 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX7D_PINS_H__ -#define __ASM_ARCH_IMX7D_PINS_H__ - -#include <asm/mach-imx/iomux-v3.h> - -enum { - MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0), - MX7D_PAD_GPIO1_IO02__SAI2_MCLK = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__CCM_CLKO1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO02__USB_OTG1_ID = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0), - - MX7D_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__PWM3_OUT = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0), - MX7D_PAD_GPIO1_IO03__SAI3_MCLK = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__CCM_CLKO2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO03__USB_OTG2_ID = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0), - - MX7D_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO04__USB_OTG1_OC = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0), - MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0), - MX7D_PAD_GPIO1_IO04__UART5_CTS_B = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0), - MX7D_PAD_GPIO1_IO04__I2C1_SCL = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0), - - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0), - MX7D_PAD_GPIO1_IO05__UART5_RTS_B = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0), - MX7D_PAD_GPIO1_IO05__I2C1_SDA = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0), - - MX7D_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO06__USB_OTG2_OC = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0), - MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0), - MX7D_PAD_GPIO1_IO06__UART5_RX_DATA = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0), - MX7D_PAD_GPIO1_IO06__I2C2_SCL = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0), - MX7D_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO06__KPP_ROW4 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0), - - MX7D_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0), - MX7D_PAD_GPIO1_IO07__UART5_TX_DATA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0), - MX7D_PAD_GPIO1_IO07__I2C2_SDA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0), - MX7D_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO07__KPP_COL4 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0), -}; - -enum { - MX7D_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__SD1_VSELECT = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__UART3_DCE_RX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0), - MX7D_PAD_GPIO1_IO08__UART3_DTE_TX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO08__I2C3_SCL = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0), - MX7D_PAD_GPIO1_IO08__KPP_COL5 = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0), - MX7D_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__SD1_LCTL = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__UART3_DCE_TX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO09__UART3_DTE_RX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0), - MX7D_PAD_GPIO1_IO09__I2C3_SDA = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0), - MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0), - MX7D_PAD_GPIO1_IO09__KPP_ROW5 = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0), - MX7D_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO10__SD2_LCTL = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO10__ENET1_MDIO = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0), - MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0), - MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO10__I2C4_SCL = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0), - MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0), - MX7D_PAD_GPIO1_IO10__KPP_COL6 = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0), - MX7D_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__SD3_LCTL = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__ENET1_MDC = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0), - MX7D_PAD_GPIO1_IO11__I2C4_SDA = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0), - MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0), - MX7D_PAD_GPIO1_IO11__KPP_ROW6 = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0), - MX7D_PAD_GPIO1_IO11__PWM4_OUT = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0), - - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__SD2_VSELECT = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0), - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0), - MX7D_PAD_GPIO1_IO12__CM4_NMI = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0), - MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO12__USB_OTG1_ID = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0), - - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__SD3_VSELECT = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0), - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0), - MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0), - MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO13__USB_OTG2_ID = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0), - - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO14__SD3_CD_B = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0), - MX7D_PAD_GPIO1_IO14__ENET2_MDIO = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0), - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0), - MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0), - MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0), - - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__SD3_WP = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0), - MX7D_PAD_GPIO1_IO15__ENET2_MDC = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0), - MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0), - MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0), - - MX7D_PAD_EPDC_DATA00__EPDC_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__KPP_ROW3 = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0), - MX7D_PAD_EPDC_DATA00__EIM_AD0 = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA00__LCD_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0), - MX7D_PAD_EPDC_DATA00__LCD_CLK = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA01__EPDC_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__KPP_COL3 = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0), - MX7D_PAD_EPDC_DATA01__EIM_AD1 = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA01__LCD_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0), - MX7D_PAD_EPDC_DATA01__LCD_ENABLE = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA02__EPDC_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__KPP_ROW2 = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0), - MX7D_PAD_EPDC_DATA02__EIM_AD2 = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA02__LCD_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0), - MX7D_PAD_EPDC_DATA02__LCD_VSYNC = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0), - - MX7D_PAD_EPDC_DATA03__EPDC_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__KPP_COL2 = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0), - MX7D_PAD_EPDC_DATA03__EIM_AD3 = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA03__LCD_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0), - MX7D_PAD_EPDC_DATA03__LCD_HSYNC = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA04__EPDC_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__QSPI_A_DQS = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__KPP_ROW1 = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0), - MX7D_PAD_EPDC_DATA04__EIM_AD4 = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA04__LCD_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0), - MX7D_PAD_EPDC_DATA04__JTAG_FAIL = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA05__EPDC_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__KPP_COL1 = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0), - MX7D_PAD_EPDC_DATA05__EIM_AD5 = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA05__LCD_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0), - MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA06__EPDC_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__KPP_ROW0 = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0), - MX7D_PAD_EPDC_DATA06__EIM_AD6 = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA06__LCD_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0), - MX7D_PAD_EPDC_DATA06__JTAG_DE_B = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA07__EPDC_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__KPP_COL0 = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0), - MX7D_PAD_EPDC_DATA07__EIM_AD7 = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA07__LCD_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0), - MX7D_PAD_EPDC_DATA07__JTAG_DONE = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA08__EPDC_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0), - MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0), - MX7D_PAD_EPDC_DATA08__UART6_DTE_TX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__EIM_OE = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA08__LCD_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0), - MX7D_PAD_EPDC_DATA08__LCD_BUSY = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0), - MX7D_PAD_EPDC_DATA08__EPDC_SDCLK = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA09__EPDC_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__UART6_DTE_RX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0), - MX7D_PAD_EPDC_DATA09__EIM_RW = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA09__LCD_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0), - MX7D_PAD_EPDC_DATA09__LCD_DATA0 = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0), - MX7D_PAD_EPDC_DATA09__EPDC_SDLE = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0), - MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__EIM_CS0_B = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA10__LCD_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0), - MX7D_PAD_EPDC_DATA10__LCD_DATA9 = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0), - MX7D_PAD_EPDC_DATA10__EPDC_SDOE = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0), - MX7D_PAD_EPDC_DATA11__EIM_BCLK = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA11__LCD_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0), - MX7D_PAD_EPDC_DATA11__LCD_DATA1 = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0), - MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0), - MX7D_PAD_EPDC_DATA12__QSPI_B_DQS = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__UART7_DCE_RX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0), - MX7D_PAD_EPDC_DATA12__UART7_DTE_TX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__EIM_LBA_B = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA12__LCD_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0), - MX7D_PAD_EPDC_DATA12__LCD_DATA21 = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0), - MX7D_PAD_EPDC_DATA12__EPDC_GDCLK = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0), - MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__UART7_DCE_TX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__UART7_DTE_RX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0), - MX7D_PAD_EPDC_DATA13__EIM_WAIT = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__LCD_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0), - MX7D_PAD_EPDC_DATA13__LCD_CS = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA13__EPDC_GDOE = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0), - MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__EIM_EB_B0 = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA14__LCD_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0), - MX7D_PAD_EPDC_DATA14__LCD_DATA22 = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0), - MX7D_PAD_EPDC_DATA14__EPDC_GDSP = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0), - MX7D_PAD_EPDC_DATA15__EIM_CS1_B = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__LCD_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0), - MX7D_PAD_EPDC_DATA15__LCD_WR_RWN = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0), - MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0), - - MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__KPP_ROW4 = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0), - MX7D_PAD_EPDC_SDCLK__EIM_AD10 = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__LCD_CLK = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCLK__LCD_DATA20 = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0), - - MX7D_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__KPP_COL4 = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0), - MX7D_PAD_EPDC_SDLE__EIM_AD11 = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDLE__LCD_DATA16 = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0), - MX7D_PAD_EPDC_SDLE__LCD_DATA8 = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0), - - MX7D_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0), - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__KPP_COL5 = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0), - MX7D_PAD_EPDC_SDOE__EIM_AD12 = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDOE__LCD_DATA17 = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0), - MX7D_PAD_EPDC_SDOE__LCD_DATA23 = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0), - - MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0), - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__KPP_ROW5 = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0), - MX7D_PAD_EPDC_SDSHR__EIM_AD13 = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDSHR__LCD_DATA18 = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0), - MX7D_PAD_EPDC_SDSHR__LCD_DATA10 = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0), - - MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0), - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__EIM_AD14 = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE0__LCD_DATA19 = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0), - MX7D_PAD_EPDC_SDCE0__LCD_DATA5 = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0), - - MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0), - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0), - MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__EIM_AD15 = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE1__LCD_DATA20 = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0), - MX7D_PAD_EPDC_SDCE1__LCD_DATA4 = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0), - - MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__KPP_COL6 = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0), - MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE2__LCD_DATA21 = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0), - MX7D_PAD_EPDC_SDCE2__LCD_DATA3 = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0), - - MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0), - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__KPP_ROW6 = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0), - MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_SDCE3__LCD_DATA22 = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0), - MX7D_PAD_EPDC_SDCE3__LCD_DATA2 = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0), - - MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0), - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__KPP_COL7 = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0), - MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDCLK__LCD_DATA23 = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0), - MX7D_PAD_EPDC_GDCLK__LCD_DATA16 = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0), - - MX7D_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0), - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__KPP_ROW7 = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0), - MX7D_PAD_EPDC_GDOE__EIM_ADDR19 = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__LCD_WR_RWN = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDOE__LCD_DATA18 = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0), - - MX7D_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0), - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__EIM_ADDR20 = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__LCD_RD_E = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDRL__LCD_DATA19 = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0), - - MX7D_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0), - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__ENET2_TX_ER = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__EIM_ADDR21 = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_GDSP__LCD_BUSY = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0), - MX7D_PAD_EPDC_GDSP__LCD_DATA17 = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0), - - MX7D_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0), - MX7D_PAD_EPDC_BDR0__EIM_ADDR22 = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__LCD_CS = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR0__LCD_DATA7 = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0), - - MX7D_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0), - MX7D_PAD_EPDC_BDR1__EIM_AD8 = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__LCD_ENABLE = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_BDR1__LCD_DATA6 = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0), - - MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0), - MX7D_PAD_EPDC_PWR_COM__ENET2_CRS = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__EIM_AD9 = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0), - - MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__ENET2_COL = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0), - MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0), - MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0), - - MX7D_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__ECSPI4_MISO = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0), - MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__CSI_DATA16 = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0), - MX7D_PAD_LCD_CLK__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_CLK__GPIO3_IO0 = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0), - MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__CSI_DATA17 = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__UART2_DCE_TX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_ENABLE__UART2_DTE_RX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0), - MX7D_PAD_LCD_ENABLE__GPIO3_IO1 = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0), - MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__CSI_DATA18 = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0), - MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_HSYNC__GPIO3_IO2 = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0), - MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0), - MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_VSYNC__CSI_DATA19 = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0), - MX7D_PAD_LCD_VSYNC__GPIO3_IO3 = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__GPT1_COMPARE1 = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__CSI_FIELD = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__EIM_DTACK_B = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_RESET__GPIO3_IO4 = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA00__LCD_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0), - MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__CSI_DATA20 = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__EIM_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__GPIO3_IO5 = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA01__LCD_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0), - MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__CSI_DATA21 = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__EIM_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__GPIO3_IO6 = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA02__LCD_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0), - MX7D_PAD_LCD_DATA02__GPT1_CLK = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__CSI_DATA22 = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__EIM_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__GPIO3_IO7 = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA03__LCD_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0), - MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__CSI_DATA23 = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__EIM_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__GPIO3_IO8 = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA04__LCD_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0), - MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0), - MX7D_PAD_LCD_DATA04__EIM_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA04__GPIO3_IO9 = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA05__LCD_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0), - MX7D_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0), - MX7D_PAD_LCD_DATA05__EIM_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA06__LCD_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0), - MX7D_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0), - MX7D_PAD_LCD_DATA06__EIM_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA07__LCD_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0), - MX7D_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA07__EIM_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA08__LCD_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0), - MX7D_PAD_LCD_DATA08__CSI_DATA9 = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0), - MX7D_PAD_LCD_DATA08__EIM_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA09__LCD_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0), - MX7D_PAD_LCD_DATA09__CSI_DATA8 = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0), - MX7D_PAD_LCD_DATA09__EIM_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0), - MX7D_PAD_LCD_DATA10__CSI_DATA7 = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0), - MX7D_PAD_LCD_DATA10__EIM_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0), - MX7D_PAD_LCD_DATA11__CSI_DATA6 = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0), - MX7D_PAD_LCD_DATA11__EIM_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0), - MX7D_PAD_LCD_DATA12__CSI_DATA5 = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0), - MX7D_PAD_LCD_DATA12__EIM_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0), - MX7D_PAD_LCD_DATA13__CSI_DATA4 = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0), - MX7D_PAD_LCD_DATA13__EIM_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0), - MX7D_PAD_LCD_DATA14__CSI_DATA3 = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0), - MX7D_PAD_LCD_DATA14__EIM_DATA14 = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0), - MX7D_PAD_LCD_DATA15__CSI_DATA2 = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0), - MX7D_PAD_LCD_DATA15__EIM_DATA15 = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0), - MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0), - MX7D_PAD_LCD_DATA16__CSI_DATA1 = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA16__EIM_CRE = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0), - MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0), - MX7D_PAD_LCD_DATA17__CSI_DATA0 = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0), - MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0), - MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__EIM_CS2_B = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA19__EIM_CS3_B = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0), - MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0), - MX7D_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__EIM_ADDR23 = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__I2C3_SCL = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0), - - MX7D_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0), - MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0), - MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0), - - MX7D_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0), - MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0), - MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__EIM_ADDR24 = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA21__I2C3_SDA = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0), - - MX7D_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0), - MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0), - MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__EIM_ADDR25 = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA22__I2C4_SCL = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0), - - MX7D_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0), - MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0), - MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__EIM_ADDR26 = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0), - MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0), - - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0), - - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0), - MX7D_PAD_UART1_RX_DATA__ENET1_MDIO = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0), - - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0), - - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0), - MX7D_PAD_UART1_TX_DATA__I2C1_SDA = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0), - MX7D_PAD_UART1_TX_DATA__SAI3_MCLK = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0), - MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0), - - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0), - - MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0), - MX7D_PAD_UART2_RX_DATA__ENET2_MDIO = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0), - - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), - - MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0), - MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0), - MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0), - MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0), - MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0), - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0), - MX7D_PAD_UART2_TX_DATA__ENET2_MDC = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0), - - MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0), - MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0), - MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0), - MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0), - MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_RX_DATA__SD1_LCTL = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0), - - MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0), - MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0), - MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0), - MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0), - MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0), - - MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__GPIO4_IO6 = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_RTS_B__SD3_LCTL = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0), - - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0), - - MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0), - MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0), - MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0), - MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0), - MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0), - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0), - MX7D_PAD_UART3_CTS_B__SD1_VSELECT = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0), - MX7D_PAD_I2C1_SCL__UART4_DCE_CTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0), - MX7D_PAD_I2C1_SCL__UART4_DTE_RTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0), - MX7D_PAD_I2C1_SCL__FLEXCAN1_RX = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0), - MX7D_PAD_I2C1_SCL__ECSPI3_MISO = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0), - MX7D_PAD_I2C1_SCL__GPIO4_IO8 = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0), - MX7D_PAD_I2C1_SCL__SD2_VSELECT = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0), - MX7D_PAD_I2C1_SDA__UART4_DCE_RTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0), - MX7D_PAD_I2C1_SDA__UART4_DTE_CTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0), - MX7D_PAD_I2C1_SDA__FLEXCAN1_TX = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0), - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0), - MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0), - MX7D_PAD_I2C1_SDA__GPIO4_IO9 = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0), - MX7D_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0), - MX7D_PAD_I2C2_SCL__UART4_DCE_RX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0), - MX7D_PAD_I2C2_SCL__UART4_DTE_TX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0), - MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0), - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0), - MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0), - MX7D_PAD_I2C2_SCL__GPIO4_IO10 = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0), - MX7D_PAD_I2C2_SCL__SD3_CD_B = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0), - - MX7D_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0), - MX7D_PAD_I2C2_SDA__UART4_DCE_TX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__UART4_DTE_RX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0), - MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__ECSPI3_SS0 = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0), - MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__GPIO4_IO11 = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0), - MX7D_PAD_I2C2_SDA__SD3_WP = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0), - - MX7D_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0), - MX7D_PAD_I2C3_SCL__UART5_DCE_CTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0), - MX7D_PAD_I2C3_SCL__UART5_DTE_RTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0), - MX7D_PAD_I2C3_SCL__FLEXCAN2_RX = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0), - MX7D_PAD_I2C3_SCL__CSI_VSYNC = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0), - MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0), - MX7D_PAD_I2C3_SCL__GPIO4_IO12 = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0), - MX7D_PAD_I2C3_SCL__EPDC_BDR0 = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0), - MX7D_PAD_I2C3_SDA__UART5_DCE_RTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0), - MX7D_PAD_I2C3_SDA__UART5_DTE_CTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0), - MX7D_PAD_I2C3_SDA__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0), - MX7D_PAD_I2C3_SDA__CSI_HSYNC = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0), - MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0), - MX7D_PAD_I2C3_SDA__GPIO4_IO13 = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0), - MX7D_PAD_I2C3_SDA__EPDC_BDR1 = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0), - MX7D_PAD_I2C4_SCL__UART5_DCE_RX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0), - MX7D_PAD_I2C4_SCL__UART5_DTE_TX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0), - MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0), - MX7D_PAD_I2C4_SCL__CSI_PIXCLK = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0), - MX7D_PAD_I2C4_SCL__USB_OTG1_ID = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0), - MX7D_PAD_I2C4_SCL__GPIO4_IO14 = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0), - MX7D_PAD_I2C4_SCL__EPDC_VCOM0 = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0), - - MX7D_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0), - MX7D_PAD_I2C4_SDA__UART5_DCE_TX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__UART5_DTE_RX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0), - MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__CSI_MCLK = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__USB_OTG2_ID = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0), - MX7D_PAD_I2C4_SDA__GPIO4_IO15 = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0), - MX7D_PAD_I2C4_SDA__EPDC_VCOM1 = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0), - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0), - MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0), - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0), - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0), - MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0), - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0), - - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0), - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0), - MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MISO__SD2_DATA6 = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MISO__CSI_DATA4 = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0), - MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0), - - MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0), - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0), - MX7D_PAD_ECSPI1_SS0__SD2_DATA7 = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SS0__CSI_DATA5 = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0), - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0), - MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0), - MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0), - MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0), - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0), - MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0), - MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0), - MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0), - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0), - - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0), - MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0), - MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__SD1_DATA6 = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_MISO__CSI_DATA8 = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0), - MX7D_PAD_ECSPI2_MISO__LCD_DATA15 = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0), - - MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0), - MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0), - MX7D_PAD_ECSPI2_SS0__SD1_DATA7 = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__CSI_DATA9 = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0), - MX7D_PAD_ECSPI2_SS0__LCD_RESET = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0), - MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0), - - MX7D_PAD_SD1_CD_B__SD1_CD_B = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_CD_B__UART6_DCE_RX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0), - MX7D_PAD_SD1_CD_B__UART6_DTE_TX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_CD_B__ECSPI4_MISO = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0), - MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0), - MX7D_PAD_SD1_CD_B__GPIO5_IO0 = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_CD_B__CCM_CLKO1 = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0), - - MX7D_PAD_SD1_WP__SD1_WP = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_WP__UART6_DCE_TX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_WP__UART6_DTE_RX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0), - MX7D_PAD_SD1_WP__ECSPI4_MOSI = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0), - MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0), - MX7D_PAD_SD1_WP__GPIO5_IO1 = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_WP__CCM_CLKO2 = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0), - - MX7D_PAD_SD1_RESET_B__SD1_RESET_B = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_RESET_B__SAI3_MCLK = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0), - MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0), - MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0), - MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0), - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0), - - MX7D_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0), - MX7D_PAD_SD1_CLK__UART6_DCE_CTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_CLK__UART6_DTE_RTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0), - MX7D_PAD_SD1_CLK__ECSPI4_SS0 = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0), - MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0), - MX7D_PAD_SD1_CLK__GPIO5_IO3 = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0), - - MX7D_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0), - MX7D_PAD_SD1_CMD__ECSPI4_SS1 = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0), - MX7D_PAD_SD1_CMD__GPIO5_IO4 = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0), - - MX7D_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0), - MX7D_PAD_SD1_DATA0__UART7_DCE_RX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0), - MX7D_PAD_SD1_DATA0__UART7_DTE_TX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__ECSPI4_SS2 = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0), - MX7D_PAD_SD1_DATA0__GPIO5_IO5 = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0), - - MX7D_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0), - MX7D_PAD_SD1_DATA1__UART7_DCE_TX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__UART7_DTE_RX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0), - MX7D_PAD_SD1_DATA1__ECSPI4_SS3 = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0), - MX7D_PAD_SD1_DATA1__GPIO5_IO6 = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0), - - MX7D_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0), - MX7D_PAD_SD1_DATA2__UART7_DCE_CTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__UART7_DTE_RTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0), - MX7D_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0), - MX7D_PAD_SD1_DATA2__GPIO5_IO7 = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0), - - MX7D_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__UART7_DCE_RTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0), - MX7D_PAD_SD1_DATA3__UART7_DTE_CTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__ECSPI3_SS1 = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0), - MX7D_PAD_SD1_DATA3__GPIO5_IO8 = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0), - MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0), - - MX7D_PAD_SD2_CD_B__SD2_CD_B = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_CD_B__ENET1_MDIO = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0), - MX7D_PAD_SD2_CD_B__ENET2_MDIO = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0), - MX7D_PAD_SD2_CD_B__ECSPI3_SS2 = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0), - MX7D_PAD_SD2_CD_B__GPIO5_IO9 = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0), - MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0), - - MX7D_PAD_SD2_WP__SD2_WP = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__ENET1_MDC = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__ENET2_MDC = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__ECSPI3_SS3 = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__USB_OTG1_ID = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0), - MX7D_PAD_SD2_WP__GPIO5_IO10 = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0), - MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0), - - MX7D_PAD_SD2_RESET_B__SD2_RESET_B = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__SAI2_MCLK = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__SD2_RESET = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__ECSPI3_RDY = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_RESET_B__USB_OTG2_ID = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0), - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_CLK__SAI2_RX_SYNC = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0), - MX7D_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_CLK__GPT4_CLK = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_CLK__GPIO5_IO12 = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_CMD__SAI2_RX_BCLK = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0), - MX7D_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0), - MX7D_PAD_SD2_CMD__GPIO5_IO13 = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0), - MX7D_PAD_SD2_DATA0__UART4_DCE_RX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0), - MX7D_PAD_SD2_DATA0__UART4_DTE_TX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA0__GPIO5_IO14 = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0), - MX7D_PAD_SD2_DATA1__UART4_DCE_TX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__UART4_DTE_RX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0), - MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA1__GPIO5_IO15 = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0), - MX7D_PAD_SD2_DATA2__UART4_DCE_CTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__UART4_DTE_RTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0), - MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA2__GPIO5_IO16 = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__UART4_DCE_RTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0), - MX7D_PAD_SD2_DATA3__UART4_DTE_CTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0), - MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0), - MX7D_PAD_SD2_DATA3__GPIO5_IO17 = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_CLK__NAND_CLE = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_CLK__ECSPI4_MISO = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0), - MX7D_PAD_SD3_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0), - MX7D_PAD_SD3_CLK__GPT3_CLK = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_CLK__GPIO6_IO0 = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_CMD__NAND_ALE = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0), - MX7D_PAD_SD3_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0), - MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_CMD__GPIO6_IO1 = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA0__NAND_DATA00 = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA0__ECSPI4_SS0 = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0), - MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0), - MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA0__GPIO6_IO2 = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA1__NAND_DATA01 = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0), - MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0), - MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA1__GPIO6_IO3 = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA2__NAND_DATA02 = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA2__I2C3_SDA = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0), - MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0), - MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA2__GPIO6_IO4 = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__NAND_DATA03 = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__I2C3_SCL = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0), - MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA3__GPIO6_IO5 = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA4__SD3_DATA4 = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA4__NAND_DATA04 = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA4__UART3_DCE_RX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0), - MX7D_PAD_SD3_DATA4__UART3_DTE_TX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA4__FLEXCAN2_RX = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0), - MX7D_PAD_SD3_DATA4__GPIO6_IO6 = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA5__SD3_DATA5 = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__NAND_DATA05 = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__UART3_DCE_TX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__UART3_DTE_RX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0), - MX7D_PAD_SD3_DATA5__FLEXCAN1_TX = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA5__GPIO6_IO7 = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA6__SD3_DATA6 = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__NAND_DATA06 = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__SD3_WP = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0), - MX7D_PAD_SD3_DATA6__UART3_DCE_RTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0), - MX7D_PAD_SD3_DATA6__UART3_DTE_CTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__FLEXCAN2_TX = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA6__GPIO6_IO8 = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_DATA7__SD3_DATA7 = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA7__NAND_DATA07 = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA7__SD3_CD_B = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0), - MX7D_PAD_SD3_DATA7__UART3_DCE_CTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_DATA7__UART3_DTE_RTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0), - MX7D_PAD_SD3_DATA7__FLEXCAN1_RX = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0), - MX7D_PAD_SD3_DATA7__GPIO6_IO9 = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_STROBE__SD3_STROBE = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_STROBE__NAND_RE_B = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_STROBE__GPIO6_IO10 = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0), - - MX7D_PAD_SD3_RESET_B__SD3_RESET_B = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__NAND_WE_B = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__SD3_RESET = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__SAI3_MCLK = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0), - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0), - - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0), - MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0), - MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0), - MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0), - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0), - MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__NAND_DQS = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0), - MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0), - MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0), - MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0), - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0), - MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0), - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0), - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0), - MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0), - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0), - MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__NAND_WP_B = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__SAI2_MCLK = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0), - MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0), - MX7D_PAD_SAI1_MCLK__GPIO6_IO18 = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0), - MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0), - - MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0), - MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0), - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0), - MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0), - MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0), - MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0), - - MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0), - MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0), - MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0), - - MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0), - MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0), - MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0), - MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0), - MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0), - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0), - MX7D_PAD_SAI2_RX_DATA__KPP_COL7 = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0), - - MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0), - MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0), - MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0), - MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0), - MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0), - MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0), - MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0), - MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0), - MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0), - MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0), - MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0), - MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0), - MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0), - - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0), - MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0), - MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0), - - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0), - - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0), - - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0), - - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0), - MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0), - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0), - MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0), - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0), - MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0), - - MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0), - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0), - MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0), - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0), - MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0), - MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0), - MX7D_PAD_ENET1_RX_CLK__GPT2_CLK = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0), - MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0), - MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__GPIO7_IO14 = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0), - MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0), - - MX7D_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__GPIO7_IO15 = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0), - MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0), - MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0), -}; -#endif /* __ASM_ARCH_IMX7D_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/mx7d_rdc.h b/arch/arm/include/asm/arch-mx7/mx7d_rdc.h deleted file mode 100644 index 2ea175c..0000000 --- a/arch/arm/include/asm/arch-mx7/mx7d_rdc.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __MX7D_RDC_H__ -#define __MX7D_RDC_H__ - -#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ - -enum { - RDC_PER_GPIO1 = 0, - RDC_PER_GPIO2, - RDC_PER_GPIO3, - RDC_PER_GPIO4, - RDC_PER_GPIO5, - RDC_PER_GPIO6, - RDC_PER_GPIO7, - RDC_PER_IOMUXC_LPSR_GPR, - RDC_PER_WDOG1, - RDC_PER_WDOG2, - RDC_PER_WDOG3, - RDC_PER_WDOG4, - RDC_PER_IOMUXC_LPSR, - RDC_PER_GPT1, - RDC_PER_GPT2, - RDC_PER_GPT3, - RDC_PER_GPT4, - RDC_PER_ROMCP, - RDC_PER_KPP, - RDC_PER_IOMUXC, - RDC_PER_IOMUXCGPR, - RDC_PER_OCOTP, - RDC_PER_ANATOP_DIG, - RDC_PER_SNVS_HP, - RDC_PER_CCM, - RDC_PER_SRC, - RDC_PER_GPC, - RDC_PER_SEMA1, - RDC_PER_SEMA2, - RDC_PER_RDC, - RDC_PER_CSU, - RDC_PER_RESERVED1, - RDC_PER_RESERVED2, - RDC_PER_ADC1, - RDC_PER_ADC2, - RDC_PER_ECSPI4, - RDC_PER_FLEX_TIMER1, - RDC_PER_FLEX_TIMER2, - RDC_PER_PWM1, - RDC_PER_PWM2, - RDC_PER_PWM3, - RDC_PER_PWM4, - RDC_PER_SYSTEM_COUNTER_READ, - RDC_PER_SYSTEM_COUNTER_COMPARE, - RDC_PER_SYSTEM_COUNTER_CONTROL, - RDC_PER_PCIE_PHY, - RDC_PER_RESERVED3, - RDC_PER_EPDC, - RDC_PER_PXP, - RDC_PER_CSI, - RDC_PER_RESERVED4, - RDC_PER_LCDIF, - RDC_PER_RESERVED5, - RDC_PER_MIPI_CSI, - RDC_PER_MIPI_DSI, - RDC_PER_RESERVED6, - RDC_PER_TZASC, - RDC_PER_DDR_PHY, - RDC_PER_DDRC, - RDC_PER_RESERVED7, - RDC_PER_PERFMON1, - RDC_PER_PERFMON2, - RDC_PER_AXI_DEBUG_MON, - RDC_PER_QOSC, - RDC_PER_FLEXCAN1, - RDC_PER_FLEXCAN2, - RDC_PER_I2C1, - RDC_PER_I2C2, - RDC_PER_I2C3, - RDC_PER_I2C4, - RDC_PER_UART4, - RDC_PER_UART5, - RDC_PER_UART6, - RDC_PER_UART7, - RDC_PER_MU_A, - RDC_PER_MU_B, - RDC_PER_SEMAPHORE_HS, - RDC_PER_USB_PL301, - RDC_PER_RESERVED8, - RDC_PER_RESERVED9, - RDC_PER_RESERVED10, - RDC_PER_USB1, - RDC_PER_USB2, - RDC_PER_USB3, - RDC_PER_USDHC1, - RDC_PER_USDHC2, - RDC_PER_USDHC3, - RDC_PER_RESERVED11, - RDC_PER_RESERVED12, - RDC_PER_SIM1, - RDC_PER_SIM2, - RDC_PER_QSPI, - RDC_PER_WEIM, - RDC_PER_SDMA, - RDC_PER_ENET1, - RDC_PER_ENET2, - RDC_PER_RESERVED13, - RDC_PER_RESERVED14, - RDC_PER_ECSPI1, - RDC_PER_ECSPI2, - RDC_PER_ECSPI3, - RDC_PER_RESERVED15, - RDC_PER_UART1, - RDC_PER_UART2, - RDC_PER_UART3, - RDC_PER_RESERVED16, - RDC_PER_SAI1, - RDC_PER_SAI2, - RDC_PER_SAI3, - RDC_PER_RESERVED17, - RDC_PER_RESERVED18, - RDC_PER_SPBA, - RDC_PER_DAP, - RDC_PER_RESERVED19, - RDC_PER_RESERVED20, - RDC_PER_RESERVED21, - RDC_PER_CAAM, - RDC_PER_RESERVED22, -}; - -enum { - RDC_MA_A7 = 0, - RDC_MA_M4, - RDC_MA_PCIE, - RDC_MA_CSI, - RDC_MA_EPDC, - RDC_MA_LCDIF, - RDC_MA_DISPLAY_PORT, - RDC_MA_PXP, - RDC_MA_CORESIGHT, - RDC_MA_DAP, - RDC_MA_CAAM, - RDC_MA_SDMA_PERI, - RDC_MA_SDMA_BURST, - RDC_MA_APBHDMA, - RDC_MA_RAWNAND, - RDC_MA_USDHC1, - RDC_MA_USDHC2, - RDC_MA_USDHC3, - RDC_MA_NC1, - RDC_MA_USB, - RDC_MA_NC2, - RDC_MA_TEST, - RDC_MA_ENET1_TX, - RDC_MA_ENET1_RX, - RDC_MA_ENET2_TX, - RDC_MA_ENET2_RX, - RDC_MA_SDMA, -}; - -#endif /* __MX7D_RDC_H__*/ diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h deleted file mode 100644 index e46a021..0000000 --- a/arch/arm/include/asm/arch-mx7/sys_proto.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ -#ifndef __SYS_PROTO_IMX7_ -#define __SYS_PROTO_IMX7_ - -#include <asm/mach-imx/sys_proto.h> - -void set_wdog_reset(struct wdog_regs *wdog); -enum boot_device get_boot_device(void); - -#endif /* __SYS_PROTO_IMX7_ */ diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h deleted file mode 100644 index eb02a20..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _ASM_ARCH_CLOCK_H -#define _ASM_ARCH_CLOCK_H - -#include <common.h> -#include <asm/arch/pcc.h> -#include <asm/arch/scg.h> - -/* Mainly for compatible to imx common code. */ -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_AXI_CLK, - MXC_DDR_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_I2C_CLK, -}; - -u32 mxc_get_clock(enum mxc_clock clk); -u32 get_lpuart_clk(void); -#ifdef CONFIG_SYS_I2C_IMX_LPI2C -int enable_i2c_clk(unsigned char enable, unsigned i2c_num); -u32 imx_get_i2cclk(unsigned i2c_num); -#endif -#ifdef CONFIG_MXC_OCOTP -void enable_ocotp_clk(unsigned char enable); -#endif -#ifdef CONFIG_USB_EHCI_HCD -void enable_usboh3_clk(unsigned char enable); -#endif -void init_clk_usdhc(u32 index); -void clock_init(void); -void hab_caam_clock_enable(unsigned char enable); -#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/gpio.h b/arch/arm/include/asm/arch-mx7ulp/gpio.h deleted file mode 100644 index 7c62560..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX7ULP_GPIO_H -#define __ASM_ARCH_MX7ULP_GPIO_H - -struct gpio_regs { - u32 gpio_pdor; - u32 gpio_psor; - u32 gpio_pcor; - u32 gpio_ptor; - u32 gpio_pdir; - u32 gpio_pddr; - u32 gpio_gacr; -}; - -#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31)) - -#endif /* __ASM_ARCH_MX7ULP_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h deleted file mode 100644 index 3c82e99..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ /dev/null @@ -1,1141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _MX7ULP_REGS_H_ -#define _MX7ULP_REGS_H_ - -#include <linux/sizes.h> - -#define ARCH_MXC - -#define ROM_SW_INFO_ADDR 0x000001E8 - -#define CAAM_SEC_SRAM_BASE (0x26000000) -#define CAAM_SEC_SRAM_SIZE (SZ_32K) -#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) - -#define OCRAM_0_BASE (0x2F000000) -#define OCRAM_0_SIZE (SZ_128K) -#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) - -#define OCRAM_1_BASE (0x2F020000) -#define OCRAM_1_SIZE (SZ_128K) -#define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) - -#define TCML_BASE (0x1FFD0000) -#define TCMU_BASE (0x20000000) - -#define AIPS3_BASE (0x40800000UL) -#define AIPS3_SLOT_SIZE (SZ_64K) -#define AIPS2_BASE (0x40000000UL) -#define AIPS2_SLOT_SIZE (SZ_64K) -#define AIPS1_BASE (0x41080000UL) -#define AIPS1_SLOT_SIZE (SZ_4K) -#define AIPS0_BASE (0x41000000UL) -#define AIPS0_SLOT_SIZE (SZ_4K) -#define IOMUXC0_AIPS0_SLOT (61) -#define WDG0_AIPS0_SLOT (37) -#define WDG1_AIPS2_SLOT (61) -#define WDG2_AIPS2_SLOT (67) -#define WDG0_PCC0_SLOT (37) -#define IOMUXC1_AIPS3_SLOT (44) -#define CMC0_AIPS1_SLOT (36) -#define CMC1_AIPS2_SLOT (65) -#define SCG0_AIPS0_SLOT (39) -#define PCC0_AIPS0_SLOT (38) -#define PCC1_AIPS1_SLOT (50) -#define PCC2_AIPS2_SLOT (63) -#define PCC3_AIPS3_SLOT (51) -#define SCG1_AIPS2_SLOT (62) -#define SIM0_AIPS1_SLOT (35) -#define SIM1_AIPS1_SLOT (48) -#define USBOTG0_AIPS2_SLOT (51) -#define USBOTG1_AIPS2_SLOT (52) -#define USBPHY_AIPS2_SLOT (53) -#define USDHC0_AIPS2_SLOT (55) -#define USDHC1_AIPS2_SLOT (56) -#define RGPIO2P0_AIPS0_SLOT (15) -#define RGPIO2P1_AIPS2_SLOT (15) -#define SNVS_AIPS2_SLOT (35) -#define IOMUXC0_AIPS0_SLOT (61) -#define OCOTP_CTRL_AIPS1_SLOT (38) -#define OCOTP_CTRL_PCC1_SLOT (38) -#define SIM1_PCC1_SLOT (48) -#define MMDC0_AIPS3_SLOT (43) -#define IOMUXC_DDR_AIPS3_SLOT (45) - -#define LPI2C0_AIPS0_SLOT (51) -#define LPI2C1_AIPS0_SLOT (52) -#define LPI2C2_AIPS0_SLOT (53) -#define LPI2C3_AIPS0_SLOT (54) -#define LPI2C4_AIPS2_SLOT (43) -#define LPI2C5_AIPS2_SLOT (44) -#define LPI2C6_AIPS3_SLOT (36) -#define LPI2C7_AIPS3_SLOT (37) - -#define LPUART0_PCC0_SLOT (58) -#define LPUART1_PCC0_SLOT (59) -#define LPUART2_PCC1_SLOT (43) -#define LPUART3_PCC1_SLOT (44) -#define LPUART0_AIPS0_SLOT (58) -#define LPUART1_AIPS0_SLOT (59) -#define LPUART2_AIPS1_SLOT (43) -#define LPUART3_AIPS1_SLOT (44) -#define LPUART4_AIPS2_SLOT (45) -#define LPUART5_AIPS2_SLOT (46) -#define LPUART6_AIPS3_SLOT (38) -#define LPUART7_AIPS3_SLOT (39) - -#define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) -#define CORE_B_ROM_BASE (0x00000000) - -#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE -#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE -#define IRAM_BASE_ADDR OCRAM_0_BASE -#define IRAM_SIZE (SZ_128K + SZ_128K) - -#define IOMUXC_PCR_MUX_ALT0 (0<<8) -#define IOMUXC_PCR_MUX_ALT1 (1<<8) -#define IOMUXC_PCR_MUX_ALT2 (2<<8) -#define IOMUXC_PCR_MUX_ALT3 (3<<8) -#define IOMUXC_PCR_MUX_ALT4 (4<<8) -#define IOMUXC_PCR_MUX_ALT5 (5<<8) -#define IOMUXC_PCR_MUX_ALT6 (6<<8) -#define IOMUXC_PCR_MUX_ALT7 (7<<8) -#define IOMUXC_PCR_MUX_ALT8 (8<<8) -#define IOMUXC_PCR_MUX_ALT9 (9<<8) -#define IOMUXC_PCR_MUX_ALT10 (10<<8) -#define IOMUXC_PCR_MUX_ALT11 (11<<8) -#define IOMUXC_PCR_MUX_ALT12 (12<<8) -#define IOMUXC_PCR_MUX_ALT13 (13<<8) -#define IOMUXC_PCR_MUX_ALT14 (14<<8) -#define IOMUXC_PCR_MUX_ALT15 (15<<8) - -#define IOMUXC_PSMI_IMUX_ALT0 (0x0) -#define IOMUXC_PSMI_IMUX_ALT1 (0x1) -#define IOMUXC_PSMI_IMUX_ALT2 (0x2) -#define IOMUXC_PSMI_IMUX_ALT3 (0x3) -#define IOMUXC_PSMI_IMUX_ALT4 (0x4) -#define IOMUXC_PSMI_IMUX_ALT5 (0x5) -#define IOMUXC_PSMI_IMUX_ALT6 (0x6) -#define IOMUXC_PSMI_IMUX_ALT7 (0x7) - - -#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) -#define SIM_SOPT1_PMIC_STBY_REQ (1<<2) -#define SIM_SOPT1_A7_SW_RESET (1<<0) - -#define IOMUXC_PCR_MUX_ALT_SHIFT (8) -#define IOMUXC_PCR_MUX_ALT_MASK (0xF00) -#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) - -#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) -#define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) -#define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) -#define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) -#define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) -#define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) -#define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) -#define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) -#define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) -#define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) -#define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) -#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) -#define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ -#define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) -#define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) -#define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) -#define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) -#define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) -#define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) - -#define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) -#define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) -#define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) -#define USB_PHY0_BASE_ADDR USBPHY_RBASE -#define USB_BASE_ADDR USBOTG0_RBASE - -#define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) -#define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) -#define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) -#define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) -#define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) -#define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) -#define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) -#define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) - -#define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) -#define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) -#define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) -#define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) -#define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) -#define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) -#define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) -#define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) - -#define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) -#define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) - -#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) -#define SNVS_LP_LPCR (SNVS_BASE + 0x38) - -#define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) -#define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) - -#define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) -#define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) -#define CMC0_SRS (CMC0_RBASE + 0x20) -#define CMC0_SSRS (CMC0_RBASE + 0x28) -#define CMC1_SRS (CMC1_RBASE + 0x20) -#define CMC1_SSRS (CMC1_RBASE + 0x28) - -#define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) -#define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) -#define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) -#define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) -#define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) -#define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) -#define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) - -#define SCG_CSR (SCG0_RBASE + 0x010) -#define SCG_RCCR (SCG0_RBASE + 0x014) -#define SCG_VCCR (SCG0_RBASE + 0x018) -#define SCG_HCCR (SCG0_RBASE + 0x01c) - -#define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) -#define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) -#define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) -#define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) -#define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) -#define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) -#define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) -#define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) - -#define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) -#define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) - -#define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) -#define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) - -#define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) - -#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) -#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) - -#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) -#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) -#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) -#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) - - -#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) -#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) -#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) -#define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) -#define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) -#define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) -#define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) -#define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) -#define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) -#define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) -#define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) -#define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) -#define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) -#define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) -#define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) -#define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) -#define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) -#define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) -#define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) -#define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) -#define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) -#define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) -#define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) -#define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) -#define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) -#define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) -#define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) -#define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) -#define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) -#define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) -#define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) -#define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) - -/* Remap the rgpio2p registers addr to driver's addr */ -#define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE -#define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) -#define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) -#define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) -#define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) -#define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) - -/* MMDC registers addresses */ -#define MMDC_MDCTL_OFFSET (0x000) -#define MMDC_MDPDC_OFFSET (0x004) -#define MMDC_MDOTC_OFFSET (0x008) -#define MMDC_MDCFG0_OFFSET (0x00C) -#define MMDC_MDCFG1_OFFSET (0x010) -#define MMDC_MDCFG2_OFFSET (0x014) -#define MMDC_MDMISC_OFFSET (0x018) -#define MMDC_MDSCR_OFFSET (0x01C) -#define MMDC_MDREF_OFFSET (0x020) -#define MMDC_MDRWD_OFFSET (0x02C) -#define MMDC_MDOR_OFFSET (0x030) -#define MMDC_MDMRR_OFFSET (0x034) -#define MMDC_MDCFG3LP_OFFSET (0x038) -#define MMDC_MDMR4_OFFSET (0x03C) -#define MMDC_MDASP_OFFSET (0x040) - -#define MMDC_MAARCR_OFFSET (0x400) -#define MMDC_MAPSR_OFFSET (0x404) -#define MMDC_MAEXIDR0_OFFSET (0x408) -#define MMDC_MAEXIDR1_OFFSET (0x40C) -#define MMDC_MADPCR0_OFFSET (0x410) -#define MMDC_MADPCR1_OFFSET (0x414) -#define MMDC_MADPSR0_OFFSET (0x418) -#define MMDC_MADPSR1_OFFSET (0x41C) -#define MMDC_MADPSR2_OFFSET (0x420) -#define MMDC_MADPSR3_OFFSET (0x424) -#define MMDC_MADPSR4_OFFSET (0x428) -#define MMDC_MADPSR5_OFFSET (0x42C) -#define MMDC_MASBS0_OFFSET (0x430) -#define MMDC_MASBS1_OFFSET (0x434) -#define MMDC_MAGENP_OFFSET (0x440) - -#define MMDC_MPZQHWCTRL_OFFSET (0x800) -#define MMDC_MPZQSWCTRL_OFFSET (0x804) -#define MMDC_MPWLGCR_OFFSET (0x808) -#define MMDC_MPWLDECTRL0_OFFSET (0x80C) -#define MMDC_MPWLDECTRL1_OFFSET (0x810) -#define MMDC_MPWLDLST_OFFSET (0x814) -#define MMDC_MPODTCTRL_OFFSET (0x818) -#define MMDC_MPREDQBY0DL_OFFSET (0x81C) -#define MMDC_MPREDQBY1DL_OFFSET (0x820) -#define MMDC_MPREDQBY2DL_OFFSET (0x824) -#define MMDC_MPREDQBY3DL_OFFSET (0x828) -#define MMDC_MPWRDQBY0DL_OFFSET (0x82C) -#define MMDC_MPWRDQBY1DL_OFFSET (0x830) -#define MMDC_MPWRDQBY2DL_OFFSET (0x834) -#define MMDC_MPWRDQBY3DL_OFFSET (0x838) -#define MMDC_MPDGCTRL0_OFFSET (0x83C) -#define MMDC_MPDGCTRL1_OFFSET (0x840) -#define MMDC_MPDGDLST_OFFSET (0x844) -#define MMDC_MPRDDLCTL_OFFSET (0x848) -#define MMDC_MPRDDLST_OFFSET (0x84C) -#define MMDC_MPWRDLCTL_OFFSET (0x850) -#define MMDC_MPWRDLST_OFFSET (0x854) -#define MMDC_MPSDCTRL_OFFSET (0x858) -#define MMDC_MPZQLP2CTL_OFFSET (0x85C) -#define MMDC_MPRDDLHWCTL_OFFSET (0x860) -#define MMDC_MPWRDLHWCTL_OFFSET (0x864) -#define MMDC_MPRDDLHWST0_OFFSET (0x868) -#define MMDC_MPRDDLHWST1_OFFSET (0x86C) -#define MMDC_MPWRDLHWST0_OFFSET (0x870) -#define MMDC_MPWRDLHWST1_OFFSET (0x874) -#define MMDC_MPWLHWERR_OFFSET (0x878) -#define MMDC_MPDGHWST0_OFFSET (0x87C) -#define MMDC_MPDGHWST1_OFFSET (0x880) -#define MMDC_MPDGHWST2_OFFSET (0x884) -#define MMDC_MPDGHWST3_OFFSET (0x888) -#define MMDC_MPPDCMPR1_OFFSET (0x88C) -#define MMDC_MPPDCMPR2_OFFSET (0x890) -#define MMDC_MPSWDAR_OFFSET (0x894) -#define MMDC_MPSWDRDR0_OFFSET (0x898) -#define MMDC_MPSWDRDR1_OFFSET (0x89C) -#define MMDC_MPSWDRDR2_OFFSET (0x8A0) -#define MMDC_MPSWDRDR3_OFFSET (0x8A4) -#define MMDC_MPSWDRDR4_OFFSET (0x8A8) -#define MMDC_MPSWDRDR5_OFFSET (0x8AC) -#define MMDC_MPSWDRDR6_OFFSET (0x8B0) -#define MMDC_MPSWDRDR7_OFFSET (0x8B4) -#define MMDC_MPMUR_OFFSET (0x8B8) -#define MMDC_MPWRCADL_OFFSET (0x8BC) -#define MMDC_MPDCCR_OFFSET (0x8C0) -#define MMDC_MPBC_OFFSET (0x8C4) -#define MMDC_MPSWDRAR_OFFSET (0x8C8) - -/* First MMDC invalid IPS address */ -#define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) -#define MMDC_REGS_BASE MMDC0_RBASE - -#define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) -#define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) -#define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) -#define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) -#define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) -#define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) -#define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) -#define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) -#define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) -#define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) -#define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) -#define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) -#define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) -#define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) -#define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) - -#define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) -#define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) -#define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) -#define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) -#define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) -#define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) -#define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) -#define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) -#define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) -#define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) -#define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) -#define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) -#define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) -#define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) -#define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) - -#define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) -#define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) -#define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) -#define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) -#define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) -#define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) -#define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) -#define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) -#define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) -#define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) -#define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) -#define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) -#define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) -#define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) -#define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) -#define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) -#define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) -#define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) -#define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) -#define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) -#define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) -#define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) -#define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) -#define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) -#define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) -#define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) -#define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) -#define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) -#define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) -#define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) -#define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) -#define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) -#define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) -#define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) -#define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) -#define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) -#define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) -#define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) -#define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) -#define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) -#define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) -#define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) -#define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) -#define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) -#define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) -#define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) -#define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) -#define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) -#define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) -#define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) -#define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) - -/* MMDC registers bit defines */ -#define MMDC_MDCTL_SDE_0 (31) -#define MMDC_MDCTL_SDE_1 (30) -#define MMDC_MDCTL_ROW (24) -#define MMDC_MDCTL_COL (20) -#define MMDC_MDCTL_BL (19) -#define MMDC_MDCTL_DSIZ (16) - -/* MDMISC */ -#define MMDC_MDMISC_CS0_RDY (31) -#define MMDC_MDMISC_CS1_RDY (30) -#define MMDC_MDMISC_CK1_DEL (22) -#define MMDC_MDMISC_CK1_GATING (21) -#define MMDC_MDMISC_CALIB_PER_CS (20) -#define MMDC_MDMISC_ADDR_MIRROR (19) -#define MMDC_MDMISC_LHD (18) -#define MMDC_MDMISC_WALAT (16) -#define MMDC_MDMISC_BI (12) -#define MMDC_MDMISC_LPDDR2_S (11) -#define MMDC_MDMISC_MIF3_MODE (9) -#define MMDC_MDMISC_RALAT (6) -#define MMDC_MDMISC_DDR_4_BANK (5) -#define MMDC_MDMISC_DDR_TYPE (3) -#define MMDC_MDMISC_RST (1) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_WL_HW_ERR (8) - -/* MDSCR */ -#define MMDC_MDSCR_CMD_ADDR_MSB (24) -#define MMDC_MDSCR_MR_OP (24) -#define MMDC_MDSCR_CMD_ADDR_LSB (16) -#define MMDC_MDSCR_MR_ADDR (16) -#define MMDC_MDSCR_CON_REQ (15) -#define MMDC_MDSCR_CON_ACK (14) -#define MMDC_MDSCR_MRR_READ_DATA_VALID (10) -#define MMDC_MDSCR_WL_EN (9) -#define MMDC_MDSCR_CMD (4) -#define MMDC_MDSCR_CMD_CS (3) -#define MMDC_MDSCR_CMD_BA (0) - -/* MPZQHWCTRL */ -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) -#define MMDC_MPZQHWCTRL_ZQ_MODE (0) - -/* MPZQSWCTRL */ -#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) -#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) -#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) -#define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) -#define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) - -/* MPDGCTRL0 */ -#define MMDC_MPDGCTRL0_RST_RD_FIFO (31) -#define MMDC_MPDGCTRL0_DG_CMP_CYC (30) -#define MMDC_MPDGCTRL0_DG_DIS (29) -#define MMDC_MPDGCTRL0_HW_DG_EN (28) -#define MMDC_MPDGCTRL0_HW_DG_ERR (12) - -/* MPRDDLHWCTL */ -#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) - -/* MPWRDLHWCTL */ -#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) - -/* MPSWDAR */ -#define MMDC_MPSWDAR_TEST_DUMMY_EN (6) -#define MMDC_MPSWDAR_SW_DUM_CMP3 (5) -#define MMDC_MPSWDAR_SW_DUM_CMP2 (4) -#define MMDC_MPSWDAR_SW_DUM_CMP1 (3) -#define MMDC_MPSWDAR_SW_DUM_CMP0 (2) -#define MMDC_MPSWDAR_SW_DUMMY_RD (1) -#define MMDC_MPSWDAR_SW_DUMMY_WR (0) - -/* MADPCR0 */ -#define MMDC_MADPCR0_SBS (9) -#define MMDC_MADPCR0_SBS_EN (8) - -/* MASBS1 */ -#define MMDC_MASBS1_SBS_VLD (0) -#define MMDC_MASBS1_SBS_TYPE (1) - -/* MDREF */ -#define MMDC_MDREF_REF_CNT (16) -#define MMDC_MDREF_REF_SEL (14) -#define MMDC_MDREF_REFR (11) -#define MMDC_MDREF_START_REF (0) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_HW_WL_EN (0) - -/* MPBC */ -#define MMDC_MPBC_BIST_DM_LP_EN (0) -#define MMDC_MPBC_BIST_CA0_LP_EN (1) -#define MMDC_MPBC_BIST_DQ0_LP_EN (3) -#define MMDC_MPBC_BIST_DQ1_LP_EN (4) -#define MMDC_MPBC_BIST_DQ2_LP_EN (5) -#define MMDC_MPBC_BIST_DQ3_LP_EN (6) - -/* MPMUR */ -#define MMDC_MPMUR_FRC_MSR (11) - -/* MPODTCTRL */ -#define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) -#define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) -#define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) -#define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) - -/* MAPSR */ -#define MMDC_MAPSR_DVACK (25) -#define MMDC_MAPSR_LPACK (24) -#define MMDC_MAPSR_DVFS (21) -#define MMDC_MAPSR_LPMD (20) - -/* MAARCR */ -#define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) - -/* MPZQLP2CTL */ -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) - -/* MDCFG3LP */ -#define MMDC_MDCFG3LP_tRC_LP (16) -#define MMDC_MDCFG3LP_tRCD_LP (8) -#define MMDC_MDCFG3LP_tRPpb_LP (4) -#define MMDC_MDCFG3LP_tRPab_LP (0) - -/* MDOR */ -#define MMDC_MDOR_tXPR (16) -#define MMDC_MDOR_SDE_to_RST (8) -#define MMDC_MDOR_RST_to_CKE (0) - -/* MDCFG0 */ -#define MMDC_MDCFG0_tRFC (24) -#define MMDC_MDCFG0_tXS (16) -#define MMDC_MDCFG0_tXP (13) -#define MMDC_MDCFG0_tXPDLL (9) -#define MMDC_MDCFG0_tFAW (4) -#define MMDC_MDCFG0_tCL (0) - -/* MDCFG1 */ -#define MMDC_MDCFG1_tRCD (29) -#define MMDC_MDCFG1_tRP (26) -#define MMDC_MDCFG1_tRC (21) -#define MMDC_MDCFG1_tRAS (16) -#define MMDC_MDCFG1_tRPA (15) -#define MMDC_MDCFG1_tWR (9) -#define MMDC_MDCFG1_tMRD (5) -#define MMDC_MDCFG1_tCWL (0) - -/* MDCFG2 */ -#define MMDC_MDCFG2_tDLLK (16) -#define MMDC_MDCFG2_tRTP (6) -#define MMDC_MDCFG2_tWTR (3) -#define MMDC_MDCFG2_tRRD (0) - -/* MDRWD */ -#define MMDC_MDRWD_tDAI (16) -#define MMDC_MDRWD_RTW_SAME (12) -#define MMDC_MDRWD_WTR_DIFF (9) -#define MMDC_MDRWD_WTW_DIFF (6) -#define MMDC_MDRWD_RTW_DIFF (3) -#define MMDC_MDRWD_RTR_DIFF (0) - -/* MDPDC */ -#define MMDC_MDPDC_PRCT_1 (28) -#define MMDC_MDPDC_PRCT_0 (24) -#define MMDC_MDPDC_tCKE (16) -#define MMDC_MDPDC_PWDT_1 (12) -#define MMDC_MDPDC_PWDT_0 (8) -#define MMDC_MDPDC_SLOW_PD (7) -#define MMDC_MDPDC_BOTH_CS_PD (6) -#define MMDC_MDPDC_tCKSRX (3) -#define MMDC_MDPDC_tCKSRE (0) - -/* MDASP */ -#define MMDC_MDASP_CS0_END (0) - -/* MAEXIDR0 */ -#define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) -#define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) - -/* MAEXIDR1 */ -#define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) -#define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) - -/* MPWRDLCTL */ -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) - -/* MPRDDLCTL */ -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) - -/* MPWRDQBY0DL */ -#define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) -#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) -#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) -#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) -#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) -#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) -#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) -#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) -#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) - -/* MPWRDQBY1DL */ -#define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) -#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) -#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) -#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) -#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) -#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) -#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) -#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) -#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) - -/* MPWRDQBY2DL */ -#define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) -#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) -#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) -#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) -#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) -#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) -#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) -#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) -#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) - -/* MPWRDQBY3DL */ -#define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) -#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) -#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) -#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) -#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) -#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) -#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) -#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) -#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) - -/* Fields masks */ -#define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) -#define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) -#define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) -#define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) -#define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) -#define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) - -/* MDMISC */ -#define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) -#define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) -#define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) -#define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) -#define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) -#define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) -#define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) -#define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) -#define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) -#define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) -#define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) -#define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) -#define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) -#define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) -#define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) - -/* MDSCR */ -#define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) -#define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) -#define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) -#define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) -#define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) -#define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) -#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) -#define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) -#define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) -#define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) -#define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) - -/* MPZQHWCTRL */ -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) -#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) - -/* MPZQSWCTRL */ -#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) -#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) -#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) - -/* MPDGCTRL0 */ -#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) -#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) -#define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) -#define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) -#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) - -/* MPRDDLHWCTL */ -#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) - -/* MPWRDLHWCTL */ -#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) - -/* MPSWDAR */ -#define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) -#define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) -#define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) -#define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) -#define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) -#define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) -#define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) - -/* MADPCR0 */ -#define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) -#define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) - -/* MASBS1 */ -#define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) -#define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) - -/* MDREF */ -#define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) -#define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) -#define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) -#define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) - -/* MPBC */ -#define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) -#define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) -#define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) -#define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) -#define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) -#define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) -#define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) - -/* MPMUR */ -#define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) - -/* MPODTCTRL */ -#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) -#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) -#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) -#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) - -/* MAPSR */ -#define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) -#define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) -#define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) -#define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) - -/* MAARCR */ -#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) - -/* MPZQLP2CTL */ -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) - -/* MDCFG3LP */ -#define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) -#define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) -#define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) -#define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) - -/* MDOR */ -#define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) -#define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) -#define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) - -/* MDCFG0 */ -#define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) -#define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) -#define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) -#define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) -#define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) -#define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) - -/* MDCFG1 */ -#define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) -#define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) -#define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) -#define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) -#define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) -#define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) -#define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) -#define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) - -/* MDCFG2 */ -#define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) -#define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) -#define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) -#define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) - -/* MDRWD */ -#define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) -#define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) -#define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) -#define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) -#define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) -#define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) - -/* MDPDC */ -#define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) -#define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) -#define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) -#define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) -#define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) -#define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) -#define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) -#define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) -#define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) - -/* MDASP */ -#define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) - -/* MAEXIDR0 */ -#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) -#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) - -/* MAEXIDR1 */ -#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) -#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) - -/* MPWRDLCTL */ -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) - -/* MPRDDLCTL */ -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) - -/* MPWRDQBY0DL */ -#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) - -/* MPWRDQBY1DL */ -#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) - -/* MPWRDQBY2DL */ -#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) - -/* MPWRDQBY3DL */ -#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) - -#define SNVS_LPCR_DPEN (0x20) -#define SNVS_LPCR_SRTC_ENV (0x1) - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) - -#include <asm/types.h> - -struct fuse_word { - u32 fuse; - u32 rsvd[3]; -}; - -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 pdn; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[3]; - u32 sw_sticky; - u32 rsvd4[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 out_status; - u32 out_status_set; - u32 out_status_clr; - u32 out_status_tog; - u32 startword; - u32 rsvd5[3]; - u32 version; - u32 rsvd6[19]; - struct fuse_word mem_repair[8]; - u32 rsvd7[0xa8]; - - /* fuse banks */ - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[0]; -}; - -struct fuse_bank1_regs { - u32 lock0; - u32 rsvd0[3]; - u32 lock1; - u32 rsvd1[3]; - u32 lock2; - u32 rsvd2[3]; - u32 cfg0; - u32 rsvd3[3]; - u32 cfg1; - u32 rsvd4[3]; - u32 cfg2; - u32 rsvd5[3]; - u32 cfg3; - u32 rsvd6[3]; - u32 cfg4; - u32 rsvd7[3]; -}; - -struct fuse_bank2_regs { - struct fuse_word boot[8]; -}; - -struct fuse_bank3_regs { - u32 mem0; - u32 rsvd0[3]; - u32 mem1; - u32 rsvd1[3]; - u32 mem2; - u32 rsvd2[3]; - u32 mem3; - u32 rsvd3[3]; - u32 ana0; - u32 rsvd4[3]; - u32 ana1; - u32 rsvd5[3]; - u32 ana2; - u32 rsvd6[3]; - u32 ana3; - u32 rsvd7[3]; -}; - -struct fuse_bank7_regs { - u32 sjc_resp0; - u32 rsvd0[3]; - u32 sjc_resp1; - u32 rsvd1[3]; - u32 gp0; - u32 rsvd2[3]; - u32 gp1; - u32 rsvd3[3]; - u32 gp2; - u32 rsvd4[3]; - u32 gp3; - u32 rsvd5[3]; - u32 gp4; - u32 rsvd6[3]; - u32 gp5; - u32 rsvd7[3]; -}; - -struct usbphy_regs { - u32 usbphy_pwd; /* 0x000 */ - u32 usbphy_pwd_set; /* 0x004 */ - u32 usbphy_pwd_clr; /* 0x008 */ - u32 usbphy_pwd_tog; /* 0x00c */ - u32 usbphy_tx; /* 0x010 */ - u32 usbphy_tx_set; /* 0x014 */ - u32 usbphy_tx_clr; /* 0x018 */ - u32 usbphy_tx_tog; /* 0x01c */ - u32 usbphy_rx; /* 0x020 */ - u32 usbphy_rx_set; /* 0x024 */ - u32 usbphy_rx_clr; /* 0x028 */ - u32 usbphy_rx_tog; /* 0x02c */ - u32 usbphy_ctrl; /* 0x030 */ - u32 usbphy_ctrl_set; /* 0x034 */ - u32 usbphy_ctrl_clr; /* 0x038 */ - u32 usbphy_ctrl_tog; /* 0x03c */ - u32 usbphy_status; /* 0x040 */ - u32 reserved0[3]; - u32 usbphy_debug0; /* 0x050 */ - u32 usbphy_debug0_set; /* 0x054 */ - u32 usbphy_debug0_clr; /* 0x058 */ - u32 usbphy_debug0_tog; /* 0x05c */ - u32 reserved1[4]; - u32 usbphy_debug1; /* 0x070 */ - u32 usbphy_debug1_set; /* 0x074 */ - u32 usbphy_debug1_clr; /* 0x078 */ - u32 usbphy_debug1_tog; /* 0x07c */ - u32 usbphy_version; /* 0x080 */ - u32 reserved2[7]; - u32 usb1_pll_480_ctrl; /* 0x0a0 */ - u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ - u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ - u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ - u32 reserved3[4]; - u32 usb1_vbus_detect; /* 0xc0 */ - u32 usb1_vbus_detect_set; /* 0xc4 */ - u32 usb1_vbus_detect_clr; /* 0xc8 */ - u32 usb1_vbus_detect_tog; /* 0xcc */ - u32 usb1_vbus_det_stat; /* 0xd0 */ - u32 reserved4[3]; - u32 usb1_chrg_detect; /* 0xe0 */ - u32 usb1_chrg_detect_set; /* 0xe4 */ - u32 usb1_chrg_detect_clr; /* 0xe8 */ - u32 usb1_chrg_detect_tog; /* 0xec */ - u32 usb1_chrg_det_stat; /* 0xf0 */ - u32 reserved5[3]; - u32 usbphy_anactrl; /* 0x100 */ - u32 usbphy_anactrl_set; /* 0x104 */ - u32 usbphy_anactrl_clr; /* 0x108 */ - u32 usbphy_anactrl_tog; /* 0x10c */ - u32 usb1_loopback; /* 0x110 */ - u32 usb1_loopback_set; /* 0x114 */ - u32 usb1_loopback_clr; /* 0x118 */ - u32 usb1_loopback_tog; /* 0x11c */ - u32 usb1_loopback_hsfscnt; /* 0x120 */ - u32 usb1_loopback_hsfscnt_set; /* 0x124 */ - u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ - u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ - u32 usphy_trim_override_en; /* 0x130 */ - u32 usphy_trim_override_en_set; /* 0x134 */ - u32 usphy_trim_override_en_clr; /* 0x138 */ - u32 usphy_trim_override_en_tog; /* 0x13c */ - u32 usb1_pfda_ctrl1; /* 0x140 */ - u32 usb1_pfda_ctrl1_set; /* 0x144 */ - u32 usb1_pfda_ctrl1_clr; /* 0x148 */ - u32 usb1_pfda_ctrl1_tog; /* 0x14c */ -}; - -struct bootrom_sw_info { - u8 reserved_1; - u8 boot_dev_instance; - u8 boot_dev_type; - u8 reserved_2; - u32 core_freq; - u32 axi_freq; - u32 ddr_freq; - u32 rom_tick_freq; - u32 reserved_3[3]; -}; - -#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) -#define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) - -#endif - -#endif /* _MX7ULP_REGS_H_*/ diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h deleted file mode 100644 index f067c02..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/iomux.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Based on Linux i.MX iomux-v3.h file: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __MACH_IOMUX_H__ -#define __MACH_IOMUX_H__ - -/* - * build IOMUX_PAD structure - * - * This iomux scheme is based around pads, which are the physical balls - * on the processor. - * - * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls - * things like driving strength and pullup/pulldown. - * - Each pad can have but not necessarily does have an output routing register - * (IOMUXC_SW_MUX_CTL_PAD_x). - * - Each pad can have but not necessarily does have an input routing register - * (IOMUXC_x_SELECT_INPUT) - * - * The three register sets do not have a fixed offset to each other, - * hence we order this table by pad control registers (which all pads - * have) and put the optional i/o routing registers into additional - * fields. - * - * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * - * IOMUX/PAD Bit field definitions - * - * MUX_CTRL_OFS: 0..15 (16) - * SEL_INPUT_OFS: 16..31 (16) - * MUX_MODE: 32..37 (6) - * SEL_INP: 38..41 (4) - * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) - * reserved: 61-63 (3) -*/ - -typedef u64 iomux_cfg_t; - -#define MUX_CTRL_OFS_SHIFT 0 -#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) -#define MUX_SEL_INPUT_OFS_SHIFT 16 -#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ - MUX_SEL_INPUT_OFS_SHIFT) - -#define MUX_MODE_SHIFT 32 -#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) -#define MUX_SEL_INPUT_SHIFT 38 -#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) -#define MUX_PAD_CTRL_SHIFT 42 -#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) - -#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) - -#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ - sel_input, pad_ctrl) \ - (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ - ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ - ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ - ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ - ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) - -#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ - MUX_PAD_CTRL(pad)) - - -#define IOMUX_CONFIG_MPORTS 0x20 -#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ - MUX_MODE_SHIFT) - -/* Bit definition below needs to be fixed acccording to ulp rm */ - -#define NO_PAD_CTRL (1 << 18) -#define PAD_CTL_OBE_ENABLE (1 << 17) -#define PAD_CTL_IBE_ENABLE (1 << 16) -#define PAD_CTL_DSE (1 << 6) -#define PAD_CTL_ODE (1 << 5) -#define PAD_CTL_SRE_FAST (0 << 2) -#define PAD_CTL_SRE_SLOW (1 << 2) -#define PAD_CTL_PUE (1 << 1) -#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) -#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) - - -void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); -void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, - unsigned count); -#endif /* __MACH_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h deleted file mode 100644 index 139b766..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h +++ /dev/null @@ -1,909 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX7ULP_PINS_H__ -#define __ASM_ARCH_IMX7ULP_PINS_H__ - -#include <asm/arch/iomux.h> - -enum { - MX7ULP_PAD_PTA0__CMP0_IN1_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA0__PTA0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA0__LPSPI0_PCS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0), - MX7ULP_PAD_PTA0__LPUART0_CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), - MX7ULP_PAD_PTA0__LPI2C0_SCL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0), - MX7ULP_PAD_PTA0__TPM0_CLKIN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0), - MX7ULP_PAD_PTA0__I2S0_RX_BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0), - MX7ULP_PAD_PTA0__LLWU0_P0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__CMP0_IN2_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__PTA1 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__LPSPI0_PCS2 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0), - MX7ULP_PAD_PTA1__LPUART0_RTS_b = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__LPI2C0_SDA = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0), - MX7ULP_PAD_PTA1__TPM0_CH0 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0), - MX7ULP_PAD_PTA1__I2S0_RX_FS = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0), - MX7ULP_PAD_PTA2__CMP1_IN2_3V = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA2__PTA2 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA2__LPSPI0_PCS3 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x1, 0), - MX7ULP_PAD_PTA2__LPUART0_TX = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x1, 0), - MX7ULP_PAD_PTA2__LPI2C0_HREQ = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x1, 0), - MX7ULP_PAD_PTA2__TPM0_CH1 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x1, 0), - MX7ULP_PAD_PTA2__I2S0_RXD0 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x1, 0), - MX7ULP_PAD_PTA3__CMP1_IN4_3V = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA3__PTA3 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA3__LPSPI0_PCS0 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x1, 0), - MX7ULP_PAD_PTA3__LPUART0_RX = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x1, 0), - MX7ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x1, 0), - MX7ULP_PAD_PTA3__I2S0_RXD1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x1, 0), - MX7ULP_PAD_PTA3__CMP0_OUT = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA3__LLWU0_P1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA4__ADC1_CH3A = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA4__PTA4 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA4__LPSPI0_SIN = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0), - MX7ULP_PAD_PTA4__LPUART1_CTS_b = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), - MX7ULP_PAD_PTA4__LPI2C1_SCL = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0), - MX7ULP_PAD_PTA4__TPM0_CH3 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0), - MX7ULP_PAD_PTA4__I2S0_MCLK = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0), - MX7ULP_PAD_PTA5__ADC1_CH3B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA5__PTA5 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA5__LPSPI0_SOUT = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0), - MX7ULP_PAD_PTA5__LPUART1_RTS_b = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA5__LPI2C1_SDA = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0), - MX7ULP_PAD_PTA5__TPM0_CH4 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0), - MX7ULP_PAD_PTA5__I2S0_TX_BCLK = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0), - MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA6__PTA6 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA6__LPSPI0_SCK = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0), - MX7ULP_PAD_PTA6__LPUART1_TX = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0), - MX7ULP_PAD_PTA6__LPI2C1_HREQ = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0), - MX7ULP_PAD_PTA6__TPM0_CH5 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0), - MX7ULP_PAD_PTA6__I2S0_TX_FS = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0), - MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA7__PTA7 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA7__LPUART1_RX = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0), - MX7ULP_PAD_PTA7__TPM1_CH1 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0), - MX7ULP_PAD_PTA7__I2S0_TXD0 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__PTA8 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__LPSPI1_PCS1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0), - MX7ULP_PAD_PTA8__LPUART2_CTS_b = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), - MX7ULP_PAD_PTA8__LPI2C2_SCL = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0), - MX7ULP_PAD_PTA8__TPM1_CLKIN = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0), - MX7ULP_PAD_PTA8__I2S0_TXD1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__PTA9 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__LPSPI1_PCS2 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0), - MX7ULP_PAD_PTA9__LPUART2_RTS_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__LPI2C2_SDA = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0), - MX7ULP_PAD_PTA9__TPM1_CH0 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0), - MX7ULP_PAD_PTA9__NMI0_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__PTA10 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__LPSPI1_PCS3 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0), - MX7ULP_PAD_PTA10__LPUART2_TX = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0), - MX7ULP_PAD_PTA10__LPI2C2_HREQ = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0), - MX7ULP_PAD_PTA10__TPM2_CLKIN = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0), - MX7ULP_PAD_PTA10__I2S0_RX_BCLK = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0), - MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA11__PTA11 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA11__LPUART2_RX = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0), - MX7ULP_PAD_PTA11__TPM2_CH0 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0), - MX7ULP_PAD_PTA11__I2S0_RX_FS = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0), - MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA12__PTA12 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA12__LPSPI1_SIN = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0), - MX7ULP_PAD_PTA12__LPUART3_CTS_b = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), - MX7ULP_PAD_PTA12__LPI2C3_SCL = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0), - MX7ULP_PAD_PTA12__TPM2_CH1 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0), - MX7ULP_PAD_PTA12__I2S0_RXD0 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0), - MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__PTA13 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__LPSPI1_SOUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0), - MX7ULP_PAD_PTA13__LPUART3_RTS_b = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__LPI2C3_SDA = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0), - MX7ULP_PAD_PTA13__TPM3_CLKIN = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0), - MX7ULP_PAD_PTA13__I2S0_RXD1 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0), - MX7ULP_PAD_PTA13__CMP0_OUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__LLWU0_P2 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__PTA14 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__LPSPI1_SCK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0), - MX7ULP_PAD_PTA14__LPUART3_TX = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0), - MX7ULP_PAD_PTA14__LPI2C3_HREQ = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x2, 0), - MX7ULP_PAD_PTA14__TPM3_CH0 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0), - MX7ULP_PAD_PTA14__I2S0_MCLK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0), - MX7ULP_PAD_PTA14__LLWU0_P3 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__PTA15 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__LPSPI1_PCS0 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0), - MX7ULP_PAD_PTA15__LPUART3_RX = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0), - MX7ULP_PAD_PTA15__TPM3_CH1 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x1, 0), - MX7ULP_PAD_PTA15__I2S0_TX_BCLK = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x2, 0), - MX7ULP_PAD_PTA16__CMP1_IN5_3V = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA16__PTA16 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA16__FXIO0_D0 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA16__LPSPI0_SOUT = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0), - MX7ULP_PAD_PTA16__LPUART0_CTS_b = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), - MX7ULP_PAD_PTA16__LPI2C0_SCL = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0), - MX7ULP_PAD_PTA16__TPM3_CH2 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0), - MX7ULP_PAD_PTA16__I2S0_TX_FS = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0), - MX7ULP_PAD_PTA17__CMP1_IN6_3V = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__PTA17 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__FXIO0_D1 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__LPSPI0_SCK = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0), - MX7ULP_PAD_PTA17__LPUART0_RTS_b = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__LPI2C0_SDA = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0), - MX7ULP_PAD_PTA17__TPM3_CH3 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0), - MX7ULP_PAD_PTA17__I2S0_TXD0 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__CMP1_IN1_3V = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__PTA18 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__FXIO0_D2 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__LPSPI0_PCS0 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x2, 0), - MX7ULP_PAD_PTA18__LPUART0_TX = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x2, 0), - MX7ULP_PAD_PTA18__LPI2C0_HREQ = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x2, 0), - MX7ULP_PAD_PTA18__TPM3_CH4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x1, 0), - MX7ULP_PAD_PTA18__I2S0_TXD1 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__LLWU0_P4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__CMP1_IN3_3V = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__PTA19 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__FXIO0_D3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__LPUART0_RX = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x2, 0), - MX7ULP_PAD_PTA19__TPM3_CH5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x1, 0), - MX7ULP_PAD_PTA19__I2S1_RX_BCLK = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0), - MX7ULP_PAD_PTA19__LPTMR0_ALT3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__LLWU0_P5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__PTA20 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__FXIO0_D4 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__LPSPI0_SIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0), - MX7ULP_PAD_PTA20__LPUART1_CTS_b = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), - MX7ULP_PAD_PTA20__LPI2C1_SCL = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0), - MX7ULP_PAD_PTA20__TPM0_CLKIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0), - MX7ULP_PAD_PTA20__I2S1_RX_FS = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0), - MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__PTA21 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__FXIO0_D5 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__LPSPI0_PCS1 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0), - MX7ULP_PAD_PTA21__LPUART1_RTS_b = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__LPI2C1_SDA = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0), - MX7ULP_PAD_PTA21__TPM0_CH0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0), - MX7ULP_PAD_PTA21__I2S1_RXD0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0), - MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__PTA22 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__FXIO0_D6 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__LPSPI0_PCS2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0), - MX7ULP_PAD_PTA22__LPUART1_TX = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x2, 0), - MX7ULP_PAD_PTA22__LPI2C1_HREQ = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x2, 0), - MX7ULP_PAD_PTA22__TPM0_CH1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0), - MX7ULP_PAD_PTA22__I2S1_RXD1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0), - MX7ULP_PAD_PTA22__LPTMR0_ALT2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__EWM_OUT_b = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__PTA23 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__FXIO0_D7 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__LPSPI0_PCS3 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0), - MX7ULP_PAD_PTA23__LPUART1_RX = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x2, 0), - MX7ULP_PAD_PTA23__TPM0_CH2 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0), - MX7ULP_PAD_PTA23__I2S1_MCLK = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0), - MX7ULP_PAD_PTA23__LLWU0_P6 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__PTA24 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__FXIO0_D8 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__LPSPI1_PCS1 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0), - MX7ULP_PAD_PTA24__LPUART2_CTS_b = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), - MX7ULP_PAD_PTA24__LPI2C2_SCL = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0), - MX7ULP_PAD_PTA24__TPM0_CH3 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0), - MX7ULP_PAD_PTA24__I2S1_TX_BCLK = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0), - MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__PTA25 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__FXIO0_D9 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__LPSPI1_PCS2 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0), - MX7ULP_PAD_PTA25__LPUART2_RTS_b = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__LPI2C2_SDA = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0), - MX7ULP_PAD_PTA25__TPM0_CH4 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0), - MX7ULP_PAD_PTA25__I2S1_TX_FS = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0), - MX7ULP_PAD_PTA26__PTA26 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA26__FXIO0_D10 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA26__LPSPI1_PCS3 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x2, 0), - MX7ULP_PAD_PTA26__LPUART2_TX = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x2, 0), - MX7ULP_PAD_PTA26__LPI2C2_HREQ = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x2, 0), - MX7ULP_PAD_PTA26__TPM0_CH5 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x2, 0), - MX7ULP_PAD_PTA26__I2S1_RXD2 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x1, 0), - MX7ULP_PAD_PTA27__PTA27 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA27__JTAG_TDO = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA27__FXIO0_D11 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA27__LPUART2_RX = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x2, 0), - MX7ULP_PAD_PTA27__TPM1_CH1 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x2, 0), - MX7ULP_PAD_PTA27__I2S1_RXD3 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x1, 0), - MX7ULP_PAD_PTA28__PTA28 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA28__JTAG_TDI = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA28__FXIO0_D12 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA28__LPSPI1_SIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0), - MX7ULP_PAD_PTA28__LPUART3_CTS_b = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), - MX7ULP_PAD_PTA28__LPI2C3_SCL = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0), - MX7ULP_PAD_PTA28__TPM1_CLKIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0), - MX7ULP_PAD_PTA28__I2S1_TXD2 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__PTA29 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__FXIO0_D13 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__LPSPI1_SOUT = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0), - MX7ULP_PAD_PTA29__LPUART3_RTS_b = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__LPI2C3_SDA = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0), - MX7ULP_PAD_PTA29__TPM1_CH0 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0), - MX7ULP_PAD_PTA29__I2S1_TXD3 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__ADC0_CH1A = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__PTA30 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__FXIO0_D14 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__LPSPI1_SCK = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x1, 0), - MX7ULP_PAD_PTA30__LPUART3_TX = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x1, 0), - MX7ULP_PAD_PTA30__LPI2C3_HREQ = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0), - MX7ULP_PAD_PTA30__TPM2_CLKIN = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0), - MX7ULP_PAD_PTA30__I2S1_TXD0 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__JTAG_TRST_b = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__ADC0_CH1B = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__PTA31 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__FXIO0_D15 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__LPSPI1_PCS0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x2, 0), - MX7ULP_PAD_PTA31__LPUART3_RX = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x2, 0), - MX7ULP_PAD_PTA31__TPM2_CH0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x2, 0), - MX7ULP_PAD_PTA31__I2S1_TXD1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__LPTMR0_ALT1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__EWM_IN = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x1, 0), - MX7ULP_PAD_PTA31__LLWU0_P7 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__ADC0_CH0A = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__PTB0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__FXIO0_D16 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__LPSPI0_SIN = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x3, 0), - MX7ULP_PAD_PTB0__LPUART0_TX = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x3, 0), - MX7ULP_PAD_PTB0__TPM2_CH1 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0), - MX7ULP_PAD_PTB0__CLKOUT0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__CMP1_OUT = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__EWM_OUT_b = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__ADC0_CH0B = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__PTB1 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__FXIO0_D17 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__LPSPI0_SOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x3, 0), - MX7ULP_PAD_PTB1__LPUART0_RX = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x3, 0), - MX7ULP_PAD_PTB1__TPM3_CLKIN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x3, 0), - MX7ULP_PAD_PTB1__I2S1_TX_BCLK = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x2, 0), - MX7ULP_PAD_PTB1__RTC_CLKOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__EWM_IN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0), - MX7ULP_PAD_PTB1__LLWU0_P8 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__PTB2 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__FXIO0_D18 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__LPSPI0_SCK = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0), - MX7ULP_PAD_PTB2__LPUART1_TX = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x3, 0), - MX7ULP_PAD_PTB2__TPM3_CH0 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0), - MX7ULP_PAD_PTB2__I2S1_TX_FS = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0), - MX7ULP_PAD_PTB2__TRACE_CLKOUT = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__PTB3 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__FXIO0_D19 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__LPSPI0_PCS0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0), - MX7ULP_PAD_PTB3__LPUART1_RX = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x3, 0), - MX7ULP_PAD_PTB3__TPM3_CH1 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x2, 0), - MX7ULP_PAD_PTB3__I2S1_TXD0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__TRACE_D0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__LPTMR1_ALT2 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__LLWU0_P9 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__PTB4 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__FXIO0_D20 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__LPSPI0_PCS1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x3, 0), - MX7ULP_PAD_PTB4__LPUART2_TX = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x3, 0), - MX7ULP_PAD_PTB4__LPI2C0_HREQ = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x3, 0), - MX7ULP_PAD_PTB4__TPM3_CH2 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x2, 0), - MX7ULP_PAD_PTB4__I2S1_TXD1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__QSPIA_DATA7 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__TRACE_D1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__PTB5 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__FXIO0_D21 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__LPSPI0_PCS2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0), - MX7ULP_PAD_PTB5__LPUART2_RX = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x3, 0), - MX7ULP_PAD_PTB5__LPI2C1_HREQ = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x3, 0), - MX7ULP_PAD_PTB5__TPM3_CH3 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x2, 0), - MX7ULP_PAD_PTB5__I2S1_TXD2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__QSPIA_DATA6 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__TRACE_D2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__ADC1_CH1A = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__PTB6 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__FXIO0_D22 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__LPSPI0_PCS3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x3, 0), - MX7ULP_PAD_PTB6__LPUART3_TX = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x3, 0), - MX7ULP_PAD_PTB6__LPI2C0_SCL = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x3, 0), - MX7ULP_PAD_PTB6__TPM3_CH4 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x2, 0), - MX7ULP_PAD_PTB6__I2S1_TXD3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__QSPIA_DATA5 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__TRACE_D3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__LPTMR1_ALT3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__LLWU0_P10 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__ADC1_CH1B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__PTB7 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__FXIO0_D23 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__LPSPI1_SIN = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x3, 0), - MX7ULP_PAD_PTB7__LPUART3_RX = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x3, 0), - MX7ULP_PAD_PTB7__LPI2C0_SDA = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x3, 0), - MX7ULP_PAD_PTB7__TPM3_CH5 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x2, 0), - MX7ULP_PAD_PTB7__I2S1_MCLK = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x2, 0), - MX7ULP_PAD_PTB7__QSPIA_SS1_B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__CMP1_OUT = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__LLWU0_P11 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__PTB8 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__FXIO0_D24 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__LPSPI1_SOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x3, 0), - MX7ULP_PAD_PTB8__LPI2C1_SCL = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x3, 0), - MX7ULP_PAD_PTB8__TPM0_CLKIN = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x3, 0), - MX7ULP_PAD_PTB8__I2S1_RX_BCLK = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x2, 0), - MX7ULP_PAD_PTB8__QSPIA_SS0_B = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__RTC_CLKOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__PTB9 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__FXIO0_D25 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__LPSPI1_SCK = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x3, 0), - MX7ULP_PAD_PTB9__LPI2C1_SDA = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x3, 0), - MX7ULP_PAD_PTB9__TPM0_CH0 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x3, 0), - MX7ULP_PAD_PTB9__I2S1_RX_FS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x2, 0), - MX7ULP_PAD_PTB9__QSPIA_DQS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__LLWU0_P12 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__CMP0_IN1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__PTB10 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__FXIO0_D26 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__LPSPI1_PCS0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x3, 0), - MX7ULP_PAD_PTB10__LPI2C2_SCL = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x3, 0), - MX7ULP_PAD_PTB10__TPM0_CH1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x3, 0), - MX7ULP_PAD_PTB10__I2S1_RXD0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x2, 0), - MX7ULP_PAD_PTB10__TRACE_D4 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__CMP0_IN3 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__PTB11 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__FXIO0_D27 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__LPSPI1_PCS1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x3, 0), - MX7ULP_PAD_PTB11__LPI2C2_SDA = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x3, 0), - MX7ULP_PAD_PTB11__TPM1_CLKIN = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x3, 0), - MX7ULP_PAD_PTB11__I2S1_RXD1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x2, 0), - MX7ULP_PAD_PTB11__TRACE_D5 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__PTB12 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__FXIO0_D28 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__LPSPI1_PCS2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0), - MX7ULP_PAD_PTB12__LPI2C3_SCL = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0), - MX7ULP_PAD_PTB12__TPM1_CH0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0), - MX7ULP_PAD_PTB12__I2S1_RXD2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0), - MX7ULP_PAD_PTB12__TRACE_D6 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__PTB13 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__FXIO0_D29 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__LPSPI1_PCS3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0), - MX7ULP_PAD_PTB13__LPI2C3_SDA = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0), - MX7ULP_PAD_PTB13__TPM1_CH1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0), - MX7ULP_PAD_PTB13__I2S1_RXD3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0), - MX7ULP_PAD_PTB13__QSPIA_DATA4 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__TRACE_D7 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__ADC1_CH2A = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__PTB14 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__FXIO0_D30 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__LPI2C2_HREQ = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0), - MX7ULP_PAD_PTB14__TPM2_CLKIN = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0), - MX7ULP_PAD_PTB14__QSPIA_SS1_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__QSPIA_SCLK_b = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__LLWU0_P13 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__ADC1_CH2B = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__PTB15 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__FXIO0_D31 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__LPI2C3_HREQ = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0), - MX7ULP_PAD_PTB15__TPM2_CH0 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0), - MX7ULP_PAD_PTB15__QSPIA_SCLK = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__PTB16 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__TPM2_CH1 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0), - MX7ULP_PAD_PTB16__QSPIA_DATA3 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__LLWU0_P14 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__PTB17 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__TPM3_CLKIN = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0), - MX7ULP_PAD_PTB17__QSPIA_DATA2 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__PTB18 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__TPM3_CH0 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0), - MX7ULP_PAD_PTB18__QSPIA_DATA1 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__PTB19 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__TPM3_CH1 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0), - MX7ULP_PAD_PTB19__QSPIA_DATA0 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__LLWU0_P15 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__PTC0 = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__LPUART4_CTS_b = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), - MX7ULP_PAD_PTC0__LPI2C4_SCL = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0), - MX7ULP_PAD_PTC0__TPM4_CLKIN = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0), - MX7ULP_PAD_PTC0__FB_AD0 = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__TRACE_D15 = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__DEBUG_MUX0 = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__PTC1 = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__LPUART4_RTS_b = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__LPI2C4_SDA = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0), - MX7ULP_PAD_PTC1__TPM4_CH0 = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0), - MX7ULP_PAD_PTC1__FB_AD1 = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__TRACE_D14 = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__DEBUG_MUX1 = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__PTC2 = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__LPUART4_TX = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0), - MX7ULP_PAD_PTC2__LPI2C4_HREQ = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0), - MX7ULP_PAD_PTC2__TPM4_CH1 = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0), - MX7ULP_PAD_PTC2__FB_AD2 = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__TRACE_D13 = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__DEBUG_MUX2 = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__PTC3 = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__LPUART4_RX = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0), - MX7ULP_PAD_PTC3__TPM4_CH2 = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0), - MX7ULP_PAD_PTC3__FB_AD3 = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__TRACE_D12 = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__DEBUG_MUX3 = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__PTC4 = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__FXIO1_D0 = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0), - MX7ULP_PAD_PTC4__LPSPI2_PCS1 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0), - MX7ULP_PAD_PTC4__LPUART5_CTS_b = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), - MX7ULP_PAD_PTC4__LPI2C5_SCL = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0), - MX7ULP_PAD_PTC4__TPM4_CH3 = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0), - MX7ULP_PAD_PTC4__FB_AD4 = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__TRACE_D11 = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__DEBUG_MUX4 = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__PTC5 = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__FXIO1_D1 = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0), - MX7ULP_PAD_PTC5__LPSPI2_PCS2 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0), - MX7ULP_PAD_PTC5__LPUART5_RTS_b = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__LPI2C5_SDA = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0), - MX7ULP_PAD_PTC5__TPM4_CH4 = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0), - MX7ULP_PAD_PTC5__FB_AD5 = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__TRACE_D10 = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__DEBUG_MUX5 = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__PTC6 = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__FXIO1_D2 = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0), - MX7ULP_PAD_PTC6__LPSPI2_PCS3 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0), - MX7ULP_PAD_PTC6__LPUART5_TX = IOMUX_PAD(0x0018, 0x0018, 0x4, 0x0258, 0x1, 0), - MX7ULP_PAD_PTC6__LPI2C5_HREQ = IOMUX_PAD(0x0018, 0x0018, 0x5, 0x02B8, 0x1, 0), - MX7ULP_PAD_PTC6__TPM4_CH5 = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0), - MX7ULP_PAD_PTC6__FB_AD6 = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__TRACE_D9 = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__DEBUG_MUX6 = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__PTC7 = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__FXIO1_D3 = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0), - MX7ULP_PAD_PTC7__LPUART5_RX = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0), - MX7ULP_PAD_PTC7__TPM5_CH1 = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0), - MX7ULP_PAD_PTC7__FB_AD7 = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__TRACE_D8 = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__DEBUG_MUX7 = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__PTC8 = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__FXIO1_D4 = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0), - MX7ULP_PAD_PTC8__LPSPI2_SIN = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0), - MX7ULP_PAD_PTC8__LPUART6_CTS_b = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), - MX7ULP_PAD_PTC8__LPI2C6_SCL = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0), - MX7ULP_PAD_PTC8__TPM5_CLKIN = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0), - MX7ULP_PAD_PTC8__FB_AD8 = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__TRACE_D7 = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__DEBUG_MUX8 = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__PTC9 = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__FXIO1_D5 = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0), - MX7ULP_PAD_PTC9__LPSPI2_SOUT = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0), - MX7ULP_PAD_PTC9__LPUART6_RTS_b = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__LPI2C6_SDA = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0), - MX7ULP_PAD_PTC9__TPM5_CH0 = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0), - MX7ULP_PAD_PTC9__FB_AD9 = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__TRACE_D6 = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__DEBUG_MUX9 = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__FXIO1_D6 = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0), - MX7ULP_PAD_PTC10__LPSPI2_SCK = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0), - MX7ULP_PAD_PTC10__LPUART6_TX = IOMUX_PAD(0x0028, 0x0028, 0x4, 0x0264, 0x1, 0), - MX7ULP_PAD_PTC10__LPI2C6_HREQ = IOMUX_PAD(0x0028, 0x0028, 0x5, 0x02F8, 0x1, 0), - MX7ULP_PAD_PTC10__TPM7_CH3 = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0), - MX7ULP_PAD_PTC10__FB_AD10 = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__TRACE_D5 = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__DEBUG_MUX10 = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__PTC11 = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__FXIO1_D7 = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0), - MX7ULP_PAD_PTC11__LPSPI2_PCS0 = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0), - MX7ULP_PAD_PTC11__LPUART6_RX = IOMUX_PAD(0x002C, 0x002C, 0x4, 0x0260, 0x1, 0), - MX7ULP_PAD_PTC11__TPM7_CH4 = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0), - MX7ULP_PAD_PTC11__FB_AD11 = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__TRACE_D4 = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__DEBUG_MUX11 = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__PTC12 = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__FXIO1_D8 = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0), - MX7ULP_PAD_PTC12__LPSPI3_PCS1 = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0), - MX7ULP_PAD_PTC12__LPUART7_CTS_b = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), - MX7ULP_PAD_PTC12__LPI2C7_SCL = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0), - MX7ULP_PAD_PTC12__TPM7_CH5 = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0), - MX7ULP_PAD_PTC12__FB_AD12 = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__TRACE_D3 = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__DEBUG_MUX12 = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__PTC13 = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__FXIO1_D9 = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0), - MX7ULP_PAD_PTC13__LPSPI3_PCS2 = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0), - MX7ULP_PAD_PTC13__LPUART7_RTS_b = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__LPI2C7_SDA = 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IOMUX_PAD(0x0198, 0x0198, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF6__VIU_D2 = IOMUX_PAD(0x0198, 0x0198, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x019C, 0x019C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF7__FXIO1_D3 = IOMUX_PAD(0x019C, 0x019C, 0x2, 0x0210, 0x2, 0), - MX7ULP_PAD_PTF7__LPUART5_RX = IOMUX_PAD(0x019C, 0x019C, 0x4, 0x0254, 0x3, 0), - MX7ULP_PAD_PTF7__TPM5_CH1 = IOMUX_PAD(0x019C, 0x019C, 0x6, 0x02C8, 0x3, 0), - MX7ULP_PAD_PTF7__FB_AD20 = IOMUX_PAD(0x019C, 0x019C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF7__VIU_D3 = IOMUX_PAD(0x019C, 0x019C, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__PTF8 = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__FXIO1_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0), - MX7ULP_PAD_PTF8__LPSPI2_SIN = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0), - MX7ULP_PAD_PTF8__LPUART6_CTS_b = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), - MX7ULP_PAD_PTF8__LPI2C6_SCL = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0), - MX7ULP_PAD_PTF8__TPM5_CLKIN = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0), - MX7ULP_PAD_PTF8__FB_AD21 = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__USB1_ULPI_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__VIU_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__PTF9 = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__FXIO1_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0), - MX7ULP_PAD_PTF9__LPSPI2_SOUT = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0), - MX7ULP_PAD_PTF9__LPUART6_RTS_b = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__LPI2C6_SDA = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0), - MX7ULP_PAD_PTF9__TPM5_CH0 = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0), - MX7ULP_PAD_PTF9__FB_AD22 = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__USB1_ULPI_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__VIU_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__PTF10 = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__FXIO1_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0), - MX7ULP_PAD_PTF10__LPSPI2_SCK = IOMUX_PAD(0x01A8, 0x01A8, 0x3, 0x02AC, 0x3, 0), - MX7ULP_PAD_PTF10__LPUART6_TX = IOMUX_PAD(0x01A8, 0x01A8, 0x4, 0x0264, 0x3, 0), - MX7ULP_PAD_PTF10__LPI2C6_HREQ = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0), - MX7ULP_PAD_PTF10__TPM7_CH3 = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0), - MX7ULP_PAD_PTF10__FB_AD23 = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__USB1_ULPI_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__VIU_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__PTF11 = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__FXIO1_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0), - MX7ULP_PAD_PTF11__LPSPI2_PCS0 = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0), - MX7ULP_PAD_PTF11__LPUART6_RX = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0), - MX7ULP_PAD_PTF11__TPM7_CH4 = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0), - MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__USB1_ULPI_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__VIU_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__PTF12 = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__FXIO1_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0), - MX7ULP_PAD_PTF12__LPSPI3_PCS1 = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0), - MX7ULP_PAD_PTF12__LPUART7_CTS_b = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), - MX7ULP_PAD_PTF12__LPI2C7_SCL = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0), - MX7ULP_PAD_PTF12__TPM7_CH5 = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0), - MX7ULP_PAD_PTF12__FB_AD24 = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__USB1_ULPI_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__VIU_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__PTF13 = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__FXIO1_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0), - MX7ULP_PAD_PTF13__LPSPI3_PCS2 = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0), - MX7ULP_PAD_PTF13__LPUART7_RTS_b = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__LPI2C7_SDA = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0), - MX7ULP_PAD_PTF13__TPM7_CLKIN = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0), - MX7ULP_PAD_PTF13__FB_AD25 = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__USB1_ULPI_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__VIU_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__PTF14 = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__FXIO1_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0), - MX7ULP_PAD_PTF14__LPSPI3_PCS3 = IOMUX_PAD(0x01B8, 0x01B8, 0x3, 0x031C, 0x3, 0), - MX7ULP_PAD_PTF14__LPUART7_TX = IOMUX_PAD(0x01B8, 0x01B8, 0x4, 0x0270, 0x3, 0), - MX7ULP_PAD_PTF14__LPI2C7_HREQ = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0), - MX7ULP_PAD_PTF14__TPM7_CH0 = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0), - MX7ULP_PAD_PTF14__FB_AD26 = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__USB1_ULPI_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__VIU_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__PTF15 = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__FXIO1_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0), - MX7ULP_PAD_PTF15__LPUART7_RX = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0), - MX7ULP_PAD_PTF15__TPM7_CH1 = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0), - MX7ULP_PAD_PTF15__FB_AD27 = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__USB1_ULPI_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__VIU_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__PTF16 = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__USB1_ULPI_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__VIU_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__FXIO1_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0), - MX7ULP_PAD_PTF16__LPSPI3_SIN = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0), - MX7ULP_PAD_PTF16__TPM7_CH2 = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0), - MX7ULP_PAD_PTF16__FB_AD28 = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__PTF17 = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__USB1_ULPI_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__VIU_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__FXIO1_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0), - MX7ULP_PAD_PTF17__LPSPI3_SOUT = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0), - MX7ULP_PAD_PTF17__TPM6_CLKIN = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0), - MX7ULP_PAD_PTF17__FB_AD29 = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__PTF18 = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__USB1_ULPI_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__VIU_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__FXIO1_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0), - MX7ULP_PAD_PTF18__LPSPI3_SCK = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0), - MX7ULP_PAD_PTF18__TPM6_CH0 = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0), - MX7ULP_PAD_PTF18__FB_AD30 = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__PTF19 = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__USB1_ULPI_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__VIU_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__FXIO1_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0), - MX7ULP_PAD_PTF19__LPSPI3_PCS0 = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0), - MX7ULP_PAD_PTF19__TPM6_CH1 = IOMUX_PAD(0x01CC, 0x01CC, 0x6, 0x02D4, 0x3, 0), - MX7ULP_PAD_PTF19__FB_AD31 = IOMUX_PAD(0x01CC, 0x01CC, 0x9, 0x0000, 0x0, 0), -}; -#endif /* __ASM_ARCH_IMX7ULP_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S deleted file mode 100644 index bcc804b..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#include <config.h> - -#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 -#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 - -plugin_start: - - push {r0-r4, lr} - - imx7ulp_ddr_setting - imx7ulp_clock_gating - imx7ulp_qos_setting - -normal_boot: - -/* - * The following is to fill in those arguments for this ROM function - * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) - * This function is used to copy data from the storage media into DDR. - * start - Initial (possibly partial) image load address on entry. - * Final image load address on exit. - * bytes - Initial (possibly partial) image size on entry. - * Final image size on exit. - * boot_data - Initial @ref ivt Boot Data load address. - */ - adr r0, boot_data2 - adr r1, image_len2 - adr r2, boot_data2 - -/* - * check the _pu_irom_api_table for the address - */ -before_calling_rom___pu_irom_hwcnfg_setup: - ldr r3, =ROM_VERSION_OFFSET - ldr r4, [r3] - ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY - ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] - blx r4 -after_calling_rom___pu_irom_hwcnfg_setup: - -/* - * To return to ROM from plugin, we need to fill in these argument. - * Here is what need to do: - * Need to construct the parameters for this function before return to ROM: - * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) - */ - pop {r0-r4, lr} - push {r5} - ldr r5, boot_data2 - str r5, [r0] - ldr r5, image_len2 - str r5, [r1] - ldr r5, second_ivt_offset - str r5, [r2] - mov r0, #1 - pop {r5} - - /* return back to ROM code */ - bx lr - -/* make the following data right in the end of the output*/ -.ltorg - -#define FLASH_OFFSET 0x400 - -/* - * second_ivt_offset is the offset from the "second_ivt_header" to - * "image_copy_start", which involves FLASH_OFFSET, plus the first - * ivt_header, the plugin code size itself recorded by "ivt2_header" - */ - -second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) - -/* - * The following is the second IVT header plus the second boot data - */ -ivt2_header: .long 0x0 -app2_code_jump_v: .long 0x0 -reserv3: .long 0x0 -dcd2_ptr: .long 0x0 -boot_data2_ptr: .long 0x0 -self_ptr2: .long 0x0 -app_code_csf2: .long 0x0 -reserv4: .long 0x0 -boot_data2: .long 0x0 -image_len2: .long 0x0 -plugin2: .long 0x0 diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h deleted file mode 100644 index dee3cfc..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ /dev/null @@ -1,372 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _ASM_ARCH_PCC_H -#define _ASM_ARCH_PCC_H - -#include <common.h> -#include <asm/arch/scg.h> - -/* PCC2 */ - -enum pcc2_entry { - /* On-Platform (32 entries) */ - RSVD0_PCC2_SLOT = 0, - RSVD1_PCC2_SLOT = 1, - CA7_GIC_PCC2_SLOT = 2, - RSVD3_PCC2_SLOT = 3, - RSVD4_PCC2_SLOT = 4, - RSVD5_PCC2_SLOT = 5, - RSVD6_PCC2_SLOT = 6, - RSVD7_PCC2_SLOT = 7, - DMA1_PCC2_SLOT = 8, - RSVD9_PCC2_SLOT = 9, - RSVD10_PCC2_SLOT = 10, - RSVD11_PCC2_SLOT = 11, - RSVD12_PCC2_SLOT = 12, - RSVD13_PCC2_SLOT = 13, - RSVD14_PCC2_SLOT = 14, - RGPIO1_PCC2_SLOT = 15, - FLEXBUS0_PCC2_SLOT = 16, - RSVD17_PCC2_SLOT = 17, - RSVD18_PCC2_SLOT = 18, - RSVD19_PCC2_SLOT = 19, - RSVD20_PCC2_SLOT = 20, - RSVD21_PCC2_SLOT = 21, - RSVD22_PCC2_SLOT = 22, - RSVD23_PCC2_SLOT = 23, - RSVD24_PCC2_SLOT = 24, - RSVD25_PCC2_SLOT = 25, - RSVD26_PCC2_SLOT = 26, - SEMA42_1_PCC2_SLOT = 27, - RSVD28_PCC2_SLOT = 28, - RSVD29_PCC2_SLOT = 29, - RSVD30_PCC2_SLOT = 30, - RSVD31_PCC2_SLOT = 31, - - /* Off-Platform (96 entries) */ - RSVD32_PCC2_SLOT = 32, - DMA1_CH_MUX0_PCC2_SLOT = 33, - MU_B_PCC2_SLOT = 34, - SNVS_PCC2_SLOT = 35, - CAAM_PCC2_SLOT = 36, - LPTPM4_PCC2_SLOT = 37, - LPTPM5_PCC2_SLOT = 38, - LPIT1_PCC2_SLOT = 39, - RSVD40_PCC2_SLOT = 40, - LPSPI2_PCC2_SLOT = 41, - LPSPI3_PCC2_SLOT = 42, - LPI2C4_PCC2_SLOT = 43, - LPI2C5_PCC2_SLOT = 44, - LPUART4_PCC2_SLOT = 45, - LPUART5_PCC2_SLOT = 46, - RSVD47_PCC2_SLOT = 47, - RSVD48_PCC2_SLOT = 48, - FLEXIO1_PCC2_SLOT = 49, - RSVD50_PCC2_SLOT = 50, - USBOTG0_PCC2_SLOT = 51, - USBOTG1_PCC2_SLOT = 52, - USBPHY_PCC2_SLOT = 53, - USB_PL301_PCC2_SLOT = 54, - USDHC0_PCC2_SLOT = 55, - USDHC1_PCC2_SLOT = 56, - RSVD57_PCC2_SLOT = 57, - TRGMUX1_PCC2_SLOT = 58, - RSVD59_PCC2_SLOT = 59, - RSVD60_PCC2_SLOT = 60, - WDG1_PCC2_SLOT = 61, - SCG1_PCC2_SLOT = 62, - PCC2_PCC2_SLOT = 63, - PMC1_PCC2_SLOT = 64, - SMC1_PCC2_SLOT = 65, - RCM1_PCC2_SLOT = 66, - WDG2_PCC2_SLOT = 67, - RSVD68_PCC2_SLOT = 68, - TEST_SPACE1_PCC2_SLOT = 69, - TEST_SPACE2_PCC2_SLOT = 70, - TEST_SPACE3_PCC2_SLOT = 71, - RSVD72_PCC2_SLOT = 72, - RSVD73_PCC2_SLOT = 73, - RSVD74_PCC2_SLOT = 74, - RSVD75_PCC2_SLOT = 75, - RSVD76_PCC2_SLOT = 76, - RSVD77_PCC2_SLOT = 77, - RSVD78_PCC2_SLOT = 78, - RSVD79_PCC2_SLOT = 79, - RSVD80_PCC2_SLOT = 80, - RSVD81_PCC2_SLOT = 81, - RSVD82_PCC2_SLOT = 82, - RSVD83_PCC2_SLOT = 83, - RSVD84_PCC2_SLOT = 84, - RSVD85_PCC2_SLOT = 85, - RSVD86_PCC2_SLOT = 86, - RSVD87_PCC2_SLOT = 87, - RSVD88_PCC2_SLOT = 88, - RSVD89_PCC2_SLOT = 89, - RSVD90_PCC2_SLOT = 90, - RSVD91_PCC2_SLOT = 91, - RSVD92_PCC2_SLOT = 92, - RSVD93_PCC2_SLOT = 93, - RSVD94_PCC2_SLOT = 94, - RSVD95_PCC2_SLOT = 95, - RSVD96_PCC2_SLOT = 96, - RSVD97_PCC2_SLOT = 97, - RSVD98_PCC2_SLOT = 98, - RSVD99_PCC2_SLOT = 99, - RSVD100_PCC2_SLOT = 100, - RSVD101_PCC2_SLOT = 101, - RSVD102_PCC2_SLOT = 102, - RSVD103_PCC2_SLOT = 103, - RSVD104_PCC2_SLOT = 104, - RSVD105_PCC2_SLOT = 105, - RSVD106_PCC2_SLOT = 106, - RSVD107_PCC2_SLOT = 107, - RSVD108_PCC2_SLOT = 108, - RSVD109_PCC2_SLOT = 109, - RSVD110_PCC2_SLOT = 110, - RSVD111_PCC2_SLOT = 111, - RSVD112_PCC2_SLOT = 112, - RSVD113_PCC2_SLOT = 113, - RSVD114_PCC2_SLOT = 114, - RSVD115_PCC2_SLOT = 115, - RSVD116_PCC2_SLOT = 116, - RSVD117_PCC2_SLOT = 117, - RSVD118_PCC2_SLOT = 118, - RSVD119_PCC2_SLOT = 119, - RSVD120_PCC2_SLOT = 120, - RSVD121_PCC2_SLOT = 121, - RSVD122_PCC2_SLOT = 122, - RSVD123_PCC2_SLOT = 123, - RSVD124_PCC2_SLOT = 124, - RSVD125_PCC2_SLOT = 125, - RSVD126_PCC2_SLOT = 126, - RSVD127_PCC2_SLOT = 127, -}; - -enum pcc3_entry { - /* On-Platform (32 entries) */ - RSVD0_PCC3_SLOT = 0, - RSVD1_PCC3_SLOT = 1, - RSVD2_PCC3_SLOT = 2, - RSVD3_PCC3_SLOT = 3, - RSVD4_PCC3_SLOT = 4, - RSVD5_PCC3_SLOT = 5, - RSVD6_PCC3_SLOT = 6, - RSVD7_PCC3_SLOT = 7, - RSVD8_PCC3_SLOT = 8, - RSVD9_PCC3_SLOT = 9, - RSVD10_PCC3_SLOT = 10, - RSVD11_PCC3_SLOT = 11, - RSVD12_PCC3_SLOT = 12, - RSVD13_PCC3_SLOT = 13, - RSVD14_PCC3_SLOT = 14, - RSVD15_PCC3_SLOT = 15, - ROMCP1_PCC3_SLOT = 16, - RSVD17_PCC3_SLOT = 17, - RSVD18_PCC3_SLOT = 18, - RSVD19_PCC3_SLOT = 19, - RSVD20_PCC3_SLOT = 20, - RSVD21_PCC3_SLOT = 21, - RSVD22_PCC3_SLOT = 22, - RSVD23_PCC3_SLOT = 23, - RSVD24_PCC3_SLOT = 24, - RSVD25_PCC3_SLOT = 25, - RSVD26_PCC3_SLOT = 26, - RSVD27_PCC3_SLOT = 27, - RSVD28_PCC3_SLOT = 28, - RSVD29_PCC3_SLOT = 29, - RSVD30_PCC3_SLOT = 30, - RSVD31_PCC3_SLOT = 31, - - /* Off-Platform (96 entries) */ - RSVD32_PCC3_SLOT = 32, - LPTPM6_PCC3_SLOT = 33, - LPTPM7_PCC3_SLOT = 34, - RSVD35_PCC3_SLOT = 35, - LPI2C6_PCC3_SLOT = 36, - LPI2C7_PCC3_SLOT = 37, - LPUART6_PCC3_SLOT = 38, - LPUART7_PCC3_SLOT = 39, - VIU0_PCC3_SLOT = 40, - DSI0_PCC3_SLOT = 41, - LCDIF0_PCC3_SLOT = 42, - MMDC0_PCC3_SLOT = 43, - IOMUXC1_PCC3_SLOT = 44, - IOMUXC_DDR_PCC3_SLOT = 45, - PORTC_PCC3_SLOT = 46, - PORTD_PCC3_SLOT = 47, - PORTE_PCC3_SLOT = 48, - PORTF_PCC3_SLOT = 49, - RSVD50_PCC3_SLOT = 50, - PCC3_PCC3_SLOT = 51, - RSVD52_PCC3_SLOT = 52, - WKPU_PCC3_SLOT = 53, - RSVD54_PCC3_SLOT = 54, - RSVD55_PCC3_SLOT = 55, - RSVD56_PCC3_SLOT = 56, - RSVD57_PCC3_SLOT = 57, - RSVD58_PCC3_SLOT = 58, - RSVD59_PCC3_SLOT = 59, - RSVD60_PCC3_SLOT = 60, - RSVD61_PCC3_SLOT = 61, - RSVD62_PCC3_SLOT = 62, - RSVD63_PCC3_SLOT = 63, - RSVD64_PCC3_SLOT = 64, - RSVD65_PCC3_SLOT = 65, - RSVD66_PCC3_SLOT = 66, - RSVD67_PCC3_SLOT = 67, - RSVD68_PCC3_SLOT = 68, - RSVD69_PCC3_SLOT = 69, - RSVD70_PCC3_SLOT = 70, - RSVD71_PCC3_SLOT = 71, - RSVD72_PCC3_SLOT = 72, - RSVD73_PCC3_SLOT = 73, - RSVD74_PCC3_SLOT = 74, - RSVD75_PCC3_SLOT = 75, - RSVD76_PCC3_SLOT = 76, - RSVD77_PCC3_SLOT = 77, - RSVD78_PCC3_SLOT = 78, - RSVD79_PCC3_SLOT = 79, - RSVD80_PCC3_SLOT = 80, - GPU3D_PCC3_SLOT = 81, - GPU2D_PCC3_SLOT = 82, - RSVD83_PCC3_SLOT = 83, - RSVD84_PCC3_SLOT = 84, - RSVD85_PCC3_SLOT = 85, - RSVD86_PCC3_SLOT = 86, - RSVD87_PCC3_SLOT = 87, - RSVD88_PCC3_SLOT = 88, - RSVD89_PCC3_SLOT = 89, - RSVD90_PCC3_SLOT = 90, - RSVD91_PCC3_SLOT = 91, - RSVD92_PCC3_SLOT = 92, - RSVD93_PCC3_SLOT = 93, - RSVD94_PCC3_SLOT = 94, - RSVD95_PCC3_SLOT = 95, - RSVD96_PCC3_SLOT = 96, - RSVD97_PCC3_SLOT = 97, - RSVD98_PCC3_SLOT = 98, - RSVD99_PCC3_SLOT = 99, - RSVD100_PCC3_SLOT = 100, - RSVD101_PCC3_SLOT = 101, - RSVD102_PCC3_SLOT = 102, - RSVD103_PCC3_SLOT = 103, - RSVD104_PCC3_SLOT = 104, - RSVD105_PCC3_SLOT = 105, - RSVD106_PCC3_SLOT = 106, - RSVD107_PCC3_SLOT = 107, - RSVD108_PCC3_SLOT = 108, - RSVD109_PCC3_SLOT = 109, - RSVD110_PCC3_SLOT = 110, - RSVD111_PCC3_SLOT = 111, - RSVD112_PCC3_SLOT = 112, - RSVD113_PCC3_SLOT = 113, - RSVD114_PCC3_SLOT = 114, - RSVD115_PCC3_SLOT = 115, - RSVD116_PCC3_SLOT = 116, - RSVD117_PCC3_SLOT = 117, - RSVD118_PCC3_SLOT = 118, - RSVD119_PCC3_SLOT = 119, - RSVD120_PCC3_SLOT = 120, - RSVD121_PCC3_SLOT = 121, - RSVD122_PCC3_SLOT = 122, - RSVD123_PCC3_SLOT = 123, - RSVD124_PCC3_SLOT = 124, - RSVD125_PCC3_SLOT = 125, - RSVD126_PCC3_SLOT = 126, - RSVD127_PCC3_SLOT = 127, -}; - - -/* PCC registers */ -#define PCC_PR_OFFSET 31 -#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) -#define PCC_CGC_OFFSET 30 -#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET) -#define PCC_INUSE_OFFSET 29 -#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) -#define PCC_PCS_OFFSET 24 -#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) -#define PCC_FRAC_OFFSET 3 -#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) -#define PCC_PCD_OFFSET 0 -#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) - - -enum pcc_clksrc_type { - CLKSRC_PER_PLAT = 0, - CLKSRC_PER_BUS = 1, - CLKSRC_NO_PCS = 2, -}; - -enum pcc_div_type { - PCC_HAS_DIV, - PCC_NO_DIV, -}; - -/* All peripheral clocks on A7 PCCs */ -enum pcc_clk { - /*PCC2 clocks*/ - PER_CLK_DMA1 = 0, - PER_CLK_RGPIO2P1, - PER_CLK_FLEXBUS, - PER_CLK_SEMA42_1, - PER_CLK_DMA_MUX1, - PER_CLK_SNVS, - PER_CLK_CAAM, - PER_CLK_LPTPM4, - PER_CLK_LPTPM5, - PER_CLK_LPIT1, - PER_CLK_LPSPI2, - PER_CLK_LPSPI3, - PER_CLK_LPI2C4, - PER_CLK_LPI2C5, - PER_CLK_LPUART4, - PER_CLK_LPUART5, - PER_CLK_FLEXIO1, - PER_CLK_USB0, - PER_CLK_USB1, - PER_CLK_USB_PHY, - PER_CLK_USB_PL301, - PER_CLK_USDHC0, - PER_CLK_USDHC1, - PER_CLK_WDG1, - PER_CLK_WDG2, - - /*PCC3 clocks*/ - PER_CLK_LPTPM6, - PER_CLK_LPTPM7, - PER_CLK_LPI2C6, - PER_CLK_LPI2C7, - PER_CLK_LPUART6, - PER_CLK_LPUART7, - PER_CLK_VIU, - PER_CLK_DSI, - PER_CLK_LCDIF, - PER_CLK_MMDC, - PER_CLK_PCTLC, - PER_CLK_PCTLD, - PER_CLK_PCTLE, - PER_CLK_PCTLF, - PER_CLK_GPU3D, - PER_CLK_GPU2D, -}; - - -/* This structure keeps info for each pcc slot */ -struct pcc_entry { - u32 pcc_base; - u32 pcc_slot; - enum pcc_clksrc_type clksrc; - enum pcc_div_type div; -}; - -int pcc_clock_enable(enum pcc_clk clk, bool enable); -int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src); -int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div); -bool pcc_clock_is_enable(enum pcc_clk clk); -int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src); -u32 pcc_clock_get_rate(enum pcc_clk clk); -#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h deleted file mode 100644 index 0e4c8ad..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _SYS_PROTO_MX7ULP_H_ -#define _SYS_PROTO_MX7ULP_H_ - -#include <asm/mach-imx/sys_proto.h> - -#define BT0CFG_LPBOOT_MASK 0x1 -#define BT0CFG_DUALBOOT_MASK 0x2 - -enum bt_mode { - LOW_POWER_BOOT, /* LP_BT = 1 */ - DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ - SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ -}; - -enum boot_device get_boot_device(void); -#endif diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h deleted file mode 100644 index ee56d10..0000000 --- a/arch/arm/include/asm/arch-mxs/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 Clock - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __CLOCK_H__ -#define __CLOCK_H__ - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_EMI_CLK, - MXC_GPMI_CLK, - MXC_IO0_CLK, - MXC_IO1_CLK, - MXC_XTAL_CLK, - MXC_SSP0_CLK, -#ifdef CONFIG_MX28 - MXC_SSP1_CLK, - MXC_SSP2_CLK, - MXC_SSP3_CLK, -#endif -}; - -enum mxs_ioclock { - MXC_IOCLK0 = 0, - MXC_IOCLK1, -}; - -enum mxs_sspclock { - MXC_SSPCLK0 = 0, -#ifdef CONFIG_MX28 - MXC_SSPCLK1, - MXC_SSPCLK2, - MXC_SSPCLK3, -#endif -}; - -uint32_t mxc_get_clock(enum mxc_clock clk); - -void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq); -void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); -void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq); -void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq); - -/* Compatibility with the FEC Ethernet driver */ -#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) - -#endif /* __CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/gpio.h b/arch/arm/include/asm/arch-mxs/gpio.h deleted file mode 100644 index 34fa421..0000000 --- a/arch/arm/include/asm/arch-mxs/gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 GPIO - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MX28_GPIO_H__ -#define __MX28_GPIO_H__ - -#ifdef CONFIG_MXS_GPIO -void mxs_gpio_init(void); -#else -inline void mxs_gpio_init(void) {} -#endif - -#endif /* __MX28_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h deleted file mode 100644 index f853c48..0000000 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 Registers - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __IMX_REGS_H__ -#define __IMX_REGS_H__ - -#include <asm/mach-imx/regs-apbh.h> -#include <asm/arch/regs-base.h> -#include <asm/mach-imx/regs-bch.h> -#include <asm/arch/regs-digctl.h> -#include <asm/mach-imx/regs-gpmi.h> -#include <asm/mach-imx/regs-lcdif.h> -#include <asm/arch/regs-i2c.h> -#include <asm/arch/regs-lradc.h> -#include <asm/arch/regs-ocotp.h> -#include <asm/arch/regs-pinctrl.h> -#include <asm/arch/regs-rtc.h> -#include <asm/arch/regs-ssp.h> -#include <asm/arch/regs-timrot.h> -#include <asm/arch/regs-usb.h> -#include <asm/arch/regs-usbphy.h> - -#ifdef CONFIG_MX23 -#include <asm/arch/regs-clkctrl-mx23.h> -#include <asm/arch/regs-power-mx23.h> -#endif - -#ifdef CONFIG_MX28 -#include <asm/arch/regs-clkctrl-mx28.h> -#include <asm/arch/regs-power-mx28.h> -#endif - -#endif /* __IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/arch/arm/include/asm/arch-mxs/iomux-mx23.h deleted file mode 100644 index 2706efa..0000000 --- a/arch/arm/include/asm/arch-mxs/iomux-mx23.h +++ /dev/null @@ -1,349 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#ifndef __MACH_IOMUX_MX23_H__ -#define __MACH_IOMUX_MX23_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) - -#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) - -#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) -#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) -#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) - -#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) - -#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) - -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) -#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) -#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) - -#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) - -#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx28.h b/arch/arm/include/asm/arch-mxs/iomux-mx28.h deleted file mode 100644 index 00356f0..0000000 --- a/arch/arm/include/asm/arch-mxs/iomux-mx28.h +++ /dev/null @@ -1,531 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#ifndef __MACH_IOMUX_MX28_H__ -#define __MACH_IOMUX_MX28_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) - -#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) - -#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) - -#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) -#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) -#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) -#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) - -#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) - -#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) - -#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) -#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) -#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) -#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) -#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) - -#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) - -#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) -#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) -#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) - -#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) -#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) -#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) -#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) -#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) - -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) - -#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) - -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) - -#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) - -#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h deleted file mode 100644 index a9896e1..0000000 --- a/arch/arm/include/asm/arch-mxs/iomux.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MACH_MXS_IOMUX_H__ -#define __MACH_MXS_IOMUX_H__ - -#ifndef __ASSEMBLY__ - -#include <asm/types.h> - -/* - * IOMUX/PAD Bit field definitions - * - * PAD_BANK: 0..2 (3) - * PAD_PIN: 3..7 (5) - * PAD_MUXSEL: 8..9 (2) - * PAD_MA: 10..11 (2) - * PAD_MA_VALID: 12 (1) - * PAD_VOL: 13 (1) - * PAD_VOL_VALID: 14 (1) - * PAD_PULL: 15 (1) - * PAD_PULL_VALID: 16 (1) - * RESERVED: 17..31 (15) - */ -typedef u32 iomux_cfg_t; - -#define MXS_PAD_BANK_SHIFT 0 -#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) -#define MXS_PAD_PIN_SHIFT 3 -#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) -#define MXS_PAD_MUXSEL_SHIFT 8 -#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) -#define MXS_PAD_MA_SHIFT 10 -#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) -#define MXS_PAD_MA_VALID_SHIFT 12 -#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) -#define MXS_PAD_VOL_SHIFT 13 -#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) -#define MXS_PAD_VOL_VALID_SHIFT 14 -#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) -#define MXS_PAD_PULL_SHIFT 15 -#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) -#define MXS_PAD_PULL_VALID_SHIFT 16 -#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) - -#define PAD_MUXSEL_0 0 -#define PAD_MUXSEL_1 1 -#define PAD_MUXSEL_2 2 -#define PAD_MUXSEL_GPIO 3 - -#define PAD_4MA 0 -#define PAD_8MA 1 -#define PAD_12MA 2 -#define PAD_16MA 3 - -#define PAD_1V8 0 -#if defined(CONFIG_MX28) -#define PAD_3V3 1 -#else -#define PAD_3V3 0 -#endif - -#define PAD_NOPULL 0 -#define PAD_PULLUP 1 - -#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) - -#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) -#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) - -#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) -#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) - -/* generic pad control used in most cases */ -#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) - -#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ - (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ - ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ - ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ - ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ - ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ - ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) - -/* - * A pad becomes naked, when none of mA, vol or pull - * validity bits is set. - */ -#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ - MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) - -static inline unsigned int PAD_BANK(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; -} - -static inline unsigned int PAD_PIN(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; -} - -static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; -} - -static inline unsigned int PAD_MA(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; -} - -static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; -} - -static inline unsigned int PAD_VOL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; -} - -static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; -} - -static inline unsigned int PAD_PULL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; -} - -static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; -} - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad); - -/* - * configures multiple pads - * convenient way to call the above function with tables - */ -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); - -#endif /* __ASSEMBLY__ */ -#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h deleted file mode 100644 index 44d40ca..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-base.h +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 Peripheral Base Addresses - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#ifndef __MXS_REGS_BASE_H__ -#define __MXS_REGS_BASE_H__ - -/* - * Register base addresses for i.MX23 - */ -#if defined(CONFIG_MX23) -#define MXS_ICOLL_BASE 0x80000000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_ECC8_BASE 0x80008000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_ETM_BASE 0x80014000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_EMI_BASE 0x80020000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_TVENC_BASE 0x80038000 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_AUDIOOUT_BASE 0x80048000 -#define MXS_AUDIOIN_BASE 0x8004C000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_RTC_BASE 0x8005C000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006C000 -#define MXS_UARTAPP1_BASE 0x8006E000 -#define MXS_UARTDBG_BASE 0x80070000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_DRAM_BASE 0x800E0000 - -/* - * Register base addresses for i.MX28 - */ -#elif defined(CONFIG_MX28) -#define MXS_ICOL_BASE 0x80000000 -#define MXS_HSADC_BASE 0x80002000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_PERFMON_BASE 0x80006000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80012000 -#define MXS_SSP2_BASE 0x80014000 -#define MXS_SSP3_BASE 0x80016000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_ETM_BASE 0x80022000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_AHB0_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_CAN0_BASE 0x80032000 -#define MXS_CAN1_BASE 0x80034000 -#define MXS_SIMDBG_BASE 0x8003C000 -#define MXS_SIMGPMISEL_BASE 0x8003C200 -#define MXS_SIMSSPSEL_BASE 0x8003C300 -#define MXS_SIMMEMSEL_BASE 0x8003C400 -#define MXS_GPIOMON_BASE 0x8003C500 -#define MXS_SIMENET_BASE 0x8003C700 -#define MXS_ARMJTAG_BASE 0x8003C800 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_RTC_BASE 0x80056000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_I2C1_BASE 0x8005A000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006A000 -#define MXS_UARTAPP1_BASE 0x8006C000 -#define MXS_UARTAPP2_BASE 0x8006E000 -#define MXS_UARTAPP3_BASE 0x80070000 -#define MXS_UARTAPP4_BASE 0x80072000 -#define MXS_UARTDBG_BASE 0x80074000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBPHY1_BASE 0x8007E000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_USBCTRL1_BASE 0x80090000 -#define MXS_DFLPT_BASE 0x800C0000 -#define MXS_DRAM_BASE 0x800E0000 -#define MXS_ENET0_BASE 0x800F0000 -#define MXS_ENET1_BASE 0x800F4000 -#else -#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 -#endif - -#endif /* __MXS_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h deleted file mode 100644 index 6e9ffeb..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 CLKCTRL Register Definitions - * - * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX23_REGS_CLKCTRL_H__ -#define __MX23_REGS_CLKCTRL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */ - mxs_reg_32(hw_clkctrl_pix) /* 0x60 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */ - - uint32_t reserved1[4]; - - mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */ - mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x120 */ - mxs_reg_32(hw_clkctrl_status) /* 0x130 */ - mxs_reg_32(hw_clkctrl_version) /* 0x140 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 16) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_BUSY (1 << 29) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) -#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_PIX_CLKGATE (1 << 31) -#define CLKCTRL_PIX_BUSY (1 << 29) -#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) -#define CLKCTRL_PIX_DIV_MASK 0xfff -#define CLKCTRL_PIX_DIV_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_IR_CLKGATE (1 << 31) -#define CLKCTRL_IR_AUTO_DIV (1 << 29) -#define CLKCTRL_IR_IR_BUSY (1 << 28) -#define CLKCTRL_IR_IROV_BUSY (1 << 27) -#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) -#define CLKCTRL_IR_IROV_DIV_OFFSET 16 -#define CLKCTRL_IR_IR_DIV_MASK 0x3ff -#define CLKCTRL_IR_IR_DIV_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) -#define CLKCTRL_TV_CLK_TV_GATE (1 << 30) - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) -#define CLKCTRL_ETM_DIV_MASK 0x3f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_PIX 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_VID 3 - -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0) - -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h deleted file mode 100644 index 01e0a7a..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h +++ /dev/null @@ -1,282 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 CLKCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_CLKCTRL_H__ -#define __MX28_REGS_CLKCTRL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ - uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */ - uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */ - mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ - mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ - mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ - mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ - mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ - mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ - mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ - mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ - - uint32_t reserved[16]; - - mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ - mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ - mxs_reg_32(hw_clkctrl_version) /* 0x200 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) -#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) -#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) -#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_SAIF1_CLKGATE (1 << 31) -#define CLKCTRL_SAIF1_BUSY (1 << 29) -#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF1_DIV_MASK 0xffff -#define CLKCTRL_SAIF1_DIV_OFFSET 0 - -#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) -#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) -#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) -#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff -#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) -#define CLKCTRL_ETM_DIV_MASK 0x7f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_ENET_SLEEP (1 << 31) -#define CLKCTRL_ENET_DISABLE (1 << 30) -#define CLKCTRL_ENET_STATUS (1 << 29) -#define CLKCTRL_ENET_BUSY_TIME (1 << 27) -#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) -#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 -#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) -#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 -#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) -#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) -#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) -#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) -#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) -#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) -#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) - -#define CLKCTRL_HSADC_RESETB (1 << 30) -#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) -#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 - -#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) -#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) -#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) -#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_IO1 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_PIX 0 -#define CLKCTRL_FRAC1_HSADC 1 -#define CLKCTRL_FRAC1_GPMI 2 - -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) - -#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) -#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) -#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) -#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h deleted file mode 100644 index 219f58b..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-digctl.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 DIGCTL Register Definitions - * - * Copyright (C) 2012 Robert Delien <robert@delien.nl> - */ - -#ifndef __MX28_REGS_DIGCTL_H__ -#define __MX28_REGS_DIGCTL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_digctl_regs { - mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ - mxs_reg_32(hw_digctl_status) /* 0x010 */ - mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ - mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ - mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ - mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ - uint32_t hw_digctl_writeonce; /* 0x060 */ - uint32_t reserved_writeonce[3]; - mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ - mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ - uint32_t hw_digctl_entropy; /* 0x090 */ - uint32_t reserved_entropy[3]; - uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ - uint32_t reserved_entropy_latched[3]; - - uint32_t reserved1[4]; - - mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ - uint32_t hw_digctl_dbgrd; /* 0x0d0 */ - uint32_t reserved_hw_digctl_dbgrd[3]; - uint32_t hw_digctl_dbg; /* 0x0e0 */ - uint32_t reserved_hw_digctl_dbg[3]; - - uint32_t reserved2[4]; - - mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ - mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ - mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ - mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ - mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ - mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ - mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ - mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ - mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ - mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ - mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ - mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ - mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ - mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ - mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ - - uint32_t reserved3[36]; - - uint32_t hw_digctl_scratch0; /* 0x280 */ - uint32_t reserved_hw_digctl_scratch0[3]; - uint32_t hw_digctl_scratch1; /* 0x290 */ - uint32_t reserved_hw_digctl_scratch1[3]; - uint32_t hw_digctl_armcache; /* 0x2a0 */ - uint32_t reserved_hw_digctl_armcache[3]; - mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ - uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; - uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; - uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; - uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; - uint32_t hw_digctl_fsl; /* 0x300 */ - uint32_t reserved_hw_digctl_fsl[3]; - uint32_t hw_digctl_chipid; /* 0x310 */ - uint32_t reserved_hw_digctl_chipid[3]; - - uint32_t reserved4[4]; - - uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ - uint32_t reserved_hw_digctl_ahb_stats_select[3]; - - uint32_t reserved5[12]; - - uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ - uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; - uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ - uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; - uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ - uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; - uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ - uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; - uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; - uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; - uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ - uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; - uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; - uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; - - uint32_t reserved6[64]; - - uint32_t hw_digctl_mpte0_loc; /* 0x500 */ - uint32_t reserved_hw_digctl_mpte0_loc[3]; - uint32_t hw_digctl_mpte1_loc; /* 0x510 */ - uint32_t reserved_hw_digctl_mpte1_loc[3]; - uint32_t hw_digctl_mpte2_loc; /* 0x520 */ - uint32_t reserved_hw_digctl_mpte2_loc[3]; - uint32_t hw_digctl_mpte3_loc; /* 0x530 */ - uint32_t reserved_hw_digctl_mpte3_loc[3]; - uint32_t hw_digctl_mpte4_loc; /* 0x540 */ - uint32_t reserved_hw_digctl_mpte4_loc[3]; - uint32_t hw_digctl_mpte5_loc; /* 0x550 */ - uint32_t reserved_hw_digctl_mpte5_loc[3]; - uint32_t hw_digctl_mpte6_loc; /* 0x560 */ - uint32_t reserved_hw_digctl_mpte6_loc[3]; - uint32_t hw_digctl_mpte7_loc; /* 0x570 */ - uint32_t reserved_hw_digctl_mpte7_loc[3]; - uint32_t hw_digctl_mpte8_loc; /* 0x580 */ - uint32_t reserved_hw_digctl_mpte8_loc[3]; - uint32_t hw_digctl_mpte9_loc; /* 0x590 */ - uint32_t reserved_hw_digctl_mpte9_loc[3]; - uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ - uint32_t reserved_hw_digctl_mpte10_loc[3]; - uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ - uint32_t reserved_hw_digctl_mpte11_loc[3]; - uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ - uint32_t reserved_hw_digctl_mpte12_loc[3]; - uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ - uint32_t reserved_hw_digctl_mpte13_loc[3]; - uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ - uint32_t reserved_hw_digctl_mpte14_loc[3]; - uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ - uint32_t reserved_hw_digctl_mpte15_loc[3]; -}; -#endif - -/* Product code identification */ -#define HW_DIGCTL_CHIPID_MASK (0xffff << 16) -#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) -#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) - -#endif /* __MX28_REGS_DIGCTL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h deleted file mode 100644 index 4cc2e0b..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-i2c.h +++ /dev/null @@ -1,193 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 I2C Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MX28_REGS_I2C_H__ -#define __MX28_REGS_I2C_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_i2c_regs { - mxs_reg_32(hw_i2c_ctrl0) - mxs_reg_32(hw_i2c_timing0) - mxs_reg_32(hw_i2c_timing1) - mxs_reg_32(hw_i2c_timing2) - mxs_reg_32(hw_i2c_ctrl1) - mxs_reg_32(hw_i2c_stat) - mxs_reg_32(hw_i2c_queuectrl) - mxs_reg_32(hw_i2c_queuestat) - mxs_reg_32(hw_i2c_queuecmd) - mxs_reg_32(hw_i2c_queuedata) - mxs_reg_32(hw_i2c_data) - mxs_reg_32(hw_i2c_debug0) - mxs_reg_32(hw_i2c_debug1) - mxs_reg_32(hw_i2c_version) -}; -#endif - -#define I2C_CTRL_SFTRST (1 << 31) -#define I2C_CTRL_CLKGATE (1 << 30) -#define I2C_CTRL_RUN (1 << 29) -#define I2C_CTRL_PREACK (1 << 27) -#define I2C_CTRL_ACKNOWLEDGE (1 << 26) -#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) -#define I2C_CTRL_MULTI_MASTER (1 << 23) -#define I2C_CTRL_CLOCK_HELD (1 << 22) -#define I2C_CTRL_RETAIN_CLOCK (1 << 21) -#define I2C_CTRL_POST_SEND_STOP (1 << 20) -#define I2C_CTRL_PRE_SEND_START (1 << 19) -#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_CTRL_MASTER_MODE (1 << 17) -#define I2C_CTRL_DIRECTION (1 << 16) -#define I2C_CTRL_XFER_COUNT_MASK 0xffff -#define I2C_CTRL_XFER_COUNT_OFFSET 0 - -#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 -#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff -#define I2C_TIMING0_RCV_COUNT_OFFSET 0 - -#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING1_LOW_COUNT_OFFSET 16 -#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff -#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 - -#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) -#define I2C_TIMING2_BUS_FREE_OFFSET 16 -#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff -#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 - -#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) -#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) -#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) -#define I2C_CTRL1_ACK_MODE (1 << 27) -#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) -#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) -#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 -#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) -#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) -#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) -#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) -#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) -#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) -#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) -#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) -#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) -#define I2C_CTRL1_SLAVE_IRQ (1 << 0) - -#define I2C_STAT_MASTER_PRESENT (1 << 31) -#define I2C_STAT_SLAVE_PRESENT (1 << 30) -#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) -#define I2C_STAT_GOT_A_NAK (1 << 28) -#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) -#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 -#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) -#define I2C_STAT_SLAVE_FOUND (1 << 14) -#define I2C_STAT_SLAVE_SEARCHING (1 << 13) -#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) -#define I2C_STAT_BUS_BUSY (1 << 11) -#define I2C_STAT_CLK_GEN_BUSY (1 << 10) -#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) -#define I2C_STAT_SLAVE_BUSY (1 << 8) -#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) -#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) -#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) -#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) -#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) -#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) -#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) -#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) - -#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) -#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 -#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) -#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 -#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) -#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) -#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) -#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) -#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) -#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) - -#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) -#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 -#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) -#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) -#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f -#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 - -#define I2C_QUEUECMD_PREACK (1 << 27) -#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) -#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) -#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) -#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) -#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) -#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) -#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) -#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_QUEUECMD_MASTER_MODE (1 << 17) -#define I2C_QUEUECMD_DIRECTION (1 << 16) -#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff -#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 - -#define I2C_QUEUEDATA_DATA_MASK 0xffffffff -#define I2C_QUEUEDATA_DATA_OFFSET 0 - -#define I2C_DATA_DATA_MASK 0xffffffff -#define I2C_DATA_DATA_OFFSET 0 - -#define I2C_DEBUG0_DMAREQ (1 << 31) -#define I2C_DEBUG0_DMAENDCMD (1 << 30) -#define I2C_DEBUG0_DMAKICK (1 << 29) -#define I2C_DEBUG0_DMATERMINATE (1 << 28) -#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) -#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 -#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) -#define I2C_DEBUG0_DMA_STATE_OFFSET 16 -#define I2C_DEBUG0_START_TOGGLE (1 << 15) -#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) -#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) -#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) -#define I2C_DEBUG0_STATE_LATCH (1 << 11) -#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) -#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff -#define I2C_DEBUG0_STATE_STATE_OFFSET 0 - -#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) -#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 -#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) -#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 -#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) -#define I2C_DEBUG1_LST_MODE_OFFSET 9 -#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) -#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) -#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) -#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) -#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) -#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) - -#define I2C_VERSION_MAJOR_MASK (0xff << 24) -#define I2C_VERSION_MAJOR_OFFSET 24 -#define I2C_VERSION_MINOR_MASK (0xff << 16) -#define I2C_VERSION_MINOR_OFFSET 16 -#define I2C_VERSION_STEP_MASK 0xffff -#define I2C_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-lradc.h b/arch/arm/include/asm/arch-mxs/regs-lradc.h deleted file mode 100644 index a48f7a4..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-lradc.h +++ /dev/null @@ -1,386 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 LRADC Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_LRADC_H__ -#define __MX28_REGS_LRADC_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_lradc_regs { - mxs_reg_32(hw_lradc_ctrl0); - mxs_reg_32(hw_lradc_ctrl1); - mxs_reg_32(hw_lradc_ctrl2); - mxs_reg_32(hw_lradc_ctrl3); - mxs_reg_32(hw_lradc_status); - mxs_reg_32(hw_lradc_ch0); - mxs_reg_32(hw_lradc_ch1); - mxs_reg_32(hw_lradc_ch2); - mxs_reg_32(hw_lradc_ch3); - mxs_reg_32(hw_lradc_ch4); - mxs_reg_32(hw_lradc_ch5); - mxs_reg_32(hw_lradc_ch6); - mxs_reg_32(hw_lradc_ch7); - mxs_reg_32(hw_lradc_delay0); - mxs_reg_32(hw_lradc_delay1); - mxs_reg_32(hw_lradc_delay2); - mxs_reg_32(hw_lradc_delay3); - mxs_reg_32(hw_lradc_debug0); - mxs_reg_32(hw_lradc_debug1); - mxs_reg_32(hw_lradc_conversion); - mxs_reg_32(hw_lradc_ctrl4); - mxs_reg_32(hw_lradc_treshold0); - mxs_reg_32(hw_lradc_treshold1); - mxs_reg_32(hw_lradc_version); -}; -#endif - -#define LRADC_CTRL0_SFTRST (1 << 31) -#define LRADC_CTRL0_CLKGATE (1 << 30) -#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) -#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) -#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) -#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) -#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) -#define LRADC_CTRL0_YNLRSW (1 << 21) -#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) -#define LRADC_CTRL0_YPLLSW_OFFSET 19 -#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) -#define LRADC_CTRL0_XNURSW_OFFSET 17 -#define LRADC_CTRL0_XPULSW (1 << 16) -#define LRADC_CTRL0_SCHEDULE_MASK 0xff -#define LRADC_CTRL0_SCHEDULE_OFFSET 0 - -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) -#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) -#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) -#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) -#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) -#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) -#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) -#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) -#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) -#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) -#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) -#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) -#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) -#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) -#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) -#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) -#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) - -#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) -#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 -#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) -#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) -#define LRADC_CTRL2_VTHSENSE_OFFSET 13 -#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) -#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) -#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 -#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) -#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) -#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) -#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) -#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) -#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) -#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) -#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) -#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 -#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) -#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) -#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) -#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) -#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) -#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) -#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) - -#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) -#define LRADC_CTRL3_DISCARD_OFFSET 24 -#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) -#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) -#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) -#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) -#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) -#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) -#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 -#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) -#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) -#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) -#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) -#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) -#define LRADC_CTRL3_HIGH_TIME_OFFSET 4 -#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) -#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) -#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) -#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) -#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) -#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) - -#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) -#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) -#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) -#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) -#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) -#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) -#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) -#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) -#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) -#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) -#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) -#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) -#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) -#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) -#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) -#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) - -#define LRADC_CH_TOGGLE (1 << 31) -#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) -#define LRADC_CH_ACCUMULATE (1 << 29) -#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) -#define LRADC_CH_NUM_SAMPLES_OFFSET 24 -#define LRADC_CH_VALUE_MASK 0x3ffff -#define LRADC_CH_VALUE_OFFSET 0 - -#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) -#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 -#define LRADC_DELAY_KICK (1 << 20) -#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) -#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 -#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) -#define LRADC_DELAY_LOOP_COUNT_OFFSET 11 -#define LRADC_DELAY_DELAY_MASK 0x7ff -#define LRADC_DELAY_DELAY_OFFSET 0 - -#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) -#define LRADC_DEBUG0_READONLY_OFFSET 16 -#define LRADC_DEBUG0_STATE_MASK (0xfff << 0) -#define LRADC_DEBUG0_STATE_OFFSET 0 - -#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) -#define LRADC_DEBUG1_REQUEST_OFFSET 16 -#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) -#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 -#define LRADC_DEBUG1_TESTMODE6 (1 << 2) -#define LRADC_DEBUG1_TESTMODE5 (1 << 1) -#define LRADC_DEBUG1_TESTMODE (1 << 0) - -#define LRADC_CONVERSION_AUTOMATIC (1 << 20) -#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 -#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) -#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff -#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 - -#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) -#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) -#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) -#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) -#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) -#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) -#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) -#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) -#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) -#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) -#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) -#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) -#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) -#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) -#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) - -#define LRADC_THRESHOLD_ENABLE (1 << 24) -#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) -#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) -#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) -#define LRADC_THRESHOLD_SETTING_OFFSET 18 -#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) -#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) -#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) -#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) -#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff -#define LRADC_THRESHOLD_VALUE_OFFSET 0 - -#define LRADC_VERSION_MAJOR_MASK (0xff << 24) -#define LRADC_VERSION_MAJOR_OFFSET 24 -#define LRADC_VERSION_MINOR_MASK (0xff << 16) -#define LRADC_VERSION_MINOR_OFFSET 16 -#define LRADC_VERSION_STEP_MASK 0xffff -#define LRADC_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_LRADC_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h deleted file mode 100644 index 8bfbd19..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-ocotp.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 OCOTP Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_OCOTP_H__ -#define __MX28_REGS_OCOTP_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_ocotp_regs { - mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ - mxs_reg_32(hw_ocotp_data) /* 0x10 */ - mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ - mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ - mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ - mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ - mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ - mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ - mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ - mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ - mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ - mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ - mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ - mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ - mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ - mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ - mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ - mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ - mxs_reg_32(hw_ocotp_lock) /* 0x120 */ - mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ - mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ - mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ - mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ - mxs_reg_32(hw_ocotp_un0) /* 0x170 */ - mxs_reg_32(hw_ocotp_un1) /* 0x180 */ - mxs_reg_32(hw_ocotp_un2) /* 0x190 */ - mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ - mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ - mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ - mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ - mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ - mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ - mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ - mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ - mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ - mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ - mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ - mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ - mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ - mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ - mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ - mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ - mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ -}; -#endif - -#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) -#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 -#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) -#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) -#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) -#define OCOTP_CTRL_ERROR (1 << 9) -#define OCOTP_CTRL_BUSY (1 << 8) -#define OCOTP_CTRL_ADDR_MASK 0x3f -#define OCOTP_CTRL_ADDR_OFFSET 0 - -#define OCOTP_DATA_DATA_MASK 0xffffffff -#define OCOTP_DATA_DATA_OFFSET 0 - -#define OCOTP_CUST_BITS_MASK 0xffffffff -#define OCOTP_CUST_BITS_OFFSET 0 - -#define OCOTP_CRYPTO_BITS_MASK 0xffffffff -#define OCOTP_CRYPTO_BITS_OFFSET 0 - -#define OCOTP_HWCAP_BITS_MASK 0xffffffff -#define OCOTP_HWCAP_BITS_OFFSET 0 - -#define OCOTP_SWCAP_BITS_MASK 0xffffffff -#define OCOTP_SWCAP_BITS_OFFSET 0 - -#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) -#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) - -#define OCOTP_LOCK_ROM7 (1 << 31) -#define OCOTP_LOCK_ROM6 (1 << 30) -#define OCOTP_LOCK_ROM5 (1 << 29) -#define OCOTP_LOCK_ROM4 (1 << 28) -#define OCOTP_LOCK_ROM3 (1 << 27) -#define OCOTP_LOCK_ROM2 (1 << 26) -#define OCOTP_LOCK_ROM1 (1 << 25) -#define OCOTP_LOCK_ROM0 (1 << 24) -#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) -#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) -#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) -#define OCOTP_LOCK_PIN (1 << 20) -#define OCOTP_LOCK_OPS (1 << 19) -#define OCOTP_LOCK_UN2 (1 << 18) -#define OCOTP_LOCK_UN1 (1 << 17) -#define OCOTP_LOCK_UN0 (1 << 16) -#define OCOTP_LOCK_SRK (1 << 15) -#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) -#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 -#define OCOTP_LOCK_SRK_SHADOW (1 << 11) -#define OCOTP_LOCK_ROM_SHADOW (1 << 10) -#define OCOTP_LOCK_CUSTCAP (1 << 9) -#define OCOTP_LOCK_HWSW (1 << 8) -#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) -#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) -#define OCOTP_LOCK_CRYPTODCP (1 << 5) -#define OCOTP_LOCK_CRYPTOKEY (1 << 4) -#define OCOTP_LOCK_CUST3 (1 << 3) -#define OCOTP_LOCK_CUST2 (1 << 2) -#define OCOTP_LOCK_CUST1 (1 << 1) -#define OCOTP_LOCK_CUST0 (1 << 0) - -#define OCOTP_OPS_BITS_MASK 0xffffffff -#define OCOTP_OPS_BITS_OFFSET 0 - -#define OCOTP_UN_BITS_MASK 0xffffffff -#define OCOTP_UN_BITS_OFFSET 0 - -#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) -#define OCOTP_ROM_BOOT_MODE_OFFSET 24 -#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) -#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 -#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) -#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 -#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) -#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 -#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) -#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 -#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) -#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 -#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) -#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) -#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) -#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) -#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) - -#define OCOTP_SRK_BITS_MASK 0xffffffff -#define OCOTP_SRK_BITS_OFFSET 0 - -#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) -#define OCOTP_VERSION_MAJOR_OFFSET 24 -#define OCOTP_VERSION_MINOR_MASK (0xff << 16) -#define OCOTP_VERSION_MINOR_OFFSET 16 -#define OCOTP_VERSION_STEP_MASK 0xffff -#define OCOTP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h deleted file mode 100644 index 134d436..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h +++ /dev/null @@ -1,1270 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 PINCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_PINCTRL_H__ -#define __MX28_REGS_PINCTRL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_pinctrl_regs { - mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */ - - uint32_t reserved1[60]; - - mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ - mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ - mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ - mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ - mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ - mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ - mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ - mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ - mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ - mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ - mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ - mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ - mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ - mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ - - uint32_t reserved2[72]; - - mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ - mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ - mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ - mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ - mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ - mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ - mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ - mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ - mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ - mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ - mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ - mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ - mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ - mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ - mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ - mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ - mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ - mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ - mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ - mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */ - - uint32_t reserved3[112]; - - mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ - mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ - mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ - mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ - mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ - mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ - mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */ - - uint32_t reserved4[36]; - - mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ - mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ - mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ - mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ - mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */ - - uint32_t reserved5[108]; - - mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ - mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ - mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ - mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ - mxs_reg_32(hw_pinctrl_din4) /* 0x940 */ - - uint32_t reserved6[108]; - - mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ - mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ - mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ - mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ - mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */ - - uint32_t reserved7[300]; - - mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ - mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ - mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ - mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ - mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ - - uint32_t reserved8[44]; - - mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ - mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ - mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ - mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ - mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ - - uint32_t reserved9[44]; - - mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ - mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ - mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ - mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ - mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ - - uint32_t reserved10[44]; - - mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ - mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ - mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ - mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ - mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ - - uint32_t reserved11[44]; - - mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ - mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ - mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ - mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ - mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ - - uint32_t reserved12[380]; - - mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ - - uint32_t reserved13[76]; - - mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ -}; -#endif - -#define PINCTRL_CTRL_SFTRST (1 << 31) -#define PINCTRL_CTRL_CLKGATE (1 << 30) -#define PINCTRL_CTRL_PRESENT4 (1 << 24) -#define PINCTRL_CTRL_PRESENT3 (1 << 23) -#define PINCTRL_CTRL_PRESENT2 (1 << 22) -#define PINCTRL_CTRL_PRESENT1 (1 << 21) -#define PINCTRL_CTRL_PRESENT0 (1 << 20) -#define PINCTRL_CTRL_IRQOUT4 (1 << 4) -#define PINCTRL_CTRL_IRQOUT3 (1 << 3) -#define PINCTRL_CTRL_IRQOUT2 (1 << 2) -#define PINCTRL_CTRL_IRQOUT1 (1 << 1) -#define PINCTRL_CTRL_IRQOUT0 (1 << 0) - -#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) -#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 -#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 - -#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 -#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 - -#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) -#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) -#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) -#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) -#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) -#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) -#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) -#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) -#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) -#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) -#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) -#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) -#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) -#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) -#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) -#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) -#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) -#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) -#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) -#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) -#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) - -#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) -#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) -#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) -#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) -#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) -#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) -#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) -#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) -#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) -#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) -#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) -#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) -#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) -#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) -#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) -#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) -#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) -#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) -#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) -#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) -#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) -#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) -#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) -#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) -#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) -#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) -#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) -#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) -#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) -#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) -#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) -#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) - -#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) -#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) -#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) -#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) -#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) -#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) -#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) -#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) -#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) -#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) -#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) -#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) -#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) -#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) -#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) -#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) -#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) -#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) -#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) -#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) -#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) -#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) -#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) -#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) -#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) - -#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) -#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) -#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) -#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) -#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) -#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) -#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) -#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) -#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) -#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) -#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) -#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) -#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) -#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) -#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) -#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) -#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) -#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) -#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) -#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) -#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) -#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) -#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) -#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) -#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) -#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) -#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) -#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) -#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) -#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) - -#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) -#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) -#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) -#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) -#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) -#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) -#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) -#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) -#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) -#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) -#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) -#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) -#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) -#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) -#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) -#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) -#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) -#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) - -#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) -#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) -#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) -#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) -#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) -#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) -#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) -#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) -#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) -#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) -#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) -#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) -#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) -#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) -#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) -#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) -#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) -#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) -#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) -#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) -#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) -#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) -#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) -#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) -#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) - -#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) -#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) -#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) -#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) -#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) -#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) -#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) -#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) -#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) -#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) -#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) -#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) -#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) -#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) -#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) -#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) -#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) -#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) -#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) -#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) -#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) -#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) -#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) -#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) - -#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff -#define PINCTRL_DOUT0_DOUT_OFFSET 0 - -#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff -#define PINCTRL_DOUT1_DOUT_OFFSET 0 - -#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff -#define PINCTRL_DOUT2_DOUT_OFFSET 0 - -#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff -#define PINCTRL_DOUT3_DOUT_OFFSET 0 - -#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff -#define PINCTRL_DOUT4_DOUT_OFFSET 0 - -#define PINCTRL_DIN0_DIN_MASK 0x1fffffff -#define PINCTRL_DIN0_DIN_OFFSET 0 - -#define PINCTRL_DIN1_DIN_MASK 0xffffffff -#define PINCTRL_DIN1_DIN_OFFSET 0 - -#define PINCTRL_DIN2_DIN_MASK 0xfffffff -#define PINCTRL_DIN2_DIN_OFFSET 0 - -#define PINCTRL_DIN3_DIN_MASK 0x7fffffff -#define PINCTRL_DIN3_DIN_OFFSET 0 - -#define PINCTRL_DIN4_DIN_MASK 0x1fffff -#define PINCTRL_DIN4_DIN_OFFSET 0 - -#define PINCTRL_DOE0_DOE_MASK 0x1fffffff -#define PINCTRL_DOE0_DOE_OFFSET 0 - -#define PINCTRL_DOE1_DOE_MASK 0xffffffff -#define PINCTRL_DOE1_DOE_OFFSET 0 - -#define PINCTRL_DOE2_DOE_MASK 0xfffffff -#define PINCTRL_DOE2_DOE_OFFSET 0 - -#define PINCTRL_DOE3_DOE_MASK 0x7fffffff -#define PINCTRL_DOE3_DOE_OFFSET 0 - -#define PINCTRL_DOE4_DOE_MASK 0x1fffff -#define PINCTRL_DOE4_DOE_OFFSET 0 - -#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff -#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff -#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff -#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff -#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff -#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 - -#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff -#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff -#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff -#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff -#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff -#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 - -#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff -#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff -#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff -#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff -#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff -#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff -#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff -#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff -#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff -#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff -#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff -#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff -#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff -#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff -#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff -#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 - -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 - -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 - -#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h deleted file mode 100644 index a0dc781..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h +++ /dev/null @@ -1,344 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 Power Controller Register Definitions - * - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - */ - -#ifndef __MX23_REGS_POWER_H__ -#define __MX23_REGS_POWER_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved1[4]; - - mxs_reg_32(hw_power_reset) - - uint32_t reserved2[4]; - - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) -}; -#endif - -#define POWER_CTRL_CLKGATE (1 << 30) -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_USE_EXTERN_R (1 << 17) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xff << 16) -#define POWER_SPEED_STATUS_OFFSET 16 -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h deleted file mode 100644 index 39250c5..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h +++ /dev/null @@ -1,399 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 Power Controller Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __MX28_REGS_POWER_H__ -#define __MX28_REGS_POWER_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved[4]; - - mxs_reg_32(hw_power_reset) - mxs_reg_32(hw_power_debug) - mxs_reg_32(hw_power_thermal) - mxs_reg_32(hw_power_usb1ctrl) - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) - mxs_reg_32(hw_power_anaclkctrl) - mxs_reg_32(hw_power_refctrl) -}; -#endif - -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_LIION_4P1 (1 << 18) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) -#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) -#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_THERMAL_WARNING (1 << 19) -#define POWER_STS_VDDMEM_BO (1 << 18) -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xffff << 8) -#define POWER_SPEED_STATUS_OFFSET 8 -#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) -#define POWER_SPEED_STATUS_SEL_OFFSET 6 -#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) -#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) -#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_THERMAL_TEST (1 << 8) -#define POWER_THERMAL_PWD (1 << 7) -#define POWER_THERMAL_LOW_POWER (1 << 6) -#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) -#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 -#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) -#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 -#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 - -#define POWER_USB1CTRL_AVALID1 (1 << 3) -#define POWER_USB1CTRL_BVALID1 (1 << 2) -#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) -#define POWER_USB1CTRL_SESSEND1 (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) -#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) -#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 -#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) -#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) -#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) -#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) -#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) -#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) -#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 -#define POWER_ANACLKCTRL_INDIV_MASK 0x7 -#define POWER_ANACLKCTRL_INDIV_OFFSET 0 - -#define POWER_REFCTRL_FASTSETTLING (1 << 26) -#define POWER_REFCTRL_RAISE_REF (1 << 25) -#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) -#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) -#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 -#define POWER_REFCTRL_LOW_PWR (1 << 19) -#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) -#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 -#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) -#define POWER_REFCTRL_ADJ_ANA (1 << 13) -#define POWER_REFCTRL_ADJ_VAG (1 << 12) -#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) -#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 -#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) -#define POWER_REFCTRL_VAG_VAL_OFFSET 4 - -#endif /* __MX28_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h deleted file mode 100644 index 8d6ba57..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-rtc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 RTC Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MX28_REGS_RTC_H__ -#define __MX28_REGS_RTC_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_rtc_regs { - mxs_reg_32(hw_rtc_ctrl) - mxs_reg_32(hw_rtc_stat) - mxs_reg_32(hw_rtc_milliseconds) - mxs_reg_32(hw_rtc_seconds) - mxs_reg_32(hw_rtc_rtc_alarm) - mxs_reg_32(hw_rtc_watchdog) - mxs_reg_32(hw_rtc_persistent0) - mxs_reg_32(hw_rtc_persistent1) - mxs_reg_32(hw_rtc_persistent2) - mxs_reg_32(hw_rtc_persistent3) - mxs_reg_32(hw_rtc_persistent4) - mxs_reg_32(hw_rtc_persistent5) - mxs_reg_32(hw_rtc_debug) - mxs_reg_32(hw_rtc_version) -}; -#endif - -#define RTC_CTRL_SFTRST (1 << 31) -#define RTC_CTRL_CLKGATE (1 << 30) -#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) -#define RTC_CTRL_FORCE_UPDATE (1 << 5) -#define RTC_CTRL_WATCHDOGEN (1 << 4) -#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) -#define RTC_CTRL_ALARM_IRQ (1 << 2) -#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) -#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) - -#define RTC_STAT_RTC_PRESENT (1 << 31) -#define RTC_STAT_ALARM_PRESENT (1 << 30) -#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) -#define RTC_STAT_XTAL32000_PRESENT (1 << 28) -#define RTC_STAT_XTAL32768_PRESENT (1 << 27) -#define RTC_STAT_STALE_REGS_MASK (0xff << 16) -#define RTC_STAT_STALE_REGS_OFFSET 16 -#define RTC_STAT_NEW_REGS_MASK (0xff << 8) -#define RTC_STAT_NEW_REGS_OFFSET 8 - -#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff -#define RTC_MILLISECONDS_COUNT_OFFSET 0 - -#define RTC_SECONDS_COUNT_MASK 0xffffffff -#define RTC_SECONDS_COUNT_OFFSET 0 - -#define RTC_ALARM_VALUE_MASK 0xffffffff -#define RTC_ALARM_VALUE_OFFSET 0 - -#define RTC_WATCHDOG_COUNT_MASK 0xffffffff -#define RTC_WATCHDOG_COUNT_OFFSET 0 - -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) -#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) -#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) -#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) -#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) -#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) -#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) -#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 -#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) -#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) -#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) -#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 -#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) -#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) -#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) -#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) -#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) -#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) -#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) -#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) -#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) -#define RTC_PERSISTENT0_LCK_SECS (1 << 3) -#define RTC_PERSISTENT0_ALARM_EN (1 << 2) -#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) -#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) - -#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT1_GENERAL_OFFSET 0 -#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 -#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 -#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 -#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 -#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 -#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 - -#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT2_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT3_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT4_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT5_GENERAL_OFFSET 0 - -#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) -#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) - -#define RTC_VERSION_MAJOR_MASK (0xff << 24) -#define RTC_VERSION_MAJOR_OFFSET 24 -#define RTC_VERSION_MINOR_MASK (0xff << 16) -#define RTC_VERSION_MINOR_OFFSET 16 -#define RTC_VERSION_STEP_MASK 0xffff -#define RTC_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_RTC_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h deleted file mode 100644 index eeb7e7f..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ /dev/null @@ -1,415 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 SSP Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_SSP_H__ -#define __MX28_REGS_SSP_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -#if defined(CONFIG_MX23) -struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_status) - - uint32_t reserved1[12]; - - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) -}; -#elif defined(CONFIG_MX28) -struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_xfer_size) - mxs_reg_32(hw_ssp_block_size) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_ddr_ctrl) - mxs_reg_32(hw_ssp_dll_ctrl) - mxs_reg_32(hw_ssp_status) - mxs_reg_32(hw_ssp_dll_sts) - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) -}; -#endif - -static inline int mxs_ssp_bus_id_valid(int bus) -{ -#if defined(CONFIG_MX23) - const unsigned int mxs_ssp_chan_count = 2; -#elif defined(CONFIG_MX28) - const unsigned int mxs_ssp_chan_count = 4; -#endif - - if (bus >= mxs_ssp_chan_count) - return 0; - - if (bus < 0) - return 0; - - return 1; -} - -static inline int mxs_ssp_clock_by_bus(unsigned int clock) -{ -#if defined(CONFIG_MX23) - return 0; -#elif defined(CONFIG_MX28) - return clock; -#endif -} - -static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) -{ - switch (port) { - case 0: - return (struct mxs_ssp_regs *)MXS_SSP0_BASE; - case 1: - return (struct mxs_ssp_regs *)MXS_SSP1_BASE; -#ifdef CONFIG_MX28 - case 2: - return (struct mxs_ssp_regs *)MXS_SSP2_BASE; - case 3: - return (struct mxs_ssp_regs *)MXS_SSP3_BASE; -#endif - default: - return NULL; - } -} -#endif - -#define SSP_CTRL0_SFTRST (1 << 31) -#define SSP_CTRL0_CLKGATE (1 << 30) -#define SSP_CTRL0_RUN (1 << 29) -#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) -#define SSP_CTRL0_LOCK_CS (1 << 27) -#define SSP_CTRL0_IGNORE_CRC (1 << 26) -#define SSP_CTRL0_READ (1 << 25) -#define SSP_CTRL0_DATA_XFER (1 << 24) -#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) -#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 -#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) -#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) -#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) -#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) -#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) -#define SSP_CTRL0_LONG_RESP (1 << 19) -#define SSP_CTRL0_CHECK_RESP (1 << 18) -#define SSP_CTRL0_GET_RESP (1 << 17) -#define SSP_CTRL0_ENABLE (1 << 16) - -#ifdef CONFIG_MX23 -#define SSP_CTRL0_XFER_COUNT_OFFSET 0 -#define SSP_CTRL0_XFER_COUNT_MASK 0xffff -#endif - -#define SSP_CMD0_SOFT_TERMINATE (1 << 26) -#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) -#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) -#define SSP_CMD0_BOOT_ACK_EN (1 << 23) -#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) -#define SSP_CMD0_CONT_CLKING_EN (1 << 21) -#define SSP_CMD0_APPEND_8CYC (1 << 20) -#if defined(CONFIG_MX23) -#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) -#define SSP_CMD0_BLOCK_SIZE_OFFSET 16 -#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) -#define SSP_CMD0_BLOCK_COUNT_OFFSET 8 -#endif -#define SSP_CMD0_CMD_MASK 0xff -#define SSP_CMD0_CMD_OFFSET 0 -#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 -#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 -#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 -#define SSP_CMD0_CMD_MMC_SWITCH 0x06 -#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 -#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 -#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a -#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b -#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e -#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 -#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 -#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 -#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a -#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_MMC_ERASE 0x26 -#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 -#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 -#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 -#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 -#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_SD_SET_DSR 0x04 -#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 -#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 -#define SSP_CMD0_CMD_SD_SEND_CID 0x0a -#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_SD_ERASE 0x26 -#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 -#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 -#define SSP_CMD0_CMD_SD_APP_CMD 0x37 -#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 - -#define SSP_CMD1_CMD_ARG_MASK 0xffffffff -#define SSP_CMD1_CMD_ARG_OFFSET 0 - -#if defined(CONFIG_MX28) -#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff -#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 - -#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) -#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 -#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf -#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 -#endif - -#define SSP_COMPREF_REFERENCE_MASK 0xffffffff -#define SSP_COMPREF_REFERENCE_OFFSET 0 - -#define SSP_COMPMASK_MASK_MASK 0xffffffff -#define SSP_COMPMASK_MASK_OFFSET 0 - -#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) -#define SSP_TIMING_TIMEOUT_OFFSET 16 -#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) -#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 -#define SSP_TIMING_CLOCK_RATE_MASK 0xff -#define SSP_TIMING_CLOCK_RATE_OFFSET 0 - -#define SSP_CTRL1_SDIO_IRQ (1 << 31) -#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) -#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) -#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) -#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) -#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) -#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) -#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) -#define SSP_CTRL1_DMA_ENABLE (1 << 13) -#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) -#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) -#define SSP_CTRL1_PHASE (1 << 10) -#define SSP_CTRL1_POLARITY (1 << 9) -#define SSP_CTRL1_SLAVE_MODE (1 << 8) -#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) -#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 -#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) -#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) -#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) -#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) -#define SSP_CTRL1_SSP_MODE_MASK 0xf -#define SSP_CTRL1_SSP_MODE_OFFSET 0 -#define SSP_CTRL1_SSP_MODE_SPI 0x0 -#define SSP_CTRL1_SSP_MODE_SSI 0x1 -#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 -#define SSP_CTRL1_SSP_MODE_MS 0x4 - -#define SSP_DATA_DATA_MASK 0xffffffff -#define SSP_DATA_DATA_OFFSET 0 - -#define SSP_SDRESP0_RESP0_MASK 0xffffffff -#define SSP_SDRESP0_RESP0_OFFSET 0 - -#define SSP_SDRESP1_RESP1_MASK 0xffffffff -#define SSP_SDRESP1_RESP1_OFFSET 0 - -#define SSP_SDRESP2_RESP2_MASK 0xffffffff -#define SSP_SDRESP2_RESP2_OFFSET 0 - -#define SSP_SDRESP3_RESP3_MASK 0xffffffff -#define SSP_SDRESP3_RESP3_OFFSET 0 - -#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) -#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 -#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) -#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) - -#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) -#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 -#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) -#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 -#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) -#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 -#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) -#define SSP_DLL_CTRL_RESET (1 << 1) -#define SSP_DLL_CTRL_ENABLE (1 << 0) - -#define SSP_STATUS_PRESENT (1 << 31) -#define SSP_STATUS_MS_PRESENT (1 << 30) -#define SSP_STATUS_SD_PRESENT (1 << 29) -#define SSP_STATUS_CARD_DETECT (1 << 28) -#define SSP_STATUS_DMABURST (1 << 22) -#define SSP_STATUS_DMASENSE (1 << 21) -#define SSP_STATUS_DMATERM (1 << 20) -#define SSP_STATUS_DMAREQ (1 << 19) -#define SSP_STATUS_DMAEND (1 << 18) -#define SSP_STATUS_SDIO_IRQ (1 << 17) -#define SSP_STATUS_RESP_CRC_ERR (1 << 16) -#define SSP_STATUS_RESP_ERR (1 << 15) -#define SSP_STATUS_RESP_TIMEOUT (1 << 14) -#define SSP_STATUS_DATA_CRC_ERR (1 << 13) -#define SSP_STATUS_TIMEOUT (1 << 12) -#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) -#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) -#define SSP_STATUS_FIFO_OVRFLW (1 << 9) -#define SSP_STATUS_FIFO_FULL (1 << 8) -#define SSP_STATUS_FIFO_EMPTY (1 << 5) -#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) -#define SSP_STATUS_CMD_BUSY (1 << 3) -#define SSP_STATUS_DATA_BUSY (1 << 2) -#define SSP_STATUS_BUSY (1 << 0) - -#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) -#define SSP_DLL_STS_REF_SEL_OFFSET 8 -#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) -#define SSP_DLL_STS_SLV_SEL_OFFSET 2 -#define SSP_DLL_STS_REF_LOCK (1 << 1) -#define SSP_DLL_STS_SLV_LOCK (1 << 0) - -#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) -#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 -#define SSP_DEBUG_DATA_STALL (1 << 27) -#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) -#define SSP_DEBUG_DAT_SM_OFFSET 24 -#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) -#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) -#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) -#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) -#define SSP_DEBUG_MSTK_SM_OFFSET 20 -#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) -#define SSP_DEBUG_CMD_OE (1 << 19) -#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) -#define SSP_DEBUG_DMA_SM_OFFSET 16 -#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) -#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) -#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) -#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) -#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) -#define SSP_DEBUG_MMC_SM_OFFSET 12 -#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) -#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) -#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) -#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) -#define SSP_DEBUG_CMD_SM_OFFSET 10 -#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) -#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) -#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) -#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) -#define SSP_DEBUG_SSP_CMD (1 << 9) -#define SSP_DEBUG_SSP_RESP (1 << 8) -#define SSP_DEBUG_SSP_RXD_MASK 0xff -#define SSP_DEBUG_SSP_RXD_OFFSET 0 - -#define SSP_VERSION_MAJOR_MASK (0xff << 24) -#define SSP_VERSION_MAJOR_OFFSET 24 -#define SSP_VERSION_MINOR_MASK (0xff << 16) -#define SSP_VERSION_MINOR_OFFSET 16 -#define SSP_VERSION_STEP_MASK 0xffff -#define SSP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_SSP_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h deleted file mode 100644 index 9e19aab..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 TIMROT Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_TIMROT_H__ -#define __MX28_REGS_TIMROT_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_timrot_regs { - mxs_reg_32(hw_timrot_rotctrl) - mxs_reg_32(hw_timrot_rotcount) -#if defined(CONFIG_MX23) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_timcount0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_timcount1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_timcount2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_timcount3) -#elif defined(CONFIG_MX28) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_running_count0) - mxs_reg_32(hw_timrot_fixed_count0) - mxs_reg_32(hw_timrot_match_count0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_running_count1) - mxs_reg_32(hw_timrot_fixed_count1) - mxs_reg_32(hw_timrot_match_count1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_running_count2) - mxs_reg_32(hw_timrot_fixed_count2) - mxs_reg_32(hw_timrot_match_count2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_running_count3) - mxs_reg_32(hw_timrot_fixed_count3) - mxs_reg_32(hw_timrot_match_count3) -#endif - mxs_reg_32(hw_timrot_version) -}; -#endif - -#define TIMROT_ROTCTRL_SFTRST (1 << 31) -#define TIMROT_ROTCTRL_CLKGATE (1 << 30) -#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) -#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) -#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) -#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) -#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) -#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) -#define TIMROT_ROTCTRL_STATE_OFFSET 22 -#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) -#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 -#define TIMROT_ROTCTRL_RELATIVE (1 << 12) -#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 -#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) -#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) -#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) -#endif -#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 -#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) -#endif -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf -#endif -#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 -#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 -#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 -#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 -#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 -#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 -#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 -#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 -#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa -#endif - -#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff -#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 - -#define TIMROT_TIMCTRLn_IRQ (1 << 15) -#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) -#if defined(CONFIG_MX28) -#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) -#endif -#define TIMROT_TIMCTRLn_POLARITY (1 << 8) -#define TIMROT_TIMCTRLn_UPDATE (1 << 7) -#define TIMROT_TIMCTRLn_RELOAD (1 << 6) -#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRLn_SELECT_MASK 0xf -#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 -#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc -#elif defined(CONFIG_MX28) -#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 -#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 -#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf -#endif - -#if defined(CONFIG_MX23) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 -#elif defined(CONFIG_MX28) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 -#endif - -#if defined(CONFIG_MX23) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#elif defined(CONFIG_MX28) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#endif - -#if defined(CONFIG_MX28) -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 -#endif - -#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 -#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) -#elif defined(CONFIG_MX28) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) -#endif -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_IRQ (1 << 15) -#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) -#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) -#endif -#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) -#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 -#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) -#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) -#define TIMROT_TIMCTRL3_UPDATE (1 << 7) -#define TIMROT_TIMCTRL3_RELOAD (1 << 6) -#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRL3_SELECT_MASK 0xf -#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 -#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 -#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 -#endif - -#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) -#define TIMROT_VERSION_MAJOR_OFFSET 24 -#define TIMROT_VERSION_MINOR_MASK (0xff << 16) -#define TIMROT_VERSION_MINOR_OFFSET 16 -#define TIMROT_VERSION_STEP_MASK 0xffff -#define TIMROT_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h deleted file mode 100644 index d89cf27..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h +++ /dev/null @@ -1,219 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale MXS UARTAPP Register Definitions - * - * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ARCH_ARM___MXS_UARTAPP_H -#define __ARCH_ARM___MXS_UARTAPP_H - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_uartapp_regs { - mxs_reg_32(hw_uartapp_ctrl0) - mxs_reg_32(hw_uartapp_ctrl1) - mxs_reg_32(hw_uartapp_ctrl2) - mxs_reg_32(hw_uartapp_linectrl) - mxs_reg_32(hw_uartapp_linectrl2) - mxs_reg_32(hw_uartapp_intr) - mxs_reg_32(hw_uartapp_data) - mxs_reg_32(hw_uartapp_stat) - mxs_reg_32(hw_uartapp_debug) - mxs_reg_32(hw_uartapp_version) - mxs_reg_32(hw_uartapp_autobaud) -}; -#endif - -#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) -#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) -#define UARTAPP_CTRL0_RUN_MASK (1 << 29) -#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) -#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) -#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 -#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) -#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL1_RUN_MASK (1 << 28) - -#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) -#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) -#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) -#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) -#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) -#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) -#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) -#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) -#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 -#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) - -#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) -#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 -#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) -#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) -#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) -#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) -#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) -#define UARTAPP_CTRL2_RTS_MASK (1 << 11) -#define UARTAPP_CTRL2_DTR_MASK (1 << 10) -#define UARTAPP_CTRL2_RXE_MASK (1 << 9) -#define UARTAPP_CTRL2_TXE_MASK (1 << 8) -#define UARTAPP_CTRL2_LBE_MASK (1 << 7) -#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) - -#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) -#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) -#define UARTAPP_CTRL2_UARTEN_MASK 0x01 - -#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) -#define UARTAPP_LINECTRL_BRK_MASK 1 - -#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) - -#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) -#define UARTAPP_INTR_OEIEN_MASK (1 << 26) -#define UARTAPP_INTR_BEIEN_MASK (1 << 25) -#define UARTAPP_INTR_PEIEN_MASK (1 << 24) -#define UARTAPP_INTR_FEIEN_MASK (1 << 23) -#define UARTAPP_INTR_RTIEN_MASK (1 << 22) -#define UARTAPP_INTR_TXIEN_MASK (1 << 21) -#define UARTAPP_INTR_RXIEN_MASK (1 << 20) -#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) -#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) -#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) -#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) - -#define UARTAPP_INTR_ABDIS_MASK (1 << 11) -#define UARTAPP_INTR_OEIS_MASK (1 << 10) -#define UARTAPP_INTR_BEIS_MASK (1 << 9) -#define UARTAPP_INTR_PEIS_MASK (1 << 8) -#define UARTAPP_INTR_FEIS_MASK (1 << 7) -#define UARTAPP_INTR_RTIS_MASK (1 << 6) -#define UARTAPP_INTR_TXIS_MASK (1 << 5) -#define UARTAPP_INTR_RXIS_MASK (1 << 4) -#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) -#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) -#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) -#define UARTAPP_INTR_RIMIS_MASK 0x1 - -#define UARTAPP_DATA_DATA_OFFSET 0 -#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF -#define UARTAPP_STAT_PRESENT_MASK (1 << 31) -#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) -#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) - -#define UARTAPP_STAT_HISPEED_MASK (1 << 30) -#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) -#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) - -#define UARTAPP_STAT_BUSY_MASK (1 << 29) -#define UARTAPP_STAT_CTS_MASK (1 << 28) -#define UARTAPP_STAT_TXFE_MASK (1 << 27) -#define UARTAPP_STAT_RXFF_MASK (1 << 26) -#define UARTAPP_STAT_TXFF_MASK (1 << 25) -#define UARTAPP_STAT_RXFE_MASK (1 << 24) -#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 -#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) - -#define UARTAPP_STAT_OERR_MASK (1 << 19) -#define UARTAPP_STAT_BERR_MASK (1 << 18) -#define UARTAPP_STAT_PERR_MASK (1 << 17) -#define UARTAPP_STAT_FERR_MASK (1 << 16) -#define UARTAPP_STAT_RXCOUNT_OFFSET 0 -#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF - -#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 -#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) - -#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 -#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) - -#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) -#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) -#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) -#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) -#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) -#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 - -#define UARTAPP_VERSION_MAJOR_OFFSET 24 -#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) - -#define UARTAPP_VERSION_MINOR_OFFSET 16 -#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) - -#define UARTAPP_VERSION_STEP_OFFSET 0 -#define UARTAPP_VERSION_STEP_MASK 0xFFFF - -#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 -#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) - -#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 -#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) - -#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) -#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) -#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) -#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) -#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 -#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/include/asm/arch-mxs/regs-usb.h b/arch/arm/include/asm/arch-mxs/regs-usb.h deleted file mode 100644 index 8d5168d..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-usb.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 USB OTG Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct mxs_usb_regs { - uint32_t hw_usbctrl_id; /* 0x000 */ - uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ - uint32_t hw_usbctrl_hwhost; /* 0x008 */ - uint32_t hw_usbctrl_hwdevice; /* 0x00c */ - uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ - uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ - - uint32_t reserved1[26]; - - uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ - uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ - uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ - uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ - uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ - - uint32_t reserved2[27]; - - uint32_t hw_usbctrl_caplength; /* 0x100 */ - uint32_t hw_usbctrl_hcsparams; /* 0x104 */ - uint32_t hw_usbctrl_hccparams; /* 0x108 */ - - uint32_t reserved3[5]; - - uint32_t hw_usbctrl_dciversion; /* 0x120 */ - uint32_t hw_usbctrl_dccparams; /* 0x124 */ - - uint32_t reserved4[6]; - - uint32_t hw_usbctrl_usbcmd; /* 0x140 */ - uint32_t hw_usbctrl_usbsts; /* 0x144 */ - uint32_t hw_usbctrl_usbintr; /* 0x148 */ - uint32_t hw_usbctrl_frindex; /* 0x14c */ - - uint32_t reserved5; - - union { - uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ - uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ - }; - union { - uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ - uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ - }; - - uint32_t hw_usbctrl_ttctrl; /* 0x15c */ - uint32_t hw_usbctrl_burstsize; /* 0x160 */ - uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ - - uint32_t reserved6; - - uint32_t hw_usbctrl_ic_usb; /* 0x16c */ - uint32_t hw_usbctrl_ulpi; /* 0x170 */ - - uint32_t reserved7; - - uint32_t hw_usbctrl_endptnak; /* 0x178 */ - uint32_t hw_usbctrl_endptnaken; /* 0x17c */ - - uint32_t reserved8; - - uint32_t hw_usbctrl_portsc1; /* 0x184 */ - - uint32_t reserved9[7]; - - uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ - uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ - uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ - uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ - uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ - uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ - uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ - uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ - uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ - uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ - uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ - uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ - uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ - uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ - uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ -}; - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) - -#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 -#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) -#define HW_USBCTRL_ID_VERSION_OFFSET 25 -#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) -#define HW_USBCTRL_ID_REVISION_OFFSET 21 -#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) -#define HW_USBCTRL_ID_TAG_OFFSET 16 -#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) -#define HW_USBCTRL_ID_NID_OFFSET 8 -#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) -#define HW_USBCTRL_ID_ID_OFFSET 0 -#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) - -#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 -#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) -#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 -#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) -#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 -#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) -#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) -#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 -#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) -#define HW_USBCTRL_HWGENERAL_RT (1 << 0) - -#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 -#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) -#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 -#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) -#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 -#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) -#define HW_USBCTRL_HWHOST_HC (1 << 0) - -#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 -#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) -#define HW_USBCTRL_HWDEVICE_DC (1 << 0) - -#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) -#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 -#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) -#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 -#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 -#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff - -#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 -#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 -#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff - -#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 -#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff - -#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) -#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) -#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff - -#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 - -#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/arch/arm/include/asm/arch-mxs/regs-usbphy.h deleted file mode 100644 index 643feab..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-usbphy.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 USB PHY Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __REGS_USBPHY_H__ -#define __REGS_USBPHY_H__ - -struct mxs_usbphy_regs { - mxs_reg_32(hw_usbphy_pwd) - mxs_reg_32(hw_usbphy_tx) - mxs_reg_32(hw_usbphy_rx) - mxs_reg_32(hw_usbphy_ctrl) - mxs_reg_32(hw_usbphy_status) - mxs_reg_32(hw_usbphy_debug) - mxs_reg_32(hw_usbphy_debug0_status) - mxs_reg_32(hw_usbphy_debug1) - mxs_reg_32(hw_usbphy_version) - mxs_reg_32(hw_usbphy_ip) -}; - -#define USBPHY_PWD_RXPWDRX (1 << 20) -#define USBPHY_PWD_RXPWDDIFF (1 << 19) -#define USBPHY_PWD_RXPWD1PT1 (1 << 18) -#define USBPHY_PWD_RXPWDENV (1 << 17) -#define USBPHY_PWD_TXPWDV2I (1 << 12) -#define USBPHY_PWD_TXPWDIBIAS (1 << 11) -#define USBPHY_PWD_TXPWDFS (1 << 10) - -#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 -#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) -#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) -#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) -#define USBPHY_TX_TXENCAL45DP (1 << 21) -#define USBPHY_TX_TXCAL45DP_OFFSET 16 -#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) -#define USBPHY_TX_TXENCAL45DM (1 << 13) -#define USBPHY_TX_TXCAL45DM_OFFSET 8 -#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) -#define USBPHY_TX_D_CAL_OFFSET 0 -#define USBPHY_TX_D_CAL_MASK 0xf - -#define USBPHY_RX_RXDBYPASS (1 << 22) -#define USBPHY_RX_DISCONADJ_OFFSET 4 -#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) -#define USBPHY_RX_ENVADJ_OFFSET 0 -#define USBPHY_RX_ENVADJ_MASK 0x7 - -#define USBPHY_CTRL_SFTRST (1 << 31) -#define USBPHY_CTRL_CLKGATE (1 << 30) -#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) -#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) -#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) -#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) -#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) -#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) -#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) -#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) -#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) -#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) -#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) -#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) -#define USBPHY_CTRL_RESUME_IRQ (1 << 10) -#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) -#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) -#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) -#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) -#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) -#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) - -#define USBPHY_STATUS_RESUME_STATUS (1 << 10) -#define USBPHY_STATUS_OTGID_STATUS (1 << 8) -#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) - -#define USBPHY_DEBUG_CLKGATE (1 << 30) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) -#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) -#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) -#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 -#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) -#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 -#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) -#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 -#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) -#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) - -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff - -#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) -#define USBPHY_DEBUG1_ENTX2TX (1 << 12) -#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 -#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf - -#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) -#define USBPHY_VERSION_MAJOR_OFFSET 24 -#define USBPHY_VERSION_MINOR_MASK (0xff << 16) -#define USBPHY_VERSION_MINOR_OFFSET 16 -#define USBPHY_VERSION_STEP_MASK 0xffff -#define USBPHY_VERSION_STEP_OFFSET 0 - -#define USBPHY_IP_DIV_SEL_OFFSET 23 -#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) -#define USBPHY_IP_LFR_SEL_OFFSET 21 -#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) -#define USBPHY_IP_CP_SEL_OFFSET 19 -#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) -#define USBPHY_IP_TSTI_TX_DP (1 << 18) -#define USBPHY_IP_TSTI_TX_DM (1 << 17) -#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) -#define USBPHY_IP_EN_USB_CLKS (1 << 2) -#define USBPHY_IP_PLL_LOCKED (1 << 1) -#define USBPHY_IP_PLL_POWER (1 << 0) - -#endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h deleted file mode 100644 index 6478692..0000000 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 specific functions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MXS_SYS_PROTO_H__ -#define __MXS_SYS_PROTO_H__ - -#include <asm/mach-imx/sys_proto.h> - -int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); - -#ifdef CONFIG_SPL_BUILD - -#if defined(CONFIG_MX23) -#include <asm/arch/iomux-mx23.h> -#elif defined(CONFIG_MX28) -#include <asm/arch/iomux-mx28.h> -#endif - -void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, - const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size); - -void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); -#endif - -struct mxs_pair { - uint8_t boot_pads; - uint8_t boot_mask; - const char *mode; -}; - -static const struct mxs_pair mxs_boot_modes[] = { -#if defined(CONFIG_MX23) - { 0x00, 0x0f, "USB" }, - { 0x01, 0x1f, "I2C, master" }, - { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, - { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, - { 0x04, 0x1f, "NAND" }, - { 0x06, 0x1f, "JTAG" }, - { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0" }, - { 0x0a, 0x1f, "SSP SD/MMC #1" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#elif defined(CONFIG_MX28) - { 0x00, 0x0f, "USB #0" }, - { 0x01, 0x1f, "I2C #0, master, 3V3" }, - { 0x11, 0x1f, "I2C #0, master, 1V8" }, - { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, - { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, - { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, - { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, - { 0x04, 0x1f, "NAND, 3V3" }, - { 0x14, 0x1f, "NAND, 1V8" }, - { 0x06, 0x1f, "JTAG" }, - { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, - { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, - { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, - { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, - { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#endif -}; - -#define MXS_BM_USB 0x00 -#define MXS_BM_I2C_MASTER_3V3 0x01 -#define MXS_BM_I2C_MASTER_1V8 0x11 -#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02 -#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12 -#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03 -#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13 -#define MXS_BM_NAND_3V3 0x04 -#define MXS_BM_NAND_1V8 0x14 -#define MXS_BM_JTAG 0x06 -#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08 -#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18 -#define MXS_BM_SDMMC0_3V3 0x09 -#define MXS_BM_SDMMC0_1V8 0x19 -#define MXS_BM_SDMMC1_3V3 0x0a -#define MXS_BM_SDMMC1_1V8 0x1a - -#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200)) - -struct mxs_spl_data { - uint8_t boot_mode_idx; - uint32_t mem_dram_size; -}; - -int mxs_dram_init(void); - -#endif /* __SYS_PROTO_H__ */ diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h deleted file mode 100644 index 33f6db1..0000000 --- a/arch/arm/include/asm/arch-omap3/am35x_def.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am35x_def.h - TI's AM35x specific definitions. - * - * Based on arch/arm/include/asm/arch-omap3/cpu.h - * - * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> - * - * Copyright (c) 2010 Texas Instruments Incorporated - */ - -#ifndef _AM35X_DEF_H_ -#define _AM35X_DEF_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ - -/* LVL_INTR_CLEAR bits */ -#define USBOTGSS_INT_CLR (1 << 4) - -/* IP_SW_RESET bits */ -#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ -#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ - -/* DEVCONF2 bits */ -#define CONF2_PHY_GPIOMODE (1 << 23) -#define CONF2_OTGMODE (3 << 14) -#define CONF2_NO_OVERRIDE (0 << 14) -#define CONF2_FORCE_HOST (1 << 14) -#define CONF2_FORCE_DEVICE (2 << 14) -#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) -#define CONF2_SESENDEN (1 << 13) -#define CONF2_VBDTCTEN (1 << 12) -#define CONF2_REFFREQ_24MHZ (2 << 8) -#define CONF2_REFFREQ_26MHZ (7 << 8) -#define CONF2_REFFREQ_13MHZ (6 << 8) -#define CONF2_REFFREQ (0xf << 8) -#define CONF2_PHYCLKGD (1 << 7) -#define CONF2_VBUSSENSE (1 << 6) -#define CONF2_PHY_PLLON (1 << 5) -#define CONF2_RESET (1 << 4) -#define CONF2_PHYPWRDN (1 << 3) -#define CONF2_OTGPWRDN (1 << 2) -#define CONF2_DATPOL (1 << 1) - -/* General register mappings of system control module */ -#define AM35X_SCM_GEN_BASE 0x48002270 -struct am35x_scm_general { - u32 res1[0xC4]; /* 0x000 - 0x30C */ - u32 devconf2; /* 0x310 */ - u32 devconf3; /* 0x314 */ - u32 res2[0x2]; /* 0x318 - 0x31C */ - u32 cba_priority; /* 0x320 */ - u32 lvl_intr_clr; /* 0x324 */ - u32 ip_sw_reset; /* 0x328 */ - u32 ipss_clk_ctrl; /* 0x32C */ -}; -#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) - -#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 - -#endif /*__ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#endif /* _AM35X_DEF_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h deleted file mode 100644 index ac537fc..0000000 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - */ -#ifndef _CLOCKS_H_ -#define _CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#define FCK_IVA2_ON 0x00000001 -#define FCK_CORE1_ON 0x03fffe29 -#define ICK_CORE1_ON 0x3ffffffb -#define ICK_CORE2_ON 0x0000001f -#define FCK_WKUP_ON 0x000000e9 -#define ICK_WKUP_ON 0x0000003f -#define FCK_DSS_ON 0x00000005 -#define ICK_DSS_ON 0x00000001 -#define FCK_CAM_ON 0x00000001 -#define ICK_CAM_ON 0x00000001 - -/* Used to index into DPLL parameter tables */ -typedef struct { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -} dpll_param; - -struct dpll_per_36x_param { - unsigned int sys_clk; - unsigned int m; - unsigned int n; - unsigned int m2; - unsigned int m3; - unsigned int m4; - unsigned int m5; - unsigned int m6; - unsigned int m2div; -}; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(void); -extern dpll_param *get_iva_dpll_param(void); -extern dpll_param *get_core_dpll_param(void); -extern dpll_param *get_per_dpll_param(void); -extern dpll_param *get_per2_dpll_param(void); - -extern dpll_param *get_36x_mpu_dpll_param(void); -extern dpll_param *get_36x_iva_dpll_param(void); -extern dpll_param *get_36x_core_dpll_param(void); -extern dpll_param *get_36x_per_dpll_param(void); -extern dpll_param *get_36x_per2_dpll_param(void); - -#endif diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h deleted file mode 100644 index 48bb391..0000000 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - */ -#ifndef _CLOCKS_OMAP3_H_ -#define _CLOCKS_OMAP3_H_ - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* - * The following configurations are OPP and SysClk value independant - * and hence are defined here. All the other DPLL related values are - * tabulated in lowlevel_init.S. - */ - -/* CORE DPLL */ -#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -#define CORE_FUSB_DIV 2 /* 41.5MHz: */ -#define CORE_L4_DIV 2 /* 83MHz : L4 */ -#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ -#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ -#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) - -/* MPU DPLL */ - -#define MPU_M_12_ES1 0x0FE -#define MPU_N_12_ES1 0x07 -#define MPU_FSEL_12_ES1 0x05 -#define MPU_M2_12_ES1 0x01 - -#define MPU_M_12_ES2 0x0FA -#define MPU_N_12_ES2 0x05 -#define MPU_FSEL_12_ES2 0x07 -#define MPU_M2_ES2 0x01 - -#define MPU_M_12 0x085 -#define MPU_N_12 0x05 -#define MPU_FSEL_12 0x07 -#define MPU_M2_12 0x01 - -#define MPU_M_13_ES1 0x17D -#define MPU_N_13_ES1 0x0C -#define MPU_FSEL_13_ES1 0x03 -#define MPU_M2_13_ES1 0x01 - -#define MPU_M_13_ES2 0x258 -#define MPU_N_13_ES2 0x0C -#define MPU_FSEL_13_ES2 0x03 -#define MPU_M2_13_ES2 0x01 - -#define MPU_M_13 0x10A -#define MPU_N_13 0x0C -#define MPU_FSEL_13 0x03 -#define MPU_M2_13 0x01 - -#define MPU_M_19P2_ES1 0x179 -#define MPU_N_19P2_ES1 0x12 -#define MPU_FSEL_19P2_ES1 0x04 -#define MPU_M2_19P2_ES1 0x01 - -#define MPU_M_19P2_ES2 0x271 -#define MPU_N_19P2_ES2 0x17 -#define MPU_FSEL_19P2_ES2 0x03 -#define MPU_M2_19P2_ES2 0x01 - -#define MPU_M_19P2 0x14C -#define MPU_N_19P2 0x17 -#define MPU_FSEL_19P2 0x03 -#define MPU_M2_19P2 0x01 - -#define MPU_M_26_ES1 0x17D -#define MPU_N_26_ES1 0x19 -#define MPU_FSEL_26_ES1 0x03 -#define MPU_M2_26_ES1 0x01 - -#define MPU_M_26_ES2 0x0FA -#define MPU_N_26_ES2 0x0C -#define MPU_FSEL_26_ES2 0x07 -#define MPU_M2_26_ES2 0x01 - -#define MPU_M_26 0x085 -#define MPU_N_26 0x0C -#define MPU_FSEL_26 0x07 -#define MPU_M2_26 0x01 - -#define MPU_M_38P4_ES1 0x1FA -#define MPU_N_38P4_ES1 0x32 -#define MPU_FSEL_38P4_ES1 0x03 -#define MPU_M2_38P4_ES1 0x01 - -#define MPU_M_38P4_ES2 0x271 -#define MPU_N_38P4_ES2 0x2F -#define MPU_FSEL_38P4_ES2 0x03 -#define MPU_M2_38P4_ES2 0x01 - -#define MPU_M_38P4 0x14C -#define MPU_N_38P4 0x2F -#define MPU_FSEL_38P4 0x03 -#define MPU_M2_38P4 0x01 - -/* IVA DPLL */ - -#define IVA_M_12_ES1 0x07D -#define IVA_N_12_ES1 0x05 -#define IVA_FSEL_12_ES1 0x07 -#define IVA_M2_12_ES1 0x01 - -#define IVA_M_12_ES2 0x0B4 -#define IVA_N_12_ES2 0x05 -#define IVA_FSEL_12_ES2 0x07 -#define IVA_M2_12_ES2 0x01 - -#define IVA_M_12 0x085 -#define IVA_N_12 0x05 -#define IVA_FSEL_12 0x07 -#define IVA_M2_12 0x01 - -#define IVA_M_13_ES1 0x0FA -#define IVA_N_13_ES1 0x0C -#define IVA_FSEL_13_ES1 0x03 -#define IVA_M2_13_ES1 0x01 - -#define IVA_M_13_ES2 0x168 -#define IVA_N_13_ES2 0x0C -#define IVA_FSEL_13_ES2 0x03 -#define IVA_M2_13_ES2 0x01 - -#define IVA_M_13 0x10A -#define IVA_N_13 0x0C -#define IVA_FSEL_13 0x03 -#define IVA_M2_13 0x01 - -#define IVA_M_19P2_ES1 0x082 -#define IVA_N_19P2_ES1 0x09 -#define IVA_FSEL_19P2_ES1 0x07 -#define IVA_M2_19P2_ES1 0x01 - -#define IVA_M_19P2_ES2 0x0E1 -#define IVA_N_19P2_ES2 0x0B -#define IVA_FSEL_19P2_ES2 0x06 -#define IVA_M2_19P2_ES2 0x01 - -#define IVA_M_19P2 0x14C -#define IVA_N_19P2 0x17 -#define IVA_FSEL_19P2 0x03 -#define IVA_M2_19P2 0x01 - -#define IVA_M_26_ES1 0x07D -#define IVA_N_26_ES1 0x0C -#define IVA_FSEL_26_ES1 0x07 -#define IVA_M2_26_ES1 0x01 - -#define IVA_M_26_ES2 0x0B4 -#define IVA_N_26_ES2 0x0C -#define IVA_FSEL_26_ES2 0x07 -#define IVA_M2_26_ES2 0x01 - -#define IVA_M_26 0x085 -#define IVA_N_26 0x0C -#define IVA_FSEL_26 0x07 -#define IVA_M2_26 0x01 - -#define IVA_M_38P4_ES1 0x13F -#define IVA_N_38P4_ES1 0x30 -#define IVA_FSEL_38P4_ES1 0x03 -#define IVA_M2_38P4_ES1 0x01 - -#define IVA_M_38P4_ES2 0x0E1 -#define IVA_N_38P4_ES2 0x17 -#define IVA_FSEL_38P4_ES2 0x06 -#define IVA_M2_38P4_ES2 0x01 - -#define IVA_M_38P4 0x14C -#define IVA_N_38P4 0x2F -#define IVA_FSEL_38P4 0x03 -#define IVA_M2_38P4 0x01 - -/* CORE DPLL */ - -#define CORE_M_12 0xA6 -#define CORE_N_12 0x05 -#define CORE_FSEL_12 0x07 -#define CORE_M2_12 0x01 /* M3 of 2 */ - -#define CORE_M_12_ES1 0x19F -#define CORE_N_12_ES1 0x0E -#define CORE_FSL_12_ES1 0x03 -#define CORE_M2_12_ES1 0x1 /* M3 of 2 */ - -#define CORE_M_13 0x14C -#define CORE_N_13 0x0C -#define CORE_FSEL_13 0x03 -#define CORE_M2_13 0x01 /* M3 of 2 */ - -#define CORE_M_13_ES1 0x1B2 -#define CORE_N_13_ES1 0x10 -#define CORE_FSL_13_ES1 0x03 -#define CORE_M2_13_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_19P2 0x19F -#define CORE_N_19P2 0x17 -#define CORE_FSEL_19P2 0x03 -#define CORE_M2_19P2 0x01 /* M3 of 2 */ - -#define CORE_M_19P2_ES1 0x19F -#define CORE_N_19P2_ES1 0x17 -#define CORE_FSL_19P2_ES1 0x03 -#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_26 0xA6 -#define CORE_N_26 0x0C -#define CORE_FSEL_26 0x07 -#define CORE_M2_26 0x01 /* M3 of 2 */ - -#define CORE_M_26_ES1 0x1B2 -#define CORE_N_26_ES1 0x21 -#define CORE_FSL_26_ES1 0x03 -#define CORE_M2_26_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_38P4 0x19F -#define CORE_N_38P4 0x2F -#define CORE_FSEL_38P4 0x03 -#define CORE_M2_38P4 0x01 /* M3 of 2 */ - -#define CORE_M_38P4_ES1 0x19F -#define CORE_N_38P4_ES1 0x2F -#define CORE_FSL_38P4_ES1 0x03 -#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ - -/* PER DPLL */ - -#define PER_M_12 0xD8 -#define PER_N_12 0x05 -#define PER_FSEL_12 0x07 -#define PER_M2_12 0x09 - -#define PER_M_13 0x1B0 -#define PER_N_13 0x0C -#define PER_FSEL_13 0x03 -#define PER_M2_13 0x09 - -#define PER_M_19P2 0xE1 -#define PER_N_19P2 0x09 -#define PER_FSEL_19P2 0x07 -#define PER_M2_19P2 0x09 - -#define PER_M_26 0xD8 -#define PER_N_26 0x0C -#define PER_FSEL_26 0x07 -#define PER_M2_26 0x09 - -#define PER_M_38P4 0xE1 -#define PER_N_38P4 0x13 -#define PER_FSEL_38P4 0x07 -#define PER_M2_38P4 0x09 - -/* PER2 DPLL */ -#define PER2_M_12 0x78 -#define PER2_N_12 0x0B -#define PER2_FSEL_12 0x03 -#define PER2_M2_12 0x01 - -#define PER2_M_13 0x78 -#define PER2_N_13 0x0C -#define PER2_FSEL_13 0x03 -#define PER2_M2_13 0x01 - -#define PER2_M_19P2 0x2EE -#define PER2_N_19P2 0x0B -#define PER2_FSEL_19P2 0x06 -#define PER2_M2_19P2 0x0A - -#define PER2_M_26 0x78 -#define PER2_N_26 0x0C -#define PER2_FSEL_26 0x03 -#define PER2_M2_26 0x01 - -#define PER2_M_38P4 0x2EE -#define PER2_N_38P4 0x0B -#define PER2_FSEL_38P4 0x06 -#define PER2_M2_38P4 0x0A - -/* 36XX PER DPLL */ - -#define PER_36XX_M_12 0x1B0 -#define PER_36XX_N_12 0x05 -#define PER_36XX_FSEL_12 0x07 -#define PER_36XX_M2_12 0x09 - -#define PER_36XX_M_13 0x360 -#define PER_36XX_N_13 0x0C -#define PER_36XX_FSEL_13 0x03 -#define PER_36XX_M2_13 0x09 - -#define PER_36XX_M_19P2 0x1C2 -#define PER_36XX_N_19P2 0x09 -#define PER_36XX_FSEL_19P2 0x07 -#define PER_36XX_M2_19P2 0x09 - -#define PER_36XX_M_26 0x1B0 -#define PER_36XX_N_26 0x0C -#define PER_36XX_FSEL_26 0x07 -#define PER_36XX_M2_26 0x09 - -#define PER_36XX_M_38P4 0x1C2 -#define PER_36XX_N_38P4 0x13 -#define PER_36XX_FSEL_38P4 0x07 -#define PER_36XX_M2_38P4 0x09 - -/* 36XX PER2 DPLL */ - -#define PER2_36XX_M_12 0x50 -#define PER2_36XX_N_12 0x00 -#define PER2_36XX_M2_12 0x08 - -#define PER2_36XX_M_13 0x1BB -#define PER2_36XX_N_13 0x05 -#define PER2_36XX_M2_13 0x08 - -#define PER2_36XX_M_19P2 0x32 -#define PER2_36XX_N_19P2 0x00 -#define PER2_36XX_M2_19P2 0x08 - -#define PER2_36XX_M_26 0x1BB -#define PER2_36XX_N_26 0x0B -#define PER2_36XX_M2_26 0x08 - -#define PER2_36XX_M_38P4 0x19 -#define PER2_36XX_N_38P4 0x00 -#define PER2_36XX_M2_38P4 0x08 - -#endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h deleted file mode 100644 index 3f0182e..0000000 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ /dev/null @@ -1,504 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -/* Register offsets of common modules */ -/* Control */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct ctrl { - u8 res1[0xC0]; - u16 gpmc_nadv_ale; /* 0xC0 */ - u16 gpmc_noe; /* 0xC2 */ - u16 gpmc_nwe; /* 0xC4 */ - u8 res2[0x22A]; - u32 status; /* 0x2F0 */ - u32 gpstatus; /* 0x2F4 */ - u8 res3[0x08]; - u32 rpubkey_0; /* 0x300 */ - u32 rpubkey_1; /* 0x304 */ - u32 rpubkey_2; /* 0x308 */ - u32 rpubkey_3; /* 0x30C */ - u32 rpubkey_4; /* 0x310 */ - u8 res4[0x04]; - u32 randkey_0; /* 0x318 */ - u32 randkey_1; /* 0x31C */ - u32 randkey_2; /* 0x320 */ - u32 randkey_3; /* 0x324 */ - u8 res5[0x124]; - u32 ctrl_omap_stat; /* 0x44C */ -}; -#else /* __ASSEMBLY__ */ -#define CONTROL_STATUS 0x2F0 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct ctrl_id { - u8 res1[0x4]; - u32 idcode; /* 0x04 */ - u32 prod_id; /* 0x08 */ - u32 sku_id; /* 0x0c */ - u8 res2[0x08]; - u32 die_id_0; /* 0x18 */ - u32 die_id_1; /* 0x1C */ - u32 die_id_2; /* 0x20 */ - u32 die_id_3; /* 0x24 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* boot pin mask */ -#define SYSBOOT_MASK 0x1F - -/* device speed */ -#define SKUID_CLK_MASK 0xf -#define SKUID_CLK_600MHZ 0x0 -#define SKUID_CLK_720MHZ 0x8 - -#define GPMC_BASE (OMAP34XX_GPMC_BASE) -#define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) - -#ifndef __KERNEL_STRICT_NAMES -#ifdef __ASSEMBLY__ -#define GPMC_CONFIG1 0x00 -#define GPMC_CONFIG2 0x04 -#define GPMC_CONFIG3 0x08 -#define GPMC_CONFIG4 0x0C -#define GPMC_CONFIG5 0x10 -#define GPMC_CONFIG6 0x14 -#define GPMC_CONFIG7 0x18 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* GPMC Mapping */ -#define FLASH_BASE 0x10000000 /* NOR flash, */ - /* aligned to 256 Meg */ -#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ - /* aligned to 64 Meg */ -#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ - /* aligned to 256 Meg */ -#define DEBUG_BASE 0x08000000 /* debug board */ -#define NAND_BASE 0x30000000 /* NAND addr */ - /* (actual size small port) */ -#define ONENAND_MAP 0x20000000 /* OneNand addr */ - /* (actual size small port) */ -/* SMS */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct sms { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x34]; - u32 rg_att0; /* 0x48 */ - u8 res3[0x84]; - u32 class_arb0; /* 0xD0 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define BURSTCOMPLETE_GROUP7 (0x1 << 31) - -/* SDRC */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct sdrc_cs { - u32 mcfg; /* 0x80 || 0xB0 */ - u32 mr; /* 0x84 || 0xB4 */ - u8 res1[0x4]; - u32 emr2; /* 0x8C || 0xBC */ - u8 res2[0x14]; - u32 rfr_ctrl; /* 0x84 || 0xD4 */ - u32 manual; /* 0xA8 || 0xD8 */ - u8 res3[0x4]; -}; - -struct sdrc_actim { - u32 ctrla; /* 0x9C || 0xC4 */ - u32 ctrlb; /* 0xA0 || 0xC8 */ -}; - -struct sdrc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u32 status; /* 0x14 */ - u8 res2[0x28]; - u32 cs_cfg; /* 0x40 */ - u32 sharing; /* 0x44 */ - u8 res3[0x18]; - u32 dlla_ctrl; /* 0x60 */ - u32 dlla_status; /* 0x64 */ - u32 dllb_ctrl; /* 0x68 */ - u32 dllb_status; /* 0x6C */ - u32 power; /* 0x70 */ - u8 res4[0xC]; - struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ -}; - -/* EMIF4 */ -typedef struct emif4 { - unsigned int emif_mod_id_rev; - unsigned int sdram_sts; - unsigned int sdram_config; - unsigned int res1; - unsigned int sdram_refresh_ctrl; - unsigned int sdram_refresh_ctrl_shdw; - unsigned int sdram_time1; - unsigned int sdram_time1_shdw; - unsigned int sdram_time2; - unsigned int sdram_time2_shdw; - unsigned int sdram_time3; - unsigned int sdram_time3_shdw; - unsigned char res2[8]; - unsigned int sdram_pwr_mgmt; - unsigned int sdram_pwr_mgmt_shdw; - unsigned char res3[32]; - unsigned int sdram_iodft_tlgc; - unsigned char res4[128]; - unsigned int ddr_phyctrl1; - unsigned int ddr_phyctrl1_shdw; - unsigned int ddr_phyctrl2; -} emif4_t; - -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define DLLPHASE_90 (0x1 << 1) -#define LOADDLL (0x1 << 2) -#define ENADLL (0x1 << 3) -#define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) - -#define PAGEPOLICY_HIGH (0x1 << 0) -#define SRFRONRESET (0x1 << 7) -#define PWDNEN (0x1 << 2) -#define WAKEUPPROC (0x1 << 26) - -#define DDR_SDRAM (0x1 << 0) -#define DEEPPD (0x1 << 3) -#define B32NOT16 (0x1 << 4) -#define BANKALLOCATION (0x2 << 6) -#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ -#define ADDRMUXLEGACY (0x1 << 19) -#define CASWIDTH_10BITS (0x5 << 20) -#define RASWIDTH_13BITS (0x2 << 24) -#define BURSTLENGTH4 (0x2 << 0) -#define CASL3 (0x3 << 4) -#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) -#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) -#define ARE_ARCV_1 (0x1 << 0) -#define ARCV (0x4e2 << 8) /* Autorefresh count */ -#define OMAP34XX_SDRC_CS0 0x80000000 -#define OMAP34XX_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET (0x1 << 1) -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - -/* DMA */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct dma4_chan { - u32 ccr; - u32 clnk_ctrl; - u32 cicr; - u32 csr; - u32 csdp; - u32 cen; - u32 cfn; - u32 cssa; - u32 cdsa; - u32 csel; - u32 csfl; - u32 cdel; - u32 cdfl; - u32 csac; - u32 cdac; - u32 ccen; - u32 ccfn; - u32 color; -}; - -struct dma4 { - u32 revision; - u8 res1[0x4]; - u32 irqstatus_l[0x4]; - u32 irqenable_l[0x4]; - u32 sysstatus; - u32 ocp_sysconfig; - u8 res2[0x34]; - u32 caps_0; - u8 res3[0x4]; - u32 caps_2; - u32 caps_3; - u32 caps_4; - u32 gcr; - u8 res4[0x4]; - struct dma4_chan chan[32]; -}; - -#endif /*__ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* timer regs offsets (32 bit regs) */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u32 tistat; /* 0x14 r */ - u32 tisr; /* 0x18 rw */ - u32 tier; /* 0x1c rw */ - u32 twer; /* 0x20 rw */ - u32 tclr; /* 0x24 rw */ - u32 tcrr; /* 0x28 rw */ - u32 tldr; /* 0x2c rw */ - u32 ttgr; /* 0x30 rw */ - u32 twpc; /* 0x34 r*/ - u32 tmar; /* 0x38 rw*/ - u32 tcar1; /* 0x3c r */ - u32 tcicr; /* 0x40 rw */ - u32 tcar2; /* 0x44 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define PRCM_BASE 0x48004000 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct prcm { - u32 fclken_iva2; /* 0x00 */ - u32 clken_pll_iva2; /* 0x04 */ - u8 res1[0x1c]; - u32 idlest_pll_iva2; /* 0x24 */ - u8 res2[0x18]; - u32 clksel1_pll_iva2 ; /* 0x40 */ - u32 clksel2_pll_iva2; /* 0x44 */ - u8 res3[0x8bc]; - u32 clken_pll_mpu; /* 0x904 */ - u8 res4[0x1c]; - u32 idlest_pll_mpu; /* 0x924 */ - u8 res5[0x18]; - u32 clksel1_pll_mpu; /* 0x940 */ - u32 clksel2_pll_mpu; /* 0x944 */ - u8 res6[0xb8]; - u32 fclken1_core; /* 0xa00 */ - u32 res_fclken2_core; - u32 fclken3_core; /* 0xa08 */ - u8 res7[0x4]; - u32 iclken1_core; /* 0xa10 */ - u32 iclken2_core; /* 0xa14 */ - u32 iclken3_core; /* 0xa18 */ - u8 res8[0x24]; - u32 clksel_core; /* 0xa40 */ - u8 res9[0xbc]; - u32 fclken_gfx; /* 0xb00 */ - u8 res10[0xc]; - u32 iclken_gfx; /* 0xb10 */ - u8 res11[0x2c]; - u32 clksel_gfx; /* 0xb40 */ - u8 res12[0xbc]; - u32 fclken_wkup; /* 0xc00 */ - u8 res13[0xc]; - u32 iclken_wkup; /* 0xc10 */ - u8 res14[0xc]; - u32 idlest_wkup; /* 0xc20 */ - u8 res15[0x1c]; - u32 clksel_wkup; /* 0xc40 */ - u8 res16[0xbc]; - u32 clken_pll; /* 0xd00 */ - u32 clken2_pll; /* 0xd04 */ - u8 res17[0x18]; - u32 idlest_ckgen; /* 0xd20 */ - u32 idlest2_ckgen; /* 0xd24 */ - u8 res18[0x18]; - u32 clksel1_pll; /* 0xd40 */ - u32 clksel2_pll; /* 0xd44 */ - u32 clksel3_pll; /* 0xd48 */ - u32 clksel4_pll; /* 0xd4c */ - u32 clksel5_pll; /* 0xd50 */ - u8 res19[0xac]; - u32 fclken_dss; /* 0xe00 */ - u8 res20[0xc]; - u32 iclken_dss; /* 0xe10 */ - u8 res21[0x2c]; - u32 clksel_dss; /* 0xe40 */ - u8 res22[0xbc]; - u32 fclken_cam; /* 0xf00 */ - u8 res23[0xc]; - u32 iclken_cam; /* 0xf10 */ - u8 res24[0x2c]; - u32 clksel_cam; /* 0xf40 */ - u8 res25[0xbc]; - u32 fclken_per; /* 0x1000 */ - u8 res26[0xc]; - u32 iclken_per; /* 0x1010 */ - u8 res27[0x2c]; - u32 clksel_per; /* 0x1040 */ - u8 res28[0xfc]; - u32 clksel1_emu; /* 0x1140 */ - u8 res29[0x2bc]; - u32 fclken_usbhost; /* 0x1400 */ - u8 res30[0xc]; - u32 iclken_usbhost; /* 0x1410 */ -}; -#else /* __ASSEMBLY__ */ -#define CM_CLKSEL_CORE 0x48004a40 -#define CM_CLKSEL_GFX 0x48004b40 -#define CM_CLKSEL_WKUP 0x48004c40 -#define CM_CLKEN_PLL 0x48004d00 -#define CM_CLKSEL1_PLL 0x48004d40 -#define CM_CLKSEL1_EMU 0x48005140 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define PRM_BASE 0x48306000 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct prm { - u8 res1[0xd40]; - u32 clksel; /* 0xd40 */ - u8 res2[0x50c]; - u32 rstctrl; /* 0x1250 */ - u8 res3[0x1c]; - u32 clksrc_ctrl; /* 0x1270 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define PRM_RSTCTRL 0x48307250 -#define PRM_RSTCTRL_RESET 0x04 -#define PRM_RSTST 0x48307258 -#define PRM_RSTST_WARM_RESET_MASK 0x7D2 -#define SYSCLKDIV_1 (0x1 << 6) -#define SYSCLKDIV_2 (0x1 << 7) - -#define CLKSEL_GPT1 (0x1 << 0) - -#define EN_GPT1 (0x1 << 0) -#define EN_32KSYNC (0x1 << 2) - -#define ST_WDT2 (0x1 << 5) - -#define ST_MPU_CLK (0x1 << 0) - -#define ST_CORE_CLK (0x1 << 0) - -#define ST_PERIPH_CLK (0x1 << 1) - -#define ST_IVA2_CLK (0x1 << 0) - -#define RESETDONE (0x1 << 0) - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct pm { - u8 res1[0x48]; - u32 req_info_permission_0; /* 0x48 */ - u8 res2[0x4]; - u32 read_permission_0; /* 0x50 */ - u8 res3[0x4]; - u32 wirte_permission_0; /* 0x58 */ - u8 res4[0x4]; - u32 addr_match_1; /* 0x58 */ - u8 res5[0x4]; - u32 req_info_permission_1; /* 0x68 */ - u8 res6[0x14]; - u32 addr_match_2; /* 0x80 */ -}; -#endif /*__ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - -#define NOT_EARLY 0 - -/* I2C base */ -#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) -#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) -#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) - -/* MUSB base */ -#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) - -/* OMAP3 GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0014 -#define OMAP_GPIO_IRQSTATUS1 0x0018 -#define OMAP_GPIO_IRQSTATUS2 0x0028 -#define OMAP_GPIO_IRQENABLE2 0x002c -#define OMAP_GPIO_IRQENABLE1 0x001c -#define OMAP_GPIO_WAKE_EN 0x0020 -#define OMAP_GPIO_CTRL 0x0030 -#define OMAP_GPIO_OE 0x0034 -#define OMAP_GPIO_DATAIN 0x0038 -#define OMAP_GPIO_DATAOUT 0x003c -#define OMAP_GPIO_LEVELDETECT0 0x0040 -#define OMAP_GPIO_LEVELDETECT1 0x0044 -#define OMAP_GPIO_RISINGDETECT 0x0048 -#define OMAP_GPIO_FALLINGDETECT 0x004c -#define OMAP_GPIO_DEBOUNCE_EN 0x0050 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0054 -#define OMAP_GPIO_CLEARIRQENABLE1 0x0060 -#define OMAP_GPIO_SETIRQENABLE1 0x0064 -#define OMAP_GPIO_CLEARWKUENA 0x0080 -#define OMAP_GPIO_SETWKUENA 0x0084 -#define OMAP_GPIO_CLEARDATAOUT 0x0090 -#define OMAP_GPIO_SETDATAOUT 0x0094 - -#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap3/dma.h b/arch/arm/include/asm/arch-omap3/dma.h deleted file mode 100644 index d26e490..0000000 --- a/arch/arm/include/asm/arch-omap3/dma.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __SDMA_H -#define __SDMA_H - -/* Copyright (C) 2011 - * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> - */ - -/* Functions */ -void omap3_dma_init(void); -int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, - uint32_t sze); -int omap3_dma_start_transfer(uint32_t chan); -int omap3_dma_wait_for_transfer(uint32_t chan); -int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config); -int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); - -/* Register settings */ -#define CSDP_DATA_TYPE_8BIT 0x0 -#define CSDP_DATA_TYPE_16BIT 0x1 -#define CSDP_DATA_TYPE_32BIT 0x2 -#define CSDP_SRC_BURST_SINGLE (0x0 << 7) -#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7) -#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7) -#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7) -#define CSDP_DST_BURST_SINGLE (0x0 << 14) -#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14) -#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14) -#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14) -#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18) -#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18) -#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19) -#define CSDP_DST_ENDIAN_BIG (0x1 << 19) -#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20) -#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20) -#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21) -#define CSDP_SRC_ENDIAN_BIG (0x1 << 21) - -#define CCR_READ_PRIORITY_LOW (0x0 << 6) -#define CCR_READ_PRIORITY_HIGH (0x1 << 6) -#define CCR_ENABLE_DISABLED (0x0 << 7) -#define CCR_ENABLE_ENABLE (0x1 << 7) -#define CCR_SRC_AMODE_CONSTANT (0x0 << 12) -#define CCR_SRC_AMODE_POST_INC (0x1 << 12) -#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12) -#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12) -#define CCR_DST_AMODE_CONSTANT (0x0 << 14) -#define CCR_DST_AMODE_POST_INC (0x1 << 14) -#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14) -#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14) - -#define CCR_RD_ACTIVE_MASK (1 << 9) -#define CCR_WR_ACTIVE_MASK (1 << 10) - -#define CSR_TRANS_ERR (1 << 8) -#define CSR_SUPERVISOR_ERR (1 << 10) -#define CSR_MISALIGNED_ADRS_ERR (1 << 11) - -/* others */ -#define CHAN_NR_MIN 0 -#define CHAN_NR_MAX 31 - -#endif /* __SDMA_H */ diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h deleted file mode 100644 index 8bf6b48..0000000 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * Referred to Linux Kernel DSS driver files for OMAP3 by - * Tomi Valkeinen from drivers/video/omap2/dss/ - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 and any - * later version the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef DSS_H -#define DSS_H - -/* DSS Base Registers */ -#define OMAP3_DSS_BASE 0x48050000 -#define OMAP3_DISPC_BASE 0x48050400 -#define OMAP3_VENC_BASE 0x48050C00 - -/* DSS Registers */ -struct dss_regs { - u32 revision; /* 0x00 */ - u8 res1[12]; /* 0x04 */ - u32 sysconfig; /* 0x10 */ - u32 sysstatus; /* 0x14 */ - u32 irqstatus; /* 0x18 */ - u8 res2[36]; /* 0x1C */ - u32 control; /* 0x40 */ - u32 sdi_control; /* 0x44 */ - u32 pll_control; /* 0x48 */ -}; - -/* DISPC Registers */ -struct dispc_regs { - u32 revision; /* 0x00 */ - u8 res1[12]; /* 0x04 */ - u32 sysconfig; /* 0x10 */ - u32 sysstatus; /* 0x14 */ - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res2[32]; /* 0x20 */ - u32 control; /* 0x40 */ - u32 config; /* 0x44 */ - u32 reserve_2; /* 0x48 */ - u32 default_color0; /* 0x4C */ - u32 default_color1; /* 0x50 */ - u32 trans_color0; /* 0x54 */ - u32 trans_color1; /* 0x58 */ - u32 line_status; /* 0x5C */ - u32 line_number; /* 0x60 */ - u32 timing_h; /* 0x64 */ - u32 timing_v; /* 0x68 */ - u32 pol_freq; /* 0x6C */ - u32 divisor; /* 0x70 */ - u32 global_alpha; /* 0x74 */ - u32 size_dig; /* 0x78 */ - u32 size_lcd; /* 0x7C */ - u32 gfx_ba0; /* 0x80 */ - u32 gfx_ba1; /* 0x84 */ - u32 gfx_position; /* 0x88 */ - u32 gfx_size; /* 0x8C */ - u8 unused[16]; /* 0x90 */ - u32 gfx_attributes; /* 0xA0 */ - u32 gfx_fifo_threshold; /* 0xA4 */ - u32 gfx_fifo_size_status; /* 0xA8 */ - u32 gfx_row_inc; /* 0xAC */ - u32 gfx_pixel_inc; /* 0xB0 */ - u32 gfx_window_skip; /* 0xB4 */ - u32 gfx_table_ba; /* 0xB8 */ -}; - -/* VENC Registers */ -struct venc_regs { - u32 rev_id; /* 0x00 */ - u32 status; /* 0x04 */ - u32 f_control; /* 0x08 */ - u32 reserve_1; /* 0x0C */ - u32 vidout_ctrl; /* 0x10 */ - u32 sync_ctrl; /* 0x14 */ - u32 reserve_2; /* 0x18 */ - u32 llen; /* 0x1C */ - u32 flens; /* 0x20 */ - u32 hfltr_ctrl; /* 0x24 */ - u32 cc_carr_wss_carr; /* 0x28 */ - u32 c_phase; /* 0x2C */ - u32 gain_u; /* 0x30 */ - u32 gain_v; /* 0x34 */ - u32 gain_y; /* 0x38 */ - u32 black_level; /* 0x3C */ - u32 blank_level; /* 0x40 */ - u32 x_color; /* 0x44 */ - u32 m_control; /* 0x48 */ - u32 bstamp_wss_data; /* 0x4C */ - u32 s_carr; /* 0x50 */ - u32 line21; /* 0x54 */ - u32 ln_sel; /* 0x58 */ - u32 l21__wc_ctl; /* 0x5C */ - u32 htrigger_vtrigger; /* 0x60 */ - u32 savid__eavid; /* 0x64 */ - u32 flen__fal; /* 0x68 */ - u32 lal__phase_reset; /* 0x6C */ - u32 hs_int_start_stop_x; /* 0x70 */ - u32 hs_ext_start_stop_x; /* 0x74 */ - u32 vs_int_start_x; /* 0x78 */ - u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */ - u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */ - u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */ - u32 vs_ext_stop_y; /* 0x88 */ - u32 reserve_3; /* 0x8C */ - u32 avid_start_stop_x; /* 0x90 */ - u32 avid_start_stop_y; /* 0x94 */ - u32 reserve_4; /* 0x98 */ - u32 reserve_5; /* 0x9C */ - u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */ - u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */ - u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */ - u32 reserve_6; /* 0xAC */ - u32 tvdetgp_int_start_stop_x; /* 0xB0 */ - u32 tvdetgp_int_start_stop_y; /* 0xB4 */ - u32 gen_ctrl; /* 0xB8 */ - u32 reserve_7; /* 0xBC */ - u32 reserve_8; /* 0xC0 */ - u32 output_control; /* 0xC4 */ - u32 dac_b__dac_c; /* 0xC8 */ - u32 height_width; /* 0xCC */ -}; - -/* Few Register Offsets */ -#define TFTSTN_SHIFT 3 -#define DATALINES_SHIFT 8 - -#define GFX_ENABLE 1 -#define GFX_FORMAT_SHIFT 1 -#define LOADMODE_SHIFT 1 - -#define DSS_SOFTRESET (1 << 1) -#define DSS_RESETDONE 1 - -/* Enabling Display controller */ -#define LCD_ENABLE 1 -#define DIG_ENABLE (1 << 1) -#define GO_LCD (1 << 5) -#define GO_DIG (1 << 6) -#define GP_OUT0 (1 << 15) -#define GP_OUT1 (1 << 16) - -/* Configure VENC DSS Params */ -#define VENC_CLK_ENABLE (1 << 3) -#define DAC_DEMEN (1 << 4) -#define DAC_POWERDN (1 << 5) -#define VENC_OUT_SEL (1 << 6) -#define DIG_LPP_SHIFT 16 - -/* LCD display type */ -#define PASSIVE_DISPLAY 0 -#define ACTIVE_DISPLAY 1 - -/* TFTDATALINES */ -#define LCD_INTERFACE_12_BIT 0 -#define LCD_INTERFACE_16_BIT 1 -#define LCD_INTERFACE_18_BIT 2 -#define LCD_INTERFACE_24_BIT 3 - -/* Polarity */ -#define DSS_IVS (1 << 12) -#define DSS_IHS (1 << 13) -#define DSS_IPC (1 << 14) -#define DSS_IEO (1 << 15) -#define DSS_ONOFF (1 << 17) - -/* GFX format */ -#define GFXFORMAT_BITMAP1 (0x0 << 1) -#define GFXFORMAT_BITMAP2 (0x1 << 1) -#define GFXFORMAT_BITMAP4 (0x2 << 1) -#define GFXFORMAT_BITMAP8 (0x3 << 1) -#define GFXFORMAT_RGB12 (0x4 << 1) -#define GFXFORMAT_ARGB16 (0x5 << 1) -#define GFXFORMAT_RGB16 (0x6 << 1) -#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1) -#define GFXFORMAT_RGB24_PACKED (0x9 << 1) -#define GFXFORMAT_ARGB32 (0xC << 1) -#define GFXFORMAT_RGBA32 (0xD << 1) -#define GFXFORMAT_RGBx32 (0xE << 1) - -/* Panel Configuration */ -struct panel_config { - u32 timing_h; - u32 timing_v; - u32 pol_freq; - u32 divisor; - u32 lcd_size; - u32 panel_type; - u32 data_lines; - u32 load_mode; - u32 panel_color; - u32 gfx_format; - void *frame_buffer; -}; - -#define DSS_HBP(bp) (((bp) - 1) << 20) -#define DSS_HFP(fp) (((fp) - 1) << 8) -#define DSS_HSW(sw) ((sw) - 1) -#define DSS_VBP(bp) ((bp) << 20) -#define DSS_VFP(fp) ((fp) << 8) -#define DSS_VSW(sw) ((sw) - 1) - -#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw)) -#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw)) -#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1)) - -/* Generic DSS Functions */ -void omap3_dss_venc_config(const struct venc_regs *venc_cfg, - u32 height, u32 width); -void omap3_dss_panel_config(const struct panel_config *panel_cfg); -void omap3_dss_enable(void); - -#endif /* DSS_H */ diff --git a/arch/arm/include/asm/arch-omap3/ehci.h b/arch/arm/include/asm/arch-omap3/ehci.h deleted file mode 100644 index fa839ef..0000000 --- a/arch/arm/include/asm/arch-omap3/ehci.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Alexander Holler <holler@ahsoftware.de> - * - * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37 - * - * See there for additional Copyrights. - */ -#ifndef _OMAP3_EHCI_H_ -#define _OMAP3_EHCI_H_ - -/* USB/EHCI registers */ -#define OMAP_USBTLL_BASE 0x48062000UL -#define OMAP_UHH_BASE 0x48064000UL -#define OMAP_EHCI_BASE 0x48064800UL - -/* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 - -/* UHH Register Set */ -#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) - -#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_CACTIVITY | \ - OMAP_UHH_SYSCONFIG_SIDLEMODE | \ - OMAP_UHH_SYSCONFIG_ENAWAKEUP | \ - OMAP_UHH_SYSCONFIG_MIDLEMODE) - -#endif /* _OMAP3_EHCI_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/emac_defs.h b/arch/arm/include/asm/arch-omap3/emac_defs.h deleted file mode 100644 index 0f4b934..0000000 --- a/arch/arm/include/asm/arch-omap3/emac_defs.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - * Modifications: - * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. - */ - -#ifndef _AM3517_EMAC_H_ -#define _AM3517_EMAC_H_ - -#define EMAC_BASE_ADDR 0x5C010000 -#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 -#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 -#define EMAC_MDIO_BASE_ADDR 0x5C030000 -#define EMAC_HW_RAM_ADDR 0x01E20000 - -#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ -#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ - -/* SOFTRESET macro definition interferes with emac_regs structure definition */ -#undef SOFTRESET - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int *dv_reg_p; - -#define DAVINCI_EMAC_VERSION2 - -#endif /* _AM3517_EMAC_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h deleted file mode 100644 index bac43b2..0000000 --- a/arch/arm/include/asm/arch-omap3/emif4.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Auther: - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef _EMIF_H_ -#define _EMIF_H_ - -/* - * Configuration values - */ -#define EMIF4_TIM1_T_RP (0x3 << 25) -#define EMIF4_TIM1_T_RCD (0x3 << 21) -#define EMIF4_TIM1_T_WR (0x3 << 17) -#define EMIF4_TIM1_T_RAS (0x8 << 12) -#define EMIF4_TIM1_T_RC (0xA << 6) -#define EMIF4_TIM1_T_RRD (0x2 << 3) -#define EMIF4_TIM1_T_WTR (0x2) - -#define EMIF4_TIM2_T_XP (0x2 << 28) -#define EMIF4_TIM2_T_ODT (0x0 << 25) -#define EMIF4_TIM2_T_XSNR (0x1C << 16) -#define EMIF4_TIM2_T_XSRD (0xC8 << 6) -#define EMIF4_TIM2_T_RTP (0x1 << 3) -#define EMIF4_TIM2_T_CKE (0x2) - -#define EMIF4_TIM3_T_RFC (0x25 << 4) -#define EMIF4_TIM3_T_RAS_MAX (0x7) - -#define EMIF4_PWR_IDLE_MODE (0x2 << 30) -#define EMIF4_PWR_DPD_DIS (0x0 << 10) -#define EMIF4_PWR_DPD_EN (0x1 << 10) -#define EMIF4_PWR_LP_MODE (0x0 << 8) -#define EMIF4_PWR_PM_TIM (0x0) - -#define EMIF4_INITREF_DIS (0x0 << 31) -#define EMIF4_REFRESH_RATE (0x50F) - -#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) -#define EMIF4_CFG_IBANK_POS (0x0 << 27) -#define EMIF4_CFG_DDR_TERM (0x0 << 24) -#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) -#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) -#define EMIF4_CFG_SDR_DRV (0x0 << 18) -#define EMIF4_CFG_NARROW_MD (0x0 << 14) -#define EMIF4_CFG_CL (0x5 << 10) -#define EMIF4_CFG_ROWSIZE (0x0 << 7) -#define EMIF4_CFG_IBANK (0x3 << 4) -#define EMIF4_CFG_EBANK (0x0 << 3) -#define EMIF4_CFG_PGSIZE (0x2) - -/* - * EMIF4 PHY Control 1 register configuration - */ -#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) -#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) -#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) -#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) -#define EMIF4_DDR1_READ_LAT (0x6 << 0) - -#endif /* endif _EMIF_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h deleted file mode 100644 index ee092f9..0000000 --- a/arch/arm/include/asm/arch-omap3/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_OMAP3_H -#define _GPIO_OMAP3_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 192 - -#define OMAP34XX_GPIO1_BASE 0x48310000 -#define OMAP34XX_GPIO2_BASE 0x49050000 -#define OMAP34XX_GPIO3_BASE 0x49052000 -#define OMAP34XX_GPIO4_BASE 0x49054000 -#define OMAP34XX_GPIO5_BASE 0x49056000 -#define OMAP34XX_GPIO6_BASE 0x49058000 - -#endif /* _GPIO_OMAP3_H */ diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h deleted file mode 100644 index b04c012..0000000 --- a/arch/arm/include/asm/arch-omap3/i2c.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - */ -#ifndef _OMAP3_I2C_H_ -#define _OMAP3_I2C_H_ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#endif /* _OMAP3_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h deleted file mode 100644 index 7adc134..0000000 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ /dev/null @@ -1,488 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -#define CS0 0x0 -#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -}; -#endif /* __ASSEMBLY__ */ - -#define EARLY_INIT 1 - -/* - * For a full explanation of these registers and values please see - * the Technical Reference Manual (TRM) for any of the processors in - * this family. - */ - -/* Slower full frequency range default timings for x32 operation*/ -#define SDRC_SHARING 0x00000100 -#define SDRC_MR_0_SDR 0x00000031 - -/* - * SDRC autorefresh control values. This register consists of autorefresh - * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The - * counter is a result of ( tREFI / tCK ) - 50. - */ -#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ -#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ -#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ - -#define DLL_OFFSET 0 -#define DLL_WRITEDDRCLKX2DIS 1 -#define DLL_ENADLL 1 -#define DLL_LOCKDLL 0 -#define DLL_DLLPHASE_72 0 -#define DLL_DLLPHASE_90 1 - -/* rkw - need to find of 90/72 degree recommendation for speed like before */ -#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ - (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) - -/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ -#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ -#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ -#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ -#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ -#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ -#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ -#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ -#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ - -#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ - ACTIM_CTRLA_TRFC(trfc) | \ - ACTIM_CTRLA_TRC(trc) | \ - ACTIM_CTRLA_TRAS(tras) | \ - ACTIM_CTRLA_TRP(trp) | \ - ACTIM_CTRLA_TRCD(trcd) | \ - ACTIM_CTRLA_TRRD(trrd) | \ - ACTIM_CTRLA_TDPL(tdpl) | \ - ACTIM_CTRLA_TDAL(tdal) - -/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ -#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ -#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ -#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ -#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ - -#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ - ACTIM_CTRLB_TWTR(twtr) | \ - ACTIM_CTRLB_TCKE(tcke) | \ - ACTIM_CTRLB_TXP(txp) | \ - ACTIM_CTRLB_TXSR(txsr) - -/* - * Values used in the MCFG register. Only values we use today - * are defined and the rest can be found in the TRM. Unless otherwise - * noted all fields are one bit. - */ -#define V_MCFG_RAMTYPE_DDR (0x1) -#define V_MCFG_DEEPPD_EN (0x1 << 3) -#define V_MCFG_B32NOT16_32 (0x1 << 4) -#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ -#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */ -#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) -#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */ -#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10) -#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */ - -/* Macro to construct MCFG */ -#define MCFG(ramsize, raswidth) \ - V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \ - V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \ - V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \ - V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR - -/* Hynix part of Overo (165MHz optimized) 6.06ns */ -#define HYNIX_TDAL_165 6 -#define HYNIX_TDPL_165 3 -#define HYNIX_TRRD_165 2 -#define HYNIX_TRCD_165 3 -#define HYNIX_TRP_165 3 -#define HYNIX_TRAS_165 7 -#define HYNIX_TRC_165 10 -#define HYNIX_TRFC_165 21 -#define HYNIX_V_ACTIMA_165 \ - ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ - HYNIX_TRAS_165, HYNIX_TRP_165, \ - HYNIX_TRCD_165, HYNIX_TRRD_165, \ - HYNIX_TDPL_165, HYNIX_TDAL_165) - -#define HYNIX_TWTR_165 1 -#define HYNIX_TCKE_165 1 -#define HYNIX_TXP_165 2 -#define HYNIX_XSR_165 24 -#define HYNIX_V_ACTIMB_165 \ - ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ - HYNIX_TXP_165, HYNIX_XSR_165) - -#define HYNIX_RASWIDTH_165 13 -#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) - -/* Hynix part of AM/DM37xEVM (200MHz optimized) */ -#define HYNIX_TDAL_200 6 -#define HYNIX_TDPL_200 3 -#define HYNIX_TRRD_200 2 -#define HYNIX_TRCD_200 4 -#define HYNIX_TRP_200 3 -#define HYNIX_TRAS_200 8 -#define HYNIX_TRC_200 11 -#define HYNIX_TRFC_200 18 -#define HYNIX_V_ACTIMA_200 \ - ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ - HYNIX_TRAS_200, HYNIX_TRP_200, \ - HYNIX_TRCD_200, HYNIX_TRRD_200, \ - HYNIX_TDPL_200, HYNIX_TDAL_200) - -#define HYNIX_TWTR_200 2 -#define HYNIX_TCKE_200 1 -#define HYNIX_TXP_200 1 -#define HYNIX_XSR_200 28 -#define HYNIX_V_ACTIMB_200 \ - ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ - HYNIX_TXP_200, HYNIX_XSR_200) - -#define HYNIX_RASWIDTH_200 14 -#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) - -/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ -#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ - /* 15/6 + 18/6 = 5.5 -> 6 */ -#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ -#define INFINEON_TRRD_165 2 /* 12/6 = 2 */ -#define INFINEON_TRCD_165 3 /* 18/6 = 3 */ -#define INFINEON_TRP_165 3 /* 18/6 = 3 */ -#define INFINEON_TRAS_165 7 /* 42/6 = 7 */ -#define INFINEON_TRC_165 10 /* 60/6 = 10 */ -#define INFINEON_TRFC_165 12 /* 72/6 = 12 */ - -#define INFINEON_V_ACTIMA_165 \ - ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ - INFINEON_TRAS_165, INFINEON_TRP_165, \ - INFINEON_TRCD_165, INFINEON_TRRD_165, \ - INFINEON_TDPL_165, INFINEON_TDAL_165) - -#define INFINEON_TWTR_165 1 -#define INFINEON_TCKE_165 2 -#define INFINEON_TXP_165 2 -#define INFINEON_XSR_165 20 /* 120/6 = 20 */ - -#define INFINEON_V_ACTIMB_165 \ - ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ - INFINEON_TXP_165, INFINEON_XSR_165) - -/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ -#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ - /* 15/6 + 18/6 = 5.5 -> 6 */ -#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ -#define MICRON_TRRD_165 2 /* 12/6 = 2 */ -#define MICRON_TRCD_165 3 /* 18/6 = 3 */ -#define MICRON_TRP_165 3 /* 18/6 = 3 */ -#define MICRON_TRAS_165 7 /* 42/6 = 7 */ -#define MICRON_TRC_165 10 /* 60/6 = 10 */ -#define MICRON_TRFC_165 21 /* 125/6 = 21 */ - -#define MICRON_V_ACTIMA_165 \ - ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ - MICRON_TRAS_165, MICRON_TRP_165, \ - MICRON_TRCD_165, MICRON_TRRD_165, \ - MICRON_TDPL_165, MICRON_TDAL_165) - -#define MICRON_TWTR_165 1 -#define MICRON_TCKE_165 1 -#define MICRON_XSR_165 23 /* 138/6 = 23 */ -#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ - -#define MICRON_V_ACTIMB_165 \ - ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ - MICRON_TXP_165, MICRON_XSR_165) - -#define MICRON_RASWIDTH_165 13 -#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) - -#define MICRON_BL_165 0x2 -#define MICRON_SIL_165 0x0 -#define MICRON_CASL_165 0x3 -#define MICRON_WBST_165 0x0 -#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ - (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ - (MICRON_BL_165)) - -/* Micron part (200MHz optimized) 5 ns */ -#define MICRON_TDAL_200 6 -#define MICRON_TDPL_200 3 -#define MICRON_TRRD_200 2 -#define MICRON_TRCD_200 3 -#define MICRON_TRP_200 3 -#define MICRON_TRAS_200 8 -#define MICRON_TRC_200 11 -#define MICRON_TRFC_200 15 -#define MICRON_V_ACTIMA_200 \ - ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ - MICRON_TRAS_200, MICRON_TRP_200, \ - MICRON_TRCD_200, MICRON_TRRD_200, \ - MICRON_TDPL_200, MICRON_TDAL_200) - -#define MICRON_TWTR_200 2 -#define MICRON_TCKE_200 4 -#define MICRON_TXP_200 2 -#define MICRON_XSR_200 23 -#define MICRON_V_ACTIMB_200 \ - ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ - MICRON_TXP_200, MICRON_XSR_200) - -#define MICRON_RASWIDTH_200 14 -#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) - -/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */ -#define SAMSUNG_TDAL_165 5 -#define SAMSUNG_TDPL_165 2 -#define SAMSUNG_TRRD_165 2 -#define SAMSUNG_TRCD_165 3 -#define SAMSUNG_TRP_165 3 -#define SAMSUNG_TRAS_165 7 -#define SAMSUNG_TRC_165 10 -#define SAMSUNG_TRFC_165 12 - -#define SAMSUNG_V_ACTIMA_165 \ - ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \ - SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \ - SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \ - SAMSUNG_TDPL_165, SAMSUNG_TDAL_165) - -#define SAMSUNG_TWTR_165 1 -#define SAMSUNG_TCKE_165 2 -#define SAMSUNG_XSR_165 20 -#define SAMSUNG_TXP_165 5 - -#define SAMSUNG_V_ACTIMB_165 \ - ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \ - SAMSUNG_TXP_165, SAMSUNG_XSR_165) - -#define SAMSUNG_RASWIDTH_165 14 -#define SAMSUNG_V_MCFG_165(size) \ - V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \ - V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \ - V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR - -/* TODO: find which register these were taken from */ - -#define SAMSUNG_BL_165 0x2 -#define SAMSUNG_SIL_165 0x0 -#define SAMSUNG_CASL_165 0x3 -#define SAMSUNG_WBST_165 0x0 -#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \ - (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \ - (SAMSUNG_BL_165)) - -#define SAMSUNG_SHARING 0x00003700 - -/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ -#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ - /* 15/6 + 18/6 = 5.5 -> 6 */ -#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ -#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ -#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ -#define NUMONYX_TRP_165 3 /* 18/6 = 3 */ -#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ -#define NUMONYX_TRC_165 10 /* 60/6 = 10 */ -#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ - -#define NUMONYX_V_ACTIMA_165 \ - ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ - NUMONYX_TRAS_165, NUMONYX_TRP_165, \ - NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ - NUMONYX_TDPL_165, NUMONYX_TDAL_165) - -#define NUMONYX_TWTR_165 2 -#define NUMONYX_TCKE_165 2 -#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ -#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ - -#define NUMONYX_V_ACTIMB_165 \ - ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ - NUMONYX_TXP_165, NUMONYX_XSR_165) - -#define NUMONYX_RASWIDTH_165 15 -#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) - -/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */ -#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */ - /* 15/5 + 15/5 = 3 + 3 -> 6 */ -#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */ -#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */ -#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */ -#define NUMONYX_TRP_200 3 /* 15/5 = 3 */ -#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */ -#define NUMONYX_TRC_200 11 /* 55/5 = 11 */ -#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */ - -#define NUMONYX_V_ACTIMA_200 \ - ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \ - NUMONYX_TRAS_200, NUMONYX_TRP_200, \ - NUMONYX_TRCD_200, NUMONYX_TRRD_200, \ - NUMONYX_TDPL_200, NUMONYX_TDAL_200) - -#define NUMONYX_TWTR_200 2 -#define NUMONYX_TCKE_200 2 -#define NUMONYX_TXP_200 3 -#define NUMONYX_XSR_200 40 - -#define NUMONYX_V_ACTIMB_200 \ - ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \ - NUMONYX_TXP_200, NUMONYX_XSR_200) - -#define NUMONYX_RASWIDTH_200 15 -#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200) - -/* - * GPMC settings - - * Definitions is as per the following format - * #define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * MNAND - Micron Large page x16 NAND - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the defn - for all CS we are interested - * #define OMAP34XX_GPMC_CSx PART - * #define OMAP34XX_GPMC_CSx_SIZE Size - * #define OMAP34XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define GPMC_BASEADDR_MASK 0x3F - -#define GPMC_CS_ENABLE 0x1 - -#define M_NAND_GPMC_CONFIG1 0x00001800 -#define M_NAND_GPMC_CONFIG2 0x00141400 -#define M_NAND_GPMC_CONFIG3 0x00141400 -#define M_NAND_GPMC_CONFIG4 0x0F010F01 -#define M_NAND_GPMC_CONFIG5 0x010C1414 -#define M_NAND_GPMC_CONFIG6 0x1f0f0A80 -#define M_NAND_GPMC_CONFIG7 0x00000C44 - -#define STNOR_GPMC_CONFIG1 0x3 -#define STNOR_GPMC_CONFIG2 0x00151501 -#define STNOR_GPMC_CONFIG3 0x00060602 -#define STNOR_GPMC_CONFIG4 0x11091109 -#define STNOR_GPMC_CONFIG5 0x01141F1F -#define STNOR_GPMC_CONFIG6 0x000004c4 - -#define SIBNOR_GPMC_CONFIG1 0x1200 -#define SIBNOR_GPMC_CONFIG2 0x001f1f00 -#define SIBNOR_GPMC_CONFIG3 0x00080802 -#define SIBNOR_GPMC_CONFIG4 0x1C091C09 -#define SIBNOR_GPMC_CONFIG5 0x01131F1F -#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -#define MPDB_GPMC_CONFIG1 0x00011000 -#define MPDB_GPMC_CONFIG2 0x001f1f01 -#define MPDB_GPMC_CONFIG3 0x00080803 -#define MPDB_GPMC_CONFIG4 0x1c0b1c0a -#define MPDB_GPMC_CONFIG5 0x041f1F1F -#define MPDB_GPMC_CONFIG6 0x1F0F04C4 - -#define P2_GPMC_CONFIG1 0x0 -#define P2_GPMC_CONFIG2 0x0 -#define P2_GPMC_CONFIG3 0x0 -#define P2_GPMC_CONFIG4 0x0 -#define P2_GPMC_CONFIG5 0x0 -#define P2_GPMC_CONFIG6 0x0 - -#define ONENAND_GPMC_CONFIG1 0x00001200 -#define ONENAND_GPMC_CONFIG2 0x000F0F01 -#define ONENAND_GPMC_CONFIG3 0x00030301 -#define ONENAND_GPMC_CONFIG4 0x0F040F04 -#define ONENAND_GPMC_CONFIG5 0x010F1010 -#define ONENAND_GPMC_CONFIG6 0x1F060000 - -#define NET_GPMC_CONFIG1 0x00001000 -#define NET_GPMC_CONFIG2 0x001e1e01 -#define NET_GPMC_CONFIG3 0x00080300 -#define NET_GPMC_CONFIG4 0x1c091c09 -#define NET_GPMC_CONFIG5 0x04181f1f -#define NET_GPMC_CONFIG6 0x00000FCF -#define NET_GPMC_CONFIG7 0x00000f6c - -/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ -#define NET_LAN9221_GPMC_CONFIG1 0x00001000 -#define NET_LAN9221_GPMC_CONFIG2 0x00060700 -#define NET_LAN9221_GPMC_CONFIG3 0x00020201 -#define NET_LAN9221_GPMC_CONFIG4 0x06000700 -#define NET_LAN9221_GPMC_CONFIG5 0x0006090A -#define NET_LAN9221_GPMC_CONFIG6 0x87030000 -#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c - - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define DBG_MPDB 6 -#define DBG_MPDB_BASE DEBUG_BASE - -#ifndef __ASSEMBLY__ - -/* Function prototypes */ -void mem_init(void); - -u32 is_mem_sdr(void); -u32 mem_ok(u32 cs); - -u32 get_sdr_cs_size(u32); -u32 get_sdr_cs_offset(u32); - -#endif /* __ASSEMBLY__ */ - -#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h deleted file mode 100644 index 39a7cba..0000000 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* T2 Register definitions */ -#define T2_BASE 0x48002000 - -typedef struct t2 { - unsigned char res1[0x274]; /* 0x000 */ - unsigned int devconf0; /* 0x274 */ - unsigned char res2[0x060]; /* 0x278 */ - unsigned int devconf1; /* 0x2D8 */ - unsigned char res3[0x16C]; /* 0x2DC */ - unsigned int ctl_prog_io1; /* 0x448 */ - unsigned char res4[0x0D4]; /* 0x44C */ - unsigned int pbias_lite; /* 0x520 */ -} t2_t; - -#define MMCSDIO1ADPCLKISEL (1 << 24) -#define MMCSDIO2ADPCLKISEL (1 << 6) - -#define EN_MMC1 (1 << 24) -#define EN_MMC2 (1 << 25) -#define EN_MMC3 (1 << 30) - -#define PBIASLITEPWRDNZ0 (1 << 1) -#define PBIASSPEEDCTRL0 (1 << 2) -#define PBIASLITEPWRDNZ1 (1 << 9) -#define PBIASLITEVMODE1 (1 << 8) -#define PBIASLITEVMODE0 (1 << 0) - -#define CTLPROGIO1SPEEDCTRL (1 << 20) - -/* - * OMAP HSMMC register definitions - */ -#define OMAP_HSMMC1_BASE 0x4809C000 -#define OMAP_HSMMC2_BASE 0x480B4000 -#define OMAP_HSMMC3_BASE 0x480AD000 - - -#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap3/musb.h b/arch/arm/include/asm/arch-omap3/musb.h deleted file mode 100644 index cb3f5d8..0000000 --- a/arch/arm/include/asm/arch-omap3/musb.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Ilya Yanok, <ilya.yanok@gmail.com> - */ - -#ifndef __ASM_ARCH_OMAP3_MUSB_H -#define __ASM_ARCH_OMAP3_MUSB_H -void am35x_musb_reset(struct udevice *dev); -void am35x_musb_phy_power(struct udevice *dev, u8 on); -void am35x_musb_clear_irq(struct udevice *dev); -#endif diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h deleted file mode 100644 index 2ed520d..0000000 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ /dev/null @@ -1,497 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - */ -#ifndef _MUX_H_ -#define _MUX_H_ - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * SB_LOW - Standby mode configuration: Output low-level - * SB_HI - Standby mode configuration: Output high-level - * SB_HIZ - Standby mode configuration: Output hi-impedence - * SB_PD - Standby mode pull-down enabled - * SB_PU - Standby mode pull-up enabled - * WKEN - Wakeup input enabled - * M0 - Mode 0 - */ - -#define IEN (1 << 8) - -#define IDIS (0 << 8) -#define PTU (1 << 4) -#define PTD (0 << 4) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define SB_LOW (1 << 9) -#define SB_HI (5 << 9) -#define SB_HIZ (2 << 9) -#define SB_PD (1 << 12) -#define SB_PU (3 << 12) -#define WKEN (1 << 14) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -/* - * To get the actual address the offset has to be added - * to OMAP34XX_CTRL_BASE - */ - -/*SDRC*/ -#define CONTROL_PADCONF_SDRC_D0 0x0030 -#define CONTROL_PADCONF_SDRC_D1 0x0032 -#define CONTROL_PADCONF_SDRC_D2 0x0034 -#define CONTROL_PADCONF_SDRC_D3 0x0036 -#define CONTROL_PADCONF_SDRC_D4 0x0038 -#define CONTROL_PADCONF_SDRC_D5 0x003A -#define CONTROL_PADCONF_SDRC_D6 0x003C -#define CONTROL_PADCONF_SDRC_D7 0x003E -#define CONTROL_PADCONF_SDRC_D8 0x0040 -#define CONTROL_PADCONF_SDRC_D9 0x0042 -#define CONTROL_PADCONF_SDRC_D10 0x0044 -#define CONTROL_PADCONF_SDRC_D11 0x0046 -#define CONTROL_PADCONF_SDRC_D12 0x0048 -#define CONTROL_PADCONF_SDRC_D13 0x004A -#define CONTROL_PADCONF_SDRC_D14 0x004C -#define CONTROL_PADCONF_SDRC_D15 0x004E -#define CONTROL_PADCONF_SDRC_D16 0x0050 -#define CONTROL_PADCONF_SDRC_D17 0x0052 -#define CONTROL_PADCONF_SDRC_D18 0x0054 -#define CONTROL_PADCONF_SDRC_D19 0x0056 -#define CONTROL_PADCONF_SDRC_D20 0x0058 -#define CONTROL_PADCONF_SDRC_D21 0x005A -#define CONTROL_PADCONF_SDRC_D22 0x005C -#define CONTROL_PADCONF_SDRC_D23 0x005E -#define CONTROL_PADCONF_SDRC_D24 0x0060 -#define CONTROL_PADCONF_SDRC_D25 0x0062 -#define CONTROL_PADCONF_SDRC_D26 0x0064 -#define CONTROL_PADCONF_SDRC_D27 0x0066 -#define CONTROL_PADCONF_SDRC_D28 0x0068 -#define CONTROL_PADCONF_SDRC_D29 0x006A -#define CONTROL_PADCONF_SDRC_D30 0x006C -#define CONTROL_PADCONF_SDRC_D31 0x006E -#define CONTROL_PADCONF_SDRC_CLK 0x0070 -#define CONTROL_PADCONF_SDRC_DQS0 0x0072 -#define CONTROL_PADCONF_SDRC_DQS1 0x0074 -#define CONTROL_PADCONF_SDRC_DQS2 0x0076 -#define CONTROL_PADCONF_SDRC_DQS3 0x0078 -#define CONTROL_PADCONF_SDRC_BA0 0x05A0 -#define CONTROL_PADCONF_SDRC_BA1 0x05A2 -#define CONTROL_PADCONF_SDRC_A0 0x05A4 -#define CONTROL_PADCONF_SDRC_A1 0x05A6 -#define CONTROL_PADCONF_SDRC_A2 0x05A8 -#define CONTROL_PADCONF_SDRC_A3 0x05AA -#define CONTROL_PADCONF_SDRC_A4 0x05AC -#define CONTROL_PADCONF_SDRC_A5 0x05AE -#define CONTROL_PADCONF_SDRC_A6 0x05B0 -#define CONTROL_PADCONF_SDRC_A7 0x05B2 -#define CONTROL_PADCONF_SDRC_A8 0x05B4 -#define CONTROL_PADCONF_SDRC_A9 0x05B6 -#define CONTROL_PADCONF_SDRC_A10 0x05B8 -#define CONTROL_PADCONF_SDRC_A11 0x05BA -#define CONTROL_PADCONF_SDRC_A12 0x05BC -#define CONTROL_PADCONF_SDRC_A13 0x05BE -#define CONTROL_PADCONF_SDRC_A14 0x05C0 -#define CONTROL_PADCONF_SDRC_NCS0 0x05C2 -#define CONTROL_PADCONF_SDRC_NCS1 0x05C4 -#define CONTROL_PADCONF_SDRC_NCLK 0x05C6 -#define CONTROL_PADCONF_SDRC_NRAS 0x05C8 -#define CONTROL_PADCONF_SDRC_NCAS 0x05CA -#define CONTROL_PADCONF_SDRC_NWE 0x05CC -#define CONTROL_PADCONF_SDRC_DM0 0x05CE -#define CONTROL_PADCONF_SDRC_DM1 0x05D0 -#define CONTROL_PADCONF_SDRC_DM2 0x05D2 -#define CONTROL_PADCONF_SDRC_DM3 0x05D4 -/*GPMC*/ -#define CONTROL_PADCONF_GPMC_A1 0x007A -#define CONTROL_PADCONF_GPMC_A2 0x007C -#define CONTROL_PADCONF_GPMC_A3 0x007E -#define CONTROL_PADCONF_GPMC_A4 0x0080 -#define CONTROL_PADCONF_GPMC_A5 0x0082 -#define CONTROL_PADCONF_GPMC_A6 0x0084 -#define CONTROL_PADCONF_GPMC_A7 0x0086 -#define CONTROL_PADCONF_GPMC_A8 0x0088 -#define CONTROL_PADCONF_GPMC_A9 0x008A -#define CONTROL_PADCONF_GPMC_A10 0x008C -#define CONTROL_PADCONF_GPMC_A11 0x0264 -#define CONTROL_PADCONF_GPMC_D0 0x008E -#define CONTROL_PADCONF_GPMC_D1 0x0090 -#define CONTROL_PADCONF_GPMC_D2 0x0092 -#define CONTROL_PADCONF_GPMC_D3 0x0094 -#define CONTROL_PADCONF_GPMC_D4 0x0096 -#define CONTROL_PADCONF_GPMC_D5 0x0098 -#define CONTROL_PADCONF_GPMC_D6 0x009A -#define CONTROL_PADCONF_GPMC_D7 0x009C -#define CONTROL_PADCONF_GPMC_D8 0x009E -#define CONTROL_PADCONF_GPMC_D9 0x00A0 -#define CONTROL_PADCONF_GPMC_D10 0x00A2 -#define CONTROL_PADCONF_GPMC_D11 0x00A4 -#define CONTROL_PADCONF_GPMC_D12 0x00A6 -#define CONTROL_PADCONF_GPMC_D13 0x00A8 -#define CONTROL_PADCONF_GPMC_D14 0x00AA -#define CONTROL_PADCONF_GPMC_D15 0x00AC -#define CONTROL_PADCONF_GPMC_NCS0 0x00AE -#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 -#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 -#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 -#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 -#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 -#define CONTROL_PADCONF_GPMC_NCS6 0x00BA -#define CONTROL_PADCONF_GPMC_NCS7 0x00BC -#define CONTROL_PADCONF_GPMC_CLK 0x00BE -#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 -#define CONTROL_PADCONF_GPMC_NOE 0x00C2 -#define CONTROL_PADCONF_GPMC_NWE 0x00C4 -#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 -#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 -#define CONTROL_PADCONF_GPMC_NWP 0x00CA -#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC -#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE -#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 -#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 -/*DSS*/ -#define CONTROL_PADCONF_DSS_PCLK 0x00D4 -#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 -#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 -#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA -#define CONTROL_PADCONF_DSS_DATA0 0x00DC -#define CONTROL_PADCONF_DSS_DATA1 0x00DE -#define CONTROL_PADCONF_DSS_DATA2 0x00E0 -#define CONTROL_PADCONF_DSS_DATA3 0x00E2 -#define CONTROL_PADCONF_DSS_DATA4 0x00E4 -#define CONTROL_PADCONF_DSS_DATA5 0x00E6 -#define CONTROL_PADCONF_DSS_DATA6 0x00E8 -#define CONTROL_PADCONF_DSS_DATA7 0x00EA -#define CONTROL_PADCONF_DSS_DATA8 0x00EC -#define CONTROL_PADCONF_DSS_DATA9 0x00EE -#define CONTROL_PADCONF_DSS_DATA10 0x00F0 -#define CONTROL_PADCONF_DSS_DATA11 0x00F2 -#define CONTROL_PADCONF_DSS_DATA12 0x00F4 -#define CONTROL_PADCONF_DSS_DATA13 0x00F6 -#define CONTROL_PADCONF_DSS_DATA14 0x00F8 -#define CONTROL_PADCONF_DSS_DATA15 0x00FA -#define CONTROL_PADCONF_DSS_DATA16 0x00FC -#define CONTROL_PADCONF_DSS_DATA17 0x00FE -#define CONTROL_PADCONF_DSS_DATA18 0x0100 -#define CONTROL_PADCONF_DSS_DATA19 0x0102 -#define CONTROL_PADCONF_DSS_DATA20 0x0104 -#define CONTROL_PADCONF_DSS_DATA21 0x0106 -#define CONTROL_PADCONF_DSS_DATA22 0x0108 -#define CONTROL_PADCONF_DSS_DATA23 0x010A -/*CAMERA*/ -#define CONTROL_PADCONF_CAM_HS 0x010C -#define CONTROL_PADCONF_CAM_VS 0x010E -#define CONTROL_PADCONF_CAM_XCLKA 0x0110 -#define CONTROL_PADCONF_CAM_PCLK 0x0112 -#define CONTROL_PADCONF_CAM_FLD 0x0114 -#define CONTROL_PADCONF_CAM_D0 0x0116 -#define CONTROL_PADCONF_CAM_D1 0x0118 -#define CONTROL_PADCONF_CAM_D2 0x011A -#define CONTROL_PADCONF_CAM_D3 0x011C -#define CONTROL_PADCONF_CAM_D4 0x011E -#define CONTROL_PADCONF_CAM_D5 0x0120 -#define CONTROL_PADCONF_CAM_D6 0x0122 -#define CONTROL_PADCONF_CAM_D7 0x0124 -#define CONTROL_PADCONF_CAM_D8 0x0126 -#define CONTROL_PADCONF_CAM_D9 0x0128 -#define CONTROL_PADCONF_CAM_D10 0x012A -#define CONTROL_PADCONF_CAM_D11 0x012C -#define CONTROL_PADCONF_CAM_XCLKB 0x012E -#define CONTROL_PADCONF_CAM_WEN 0x0130 -#define CONTROL_PADCONF_CAM_STROBE 0x0132 -#define CONTROL_PADCONF_CSI2_DX0 0x0134 -#define CONTROL_PADCONF_CSI2_DY0 0x0136 -#define CONTROL_PADCONF_CSI2_DX1 0x0138 -#define CONTROL_PADCONF_CSI2_DY1 0x013A -/*Audio Interface */ -#define CONTROL_PADCONF_MCBSP2_FSX 0x013C -#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E -#define CONTROL_PADCONF_MCBSP2_DR 0x0140 -#define CONTROL_PADCONF_MCBSP2_DX 0x0142 -#define CONTROL_PADCONF_MMC1_CLK 0x0144 -#define CONTROL_PADCONF_MMC1_CMD 0x0146 -#define CONTROL_PADCONF_MMC1_DAT0 0x0148 -#define CONTROL_PADCONF_MMC1_DAT1 0x014A -#define CONTROL_PADCONF_MMC1_DAT2 0x014C -#define CONTROL_PADCONF_MMC1_DAT3 0x014E -#define CONTROL_PADCONF_MMC1_DAT4 0x0150 -#define CONTROL_PADCONF_MMC1_DAT5 0x0152 -#define CONTROL_PADCONF_MMC1_DAT6 0x0154 -#define CONTROL_PADCONF_MMC1_DAT7 0x0156 -/*Wireless LAN */ -#define CONTROL_PADCONF_MMC2_CLK 0x0158 -#define CONTROL_PADCONF_MMC2_CMD 0x015A -#define CONTROL_PADCONF_MMC2_DAT0 0x015C -#define CONTROL_PADCONF_MMC2_DAT1 0x015E -#define CONTROL_PADCONF_MMC2_DAT2 0x0160 -#define CONTROL_PADCONF_MMC2_DAT3 0x0162 -#define CONTROL_PADCONF_MMC2_DAT4 0x0164 -#define CONTROL_PADCONF_MMC2_DAT5 0x0166 -#define CONTROL_PADCONF_MMC2_DAT6 0x0168 -#define CONTROL_PADCONF_MMC2_DAT7 0x016A -/*Bluetooth*/ -#define CONTROL_PADCONF_MCBSP3_DX 0x016C -#define CONTROL_PADCONF_MCBSP3_DR 0x016E -#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 -#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 -#define CONTROL_PADCONF_UART2_CTS 0x0174 -#define CONTROL_PADCONF_UART2_RTS 0x0176 -#define CONTROL_PADCONF_UART2_TX 0x0178 -#define CONTROL_PADCONF_UART2_RX 0x017A -/*Modem Interface */ -#define CONTROL_PADCONF_UART1_TX 0x017C -#define CONTROL_PADCONF_UART1_RTS 0x017E -#define CONTROL_PADCONF_UART1_CTS 0x0180 -#define CONTROL_PADCONF_UART1_RX 0x0182 -#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 -#define CONTROL_PADCONF_MCBSP4_DR 0x0186 -#define CONTROL_PADCONF_MCBSP4_DX 0x0188 -#define CONTROL_PADCONF_MCBSP4_FSX 0x018A -#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C -#define CONTROL_PADCONF_MCBSP1_FSR 0x018E -#define CONTROL_PADCONF_MCBSP1_DX 0x0190 -#define CONTROL_PADCONF_MCBSP1_DR 0x0192 -#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 -#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 -#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 -/*Serial Interface*/ -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A -#define CONTROL_PADCONF_UART3_RTS_SD 0x019C -#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E -#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 -#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 -#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 -#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 -#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 -#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA -#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC -#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE -#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 -#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 -#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 -#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 -#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 -#define CONTROL_PADCONF_I2C1_SCL 0x01BA -#define CONTROL_PADCONF_I2C1_SDA 0x01BC -#define CONTROL_PADCONF_I2C2_SCL 0x01BE -#define CONTROL_PADCONF_I2C2_SDA 0x01C0 -#define CONTROL_PADCONF_I2C3_SCL 0x01C2 -#define CONTROL_PADCONF_I2C3_SDA 0x01C4 -#define CONTROL_PADCONF_I2C4_SCL 0x0A00 -#define CONTROL_PADCONF_I2C4_SDA 0x0A02 -#define CONTROL_PADCONF_HDQ_SIO 0x01C6 -#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 -#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA -#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC -#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE -#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 -#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 -#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 -#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 -#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 -#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA -#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC -#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE -/*Control and debug */ -#define CONTROL_PADCONF_SYS_32K 0x0A04 -#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 -#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A -#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C -#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E -#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 -#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 -#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 -#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 -#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 -#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A -#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C -#define CONTROL_PADCONF_JTAG_TCK 0x0A1E -#define CONTROL_PADCONF_JTAG_TMS 0x0A20 -#define CONTROL_PADCONF_JTAG_TDI 0x0A22 -#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 -#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 -#define CONTROL_PADCONF_ETK_CLK 0x0A28 -#define CONTROL_PADCONF_ETK_CTL 0x0A2A -#define CONTROL_PADCONF_ETK_D0 0x0A2C -#define CONTROL_PADCONF_ETK_D1 0x0A2E -#define CONTROL_PADCONF_ETK_D2 0x0A30 -#define CONTROL_PADCONF_ETK_D3 0x0A32 -#define CONTROL_PADCONF_ETK_D4 0x0A34 -#define CONTROL_PADCONF_ETK_D5 0x0A36 -#define CONTROL_PADCONF_ETK_D6 0x0A38 -#define CONTROL_PADCONF_ETK_D7 0x0A3A -#define CONTROL_PADCONF_ETK_D8 0x0A3C -#define CONTROL_PADCONF_ETK_D9 0x0A3E -#define CONTROL_PADCONF_ETK_D10 0x0A40 -#define CONTROL_PADCONF_ETK_D11 0x0A42 -#define CONTROL_PADCONF_ETK_D12 0x0A44 -#define CONTROL_PADCONF_ETK_D13 0x0A46 -#define CONTROL_PADCONF_ETK_D14 0x0A48 -#define CONTROL_PADCONF_ETK_D15 0x0A4A -#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 -#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA -#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC -#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE -#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 -#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 -#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 -#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 -#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 -#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA -#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC -#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE -#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 -#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 -#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 -#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 -#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 -#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA -#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E -#define CONTROL_PADCONF_JTAG_TDO 0x0A50 -/*Die to Die */ -#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 -#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 -#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 -#define CONTROL_PADCONF_D2D_MCAD3 0x01EA -#define CONTROL_PADCONF_D2D_MCAD4 0x01EC -#define CONTROL_PADCONF_D2D_MCAD5 0x01EE -#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 -#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 -#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 -#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 -#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 -#define CONTROL_PADCONF_D2D_MCAD11 0x01FA -#define CONTROL_PADCONF_D2D_MCAD12 0x01FC -#define CONTROL_PADCONF_D2D_MCAD13 0x01FE -#define CONTROL_PADCONF_D2D_MCAD14 0x0200 -#define CONTROL_PADCONF_D2D_MCAD15 0x0202 -#define CONTROL_PADCONF_D2D_MCAD16 0x0204 -#define CONTROL_PADCONF_D2D_MCAD17 0x0206 -#define CONTROL_PADCONF_D2D_MCAD18 0x0208 -#define CONTROL_PADCONF_D2D_MCAD19 0x020A -#define CONTROL_PADCONF_D2D_MCAD20 0x020C -#define CONTROL_PADCONF_D2D_MCAD21 0x020E -#define CONTROL_PADCONF_D2D_MCAD22 0x0210 -#define CONTROL_PADCONF_D2D_MCAD23 0x0212 -#define CONTROL_PADCONF_D2D_MCAD24 0x0214 -#define CONTROL_PADCONF_D2D_MCAD25 0x0216 -#define CONTROL_PADCONF_D2D_MCAD26 0x0218 -#define CONTROL_PADCONF_D2D_MCAD27 0x021A -#define CONTROL_PADCONF_D2D_MCAD28 0x021C -#define CONTROL_PADCONF_D2D_MCAD29 0x021E -#define CONTROL_PADCONF_D2D_MCAD30 0x0220 -#define CONTROL_PADCONF_D2D_MCAD31 0x0222 -#define CONTROL_PADCONF_D2D_MCAD32 0x0224 -#define CONTROL_PADCONF_D2D_MCAD33 0x0226 -#define CONTROL_PADCONF_D2D_MCAD34 0x0228 -#define CONTROL_PADCONF_D2D_MCAD35 0x022A -#define CONTROL_PADCONF_D2D_MCAD36 0x022C -#define CONTROL_PADCONF_D2D_CLK26MI 0x022E -#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 -#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 -#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 -#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 -#define CONTROL_PADCONF_D2D_SPINT 0x0238 -#define CONTROL_PADCONF_D2D_FRINT 0x023A -#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C -#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E -#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 -#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 -#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 -#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 -#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 -#define CONTROL_PADCONF_D2D_N3GTMS 0x024A -#define CONTROL_PADCONF_D2D_N3GTCK 0x024C -#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E -#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 -#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C -#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 -#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 -#define CONTROL_PADCONF_D2D_MWRITE 0x0256 -#define CONTROL_PADCONF_D2D_SWRITE 0x0258 -#define CONTROL_PADCONF_D2D_MREAD 0x025A -#define CONTROL_PADCONF_D2D_SREAD 0x025C -#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E -#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 -#define CONTROL_PADCONF_SDRC_CKE0 0x0262 -#define CONTROL_PADCONF_SDRC_CKE1 0x0264 - -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 - -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 - -/* AM/DM37xx specific */ -#define CONTROL_PADCONF_GPIO112 0x0134 -#define CONTROL_PADCONF_GPIO113 0x0136 -#define CONTROL_PADCONF_GPIO114 0x0138 -#define CONTROL_PADCONF_GPIO115 0x013A -#define CONTROL_PADCONF_GPIO127 0x0A54 -#define CONTROL_PADCONF_GPIO126 0x0A56 -#define CONTROL_PADCONF_GPIO128 0x0A58 -#define CONTROL_PADCONF_GPIO129 0x0A5A - -/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration - * of the extended drain cells */ -#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) -#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) - -#define MUX_VAL(OFFSET, VALUE)\ - writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) - -#endif diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h deleted file mode 100644 index 19155a2..0000000 --- a/arch/arm/include/asm/arch-omap3/omap.h +++ /dev/null @@ -1,284 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - */ - -#ifndef _OMAP3_H_ -#define _OMAP3_H_ - -#include <linux/sizes.h> - -/* Stuff on L3 Interconnect */ -#define SMX_APE_BASE 0x68000000 - -/* GPMC */ -#define OMAP34XX_GPMC_BASE 0x6E000000 - -/* SMS */ -#define OMAP34XX_SMS_BASE 0x6C000000 - -/* SDRC */ -#define OMAP34XX_SDRC_BASE 0x6D000000 - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 -#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 -#define OMAP34XX_ID_L4_IO_BASE 0x4830A200 -#define OMAP34XX_L4_PER 0x49000000 -#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE - -/* DMA4/SDMA */ -#define OMAP34XX_DMA4_BASE 0x48056000 - -/* CONTROL */ -#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) - -#ifndef __ASSEMBLY__ -/* Signal Integrity Parameter Control Registers */ -struct control_prog_io { - unsigned char res[0x408]; - unsigned int io2; /* 0x408 */ - unsigned char res2[0x38]; - unsigned int io0; /* 0x444 */ - unsigned int io1; /* 0x448 */ -}; -#endif /* __ASSEMBLY__ */ - -/* Bit definition for CONTROL_PROG_IO1 */ -#define PRG_I2C2_PULLUPRESX 0x00000001 - -/* Scratchpad memory */ -#define OMAP34XX_SCRATCHPAD (OMAP34XX_CTRL_BASE + 0x910) - -/* UART */ -#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) -#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) -#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) -#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) - -/* General Purpose Timers */ -#define OMAP34XX_GPT1 0x48318000 -#define OMAP34XX_GPT2 0x49032000 -#define OMAP34XX_GPT3 0x49034000 -#define OMAP34XX_GPT4 0x49036000 -#define OMAP34XX_GPT5 0x49038000 -#define OMAP34XX_GPT6 0x4903A000 -#define OMAP34XX_GPT7 0x4903C000 -#define OMAP34XX_GPT8 0x4903E000 -#define OMAP34XX_GPT9 0x49040000 -#define OMAP34XX_GPT10 0x48086000 -#define OMAP34XX_GPT11 0x48088000 -#define OMAP34XX_GPT12 0x48304000 - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x4830C000 -#define WD2_BASE 0x48314000 -#define WD3_BASE 0x49030000 - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE 0x48320000 - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#define DEVICE_TYPE_SHIFT 0x8 -#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) - -#endif /* __ASSEMBLY__ */ - -#ifndef __ASSEMBLY__ -struct gpio { - unsigned char res1[0x34]; - unsigned int oe; /* 0x34 */ - unsigned int datain; /* 0x38 */ - unsigned char res2[0x54]; - unsigned int cleardataout; /* 0x90 */ - unsigned int setdataout; /* 0x94 */ -}; -#endif /* __ASSEMBLY__ */ - -#define GPIO0 (0x1 << 0) -#define GPIO1 (0x1 << 1) -#define GPIO2 (0x1 << 2) -#define GPIO3 (0x1 << 3) -#define GPIO4 (0x1 << 4) -#define GPIO5 (0x1 << 5) -#define GPIO6 (0x1 << 6) -#define GPIO7 (0x1 << 7) -#define GPIO8 (0x1 << 8) -#define GPIO9 (0x1 << 9) -#define GPIO10 (0x1 << 10) -#define GPIO11 (0x1 << 11) -#define GPIO12 (0x1 << 12) -#define GPIO13 (0x1 << 13) -#define GPIO14 (0x1 << 14) -#define GPIO15 (0x1 << 15) -#define GPIO16 (0x1 << 16) -#define GPIO17 (0x1 << 17) -#define GPIO18 (0x1 << 18) -#define GPIO19 (0x1 << 19) -#define GPIO20 (0x1 << 20) -#define GPIO21 (0x1 << 21) -#define GPIO22 (0x1 << 22) -#define GPIO23 (0x1 << 23) -#define GPIO24 (0x1 << 24) -#define GPIO25 (0x1 << 25) -#define GPIO26 (0x1 << 26) -#define GPIO27 (0x1 << 27) -#define GPIO28 (0x1 << 28) -#define GPIO29 (0x1 << 29) -#define GPIO30 (0x1 << 30) -#define GPIO31 (0x1 << 31) - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ - SRAM_OFFSET2) -#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) - -#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */ -#define NON_SECURE_SRAM_END 0x40210000 -#define NON_SECURE_SRAM_IMG_END 0x4020F000 -#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -/* scratch area - accessible on both EMU and GP */ -#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START - -#define DEBUG_LED1 149 /* gpio */ -#define DEBUG_LED2 150 /* gpio */ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module */ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -/* - * 343x real hardware: - * ES1 = rev 0 - * - * ES2 onwards, the value maps to contents of IDCODE register [31:28]. - * - * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. - */ -#define CPU_3XX_ES10 0 -#define CPU_3XX_ES20 1 -#define CPU_3XX_ES21 2 -#define CPU_3XX_ES30 3 -#define CPU_3XX_ES31 4 -#define CPU_3XX_ES312 7 -#define CPU_3XX_MAX_REV 8 - -/* - * 37xx real hardware: - * ES1.0 onwards, the value maps to contents of IDCODE register [31:28]. - */ - -#define CPU_37XX_ES10 0 -#define CPU_37XX_ES11 1 -#define CPU_37XX_ES12 2 -#define CPU_37XX_MAX_REV 3 - -#define CPU_3XX_ID_SHIFT 28 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -/* - * Hawkeye values - */ -#define HAWKEYE_OMAP34XX 0xb7ae -#define HAWKEYE_AM35XX 0xb868 -#define HAWKEYE_OMAP36XX 0xb891 - -#define HAWKEYE_SHIFT 12 - -/* - * Define CPU families - */ -#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ -#define CPU_AM35XX 0x3500 /* AM35xx devices */ -#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ - -/* - * Control status register values corresponding to cpu variants - */ -#define OMAP3503 0x5c00 -#define OMAP3515 0x1c00 -#define OMAP3525 0x4c00 -#define OMAP3530 0x0c00 - -#define AM3505 0x5c00 -#define AM3517 0x1c00 - -#define OMAP3730 0x0c00 -#define OMAP3725 0x4c00 -#define AM3715 0x1c00 -#define AM3703 0x5c00 - -#define OMAP3730_1GHZ 0x0e00 -#define OMAP3725_1GHZ 0x4e00 -#define AM3715_1GHZ 0x1e00 -#define AM3703_1GHZ 0x5e00 - -/* - * ROM code API related flags - */ -#define OMAP3_GP_ROMCODE_API_L2_INVAL 1 -#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR 2 -#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 - -/* - * EMU device PPA HAL related flags - */ -#define OMAP3_EMU_HAL_API_L2_INVAL 40 -#define OMAP3_EMU_HAL_API_WRITE_ACR 42 - -#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4 - -/* ABB settings */ -#define OMAP_ABB_SETTLING_TIME 30 -#define OMAP_ABB_CLOCK_CYCLES 8 - -/* ABB tranxdone mask */ -#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26) - -#define OMAP_REBOOT_REASON_OFFSET 0x04 - -/* Boot parameters */ -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - unsigned int boot_message; - unsigned char boot_device; - unsigned char reserved; - unsigned char reset_reason; - unsigned char ch_flags; - unsigned int boot_device_descriptor; -}; - -int omap_reboot_mode(char *mode, unsigned int length); -int omap_reboot_mode_clear(void); -int omap_reboot_mode_store(char *mode); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h deleted file mode 100644 index 7b3c6c7..0000000 --- a/arch/arm/include/asm/arch-omap3/omap3-regs.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it> - */ - -#ifndef _OMAP3_REGS_H -#define _OMAP3_REGS_H - -/* - * Register definitions for OMAP3 processors. - */ - -/* - * GPMC_CONFIG1 - GPMC_CONFIG7 - */ - -/* Values for GPMC_CONFIG1 - signal control parameters */ -#define WRAPBURST (1 << 31) -#define READMULTIPLE (1 << 30) -#define READTYPE (1 << 29) -#define WRITEMULTIPLE (1 << 28) -#define WRITETYPE (1 << 27) -#define CLKACTIVATIONTIME(x) (((x) & 3) << 25) -#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) -#define WAITREADMONITORING (1 << 22) -#define WAITWRITEMONITORING (1 << 21) -#define WAITMONITORINGTIME(x) (((x) & 3) << 18) -#define WAITPINSELECT(x) (((x) & 3) << 16) -#define DEVICESIZE(x) (((x) & 3) << 12) -#define DEVICESIZE_8BIT DEVICESIZE(0) -#define DEVICESIZE_16BIT DEVICESIZE(1) -#define DEVICETYPE(x) (((x) & 3) << 10) -#define DEVICETYPE_NOR DEVICETYPE(0) -#define DEVICETYPE_NAND DEVICETYPE(2) -#define MUXADDDATA (1 << 9) -#define TIMEPARAGRANULARITY (1 << 4) -#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) - -/* Values for GPMC_CONFIG2 - CS timing */ -#define CSWROFFTIME(x) (((x) & 0x1f) << 16) -#define CSRDOFFTIME(x) (((x) & 0x1f) << 8) -#define CSEXTRADELAY (1 << 7) -#define CSONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG3 - nADV timing */ -#define ADVWROFFTIME(x) (((x) & 0x1f) << 16) -#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) -#define ADVEXTRADELAY (1 << 7) -#define ADVONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG4 - nWE and nOE timing */ -#define WEOFFTIME(x) (((x) & 0x1f) << 24) -#define WEEXTRADELAY (1 << 23) -#define WEONTIME(x) (((x) & 0xf) << 16) -#define OEOFFTIME(x) (((x) & 0x1f) << 8) -#define OEEXTRADELAY (1 << 7) -#define OEONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ -#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) -#define RDACCESSTIME(x) (((x) & 0x1f) << 16) -#define WRCYCLETIME(x) (((x) & 0x1f) << 8) -#define RDCYCLETIME(x) (((x) & 0x1f) << 0) - -/* Values for GPMC_CONFIG6 - misc timings */ -#define WRACCESSTIME(x) (((x) & 0x1f) << 24) -#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) -#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) -#define CYCLE2CYCLESAMECSEN (1 << 7) -#define CYCLE2CYCLEDIFFCSEN (1 << 6) -#define BUSTURNAROUND(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG7 - CS address mapping configuration */ -#define MASKADDRESS(x) (((x) & 0xf) << 8) -#define CSVALID (1 << 6) -#define BASEADDRESS(x) (((x) & 0x3f) << 0) - -#endif /* _OMAP3_REGS_H */ diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h deleted file mode 100644 index 86b1f46..0000000 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0x00 -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_NAND 0x02 -#define BOOT_DEVICE_ONENAND 0x03 -#define BOOT_DEVICE_MMC2 0x05 -#define BOOT_DEVICE_MMC1 0x06 -#define BOOT_DEVICE_XIPWAIT 0x07 -#define BOOT_DEVICE_MMC2_2 0x08 -#define BOOT_DEVICE_UART 0x10 -#define BOOT_DEVICE_USB 0x11 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h deleted file mode 100644 index 32ac033..0000000 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ -#include <linux/mtd/omap_gpmc.h> -#include <asm/omap_common.h> - -typedef struct { - u32 mtype; - char *board_string; - char *nand_string; -} omap3_sysinfo; - -struct emu_hal_params { - u32 num_params; - u32 param1; -}; - -/* Board SDRC timing values */ -struct board_sdrc_timings { - u32 sharing; - u32 mcfg; - u32 ctrla; - u32 ctrlb; - u32 rfr_ctrl; - u32 mr; -}; - -void prcm_init(void); -void per_clocks_enable(void); -void ehci_clocks_enable(void); - -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32, u32); - -void get_board_mem_timings(struct board_sdrc_timings *timings); -int identify_nand_chip(int *mfr, int *id); -void emif4_init(void); -void gpmc_init(void); -void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, - u32 base, u32 size); -void set_gpmc_cs0(int flash_type); - -void watchdog_init(void); -void set_muxconf_regs(void); - -u32 get_cpu_family(void); -u32 get_cpu_rev(void); -u32 get_sku_id(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 is_running_in_sdram(void); -u32 is_running_in_sram(void); -u32 is_running_in_flash(void); -u32 get_device_type(void); -void secureworld_exit(void); -void try_unlock_memory(void); -u32 get_boot_type(void); -void invalidate_dcache(u32); -u32 wait_on_value(u32, u32, void *, u32); -void cancel_out(u32 *num, u32 *den, u32 den_limit); -void sdelay(unsigned long); -void make_cs1_contiguous(void); -int omap_nand_switch_ecc(uint32_t, uint32_t); -void power_init_r(void); -void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); -void omap3_set_aux_cr_secure(u32 acr); -u32 warm_reset(void); - -void save_omap_boot_params(void); -#endif diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h deleted file mode 100644 index 037045c..0000000 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ /dev/null @@ -1,252 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - */ -#ifndef _CLOCKS_OMAP4_H_ -#define _CLOCKS_OMAP4_H_ -#include <common.h> -#include <asm/omap_common.h> - -/* - * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per - * loop, allow for a minimum of 2 ms wait (in reality the wait will be - * much more than that) - */ -#define LDELAY 1000000 - -/* CM_DLL_CTRL */ -#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 - -/* CM_ABE_PLL_REF_CLKSEL */ -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 - -/* CM_BYPCLK_DPLL_IVA */ -#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 -#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 - -#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 - -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_DSS_DSS_CLKCTRL */ -#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 - -/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ -#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) - -/* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8) - -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) - -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - -/* PMIC */ -#define SMPS_I2C_SLAVE_ADDR 0x12 -/* TWL6030 SMPS */ -#define SMPS_REG_ADDR_VCORE1 0x55 -#define SMPS_REG_ADDR_VCORE2 0x5B -#define SMPS_REG_ADDR_VCORE3 0x61 -/* TWL6032 SMPS */ -#define SMPS_REG_ADDR_SMPS1 0x55 -#define SMPS_REG_ADDR_SMPS2 0x5B -#define SMPS_REG_ADDR_SMPS5 0x49 - -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 -#define TPS62361_VSEL0_GPIO 7 - -/* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) -#define AUXCLK_SRCSELECT_SHIFT 1 -#define AUXCLK_SRCSELECT_MASK (3 << 1) -#define AUXCLK_CLKDIV_SHIFT 16 -#define AUXCLK_CLKDIV_MASK (0xF << 16) - -#define AUXCLK_SRCSELECT_SYS_CLK 0 -#define AUXCLK_SRCSELECT_CORE_DPLL 1 -#define AUXCLK_SRCSELECT_PER_DPLL 2 -#define AUXCLK_SRCSELECT_ALTERNATE 3 - -#define AUXCLK_CLKDIV_2 1 -#define AUXCLK_CLKDIV_16 0xF - -/* ALTCLKSRC */ -#define ALTCLKSRC_MODE_MASK 3 -#define ALTCLKSRC_ENABLE_INT_MASK 4 -#define ALTCLKSRC_ENABLE_EXT_MASK 8 - -#define ALTCLKSRC_MODE_ACTIVE 1 - -#define DPLL_NO_LOCK 0 -#define DPLL_LOCK 1 - -/* Clock Defines */ -#define V_OSCK 38400000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - -struct omap4_scrm_regs { - u32 revision; /* 0x0000 */ - u32 pad00[63]; - u32 clksetuptime; /* 0x0100 */ - u32 pmicsetuptime; /* 0x0104 */ - u32 pad01[2]; - u32 altclksrc; /* 0x0110 */ - u32 pad02[2]; - u32 c2cclkm; /* 0x011c */ - u32 pad03[56]; - u32 extclkreq; /* 0x0200 */ - u32 accclkreq; /* 0x0204 */ - u32 pwrreq; /* 0x0208 */ - u32 pad04[1]; - u32 auxclkreq0; /* 0x0210 */ - u32 auxclkreq1; /* 0x0214 */ - u32 auxclkreq2; /* 0x0218 */ - u32 auxclkreq3; /* 0x021c */ - u32 auxclkreq4; /* 0x0220 */ - u32 auxclkreq5; /* 0x0224 */ - u32 pad05[3]; - u32 c2cclkreq; /* 0x0234 */ - u32 pad06[54]; - u32 auxclk0; /* 0x0310 */ - u32 auxclk1; /* 0x0314 */ - u32 auxclk2; /* 0x0318 */ - u32 auxclk3; /* 0x031c */ - u32 auxclk4; /* 0x0320 */ - u32 auxclk5; /* 0x0324 */ - u32 pad07[54]; - u32 rsttime_reg; /* 0x0400 */ - u32 pad08[6]; - u32 c2crstctrl; /* 0x041c */ - u32 extpwronrstctrl; /* 0x0420 */ - u32 pad09[59]; - u32 extwarmrstst_reg; /* 0x0510 */ - u32 apewarmrstst_reg; /* 0x0514 */ - u32 pad10[1]; - u32 c2cwarmrstst_reg; /* 0x051C */ -}; -#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h deleted file mode 100644 index 4c9ed45..0000000 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Texas Instruments, <www.ti.com> - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <asm/arch/hardware.h> - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u32 tistat; /* 0x14 r */ - u32 tisr; /* 0x18 rw */ - u32 tier; /* 0x1c rw */ - u32 twer; /* 0x20 rw */ - u32 tclr; /* 0x24 rw */ - u32 tcrr; /* 0x28 rw */ - u32 tldr; /* 0x2c rw */ - u32 ttgr; /* 0x30 rw */ - u32 twpc; /* 0x34 r */ - u32 tmar; /* 0x38 rw */ - u32 tcar1; /* 0x3c r */ - u32 tcicr; /* 0x40 rw */ - u32 tcar2; /* 0x44 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* I2C base */ -#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) -#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) -#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) -#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) - -/* MUSB base */ -#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) - -/* OMAP4 GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0114 -#define OMAP_GPIO_IRQSTATUS1 0x0118 -#define OMAP_GPIO_IRQSTATUS2 0x0128 -#define OMAP_GPIO_IRQENABLE2 0x012c -#define OMAP_GPIO_IRQENABLE1 0x011c -#define OMAP_GPIO_WAKE_EN 0x0120 -#define OMAP_GPIO_CTRL 0x0130 -#define OMAP_GPIO_OE 0x0134 -#define OMAP_GPIO_DATAIN 0x0138 -#define OMAP_GPIO_DATAOUT 0x013c -#define OMAP_GPIO_LEVELDETECT0 0x0140 -#define OMAP_GPIO_LEVELDETECT1 0x0144 -#define OMAP_GPIO_RISINGDETECT 0x0148 -#define OMAP_GPIO_FALLINGDETECT 0x014c -#define OMAP_GPIO_DEBOUNCE_EN 0x0150 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 -#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 -#define OMAP_GPIO_SETIRQENABLE1 0x0164 -#define OMAP_GPIO_CLEARWKUENA 0x0180 -#define OMAP_GPIO_SETWKUENA 0x0184 -#define OMAP_GPIO_CLEARDATAOUT 0x0190 -#define OMAP_GPIO_SETDATAOUT 0x0194 - -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4A306000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 -#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) -#define PRM_RSTST_WARM_RESET_MASK 0x07EA - -#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h deleted file mode 100644 index 30bdaad..0000000 --- a/arch/arm/include/asm/arch-omap4/ehci.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * OMAP EHCI port support - * Based on LINUX KERNEL - * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com - * Author: Govindraj R <govindraj.raja@ti.com> - */ - -#ifndef _OMAP4_EHCI_H_ -#define _OMAP4_EHCI_H_ - -#define OMAP_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00) -#define OMAP_UHH_BASE (OMAP44XX_L4_CORE_BASE + 0x64000) -#define OMAP_USBTLL_BASE (OMAP44XX_L4_CORE_BASE + 0x62000) - -/* UHH, TLL and opt clocks */ -#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL - -#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK (1 << 24) - -/* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 - -#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) - -#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ - OMAP_UHH_SYSCONFIG_NOSTDBY) - -#endif /* _OMAP4_EHCI_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h deleted file mode 100644 index aceb3e2..0000000 --- a/arch/arm/include/asm/arch-omap4/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_OMAP4_H -#define _GPIO_OMAP4_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 192 - -#define OMAP44XX_GPIO1_BASE 0x4A310000 -#define OMAP44XX_GPIO2_BASE 0x48055000 -#define OMAP44XX_GPIO3_BASE 0x48057000 -#define OMAP44XX_GPIO4_BASE 0x48059000 -#define OMAP44XX_GPIO5_BASE 0x4805B000 -#define OMAP44XX_GPIO6_BASE 0x4805D000 - -#endif /* _GPIO_OMAP4_H */ diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h deleted file mode 100644 index 48dc809..0000000 --- a/arch/arm/include/asm/arch-omap4/hardware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware.h - * - * hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __OMAP_HARDWARE_H -#define __OMAP_HARDWARE_H - -#include <asm/arch/omap.h> - -/* - * Common hardware definitions - */ - -/* BCH Error Location Module */ -#define ELM_BASE 0x48078000 - -/* GPMC Base address */ -#define GPMC_BASE 0x50000000 - -#endif diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h deleted file mode 100644 index c8f2f97..0000000 --- a/arch/arm/include/asm/arch-omap4/i2c.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2010 - * Texas Instruments, <www.ti.com> - */ -#ifndef _OMAP4_I2C_H_ -#define _OMAP4_I2C_H_ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#endif /* _OMAP4_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h deleted file mode 100644 index 3026a00..0000000 --- a/arch/arm/include/asm/arch-omap4/mem.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * Author - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Richard Woodruff <r-woodruff2@ti.com> - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -/* - * GPMC settings - - * Definitions is as per the following format - * #define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL - */ -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define M_NAND_GPMC_CONFIG1 0x00000800 -#define M_NAND_GPMC_CONFIG2 0x001e1e00 -#define M_NAND_GPMC_CONFIG3 0x001e1e00 -#define M_NAND_GPMC_CONFIG4 0x16051807 -#define M_NAND_GPMC_CONFIG5 0x00151e1e -#define M_NAND_GPMC_CONFIG6 0x16000f80 -#define M_NAND_GPMC_CONFIG7 0x00000008 - -#define STNOR_GPMC_CONFIG1 0x00001200 -#define STNOR_GPMC_CONFIG2 0x00101000 -#define STNOR_GPMC_CONFIG3 0x00030301 -#define STNOR_GPMC_CONFIG4 0x10041004 -#define STNOR_GPMC_CONFIG5 0x000C1010 -#define STNOR_GPMC_CONFIG6 0x08070280 -#define STNOR_GPMC_CONFIG7 0x00000F48 - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h deleted file mode 100644 index d067799..0000000 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* - * OMAP HSMMC register definitions - */ - -#define OMAP_HSMMC1_BASE 0x4809C000 -#define OMAP_HSMMC2_BASE 0x480B4000 -#define OMAP_HSMMC3_BASE 0x480AD000 - -#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h deleted file mode 100644 index 854203c..0000000 --- a/arch/arm/include/asm/arch-omap4/mux_omap4.h +++ /dev/null @@ -1,328 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff <r-woodruff2@ti.com> - * Aneesh V <aneesh@ti.com> - * Balaji Krishnamoorthy <balajitk@ti.com> - */ -#ifndef _MUX_OMAP4_H_ -#define _MUX_OMAP4_H_ - -#include <asm/types.h> - -struct pad_conf_entry { - - u16 offset; - - u16 val; - -}; - -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define GPMC_AD0 0x0040 -#define GPMC_AD1 0x0042 -#define GPMC_AD2 0x0044 -#define GPMC_AD3 0x0046 -#define GPMC_AD4 0x0048 -#define GPMC_AD5 0x004A -#define GPMC_AD6 0x004C -#define GPMC_AD7 0x004E -#define GPMC_AD8 0x0050 -#define GPMC_AD9 0x0052 -#define GPMC_AD10 0x0054 -#define GPMC_AD11 0x0056 -#define GPMC_AD12 0x0058 -#define GPMC_AD13 0x005A -#define GPMC_AD14 0x005C -#define GPMC_AD15 0x005E -#define GPMC_A16 0x0060 -#define GPMC_A17 0x0062 -#define GPMC_A18 0x0064 -#define GPMC_A19 0x0066 -#define GPMC_A20 0x0068 -#define GPMC_A21 0x006A -#define GPMC_A22 0x006C -#define GPMC_A23 0x006E -#define GPMC_A24 0x0070 -#define GPMC_A25 0x0072 -#define GPMC_NCS0 0x0074 -#define GPMC_NCS1 0x0076 -#define GPMC_NCS2 0x0078 -#define GPMC_NCS3 0x007A -#define GPMC_NWP 0x007C -#define GPMC_CLK 0x007E -#define GPMC_NADV_ALE 0x0080 -#define GPMC_NOE 0x0082 -#define GPMC_NWE 0x0084 -#define GPMC_NBE0_CLE 0x0086 -#define GPMC_NBE1 0x0088 -#define GPMC_WAIT0 0x008A -#define GPMC_WAIT1 0x008C -#define C2C_DATA11 0x008E -#define C2C_DATA12 0x0090 -#define C2C_DATA13 0x0092 -#define C2C_DATA14 0x0094 -#define C2C_DATA15 0x0096 -#define HDMI_HPD 0x0098 -#define HDMI_CEC 0x009A -#define HDMI_DDC_SCL 0x009C -#define HDMI_DDC_SDA 0x009E -#define CSI21_DX0 0x00A0 -#define CSI21_DY0 0x00A2 -#define CSI21_DX1 0x00A4 -#define CSI21_DY1 0x00A6 -#define CSI21_DX2 0x00A8 -#define CSI21_DY2 0x00AA -#define CSI21_DX3 0x00AC -#define CSI21_DY3 0x00AE -#define CSI21_DX4 0x00B0 -#define CSI21_DY4 0x00B2 -#define CSI22_DX0 0x00B4 -#define CSI22_DY0 0x00B6 -#define CSI22_DX1 0x00B8 -#define CSI22_DY1 0x00BA -#define CAM_SHUTTER 0x00BC -#define CAM_STROBE 0x00BE -#define CAM_GLOBALRESET 0x00C0 -#define USBB1_ULPITLL_CLK 0x00C2 -#define USBB1_ULPITLL_STP 0x00C4 -#define USBB1_ULPITLL_DIR 0x00C6 -#define USBB1_ULPITLL_NXT 0x00C8 -#define USBB1_ULPITLL_DAT0 0x00CA -#define USBB1_ULPITLL_DAT1 0x00CC -#define USBB1_ULPITLL_DAT2 0x00CE -#define USBB1_ULPITLL_DAT3 0x00D0 -#define USBB1_ULPITLL_DAT4 0x00D2 -#define USBB1_ULPITLL_DAT5 0x00D4 -#define USBB1_ULPITLL_DAT6 0x00D6 -#define USBB1_ULPITLL_DAT7 0x00D8 -#define USBB1_HSIC_DATA 0x00DA -#define USBB1_HSIC_STROBE 0x00DC -#define USBC1_ICUSB_DP 0x00DE -#define USBC1_ICUSB_DM 0x00E0 -#define SDMMC1_CLK 0x00E2 -#define SDMMC1_CMD 0x00E4 -#define SDMMC1_DAT0 0x00E6 -#define SDMMC1_DAT1 0x00E8 -#define SDMMC1_DAT2 0x00EA -#define SDMMC1_DAT3 0x00EC -#define SDMMC1_DAT4 0x00EE -#define SDMMC1_DAT5 0x00F0 -#define SDMMC1_DAT6 0x00F2 -#define SDMMC1_DAT7 0x00F4 -#define ABE_MCBSP2_CLKX 0x00F6 -#define ABE_MCBSP2_DR 0x00F8 -#define ABE_MCBSP2_DX 0x00FA -#define ABE_MCBSP2_FSX 0x00FC -#define ABE_MCBSP1_CLKX 0x00FE -#define ABE_MCBSP1_DR 0x0100 -#define ABE_MCBSP1_DX 0x0102 -#define ABE_MCBSP1_FSX 0x0104 -#define ABE_PDM_UL_DATA 0x0106 -#define ABE_PDM_DL_DATA 0x0108 -#define ABE_PDM_FRAME 0x010A -#define ABE_PDM_LB_CLK 0x010C -#define ABE_CLKS 0x010E -#define ABE_DMIC_CLK1 0x0110 -#define ABE_DMIC_DIN1 0x0112 -#define ABE_DMIC_DIN2 0x0114 -#define ABE_DMIC_DIN3 0x0116 -#define UART2_CTS 0x0118 -#define UART2_RTS 0x011A -#define UART2_RX 0x011C -#define UART2_TX 0x011E -#define HDQ_SIO 0x0120 -#define I2C1_SCL 0x0122 -#define I2C1_SDA 0x0124 -#define I2C2_SCL 0x0126 -#define I2C2_SDA 0x0128 -#define I2C3_SCL 0x012A -#define I2C3_SDA 0x012C -#define I2C4_SCL 0x012E -#define I2C4_SDA 0x0130 -#define MCSPI1_CLK 0x0132 -#define MCSPI1_SOMI 0x0134 -#define MCSPI1_SIMO 0x0136 -#define MCSPI1_CS0 0x0138 -#define MCSPI1_CS1 0x013A -#define MCSPI1_CS2 0x013C -#define MCSPI1_CS3 0x013E -#define UART3_CTS_RCTX 0x0140 -#define UART3_RTS_SD 0x0142 -#define UART3_RX_IRRX 0x0144 -#define UART3_TX_IRTX 0x0146 -#define SDMMC5_CLK 0x0148 -#define SDMMC5_CMD 0x014A -#define SDMMC5_DAT0 0x014C -#define SDMMC5_DAT1 0x014E -#define SDMMC5_DAT2 0x0150 -#define SDMMC5_DAT3 0x0152 -#define MCSPI4_CLK 0x0154 -#define MCSPI4_SIMO 0x0156 -#define MCSPI4_SOMI 0x0158 -#define MCSPI4_CS0 0x015A -#define UART4_RX 0x015C -#define UART4_TX 0x015E -#define USBB2_ULPITLL_CLK 0x0160 -#define USBB2_ULPITLL_STP 0x0162 -#define USBB2_ULPITLL_DIR 0x0164 -#define USBB2_ULPITLL_NXT 0x0166 -#define USBB2_ULPITLL_DAT0 0x0168 -#define USBB2_ULPITLL_DAT1 0x016A -#define USBB2_ULPITLL_DAT2 0x016C -#define USBB2_ULPITLL_DAT3 0x016E -#define USBB2_ULPITLL_DAT4 0x0170 -#define USBB2_ULPITLL_DAT5 0x0172 -#define USBB2_ULPITLL_DAT6 0x0174 -#define USBB2_ULPITLL_DAT7 0x0176 -#define USBB2_HSIC_DATA 0x0178 -#define USBB2_HSIC_STROBE 0x017A -#define UNIPRO_TX0 0x017C -#define UNIPRO_TY0 0x017E -#define UNIPRO_TX1 0x0180 -#define UNIPRO_TY1 0x0182 -#define UNIPRO_TX2 0x0184 -#define UNIPRO_TY2 0x0186 -#define UNIPRO_RX0 0x0188 -#define UNIPRO_RY0 0x018A -#define UNIPRO_RX1 0x018C -#define UNIPRO_RY1 0x018E -#define UNIPRO_RX2 0x0190 -#define UNIPRO_RY2 0x0192 -#define USBA0_OTG_CE 0x0194 -#define USBA0_OTG_DP 0x0196 -#define USBA0_OTG_DM 0x0198 -#define FREF_CLK1_OUT 0x019A -#define FREF_CLK2_OUT 0x019C -#define SYS_NIRQ1 0x019E -#define SYS_NIRQ2 0x01A0 -#define SYS_BOOT0 0x01A2 -#define SYS_BOOT1 0x01A4 -#define SYS_BOOT2 0x01A6 -#define SYS_BOOT3 0x01A8 -#define SYS_BOOT4 0x01AA -#define SYS_BOOT5 0x01AC -#define DPM_EMU0 0x01AE -#define DPM_EMU1 0x01B0 -#define DPM_EMU2 0x01B2 -#define DPM_EMU3 0x01B4 -#define DPM_EMU4 0x01B6 -#define DPM_EMU5 0x01B8 -#define DPM_EMU6 0x01BA -#define DPM_EMU7 0x01BC -#define DPM_EMU8 0x01BE -#define DPM_EMU9 0x01C0 -#define DPM_EMU10 0x01C2 -#define DPM_EMU11 0x01C4 -#define DPM_EMU12 0x01C6 -#define DPM_EMU13 0x01C8 -#define DPM_EMU14 0x01CA -#define DPM_EMU15 0x01CC -#define DPM_EMU16 0x01CE -#define DPM_EMU17 0x01D0 -#define DPM_EMU18 0x01D2 -#define DPM_EMU19 0x01D4 -#define WAKEUPEVENT_0 0x01D8 -#define WAKEUPEVENT_1 0x01DC -#define WAKEUPEVENT_2 0x01E0 -#define WAKEUPEVENT_3 0x01E4 -#define WAKEUPEVENT_4 0x01E8 -#define WAKEUPEVENT_5 0x01EC -#define WAKEUPEVENT_6 0x01F0 - -#define WKUP_REVISION 0x0000 -#define WKUP_HWINFO 0x0004 -#define WKUP_SYSCONFIG 0x0010 -#define PAD0_SIM_IO 0x0040 -#define PAD1_SIM_CLK 0x0042 -#define PAD0_SIM_RESET 0x0044 -#define PAD1_SIM_CD 0x0046 -#define PAD0_SIM_PWRCTRL 0x0048 -#define PAD1_SR_SCL 0x004A -#define PAD0_SR_SDA 0x004C -#define PAD1_FREF_XTAL_IN 0x004E -#define PAD0_FREF_SLICER_IN 0x0050 -#define PAD1_FREF_CLK_IOREQ 0x0052 -#define PAD0_FREF_CLK0_OUT 0x0054 -#define PAD1_FREF_CLK3_REQ 0x0056 -#define PAD0_FREF_CLK3_OUT 0x0058 -#define PAD1_FREF_CLK4_REQ 0x005A -#define PAD0_FREF_CLK4_OUT 0x005C -#define PAD1_SYS_32K 0x005E -#define PAD0_SYS_NRESPWRON 0x0060 -#define PAD1_SYS_NRESWARM 0x0062 -#define PAD0_SYS_PWR_REQ 0x0064 -#define PAD1_SYS_PWRON_RESET 0x0066 -#define PAD0_SYS_BOOT6 0x0068 -#define PAD1_SYS_BOOT7 0x006A -#define PAD0_JTAG_NTRST 0x006C -#define PAD1_JTAG_TCK 0x006D -#define PAD0_JTAG_RTCK 0x0070 -#define PAD1_JTAG_TMS_TMSC 0x0072 -#define PAD0_JTAG_TDI 0x0074 -#define PAD1_JTAG_TDO 0x0076 -#define PADCONF_WAKEUPEVENT_0 0x007C -#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 -#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 -#define PADCONF_MODE 0x05A8 -#define CONTROL_XTAL_OSCILLATOR 0x05AC -#define CONTROL_CONTROL_I2C_2 0x0604 -#define CONTROL_CONTROL_JTAG 0x0608 -#define CONTROL_CONTROL_SYS 0x060C -#define CONTROL_SPARE_RW 0x0614 -#define CONTROL_SPARE_R 0x0618 -#define CONTROL_SPARE_R_C0 0x061C - -#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A -#endif /* _MUX_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h deleted file mode 100644 index 8919088..0000000 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Authors: - * Aneesh V <aneesh@ti.com> - * - * Derived from OMAP3 work by - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - */ - -#ifndef _OMAP4_H_ -#define _OMAP4_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <linux/sizes.h> - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP44XX_L4_CORE_BASE 0x4A000000 -#define OMAP44XX_L4_WKUP_BASE 0x4A300000 -#define OMAP44XX_L4_PER_BASE 0x48000000 - -#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 -#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START -#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END - -/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE 0x4A002204 - -#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F -#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F -#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F -#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F -#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F -#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F -#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F -#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F - -/* UART */ -#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) -#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) -#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) - -/* General Purpose Timers */ -#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) -#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) -#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) - -/* Watchdog Timer2 - MPU watchdog */ -#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) - -/* - * Hardware Register Details - */ - -/* Watchdog Timer */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* GP Timer */ -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* Control Module */ -#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) -#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f -#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 -#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 - -/* LPDDR2 IO regs */ -#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C -#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E -#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C -#define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F - -/* CONTROL_EFUSE_2 */ -#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 - -#define MMC1_PWRDNZ (1 << 26) -#define MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define MMC1_PBIASLITE_VMODE (1 << 21) - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#define DEVICE_TYPE_SHIFT (0x8) -#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) - -#endif /* __ASSEMBLY__ */ - -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ -#define NON_SECURE_SRAM_START 0x40304000 -#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ -#define NON_SECURE_SRAM_IMG_END 0x4030C000 -#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_ROM_VECT_BASE 0x4030D000 - -/* ABB settings */ -#define OMAP_ABB_SETTLING_TIME 50 -#define OMAP_ABB_CLOCK_CYCLES 16 - -/* ABB tranxdone mask */ -#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) - -#define OMAP44XX_SAR_RAM_BASE 0x4a326000 -#define OMAP_REBOOT_REASON_OFFSET 0xA0C -#define OMAP_REBOOT_REASON_SIZE 0x0F - -/* Boot parameters */ -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - unsigned int boot_message; - unsigned int boot_device_descriptor; - unsigned char boot_device; - unsigned char reset_reason; - unsigned char ch_flags; -}; - -int omap_reboot_mode(char *mode, unsigned int length); -int omap_reboot_mode_clear(void); -int omap_reboot_mode_store(char *mode); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h deleted file mode 100644 index d24944a..0000000 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0x00 -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x03 -#define BOOT_DEVICE_ONENAND 0x04 -#define BOOT_DEVICE_MMC1 0x05 -#define BOOT_DEVICE_MMC2 0x06 -#define BOOT_DEVICE_MMC2_2 0x07 -#define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_USB 0x45 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 -#endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h deleted file mode 100644 index b2a6887..0000000 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <asm/arch/omap.h> -#include <asm/arch/clock.h> -#include <asm/io.h> -#include <asm/omap_common.h> -#include <linux/mtd/omap_gpmc.h> -#include <asm/arch/mux_omap4.h> -#include <asm/ti-common/sys_proto.h> - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; -extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; -extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; -extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; -extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; -extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; -extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; -#else -extern const struct lpddr2_device_details elpida_2G_S4_details; -extern const struct lpddr2_device_details elpida_4G_S4_details; -#endif - -#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -extern const struct lpddr2_device_timings jedec_default_timings; -#else -extern const struct lpddr2_device_timings elpida_2G_S4_timings; -#endif - -struct omap_sysinfo { - char *board_string; -}; -extern const struct omap_sysinfo sysinfo; - -void gpmc_init(void); -void watchdog_init(void); -u32 get_device_type(void); -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); -void set_muxconf_regs(void); -u32 wait_on_value(u32, u32, void *, u32); -void sdelay(unsigned long); -void setup_early_clocks(void); -void prcm_init(void); -void do_board_detect(void); -void bypass_dpll(u32 const base); -void freq_update_core(void); -u32 get_sys_clk_freq(void); -u32 omap4_ddr_clk(void); -void cancel_out(u32 *num, u32 *den, u32 den_limit); -void sdram_init(void); -u32 omap_sdram_size(void); -u32 cortex_rev(void); -void save_omap_boot_params(void); -void init_omap_revision(void); -void do_io_settings(void); -void sri2c_init(void); -int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); -u32 warm_reset(void); -void force_emif_self_refresh(void); -void setup_warmreset_time(void); - -#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 - -#endif diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h deleted file mode 100644 index e261bd4..0000000 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ /dev/null @@ -1,417 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * Sricharan R <r.sricharan@ti.com> - */ -#ifndef _CLOCKS_OMAP5_H_ -#define _CLOCKS_OMAP5_H_ -#include <common.h> -#include <asm/omap_common.h> - -/* - * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per - * loop, allow for a minimum of 2 ms wait (in reality the wait will be - * much more than that) - */ -#define LDELAY 1000000 - -/* CM_DLL_CTRL */ -#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* SGX */ -#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) -#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 - -/* CM_ABE_PLL_REF_CLKSEL */ -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 - -/* CM_CLKSEL_ABE_PLL_SYS */ -#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 -#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 -#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 -#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 - -/* CM_BYPCLK_DPLL_IVA */ -#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 -#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 - -#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 - -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) - -/* CM_L3INIT_SATA_CLKCTRL */ -#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_DSS_DSS_CLKCTRL */ -#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 - -/* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 - -/* CM_L3INIT_USB_HOST_HS_CLKCTRL */ -#define OPTFCLKEN_FUNC48M_CLK (1 << 15) -#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) -#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) -#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) -#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) -#define OPTFCLKEN_UTMI_P3_CLK (1 << 10) -#define OPTFCLKEN_UTMI_P2_CLK (1 << 9) -#define OPTFCLKEN_UTMI_P1_CLK (1 << 8) -#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) -#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) - -/* CM_L3INIT_USB_TLL_HS_CLKCTRL */ -#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) -#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) -#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) - -/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ -#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) - -/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */ -#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8) - -/* CM_L3INIT_USB_OTG_SS_CLKCTRL */ -#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) -#define OPTFCLKEN_REFCLK960M (1 << 8) - -/* CM_L3INIT_OCP2SCP1_CLKCTRL */ -#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) - -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) - -/* CM_WKUPAON_SCRM_CLKCTRL */ -#define OPTFCLKEN_SCRM_PER_SHIFT 9 -#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) -#define OPTFCLKEN_SCRM_CORE_SHIFT 8 -#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) - -/* CM_COREAON_IO_SRCOMP_CLKCTRL */ -#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 -#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) - -/* PRM_RSTTIME */ -#define RSTTIME1_SHIFT 0 -#define RSTTIME1_MASK (0x3ff << 0) - -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - -/* CTRL_CORE_SRCOMP_NORTH_SIDE */ -#define USB2PHY_DISCHGDET (1 << 29) -#define USB2PHY_AUTORESUME_EN (1 << 30) - -/* SMPS */ -#define SMPS_I2C_SLAVE_ADDR 0x12 -#define SMPS_REG_ADDR_12_MPU 0x23 -#define SMPS_REG_ADDR_45_IVA 0x2B -#define SMPS_REG_ADDR_8_CORE 0x37 - -/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ -/* ES1.0 settings */ -#define VDD_MPU 1040 -#define VDD_MM 1040 -#define VDD_CORE 1040 - -#define VDD_MPU_LOW 890 -#define VDD_MM_LOW 890 -#define VDD_CORE_LOW 890 - -/* ES2.0 settings */ -#define VDD_MPU_ES2 1060 -#define VDD_MM_ES2 1025 -#define VDD_CORE_ES2 1040 - -#define VDD_MPU_ES2_HIGH 1250 -#define VDD_MM_ES2_OD 1120 - -/* Efuse register offsets for OMAP5 platform */ -#define OMAP5_ES2_EFUSE_BASE 0x4A002000 -#define OMAP5_ES2_PROD_REGBITS 16 - -/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ -#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) - -/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ -#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) -/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ -#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) -/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ -#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) -/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ -#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) - -/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA7_NOM 1150 -#define VDD_CORE_DRA7_NOM 1150 -#define VDD_EVE_DRA7_NOM 1060 -#define VDD_GPU_DRA7_NOM 1060 -#define VDD_IVA_DRA7_NOM 1060 - -/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */ -#define VDD_EVE_DRA7_OD 1150 -#define VDD_GPU_DRA7_OD 1150 -#define VDD_IVA_DRA7_OD 1150 - -/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */ -#define VDD_EVE_DRA7_HIGH 1250 -#define VDD_GPU_DRA7_HIGH 1250 -#define VDD_IVA_DRA7_HIGH 1250 - -/* Efuse register offsets for DRA7xx platform */ -#define DRA752_EFUSE_BASE 0x4A002000 -#define DRA752_EFUSE_REGBITS 16 -/* STD_FUSE_OPP_VMIN_IVA_2 */ -#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) -/* STD_FUSE_OPP_VMIN_IVA_3 */ -#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) -/* STD_FUSE_OPP_VMIN_IVA_4 */ -#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) -/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ -#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) -/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ -#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) -/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ -#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) -/* STD_FUSE_OPP_VMIN_CORE_2 */ -#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) -/* STD_FUSE_OPP_VMIN_GPU_2 */ -#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) -/* STD_FUSE_OPP_VMIN_GPU_3 */ -#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) -/* STD_FUSE_OPP_VMIN_GPU_4 */ -#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) -/* STD_FUSE_OPP_VMIN_MPU_2 */ -#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) -/* STD_FUSE_OPP_VMIN_MPU_3 */ -#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) -/* STD_FUSE_OPP_VMIN_MPU_4 */ -#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) - -#if defined(CONFIG_DRA7_MPU_OPP_HIGH) -#define DRA7_MPU_OPP OPP_HIGH -#elif defined(CONFIG_DRA7_MPU_OPP_OD) -#define DRA7_MPU_OPP OPP_OD -#else /* OPP_NOM default */ -#define DRA7_MPU_OPP OPP_NOM -#endif - -/* OPP_NOM only available option for CORE */ -#define DRA7_CORE_OPP OPP_NOM - -#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH) -#define DRA7_DSPEVE_OPP OPP_HIGH -#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD) -#define DRA7_DSPEVE_OPP OPP_OD -#else /* OPP_NOM default */ -#define DRA7_DSPEVE_OPP OPP_NOM -#endif - -#if defined(CONFIG_DRA7_IVA_OPP_HIGH) -#define DRA7_IVA_OPP OPP_HIGH -#elif defined(CONFIG_DRA7_IVA_OPP_OD) -#define DRA7_IVA_OPP OPP_OD -#else /* OPP_NOM default */ -#define DRA7_IVA_OPP OPP_NOM -#endif - -#if defined(CONFIG_DRA7_GPU_OPP_HIGH) -#define DRA7_GPU_OPP OPP_HIGH -#elif defined(CONFIG_DRA7_GPU_OPP_OD) -#define DRA7_GPU_OPP OPP_OD -#else /* OPP_NOM default */ -#define DRA7_GPU_OPP OPP_NOM -#endif - -/* Standard offset is 0.5v expressed in uv */ -#define PALMAS_SMPS_BASE_VOLT_UV 500000 - -/* Offset is 0.73V for LP873x */ -#define LP873X_BUCK_BASE_VOLT_UV 730000 - -/* Offset is 0.73V for LP87565 */ -#define LP87565_BUCK_BASE_VOLT_UV 730000 - -/* TPS659038 */ -#define TPS659038_I2C_SLAVE_ADDR 0x58 -#define TPS659038_REG_ADDR_SMPS12 0x23 -#define TPS659038_REG_ADDR_SMPS45 0x2B -#define TPS659038_REG_ADDR_SMPS6 0x2F -#define TPS659038_REG_ADDR_SMPS7 0x33 -#define TPS659038_REG_ADDR_SMPS8 0x37 - -/* TPS65917 */ -#define TPS65917_I2C_SLAVE_ADDR 0x58 -#define TPS65917_REG_ADDR_SMPS1 0x23 -#define TPS65917_REG_ADDR_SMPS2 0x27 -#define TPS65917_REG_ADDR_SMPS3 0x2F -#define TPS65917_REG_ADDR_SMPS4 0x33 - -/* LP873X */ -#define LP873X_I2C_SLAVE_ADDR 0x60 -#define LP873X_REG_ADDR_BUCK0 0x6 -#define LP873X_REG_ADDR_BUCK1 0x7 -#define LP873X_REG_ADDR_LDO1 0xA - -/* LP87565 */ -#define LP87565_I2C_SLAVE_ADDR 0x61 -#define LP87565_REG_ADDR_BUCK01 0xA -#define LP87565_REG_ADDR_BUCK23 0xE - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 -#define TPS62361_VSEL0_GPIO 7 - -/* Defines for DPLL setup */ -#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 -#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 -#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 - -#define DPLL_NO_LOCK 0 -#define DPLL_LOCK 1 - -#if defined(CONFIG_DRA7XX) -#define V_OSCK 20000000 /* Clock output from T2 */ -#else -#define V_OSCK 19200000 /* Clock output from T2 */ -#endif - -#define V_SCLK V_OSCK - -/* CKO buffer control */ -#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) - -/* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) -#define AUXCLK_SRCSELECT_SHIFT 1 -#define AUXCLK_SRCSELECT_MASK (3 << 1) -#define AUXCLK_CLKDIV_SHIFT 16 -#define AUXCLK_CLKDIV_MASK (0xF << 16) - -#define AUXCLK_SRCSELECT_SYS_CLK 0 -#define AUXCLK_SRCSELECT_CORE_DPLL 1 -#define AUXCLK_SRCSELECT_PER_DPLL 2 -#define AUXCLK_SRCSELECT_ALTERNATE 3 - -#endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h deleted file mode 100644 index 9e56553..0000000 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <asm/arch/hardware.h> - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -#include <asm/ti-common/omap_wdt.h> - -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res1[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u8 res2[0x10]; - u32 tisr_raw; /* 0x24 r */ - u32 tisr; /* 0x28 rw */ - u32 tier; /* 0x2c rw */ - u32 ticr; /* 0x30 rw */ - u32 twer; /* 0x34 rw */ - u32 tclr; /* 0x38 rw */ - u32 tcrr; /* 0x3c rw */ - u32 tldr; /* 0x40 rw */ - u32 ttgr; /* 0x44 rw */ - u32 twpc; /* 0x48 r */ - u32 tmar; /* 0x4c rw */ - u32 tcar1; /* 0x50 r */ - u32 tcicr; /* 0x54 rw */ - u32 tcar2; /* 0x58 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -#define WDT_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* I2C base */ -#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) -#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) -#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) -#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) -#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) - -/* MUSB base */ -#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) - -/* OMAP4 GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0114 -#define OMAP_GPIO_IRQSTATUS1 0x0118 -#define OMAP_GPIO_IRQSTATUS2 0x0128 -#define OMAP_GPIO_IRQENABLE2 0x012c -#define OMAP_GPIO_IRQENABLE1 0x011c -#define OMAP_GPIO_WAKE_EN 0x0120 -#define OMAP_GPIO_CTRL 0x0130 -#define OMAP_GPIO_OE 0x0134 -#define OMAP_GPIO_DATAIN 0x0138 -#define OMAP_GPIO_DATAOUT 0x013c -#define OMAP_GPIO_LEVELDETECT0 0x0140 -#define OMAP_GPIO_LEVELDETECT1 0x0144 -#define OMAP_GPIO_RISINGDETECT 0x0148 -#define OMAP_GPIO_FALLINGDETECT 0x014c -#define OMAP_GPIO_DEBOUNCE_EN 0x0150 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 -#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 -#define OMAP_GPIO_SETIRQENABLE1 0x0164 -#define OMAP_GPIO_CLEARWKUENA 0x0180 -#define OMAP_GPIO_SETWKUENA 0x0184 -#define OMAP_GPIO_CLEARDATAOUT 0x0190 -#define OMAP_GPIO_SETDATAOUT 0x0194 - -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4AE06000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 -#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) -#define PRM_RSTST_WARM_RESET_MASK 0x7FEA - -/* DRA7XX CPSW Config space */ -#define CPSW_BASE 0x48484000 -#define CPSW_MDIO_BASE 0x48485000 - -/* gmii_sel register defines */ -#define GMII1_SEL_MII 0x0 -#define GMII1_SEL_RMII 0x1 -#define GMII1_SEL_RGMII 0x2 -#define GMII2_SEL_MII (GMII1_SEL_MII << 4) -#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4) -#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4) - -#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) -#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) -#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) - -#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h deleted file mode 100644 index 09edfad..0000000 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Texas Instruments Incorporated - * - * Lokesh Vutla <lokeshvutla@ti.com> - */ - -#ifndef _DRA7_IODELAY_H_ -#define _DRA7_IODELAY_H_ - -#include <common.h> -#include <asm/arch/sys_proto.h> - -/* CONFIG_REG_0 */ -#define CFG_REG_0_OFFSET 0xC -#define CFG_REG_ROM_READ_SHIFT 1 -#define CFG_REG_ROM_READ_MASK (1 << 1) -#define CFG_REG_CALIB_STRT_SHIFT 0 -#define CFG_REG_CALIB_STRT_MASK (1 << 0) -#define CFG_REG_CALIB_STRT 1 -#define CFG_REG_CALIB_END 0 -#define CFG_REG_ROM_READ_START (1 << 1) -#define CFG_REG_ROM_READ_END (0 << 1) - -/* CONFIG_REG_2 */ -#define CFG_REG_2_OFFSET 0x14 -#define CFG_REG_REFCLK_PERIOD_SHIFT 0 -#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) -#define CFG_REG_REFCLK_PERIOD 0x2EF - -/* CONFIG_REG_8 */ -#define CFG_REG_8_OFFSET 0x2C -#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA -#define CFG_IODELAY_LOCK_KEY 0x0000AAAB - -/* CONFIG_REG_3/4 */ -#define CFG_REG_3_OFFSET 0x18 -#define CFG_REG_4_OFFSET 0x1C -#define CFG_REG_DLY_CNT_SHIFT 16 -#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16) -#define CFG_REG_REF_CNT_SHIFT 0 -#define CFG_REG_REF_CNT_MASK (0xFFFF << 0) - -/* CTRL_CORE_SMA_SW_0 */ -#define CTRL_ISOLATE_SHIFT 2 -#define CTRL_ISOLATE_MASK (1 << 2) -#define ISOLATE_IO 1 -#define DEISOLATE_IO 0 - -/* CTRL_CORE_SMA_SW_1 */ -#define RGMII2_ID_MODE_N_MASK (1 << 26) -#define RGMII1_ID_MODE_N_MASK (1 << 25) - -/* PRM_IO_PMCTRL */ -#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 -#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) -#define PMCTRL_ISOCLK_STATUS_SHIFT 1 -#define PMCTRL_ISOCLK_STATUS_MASK (1 << 1) -#define PMCTRL_ISOCLK_OVERRIDE_CTRL 1 -#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0 - -#define ERR_CALIBRATE_IODELAY 0x1 -#define ERR_DEISOLATE_IO 0x2 -#define ERR_ISOLATE_IO 0x4 -#define ERR_UPDATE_DELAY 0x8 -#define ERR_CPDE 0x3 -#define ERR_FPDE 0x5 - -/* CFG_XXX */ -#define CFG_X_SIGNATURE_SHIFT 12 -#define CFG_X_SIGNATURE_MASK (0x3F << 12) -#define CFG_X_LOCK_SHIFT 10 -#define CFG_X_LOCK_MASK (0x1 << 10) -#define CFG_X_COARSE_DLY_SHIFT 5 -#define CFG_X_COARSE_DLY_MASK (0x1F << 5) -#define CFG_X_FINE_DLY_SHIFT 0 -#define CFG_X_FINE_DLY_MASK (0x1F << 0) -#define CFG_X_SIGNATURE 0x29 -#define CFG_X_LOCK 1 - -void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, - struct iodelay_cfg_entry const *iodelay, - int niodelays); -void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, - struct iodelay_cfg_entry const *iodelay, - int niodelays); -int __recalibrate_iodelay_start(void); -void __recalibrate_iodelay_end(int ret); - -int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, - int niodelays); -#endif diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h deleted file mode 100644 index 1790b92..0000000 --- a/arch/arm/include/asm/arch-omap5/ehci.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com* - * Author: Govindraj R <govindraj.raja@ti.com> - */ - -#ifndef _EHCI_H -#define _EHCI_H - -#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00) -#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000) -#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000) - -/* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 - -#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) - -#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ - OMAP_UHH_SYSCONFIG_NOSTDBY) - -#endif /* _EHCI_H */ diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h deleted file mode 100644 index 1e44fb5..0000000 --- a/arch/arm/include/asm/arch-omap5/gpio.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_OMAP5_H -#define _GPIO_OMAP5_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 256 - -#define OMAP54XX_GPIO1_BASE 0x4Ae10000 -#define OMAP54XX_GPIO2_BASE 0x48055000 -#define OMAP54XX_GPIO3_BASE 0x48057000 -#define OMAP54XX_GPIO4_BASE 0x48059000 -#define OMAP54XX_GPIO5_BASE 0x4805B000 -#define OMAP54XX_GPIO6_BASE 0x4805D000 -#define OMAP54XX_GPIO7_BASE 0x48051000 -#define OMAP54XX_GPIO8_BASE 0x48053000 - - -/* Get the GPIO index from the given bank number and bank gpio */ -#define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio)) - -#endif /* _GPIO_OMAP5_H */ diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h deleted file mode 100644 index b6d26e9..0000000 --- a/arch/arm/include/asm/arch-omap5/hardware.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware.h - * - * hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __OMAP_HARDWARE_H -#define __OMAP_HARDWARE_H - -#include <asm/arch/omap.h> - -/* - * Common hardware definitions - */ - -/* BCH Error Location Module */ -#define ELM_BASE 0x48078000 - -/* GPMC Base address */ -#define GPMC_BASE 0x50000000 - -/* EDMA3 Base address for DRA7XX and AM57XX */ -#if defined(CONFIG_DRA7XX) -#define EDMA3_BASE 0x43300000 -#endif - -#endif diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h deleted file mode 100644 index 9e1edcf..0000000 --- a/arch/arm/include/asm/arch-omap5/i2c.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2010 - * Texas Instruments, <www.ti.com> - */ -#ifndef _OMAP5_I2C_H_ -#define _OMAP5_I2C_H_ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#endif /* _OMAP5_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h deleted file mode 100644 index bd72fb6..0000000 --- a/arch/arm/include/asm/arch-omap5/mem.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * Author - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Richard Woodruff <r-woodruff2@ti.com> - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -/* - * GPMC settings - - * Definitions is as per the following format - * #define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL - */ -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define M_NAND_GPMC_CONFIG1 0x00000800 -#define M_NAND_GPMC_CONFIG2 0x001e1e00 -#define M_NAND_GPMC_CONFIG3 0x001e1e00 -#define M_NAND_GPMC_CONFIG4 0x16051807 -#define M_NAND_GPMC_CONFIG5 0x00151e1e -#define M_NAND_GPMC_CONFIG6 0x16000f80 -#define M_NAND_GPMC_CONFIG7 0x00000008 - -#define STNOR_GPMC_CONFIG1 0x00001000 -#define STNOR_GPMC_CONFIG2 0x001f1f00 -#define STNOR_GPMC_CONFIG3 0x001f1f01 -#define STNOR_GPMC_CONFIG4 0x1f011f01 -#define STNOR_GPMC_CONFIG5 0x001d1f1f -#define STNOR_GPMC_CONFIG6 0x08070280 -#define STNOR_GPMC_CONFIG7 0x00000048 - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h deleted file mode 100644 index d067799..0000000 --- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* - * OMAP HSMMC register definitions - */ - -#define OMAP_HSMMC1_BASE 0x4809C000 -#define OMAP_HSMMC2_BASE 0x480B4000 -#define OMAP_HSMMC3_BASE 0x480AD000 - -#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h deleted file mode 100644 index c7c118e..0000000 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated - * - * Nishant Kamat <nskamat@ti.com> - * Lokesh Vutla <lokeshvutla@ti.com> - */ -#ifndef _MUX_DRA7XX_H_ -#define _MUX_DRA7XX_H_ - -#include <asm/types.h> - -#define PULL_ENA (0 << 16) -#define PULL_DIS (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCONTROL (1 << 19) - -/* Active pin states */ -#define PIN_OUTPUT (0 | PULL_DIS) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN (0) -#define PIN_INPUT (INPUT_EN | PULL_DIS) -#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 -#define M8 8 -#define M9 9 -#define M10 10 -#define M11 11 -#define M12 12 -#define M13 13 -#define M14 14 -#define M15 15 - -#define MODE_SELECT (1 << 8) -#define DELAYMODE_SHIFT 4 - -#define MANUAL_MODE MODE_SELECT - -#define VIRTUAL_MODE0 (MODE_SELECT | (0x0 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE1 (MODE_SELECT | (0x1 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE2 (MODE_SELECT | (0x2 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE3 (MODE_SELECT | (0x3 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE4 (MODE_SELECT | (0x4 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE5 (MODE_SELECT | (0x5 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE6 (MODE_SELECT | (0x6 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE7 (MODE_SELECT | (0x7 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE8 (MODE_SELECT | (0x8 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE9 (MODE_SELECT | (0x9 << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE10 (MODE_SELECT | (0xa << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE11 (MODE_SELECT | (0xb << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE12 (MODE_SELECT | (0xc << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE13 (MODE_SELECT | (0xd << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE14 (MODE_SELECT | (0xe << DELAYMODE_SHIFT)) -#define VIRTUAL_MODE15 (MODE_SELECT | (0xf << DELAYMODE_SHIFT)) - -#define SAFE_MODE M15 - -#define GPMC_AD0 0x000 -#define GPMC_AD1 0x004 -#define GPMC_AD2 0x008 -#define GPMC_AD3 0x00C -#define GPMC_AD4 0x010 -#define GPMC_AD5 0x014 -#define GPMC_AD6 0x018 -#define GPMC_AD7 0x01C -#define GPMC_AD8 0x020 -#define GPMC_AD9 0x024 -#define GPMC_AD10 0x028 -#define GPMC_AD11 0x02C -#define GPMC_AD12 0x030 -#define GPMC_AD13 0x034 -#define GPMC_AD14 0x038 -#define GPMC_AD15 0x03C -#define GPMC_A0 0x040 -#define GPMC_A1 0x044 -#define GPMC_A2 0x048 -#define GPMC_A3 0x04C -#define GPMC_A4 0x050 -#define GPMC_A5 0x054 -#define GPMC_A6 0x058 -#define GPMC_A7 0x05C -#define GPMC_A8 0x060 -#define GPMC_A9 0x064 -#define GPMC_A10 0x068 -#define GPMC_A11 0x06C -#define GPMC_A12 0x070 -#define GPMC_A13 0x074 -#define GPMC_A14 0x078 -#define GPMC_A15 0x07C -#define GPMC_A16 0x080 -#define GPMC_A17 0x084 -#define GPMC_A18 0x088 -#define GPMC_A19 0x08C -#define GPMC_A20 0x090 -#define GPMC_A21 0x094 -#define GPMC_A22 0x098 -#define GPMC_A23 0x09C -#define GPMC_A24 0x0A0 -#define GPMC_A25 0x0A4 -#define GPMC_A26 0x0A8 -#define GPMC_A27 0x0AC -#define GPMC_CS1 0x0B0 -#define GPMC_CS0 0x0B4 -#define GPMC_CS2 0x0B8 -#define GPMC_CS3 0x0BC -#define GPMC_CLK 0x0C0 -#define GPMC_ADVN_ALE 0x0C4 -#define GPMC_OEN_REN 0x0C8 -#define GPMC_WEN 0x0CC -#define GPMC_BEN0 0x0D0 -#define GPMC_BEN1 0x0D4 -#define GPMC_WAIT0 0x0D8 -#define VIN1A_CLK0 0x0DC -#define VIN1B_CLK1 0x0E0 -#define VIN1A_DE0 0x0E4 -#define VIN1A_FLD0 0x0E8 -#define VIN1A_HSYNC0 0x0EC -#define VIN1A_VSYNC0 0x0F0 -#define VIN1A_D0 0x0F4 -#define VIN1A_D1 0x0F8 -#define VIN1A_D2 0x0FC -#define VIN1A_D3 0x100 -#define VIN1A_D4 0x104 -#define VIN1A_D5 0x108 -#define VIN1A_D6 0x10C -#define VIN1A_D7 0x110 -#define VIN1A_D8 0x114 -#define VIN1A_D9 0x118 -#define VIN1A_D10 0x11C -#define VIN1A_D11 0x120 -#define VIN1A_D12 0x124 -#define VIN1A_D13 0x128 -#define VIN1A_D14 0x12C -#define VIN1A_D15 0x130 -#define VIN1A_D16 0x134 -#define VIN1A_D17 0x138 -#define VIN1A_D18 0x13C -#define VIN1A_D19 0x140 -#define VIN1A_D20 0x144 -#define VIN1A_D21 0x148 -#define VIN1A_D22 0x14C -#define VIN1A_D23 0x150 -#define VIN2A_CLK0 0x154 -#define VIN2A_DE0 0x158 -#define VIN2A_FLD0 0x15C -#define VIN2A_HSYNC0 0x160 -#define VIN2A_VSYNC0 0x164 -#define VIN2A_D0 0x168 -#define VIN2A_D1 0x16C -#define VIN2A_D2 0x170 -#define VIN2A_D3 0x174 -#define VIN2A_D4 0x178 -#define VIN2A_D5 0x17C -#define VIN2A_D6 0x180 -#define VIN2A_D7 0x184 -#define VIN2A_D8 0x188 -#define VIN2A_D9 0x18C -#define VIN2A_D10 0x190 -#define VIN2A_D11 0x194 -#define VIN2A_D12 0x198 -#define VIN2A_D13 0x19C -#define VIN2A_D14 0x1A0 -#define VIN2A_D15 0x1A4 -#define VIN2A_D16 0x1A8 -#define VIN2A_D17 0x1AC -#define VIN2A_D18 0x1B0 -#define VIN2A_D19 0x1B4 -#define VIN2A_D20 0x1B8 -#define VIN2A_D21 0x1BC -#define VIN2A_D22 0x1C0 -#define VIN2A_D23 0x1C4 -#define VOUT1_CLK 0x1C8 -#define VOUT1_DE 0x1CC -#define VOUT1_FLD 0x1D0 -#define VOUT1_HSYNC 0x1D4 -#define VOUT1_VSYNC 0x1D8 -#define VOUT1_D0 0x1DC -#define VOUT1_D1 0x1E0 -#define VOUT1_D2 0x1E4 -#define VOUT1_D3 0x1E8 -#define VOUT1_D4 0x1EC -#define VOUT1_D5 0x1F0 -#define VOUT1_D6 0x1F4 -#define VOUT1_D7 0x1F8 -#define VOUT1_D8 0x1FC -#define VOUT1_D9 0x200 -#define VOUT1_D10 0x204 -#define VOUT1_D11 0x208 -#define VOUT1_D12 0x20C -#define VOUT1_D13 0x210 -#define VOUT1_D14 0x214 -#define VOUT1_D15 0x218 -#define VOUT1_D16 0x21C -#define VOUT1_D17 0x220 -#define VOUT1_D18 0x224 -#define VOUT1_D19 0x228 -#define VOUT1_D20 0x22C -#define VOUT1_D21 0x230 -#define VOUT1_D22 0x234 -#define VOUT1_D23 0x238 -#define MDIO_MCLK 0x23C -#define MDIO_D 0x240 -#define RMII_MHZ_50_CLK 0x244 -#define UART3_RXD 0x248 -#define UART3_TXD 0x24C -#define RGMII0_TXC 0x250 -#define RGMII0_TXCTL 0x254 -#define RGMII0_TXD3 0x258 -#define RGMII0_TXD2 0x25C -#define RGMII0_TXD1 0x260 -#define RGMII0_TXD0 0x264 -#define RGMII0_RXC 0x268 -#define RGMII0_RXCTL 0x26C -#define RGMII0_RXD3 0x270 -#define RGMII0_RXD2 0x274 -#define RGMII0_RXD1 0x278 -#define RGMII0_RXD0 0x27C -#define USB1_DRVVBUS 0x280 -#define USB2_DRVVBUS 0x284 -#define GPIO6_14 0x288 -#define GPIO6_15 0x28C -#define GPIO6_16 0x290 -#define XREF_CLK0 0x294 -#define XREF_CLK1 0x298 -#define XREF_CLK2 0x29C -#define XREF_CLK3 0x2A0 -#define MCASP1_ACLKX 0x2A4 -#define MCASP1_FSX 0x2A8 -#define MCASP1_ACLKR 0x2AC -#define MCASP1_FSR 0x2B0 -#define MCASP1_AXR0 0x2B4 -#define MCASP1_AXR1 0x2B8 -#define MCASP1_AXR2 0x2BC -#define MCASP1_AXR3 0x2C0 -#define MCASP1_AXR4 0x2C4 -#define MCASP1_AXR5 0x2C8 -#define MCASP1_AXR6 0x2CC -#define MCASP1_AXR7 0x2D0 -#define MCASP1_AXR8 0x2D4 -#define MCASP1_AXR9 0x2D8 -#define MCASP1_AXR10 0x2DC -#define MCASP1_AXR11 0x2E0 -#define MCASP1_AXR12 0x2E4 -#define MCASP1_AXR13 0x2E8 -#define MCASP1_AXR14 0x2EC -#define MCASP1_AXR15 0x2F0 -#define MCASP2_ACLKX 0x2F4 -#define MCASP2_FSX 0x2F8 -#define MCASP2_ACLKR 0x2FC -#define MCASP2_FSR 0x300 -#define MCASP2_AXR0 0x304 -#define MCASP2_AXR1 0x308 -#define MCASP2_AXR2 0x30C -#define MCASP2_AXR3 0x310 -#define MCASP2_AXR4 0x314 -#define MCASP2_AXR5 0x318 -#define MCASP2_AXR6 0x31C -#define MCASP2_AXR7 0x320 -#define MCASP3_ACLKX 0x324 -#define MCASP3_FSX 0x328 -#define MCASP3_AXR0 0x32C -#define MCASP3_AXR1 0x330 -#define MCASP4_ACLKX 0x334 -#define MCASP4_FSX 0x338 -#define MCASP4_AXR0 0x33C -#define MCASP4_AXR1 0x340 -#define MCASP5_ACLKX 0x344 -#define MCASP5_FSX 0x348 -#define MCASP5_AXR0 0x34C -#define MCASP5_AXR1 0x350 -#define MMC1_CLK 0x354 -#define MMC1_CMD 0x358 -#define MMC1_DAT0 0x35C -#define MMC1_DAT1 0x360 -#define MMC1_DAT2 0x364 -#define MMC1_DAT3 0x368 -#define MMC1_SDCD 0x36C -#define MMC1_SDWP 0x370 -#define GPIO6_10 0x374 -#define GPIO6_11 0x378 -#define MMC3_CLK 0x37C -#define MMC3_CMD 0x380 -#define MMC3_DAT0 0x384 -#define MMC3_DAT1 0x388 -#define MMC3_DAT2 0x38C -#define MMC3_DAT3 0x390 -#define MMC3_DAT4 0x394 -#define MMC3_DAT5 0x398 -#define MMC3_DAT6 0x39C -#define MMC3_DAT7 0x3A0 -#define SPI1_SCLK 0x3A4 -#define SPI1_D1 0x3A8 -#define SPI1_D0 0x3AC -#define SPI1_CS0 0x3B0 -#define SPI1_CS1 0x3B4 -#define SPI1_CS2 0x3B8 -#define SPI1_CS3 0x3BC -#define SPI2_SCLK 0x3C0 -#define SPI2_D1 0x3C4 -#define SPI2_D0 0x3C8 -#define SPI2_CS0 0x3CC -#define DCAN1_TX 0x3D0 -#define DCAN1_RX 0x3D4 -#define DCAN2_TX 0x3D8 -#define DCAN2_RX 0x3DC -#define UART1_RXD 0x3E0 -#define UART1_TXD 0x3E4 -#define UART1_CTSN 0x3E8 -#define UART1_RTSN 0x3EC -#define UART2_RXD 0x3F0 -#define UART2_TXD 0x3F4 -#define UART2_CTSN 0x3F8 -#define UART2_RTSN 0x3FC -#define I2C1_SDA 0x400 -#define I2C1_SCL 0x404 -#define I2C2_SDA 0x408 -#define I2C2_SCL 0x40C -#define I2C3_SDA 0x410 -#define I2C3_SCL 0x414 -#define WAKEUP0 0x418 -#define WAKEUP1 0x41C -#define WAKEUP2 0x420 -#define WAKEUP3 0x424 -#define ON_OFF 0x428 -#define RTC_PORZ 0x42C -#define TMS 0x430 -#define TDI 0x434 -#define TDO 0x438 -#define TCLK 0x43C -#define TRSTN 0x440 -#define RTCK 0x444 -#define EMU0 0x448 -#define EMU1 0x44C -#define EMU2 0x450 -#define EMU3 0x454 -#define EMU4 0x458 -#define RESETN 0x45C -#define NMIN_DSP 0x460 -#define RSTOUTN 0x464 - -#define MCAN_SEL_ALT_MASK 0x6000 -#define MCAN_SEL 0x2000 - -#endif /* _MUX_DRA7XX_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h deleted file mode 100644 index 2460646..0000000 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ /dev/null @@ -1,317 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff <r-woodruff2@ti.com> - * Aneesh V <aneesh@ti.com> - * Balaji Krishnamoorthy <balajitk@ti.com> - */ -#ifndef _MUX_OMAP5_H_ -#define _MUX_OMAP5_H_ - -#include <asm/types.h> - -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define EMMC_CLK 0x0040 -#define EMMC_CMD 0x0042 -#define EMMC_DATA0 0x0044 -#define EMMC_DATA1 0x0046 -#define EMMC_DATA2 0x0048 -#define EMMC_DATA3 0x004a -#define EMMC_DATA4 0x004c -#define EMMC_DATA5 0x004e -#define EMMC_DATA6 0x0050 -#define EMMC_DATA7 0x0052 -#define C2C_CLKOUT0 0x0054 -#define C2C_CLKOUT1 0x0056 -#define C2C_CLKIN0 0x0058 -#define C2C_CLKIN1 0x005a -#define C2C_DATAIN0 0x005c -#define C2C_DATAIN1 0x005e -#define C2C_DATAIN2 0x0060 -#define C2C_DATAIN3 0x0062 -#define C2C_DATAIN4 0x0064 -#define C2C_DATAIN5 0x0066 -#define C2C_DATAIN6 0x0068 -#define C2C_DATAIN7 0x006a -#define C2C_DATAOUT0 0x006c -#define C2C_DATAOUT1 0x006e -#define C2C_DATAOUT2 0x0070 -#define C2C_DATAOUT3 0x0072 -#define C2C_DATAOUT4 0x0074 -#define C2C_DATAOUT5 0x0076 -#define C2C_DATAOUT6 0x0078 -#define C2C_DATAOUT7 0x007a -#define C2C_DATA8 0x007c -#define C2C_DATA9 0x007e -#define C2C_DATA10 0x0080 -#define C2C_DATA11 0x0082 -#define C2C_DATA12 0x0084 -#define C2C_DATA13 0x0086 -#define C2C_DATA14 0x0088 -#define C2C_DATA15 0x008a -#define LLIA_WAKEREQOUT 0x008c -#define LLIB_WAKEREQOUT 0x008e -#define HSI1_ACREADY 0x0090 -#define HSI1_CAREADY 0x0092 -#define HSI1_ACWAKE 0x0094 -#define HSI1_CAWAKE 0x0096 -#define HSI1_ACFLAG 0x0098 -#define HSI1_ACDATA 0x009a -#define HSI1_CAFLAG 0x009c -#define HSI1_CADATA 0x009e -#define UART1_TX 0x00a0 -#define UART1_CTS 0x00a2 -#define UART1_RX 0x00a4 -#define UART1_RTS 0x00a6 -#define HSI2_CAREADY 0x00a8 -#define HSI2_ACREADY 0x00aa -#define HSI2_CAWAKE 0x00ac -#define HSI2_ACWAKE 0x00ae -#define HSI2_CAFLAG 0x00b0 -#define HSI2_CADATA 0x00b2 -#define HSI2_ACFLAG 0x00b4 -#define HSI2_ACDATA 0x00b6 -#define UART2_RTS 0x00b8 -#define UART2_CTS 0x00ba -#define UART2_RX 0x00bc -#define UART2_TX 0x00be -#define USBB1_HSIC_STROBE 0x00c0 -#define USBB1_HSIC_DATA 0x00c2 -#define USBB2_HSIC_STROBE 0x00c4 -#define USBB2_HSIC_DATA 0x00c6 -#define TIMER10_PWM_EVT 0x00c8 -#define DSIPORTA_TE0 0x00ca -#define DSIPORTA_LANE0X 0x00cc -#define DSIPORTA_LANE0Y 0x00ce -#define DSIPORTA_LANE1X 0x00d0 -#define DSIPORTA_LANE1Y 0x00d2 -#define DSIPORTA_LANE2X 0x00d4 -#define DSIPORTA_LANE2Y 0x00d6 -#define DSIPORTA_LANE3X 0x00d8 -#define DSIPORTA_LANE3Y 0x00da -#define DSIPORTA_LANE4X 0x00dc -#define DSIPORTA_LANE4Y 0x00de -#define DSIPORTC_LANE0X 0x00e0 -#define DSIPORTC_LANE0Y 0x00e2 -#define DSIPORTC_LANE1X 0x00e4 -#define DSIPORTC_LANE1Y 0x00e6 -#define DSIPORTC_LANE2X 0x00e8 -#define DSIPORTC_LANE2Y 0x00ea -#define DSIPORTC_LANE3X 0x00ec -#define DSIPORTC_LANE3Y 0x00ee -#define DSIPORTC_LANE4X 0x00f0 -#define DSIPORTC_LANE4Y 0x00f2 -#define DSIPORTC_TE0 0x00f4 -#define TIMER9_PWM_EVT 0x00f6 -#define I2C4_SCL 0x00f8 -#define I2C4_SDA 0x00fa -#define MCSPI2_CLK 0x00fc -#define MCSPI2_SIMO 0x00fe -#define MCSPI2_SOMI 0x0100 -#define MCSPI2_CS0 0x0102 -#define RFBI_DATA15 0x0104 -#define RFBI_DATA14 0x0106 -#define RFBI_DATA13 0x0108 -#define RFBI_DATA12 0x010a -#define RFBI_DATA11 0x010c -#define RFBI_DATA10 0x010e -#define RFBI_DATA9 0x0110 -#define RFBI_DATA8 0x0112 -#define RFBI_DATA7 0x0114 -#define RFBI_DATA6 0x0116 -#define RFBI_DATA5 0x0118 -#define RFBI_DATA4 0x011a -#define RFBI_DATA3 0x011c -#define RFBI_DATA2 0x011e -#define RFBI_DATA1 0x0120 -#define RFBI_DATA0 0x0122 -#define RFBI_WE 0x0124 -#define RFBI_CS0 0x0126 -#define RFBI_A0 0x0128 -#define RFBI_RE 0x012a -#define RFBI_HSYNC0 0x012c -#define RFBI_TE_VSYNC0 0x012e -#define GPIO6_182 0x0130 -#define GPIO6_183 0x0132 -#define GPIO6_184 0x0134 -#define GPIO6_185 0x0136 -#define GPIO6_186 0x0138 -#define GPIO6_187 0x013a -#define HDMI_CEC 0x013c -#define HDMI_HPD 0x013e -#define HDMI_DDC_SCL 0x0140 -#define HDMI_DDC_SDA 0x0142 -#define CSIPORTC_LANE0X 0x0144 -#define CSIPORTC_LANE0Y 0x0146 -#define CSIPORTC_LANE1X 0x0148 -#define CSIPORTC_LANE1Y 0x014a -#define CSIPORTB_LANE0X 0x014c -#define CSIPORTB_LANE0Y 0x014e -#define CSIPORTB_LANE1X 0x0150 -#define CSIPORTB_LANE1Y 0x0152 -#define CSIPORTB_LANE2X 0x0154 -#define CSIPORTB_LANE2Y 0x0156 -#define CSIPORTA_LANE0X 0x0158 -#define CSIPORTA_LANE0Y 0x015a -#define CSIPORTA_LANE1X 0x015c -#define CSIPORTA_LANE1Y 0x015e -#define CSIPORTA_LANE2X 0x0160 -#define CSIPORTA_LANE2Y 0x0162 -#define CSIPORTA_LANE3X 0x0164 -#define CSIPORTA_LANE3Y 0x0166 -#define CSIPORTA_LANE4X 0x0168 -#define CSIPORTA_LANE4Y 0x016a -#define CAM_SHUTTER 0x016c -#define CAM_STROBE 0x016e -#define CAM_GLOBALRESET 0x0170 -#define TIMER11_PWM_EVT 0x0172 -#define TIMER5_PWM_EVT 0x0174 -#define TIMER6_PWM_EVT 0x0176 -#define TIMER8_PWM_EVT 0x0178 -#define I2C3_SCL 0x017a -#define I2C3_SDA 0x017c -#define GPIO8_233 0x017e -#define GPIO8_234 0x0180 -#define ABE_CLKS 0x0182 -#define ABEDMIC_DIN1 0x0184 -#define ABEDMIC_DIN2 0x0186 -#define ABEDMIC_DIN3 0x0188 -#define ABEDMIC_CLK1 0x018a -#define ABEDMIC_CLK2 0x018c -#define ABEDMIC_CLK3 0x018e -#define ABESLIMBUS1_CLOCK 0x0190 -#define ABESLIMBUS1_DATA 0x0192 -#define ABEMCBSP2_DR 0x0194 -#define ABEMCBSP2_DX 0x0196 -#define ABEMCBSP2_FSX 0x0198 -#define ABEMCBSP2_CLKX 0x019a -#define ABEMCPDM_UL_DATA 0x019c -#define ABEMCPDM_DL_DATA 0x019e -#define ABEMCPDM_FRAME 0x01a0 -#define ABEMCPDM_LB_CLK 0x01a2 -#define WLSDIO_CLK 0x01a4 -#define WLSDIO_CMD 0x01a6 -#define WLSDIO_DATA0 0x01a8 -#define WLSDIO_DATA1 0x01aa -#define WLSDIO_DATA2 0x01ac -#define WLSDIO_DATA3 0x01ae -#define UART5_RX 0x01b0 -#define UART5_TX 0x01b2 -#define UART5_CTS 0x01b4 -#define UART5_RTS 0x01b6 -#define I2C2_SCL 0x01b8 -#define I2C2_SDA 0x01ba -#define MCSPI1_CLK 0x01bc -#define MCSPI1_SOMI 0x01be -#define MCSPI1_SIMO 0x01c0 -#define MCSPI1_CS0 0x01c2 -#define MCSPI1_CS1 0x01c4 -#define I2C5_SCL 0x01c6 -#define I2C5_SDA 0x01c8 -#define PERSLIMBUS2_CLOCK 0x01ca -#define PERSLIMBUS2_DATA 0x01cc -#define UART6_TX 0x01ce -#define UART6_RX 0x01d0 -#define UART6_CTS 0x01d2 -#define UART6_RTS 0x01d4 -#define UART3_CTS_RCTX 0x01d6 -#define UART3_RTS_IRSD 0x01d8 -#define UART3_TX_IRTX 0x01da -#define UART3_RX_IRRX 0x01dc -#define USBB3_HSIC_STROBE 0x01de -#define USBB3_HSIC_DATA 0x01e0 -#define SDCARD_CLK 0x01e2 -#define SDCARD_CMD 0x01e4 -#define SDCARD_DATA2 0x01e6 -#define SDCARD_DATA3 0x01e8 -#define SDCARD_DATA0 0x01ea -#define SDCARD_DATA1 0x01ec -#define USBD0_HS_DP 0x01ee -#define USBD0_HS_DM 0x01f0 -#define I2C1_PMIC_SCL 0x01f2 -#define I2C1_PMIC_SDA 0x01f4 -#define USBD0_SS_RX 0x01f6 - -#define LLIA_WAKEREQIN 0x0040 -#define LLIB_WAKEREQIN 0x0042 -#define DRM_EMU0 0x0044 -#define DRM_EMU1 0x0046 -#define JTAG_NTRST 0x0048 -#define JTAG_TCK 0x004a -#define JTAG_RTCK 0x004c -#define JTAG_TMSC 0x004e -#define JTAG_TDI 0x0050 -#define JTAG_TDO 0x0052 -#define SYS_32K 0x0054 -#define FREF_CLK_IOREQ 0x0056 -#define FREF_CLK0_OUT 0x0058 -#define FREF_CLK1_OUT 0x005a -#define FREF_CLK2_OUT 0x005c -#define FREF_CLK2_REQ 0x005e -#define FREF_CLK1_REQ 0x0060 -#define SYS_NRESPWRON 0x0062 -#define SYS_NRESWARM 0x0064 -#define SYS_PWR_REQ 0x0066 -#define SYS_NIRQ1 0x0068 -#define SYS_NIRQ2 0x006a -#define SR_PMIC_SCL 0x006c -#define SR_PMIC_SDA 0x006e -#define SYS_BOOT0 0x0070 -#define SYS_BOOT1 0x0072 -#define SYS_BOOT2 0x0074 -#define SYS_BOOT3 0x0076 -#define SYS_BOOT4 0x0078 -#define SYS_BOOT5 0x007a - -#endif /* _MUX_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h deleted file mode 100644 index a9c0421..0000000 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ /dev/null @@ -1,271 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Authors: - * Aneesh V <aneesh@ti.com> - * Sricharan R <r.sricharan@ti.com> - */ - -#ifndef _OMAP5_H_ -#define _OMAP5_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <linux/sizes.h> - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP54XX_L4_CORE_BASE 0x4A000000 -#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 -#define OMAP54XX_L4_PER_BASE 0x48000000 - -/* CONTROL ID CODE */ -#define CONTROL_CORE_ID_CODE 0x4A002204 -#define CONTROL_WKUP_ID_CODE 0x4AE0C204 - -#if defined(CONFIG_DRA7XX) -#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE -#else -#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE -#endif - -#if defined(CONFIG_DRA7XX) -#define DRA7_USB_OTG_SS1_BASE 0x48890000 -#define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 -#define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 -#define DRA7_USB3_PHY1_POWER 0x4A002370 -#define DRA7_USB2_PHY1_POWER 0x4A002300 - -#define DRA7_USB_OTG_SS2_BASE 0x488D0000 -#define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 -#define DRA7_USB2_PHY2_POWER 0x4A002E74 -#else -#define OMAP5XX_USB_OTG_SS_BASE 0x4A030000 -#define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000 -#define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00 -#define OMAP5XX_USB3_PHY_POWER 0x4A002370 -#define OMAP5XX_USB2_PHY_POWER 0x4A002300 -#endif - -/* To be verified */ -#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F -#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F -#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F -#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F -#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F -#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F -#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F -#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F -#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F -#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F -#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F - -#define DRA762_ABZ_PACKAGE 0x2 -#define DRA762_ACD_PACKAGE 0x3 - -/* UART */ -#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) -#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) -#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) -#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) - -/* General Purpose Timers */ -#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) -#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) -#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) - -/* Watchdog Timer2 - MPU watchdog */ -#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) - -/* QSPI */ -#define QSPI_BASE 0x4B300000 - -/* SATA */ -#define DWC_AHSATA_BASE 0x4A140000 - -/* - * Hardware Register Details - */ - -/* Watchdog Timer */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* GP Timer */ -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* Control Module */ -#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) -#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f -#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 -#define CONTROL_EFUSE_2_OVERRIDE 0x00084000 - -/* LPDDR2 IO regs */ -#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C -#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E -#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C -#define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 - -/* CONTROL_EFUSE_2 */ -#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 - -#define SDCARD_BIAS_PWRDNZ (1 << 27) -#define SDCARD_PWRDNZ (1 << 26) -#define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_PBIASLITE_VMODE (1 << 21) - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#define DEVICE_TYPE_SHIFT 0x6 -#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) - -/* Output impedance control */ -#define ds_120_ohm 0x0 -#define ds_60_ohm 0x1 -#define ds_45_ohm 0x2 -#define ds_30_ohm 0x3 -#define ds_mask 0x3 - -/* Slew rate control */ -#define sc_slow 0x0 -#define sc_medium 0x1 -#define sc_fast 0x2 -#define sc_na 0x3 -#define sc_mask 0x3 - -/* Target capacitance control */ -#define lb_5_12_pf 0x0 -#define lb_12_25_pf 0x1 -#define lb_25_50_pf 0x2 -#define lb_50_80_pf 0x3 -#define lb_mask 0x3 - -#define usb_i_mask 0x7 - -#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 -#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 -#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 -#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 -#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 - -#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 -#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC -#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 - -#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 -#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC -#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 - -#define EFUSE_1 0x45145100 -#define EFUSE_2 0x45145100 -#define EFUSE_3 0x45145100 -#define EFUSE_4 0x45145100 -#endif /* __ASSEMBLY__ */ - -/* - * In all cases, the TRM defines the RAM Memory Map for the processor - * and indicates the area for the downloaded image. We use all of that - * space for download and once up and running may use other parts of the - * map for our needs. We set a scratch space that is at the end of the - * OMAP5 download area, but within the DRA7xx download area (as it is - * much larger) and do not, at this time, make use of the additional - * space. - */ -#if defined(CONFIG_DRA7XX) -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ -#define NON_SECURE_SRAM_IMG_END 0x4037C000 -#else -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ -#define NON_SECURE_SRAM_IMG_END 0x4031E000 -#endif -#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_ROM_VECT_BASE 0x4031F000 - -/* CONTROL_SRCOMP_XXX_SIDE */ -#define OVERRIDE_XS_SHIFT 30 -#define OVERRIDE_XS_MASK (1 << 30) -#define SRCODE_READ_XS_SHIFT 12 -#define SRCODE_READ_XS_MASK (0xff << 12) -#define PWRDWN_XS_SHIFT 11 -#define PWRDWN_XS_MASK (1 << 11) -#define DIVIDE_FACTOR_XS_SHIFT 4 -#define DIVIDE_FACTOR_XS_MASK (0x7f << 4) -#define MULTIPLY_FACTOR_XS_SHIFT 1 -#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) -#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 -#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) - -/* ABB settings */ -#define OMAP_ABB_SETTLING_TIME 50 -#define OMAP_ABB_CLOCK_CYCLES 16 - -/* ABB tranxdone mask */ -#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) -#define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) -#define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) -#define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) -#define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) - -/* ABB efuse masks */ -#define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) -#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) -#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) -#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) -#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) -#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) - -#ifndef __ASSEMBLY__ -struct srcomp_params { - s8 divide_factor; - s8 multiply_factor; -}; - -struct ctrl_ioregs { - u32 ctrl_ddrch; - u32 ctrl_lpddr2ch; - u32 ctrl_ddr3ch; - u32 ctrl_ddrio_0; - u32 ctrl_ddrio_1; - u32 ctrl_ddrio_2; - u32 ctrl_emif_sdram_config_ext; - u32 ctrl_emif_sdram_config_ext_final; - u32 ctrl_ddr_ctrl_ext_0; -}; - -void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); - -#endif /* __ASSEMBLY__ */ - -/* Boot parameters */ -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - unsigned int boot_message; - unsigned int boot_device_descriptor; - unsigned char boot_device; - unsigned char reset_reason; - unsigned char ch_flags; -}; -#endif - -#endif diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h deleted file mode 100644 index 96c84fc..0000000 --- a/arch/arm/include/asm/arch-omap5/sata.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SATA Wrapper Register map - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - */ - -#ifndef _TI_SATA_H -#define _TI_SATA_H - -/* SATA Wrapper module */ -#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100) -/* SATA PHY Module */ -#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800) - -/* SATA Wrapper register offsets */ -#define TI_SATA_SYSCONFIG 0x00 -#define TI_SATA_CDRLOCK 0x04 - -/* Register Set */ -#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) -#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) -#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) - -/* Standby modes */ -#define TI_SATA_STANDBY_FORCE 0x0 -#define TI_SATA_STANDBY_NO (0x1 << 4) -#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4) -#define TI_SATA_STANDBY_SMART (0x2 << 4) - -/* Idle modes */ -#define TI_SATA_IDLE_FORCE 0x0 -#define TI_SATA_IDLE_NO (0x1 << 2) -#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) -#define TI_SATA_IDLE_SMART (0x2 << 2) - -#endif /* _TI_SATA_H */ diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h deleted file mode 100644 index cda3b46..0000000 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0x00 -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x03 -#define BOOT_DEVICE_ONENAND 0x04 -#define BOOT_DEVICE_MMC1 0x05 -#define BOOT_DEVICE_MMC2 0x06 -#define BOOT_DEVICE_MMC2_2 0x07 -#define BOOT_DEVICE_SATA 0x09 -#define BOOT_DEVICE_SPI 0x0A -#define BOOT_DEVICE_QSPI_1 0x0A -#define BOOT_DEVICE_QSPI_4 0x0B -#define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_DFU 0x45 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 -#endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h deleted file mode 100644 index 80b0c93..0000000 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <asm/arch/omap.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/omap_common.h> -#include <linux/mtd/omap_gpmc.h> -#include <asm/arch/clock.h> -#include <asm/ti-common/sys_proto.h> - -/* - * Structure for Iodelay configuration registers. - * Theoretical max for g_delay is 21560 ps. - * Theoretical max for a_delay is 1/3rd of g_delay max. - * So using u16 for both a/g_delay. - */ -struct iodelay_cfg_entry { - u16 offset; - u16 a_delay; - u16 g_delay; -}; - -struct pad_conf_entry { - u32 offset; - u32 val; -}; - -struct mmc_platform_fixups { - const char *hw_rev; - u32 unsupported_caps; - u32 max_freq; -}; - -struct omap_sysinfo { - char *board_string; -}; -extern const struct omap_sysinfo sysinfo; - -void gpmc_init(void); -void watchdog_init(void); -u32 get_device_type(void); -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); -void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size); -void set_muxconf_regs(void); -u32 wait_on_value(u32, u32, void *, u32); -void sdelay(unsigned long); -void setup_early_clocks(void); -void prcm_init(void); -void do_board_detect(void); -void vcores_init(void); -void bypass_dpll(u32 const base); -void freq_update_core(void); -u32 get_sys_clk_freq(void); -u32 omap5_ddr_clk(void); -void cancel_out(u32 *num, u32 *den, u32 den_limit); -void sdram_init(void); -u32 omap_sdram_size(void); -u32 cortex_rev(void); -void save_omap_boot_params(void); -void init_omap_revision(void); -void init_package_revision(void); -void do_io_settings(void); -void sri2c_init(void); -int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); -u32 warm_reset(void); -void force_emif_self_refresh(void); -void get_ioregs(const struct ctrl_ioregs **regs); -void srcomp_enable(void); -void setup_warmreset_time(void); -const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr); - -static inline u32 div_round_up(u32 num, u32 den) -{ - return (num + den - 1)/den; -} - -static inline u32 usec_to_32k(u32 usec) -{ - return div_round_up(32768 * usec, 1000000); -} - -#define OMAP5_SERVICE_L2ACTLR_SET 0x104 -#define OMAP5_SERVICE_ACR_SET 0x107 - -#endif diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h deleted file mode 100644 index dc0a9b9..0000000 --- a/arch/arm/include/asm/arch-orion5x/spl.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net> - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NOR 1 diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h deleted file mode 100644 index 88e88f7..0000000 --- a/arch/arm/include/asm/arch-owl/clk_s900.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Actions Semi S900 Clock Definitions - * - * Copyright (C) 2015 Actions Semi Co., Ltd. - * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - * - */ - -#ifndef _OWL_CLK_S900_H_ -#define _OWL_CLK_S900_H_ - -#include <clk-uclass.h> - -struct owl_clk_priv { - phys_addr_t base; -}; - -/* BUSCLK register definitions */ -#define CMU_PDBGDIV_8 7 -#define CMU_PDBGDIV_SHIFT 26 -#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) -#define CMU_PERDIV_8 7 -#define CMU_PERDIV_SHIFT 20 -#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) -#define CMU_NOCDIV_2 1 -#define CMU_NOCDIV_SHIFT 19 -#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) -#define CMU_DMMCLK_SRC_APLL 2 -#define CMU_DMMCLK_SRC_SHIFT 10 -#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) -#define CMU_APBCLK_DIV BIT(8) -#define CMU_NOCCLK_SRC BIT(7) -#define CMU_AHBCLK_DIV BIT(4) -#define CMU_CORECLK_MASK 3 -#define CMU_CORECLK_CPLL BIT(1) -#define CMU_CORECLK_HOSC BIT(0) - -/* COREPLL register definitions */ -#define CMU_COREPLL_EN BIT(9) -#define CMU_COREPLL_HOSC_EN BIT(8) -#define CMU_COREPLL_OUT (1104 / 24) - -/* DEVPLL register definitions */ -#define CMU_DEVPLL_CLK BIT(12) -#define CMU_DEVPLL_EN BIT(8) -#define CMU_DEVPLL_OUT (660 / 6) - -/* UARTCLK register definitions */ -#define CMU_UARTCLK_SRC_DEVPLL BIT(16) - -/* DEVCLKEN1 register definitions */ -#define CMU_DEVCLKEN1_UART5 BIT(21) - -#define PLL_STABILITY_WAIT_US 50 - -#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s900.h b/arch/arm/include/asm/arch-owl/regs_s900.h deleted file mode 100644 index 9e9106d..0000000 --- a/arch/arm/include/asm/arch-owl/regs_s900.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Actions Semi S900 Register Definitions - * - * Copyright (C) 2015 Actions Semi Co., Ltd. - * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - * - */ - -#ifndef _OWL_REGS_S900_H_ -#define _OWL_REGS_S900_H_ - -/* CMU registers */ -#define CMU_COREPLL (0x0000) -#define CMU_DEVPLL (0x0004) -#define CMU_DDRPLL (0x0008) -#define CMU_NANDPLL (0x000C) -#define CMU_DISPLAYPLL (0x0010) -#define CMU_AUDIOPLL (0x0014) -#define CMU_TVOUTPLL (0x0018) -#define CMU_BUSCLK (0x001C) -#define CMU_SENSORCLK (0x0020) -#define CMU_LCDCLK (0x0024) -#define CMU_DSICLK (0x0028) -#define CMU_CSICLK (0x002C) -#define CMU_DECLK (0x0030) -#define CMU_BISPCLK (0x0034) -#define CMU_IMXCLK (0x0038) -#define CMU_HDECLK (0x003C) -#define CMU_VDECLK (0x0040) -#define CMU_VCECLK (0x0044) -#define CMU_NANDCCLK (0x004C) -#define CMU_SD0CLK (0x0050) -#define CMU_SD1CLK (0x0054) -#define CMU_SD2CLK (0x0058) -#define CMU_UART0CLK (0x005C) -#define CMU_UART1CLK (0x0060) -#define CMU_UART2CLK (0x0064) -#define CMU_PWM0CLK (0x0070) -#define CMU_PWM1CLK (0x0074) -#define CMU_PWM2CLK (0x0078) -#define CMU_PWM3CLK (0x007C) -#define CMU_USBPLL (0x0080) -#define CMU_ASSISTPLL (0x0084) -#define CMU_EDPCLK (0x0088) -#define CMU_GPU3DCLK (0x0090) -#define CMU_CORECTL (0x009C) -#define CMU_DEVCLKEN0 (0x00A0) -#define CMU_DEVCLKEN1 (0x00A4) -#define CMU_DEVRST0 (0x00A8) -#define CMU_DEVRST1 (0x00AC) -#define CMU_UART3CLK (0x00B0) -#define CMU_UART4CLK (0x00B4) -#define CMU_UART5CLK (0x00B8) -#define CMU_UART6CLK (0x00BC) -#define CMU_TLSCLK (0x00C0) -#define CMU_SD3CLK (0x00C4) -#define CMU_PWM4CLK (0x00C8) -#define CMU_PWM5CLK (0x00CC) -#define CMU_ANALOGDEBUG (0x00D4) -#define CMU_TVOUTPLLDEBUG0 (0x00EC) -#define CMU_TVOUTPLLDEBUG1 (0x00FC) - -#endif diff --git a/arch/arm/include/asm/arch-pxa/bitfield.h b/arch/arm/include/asm/arch-pxa/bitfield.h deleted file mode 100644 index 104a21c..0000000 --- a/arch/arm/include/asm/arch-pxa/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/arch/arm/include/asm/arch-pxa/config.h b/arch/arm/include/asm/arch-pxa/config.h deleted file mode 100644 index 75b0e49..0000000 --- a/arch/arm/include/asm/arch-pxa/config.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Andrew Ruder <andrew.ruder@elecsyscorp.com> - */ - -#ifndef _ASM_ARM_PXA_CONFIG_ -#define _ASM_ARM_PXA_CONFIG_ - -#include <asm/arch/pxa-regs.h> - -/* - * Generic timer support - */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define CONFIG_SYS_TIMER_RATE 3250000 -#elif defined(CONFIG_CPU_PXA25X) -#define CONFIG_SYS_TIMER_RATE 3686400 -#else -#error "Timer frequency unknown - please config PXA CPU type" -#endif - -#define CONFIG_SYS_TIMER_COUNTER OSCR - -#endif /* _ASM_ARM_PXA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h deleted file mode 100644 index 6d0023d..0000000 --- a/arch/arm/include/asm/arch-pxa/hardware.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/hardware.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: This file was taken from linux-2.4.19-rmk4-pxa1 - * - * - 2003/01/20 implementation specifics activated - * Robert Schwebel <r.schwebel@pengutronix.de> - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/mach-types.h> - -/* - * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. - * PXA300/310/320 all have distinct register mappings in some cases, that's why - * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common - * drivers and compatibility glue with old source then. - */ -#ifndef CONFIG_CPU_MONAHANS -#if defined(CONFIG_CPU_PXA300) || \ - defined(CONFIG_CPU_PXA310) || \ - defined(CONFIG_CPU_PXA320) -#define CONFIG_CPU_MONAHANS -#endif -#endif - -/* - * These are statically mapped PCMCIA IO space for designs using it as a - * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. - * The actual PCMCIA code is mapping required IO region at run time. - */ -#define PCMCIA_IO_0_BASE 0xf6000000 -#define PCMCIA_IO_1_BASE 0xf7000000 - - -/* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 - -/* - * Workarounds for at least 2 errata so far require this. - * The mapping is set in mach-pxa/generic.c. - */ -#define UNCACHED_PHYS_0 0xff000000 -#define UNCACHED_ADDR UNCACHED_PHYS_0 - -/* - * Intel PXA internal I/O mappings: - * - * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff - * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff - * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff - */ - -#include "pxa-regs.h" - -#ifndef __ASSEMBLY__ - -/* - * GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * This must be called *before* the corresponding IRQ is registered. - * Use this instead of directly setting GRER/GFER. - */ -#define GPIO_FALLING_EDGE 1 -#define GPIO_RISING_EDGE 2 -#define GPIO_BOTH_EDGES 3 - -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h deleted file mode 100644 index b81b42c..0000000 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ /dev/null @@ -1,2635 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/pxa-regs.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de - * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions. - * Added include for hardware.h (for __REG definition) - */ -#ifndef _PXA_REGS_H_ -#define _PXA_REGS_H_ - -#include "bitfield.h" -#include "hardware.h" - -/* FIXME hack so that SA-1111.h will work [cb] */ - -#ifndef __ASSEMBLY__ -typedef unsigned short Word16 ; -typedef unsigned int Word32 ; -typedef Word32 Word ; -typedef Word Quad [4] ; -typedef void *Address ; -typedef void (*ExcpHndlr) (void) ; -#endif - -/* - * PXA Chip selects - */ -#ifdef CONFIG_CPU_MONAHANS -#define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */ -#define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */ -#define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */ -#define PXA_CS2_PHYS 0x10000000 /* (64MB) */ -#define PXA_CS3_PHYS 0x14000000 /* (64MB) */ -#define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */ -#else -#define PXA_CS0_PHYS 0x00000000 -#define PXA_CS1_PHYS 0x04000000 -#define PXA_CS2_PHYS 0x08000000 -#define PXA_CS3_PHYS 0x0C000000 -#define PXA_CS4_PHYS 0x10000000 -#define PXA_CS5_PHYS 0x14000000 -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * Personal Computer Memory Card International Association (PCMCIA) sockets - */ -#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ -#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ - -#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ -#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ -#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ -#endif - -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ -#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ -#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ - -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) - -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ - -#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ -#endif - -/* - * DMA Controller - */ -#define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */ -#define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */ -#define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */ -#define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */ -#define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */ -#define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */ -#define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */ -#define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */ -#define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */ -#define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */ -#define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */ -#define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */ -#define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */ -#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ -#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ -#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ -#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ -#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ -#define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */ -#define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */ -#define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */ -#define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */ -#define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */ -#define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */ -#define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */ -#define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */ -#define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */ -#define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */ -#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ -#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ -#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#define DCSR(x) (0x40000000 | ((x) << 2)) - -#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ -#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ -#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ -#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ -#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ -#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ -#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ -#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ -#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ -#endif - -#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ -#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ -#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ -#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ -#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ - -#define DINT 0x400000f0 /* DMA Interrupt Register */ - -#define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */ -#define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */ -#define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */ -#define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */ -#define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */ -#define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ -#define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */ -#define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */ -#define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */ -#define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */ -#define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */ -#define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */ -#define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */ -#define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */ -#define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */ -#define DRCMR15 0x4000013c /* Reserved */ -#define DRCMR16 0x40000140 /* Reserved */ -#define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */ -#define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */ -#define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */ -#define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */ -#define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */ -#define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */ -#define DRCMR23 0x4000015c /* Reserved */ -#define DRCMR24 0x40000160 /* Reserved */ -#define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */ -#define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */ -#define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */ -#define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */ -#define DRCMR29 0x40000174 /* Reserved */ -#define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */ -#define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */ -#define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */ -#define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */ -#define DRCMR34 0x40000188 /* Reserved */ -#define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */ -#define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */ -#define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */ -#define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */ -#define DRCMR39 0x4000019C /* Reserved */ - -#define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */ -#define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */ -#define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */ - -#define DRCMRRXSADR DRCMR2 -#define DRCMRTXSADR DRCMR3 -#define DRCMRRXBTRBR DRCMR4 -#define DRCMRTXBTTHR DRCMR5 -#define DRCMRRXFFRBR DRCMR6 -#define DRCMRTXFFTHR DRCMR7 -#define DRCMRRXMCDR DRCMR8 -#define DRCMRRXMODR DRCMR9 -#define DRCMRTXMODR DRCMR10 -#define DRCMRRXPCDR DRCMR11 -#define DRCMRTXPCDR DRCMR12 -#define DRCMRRXSSDR DRCMR13 -#define DRCMRTXSSDR DRCMR14 -#define DRCMRRXICDR DRCMR17 -#define DRCMRTXICDR DRCMR18 -#define DRCMRRXSTRBR DRCMR19 -#define DRCMRTXSTTHR DRCMR20 -#define DRCMRRXMMC DRCMR21 -#define DRCMRTXMMC DRCMR22 - -#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ -#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */ - -#define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */ -#define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */ -#define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */ -#define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */ -#define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */ -#define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */ -#define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */ -#define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */ -#define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */ -#define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */ -#define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */ -#define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */ -#define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */ -#define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */ -#define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */ -#define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */ -#define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */ -#define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */ -#define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */ -#define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */ -#define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */ -#define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */ -#define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */ -#define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */ -#define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */ -#define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */ -#define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */ -#define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */ -#define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */ -#define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */ -#define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */ -#define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */ -#define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */ -#define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */ -#define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */ -#define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */ -#define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */ -#define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */ -#define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */ -#define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */ -#define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */ -#define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */ -#define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */ -#define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */ -#define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */ -#define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */ -#define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */ -#define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */ -#define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */ -#define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */ -#define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */ -#define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */ -#define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */ -#define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */ -#define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */ -#define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */ -#define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */ -#define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */ -#define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */ -#define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */ -#define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */ -#define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */ -#define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */ -#define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */ - -#define DDADR(x) (0x40000200 | ((x) << 4)) -#define DSADR(x) (0x40000204 | ((x) << 4)) -#define DTADR(x) (0x40000208 | ((x) << 4)) -#define DCMD(x) (0x4000020c | ((x) << 4)) - -#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ -#define DDADR_STOP (1 << 0) /* Stop (read / write) */ - -#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ -#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ -#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ -#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ -#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ -#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ -#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ -#define DCMD_BURST8 (1 << 16) /* 8 byte burst */ -#define DCMD_BURST16 (2 << 16) /* 16 byte burst */ -#define DCMD_BURST32 (3 << 16) /* 32 byte burst */ -#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ -#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ -#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ -#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ - -/* default combinations */ -#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) -#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) -#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) - -/******************************************************************************/ -/* - * IrSR (Infrared Selection Register) - */ -#define IrSR_OFFSET 0x20 - -#define IrSR_RXPL_NEG_IS_ZERO (1<<4) -#define IrSR_RXPL_POS_IS_ZERO 0x0 -#define IrSR_TXPL_NEG_IS_ZERO (1<<3) -#define IrSR_TXPL_POS_IS_ZERO 0x0 -#define IrSR_XMODE_PULSE_1_6 (1<<2) -#define IrSR_XMODE_PULSE_3_16 0x0 -#define IrSR_RCVEIR_IR_MODE (1<<1) -#define IrSR_RCVEIR_UART_MODE 0x0 -#define IrSR_XMITIR_IR_MODE (1<<0) -#define IrSR_XMITIR_UART_MODE 0x0 - -#define IrSR_IR_RECEIVE_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_IR_MODE | \ - IrSR_XMITIR_UART_MODE) - -#define IrSR_IR_TRANSMIT_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_UART_MODE | \ - IrSR_XMITIR_IR_MODE) - -/* - * Serial Audio Controller - */ -/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these - * short defines because there is too much chance of namespace collision - */ -#define SACR0 0x40400000 /* Global Control Register */ -#define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */ -#define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ -#define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */ -#define SAICR 0x40400018 /* Serial Audio Interrupt Clear Register */ -#define SADIV 0x40400060 /* Audio Clock Divider Register. */ -#define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ - -/* - * AC97 Controller registers - */ -#define POCR 0x40500000 /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define PICR 0x40500004 /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define MCCR 0x40500008 /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define GCR 0x4050000C /* Global Control Register */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ - -#define POSR 0x40500010 /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ - -#define PISR 0x40500014 /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ - -#define MCSR 0x40500018 /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ - -#define GSR 0x4050001C /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ - -#define CAR 0x40500020 /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ - -#define PCDR 0x40500040 /* PCM FIFO Data Register */ -#define MCDR 0x40500060 /* Mic-in FIFO Data Register */ - -#define MOCR 0x40500100 /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ - -#define MICR 0x40500108 /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ - -#define MOSR 0x40500110 /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ - -#define MISR 0x40500118 /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ - -#define MODR 0x40500140 /* Modem FIFO Data Register */ - -#define PAC_REG_BASE 0x40500200 /* Primary Audio Codec */ -#define SAC_REG_BASE 0x40500300 /* Secondary Audio Codec */ -#define PMC_REG_BASE 0x40500400 /* Primary Modem Codec */ -#define SMC_REG_BASE 0x40500500 /* Secondary Modem Codec */ - - -/* - * USB Device Controller - */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - -#define UDCCR 0x40600000 /* UDC Control Register */ -#define UDCCR_UDE (1 << 0) /* UDC enable */ -#define UDCCR_UDA (1 << 1) /* UDC active */ -#define UDCCR_RSM (1 << 2) /* Device resume */ -#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ -#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active Configuration */ -#define UDCCR_RESIR (1 << 29) /* Resume interrupt request */ -#define UDCCR_SUSIR (1 << 28) /* Suspend interrupt request */ -#define UDCCR_SM (1 << 28) /* Suspend interrupt mask */ -#define UDCCR_RSTIR (1 << 27) /* Reset interrupt request */ -#define UDCCR_REM (1 << 27) /* Reset interrupt mask */ -#define UDCCR_RM (1 << 29) /* resume interrupt mask */ -#define UDCCR_SRM (UDCCR_SM|UDCCR_RM) -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */ -#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */ -#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */ -#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ -#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ -#define UDCCR_ACN_S 11 -#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ -#define UDCCR_AIN_S 8 -#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */ -#define UDCCR_AAISN_S 5 - -#define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */ -#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ -#define UDCCS0_IPR (1 << 1) /* IN packet ready */ -#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS0_DRWF (1 << 16) /* Device remote wakeup feature */ -#define UDCCS0_SST (1 << 4) /* Sent stall */ -#define UDCCS0_FST (1 << 5) /* Force stall */ -#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ -#define UDCCS0_SA (1 << 7) /* Setup active */ - -/* Bulk IN - Endpoint 1,6,11 */ -#define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */ -#define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */ -#define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */ - -#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_BI_FTF (1 << 8) /* Flush Tx FIFO */ -#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_BI_SST (1 << 4) /* Sent stall */ -#define UDCCS_BI_FST (1 << 5) /* Force stall */ -#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ - -/* Bulk OUT - Endpoint 2,7,12 */ -#define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */ -#define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */ -#define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */ - -#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_BO_DME (1 << 3) /* DMA enable */ -#define UDCCS_BO_SST (1 << 4) /* Sent stall */ -#define UDCCS_BO_FST (1 << 5) /* Force stall */ -#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ - -/* Isochronous IN - Endpoint 3,8,13 */ -#define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */ -#define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */ -#define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */ - -#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ - -/* Isochronous OUT - Endpoint 4,9,14 */ -#define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */ -#define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */ -#define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */ - -#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ -#define UDCCS_IO_DME (1 << 3) /* DMA enable */ -#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ - -/* Interrupt IN - Endpoint 5,10,15 */ -#define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */ -#define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */ -#define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */ - -#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_INT_SST (1 << 4) /* Sent stall */ -#define UDCCS_INT_FST (1 << 5) /* Force stall */ -#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ - -#define UFNRH 0x40600060 /* UDC Frame Number Register High */ -#define UFNRL 0x40600014 /* UDC Frame Number Register Low */ -#define UBCR2 0x40600208 /* UDC Byte Count Reg 2 */ -#define UBCR4 0x4060006c /* UDC Byte Count Reg 4 */ -#define UBCR7 0x40600070 /* UDC Byte Count Reg 7 */ -#define UBCR9 0x40600074 /* UDC Byte Count Reg 9 */ -#define UBCR12 0x40600078 /* UDC Byte Count Reg 12 */ -#define UBCR14 0x4060007c /* UDC Byte Count Reg 14 */ -#define UDDR0 0x40600300 /* UDC Endpoint 0 Data Register */ -#define UDDR1 0x40600304 /* UDC Endpoint 1 Data Register */ -#define UDDR2 0x40600308 /* UDC Endpoint 2 Data Register */ -#define UDDR3 0x40600200 /* UDC Endpoint 3 Data Register */ -#define UDDR4 0x40600400 /* UDC Endpoint 4 Data Register */ -#define UDDR5 0x406000A0 /* UDC Endpoint 5 Data Register */ -#define UDDR6 0x40600600 /* UDC Endpoint 6 Data Register */ -#define UDDR7 0x40600680 /* UDC Endpoint 7 Data Register */ -#define UDDR8 0x40600700 /* UDC Endpoint 8 Data Register */ -#define UDDR9 0x40600900 /* UDC Endpoint 9 Data Register */ -#define UDDR10 0x406000C0 /* UDC Endpoint 10 Data Register */ -#define UDDR11 0x40600B00 /* UDC Endpoint 11 Data Register */ -#define UDDR12 0x40600B80 /* UDC Endpoint 12 Data Register */ -#define UDDR13 0x40600C00 /* UDC Endpoint 13 Data Register */ -#define UDDR14 0x40600E00 /* UDC Endpoint 14 Data Register */ -#define UDDR15 0x406000E0 /* UDC Endpoint 15 Data Register */ - -#define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */ - -#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ -#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ -#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ -#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ -#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ -#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ -#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ -#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ - -#define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */ - -#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ -#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ -#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ -#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ -#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ -#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ -#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ -#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ - -#define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */ - -#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ -#define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */ -#define USIR0_IR2 (1 << 4) /* Interrup request ep 2 */ -#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ -#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ -#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ -#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ -#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ - -#define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */ - -#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ -#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ -#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ -#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ -#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ -#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ -#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ -#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ - - -#define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */ -#define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */ -#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ -#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ - -#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ - -#define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */ -#define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */ -#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */ -#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */ -#define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */ -#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */ - - -#define UDCFNR 0x40600014 /* UDC Frame Number Register */ -#define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */ -#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ -#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ - -#define UDCCSN(x) (0x40600100 + ((x) << 2)) -#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */ - -#define UDCCSR0_SA (1 << 7) /* Setup Active */ -#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ -#define UDCCSR0_FST (1 << 5) /* Force Stall */ -#define UDCCSR0_SST (1 << 4) /* Sent Stall */ -#define UDCCSR0_DME (1 << 3) /* DMA Enable */ -#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ -#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ -#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ - -#define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */ -#define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */ -#define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */ -#define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */ -#define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */ -#define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */ -#define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */ -#define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */ -#define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */ -#define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */ -#define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */ -#define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */ -#define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */ -#define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */ -#define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */ -#define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */ -#define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */ -#define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */ -#define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */ -#define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */ -#define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */ -#define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */ -#define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */ - -#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ -#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ -#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ -#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ -#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ -#define UDCCSR_FST (1 << 5) /* Force STALL */ -#define UDCCSR_SST (1 << 4) /* Sent STALL */ -#define UDCCSR_DME (1 << 3) /* DMA Enable */ -#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ -#define UDCCSR_PC (1 << 1) /* Packet Complete */ -#define UDCCSR_FS (1 << 0) /* FIFO needs service */ - -#define UDCBCN(x) (0x40600200 + ((x) << 2)) -#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */ -#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */ -#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */ -#define UDCBCRC 0x4060020C /* Byte Count Register - EPC */ -#define UDCBCRD 0x40600210 /* Byte Count Register - EPD */ -#define UDCBCRE 0x40600214 /* Byte Count Register - EPE */ -#define UDCBCRF 0x40600218 /* Byte Count Register - EPF */ -#define UDCBCRG 0x4060021C /* Byte Count Register - EPG */ -#define UDCBCRH 0x40600220 /* Byte Count Register - EPH */ -#define UDCBCRI 0x40600224 /* Byte Count Register - EPI */ -#define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */ -#define UDCBCRK 0x4060022C /* Byte Count Register - EPK */ -#define UDCBCRL 0x40600230 /* Byte Count Register - EPL */ -#define UDCBCRM 0x40600234 /* Byte Count Register - EPM */ -#define UDCBCRN 0x40600238 /* Byte Count Register - EPN */ -#define UDCBCRP 0x4060023C /* Byte Count Register - EPP */ -#define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */ -#define UDCBCRR 0x40600244 /* Byte Count Register - EPR */ -#define UDCBCRS 0x40600248 /* Byte Count Register - EPS */ -#define UDCBCRT 0x4060024C /* Byte Count Register - EPT */ -#define UDCBCRU 0x40600250 /* Byte Count Register - EPU */ -#define UDCBCRV 0x40600254 /* Byte Count Register - EPV */ -#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */ -#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */ - -#define UDCDN(x) (0x40600300 + ((x) << 2)) -#define UDCDR0 0x40600300 /* Data Register - EP0 */ -#define UDCDRA 0x40600304 /* Data Register - EPA */ -#define UDCDRB 0x40600308 /* Data Register - EPB */ -#define UDCDRC 0x4060030C /* Data Register - EPC */ -#define UDCDRD 0x40600310 /* Data Register - EPD */ -#define UDCDRE 0x40600314 /* Data Register - EPE */ -#define UDCDRF 0x40600318 /* Data Register - EPF */ -#define UDCDRG 0x4060031C /* Data Register - EPG */ -#define UDCDRH 0x40600320 /* Data Register - EPH */ -#define UDCDRI 0x40600324 /* Data Register - EPI */ -#define UDCDRJ 0x40600328 /* Data Register - EPJ */ -#define UDCDRK 0x4060032C /* Data Register - EPK */ -#define UDCDRL 0x40600330 /* Data Register - EPL */ -#define UDCDRM 0x40600334 /* Data Register - EPM */ -#define UDCDRN 0x40600338 /* Data Register - EPN */ -#define UDCDRP 0x4060033C /* Data Register - EPP */ -#define UDCDRQ 0x40600340 /* Data Register - EPQ */ -#define UDCDRR 0x40600344 /* Data Register - EPR */ -#define UDCDRS 0x40600348 /* Data Register - EPS */ -#define UDCDRT 0x4060034C /* Data Register - EPT */ -#define UDCDRU 0x40600350 /* Data Register - EPU */ -#define UDCDRV 0x40600354 /* Data Register - EPV */ -#define UDCDRW 0x40600358 /* Data Register - EPW */ -#define UDCDRX 0x4060035C /* Data Register - EPX */ - -#define UDCCN(x) (0x40600400 + ((x) << 2)) -#define UDCCRA 0x40600404 /* Configuration register EPA */ -#define UDCCRB 0x40600408 /* Configuration register EPB */ -#define UDCCRC 0x4060040C /* Configuration register EPC */ -#define UDCCRD 0x40600410 /* Configuration register EPD */ -#define UDCCRE 0x40600414 /* Configuration register EPE */ -#define UDCCRF 0x40600418 /* Configuration register EPF */ -#define UDCCRG 0x4060041C /* Configuration register EPG */ -#define UDCCRH 0x40600420 /* Configuration register EPH */ -#define UDCCRI 0x40600424 /* Configuration register EPI */ -#define UDCCRJ 0x40600428 /* Configuration register EPJ */ -#define UDCCRK 0x4060042C /* Configuration register EPK */ -#define UDCCRL 0x40600430 /* Configuration register EPL */ -#define UDCCRM 0x40600434 /* Configuration register EPM */ -#define UDCCRN 0x40600438 /* Configuration register EPN */ -#define UDCCRP 0x4060043C /* Configuration register EPP */ -#define UDCCRQ 0x40600440 /* Configuration register EPQ */ -#define UDCCRR 0x40600444 /* Configuration register EPR */ -#define UDCCRS 0x40600448 /* Configuration register EPS */ -#define UDCCRT 0x4060044C /* Configuration register EPT */ -#define UDCCRU 0x40600450 /* Configuration register EPU */ -#define UDCCRV 0x40600454 /* Configuration register EPV */ -#define UDCCRW 0x40600458 /* Configuration register EPW */ -#define UDCCRX 0x4060045C /* Configuration register EPX */ - -#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ -#define UDCCONR_CN_S (25) -#define UDCCONR_IN (0x07 << 22) /* Interface Number */ -#define UDCCONR_IN_S (22) -#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ -#define UDCCONR_AISN_S (19) -#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ -#define UDCCONR_EN_S (15) -#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ -#define UDCCONR_ET_S (13) -#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ -#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ -#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ -#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ -#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ -#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ -#define UDCCONR_MPS_S (2) -#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ -#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ - - -#define UDC_INT_FIFOERROR (0x2) -#define UDC_INT_PACKETCMP (0x1) -#define UDC_FNR_MASK (0x7ff) -#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) -#define UDC_BCR_MASK (0x3ff) - -#endif /* CONFIG_CPU_PXA27X */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - -/******************************************************************************/ -/* - * USB Host Controller - */ -#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */ -#define UHCREV 0x4C000000 -#define UHCHCON 0x4C000004 -#define UHCCOMS 0x4C000008 -#define UHCINTS 0x4C00000C -#define UHCINTE 0x4C000010 -#define UHCINTD 0x4C000014 -#define UHCHCCA 0x4C000018 -#define UHCPCED 0x4C00001C -#define UHCCHED 0x4C000020 -#define UHCCCED 0x4C000024 -#define UHCBHED 0x4C000028 -#define UHCBCED 0x4C00002C -#define UHCDHEAD 0x4C000030 -#define UHCFMI 0x4C000034 -#define UHCFMR 0x4C000038 -#define UHCFMN 0x4C00003C -#define UHCPERS 0x4C000040 -#define UHCLST 0x4C000044 -#define UHCRHDA 0x4C000048 -#define UHCRHDB 0x4C00004C -#define UHCRHS 0x4C000050 -#define UHCRHPS1 0x4C000054 -#define UHCRHPS2 0x4C000058 -#define UHCRHPS3 0x4C00005C -#define UHCSTAT 0x4C000060 -#define UHCHR 0x4C000064 -#define UHCHIE 0x4C000068 -#define UHCHIT 0x4C00006C - -#define UHCCOMS_HCR (1<<0) - -#define UHCHR_FSBIR (1<<0) -#define UHCHR_FHR (1<<1) -#define UHCHR_CGR (1<<2) -#define UHCHR_SSDC (1<<3) -#define UHCHR_UIT (1<<4) -#define UHCHR_SSE (1<<5) -#define UHCHR_PSPL (1<<6) -#define UHCHR_PCPL (1<<7) -#define UHCHR_SSEP0 (1<<9) -#define UHCHR_SSEP1 (1<<10) -#define UHCHR_SSEP2 (1<<11) - -#define UHCHIE_UPRIE (1<<13) -#define UHCHIE_UPS2IE (1<<12) -#define UHCHIE_UPS1IE (1<<11) -#define UHCHIE_TAIE (1<<10) -#define UHCHIE_HBAIE (1<<8) -#define UHCHIE_RWIE (1<<7) - -#define UP2OCR 0x40600020 - -#define UP2OCR_HXOE (1<<17) -#define UP2OCR_HXS (1<<16) -#define UP2OCR_IDON (1<<10) -#define UP2OCR_EXSUS (1<<9) -#define UP2OCR_EXSP (1<<8) -#define UP2OCR_DMSTATE (1<<7) -#define UP2OCR_VPM (1<<6) -#define UP2OCR_DPSTATE (1<<5) -#define UP2OCR_DPPUE (1<<4) -#define UP2OCR_DMPDE (1<<3) -#define UP2OCR_DPPDE (1<<2) -#define UP2OCR_CPVPE (1<<1) -#define UP2OCR_CPVEN (1<<0) - -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * Fast Infrared Communication Port - */ -#define ICCR0 0x40800000 /* ICP Control Register 0 */ -#define ICCR1 0x40800004 /* ICP Control Register 1 */ -#define ICCR2 0x40800008 /* ICP Control Register 2 */ -#define ICDR 0x4080000c /* ICP Data Register */ -#define ICSR0 0x40800014 /* ICP Status Register 0 */ -#define ICSR1 0x40800018 /* ICP Status Register 1 */ - -/* - * Real Time Clock - */ -#define RCNR 0x40900000 /* RTC Count Register */ -#define RTAR 0x40900004 /* RTC Alarm Register */ -#define RTSR 0x40900008 /* RTC Status Register */ -#define RTTR 0x4090000C /* RTC Timer Trim Register */ -#define RDAR1 0x40900018 /* Wristwatch Day Alarm Reg 1 */ -#define RDAR2 0x40900020 /* Wristwatch Day Alarm Reg 2 */ -#define RYAR1 0x4090001C /* Wristwatch Year Alarm Reg 1 */ -#define RYAR2 0x40900024 /* Wristwatch Year Alarm Reg 2 */ -#define SWAR1 0x4090002C /* Stopwatch Alarm Register 1 */ -#define SWAR2 0x40900030 /* Stopwatch Alarm Register 2 */ -#define PIAR 0x40900038 /* Periodic Interrupt Alarm Register */ -#define RDCR 0x40900010 /* RTC Day Count Register. */ -#define RYCR 0x40900014 /* RTC Year Count Register. */ -#define SWCR 0x40900028 /* Stopwatch Count Register */ -#define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */ - -#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ -#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ -#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */ -#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ -#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ -#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ -#define RTSR_AL (1 << 0) /* RTC alarm detected */ - -/******************************************************************************/ -/* - * OS Timer & Match Registers - */ -#define OSMR0 0x40A00000 /* OS Timer Match Register 0 */ -#define OSMR1 0x40A00004 /* OS Timer Match Register 1 */ -#define OSMR2 0x40A00008 /* OS Timer Match Register 2 */ -#define OSMR3 0x40A0000C /* OS Timer Match Register 3 */ -#define OSCR 0x40A00010 /* OS Timer Counter Register */ -#define OSSR 0x40A00014 /* OS Timer Status Register */ -#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ -#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ -#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ -#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ -#define OSCR7 0x40A0004C /* OS Timer Counter Register 7 */ -#define OSCR8 0x40A00050 /* OS Timer Counter Register 8 */ -#define OSCR9 0x40A00054 /* OS Timer Counter Register 9 */ -#define OSCR10 0x40A00058 /* OS Timer Counter Register 10 */ -#define OSCR11 0x40A0005C /* OS Timer Counter Register 11 */ - -#define OSMR4 0x40A00080 /* OS Timer Match Register 4 */ -#define OSMR5 0x40A00084 /* OS Timer Match Register 5 */ -#define OSMR6 0x40A00088 /* OS Timer Match Register 6 */ -#define OSMR7 0x40A0008C /* OS Timer Match Register 7 */ -#define OSMR8 0x40A00090 /* OS Timer Match Register 8 */ -#define OSMR9 0x40A00094 /* OS Timer Match Register 9 */ -#define OSMR10 0x40A00098 /* OS Timer Match Register 10 */ -#define OSMR11 0x40A0009C /* OS Timer Match Register 11 */ - -#define OMCR4 0x40A000C0 /* OS Match Control Register 4 */ -#define OMCR5 0x40A000C4 /* OS Match Control Register 5 */ -#define OMCR6 0x40A000C8 /* OS Match Control Register 6 */ -#define OMCR7 0x40A000CC /* OS Match Control Register 7 */ -#define OMCR8 0x40A000D0 /* OS Match Control Register 8 */ -#define OMCR9 0x40A000D4 /* OS Match Control Register 9 */ -#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ -#define OMCR11 0x40A000DC /* OS Match Control Register 11 */ - -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#define OSSR_M4 (1 << 4) /* Match status channel 4 */ -#define OSSR_M3 (1 << 3) /* Match status channel 3 */ -#define OSSR_M2 (1 << 2) /* Match status channel 2 */ -#define OSSR_M1 (1 << 1) /* Match status channel 1 */ -#define OSSR_M0 (1 << 0) /* Match status channel 0 */ - -#define OWER_WME (1 << 0) /* Watchdog Match Enable */ - -#define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */ -#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ -#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ -#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ -#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ - -#define OSCR_CLK_FREQ 3250 - -/******************************************************************************/ -/* - * Core Clock - */ - -#if defined(CONFIG_CPU_MONAHANS) -#define ACCR 0x41340000 /* Application Subsystem Clock Configuration Register */ -#define ACSR 0x41340004 /* Application Subsystem Clock Status Register */ -#define AICSR 0x41340008 /* Application Subsystem Interrupt Control/Status Register */ -#define CKENA 0x4134000C /* A Clock Enable Register */ -#define CKENB 0x41340010 /* B Clock Enable Register */ -#define AC97_DIV 0x41340014 /* AC97 clock divisor value register */ - -#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ -#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ -#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ -#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ -#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ -#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define ACCR_XPDIS (1 << 31) -#define ACCR_SPDIS (1 << 30) -#define ACCR_13MEND1 (1 << 27) -#define ACCR_D0CS (1 << 26) -#define ACCR_13MEND2 (1 << 21) -#define ACCR_PCCE (1 << 11) - -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ -#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ -#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ -#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ -#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ -#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ -#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ -#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ -#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ -#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ -#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ - -#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ -#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ - -#else /* if defined CONFIG_CPU_MONAHANS */ - -#define CCCR 0x41300000 /* Core Clock Configuration Register */ -#define CKEN 0x41300004 /* Clock Enable Register */ -#define OSCC 0x41300008 /* Oscillator Configuration Register */ -#define CCSR 0x4130000C /* Core Clock Status Register */ - -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controler */ -#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ -#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ -#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_CPU_PXA27X) -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#endif -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_CPU_PXA27X) -#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ -#endif -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -#if !defined(CONFIG_CPU_PXA27X) -#define CCCR_L09 (0x1F) -#define CCCR_L27 (0x1) -#define CCCR_L32 (0x2) -#define CCCR_L36 (0x3) -#define CCCR_L40 (0x4) -#define CCCR_L45 (0x5) - -#define CCCR_M1 (0x1 << 5) -#define CCCR_M2 (0x2 << 5) -#define CCCR_M4 (0x3 << 5) - -#define CCCR_N10 (0x2 << 7) -#define CCCR_N15 (0x3 << 7) -#define CCCR_N20 (0x4 << 7) -#define CCCR_N25 (0x5 << 7) -#define CCCR_N30 (0x6 << 7) -#endif - -#endif /* CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * Pulse Width Modulator - */ -#define PWM_CTRL0 0x40B00000 /* PWM 0 Control Register */ -#define PWM_PWDUTY0 0x40B00004 /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 0x40B00008 /* PWM 0 Period Control Register */ - -#define PWM_CTRL1 0x40C00000 /* PWM 1 Control Register */ -#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ -#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ -#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ - -#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ -#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ -#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/* - * Interrupt Controller - */ -#define ICIP 0x40D00000 /* Interrupt Controller IRQ Pending Register */ -#define ICMR 0x40D00004 /* Interrupt Controller Mask Register */ -#define ICLR 0x40D00008 /* Interrupt Controller Level Register */ -#define ICFP 0x40D0000C /* Interrupt Controller FIQ Pending Register */ -#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ -#define ICCR 0x40D00014 /* Interrupt Controller Control Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ -#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ -#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ -#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * General Purpose I/O - */ -#define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ -#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */ - -#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */ - -#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */ - -#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */ - -#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */ - -#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */ - -#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */ -#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */ -#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ -#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ -#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#ifdef CONFIG_CPU_MONAHANS -#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ -#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */ -#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */ -#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */ - -#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */ -#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */ -#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */ -#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */ - -#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */ -#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */ - -#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */ -#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */ - -#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */ -#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */ - -#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */ -#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */ - -#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3) -#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3) -#endif - -#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3)) -#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3)) -#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3)) -#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3)) -#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3)) -#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3)) -#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) -#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) -#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) -#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) -#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)) -#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)) -#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)) -#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)) -#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))) -#else -#define GPLR(x) _GPLR(x) -#define GPDR(x) _GPDR(x) -#define GPSR(x) _GPSR(x) -#define GPCR(x) _GPCR(x) -#define GRER(x) _GRER(x) -#define GFER(x) _GFER(x) -#define GEDR(x) _GEDR(x) -#define GAFR(x) _GAFR(x) -#endif - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -/******************************************************************************/ -/* - * Multi-function Pin Registers: - */ -/* PXA320 */ -#if defined(CONFIG_CPU_PXA320) -#define DF_IO0 0x40e1024c -#define DF_IO1 0x40e10254 -#define DF_IO2 0x40e1025c -#define DF_IO3 0x40e10264 -#define DF_IO4 0x40e1026c -#define DF_IO5 0x40e10274 -#define DF_IO6 0x40e1027c -#define DF_IO7 0x40e10284 -#define DF_IO8 0x40e10250 -#define DF_IO9 0x40e10258 -#define DF_IO10 0x40e10260 -#define DF_IO11 0x40e10268 -#define DF_IO12 0x40e10270 -#define DF_IO13 0x40e10278 -#define DF_IO14 0x40e10280 -#define DF_IO15 0x40e10288 -#define DF_CLE_nOE 0x40e10204 -#define DF_ALE_nWE1 0x40e10208 -#define DF_ALE_nWE2 0x40e1021c -#define DF_SCLK_E 0x40e10210 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define nBE0 0x40e10214 -#define nBE1 0x40e10218 -#define nLUA 0x40e10234 -#define nLLA 0x40e10238 -#define DF_ADDR0 0x40e1023c -#define DF_ADDR1 0x40e10240 -#define DF_ADDR2 0x40e10244 -#define DF_ADDR3 0x40e10248 -#define DF_INT_RnB 0x40e10220 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define DF_nWE 0x40e1022c -#define DF_nRE 0x40e10230 - -#define nXCVREN 0x40e10138 - -#define GPIO0 0x40e10124 -#define GPIO1 0x40e10128 -#define GPIO2 0x40e1012c -#define GPIO3 0x40e10130 -#define GPIO4 0x40e10134 -#define GPIO5 0x40e1028c -#define GPIO6 0x40e10290 -#define GPIO7 0x40e10294 -#define GPIO8 0x40e10298 -#define GPIO9 0x40e1029c -#define GPIO10 0x40e10458 -#define GPIO11 0x40e102a0 -#define GPIO12 0x40e102a4 -#define GPIO13 0x40e102a8 -#define GPIO14 0x40e102ac -#define GPIO15 0x40e102b0 -#define GPIO16 0x40e102b4 -#define GPIO17 0x40e102b8 -#define GPIO18 0x40e102bc -#define GPIO19 0x40e102c0 -#define GPIO20 0x40e102c4 -#define GPIO21 0x40e102c8 -#define GPIO22 0x40e102cc -#define GPIO23 0x40e102d0 -#define GPIO24 0x40e102d4 -#define GPIO25 0x40e102d8 -#define GPIO26 0x40e102dc - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define GPIO30 0x40e1040c -#define GPIO31 0x40e10410 -#define GPIO32 0x40e10414 -#define GPIO33 0x40e10418 -#define GPIO34 0x40e1041c -#define GPIO35 0x40e10420 -#define GPIO36 0x40e10424 -#define GPIO37 0x40e10428 -#define GPIO38 0x40e1042c -#define GPIO39 0x40e10430 -#define GPIO40 0x40e10434 -#define GPIO41 0x40e10438 -#define GPIO42 0x40e1043c -#define GPIO43 0x40e10440 -#define GPIO44 0x40e10444 -#define GPIO45 0x40e10448 -#define GPIO46 0x40e1044c -#define GPIO47 0x40e10450 -#define GPIO48 0x40e10454 -#define GPIO49 0x40e1045c -#define GPIO50 0x40e10460 -#define GPIO51 0x40e10464 -#define GPIO52 0x40e10468 -#define GPIO53 0x40e1046c -#define GPIO54 0x40e10470 -#define GPIO55 0x40e10474 -#define GPIO56 0x40e10478 -#define GPIO57 0x40e1047c -#define GPIO58 0x40e10480 -#define GPIO59 0x40e10484 -#define GPIO60 0x40e10488 -#define GPIO61 0x40e1048c -#define GPIO62 0x40e10490 - -#define GPIO6_2 0x40e10494 -#define GPIO7_2 0x40e10498 -#define GPIO8_2 0x40e1049c -#define GPIO9_2 0x40e104a0 -#define GPIO10_2 0x40e104a4 -#define GPIO11_2 0x40e104a8 -#define GPIO12_2 0x40e104ac -#define GPIO13_2 0x40e104b0 - -#define GPIO63 0x40e104b4 -#define GPIO64 0x40e104b8 -#define GPIO65 0x40e104bc -#define GPIO66 0x40e104c0 -#define GPIO67 0x40e104c4 -#define GPIO68 0x40e104c8 -#define GPIO69 0x40e104cc -#define GPIO70 0x40e104d0 -#define GPIO71 0x40e104d4 -#define GPIO72 0x40e104d8 -#define GPIO73 0x40e104dc - -#define GPIO14_2 0x40e104e0 -#define GPIO15_2 0x40e104e4 -#define GPIO16_2 0x40e104e8 -#define GPIO17_2 0x40e104ec - -#define GPIO74 0x40e104f0 -#define GPIO75 0x40e104f4 -#define GPIO76 0x40e104f8 -#define GPIO77 0x40e104fc -#define GPIO78 0x40e10500 -#define GPIO79 0x40e10504 -#define GPIO80 0x40e10508 -#define GPIO81 0x40e1050c -#define GPIO82 0x40e10510 -#define GPIO83 0x40e10514 -#define GPIO84 0x40e10518 -#define GPIO85 0x40e1051c -#define GPIO86 0x40e10520 -#define GPIO87 0x40e10524 -#define GPIO88 0x40e10528 -#define GPIO89 0x40e1052c -#define GPIO90 0x40e10530 -#define GPIO91 0x40e10534 -#define GPIO92 0x40e10538 -#define GPIO93 0x40e1053c -#define GPIO94 0x40e10540 -#define GPIO95 0x40e10544 -#define GPIO96 0x40e10548 -#define GPIO97 0x40e1054c -#define GPIO98 0x40e10550 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e1067c -#define GPIO3_2 0x40e10680 -#define GPIO4_2 0x40e10684 -#define GPIO5_2 0x40e10688 - -/* PXA300 and PXA310 */ -#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310) -#define DF_IO0 0x40e10220 -#define DF_IO1 0x40e10228 -#define DF_IO2 0x40e10230 -#define DF_IO3 0x40e10238 -#define DF_IO4 0x40e10258 -#define DF_IO5 0x40e10260 -#define DF_IO7 0x40e10270 -#define DF_IO6 0x40e10268 -#define DF_IO8 0x40e10224 -#define DF_IO9 0x40e1022c -#define DF_IO10 0x40e10234 -#define DF_IO11 0x40e1023c -#define DF_IO12 0x40e1025c -#define DF_IO13 0x40e10264 -#define DF_IO14 0x40e1026c -#define DF_IO15 0x40e10274 -#define DF_CLE_NOE 0x40e10240 -#define DF_ALE_nWE 0x40e1020c -#define DF_SCLK_E 0x40e10250 -#define nCS0 0x40e100c4 -#define nCS1 0x40e100c0 -#define nBE0 0x40e10204 -#define nBE1 0x40e10208 -#define nLUA 0x40e10244 -#define nLLA 0x40e10254 -#define DF_ADDR0 0x40e10210 -#define DF_ADDR1 0x40e10214 -#define DF_ADDR2 0x40e10218 -#define DF_ADDR3 0x40e1021c -#define DF_INT_RnB 0x40e100c8 -#define DF_nCS0 0x40e10248 -#define DF_nCS1 0x40e10278 -#define DF_nWE 0x40e100cc -#define DF_nRE 0x40e10200 - -#define GPIO0 0x40e100b4 -#define GPIO1 0x40e100b8 -#define GPIO2 0x40e100bc -#define GPIO3 0x40e1027c -#define GPIO4 0x40e10280 - -#define GPIO5 0x40e10284 -#define GPIO6 0x40e10288 -#define GPIO7 0x40e1028c -#define GPIO8 0x40e10290 -#define GPIO9 0x40e10294 -#define GPIO10 0x40e10298 -#define GPIO11 0x40e1029c -#define GPIO12 0x40e102a0 -#define GPIO13 0x40e102a4 -#define GPIO14 0x40e102a8 -#define GPIO15 0x40e102ac -#define GPIO16 0x40e102b0 -#define GPIO17 0x40e102b4 -#define GPIO18 0x40e102b8 -#define GPIO19 0x40e102bc -#define GPIO20 0x40e102c0 -#define GPIO21 0x40e102c4 -#define GPIO22 0x40e102c8 -#define GPIO23 0x40e102cc -#define GPIO24 0x40e102d0 -#define GPIO25 0x40e102d4 -#define GPIO26 0x40e102d8 - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define ULPI_STP 0x40e1040c -#define ULPI_NXT 0x40e10410 -#define ULPI_DIR 0x40e10414 -#define GPIO30 0x40e10418 -#define GPIO31 0x40e1041c -#define GPIO32 0x40e10420 -#define GPIO33 0x40e10424 -#define GPIO34 0x40e10428 -#define GPIO35 0x40e1042c -#define GPIO36 0x40e10430 -#define GPIO37 0x40e10434 -#define GPIO38 0x40e10438 -#define GPIO39 0x40e1043c -#define GPIO40 0x40e10440 -#define GPIO41 0x40e10444 -#define GPIO42 0x40e10448 -#define GPIO43 0x40e1044c -#define GPIO44 0x40e10450 -#define GPIO45 0x40e10454 -#define GPIO46 0x40e10458 -#define GPIO47 0x40e1045c -#define GPIO48 0x40e10460 - -#define GPIO49 0x40e10464 -#define GPIO50 0x40e10468 -#define GPIO51 0x40e1046c -#define GPIO52 0x40e10470 -#define GPIO53 0x40e10474 -#define GPIO54 0x40e10478 -#define GPIO55 0x40e1047c -#define GPIO56 0x40e10480 -#define GPIO57 0x40e10484 -#define GPIO58 0x40e10488 -#define GPIO59 0x40e1048c -#define GPIO60 0x40e10490 -#define GPIO61 0x40e10494 -#define GPIO62 0x40e10498 -#define GPIO63 0x40e1049c -#define GPIO64 0x40e104a0 -#define GPIO65 0x40e104a4 -#define GPIO66 0x40e104a8 -#define GPIO67 0x40e104ac -#define GPIO68 0x40e104b0 -#define GPIO69 0x40e104b4 -#define GPIO70 0x40e104b8 -#define GPIO71 0x40e104bc -#define GPIO72 0x40e104c0 -#define GPIO73 0x40e104c4 -#define GPIO74 0x40e104c8 -#define GPIO75 0x40e104cc -#define GPIO76 0x40e104d0 -#define GPIO77 0x40e104d4 -#define GPIO78 0x40e104d8 -#define GPIO79 0x40e104dc -#define GPIO80 0x40e104e0 -#define GPIO81 0x40e104e4 -#define GPIO82 0x40e104e8 -#define GPIO83 0x40e104ec -#define GPIO84 0x40e104f0 -#define GPIO85 0x40e104f4 -#define GPIO86 0x40e104f8 -#define GPIO87 0x40e104fc -#define GPIO88 0x40e10500 -#define GPIO89 0x40e10504 -#define GPIO90 0x40e10508 -#define GPIO91 0x40e1050c -#define GPIO92 0x40e10510 -#define GPIO93 0x40e10514 -#define GPIO94 0x40e10518 -#define GPIO95 0x40e1051c -#define GPIO96 0x40e10520 -#define GPIO97 0x40e10524 -#define GPIO98 0x40e10528 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e102dc -#define GPIO3_2 0x40e102e0 -#define GPIO4_2 0x40e102e4 -#define GPIO5_2 0x40e102e8 -#define GPIO6_2 0x40e102ec - -#ifndef CONFIG_CPU_PXA300 /* PXA310 only */ -#define GPIO7_2 0x40e1052c -#define GPIO8_2 0x40e10530 -#define GPIO9_2 0x40e10534 -#define GPIO10_2 0x40e10538 -#endif -#endif - -#ifdef CONFIG_CPU_MONAHANS -/* MFPR Bit Definitions, see 4-10, Vol. 1 */ -#define PULL_SEL 0x8000 -#define PULLUP_EN 0x4000 -#define PULLDOWN_EN 0x2000 - -#define DRIVE_FAST_1mA 0x0 -#define DRIVE_FAST_2mA 0x400 -#define DRIVE_FAST_3mA 0x800 -#define DRIVE_FAST_4mA 0xC00 -#define DRIVE_SLOW_6mA 0x1000 -#define DRIVE_FAST_6mA 0x1400 -#define DRIVE_SLOW_10mA 0x1800 -#define DRIVE_FAST_10mA 0x1C00 - -#define SLEEP_SEL 0x200 -#define SLEEP_DATA 0x100 -#define SLEEP_OE_N 0x80 -#define EDGE_CLEAR 0x40 -#define EDGE_FALL_EN 0x20 -#define EDGE_RISE_EN 0x10 - -#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */ -#define AF_SEL_1 0x1 /* Alternate function 1 */ -#define AF_SEL_2 0x2 /* Alternate function 2 */ -#define AF_SEL_3 0x3 /* Alternate function 3 */ -#define AF_SEL_4 0x4 /* Alternate function 4 */ -#define AF_SEL_5 0x5 /* Alternate function 5 */ -#define AF_SEL_6 0x6 /* Alternate function 6 */ -#define AF_SEL_7 0x7 /* Alternate function 7 */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO8_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) - -#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) -#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) - -/* - * Power Manager - */ -#ifdef CONFIG_CPU_MONAHANS - -#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */ -#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */ -#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */ -#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */ -#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */ -#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */ -#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */ -#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */ -#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */ -#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */ -#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */ -#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */ -#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */ -#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */ - -#define PMCR 0x40F50000 /* Power Manager Control Register */ -#define PSR 0x40F50004 /* Power Manager S2 Status Register */ -#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */ -#define PCFR 0x40F5000C /* Power Manager General Configuration Register */ -#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */ -#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */ -#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */ -#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */ -#define PCMD(x) (0x40F50110 + x*4) -#define PCMD0 (0x40F50110 + 0 * 4) -#define PCMD1 (0x40F50110 + 1 * 4) -#define PCMD2 (0x40F50110 + 2 * 4) -#define PCMD3 (0x40F50110 + 3 * 4) -#define PCMD4 (0x40F50110 + 4 * 4) -#define PCMD5 (0x40F50110 + 5 * 4) -#define PCMD6 (0x40F50110 + 6 * 4) -#define PCMD7 (0x40F50110 + 7 * 4) -#define PCMD8 (0x40F50110 + 8 * 4) -#define PCMD9 (0x40F50110 + 9 * 4) -#define PCMD10 (0x40F50110 + 10 * 4) -#define PCMD11 (0x40F50110 + 11 * 4) -#define PCMD12 (0x40F50110 + 12 * 4) -#define PCMD13 (0x40F50110 + 13 * 4) -#define PCMD14 (0x40F50110 + 14 * 4) -#define PCMD15 (0x40F50110 + 15 * 4) -#define PCMD16 (0x40F50110 + 16 * 4) -#define PCMD17 (0x40F50110 + 17 * 4) -#define PCMD18 (0x40F50110 + 18 * 4) -#define PCMD19 (0x40F50110 + 19 * 4) -#define PCMD20 (0x40F50110 + 20 * 4) -#define PCMD21 (0x40F50110 + 21 * 4) -#define PCMD22 (0x40F50110 + 22 * 4) -#define PCMD23 (0x40F50110 + 23 * 4) -#define PCMD24 (0x40F50110 + 24 * 4) -#define PCMD25 (0x40F50110 + 25 * 4) -#define PCMD26 (0x40F50110 + 26 * 4) -#define PCMD27 (0x40F50110 + 27 * 4) -#define PCMD28 (0x40F50110 + 28 * 4) -#define PCMD29 (0x40F50110 + 29 * 4) -#define PCMD30 (0x40F50110 + 30 * 4) -#define PCMD31 (0x40F50110 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ - -#define PVCR_FVC (0x1 << 28) -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -#define PVCR_ReadPointer 0x01f00000 -#define PVCR_SlaveAddress (0x7f) - -#else /* ifdef CONFIG_CPU_MONAHANS */ - -#define PMCR 0x40F00000 /* Power Manager Control Register */ -#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */ -#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */ -#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */ -#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR 0x40F0001C /* Power Manager General Configuration Register */ -#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR 0x40F00030 /* Reset Controller Status Register */ - -#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */ -#define PSTR 0x40F00038 /* Power Manager Standby Config Register */ -#define PSNR 0x40F0003C /* Power Manager Sense Config Register */ -#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */ -#define PCMD(x) (0x40F00080 + x*4) -#define PCMD0 (0x40F00080 + 0 * 4) -#define PCMD1 (0x40F00080 + 1 * 4) -#define PCMD2 (0x40F00080 + 2 * 4) -#define PCMD3 (0x40F00080 + 3 * 4) -#define PCMD4 (0x40F00080 + 4 * 4) -#define PCMD5 (0x40F00080 + 5 * 4) -#define PCMD6 (0x40F00080 + 6 * 4) -#define PCMD7 (0x40F00080 + 7 * 4) -#define PCMD8 (0x40F00080 + 8 * 4) -#define PCMD9 (0x40F00080 + 9 * 4) -#define PCMD10 (0x40F00080 + 10 * 4) -#define PCMD11 (0x40F00080 + 11 * 4) -#define PCMD12 (0x40F00080 + 12 * 4) -#define PCMD13 (0x40F00080 + 13 * 4) -#define PCMD14 (0x40F00080 + 14 * 4) -#define PCMD15 (0x40F00080 + 15 * 4) -#define PCMD16 (0x40F00080 + 16 * 4) -#define PCMD17 (0x40F00080 + 17 * 4) -#define PCMD18 (0x40F00080 + 18 * 4) -#define PCMD19 (0x40F00080 + 19 * 4) -#define PCMD20 (0x40F00080 + 20 * 4) -#define PCMD21 (0x40F00080 + 21 * 4) -#define PCMD22 (0x40F00080 + 22 * 4) -#define PCMD23 (0x40F00080 + 23 * 4) -#define PCMD24 (0x40F00080 + 24 * 4) -#define PCMD25 (0x40F00080 + 25 * 4) -#define PCMD26 (0x40F00080 + 26 * 4) -#define PCMD27 (0x40F00080 + 27 * 4) -#define PCMD28 (0x40F00080 + 28 * 4) -#define PCMD29 (0x40F00080 + 29 * 4) -#define PCMD30 (0x40F00080 + 30 * 4) -#define PCMD31 (0x40F00080 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -/* FIXME: PCMD_SQC need be checked. */ -#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ - /* bit 9 should be 0 all day. */ -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -/* define MACRO for Power Manager General Configuration Register (PCFR) */ -#define PCFR_FVC (0x1 << 10) -#define PCFR_PI2C_EN (0x1 << 6) - -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * SSP Serial Port Registers - */ -#define SSCR0 0x41000000 /* SSP Control Register 0 */ -#define SSCR1 0x41000004 /* SSP Control Register 1 */ -#define SSSR 0x41000008 /* SSP Status Register */ -#define SSITR 0x4100000C /* SSP Interrupt Test Register */ -#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ - -/* - * MultiMediaCard (MMC) controller - */ -#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */ -#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */ -#define MMC_CLKRT 0x41100008 /* MMC clock rate */ -#define MMC_SPI 0x4110000c /* SPI mode control bits */ -#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */ -#define MMC_RESTO 0x41100014 /* Expected response time out */ -#define MMC_RDTO 0x41100018 /* Expected data read time out */ -#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */ -#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */ -#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK 0x41100028 /* Interrupt Mask */ -#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */ -#define MMC_CMD 0x41100030 /* Index of current command */ -#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */ -#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */ -#define MMC_RES 0x4110003c /* Response FIFO (read only) */ -#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */ -#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */ - - -/* - * LCD - */ -#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */ -#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */ -#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */ -#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */ -#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define LCSR0 0x44000038 /* LCD Controller Status Register */ -#define LCSR1 0x44000034 /* LCD Controller Status Register */ -#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */ -#define TMEDCR 0x44000044 /* TMED Control Register */ - -#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */ -#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ -#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ -#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ -#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_CPU_PXA27X) -#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ -#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ -#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ -#endif - -#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ - (((Pixel) - 1) << FShft (LCCR1_PPL)) - -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) - -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) - -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) - -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) - -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) - -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ -#define LCCR3_OEP (1 << 23) /* output enable polarity */ -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ - -#define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) -#define LCCR3_PDFOR_2 (2 << 30) -#define LCCR3_PDFOR_3 (3 << 30) - - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ - (((Div) << FShft (LCCR3_PCD))) - - -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ - ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) - -#define LCCR3_ACB Fld (8, 8) /* AC Bias */ -#define LCCR3_Acb(Acb) /* BAC Bias */ \ - (((Acb) << FShft (LCCR3_ACB))) - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ - -#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR0_SOF (1 << 1) /* Start of frame */ -#define LCSR0_BER (1 << 2) /* Bus error */ -#define LCSR0_ABC (1 << 3) /* AC Bias count */ -#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR0_OU (1 << 6) /* output FIFO underrun */ -#define LCSR0_QD (1 << 7) /* quick disable */ -#define LCSR0_EOF0 (1 << 8) /* end of frame */ -#define LCSR0_BS (1 << 9) /* branch status */ -#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ - -#define LCSR1_SOF1 (1 << 0) -#define LCSR1_SOF2 (1 << 1) -#define LCSR1_SOF3 (1 << 2) -#define LCSR1_SOF4 (1 << 3) -#define LCSR1_SOF5 (1 << 4) -#define LCSR1_SOF6 (1 << 5) - -#define LCSR1_EOF1 (1 << 8) -#define LCSR1_EOF2 (1 << 9) -#define LCSR1_EOF3 (1 << 10) -#define LCSR1_EOF4 (1 << 11) -#define LCSR1_EOF5 (1 << 12) -#define LCSR1_EOF6 (1 << 13) - -#define LCSR1_BS1 (1 << 16) -#define LCSR1_BS2 (1 << 17) -#define LCSR1_BS3 (1 << 18) -#define LCSR1_BS4 (1 << 19) -#define LCSR1_BS5 (1 << 20) -#define LCSR1_BS6 (1 << 21) - -#define LCSR1_IU2 (1 << 25) -#define LCSR1_IU3 (1 << 26) -#define LCSR1_IU4 (1 << 27) -#define LCSR1_IU5 (1 << 28) -#define LCSR1_IU6 (1 << 29) - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_CPU_PXA27X) -#define LDCMD_SOFINT (1 << 22) -#define LDCMD_EOFINT (1 << 21) -#endif - -/* - * Memory controller - */ - -#ifdef CONFIG_CPU_MONAHANS - -/* PXA3xx */ - -/* Static Memory Controller Registers */ -#define MSC0 0x4A000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4A00000C /* Static Memory Control Register 1 */ -#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */ -#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */ -#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */ -#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */ -#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */ -#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */ -#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */ -#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */ -#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */ -#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */ - -/* Dynamic Memory Controller Registers */ -#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ -#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */ -#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */ -#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */ -#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */ -#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */ -#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */ -#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */ -#define EMPI 0x48100090 /* EMPI Control Register */ -#define RCOMP 0x48100100 -#define PAD_MA 0x48100110 -#define PAD_MDMSB 0x48100114 -#define PAD_MDLSB 0x48100118 -#define PAD_DMEM 0x4810011c -#define PAD_SDCLK 0x48100120 -#define PAD_SDCS 0x48100124 -#define PAD_SMEM 0x48100128 -#define PAD_SCLK 0x4810012C -#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */ - -/* Some frequently used bits */ -#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ -#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */ -#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */ -#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */ - -#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */ -#define MDCNFG_DTC_1 0x100 -#define MDCNFG_DTC_2 0x200 -#define MDCNFG_DTC_3 0x300 - -#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */ -#define MDCNFG_DRAC_13 0x20 -#define MDCNFG_DRAC_14 0x40 - -#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */ -#define MDCNFG_DCAC_10 0x08 -#define MDCNFG_DCAC_11 0x10 - -#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */ -#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */ -#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */ - - -/* Data Flash Controller Registers */ - -#define NDCR 0x43100000 /* Data Flash Control register */ -#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ -/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ -#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ -/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ -#define NDSR 0x43100014 /* Data Controller Status Register */ -#define NDPCR 0x43100018 /* Data Controller Page Count Register */ -#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */ -#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */ -#define NDDB 0x43100040 /* Data Controller Data Buffer */ -#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */ -#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */ -#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */ - -#define NDCR_SPARE_EN (0x1<<31) -#define NDCR_ECC_EN (0x1<<30) -#define NDCR_DMA_EN (0x1<<29) -#define NDCR_ND_RUN (0x1<<28) -#define NDCR_DWIDTH_C (0x1<<27) -#define NDCR_DWIDTH_M (0x1<<26) -#define NDCR_PAGE_SZ (0x3<<24) -#define NDCR_NCSX (0x1<<23) -#define NDCR_ND_STOP (0x1<<22) -/* reserved: - * #define NDCR_ND_MODE (0x3<<21) - * #define NDCR_NAND_MODE 0x0 */ -#define NDCR_CLR_PG_CNT (0x1<<20) -#define NDCR_CLR_ECC (0x1<<19) -#define NDCR_RD_ID_CNT (0x7<<16) -#define NDCR_RA_START (0x1<<15) -#define NDCR_PG_PER_BLK (0x1<<14) -#define NDCR_ND_ARB_EN (0x1<<12) -#define NDCR_RDYM (0x1<<11) -#define NDCR_CS0_PAGEDM (0x1<<10) -#define NDCR_CS1_PAGEDM (0x1<<9) -#define NDCR_CS0_CMDDM (0x1<<8) -#define NDCR_CS1_CMDDM (0x1<<7) -#define NDCR_CS0_BBDM (0x1<<6) -#define NDCR_CS1_BBDM (0x1<<5) -#define NDCR_DBERRM (0x1<<4) -#define NDCR_SBERRM (0x1<<3) -#define NDCR_WRDREQM (0x1<<2) -#define NDCR_RDDREQM (0x1<<1) -#define NDCR_WRCMDREQM (0x1) - -#define NDSR_RDY (0x1<<11) -#define NDSR_CS0_PAGED (0x1<<10) -#define NDSR_CS1_PAGED (0x1<<9) -#define NDSR_CS0_CMDD (0x1<<8) -#define NDSR_CS1_CMDD (0x1<<7) -#define NDSR_CS0_BBD (0x1<<6) -#define NDSR_CS1_BBD (0x1<<5) -#define NDSR_DBERR (0x1<<4) -#define NDSR_SBERR (0x1<<3) -#define NDSR_WRDREQ (0x1<<2) -#define NDSR_RDDREQ (0x1<<1) -#define NDSR_WRCMDREQ (0x1) - -#define NDCB0_AUTO_RS (0x1<<25) -#define NDCB0_CSEL (0x1<<24) -#define NDCB0_CMD_TYPE (0x7<<21) -#define NDCB0_NC (0x1<<20) -#define NDCB0_DBC (0x1<<19) -#define NDCB0_ADDR_CYC (0x7<<16) -#define NDCB0_CMD2 (0xff<<8) -#define NDCB0_CMD1 (0xff) -#define MCMEM(s) MCMEM0 -#define MCATT(s) MCATT0 -#define MCIO(s) MCIO0 -#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ - -/* Maximum values for NAND Interface Timing Registers in DFC clock - * periods */ -#define DFC_MAX_tCH 7 -#define DFC_MAX_tCS 7 -#define DFC_MAX_tWH 7 -#define DFC_MAX_tWP 7 -#define DFC_MAX_tRH 7 -#define DFC_MAX_tRP 15 -#define DFC_MAX_tR 65535 -#define DFC_MAX_tWHR 15 -#define DFC_MAX_tAR 15 - -#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ -#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ - -#else /* CONFIG_CPU_MONAHANS */ - -/* PXA2xx */ - -#define MEMC_BASE 0x48000000 /* Base of Memory Controller */ -#define MDCNFG_OFFSET 0x0 -#define MDREFR_OFFSET 0x4 -#define MSC0_OFFSET 0x8 -#define MSC1_OFFSET 0xC -#define MSC2_OFFSET 0x10 -#define MECR_OFFSET 0x14 -#define SXLCR_OFFSET 0x18 -#define SXCNFG_OFFSET 0x1C -#define FLYCNFG_OFFSET 0x20 -#define SXMRS_OFFSET 0x24 -#define MCMEM0_OFFSET 0x28 -#define MCMEM1_OFFSET 0x2C -#define MCATT0_OFFSET 0x30 -#define MCATT1_OFFSET 0x34 -#define MCIO0_OFFSET 0x38 -#define MCIO1_OFFSET 0x3C -#define MDMRS_OFFSET 0x40 - -#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ -#define MDCNFG_DE0 0x00000001 -#define MDCNFG_DE1 0x00000002 -#define MDCNFG_DE2 0x00010000 -#define MDCNFG_DE3 0x00020000 -#define MDCNFG_DWID0 0x00000004 - -#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */ -#define MSC0 0x48000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4800000C /* Static Memory Control Register 1 */ -#define MSC2 0x48000010 /* Static Memory Control Register 2 */ -#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */ -#define FLYCNFG 0x48000020 -#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */ -#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ -#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -#if defined(CONFIG_CPU_PXA27X) - -#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - -#endif /* CONFIG_CPU_PXA27X */ - -/* LCD registers */ -#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ -#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ -#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */ -#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */ -#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */ -#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */ -#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */ -#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */ -#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */ -#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */ -#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */ -#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */ -#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */ -#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */ -#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */ -#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */ -#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */ -#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */ -#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */ -#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */ -#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */ - -#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */ -#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */ -#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */ -#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */ -#define CCR 0x44000090 /* Cursor Control Register */ - -#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ -#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */ - -#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ -#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ - -#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ -#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ - -#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ -#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ - -#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ -#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ -#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ -#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ -#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ -#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ - -#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ -#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ -#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ - -#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ -#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ -#define CCR_CEN (1<<31) /* Enable bit for Cursor */ - -/* Keypad controller */ - -#define KPC 0x41500000 /* Keypad Interface Control register */ -#define KPDK 0x41500008 /* Keypad Interface Direct Key register */ -#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */ -#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */ -#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */ -#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ -#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ -#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ -#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ -#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */ - -#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ -#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ -#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ -#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ -#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ -#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ -#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ -#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ -#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ -#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ -#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ -#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ -#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ -#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ -#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ -#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ -#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ -#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ -#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ - -#define KPDK_DKP (0x1 << 31) -#define KPDK_DK7 (0x1 << 7) -#define KPDK_DK6 (0x1 << 6) -#define KPDK_DK5 (0x1 << 5) -#define KPDK_DK4 (0x1 << 4) -#define KPDK_DK3 (0x1 << 3) -#define KPDK_DK2 (0x1 << 2) -#define KPDK_DK1 (0x1 << 1) -#define KPDK_DK0 (0x1 << 0) - -#define KPREC_OF1 (0x1 << 31) -#define kPREC_UF1 (0x1 << 30) -#define KPREC_OF0 (0x1 << 15) -#define KPREC_UF0 (0x1 << 14) - -#define KPMK_MKP (0x1 << 31) -#define KPAS_SO (0x1 << 31) -#define KPASMKPx_SO (0x1 << 31) - -#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR 0x40F00034 -#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */ -#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */ -#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 0x40A00080 /* */ -#define OSCR4 0x40A00040 /* OS Timer Counter Register */ -#define OMCR4 0x40A000C0 /* */ - -#endif /* CONFIG_CPU_PXA27X */ - -#endif /* _PXA_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h deleted file mode 100644 index 428a848..0000000 --- a/arch/arm/include/asm/arch-pxa/pxa.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA common functions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __PXA_H__ -#define __PXA_H__ - -#define PXA255_A0 0x00000106 -#define PXA250_C0 0x00000105 -#define PXA250_B2 0x00000104 -#define PXA250_B1 0x00000103 -#define PXA250_B0 0x00000102 -#define PXA250_A1 0x00000101 -#define PXA250_A0 0x00000100 -#define PXA210_C0 0x00000125 -#define PXA210_B2 0x00000124 -#define PXA210_B1 0x00000123 -#define PXA210_B0 0x00000122 - -int cpu_is_pxa25x(void); -int cpu_is_pxa27x(void); -uint32_t pxa_get_cpu_revision(void); -void pxa2xx_dram_init(void); - -#endif /* __PXA_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-mmc.h b/arch/arm/include/asm/arch-pxa/regs-mmc.h deleted file mode 100644 index 6d9a736..0000000 --- a/arch/arm/include/asm/arch-pxa/regs-mmc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __REGS_MMC_H__ -#define __REGS_MMC_H__ - -#define MMC0_BASE 0x41100000 -#define MMC1_BASE 0x42000000 - -int pxa_mmc_register(int card_index); - -struct pxa_mmc_regs { - uint32_t strpcl; - uint32_t stat; - uint32_t clkrt; - uint32_t spi; - uint32_t cmdat; - uint32_t resto; - uint32_t rdto; - uint32_t blklen; - uint32_t nob; - uint32_t prtbuf; - uint32_t i_mask; - uint32_t i_reg; - uint32_t cmd; - uint32_t argh; - uint32_t argl; - uint32_t res; - uint32_t rxfifo; - uint32_t txfifo; -}; - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (1 << 0) -#define MMC_STRPCL_START_CLK (1 << 1) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (1 << 13) -#define MMC_STAT_PRG_DONE (1 << 12) -#define MMC_STAT_DATA_TRAN_DONE (1 << 11) -#define MMC_STAT_CLK_EN (1 << 8) -#define MMC_STAT_RECV_FIFO_FULL (1 << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) -#define MMC_STAT_RES_CRC_ERROR (1 << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) -#define MMC_STAT_CRC_READ_ERROR (1 << 3) -#define MMC_STAT_CRC_WRITE_ERROR (1 << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) -#define MMC_STAT_READ_TIME_OUT (1 << 0) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ 0 -#define MMC_CLKRT_10MHZ 1 -#define MMC_CLKRT_5MHZ 2 -#define MMC_CLKRT_2_5MHZ 3 -#define MMC_CLKRT_1_25MHZ 4 -#define MMC_CLKRT_0_625MHZ 5 -#define MMC_CLKRT_0_3125MHZ 6 - -/* MMC_SPI */ -#define MMC_SPI_EN (1 << 0) -#define MMC_SPI_CS_EN (1 << 2) -#define MMC_SPI_CS_ADDRESS (1 << 3) -#define MMC_SPI_CRC_ON (1 << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (1 << 8) -#define MMC_CMDAT_MMC_DMA_EN (1 << 7) -#define MMC_CMDAT_INIT (1 << 6) -#define MMC_CMDAT_BUSY (1 << 5) -#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) -#define MMC_CMDAT_STREAM (1 << 4) -#define MMC_CMDAT_WRITE (1 << 3) -#define MMC_CMDAT_DATA_EN (1 << 2) -#define MMC_CMDAT_R0 0 -#define MMC_CMDAT_R1 1 -#define MMC_CMDAT_R2 2 -#define MMC_CMDAT_R3 3 - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX_MASK 0x7f - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX_MASK 0xffff - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX_MASK 0x3ff - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (1 << 0) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_MASK_CLK_IS_OFF (1 << 4) -#define MMC_I_MASK_STOP_CMD (1 << 3) -#define MMC_I_MASK_END_CMD_RES (1 << 2) -#define MMC_I_MASK_PRG_DONE (1 << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) -#define MMC_I_MASK_ALL 0x7f - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_REG_CLK_IS_OFF (1 << 4) -#define MMC_I_REG_STOP_CMD (1 << 3) -#define MMC_I_REG_END_CMD_RES (1 << 2) -#define MMC_I_REG_PRG_DONE (1 << 1) -#define MMC_I_REG_DATA_TRAN_DONE (1 << 0) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX 0x6f - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -#endif /* __REGS_MMC_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h deleted file mode 100644 index bdd0a47..0000000 --- a/arch/arm/include/asm/arch-pxa/regs-uart.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __REGS_UART_H__ -#define __REGS_UART_H__ - -#define FFUART_BASE 0x40100000 -#define BTUART_BASE 0x40200000 -#define STUART_BASE 0x40700000 -#define HWUART_BASE 0x41600000 - -struct pxa_uart_regs { - union { - uint32_t thr; - uint32_t rbr; - uint32_t dll; - }; - union { - uint32_t ier; - uint32_t dlh; - }; - union { - uint32_t fcr; - uint32_t iir; - }; - uint32_t lcr; - uint32_t mcr; - uint32_t lsr; - uint32_t msr; - uint32_t spr; - uint32_t isr; -}; - -#define IER_DMAE (1 << 7) -#define IER_UUE (1 << 6) -#define IER_NRZE (1 << 5) -#define IER_RTIOE (1 << 4) -#define IER_MIE (1 << 3) -#define IER_RLSE (1 << 2) -#define IER_TIE (1 << 1) -#define IER_RAVIE (1 << 0) - -#define IIR_FIFOES1 (1 << 7) -#define IIR_FIFOES0 (1 << 6) -#define IIR_TOD (1 << 3) -#define IIR_IID2 (1 << 2) -#define IIR_IID1 (1 << 1) -#define IIR_IP (1 << 0) - -#define FCR_ITL2 (1 << 7) -#define FCR_ITL1 (1 << 6) -#define FCR_RESETTF (1 << 2) -#define FCR_RESETRF (1 << 1) -#define FCR_TRFIFOE (1 << 0) -#define FCR_ITL_1 0 -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) -#define LCR_SB (1 << 6) -#define LCR_STKYP (1 << 5) -#define LCR_EPS (1 << 4) -#define LCR_PEN (1 << 3) -#define LCR_STB (1 << 2) -#define LCR_WLS1 (1 << 1) -#define LCR_WLS0 (1 << 0) - -#define LSR_FIFOE (1 << 7) -#define LSR_TEMT (1 << 6) -#define LSR_TDRQ (1 << 5) -#define LSR_BI (1 << 4) -#define LSR_FE (1 << 3) -#define LSR_PE (1 << 2) -#define LSR_OE (1 << 1) -#define LSR_DR (1 << 0) - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) -#define MCR_OUT1 (1 << 2) -#define MCR_RTS (1 << 1) -#define MCR_DTR (1 << 0) - -#define MSR_DCD (1 << 7) -#define MSR_RI (1 << 6) -#define MSR_DSR (1 << 5) -#define MSR_CTS (1 << 4) -#define MSR_DDCD (1 << 3) -#define MSR_TERI (1 << 2) -#define MSR_DDSR (1 << 1) -#define MSR_DCTS (1 << 0) - -#endif /* __REGS_UART_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-usb.h b/arch/arm/include/asm/arch-pxa/regs-usb.h deleted file mode 100644 index e46887c..0000000 --- a/arch/arm/include/asm/arch-pxa/regs-usb.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * PXA25x UDC definitions - * - * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com> - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct pxa25x_udc_regs { - /* UDC Control Register */ - uint32_t udccr; /* 0x000 */ - uint32_t reserved1; - - /* UDC Control Function Register */ - uint32_t udccfr; /* 0x008 */ - uint32_t reserved2; - - /* UDC Endpoint Control/Status Registers */ - uint32_t udccs[16]; /* 0x010 - 0x04c */ - - /* UDC Interrupt Control/Status Registers */ - uint32_t uicr0; /* 0x050 */ - uint32_t uicr1; /* 0x054 */ - uint32_t usir0; /* 0x058 */ - uint32_t usir1; /* 0x05c */ - - /* UDC Frame Number/Byte Count Registers */ - uint32_t ufnrh; /* 0x060 */ - uint32_t ufnrl; /* 0x064 */ - uint32_t ubcr2; /* 0x068 */ - uint32_t ubcr4; /* 0x06c */ - uint32_t ubcr7; /* 0x070 */ - uint32_t ubcr9; /* 0x074 */ - uint32_t ubcr12; /* 0x078 */ - uint32_t ubcr14; /* 0x07c */ - - /* UDC Endpoint Data Registers */ - uint32_t uddr0; /* 0x080 */ - uint32_t reserved3[7]; - uint32_t uddr5; /* 0x0a0 */ - uint32_t reserved4[7]; - uint32_t uddr10; /* 0x0c0 */ - uint32_t reserved5[7]; - uint32_t uddr15; /* 0x0e0 */ - uint32_t reserved6[7]; - uint32_t uddr1; /* 0x100 */ - uint32_t reserved7[31]; - uint32_t uddr2; /* 0x180 */ - uint32_t reserved8[31]; - uint32_t uddr3; /* 0x200 */ - uint32_t reserved9[127]; - uint32_t uddr4; /* 0x400 */ - uint32_t reserved10[127]; - uint32_t uddr6; /* 0x600 */ - uint32_t reserved11[31]; - uint32_t uddr7; /* 0x680 */ - uint32_t reserved12[31]; - uint32_t uddr8; /* 0x700 */ - uint32_t reserved13[127]; - uint32_t uddr9; /* 0x900 */ - uint32_t reserved14[127]; - uint32_t uddr11; /* 0xb00 */ - uint32_t reserved15[31]; - uint32_t uddr12; /* 0xb80 */ - uint32_t reserved16[31]; - uint32_t uddr13; /* 0xc00 */ - uint32_t reserved17[127]; - uint32_t uddr14; /* 0xe00 */ - -}; - -#define PXA25X_UDC_BASE 0x40600000 - -#define UDCCR_UDE (1 << 0) -#define UDCCR_UDA (1 << 1) -#define UDCCR_RSM (1 << 2) -#define UDCCR_RESIR (1 << 3) -#define UDCCR_SUSIR (1 << 4) -#define UDCCR_SRM (1 << 5) -#define UDCCR_RSTIR (1 << 6) -#define UDCCR_REM (1 << 7) - -/* Bulk IN endpoint 1/6/11 */ -#define UDCCS_BI_TSP (1 << 7) -#define UDCCS_BI_FST (1 << 5) -#define UDCCS_BI_SST (1 << 4) -#define UDCCS_BI_TUR (1 << 3) -#define UDCCS_BI_FTF (1 << 2) -#define UDCCS_BI_TPC (1 << 1) -#define UDCCS_BI_TFS (1 << 0) - -/* Bulk OUT endpoint 2/7/12 */ -#define UDCCS_BO_RSP (1 << 7) -#define UDCCS_BO_RNE (1 << 6) -#define UDCCS_BO_FST (1 << 5) -#define UDCCS_BO_SST (1 << 4) -#define UDCCS_BO_DME (1 << 3) -#define UDCCS_BO_RPC (1 << 1) -#define UDCCS_BO_RFS (1 << 0) - -/* Isochronous OUT endpoint 4/9/14 */ -#define UDCCS_IO_RSP (1 << 7) -#define UDCCS_IO_RNE (1 << 6) -#define UDCCS_IO_DME (1 << 3) -#define UDCCS_IO_ROF (1 << 2) -#define UDCCS_IO_RPC (1 << 1) -#define UDCCS_IO_RFS (1 << 0) - -/* Control endpoint 0 */ -#define UDCCS0_OPR (1 << 0) -#define UDCCS0_IPR (1 << 1) -#define UDCCS0_FTF (1 << 2) -#define UDCCS0_DRWF (1 << 3) -#define UDCCS0_SST (1 << 4) -#define UDCCS0_FST (1 << 5) -#define UDCCS0_RNE (1 << 6) -#define UDCCS0_SA (1 << 7) - -#define UICR0_IM0 (1 << 0) - -#define USIR0_IR0 (1 << 0) -#define USIR0_IR1 (1 << 1) -#define USIR0_IR2 (1 << 2) -#define USIR0_IR3 (1 << 3) -#define USIR0_IR4 (1 << 4) -#define USIR0_IR5 (1 << 5) -#define USIR0_IR6 (1 << 6) -#define USIR0_IR7 (1 << 7) - -#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ -#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ -/* - * Intel(R) PXA255 Processor Specification, September 2003 (page 31) - * define new "must be one" bits in UDCCFR (see Table 12-13.) - */ -#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) - -#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ -#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ -#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ -#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ -#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ - -#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-rk3036/boot0.h b/arch/arm/include/asm/arch-rk3036/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk3036/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3036/gpio.h b/arch/arm/include/asm/arch-rk3036/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk3036/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3128/boot0.h b/arch/arm/include/asm/arch-rk3128/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk3128/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3128/gpio.h b/arch/arm/include/asm/arch-rk3128/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk3128/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3188/boot0.h b/arch/arm/include/asm/arch-rk3188/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk3188/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3188/gpio.h b/arch/arm/include/asm/arch-rk3188/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk3188/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk322x/boot0.h b/arch/arm/include/asm/arch-rk322x/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk322x/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk322x/gpio.h b/arch/arm/include/asm/arch-rk322x/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk322x/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3288/boot0.h b/arch/arm/include/asm/arch-rk3288/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk3288/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3288/gpio.h b/arch/arm/include/asm/arch-rk3288/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk3288/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3328/boot0.h b/arch/arm/include/asm/arch-rk3328/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk3328/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3328/gpio.h b/arch/arm/include/asm/arch-rk3328/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk3328/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3368/boot0.h b/arch/arm/include/asm/arch-rk3368/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk3368/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3368/gpio.h b/arch/arm/include/asm/arch-rk3368/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk3368/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3399/boot0.h b/arch/arm/include/asm/arch-rk3399/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rk3399/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rk3399/gpio.h b/arch/arm/include/asm/arch-rk3399/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rk3399/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h deleted file mode 100644 index 0c375e5..0000000 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -/* - * Execution starts on the instruction following this 4-byte header - * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This - * magic constant will be written into the final image by the rkimage - * tool, but we need to reserve space for it here. - * - * To make life easier for everyone, we build the SPL binary with - * space for this 4-byte header already included in the binary. - */ -#ifdef CONFIG_SPL_BUILD - /* - * We need to add 4 bytes of space for the 'RK33' at the - * beginning of the executable. However, as we want to keep - * this generic and make it applicable to builds that are like - * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no - * TPL, but extra space needed in the SPL), we simply insert - * a branch-to-next-instruction-word with the expectation that - * the first one may be overwritten, if this is the first stage - * contained in the final image created with mkimage)... - */ - b 1f /* if overwritten, entry-address is at the next word */ -1: -#endif -#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) - adr r3, entry_counter - ldr r0, [r3] - cmp r0, #1 /* check if entry_counter == 1 */ - beq reset /* regular bootup */ - add r0, #1 - str r0, [r3] /* increment the entry_counter in memory */ - mov r0, #0 /* return 0 to the BROM to signal 'OK' */ - bx lr /* return control to the BROM */ -entry_counter: - .word 0 -#endif - -#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64)) - /* U-Boot proper of armv7 do not need this */ - b reset -#endif - -#if !defined(CONFIG_ARM64) - /* - * For armv7, the addr '_start' will used as vector start address - * and write to VBAR register, which needs to aligned to 0x20. - */ - .align(5), 0x0 -_start: - ARM_VECTORS -#endif - -#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \ - (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) - .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ -#endif diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h deleted file mode 100644 index 6b2a610..0000000 --- a/arch/arm/include/asm/arch-rockchip/boot_mode.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __REBOOT_MODE_H -#define __REBOOT_MODE_H - -/* high 24 bits is tag, low 8 bits is type */ -#define REBOOT_FLAG 0x5242C300 -/* normal boot */ -#define BOOT_NORMAL (REBOOT_FLAG + 0) -/* enter loader rockusb mode */ -#define BOOT_LOADER (REBOOT_FLAG + 1) -/* enter recovery */ -#define BOOT_RECOVERY (REBOOT_FLAG + 3) -/* enter fastboot mode */ -#define BOOT_FASTBOOT (REBOOT_FLAG + 9) -/* enter charging mode */ -#define BOOT_CHARGING (REBOOT_FLAG + 11) -/* enter usb mass storage mode */ -#define BOOT_UMS (REBOOT_FLAG + 12) -/* enter bootrom download mode */ -#define BOOT_BROM_DOWNLOAD 0xEF08A53C - -#ifndef __ASSEMBLY__ -int setup_boot_mode(void); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h deleted file mode 100644 index 0da78f3..0000000 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de> - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#ifndef _ASM_ARCH_BOOTROM_H -#define _ASM_ARCH_BOOTROM_H - -/* - * Saved Stack pointer address. - * Access might be needed in some special cases. - */ -extern u32 SAVE_SP_ADDR; - -/** - * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a - * result code - * - * Transfer control back to the Rockchip BROM, restoring necessary - * register context and passing a command/result code to the BROM - * to instruct its next actions (e.g. continue boot sequence, enter - * download mode, ...). - * - * This function does not return. - * - * @brom_cmd: indicates how the bootrom should continue the boot - * sequence (e.g. load the next stage) - */ -enum rockchip_bootrom_cmd { - /* - * These can not start at 0, as 0 has a special meaning - * for setjmp(). - */ - - BROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */ - BROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */ -}; - -void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd); - -/** - * Boot-device identifiers as used by the BROM - */ -enum { - BROM_BOOTSOURCE_NAND = 1, - BROM_BOOTSOURCE_EMMC = 2, - BROM_BOOTSOURCE_SPINOR = 3, - BROM_BOOTSOURCE_SPINAND = 4, - BROM_BOOTSOURCE_SD = 5, - BROM_BOOTSOURCE_USB = 10, - BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB -}; - -extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; - -/** - * Locations of the boot-device identifier in SRAM - */ -#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10) - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h deleted file mode 100644 index 0eb19ca..0000000 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef _ASM_ARCH_CLOCK_H -#define _ASM_ARCH_CLOCK_H - -/* define pll mode */ -#define RKCLK_PLL_MODE_SLOW 0 -#define RKCLK_PLL_MODE_NORMAL 1 - -enum { - ROCKCHIP_SYSCON_NOC, - ROCKCHIP_SYSCON_GRF, - ROCKCHIP_SYSCON_SGRF, - ROCKCHIP_SYSCON_PMU, - ROCKCHIP_SYSCON_PMUGRF, - ROCKCHIP_SYSCON_PMUSGRF, - ROCKCHIP_SYSCON_CIC, - ROCKCHIP_SYSCON_MSCH, -}; - -/* Standard Rockchip clock numbers */ -enum rk_clk_id { - CLK_OSC, - CLK_ARM, - CLK_DDR, - CLK_CODEC, - CLK_GENERAL, - CLK_NEW, - - CLK_COUNT, -}; - -static inline int rk_pll_id(enum rk_clk_id clk_id) -{ - return clk_id - 1; -} - -struct sysreset_reg { - unsigned int glb_srst_fst_value; - unsigned int glb_srst_snd_value; -}; - -struct softreset_reg { - void __iomem *base; - unsigned int sf_reset_offset; - unsigned int sf_reset_num; -}; - -/** - * clk_get_divisor() - Calculate the required clock divisior - * - * Given an input rate and a required output_rate, calculate the Rockchip - * divisor needed to achieve this. - * - * @input_rate: Input clock rate in Hz - * @output_rate: Output clock rate in Hz - * @return divisor register value to use - */ -static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) -{ - uint clk_div; - - clk_div = input_rate / output_rate; - clk_div = (clk_div + 1) & 0xfffe; - - return clk_div; -} - -/** - * rockchip_get_cru() - get a pointer to the clock/reset unit registers - * - * @return pointer to registers, or -ve error on error - */ -void *rockchip_get_cru(void); - -/** - * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers - * - * @return pointer to registers, or -ve error on error - */ -void *rockchip_get_pmucru(void); - -struct rk3288_cru; -struct rk3288_grf; - -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); - -int rockchip_get_clk(struct udevice **devp); - -/* - * rockchip_reset_bind() - Bind soft reset device as child of clock device - * - * @pdev: clock udevice - * @reg_offset: the first offset in cru for softreset registers - * @reg_number: the reg numbers of softreset registers - * @return 0 success, or error value - */ -int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h deleted file mode 100644 index 4722522..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ -#ifndef _ASM_ARCH_CRU_RK3036_H -#define _ASM_ARCH_CRU_RK3036_H - -#include <common.h> - -#define OSC_HZ (24 * 1000 * 1000) - -#define APLL_HZ (600 * 1000000) -#define GPLL_HZ (594 * 1000000) - -#define CORE_PERI_HZ 150000000 -#define CORE_ACLK_HZ 300000000 - -#define BUS_ACLK_HZ 148500000 -#define BUS_HCLK_HZ 148500000 -#define BUS_PCLK_HZ 74250000 - -#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 - -/* Private data for the clock driver - used by rockchip_get_cru() */ -struct rk3036_clk_priv { - struct rk3036_cru *cru; - ulong rate; -}; - -struct rk3036_cru { - struct rk3036_pll { - unsigned int con0; - unsigned int con1; - unsigned int con2; - unsigned int con3; - } pll[4]; - unsigned int cru_mode_con; - unsigned int cru_clksel_con[35]; - unsigned int cru_clkgate_con[11]; - unsigned int reserved; - unsigned int cru_glb_srst_fst_value; - unsigned int cru_glb_srst_snd_value; - unsigned int reserved1[2]; - unsigned int cru_softrst_con[9]; - unsigned int cru_misc_con; - unsigned int reserved2[2]; - unsigned int cru_glb_cnt_th; - unsigned int cru_sdmmc_con[2]; - unsigned int cru_sdio_con[2]; - unsigned int cru_emmc_con[2]; - unsigned int reserved3; - unsigned int cru_rst_st; - unsigned int reserved4[0x23]; - unsigned int cru_pll_mask_con; -}; -check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); - -struct pll_div { - u32 refdiv; - u32 fbdiv; - u32 postdiv1; - u32 postdiv2; - u32 frac; -}; - -enum { - /* PLLCON0*/ - PLL_POSTDIV1_SHIFT = 12, - PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, - PLL_FBDIV_SHIFT = 0, - PLL_FBDIV_MASK = 0xfff, - - /* PLLCON1 */ - PLL_RST_SHIFT = 14, - PLL_DSMPD_SHIFT = 12, - PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, - PLL_LOCK_STATUS_SHIFT = 10, - PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, - PLL_POSTDIV2_SHIFT = 6, - PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, - PLL_REFDIV_SHIFT = 0, - PLL_REFDIV_MASK = 0x3f, - - /* CRU_MODE */ - GPLL_MODE_SHIFT = 12, - GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, - GPLL_MODE_SLOW = 0, - GPLL_MODE_NORM, - GPLL_MODE_DEEP, - DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, - DPLL_MODE_SLOW = 0, - DPLL_MODE_NORM, - APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, - APLL_MODE_SLOW = 0, - APLL_MODE_NORM, - - /* CRU_CLK_SEL0_CON */ - BUS_ACLK_PLL_SEL_SHIFT = 14, - BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, - BUS_ACLK_PLL_SEL_APLL = 0, - BUS_ACLK_PLL_SEL_DPLL, - BUS_ACLK_PLL_SEL_GPLL, - BUS_ACLK_DIV_SHIFT = 8, - BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, - CORE_CLK_PLL_SEL_SHIFT = 7, - CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, - CORE_CLK_PLL_SEL_APLL = 0, - CORE_CLK_PLL_SEL_GPLL, - CORE_DIV_CON_SHIFT = 0, - CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, - - /* CRU_CLK_SEL1_CON */ - BUS_PCLK_DIV_SHIFT = 12, - BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, - BUS_HCLK_DIV_SHIFT = 8, - BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, - CORE_ACLK_DIV_SHIFT = 4, - CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, - CORE_PERI_DIV_SHIFT = 0, - CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, - - /* CRU_CLKSEL10_CON */ - PERI_PLL_SEL_SHIFT = 14, - PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, - PERI_PLL_APLL = 0, - PERI_PLL_DPLL, - PERI_PLL_GPLL, - PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, - PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, - PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, - - /* CRU_CLKSEL11_CON */ - SDIO_DIV_SHIFT = 8, - SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, - MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, - - /* CRU_CLKSEL12_CON */ - EMMC_PLL_SHIFT = 12, - EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, - EMMC_SEL_APLL = 0, - EMMC_SEL_DPLL, - EMMC_SEL_GPLL, - EMMC_SEL_24M, - SDIO_PLL_SHIFT = 10, - SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, - SDIO_SEL_APLL = 0, - SDIO_SEL_DPLL, - SDIO_SEL_GPLL, - SDIO_SEL_24M, - MMC0_PLL_SHIFT = 8, - MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, - MMC0_SEL_APLL = 0, - MMC0_SEL_DPLL, - MMC0_SEL_GPLL, - MMC0_SEL_24M, - EMMC_DIV_SHIFT = 0, - EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, - - /* CRU_SOFTRST5_CON */ - DDRCTRL_PSRST_SHIFT = 11, - DDRCTRL_SRST_SHIFT = 10, - DDRPHY_PSRST_SHIFT = 9, - DDRPHY_SRST_SHIFT = 8, -}; -#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h deleted file mode 100644 index b856560..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h +++ /dev/null @@ -1,211 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Rockchip Electronics Co., Ltd - */ - -#ifndef _ASM_ARCH_CRU_RK3128_H -#define _ASM_ARCH_CRU_RK3128_H - -#include <common.h> - -#define MHz 1000000 -#define OSC_HZ (24 * MHz) - -#define APLL_HZ (600 * MHz) -#define GPLL_HZ (594 * MHz) - -#define CORE_PERI_HZ 150000000 -#define CORE_ACLK_HZ 300000000 - -#define BUS_ACLK_HZ 148500000 -#define BUS_HCLK_HZ 148500000 -#define BUS_PCLK_HZ 74250000 - -#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 - -/* Private data for the clock driver - used by rockchip_get_cru() */ -struct rk3128_clk_priv { - struct rk3128_cru *cru; -}; - -struct rk3128_cru { - struct rk3128_pll { - unsigned int con0; - unsigned int con1; - unsigned int con2; - unsigned int con3; - } pll[4]; - unsigned int cru_mode_con; - unsigned int cru_clksel_con[35]; - unsigned int cru_clkgate_con[11]; - unsigned int reserved; - unsigned int cru_glb_srst_fst_value; - unsigned int cru_glb_srst_snd_value; - unsigned int reserved1[2]; - unsigned int cru_softrst_con[9]; - unsigned int cru_misc_con; - unsigned int reserved2[2]; - unsigned int cru_glb_cnt_th; - unsigned int reserved3[3]; - unsigned int cru_glb_rst_st; - unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; - unsigned int cru_sdmmc_con[2]; - unsigned int cru_sdio_con[2]; - unsigned int reserved5[2]; - unsigned int cru_emmc_con[2]; - unsigned int reserved6[4]; - unsigned int cru_pll_prg_en; -}; -check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); - -struct pll_div { - u32 refdiv; - u32 fbdiv; - u32 postdiv1; - u32 postdiv2; - u32 frac; -}; - -enum { - /* PLLCON0*/ - PLL_POSTDIV1_SHIFT = 12, - PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, - PLL_FBDIV_SHIFT = 0, - PLL_FBDIV_MASK = 0xfff, - - /* PLLCON1 */ - PLL_RST_SHIFT = 14, - PLL_PD_SHIFT = 13, - PLL_PD_MASK = 1 << PLL_PD_SHIFT, - PLL_DSMPD_SHIFT = 12, - PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, - PLL_LOCK_STATUS_SHIFT = 10, - PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, - PLL_POSTDIV2_SHIFT = 6, - PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, - PLL_REFDIV_SHIFT = 0, - PLL_REFDIV_MASK = 0x3f, - - /* CRU_MODE */ - GPLL_MODE_SHIFT = 12, - GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, - GPLL_MODE_SLOW = 0, - GPLL_MODE_NORM, - GPLL_MODE_DEEP, - CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, - CPLL_MODE_SLOW = 0, - CPLL_MODE_NORM, - DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, - DPLL_MODE_SLOW = 0, - DPLL_MODE_NORM, - APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, - APLL_MODE_SLOW = 0, - APLL_MODE_NORM, - - /* CRU_CLK_SEL0_CON */ - BUS_ACLK_PLL_SEL_SHIFT = 14, - BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, - BUS_ACLK_PLL_SEL_CPLL = 0, - BUS_ACLK_PLL_SEL_GPLL, - BUS_ACLK_PLL_SEL_GPLL_DIV2, - BUS_ACLK_PLL_SEL_GPLL_DIV3, - BUS_ACLK_DIV_SHIFT = 8, - BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, - CORE_CLK_PLL_SEL_SHIFT = 7, - CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, - CORE_CLK_PLL_SEL_APLL = 0, - CORE_CLK_PLL_SEL_GPLL_DIV2, - CORE_DIV_CON_SHIFT = 0, - CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, - - /* CRU_CLK_SEL1_CON */ - BUS_PCLK_DIV_SHIFT = 12, - BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, - BUS_HCLK_DIV_SHIFT = 8, - BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, - CORE_ACLK_DIV_SHIFT = 4, - CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, - CORE_PERI_DIV_SHIFT = 0, - CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, - - /* CRU_CLK_SEL2_CON */ - NANDC_PLL_SEL_SHIFT = 14, - NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, - NANDC_PLL_SEL_CPLL = 0, - NANDC_PLL_SEL_GPLL, - NANDC_CLK_DIV_SHIFT = 8, - NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, - PVTM_CLK_DIV_SHIFT = 0, - PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, - - /* CRU_CLKSEL10_CON */ - PERI_PLL_SEL_SHIFT = 14, - PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT, - PERI_PLL_APLL = 0, - PERI_PLL_DPLL, - PERI_PLL_GPLL, - PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, - PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, - PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, - - /* CRU_CLKSEL11_CON */ - MMC0_PLL_SHIFT = 6, - MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, - MMC0_SEL_APLL = 0, - MMC0_SEL_GPLL, - MMC0_SEL_GPLL_DIV2, - MMC0_SEL_24M, - MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, - - /* CRU_CLKSEL12_CON */ - EMMC_PLL_SHIFT = 14, - EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, - EMMC_SEL_APLL = 0, - EMMC_SEL_GPLL, - EMMC_SEL_GPLL_DIV2, - EMMC_SEL_24M, - EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, - - /* CLKSEL_CON24 */ - SARADC_DIV_CON_SHIFT = 8, - SARADC_DIV_CON_MASK = GENMASK(15, 8), - SARADC_DIV_CON_WIDTH = 8, - - /* CRU_CLKSEL27_CON*/ - DCLK_VOP_SEL_SHIFT = 0, - DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, - DCLK_VOP_PLL_SEL_CPLL = 0, - DCLK_VOP_DIV_CON_SHIFT = 8, - DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, - - /* CRU_CLKSEL31_CON */ - VIO0_PLL_SHIFT = 5, - VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, - VI00_SEL_CPLL = 0, - VIO0_SEL_GPLL, - VIO0_DIV_SHIFT = 0, - VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, - VIO1_PLL_SHIFT = 13, - VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, - VI01_SEL_CPLL = 0, - VIO1_SEL_GPLL, - VIO1_DIV_SHIFT = 8, - VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, - - /* CRU_SOFTRST5_CON */ - DDRCTRL_PSRST_SHIFT = 11, - DDRCTRL_SRST_SHIFT = 10, - DDRPHY_PSRST_SHIFT = 9, - DDRPHY_SRST_SHIFT = 8, -}; -#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h deleted file mode 100644 index eec4815..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h +++ /dev/null @@ -1,191 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de> - */ -#ifndef _ASM_ARCH_CRU_RK3188_H -#define _ASM_ARCH_CRU_RK3188_H - -#define OSC_HZ (24 * 1000 * 1000) - -#define APLL_HZ (1608 * 1000000) -#define APLL_SAFE_HZ (600 * 1000000) -#define GPLL_HZ (594 * 1000000) -#define CPLL_HZ (384 * 1000000) - -/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ -#define CPU_ACLK_HZ 297000000 -#define CPU_HCLK_HZ 148500000 -#define CPU_PCLK_HZ 74250000 -#define CPU_H2P_HZ 74250000 - -#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 - -/* Private data for the clock driver - used by rockchip_get_cru() */ -struct rk3188_clk_priv { - struct rk3188_grf *grf; - struct rk3188_cru *cru; - ulong rate; - bool has_bwadj; -}; - -struct rk3188_cru { - struct rk3188_pll { - u32 con0; - u32 con1; - u32 con2; - u32 con3; - } pll[4]; - u32 cru_mode_con; - u32 cru_clksel_con[35]; - u32 cru_clkgate_con[10]; - u32 reserved1[2]; - u32 cru_glb_srst_fst_value; - u32 cru_glb_srst_snd_value; - u32 reserved2[2]; - u32 cru_softrst_con[9]; - u32 cru_misc_con; - u32 reserved3[2]; - u32 cru_glb_cnt_th; -}; -check_member(rk3188_cru, cru_glb_cnt_th, 0x0140); - -/* CRU_CLKSEL0_CON */ -enum { - /* a9_core_div: core = core_src / (a9_core_div + 1) */ - A9_CORE_DIV_SHIFT = 9, - A9_CORE_DIV_MASK = 0x1f, - CORE_PLL_SHIFT = 8, - CORE_PLL_MASK = 1, - CORE_PLL_SELECT_APLL = 0, - CORE_PLL_SELECT_GPLL, - - /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ - CORE_PERI_DIV_SHIFT = 6, - CORE_PERI_DIV_MASK = 3, - - /* aclk_cpu pll selection */ - CPU_ACLK_PLL_SHIFT = 5, - CPU_ACLK_PLL_MASK = 1, - CPU_ACLK_PLL_SELECT_APLL = 0, - CPU_ACLK_PLL_SELECT_GPLL, - - /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ - A9_CPU_DIV_SHIFT = 0, - A9_CPU_DIV_MASK = 0x1f, -}; - -/* CRU_CLKSEL1_CON */ -enum { - /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ - AHB2APB_DIV_SHIFT = 14, - AHB2APB_DIV_MASK = 3, - - /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ - CPU_PCLK_DIV_SHIFT = 12, - CPU_PCLK_DIV_MASK = 3, - - /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ - CPU_HCLK_DIV_SHIFT = 8, - CPU_HCLK_DIV_MASK = 3, - - /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ - CORE_ACLK_DIV_SHIFT = 3, - CORE_ACLK_DIV_MASK = 7, -}; - -/* CRU_CLKSEL10_CON */ -enum { - PERI_SEL_PLL_MASK = 1, - PERI_SEL_PLL_SHIFT = 15, - PERI_SEL_CPLL = 0, - PERI_SEL_GPLL, - - /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ - PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 3, - - /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ - PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3, - - /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ - PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f, -}; -/* CRU_CLKSEL11_CON */ -enum { - HSICPHY_DIV_SHIFT = 8, - HSICPHY_DIV_MASK = 0x3f, - - MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x3f, -}; - -/* CRU_CLKSEL12_CON */ -enum { - UART_PLL_SHIFT = 15, - UART_PLL_MASK = 1, - UART_PLL_SELECT_GENERAL = 0, - UART_PLL_SELECT_CODEC, - - EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f, - - SDIO_DIV_SHIFT = 0, - SDIO_DIV_MASK = 0x3f, -}; - -/* CRU_CLKSEL25_CON */ -enum { - SPI1_DIV_SHIFT = 8, - SPI1_DIV_MASK = 0x7f, - - SPI0_DIV_SHIFT = 0, - SPI0_DIV_MASK = 0x7f, -}; - -/* CRU_MODE_CON */ -enum { - GPLL_MODE_SHIFT = 12, - GPLL_MODE_MASK = 3, - GPLL_MODE_SLOW = 0, - GPLL_MODE_NORMAL, - GPLL_MODE_DEEP, - - CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = 3, - CPLL_MODE_SLOW = 0, - CPLL_MODE_NORMAL, - CPLL_MODE_DEEP, - - DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 3, - DPLL_MODE_SLOW = 0, - DPLL_MODE_NORMAL, - DPLL_MODE_DEEP, - - APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 3, - APLL_MODE_SLOW = 0, - APLL_MODE_NORMAL, - APLL_MODE_DEEP, -}; - -/* CRU_APLL_CON0 */ -enum { - CLKR_SHIFT = 8, - CLKR_MASK = 0x3f, - - CLKOD_SHIFT = 0, - CLKOD_MASK = 0x3f, -}; - -/* CRU_APLL_CON1 */ -enum { - CLKF_SHIFT = 0, - CLKF_MASK = 0x1fff, -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h deleted file mode 100644 index c87c830..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +++ /dev/null @@ -1,211 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ -#ifndef _ASM_ARCH_CRU_RK322X_H -#define _ASM_ARCH_CRU_RK322X_H - -#include <common.h> - -#define MHz 1000000 -#define OSC_HZ (24 * MHz) - -#define APLL_HZ (600 * MHz) -#define GPLL_HZ (594 * MHz) - -#define CORE_PERI_HZ 150000000 -#define CORE_ACLK_HZ 300000000 - -#define BUS_ACLK_HZ 148500000 -#define BUS_HCLK_HZ 148500000 -#define BUS_PCLK_HZ 74250000 - -#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 - -/* Private data for the clock driver - used by rockchip_get_cru() */ -struct rk322x_clk_priv { - struct rk322x_cru *cru; - ulong rate; -}; - -struct rk322x_cru { - struct rk322x_pll { - unsigned int con0; - unsigned int con1; - unsigned int con2; - } pll[4]; - unsigned int reserved0[4]; - unsigned int cru_mode_con; - unsigned int cru_clksel_con[35]; - unsigned int cru_clkgate_con[16]; - unsigned int cru_softrst_con[9]; - unsigned int cru_misc_con; - unsigned int reserved1[2]; - unsigned int cru_glb_cnt_th; - unsigned int reserved2[3]; - unsigned int cru_glb_rst_st; - unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; - unsigned int cru_sdmmc_con[2]; - unsigned int cru_sdio_con[2]; - unsigned int reserved4[2]; - unsigned int cru_emmc_con[2]; - unsigned int reserved5[4]; - unsigned int cru_glb_srst_fst_value; - unsigned int cru_glb_srst_snd_value; - unsigned int cru_pll_mask_con; -}; -check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); - -struct pll_div { - u32 refdiv; - u32 fbdiv; - u32 postdiv1; - u32 postdiv2; - u32 frac; -}; - -enum { - /* PLLCON0*/ - PLL_BP_SHIFT = 15, - PLL_POSTDIV1_SHIFT = 12, - PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, - PLL_FBDIV_SHIFT = 0, - PLL_FBDIV_MASK = 0xfff, - - /* PLLCON1 */ - PLL_RST_SHIFT = 14, - PLL_PD_SHIFT = 13, - PLL_PD_MASK = 1 << PLL_PD_SHIFT, - PLL_DSMPD_SHIFT = 12, - PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, - PLL_LOCK_STATUS_SHIFT = 10, - PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, - PLL_POSTDIV2_SHIFT = 6, - PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, - PLL_REFDIV_SHIFT = 0, - PLL_REFDIV_MASK = 0x3f, - - /* CRU_MODE */ - GPLL_MODE_SHIFT = 12, - GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT, - GPLL_MODE_SLOW = 0, - GPLL_MODE_NORM, - CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, - CPLL_MODE_SLOW = 0, - CPLL_MODE_NORM, - DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, - DPLL_MODE_SLOW = 0, - DPLL_MODE_NORM, - APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, - APLL_MODE_SLOW = 0, - APLL_MODE_NORM, - - /* CRU_CLK_SEL0_CON */ - BUS_ACLK_PLL_SEL_SHIFT = 13, - BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, - BUS_ACLK_PLL_SEL_APLL = 0, - BUS_ACLK_PLL_SEL_GPLL, - BUS_ACLK_PLL_SEL_HDMIPLL, - BUS_ACLK_DIV_SHIFT = 8, - BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, - CORE_CLK_PLL_SEL_SHIFT = 6, - CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, - CORE_CLK_PLL_SEL_APLL = 0, - CORE_CLK_PLL_SEL_GPLL, - CORE_CLK_PLL_SEL_DPLL, - CORE_DIV_CON_SHIFT = 0, - CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, - - /* CRU_CLK_SEL1_CON */ - BUS_PCLK_DIV_SHIFT = 12, - BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, - BUS_HCLK_DIV_SHIFT = 8, - BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, - CORE_ACLK_DIV_SHIFT = 4, - CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, - CORE_PERI_DIV_SHIFT = 0, - CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, - - /* CRU_CLKSEL5_CON */ - GMAC_OUT_PLL_SHIFT = 15, - GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, - GMAC_OUT_DIV_SHIFT = 8, - GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, - MAC_PLL_SEL_SHIFT = 7, - MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, - RMII_EXTCLK_SLE_SHIFT = 5, - RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, - RMII_EXTCLK_SEL_INT = 0, - RMII_EXTCLK_SEL_EXT, - CLK_MAC_DIV_SHIFT = 0, - CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, - - /* CRU_CLKSEL10_CON */ - PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, - PERI_PLL_SEL_SHIFT = 10, - PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, - PERI_PLL_CPLL = 0, - PERI_PLL_GPLL, - PERI_PLL_HDMIPLL, - PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, - PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, - - /* CRU_CLKSEL11_CON */ - EMMC_PLL_SHIFT = 12, - EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, - EMMC_SEL_CPLL = 0, - EMMC_SEL_GPLL, - EMMC_SEL_24M, - SDIO_PLL_SHIFT = 10, - SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, - SDIO_SEL_CPLL = 0, - SDIO_SEL_GPLL, - SDIO_SEL_24M, - MMC0_PLL_SHIFT = 8, - MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, - MMC0_SEL_CPLL = 0, - MMC0_SEL_GPLL, - MMC0_SEL_24M, - MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, - - /* CRU_CLKSEL12_CON */ - EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, - SDIO_DIV_SHIFT = 0, - SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, - - /* CRU_CLKSEL26_CON */ - DDR_CLK_PLL_SEL_SHIFT = 8, - DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, - DDR_CLK_SEL_DPLL = 0, - DDR_CLK_SEL_GPLL, - DDR_CLK_SEL_APLL, - DDR_DIV_SEL_SHIFT = 0, - DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, - - /* CRU_CLKSEL27_CON */ - VOP_DCLK_DIV_SHIFT = 8, - VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT, - VOP_PLL_SEL_SHIFT = 1, - VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT, - - /* CRU_CLKSEL29_CON */ - GMAC_CLK_SRC_SHIFT = 12, - GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, - - /* CRU_SOFTRST5_CON */ - DDRCTRL_PSRST_SHIFT = 11, - DDRCTRL_SRST_SHIFT = 10, - DDRPHY_PSRST_SHIFT = 9, - DDRPHY_SRST_SHIFT = 8, -}; -#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h deleted file mode 100644 index e891f20..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - * - * (C) Copyright 2008-2014 Rockchip Electronics - * Peter, Software Engineering, <superpeter.cai@gmail.com>. - */ -#ifndef _ASM_ARCH_CRU_RK3288_H -#define _ASM_ARCH_CRU_RK3288_H - -#define OSC_HZ (24 * 1000 * 1000) - -#define APLL_HZ (1800 * 1000000) -#define GPLL_HZ (594 * 1000000) -#define CPLL_HZ (384 * 1000000) -#define NPLL_HZ (384 * 1000000) - -/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */ -#define PD_BUS_ACLK_HZ 297000000 -#define PD_BUS_HCLK_HZ 148500000 -#define PD_BUS_PCLK_HZ 74250000 - -#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 - -/* Private data for the clock driver - used by rockchip_get_cru() */ -struct rk3288_clk_priv { - struct rk3288_grf *grf; - struct rk3288_cru *cru; - ulong rate; -}; - -struct rk3288_cru { - struct rk3288_pll { - u32 con0; - u32 con1; - u32 con2; - u32 con3; - } pll[5]; - u32 cru_mode_con; - u32 reserved0[3]; - u32 cru_clksel_con[43]; - u32 reserved1[21]; - u32 cru_clkgate_con[19]; - u32 reserved2; - u32 cru_glb_srst_fst_value; - u32 cru_glb_srst_snd_value; - u32 cru_softrst_con[12]; - u32 cru_misc_con; - u32 cru_glb_cnt_th; - u32 cru_glb_rst_con; - u32 reserved3; - u32 cru_glb_rst_st; - u32 reserved4; - u32 cru_sdmmc_con[2]; - u32 cru_sdio0_con[2]; - u32 cru_sdio1_con[2]; - u32 cru_emmc_con[2]; -}; -check_member(rk3288_cru, cru_emmc_con[1], 0x021c); - -/* CRU_CLKSEL11_CON */ -enum { - HSICPHY_DIV_SHIFT = 8, - HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT, - - MMC0_PLL_SHIFT = 6, - MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, - MMC0_PLL_SELECT_CODEC = 0, - MMC0_PLL_SELECT_GENERAL, - MMC0_PLL_SELECT_24MHZ, - - MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, -}; - -/* CRU_CLKSEL8_CON */ -enum { - I2S0_FRAC_DENOM_SHIFT = 0, - I2S0_FRAC_DENOM_MASK = 0xffff << I2S0_FRAC_DENOM_SHIFT, - I2S0_FRAC_NUMER_SHIFT = 16, - I2S0_FRAC_NUMER_MASK = 0xffffu << I2S0_FRAC_NUMER_SHIFT, -}; - -/* CRU_CLKSEL12_CON */ -enum { - EMMC_PLL_SHIFT = 0xe, - EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, - EMMC_PLL_SELECT_CODEC = 0, - EMMC_PLL_SELECT_GENERAL, - EMMC_PLL_SELECT_24MHZ, - - EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, - - SDIO0_PLL_SHIFT = 6, - SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, - SDIO0_PLL_SELECT_CODEC = 0, - SDIO0_PLL_SELECT_GENERAL, - SDIO0_PLL_SELECT_24MHZ, - - SDIO0_DIV_SHIFT = 0, - SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT, -}; - -/* CRU_CLKSEL21_CON */ -enum { - MAC_DIV_CON_SHIFT = 0xf, - MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT, - - RMII_EXTCLK_SHIFT = 4, - RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT, - RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, - RMII_EXTCLK_SELECT_EXT_CLK = 1, - - EMAC_PLL_SHIFT = 0, - EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT, - EMAC_PLL_SELECT_NEW = 0x0, - EMAC_PLL_SELECT_CODEC = 0x1, - EMAC_PLL_SELECT_GENERAL = 0x2, -}; - -/* CRU_CLKSEL25_CON */ -enum { - SPI1_PLL_SHIFT = 0xf, - SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT, - SPI1_PLL_SELECT_CODEC = 0, - SPI1_PLL_SELECT_GENERAL, - - SPI1_DIV_SHIFT = 8, - SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, - - SPI0_PLL_SHIFT = 7, - SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT, - SPI0_PLL_SELECT_CODEC = 0, - SPI0_PLL_SELECT_GENERAL, - - SPI0_DIV_SHIFT = 0, - SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, -}; - -/* CRU_CLKSEL37_CON */ -enum { - PCLK_CORE_DBG_DIV_SHIFT = 9, - PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT, - - ATCLK_CORE_DIV_CON_SHIFT = 4, - ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT, - - CLK_L2RAM_DIV_SHIFT = 0, - CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT, -}; - -/* CRU_CLKSEL39_CON */ -enum { - ACLK_HEVC_PLL_SHIFT = 0xe, - ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT, - ACLK_HEVC_PLL_SELECT_CODEC = 0, - ACLK_HEVC_PLL_SELECT_GENERAL, - ACLK_HEVC_PLL_SELECT_NEW, - - ACLK_HEVC_DIV_SHIFT = 8, - ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT, - - SPI2_PLL_SHIFT = 7, - SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT, - SPI2_PLL_SELECT_CODEC = 0, - SPI2_PLL_SELECT_GENERAL, - - SPI2_DIV_SHIFT = 0, - SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT, -}; - -/* CRU_MODE_CON */ -enum { - CRU_MODE_MASK = 3, - - NPLL_MODE_SHIFT = 0xe, - NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT, - NPLL_MODE_SLOW = 0, - NPLL_MODE_NORMAL, - NPLL_MODE_DEEP, - - GPLL_MODE_SHIFT = 0xc, - GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT, - GPLL_MODE_SLOW = 0, - GPLL_MODE_NORMAL, - GPLL_MODE_DEEP, - - CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT, - CPLL_MODE_SLOW = 0, - CPLL_MODE_NORMAL, - CPLL_MODE_DEEP, - - DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, - DPLL_MODE_SLOW = 0, - DPLL_MODE_NORMAL, - DPLL_MODE_DEEP, - - APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, - APLL_MODE_SLOW = 0, - APLL_MODE_NORMAL, - APLL_MODE_DEEP, -}; - -/* CRU_APLL_CON0 */ -enum { - CLKR_SHIFT = 8, - CLKR_MASK = 0x3f << CLKR_SHIFT, - - CLKOD_SHIFT = 0, - CLKOD_MASK = 0xf << CLKOD_SHIFT, -}; - -/* CRU_APLL_CON1 */ -enum { - LOCK_SHIFT = 0x1f, - LOCK_MASK = 1 << LOCK_SHIFT, - LOCK_UNLOCK = 0, - LOCK_LOCK, - - CLKF_SHIFT = 0, - CLKF_MASK = 0x1fff << CLKF_SHIFT, -}; - -/* CRU_GLB_RST_ST */ -enum { - GLB_POR_RST, - FST_GLB_RST_ST = BIT(0), - SND_GLB_RST_ST = BIT(1), - FST_GLB_TSADC_RST_ST = BIT(2), - SND_GLB_TSADC_RST_ST = BIT(3), - FST_GLB_WDT_RST_ST = BIT(4), - SND_GLB_WDT_RST_ST = BIT(5), - GLB_RST_ST_MASK = GENMASK(5, 0), -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h deleted file mode 100644 index 15b9788..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_CRU_RK3328_H_ -#define __ASM_ARCH_CRU_RK3328_H_ - -#include <common.h> - -struct rk3328_clk_priv { - struct rk3328_cru *cru; - ulong rate; -}; - -struct rk3328_cru { - u32 apll_con[5]; - u32 reserved1[3]; - u32 dpll_con[5]; - u32 reserved2[3]; - u32 cpll_con[5]; - u32 reserved3[3]; - u32 gpll_con[5]; - u32 reserved4[3]; - u32 mode_con; - u32 misc; - u32 reserved5[2]; - u32 glb_cnt_th; - u32 glb_rst_st; - u32 glb_srst_snd_value; - u32 glb_srst_fst_value; - u32 npll_con[5]; - u32 reserved6[(0x100 - 0xb4) / 4]; - u32 clksel_con[53]; - u32 reserved7[(0x200 - 0x1d4) / 4]; - u32 clkgate_con[29]; - u32 reserved8[3]; - u32 ssgtbl[32]; - u32 softrst_con[12]; - u32 reserved9[(0x380 - 0x330) / 4]; - u32 sdmmc_con[2]; - u32 sdio_con[2]; - u32 emmc_con[2]; - u32 sdmmc_ext_con[2]; -}; -check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); -#define MHz 1000000 -#define KHz 1000 -#define OSC_HZ (24 * MHz) -#define APLL_HZ (600 * MHz) -#define GPLL_HZ (576 * MHz) -#define CPLL_HZ (594 * MHz) - -#define CLK_CORE_HZ (600 * MHz) -#define ACLKM_CORE_HZ (300 * MHz) -#define PCLK_DBG_HZ (300 * MHz) - -#define PERIHP_ACLK_HZ (144000 * KHz) -#define PERIHP_HCLK_HZ (72000 * KHz) -#define PERIHP_PCLK_HZ (72000 * KHz) - -#define PWM_CLOCK_HZ (74 * MHz) - -enum apll_frequencies { - APLL_816_MHZ, - APLL_600_MHZ, -}; - -#endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h deleted file mode 100644 index 1fe1f01..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - * Author: Andy Yan <andy.yan@rock-chips.com> - */ -#ifndef _ASM_ARCH_CRU_RK3368_H -#define _ASM_ARCH_CRU_RK3368_H - -#include <common.h> - - -/* RK3368 clock numbers */ -enum rk3368_pll_id { - APLLB, - APLLL, - DPLL, - CPLL, - GPLL, - NPLL, - PLL_COUNT, -}; - -struct rk3368_cru { - struct rk3368_pll { - unsigned int con0; - unsigned int con1; - unsigned int con2; - unsigned int con3; - } pll[6]; - unsigned int reserved[0x28]; - unsigned int clksel_con[56]; - unsigned int reserved1[8]; - unsigned int clkgate_con[25]; - unsigned int reserved2[7]; - unsigned int glb_srst_fst_val; - unsigned int glb_srst_snd_val; - unsigned int reserved3[0x1e]; - unsigned int softrst_con[15]; - unsigned int reserved4[0x11]; - unsigned int misc_con; - unsigned int glb_cnt_th; - unsigned int glb_rst_con; - unsigned int glb_rst_st; - unsigned int reserved5[0x1c]; - unsigned int sdmmc_con[2]; - unsigned int sdio0_con[2]; - unsigned int sdio1_con[2]; - unsigned int emmc_con[2]; -}; -check_member(rk3368_cru, emmc_con[1], 0x41c); - -struct rk3368_clk_priv { - struct rk3368_cru *cru; -}; - -enum { - /* PLL CON0 */ - PLL_NR_SHIFT = 8, - PLL_NR_MASK = GENMASK(13, 8), - PLL_OD_SHIFT = 0, - PLL_OD_MASK = GENMASK(3, 0), - - /* PLL CON1 */ - PLL_LOCK_STA = BIT(31), - PLL_NF_SHIFT = 0, - PLL_NF_MASK = GENMASK(12, 0), - - /* PLL CON2 */ - PLL_BWADJ_SHIFT = 0, - PLL_BWADJ_MASK = GENMASK(11, 0), - - /* PLL CON3 */ - PLL_MODE_SHIFT = 8, - PLL_MODE_MASK = GENMASK(9, 8), - PLL_MODE_SLOW = 0, - PLL_MODE_NORMAL = 1, - PLL_MODE_DEEP_SLOW = 3, - PLL_RESET_SHIFT = 5, - PLL_RESET = 1, - PLL_RESET_MASK = GENMASK(5, 5), - - /* CLKSEL12_CON */ - MCU_STCLK_DIV_SHIFT = 8, - MCU_STCLK_DIV_MASK = GENMASK(10, 8), - MCU_PLL_SEL_SHIFT = 7, - MCU_PLL_SEL_MASK = BIT(7), - MCU_PLL_SEL_CPLL = 0, - MCU_PLL_SEL_GPLL = 1, - MCU_CLK_DIV_SHIFT = 0, - MCU_CLK_DIV_MASK = GENMASK(4, 0), - - /* CLKSEL_CON25 */ - CLK_SARADC_DIV_CON_SHIFT = 8, - CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), - CLK_SARADC_DIV_CON_WIDTH = 8, - - /* CLKSEL43_CON */ - GMAC_DIV_CON_SHIFT = 0x0, - GMAC_DIV_CON_MASK = GENMASK(4, 0), - GMAC_PLL_SHIFT = 6, - GMAC_PLL_MASK = GENMASK(7, 6), - GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT), - GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT), - GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT), - GMAC_MUX_SEL_EXTCLK = BIT(8), - - /* CLKSEL51_CON */ - MMC_PLL_SEL_SHIFT = 8, - MMC_PLL_SEL_MASK = GENMASK(9, 8), - MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT), - MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT), - MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT), - MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT), - MMC_CLK_DIV_SHIFT = 0, - MMC_CLK_DIV_MASK = GENMASK(6, 0), - - /* SOFTRST1_CON */ - MCU_PO_SRST_MASK = BIT(13), - MCU_SYS_SRST_MASK = BIT(12), - DMA1_SRST_REQ = BIT(2), - - /* SOFTRST4_CON */ - DMA2_SRST_REQ = BIT(0), - - /* GLB_RST_CON */ - PMU_GLB_SRST_CTRL_SHIFT = 2, - PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), - PMU_RST_BY_FST_GLB_SRST = 0, - PMU_RST_BY_SND_GLB_SRST = 1, - PMU_RST_DISABLE = 2, - WDT_GLB_SRST_CTRL_SHIFT = 1, - WDT_GLB_SRST_CTRL_MASK = BIT(1), - WDT_TRIGGER_SND_GLB_SRST = 0, - WDT_TRIGGER_FST_GLB_SRST = 1, - TSADC_GLB_SRST_CTRL_SHIFT = 0, - TSADC_GLB_SRST_CTRL_MASK = BIT(0), - TSADC_TRIGGER_SND_GLB_SRST = 0, - TSADC_TRIGGER_FST_GLB_SRST = 1, - -}; -#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h deleted file mode 100644 index 15eeb9c..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_CRU_RK3399_H_ -#define __ASM_ARCH_CRU_RK3399_H_ - -#include <common.h> - -/* Private data for the clock driver - used by rockchip_get_cru() */ -struct rk3399_clk_priv { - struct rk3399_cru *cru; -}; - -struct rk3399_pmuclk_priv { - struct rk3399_pmucru *pmucru; -}; - -struct rk3399_pmucru { - u32 ppll_con[6]; - u32 reserved[0x1a]; - u32 pmucru_clksel[6]; - u32 pmucru_clkfrac_con[2]; - u32 reserved2[0x18]; - u32 pmucru_clkgate_con[3]; - u32 reserved3; - u32 pmucru_softrst_con[2]; - u32 reserved4[2]; - u32 pmucru_rstnhold_con[2]; - u32 reserved5[2]; - u32 pmucru_gatedis_con[2]; -}; -check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); - -struct rk3399_cru { - u32 apll_l_con[6]; - u32 reserved[2]; - u32 apll_b_con[6]; - u32 reserved1[2]; - u32 dpll_con[6]; - u32 reserved2[2]; - u32 cpll_con[6]; - u32 reserved3[2]; - u32 gpll_con[6]; - u32 reserved4[2]; - u32 npll_con[6]; - u32 reserved5[2]; - u32 vpll_con[6]; - u32 reserved6[0x0a]; - u32 clksel_con[108]; - u32 reserved7[0x14]; - u32 clkgate_con[35]; - u32 reserved8[0x1d]; - u32 softrst_con[21]; - u32 reserved9[0x2b]; - u32 glb_srst_fst_value; - u32 glb_srst_snd_value; - u32 glb_cnt_th; - u32 misc_con; - u32 glb_rst_con; - u32 glb_rst_st; - u32 reserved10[0x1a]; - u32 sdmmc_con[2]; - u32 sdio0_con[2]; - u32 sdio1_con[2]; -}; -check_member(rk3399_cru, sdio1_con[1], 0x594); -#define MHz 1000000 -#define KHz 1000 -#define OSC_HZ (24*MHz) -#define LPLL_HZ (600*MHz) -#define BPLL_HZ (600*MHz) -#define GPLL_HZ (594*MHz) -#define CPLL_HZ (384*MHz) -#define PPLL_HZ (676*MHz) - -#define PMU_PCLK_HZ (48*MHz) - -#define ACLKM_CORE_L_HZ (300*MHz) -#define ATCLK_CORE_L_HZ (300*MHz) -#define PCLK_DBG_L_HZ (100*MHz) - -#define ACLKM_CORE_B_HZ (300*MHz) -#define ATCLK_CORE_B_HZ (300*MHz) -#define PCLK_DBG_B_HZ (100*MHz) - -#define PERIHP_ACLK_HZ (148500*KHz) -#define PERIHP_HCLK_HZ (148500*KHz) -#define PERIHP_PCLK_HZ (37125*KHz) - -#define PERILP0_ACLK_HZ (99000*KHz) -#define PERILP0_HCLK_HZ (99000*KHz) -#define PERILP0_PCLK_HZ (49500*KHz) - -#define PERILP1_HCLK_HZ (99000*KHz) -#define PERILP1_PCLK_HZ (49500*KHz) - -#define PWM_CLOCK_HZ PMU_PCLK_HZ - -enum apll_l_frequencies { - APLL_L_1600_MHZ, - APLL_L_600_MHZ, -}; - -enum apll_b_frequencies { - APLL_B_600_MHZ, -}; - -void rk3399_configure_cpu_l(struct rk3399_cru *cru, - enum apll_l_frequencies apll_l_freq); -void rk3399_configure_cpu_b(struct rk3399_cru *cru, - enum apll_b_frequencies apll_b_freq); - -#endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h deleted file mode 100644 index 7697e96..0000000 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * Author: Andy Yan <andy.yan@rock-chips.com> - */ -#ifndef _ASM_ARCH_CRU_RV1108_H -#define _ASM_ARCH_CRU_RV1108_H - -#include <common.h> - -#define OSC_HZ (24 * 1000 * 1000) - -#define APLL_HZ (600 * 1000000) -#define GPLL_HZ (1188 * 1000000) -#define ACLK_PERI_HZ (148500000) -#define HCLK_PERI_HZ (148500000) -#define PCLK_PERI_HZ (74250000) -#define ACLK_BUS_HZ (148500000) - -struct rv1108_clk_priv { - struct rv1108_cru *cru; - ulong rate; -}; - -struct rv1108_cru { - struct rv1108_pll { - unsigned int con0; - unsigned int con1; - unsigned int con2; - unsigned int con3; - unsigned int con4; - unsigned int con5; - unsigned int reserved[2]; - } pll[3]; - unsigned int clksel_con[46]; - unsigned int reserved1[2]; - unsigned int clkgate_con[20]; - unsigned int reserved2[4]; - unsigned int softrst_con[13]; - unsigned int reserved3[3]; - unsigned int glb_srst_fst_val; - unsigned int glb_srst_snd_val; - unsigned int glb_cnt_th; - unsigned int misc_con; - unsigned int glb_rst_con; - unsigned int glb_rst_st; - unsigned int sdmmc_con[2]; - unsigned int sdio_con[2]; - unsigned int emmc_con[2]; -}; -check_member(rv1108_cru, emmc_con[1], 0x01ec); - -struct pll_div { - u32 refdiv; - u32 fbdiv; - u32 postdiv1; - u32 postdiv2; - u32 frac; -}; - -enum { - /* PLL CON0 */ - FBDIV_MASK = 0xfff, - FBDIV_SHIFT = 0, - - /* PLL CON1 */ - POSTDIV2_SHIFT = 12, - POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, - POSTDIV1_SHIFT = 8, - POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, - REFDIV_MASK = 0x3f, - REFDIV_SHIFT = 0, - - /* PLL CON2 */ - LOCK_STA_SHIFT = 31, - LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, - FRACDIV_MASK = 0xffffff, - FRACDIV_SHIFT = 0, - - /* PLL CON3 */ - WORK_MODE_SHIFT = 8, - WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, - WORK_MODE_SLOW = 0, - WORK_MODE_NORMAL = 1, - DSMPD_SHIFT = 3, - DSMPD_MASK = 1 << DSMPD_SHIFT, - INTEGER_MODE = 1, - GLOBAL_POWER_DOWN_SHIFT = 0, - GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, - GLOBAL_POWER_DOWN = 1, - GLOBAL_POWER_UP = 0, - - /* CLKSEL0_CON */ - CORE_PLL_SEL_SHIFT = 8, - CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, - CORE_PLL_SEL_APLL = 0, - CORE_PLL_SEL_GPLL = 1, - CORE_PLL_SEL_DPLL = 2, - CORE_CLK_DIV_SHIFT = 0, - CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, - - /* CLKSEL_CON1 */ - PCLK_DBG_DIV_CON_SHIFT = 4, - PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, - ACLK_CORE_DIV_CON_SHIFT = 0, - ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, - - /* CLKSEL_CON2 */ - ACLK_BUS_PLL_SEL_SHIFT = 8, - ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, - ACLK_BUS_PLL_SEL_GPLL = 0, - ACLK_BUS_PLL_SEL_APLL = 1, - ACLK_BUS_PLL_SEL_DPLL = 2, - ACLK_BUS_DIV_CON_SHIFT = 0, - ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, - ACLK_BUS_DIV_CON_WIDTH = 5, - - /* CLKSEL_CON3 */ - PCLK_BUS_DIV_CON_SHIFT = 8, - PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, - HCLK_BUS_DIV_CON_SHIFT = 0, - HCLK_BUS_DIV_CON_MASK = 0x1f, - - /* CLKSEL_CON4 */ - CLK_DDR_PLL_SEL_SHIFT = 8, - CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, - CLK_DDR_DIV_CON_SHIFT = 0, - CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, - - /* CLKSEL_CON19 */ - CLK_I2C1_PLL_SEL_SHIFT = 15, - CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, - CLK_I2C1_PLL_SEL_DPLL = 0, - CLK_I2C1_PLL_SEL_GPLL = 1, - CLK_I2C1_DIV_CON_SHIFT = 8, - CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, - CLK_I2C0_PLL_SEL_SHIFT = 7, - CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, - CLK_I2C0_DIV_CON_SHIFT = 0, - CLK_I2C0_DIV_CON_MASK = 0x7f, - I2C_DIV_CON_WIDTH = 7, - - /* CLKSEL_CON20 */ - CLK_I2C3_PLL_SEL_SHIFT = 15, - CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, - CLK_I2C3_PLL_SEL_DPLL = 0, - CLK_I2C3_PLL_SEL_GPLL = 1, - CLK_I2C3_DIV_CON_SHIFT = 8, - CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, - CLK_I2C2_PLL_SEL_SHIFT = 7, - CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, - CLK_I2C2_DIV_CON_SHIFT = 0, - CLK_I2C2_DIV_CON_MASK = 0x7f, - - /* CLKSEL_CON22 */ - CLK_SARADC_DIV_CON_SHIFT= 0, - CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), - CLK_SARADC_DIV_CON_WIDTH= 10, - - /* CLKSEL_CON23 */ - ACLK_PERI_PLL_SEL_SHIFT = 15, - ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, - ACLK_PERI_PLL_SEL_GPLL = 0, - ACLK_PERI_PLL_SEL_DPLL = 1, - PCLK_PERI_DIV_CON_SHIFT = 10, - PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, - HCLK_PERI_DIV_CON_SHIFT = 5, - HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, - ACLK_PERI_DIV_CON_SHIFT = 0, - ACLK_PERI_DIV_CON_MASK = 0x1f, - PERI_DIV_CON_WIDTH = 5, - - /* CLKSEL24_CON */ - MAC_PLL_SEL_SHIFT = 12, - MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, - MAC_PLL_SEL_APLL = 0, - MAC_PLL_SEL_GPLL = 1, - RMII_EXTCLK_SEL_SHIFT = 8, - RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, - MAC_CLK_DIV_MASK = 0x1f, - MAC_CLK_DIV_SHIFT = 0, - - /* CLKSEL25_CON */ - EMMC_PLL_SEL_SHIFT = 12, - EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT, - EMMC_PLL_SEL_DPLL = 0, - EMMC_PLL_SEL_GPLL, - EMMC_PLL_SEL_OSC, - - /* CLKSEL26_CON */ - EMMC_CLK_DIV_SHIFT = 8, - EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT, - - /* CLKSEL27_CON */ - SFC_PLL_SEL_SHIFT = 7, - SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, - SFC_PLL_SEL_DPLL = 0, - SFC_PLL_SEL_GPLL = 1, - SFC_CLK_DIV_SHIFT = 0, - SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, - - /* CLKSEL28_CON */ - ACLK_VIO1_PLL_SEL_SHIFT = 14, - ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, - VIO_PLL_SEL_DPLL = 0, - VIO_PLL_SEL_GPLL = 1, - ACLK_VIO1_CLK_DIV_SHIFT = 8, - ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, - CLK_VIO_DIV_CON_WIDTH = 5, - ACLK_VIO0_PLL_SEL_SHIFT = 6, - ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, - ACLK_VIO0_CLK_DIV_SHIFT = 0, - ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, - - /* CLKSEL29_CON */ - PCLK_VIO_CLK_DIV_SHIFT = 8, - PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, - HCLK_VIO_CLK_DIV_SHIFT = 0, - HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, - - /* CLKSEL32_CON */ - DCLK_VOP_SEL_SHIFT = 7, - DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, - DCLK_VOP_SEL_HDMI = 0, - DCLK_VOP_SEL_PLL = 1, - DCLK_VOP_PLL_SEL_SHIFT = 6, - DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, - DCLK_VOP_PLL_SEL_GPLL = 0, - DCLK_VOP_PLL_SEL_DPLL = 1, - DCLK_VOP_CLK_DIV_SHIFT = 0, - DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, - DCLK_VOP_DIV_CON_WIDTH = 6, - - /* SOFTRST1_CON*/ - DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, - DDRPHY_SRSTN_CLKDIV_REQ = 1, - DDRPHY_SRSTN_CLKDIV_DIS = 0, - DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, - DDRPHY_SRSTN_REQ_SHIFT = 1, - DDRPHY_SRSTN_REQ = 1, - DDRPHY_SRSTN_DIS = 0, - DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, - DDRPHY_PSRSTN_REQ_SHIFT = 2, - DDRPHY_PSRSTN_REQ = 1, - DDRPHY_PSRSTN_DIS = 0, - DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, - - /* SOFTRST2_CON*/ - DDRUPCTL_PSRSTN_REQ_SHIFT = 0, - DDRUPCTL_PSRSTN_REQ = 1, - DDRUPCTL_PSRSTN_DIS = 0, - DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, - DDRUPCTL_NSRSTN_REQ_SHIFT = 1, - DDRUPCTL_NSRSTN_REQ = 1, - DDRUPCTL_NSRSTN_DIS = 0, - DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, -}; -#endif diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h deleted file mode 100644 index db83d0e..0000000 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef _ASM_ARCH_DDR_RK3188_H -#define _ASM_ARCH_DDR_RK3188_H - -#include <asm/arch-rockchip/ddr_rk3288.h> - -/* - * RK3188 Memory scheduler register map. - */ -struct rk3188_msch { - u32 coreid; - u32 revisionid; - u32 ddrconf; - u32 ddrtiming; - u32 ddrmode; - u32 readlatency; -}; -check_member(rk3188_msch, readlatency, 0x0014); - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h deleted file mode 100644 index 979d547..0000000 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ /dev/null @@ -1,443 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef _ASM_ARCH_DDR_RK3288_H -#define _ASM_ARCH_DDR_RK3288_H - -struct rk3288_ddr_pctl { - u32 scfg; - u32 sctl; - u32 stat; - u32 intrstat; - u32 reserved0[12]; - u32 mcmd; - u32 powctl; - u32 powstat; - u32 cmdtstat; - u32 tstaten; - u32 reserved1[3]; - u32 mrrcfg0; - u32 mrrstat0; - u32 mrrstat1; - u32 reserved2[4]; - u32 mcfg1; - u32 mcfg; - u32 ppcfg; - u32 mstat; - u32 lpddr2zqcfg; - u32 reserved3; - u32 dtupdes; - u32 dtuna; - u32 dtune; - u32 dtuprd0; - u32 dtuprd1; - u32 dtuprd2; - u32 dtuprd3; - u32 dtuawdt; - u32 reserved4[3]; - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; - u32 reserved5[14]; - u32 ecccfg; - u32 ecctst; - u32 eccclr; - u32 ecclog; - u32 reserved6[28]; - u32 dtuwactl; - u32 dturactl; - u32 dtucfg; - u32 dtuectl; - u32 dtuwd0; - u32 dtuwd1; - u32 dtuwd2; - u32 dtuwd3; - u32 dtuwdm; - u32 dturd0; - u32 dturd1; - u32 dturd2; - u32 dturd3; - u32 dtulfsrwd; - u32 dtulfsrrd; - u32 dtueaf; - u32 dfitctrldelay; - u32 dfiodtcfg; - u32 dfiodtcfg1; - u32 dfiodtrankmap; - u32 dfitphywrdata; - u32 dfitphywrlat; - u32 reserved7[2]; - u32 dfitrddataen; - u32 dfitphyrdlat; - u32 reserved8[2]; - u32 dfitphyupdtype0; - u32 dfitphyupdtype1; - u32 dfitphyupdtype2; - u32 dfitphyupdtype3; - u32 dfitctrlupdmin; - u32 dfitctrlupdmax; - u32 dfitctrlupddly; - u32 reserved9; - u32 dfiupdcfg; - u32 dfitrefmski; - u32 dfitctrlupdi; - u32 reserved10[4]; - u32 dfitrcfg0; - u32 dfitrstat0; - u32 dfitrwrlvlen; - u32 dfitrrdlvlen; - u32 dfitrrdlvlgateen; - u32 dfiststat0; - u32 dfistcfg0; - u32 dfistcfg1; - u32 reserved11; - u32 dfitdramclken; - u32 dfitdramclkdis; - u32 dfistcfg2; - u32 dfistparclr; - u32 dfistparlog; - u32 reserved12[3]; - u32 dfilpcfg0; - u32 reserved13[3]; - u32 dfitrwrlvlresp0; - u32 dfitrwrlvlresp1; - u32 dfitrwrlvlresp2; - u32 dfitrrdlvlresp0; - u32 dfitrrdlvlresp1; - u32 dfitrrdlvlresp2; - u32 dfitrwrlvldelay0; - u32 dfitrwrlvldelay1; - u32 dfitrwrlvldelay2; - u32 dfitrrdlvldelay0; - u32 dfitrrdlvldelay1; - u32 dfitrrdlvldelay2; - u32 dfitrrdlvlgatedelay0; - u32 dfitrrdlvlgatedelay1; - u32 dfitrrdlvlgatedelay2; - u32 dfitrcmd; - u32 reserved14[46]; - u32 ipvr; - u32 iptr; -}; -check_member(rk3288_ddr_pctl, iptr, 0x03fc); - -struct rk3288_ddr_publ_datx { - u32 dxgcr; - u32 dxgsr[2]; - u32 dxdllcr; - u32 dxdqtr; - u32 dxdqstr; - u32 reserved[10]; -}; - -struct rk3288_ddr_publ { - u32 ridr; - u32 pir; - u32 pgcr; - u32 pgsr; - u32 dllgcr; - u32 acdllcr; - u32 ptr[3]; - u32 aciocr; - u32 dxccr; - u32 dsgcr; - u32 dcr; - u32 dtpr[3]; - u32 mr[4]; - u32 odtcr; - u32 dtar; - u32 dtdr[2]; - u32 reserved1[24]; - u32 dcuar; - u32 dcudr; - u32 dcurr; - u32 dculr; - u32 dcugcr; - u32 dcutpr; - u32 dcusr[2]; - u32 reserved2[8]; - u32 bist[17]; - u32 reserved3[15]; - u32 zq0cr[2]; - u32 zq0sr[2]; - u32 zq1cr[2]; - u32 zq1sr[2]; - u32 zq2cr[2]; - u32 zq2sr[2]; - u32 zq3cr[2]; - u32 zq3sr[2]; - struct rk3288_ddr_publ_datx datx8[4]; -}; -check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294); - -struct rk3288_msch { - u32 coreid; - u32 revisionid; - u32 ddrconf; - u32 ddrtiming; - u32 ddrmode; - u32 readlatency; - u32 reserved1[8]; - u32 activate; - u32 devtodev; -}; -check_member(rk3288_msch, devtodev, 0x003c); - -/* PCT_DFISTCFG0 */ -#define DFI_INIT_START (1 << 0) - -/* PCT_DFISTCFG1 */ -#define DFI_DRAM_CLK_SR_EN (1 << 0) -#define DFI_DRAM_CLK_DPD_EN (1 << 1) - -/* PCT_DFISTCFG2 */ -#define DFI_PARITY_INTR_EN (1 << 0) -#define DFI_PARITY_EN (1 << 1) - -/* PCT_DFILPCFG0 */ -#define TLP_RESP_TIME_SHIFT 16 -#define LP_SR_EN (1 << 8) -#define LP_PD_EN (1 << 0) - -/* PCT_DFITCTRLDELAY */ -#define TCTRL_DELAY_TIME_SHIFT 0 - -/* PCT_DFITPHYWRDATA */ -#define TPHY_WRDATA_TIME_SHIFT 0 - -/* PCT_DFITPHYRDLAT */ -#define TPHY_RDLAT_TIME_SHIFT 0 - -/* PCT_DFITDRAMCLKDIS */ -#define TDRAM_CLK_DIS_TIME_SHIFT 0 - -/* PCT_DFITDRAMCLKEN */ -#define TDRAM_CLK_EN_TIME_SHIFT 0 - -/* PCTL_DFIODTCFG */ -#define RANK0_ODT_WRITE_SEL (1 << 3) -#define RANK1_ODT_WRITE_SEL (1 << 11) - -/* PCTL_DFIODTCFG1 */ -#define ODT_LEN_BL8_W_SHIFT 16 - -/* PUBL_ACDLLCR */ -#define ACDLLCR_DLLDIS (1 << 31) -#define ACDLLCR_DLLSRST (1 << 30) - -/* PUBL_DXDLLCR */ -#define DXDLLCR_DLLDIS (1 << 31) -#define DXDLLCR_DLLSRST (1 << 30) - -/* PUBL_DLLGCR */ -#define DLLGCR_SBIAS (1 << 30) - -/* PUBL_DXGCR */ -#define DQSRTT (1 << 9) -#define DQRTT (1 << 10) - -/* PIR */ -#define PIR_INIT (1 << 0) -#define PIR_DLLSRST (1 << 1) -#define PIR_DLLLOCK (1 << 2) -#define PIR_ZCAL (1 << 3) -#define PIR_ITMSRST (1 << 4) -#define PIR_DRAMRST (1 << 5) -#define PIR_DRAMINIT (1 << 6) -#define PIR_QSTRN (1 << 7) -#define PIR_RVTRN (1 << 8) -#define PIR_ICPC (1 << 16) -#define PIR_DLLBYP (1 << 17) -#define PIR_CTLDINIT (1 << 18) -#define PIR_CLRSR (1 << 28) -#define PIR_LOCKBYP (1 << 29) -#define PIR_ZCALBYP (1 << 30) -#define PIR_INITBYP (1u << 31) - -/* PGCR */ -#define PGCR_DFTLMT_SHIFT 3 -#define PGCR_DFTCMP_SHIFT 2 -#define PGCR_DQSCFG_SHIFT 1 -#define PGCR_ITMDMD_SHIFT 0 - -/* PGSR */ -#define PGSR_IDONE (1 << 0) -#define PGSR_DLDONE (1 << 1) -#define PGSR_ZCDONE (1 << 2) -#define PGSR_DIDONE (1 << 3) -#define PGSR_DTDONE (1 << 4) -#define PGSR_DTERR (1 << 5) -#define PGSR_DTIERR (1 << 6) -#define PGSR_DFTERR (1 << 7) -#define PGSR_RVERR (1 << 8) -#define PGSR_RVEIRR (1 << 9) - -/* PTR0 */ -#define PRT_ITMSRST_SHIFT 18 -#define PRT_DLLLOCK_SHIFT 6 -#define PRT_DLLSRST_SHIFT 0 - -/* PTR1 */ -#define PRT_DINIT0_SHIFT 0 -#define PRT_DINIT1_SHIFT 19 - -/* PTR2 */ -#define PRT_DINIT2_SHIFT 0 -#define PRT_DINIT3_SHIFT 17 - -/* DCR */ -#define DDRMD_LPDDR 0 -#define DDRMD_DDR 1 -#define DDRMD_DDR2 2 -#define DDRMD_DDR3 3 -#define DDRMD_LPDDR2_LPDDR3 4 -#define DDRMD_MASK 7 -#define DDRMD_SHIFT 0 -#define PDQ_MASK 7 -#define PDQ_SHIFT 4 - -/* DXCCR */ -#define DQSNRES_MASK 0xf -#define DQSNRES_SHIFT 8 -#define DQSRES_MASK 0xf -#define DQSRES_SHIFT 4 - -/* DTPR */ -#define TDQSCKMAX_SHIFT 27 -#define TDQSCKMAX_MASK 7 -#define TDQSCK_SHIFT 24 -#define TDQSCK_MASK 7 - -/* DSGCR */ -#define DQSGX_SHIFT 5 -#define DQSGX_MASK 7 -#define DQSGE_SHIFT 8 -#define DQSGE_MASK 7 - -/* SCTL */ -#define INIT_STATE 0 -#define CFG_STATE 1 -#define GO_STATE 2 -#define SLEEP_STATE 3 -#define WAKEUP_STATE 4 - -/* STAT */ -#define LP_TRIG_SHIFT 4 -#define LP_TRIG_MASK 7 -#define PCTL_STAT_MSK 7 -#define INIT_MEM 0 -#define CONFIG 1 -#define CONFIG_REQ 2 -#define ACCESS 3 -#define ACCESS_REQ 4 -#define LOW_POWER 5 -#define LOW_POWER_ENTRY_REQ 6 -#define LOW_POWER_EXIT_REQ 7 - -/* ZQCR*/ -#define PD_OUTPUT_SHIFT 0 -#define PU_OUTPUT_SHIFT 5 -#define PD_ONDIE_SHIFT 10 -#define PU_ONDIE_SHIFT 15 -#define ZDEN_SHIFT 28 - -/* DDLGCR */ -#define SBIAS_BYPASS (1 << 23) - -/* MCFG */ -#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 -#define PD_IDLE_SHIFT 8 -#define MDDR_EN (2 << 22) -#define LPDDR2_EN (3 << 22) -#define DDR2_EN (0 << 5) -#define DDR3_EN (1 << 5) -#define LPDDR2_S2 (0 << 6) -#define LPDDR2_S4 (1 << 6) -#define MDDR_LPDDR2_BL_2 (0 << 20) -#define MDDR_LPDDR2_BL_4 (1 << 20) -#define MDDR_LPDDR2_BL_8 (2 << 20) -#define MDDR_LPDDR2_BL_16 (3 << 20) -#define DDR2_DDR3_BL_4 0 -#define DDR2_DDR3_BL_8 1 -#define TFAW_SHIFT 18 -#define PD_EXIT_SLOW (0 << 17) -#define PD_EXIT_FAST (1 << 17) -#define PD_TYPE_SHIFT 16 -#define BURSTLENGTH_SHIFT 20 - -/* POWCTL */ -#define POWER_UP_START (1 << 0) - -/* POWSTAT */ -#define POWER_UP_DONE (1 << 0) - -/* MCMD */ -enum { - DESELECT_CMD = 0, - PREA_CMD, - REF_CMD, - MRS_CMD, - ZQCS_CMD, - ZQCL_CMD, - RSTL_CMD, - MRR_CMD = 8, - DPDE_CMD, -}; - -#define LPDDR2_MA_SHIFT 4 -#define LPDDR2_MA_MASK 0xff -#define LPDDR2_OP_SHIFT 12 -#define LPDDR2_OP_MASK 0xff - -#define START_CMD (1u << 31) - -/* - * DDRCONF - * [5:4] row(13+n) - * [1:0] col(9+n), assume bw=2 - */ -#define DDRCONF_ROW_SHIFT 4 -#define DDRCONF_COL_SHIFT 0 - -/* DEVTODEV */ -#define BUSWRTORD_SHIFT 4 -#define BUSRDTOWR_SHIFT 2 -#define BUSRDTORD_SHIFT 0 - -/* mr1 for ddr3 */ -#define DDR3_DLL_DISABLE 1 - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h deleted file mode 100644 index 82234cf..0000000 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#ifndef __ASM_ARCH_DDR_RK3368_H__ -#define __ASM_ARCH_DDR_RK3368_H__ - -/* - * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only - * in a few details. Most notably, it has an additional field to track - * tREFI in controller cycles (i.e. trefi_mem_ddr3). - */ -struct rk3368_ddr_pctl { - u32 scfg; - u32 sctl; - u32 stat; - u32 intrstat; - u32 reserved0[12]; - u32 mcmd; - u32 powctl; - u32 powstat; - u32 cmdtstat; - u32 cmdtstaten; - u32 reserved1[3]; - u32 mrrcfg0; - u32 mrrstat0; - u32 mrrstat1; - u32 reserved2[4]; - u32 mcfg1; - u32 mcfg; - u32 ppcfg; - u32 mstat; - u32 lpddr2zqcfg; - u32 reserved3; - u32 dtupdes; - u32 dtuna; - u32 dtune; - u32 dtuprd0; - u32 dtuprd1; - u32 dtuprd2; - u32 dtuprd3; - u32 dtuawdt; - u32 reserved4[3]; - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; - u32 trefi_mem_ddr3; - u32 reserved5[45]; - u32 dtuwactl; - u32 dturactl; - u32 dtucfg; - u32 dtuectl; - u32 dtuwd0; - u32 dtuwd1; - u32 dtuwd2; - u32 dtuwd3; - u32 dtuwdm; - u32 dturd0; - u32 dturd1; - u32 dturd2; - u32 dturd3; - u32 dtulfsrwd; - u32 dtulfsrrd; - u32 dtueaf; - u32 dfitctrldelay; - u32 dfiodtcfg; - u32 dfiodtcfg1; - u32 dfiodtrankmap; - u32 dfitphywrdata; - u32 dfitphywrlat; - u32 reserved7[2]; - u32 dfitrddataen; - u32 dfitphyrdlat; - u32 reserved8[2]; - u32 dfitphyupdtype0; - u32 dfitphyupdtype1; - u32 dfitphyupdtype2; - u32 dfitphyupdtype3; - u32 dfitctrlupdmin; - u32 dfitctrlupdmax; - u32 dfitctrlupddly; - u32 reserved9; - u32 dfiupdcfg; - u32 dfitrefmski; - u32 dfitctrlupdi; - u32 reserved10[4]; - u32 dfitrcfg0; - u32 dfitrstat0; - u32 dfitrwrlvlen; - u32 dfitrrdlvlen; - u32 dfitrrdlvlgateen; - u32 dfiststat0; - u32 dfistcfg0; - u32 dfistcfg1; - u32 reserved11; - u32 dfitdramclken; - u32 dfitdramclkdis; - u32 dfistcfg2; - u32 dfistparclr; - u32 dfistparlog; - u32 reserved12[3]; - u32 dfilpcfg0; - u32 reserved13[3]; - u32 dfitrwrlvlresp0; - u32 dfitrwrlvlresp1; - u32 dfitrwrlvlresp2; - u32 dfitrrdlvlresp0; - u32 dfitrrdlvlresp1; - u32 dfitrrdlvlresp2; - u32 dfitrwrlvldelay0; - u32 dfitrwrlvldelay1; - u32 dfitrwrlvldelay2; - u32 dfitrrdlvldelay0; - u32 dfitrrdlvldelay1; - u32 dfitrrdlvldelay2; - u32 dfitrrdlvlgatedelay0; - u32 dfitrrdlvlgatedelay1; - u32 dfitrrdlvlgatedelay2; - u32 dfitrcmd; - u32 reserved14[46]; - u32 ipvr; - u32 iptr; -}; -check_member(rk3368_ddr_pctl, iptr, 0x03fc); - -struct rk3368_ddrphy { - u32 reg[0x100]; -}; -check_member(rk3368_ddrphy, reg[0xff], 0x03fc); - -struct rk3368_msch { - u32 coreid; - u32 revisionid; - u32 ddrconf; - u32 ddrtiming; - u32 ddrmode; - u32 readlatency; - u32 reserved1[8]; - u32 activate; - u32 devtodev; -}; -check_member(rk3368_msch, devtodev, 0x003c); - -/* GRF_SOC_CON0 */ -enum { - NOC_RSP_ERR_STALL = BIT(9), - MOBILE_DDR_SEL = BIT(4), - DDR0_16BIT_EN = BIT(3), - MSCH0_MAINDDR3_DDR3 = BIT(2), - MSCH0_MAINPARTIALPOP = BIT(1), - UPCTL_C_ACTIVE = BIT(0), -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h deleted file mode 100644 index 105a335..0000000 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ /dev/null @@ -1,635 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - * Copyright 2014 Rockchip Inc. - */ - -#ifndef _ASM_ARCH_EDP_H -#define _ASM_ARCH_EDP_H - -struct rk3288_edp { - u8 res0[0x10]; - u32 dp_tx_version; - u8 res1[0x4]; - u32 func_en_1; - u32 func_en_2; - u32 video_ctl_1; - u32 video_ctl_2; - u32 video_ctl_3; - u32 video_ctl_4; - u8 res2[0xc]; - u32 video_ctl_8; - u8 res3[0x4]; - u32 video_ctl_10; - u32 total_line_l; - u32 total_line_h; - u32 active_line_l; - u32 active_line_h; - u32 v_f_porch; - u32 vsync; - u32 v_b_porch; - u32 total_pixel_l; - u32 total_pixel_h; - u32 active_pixel_l; - u32 active_pixel_h; - u32 h_f_porch_l; - u32 h_f_porch_h; - u32 hsync_l; - u32 hysnc_h; - u32 h_b_porch_l; - u32 h_b_porch_h; - u32 vid_status; - u32 total_line_sta_l; - u32 total_line_sta_h; - u32 active_line_sta_l; - u32 active_line_sta_h; - u32 v_f_porch_sta; - u32 vsync_sta; - u32 v_b_porch_sta; - u32 total_pixel_sta_l; - u32 total_pixel_sta_h; - u32 active_pixel_sta_l; - u32 active_pixel_sta_h; - u32 h_f_porch_sta_l; - u32 h_f_porch_sta_h; - u32 hsync_sta_l; - u32 hsync_sta_h; - u32 h_b_porch_sta_l; - u32 h_b_porch__sta_h; - u8 res4[0x28]; - u32 pll_reg_1; - u8 res5[4]; - u32 ssc_reg; - u8 res6[0xc]; - u32 tx_common; - u32 tx_common2; - u8 res7[0x4]; - u32 dp_aux; - u32 dp_bias; - u32 dp_test; - u32 dp_pd; - u32 dp_reserv1; - u32 dp_reserv2; - u8 res8[0x224]; - u32 lane_map; - u8 res9[0x14]; - u32 analog_ctl_2; - u8 res10[0x48]; - u32 int_state; - u32 common_int_sta_1; - u32 common_int_sta_2; - u32 common_int_sta_3; - u32 common_int_sta_4; - u32 spdif_biphase_int_sta; - u8 res11[0x4]; - u32 dp_int_sta; - u32 common_int_mask_1; - u32 common_int_mask_2; - u32 common_int_mask_3; - u32 common_int_mask_4; - u8 res12[0x08]; - u32 int_sta_mask; - u32 int_ctl; - u8 res13[0x200]; - u32 sys_ctl_1; - u32 sys_ctl_2; - u32 sys_ctl_3; - u32 sys_ctl_4; - u32 dp_vid_ctl; - u8 res14[0x4]; - u32 dp_aud_ctl; - u8 res15[0x24]; - u32 pkt_send_ctl; - u8 res16[0x4]; - u32 dp_hdcp_ctl; - u8 res17[0x34]; - u32 link_bw_set; - u32 lane_count_set; - u32 dp_training_ptn_set; - u32 ln_link_trn_ctl[4]; - u8 res18[0x4]; - u32 dp_hw_link_training; - u8 res19[0x1c]; - u32 dp_debug_ctl; - u32 hpd_deglitch_l; - u32 hpd_deglitch_h; - u8 res20[0x14]; - u32 dp_link_debug_ctl; - u8 res21[0x1c]; - u32 m_vid_0; - u32 m_vid_1; - u32 m_vid_2; - u32 n_vid_0; - u32 n_vid_1; - u32 n_vid_2; - u32 m_vid_mon; - u8 res22[0x14]; - u32 dp_video_fifo_thrd; - u8 res23[0x8]; - u32 dp_audio_margin; - u8 res24[0x20]; - u32 dp_m_cal_ctl; - u32 m_vid_gen_filter_th; - u8 res25[0x10]; - u32 m_aud_gen_filter_th; - u8 res26[0x4]; - u32 aux_ch_sta; - u32 aux_err_num; - u32 aux_ch_defer_dtl; - u32 aux_rx_comm; - u32 buf_data_ctl; - u32 aux_ch_ctl_1; - u32 aux_addr_7_0; - u32 aux_addr_15_8; - u32 aux_addr_19_16; - u32 aux_ch_ctl_2; - u8 res27[0x18]; - u32 buf_data[16]; - u32 soc_general_ctl; - u8 res29[0x1e0]; - u32 pll_reg_2; - u32 pll_reg_3; - u32 pll_reg_4; - u8 res30[0x10]; - u32 pll_reg_5; -}; -check_member(rk3288_edp, pll_reg_5, 0xa00); - -/* func_en_1 */ -#define VID_CAP_FUNC_EN_N (0x1 << 6) -#define VID_FIFO_FUNC_EN_N (0x1 << 5) -#define AUD_FIFO_FUNC_EN_N (0x1 << 4) -#define AUD_FUNC_EN_N (0x1 << 3) -#define HDCP_FUNC_EN_N (0x1 << 2) -#define SW_FUNC_EN_N (0x1 << 0) - -/* func_en_2 */ -#define SSC_FUNC_EN_N (0x1 << 7) -#define AUX_FUNC_EN_N (0x1 << 2) -#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) -#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) - -/* video_ctl_1 */ -#define VIDEO_EN (0x1 << 7) -#define VIDEO_MUTE (0x1 << 6) - -/* video_ctl_2 */ -#define IN_D_RANGE_MASK (0x1 << 7) -#define IN_D_RANGE_SHIFT (7) -#define IN_D_RANGE_CEA (0x1 << 7) -#define IN_D_RANGE_VESA (0x0 << 7) -#define IN_BPC_MASK (0x7 << 4) -#define IN_BPC_SHIFT (4) -#define IN_BPC_12_BITS (0x3 << 4) -#define IN_BPC_10_BITS (0x2 << 4) -#define IN_BPC_8_BITS (0x1 << 4) -#define IN_BPC_6_BITS (0x0 << 4) -#define IN_COLOR_F_MASK (0x3 << 0) -#define IN_COLOR_F_SHIFT (0) -#define IN_COLOR_F_YCBCR444 (0x2 << 0) -#define IN_COLOR_F_YCBCR422 (0x1 << 0) -#define IN_COLOR_F_RGB (0x0 << 0) - -/* video_ctl_3 */ -#define IN_YC_COEFFI_MASK (0x1 << 7) -#define IN_YC_COEFFI_SHIFT (7) -#define IN_YC_COEFFI_ITU709 (0x1 << 7) -#define IN_YC_COEFFI_ITU601 (0x0 << 7) -#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) -#define VID_CHK_UPDATE_TYPE_SHIFT (4) -#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) -#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) - -/* video_ctl_4 */ -#define BIST_EN (0x1 << 3) -#define BIST_WH_64 (0x1 << 2) -#define BIST_WH_32 (0x0 << 2) -#define BIST_TYPE_COLR_BAR (0x0 << 0) -#define BIST_TYPE_GRAY_BAR (0x1 << 0) -#define BIST_TYPE_MOBILE_BAR (0x2 << 0) - -/* video_ctl_8 */ -#define VID_HRES_TH(x) (((x) & 0xf) << 4) -#define VID_VRES_TH(x) (((x) & 0xf) << 0) - -/* video_ctl_10 */ -#define F_SEL (0x1 << 4) -#define INTERACE_SCAN_CFG (0x1 << 2) -#define INTERACD_SCAN_CFG_OFFSET 2 -#define VSYNC_POLARITY_CFG (0x1 << 1) -#define VSYNC_POLARITY_CFG_OFFSET 1 -#define HSYNC_POLARITY_CFG (0x1 << 0) -#define HSYNC_POLARITY_CFG_OFFSET 0 - -/* dp_pd */ -#define PD_INC_BG (0x1 << 7) -#define PD_EXP_BG (0x1 << 6) -#define PD_AUX (0x1 << 5) -#define PD_PLL (0x1 << 4) -#define PD_CH3 (0x1 << 3) -#define PD_CH2 (0x1 << 2) -#define PD_CH1 (0x1 << 1) -#define PD_CH0 (0x1 << 0) - -/* pll_reg_1 */ -#define REF_CLK_24M (0x1 << 1) -#define REF_CLK_27M (0x0 << 1) - -/* line_map */ -#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) -#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) -#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) -#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) -#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) -#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) -#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) -#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) -#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) -#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) -#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) -#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) -#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) -#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) -#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) -#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) - -/* analog_ctl_2 */ -#define SEL_24M (0x1 << 3) - -/* common_int_sta_1 */ -#define VSYNC_DET (0x1 << 7) -#define PLL_LOCK_CHG (0x1 << 6) -#define SPDIF_ERR (0x1 << 5) -#define SPDIF_UNSTBL (0x1 << 4) -#define VID_FORMAT_CHG (0x1 << 3) -#define AUD_CLK_CHG (0x1 << 2) -#define VID_CLK_CHG (0x1 << 1) -#define SW_INT (0x1 << 0) - -/* common_int_sta_2 */ -#define ENC_EN_CHG (0x1 << 6) -#define HW_BKSV_RDY (0x1 << 3) -#define HW_SHA_DONE (0x1 << 2) -#define HW_AUTH_STATE_CHG (0x1 << 1) -#define HW_AUTH_DONE (0x1 << 0) - -/* common_int_sta_3 */ -#define AFIFO_UNDER (0x1 << 7) -#define AFIFO_OVER (0x1 << 6) -#define R0_CHK_FLAG (0x1 << 5) - -/* common_int_sta_4 */ -#define PSR_ACTIVE (0x1 << 7) -#define PSR_INACTIVE (0x1 << 6) -#define SPDIF_BI_PHASE_ERR (0x1 << 5) -#define HOTPLUG_CHG (0x1 << 2) -#define HPD_LOST (0x1 << 1) -#define PLUG (0x1 << 0) - -/* dp_int_sta */ -#define INT_HPD (0x1 << 6) -#define HW_LT_DONE (0x1 << 5) -#define SINK_LOST (0x1 << 3) -#define LINK_LOST (0x1 << 2) -#define RPLY_RECEIV (0x1 << 1) -#define AUX_ERR (0x1 << 0) - -/* int_ctl */ -#define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) - -/* sys_ctl_1 */ -#define DET_STA (0x1 << 2) -#define FORCE_DET (0x1 << 1) -#define DET_CTRL (0x1 << 0) - -/* sys_ctl_2 */ -#define CHA_CRI(x) (((x) & 0xf) << 4) -#define CHA_STA (0x1 << 2) -#define FORCE_CHA (0x1 << 1) -#define CHA_CTRL (0x1 << 0) - -/* sys_ctl_3 */ -#define HPD_STATUS (0x1 << 6) -#define F_HPD (0x1 << 5) -#define HPD_CTRL (0x1 << 4) -#define HDCP_RDY (0x1 << 3) -#define STRM_VALID (0x1 << 2) -#define F_VALID (0x1 << 1) -#define VALID_CTRL (0x1 << 0) - -/* sys_ctl_4 */ -#define FIX_M_AUD (0x1 << 4) -#define ENHANCED (0x1 << 3) -#define FIX_M_VID (0x1 << 2) -#define M_VID_UPDATE_CTRL (0x3 << 0) - -/* pll_reg_2 */ -#define LDO_OUTPUT_V_SEL_145 (2 << 6) -#define KVCO_DEFALUT (1 << 4) -#define CHG_PUMP_CUR_SEL_5US (1 << 2) -#define V2L_CUR_SEL_1MA (1 << 0) - -/* pll_reg_3 */ -#define LOCK_DET_CNT_SEL_256 (2 << 5) -#define LOOP_FILTER_RESET (0 << 4) -#define PALL_SSC_RESET (0 << 3) -#define LOCK_DET_BYPASS (0 << 2) -#define PLL_LOCK_DET_MODE (0 << 1) -#define PLL_LOCK_DET_FORCE (0 << 0) - -/* pll_reg_5 */ -#define REGULATOR_V_SEL_950MV (2 << 4) -#define STANDBY_CUR_SEL (0 << 3) -#define CHG_PUMP_INOUT_CTRL_1200MV (1 << 1) -#define CHG_PUMP_INPUT_CTRL_OP (0 << 0) - -/* ssc_reg */ -#define SSC_OFFSET (0 << 6) -#define SSC_MODE (1 << 4) -#define SSC_DEPTH (9 << 0) - -/* tx_common */ -#define TX_SWING_PRE_EMP_MODE (1 << 7) -#define PRE_DRIVER_PW_CTRL1 (0 << 5) -#define LP_MODE_CLK_REGULATOR (0 << 4) -#define RESISTOR_MSB_CTRL (0 << 3) -#define RESISTOR_CTRL (7 << 0) - -/* dp_aux */ -#define DP_AUX_COMMON_MODE (0 << 4) -#define DP_AUX_EN (0 << 3) -#define AUX_TERM_50OHM (3 << 0) - -/* dp_bias */ -#define DP_BG_OUT_SEL (4 << 4) -#define DP_DB_CUR_CTRL (0 << 3) -#define DP_BG_SEL (1 << 2) -#define DP_RESISTOR_TUNE_BG (2 << 0) - -/* dp_reserv2 */ -#define CH1_CH3_SWING_EMP_CTRL (5 << 4) -#define CH0_CH2_SWING_EMP_CTRL (5 << 0) - -/* dp_training_ptn_set */ -#define SCRAMBLING_DISABLE (0x1 << 5) -#define SCRAMBLING_ENABLE (0x0 << 5) -#define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2) -#define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2) -#define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2) -#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) -#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) -#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) -#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) -#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) -#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) -#define SW_TRAINING_PATTERN_SET_DISABLE (0x0 << 0) - -/* dp_hw_link_training_ctl */ -#define HW_LT_ERR_CODE_MASK 0x70 -#define HW_LT_ERR_CODE_SHIFT 4 -#define HW_LT_EN (0x1 << 0) - -/* dp_debug_ctl */ -#define PLL_LOCK (0x1 << 4) -#define F_PLL_LOCK (0x1 << 3) -#define PLL_LOCK_CTRL (0x1 << 2) -#define POLL_EN (0x1 << 1) -#define PN_INV (0x1 << 0) - -/* aux_ch_sta */ -#define AUX_BUSY (0x1 << 4) -#define AUX_STATUS_MASK (0xf << 0) - -/* aux_ch_defer_ctl */ -#define DEFER_CTRL_EN (0x1 << 7) -#define DEFER_COUNT(x) (((x) & 0x7f) << 0) - -/* aux_rx_comm */ -#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) -#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) - -/* buffer_data_ctl */ -#define BUF_CLR (0x1 << 7) -#define BUF_HAVE_DATA (0x1 << 4) -#define BUF_DATA_COUNT(x) (((x) & 0xf) << 0) - -/* aux_ch_ctl_1 */ -#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) -#define AUX_TX_COMM_MASK (0xf << 0) -#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) -#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) -#define AUX_TX_COMM_MOT (0x1 << 2) -#define AUX_TX_COMM_WRITE (0x0 << 0) -#define AUX_TX_COMM_READ (0x1 << 0) - -/* aux_ch_ctl_2 */ -#define PD_AUX_IDLE (0x1 << 3) -#define ADDR_ONLY (0x1 << 1) -#define AUX_EN (0x1 << 0) - -/* tx_sw_reset */ -#define RST_DP_TX (0x1 << 0) - -/* analog_ctl_1 */ -#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) - -/* analog_ctl_3 */ -#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) -#define VCO_BIT_600_MICRO (0x5 << 0) - -/* pll_filter_ctl_1 */ -#define PD_RING_OSC (0x1 << 6) -#define AUX_TERMINAL_CTRL_37_5_OHM (0x0 << 4) -#define AUX_TERMINAL_CTRL_45_OHM (0x1 << 4) -#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) -#define AUX_TERMINAL_CTRL_65_OHM (0x3 << 4) -#define TX_CUR1_2X (0x1 << 2) -#define TX_CUR_16_MA (0x3 << 0) - -/* Definition for DPCD Register */ -#define DPCD_DPCD_REV (0x0000) -#define DPCD_MAX_LINK_RATE (0x0001) -#define DPCD_MAX_LANE_COUNT (0x0002) -#define DP_MAX_LANE_COUNT_MASK 0x1f -#define DP_TPS3_SUPPORTED (1 << 6) -#define DP_ENHANCED_FRAME_CAP (1 << 7) - -#define DPCD_LINK_BW_SET (0x0100) -#define DPCD_LANE_COUNT_SET (0x0101) - -#define DPCD_TRAINING_PATTERN_SET (0x0102) -#define DP_TRAINING_PATTERN_DISABLE 0 -#define DP_TRAINING_PATTERN_1 1 -#define DP_TRAINING_PATTERN_2 2 -#define DP_TRAINING_PATTERN_3 3 -#define DP_TRAINING_PATTERN_MASK 0x3 - -#define DPCD_TRAINING_LANE0_SET (0x0103) -#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -#define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -#define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -#define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -#define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -#define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - -#define DPCD_LANE0_1_STATUS (0x0202) -#define DPCD_LANE2_3_STATUS (0x0203) -#define DP_LANE_CR_DONE (1 << 0) -#define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -#define DP_LANE_SYMBOL_LOCKED (1 << 2) -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |\ - DP_LANE_CHANNEL_EQ_DONE |\ - DP_LANE_SYMBOL_LOCKED) - -#define DPCD_LANE_ALIGN_STATUS_UPDATED (0x0204) -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) -#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) -#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DPCD_TEST_REQUEST (0x0218) -#define DPCD_TEST_RESPONSE (0x0260) -#define DPCD_TEST_EDID_CHECKSUM (0x0261) -#define DPCD_LINK_POWER_STATE (0x0600) -#define DP_SET_POWER_D0 0x1 -#define DP_SET_POWER_D3 0x2 -#define DP_SET_POWER_MASK 0x3 - -#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) -#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) -#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) - -#define STREAM_ON_TIMEOUT 100 -#define PLL_LOCK_TIMEOUT 10 -#define DP_INIT_TRIES 10 - -#define EDID_ADDR 0x50 -#define EDID_LENGTH 0x80 -#define EDID_HEADER 0x00 -#define EDID_EXTENSION_FLAG 0x7e - - -enum dpcd_request { - DPCD_READ, - DPCD_WRITE, -}; - -enum dp_irq_type { - DP_IRQ_TYPE_HP_CABLE_IN, - DP_IRQ_TYPE_HP_CABLE_OUT, - DP_IRQ_TYPE_HP_CHANGE, - DP_IRQ_TYPE_UNKNOWN, -}; - -enum color_coefficient { - COLOR_YCBCR601, - COLOR_YCBCR709 -}; - -enum dynamic_range { - VESA, - CEA -}; - -enum clock_recovery_m_value_type { - CALCULATED_M, - REGISTER_M -}; - -enum video_timing_recognition_type { - VIDEO_TIMING_FROM_CAPTURE, - VIDEO_TIMING_FROM_REGISTER -}; - -enum pattern_set { - PRBS7, - D10_2, - TRAINING_PTN1, - TRAINING_PTN2, - DP_NONE -}; - -enum color_space { - CS_RGB, - CS_YCBCR422, - CS_YCBCR444 -}; - -enum color_depth { - COLOR_6, - COLOR_8, - COLOR_10, - COLOR_12 -}; - -enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a -}; - -enum link_lane_count_type { - LANE_CNT1 = 1, - LANE_CNT2 = 2, - LANE_CNT4 = 4 -}; - -enum link_training_state { - LT_START, - LT_CLK_RECOVERY, - LT_EQ_TRAINING, - FINISHED, - FAILED -}; - -enum voltage_swing_level { - VOLTAGE_LEVEL_0, - VOLTAGE_LEVEL_1, - VOLTAGE_LEVEL_2, - VOLTAGE_LEVEL_3, -}; - -enum pre_emphasis_level { - PRE_EMPHASIS_LEVEL_0, - PRE_EMPHASIS_LEVEL_1, - PRE_EMPHASIS_LEVEL_2, - PRE_EMPHASIS_LEVEL_3, -}; - -enum analog_power_block { - AUX_BLOCK, - CH0_BLOCK, - CH1_BLOCK, - CH2_BLOCK, - CH3_BLOCK, - ANALOG_TOTAL, - POWER_ALL -}; - -struct link_train { - unsigned char revision; - u8 link_rate; - u8 lane_count; -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h deleted file mode 100644 index 9772321..0000000 --- a/arch/arm/include/asm/arch-rockchip/f_rockusb.h +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 - * - * Eddie Cai <eddie.cai.linux@gmail.com> - */ - -#ifndef _F_ROCKUSB_H_ -#define _F_ROCKUSB_H_ -#include <blk.h> - -#define ROCKUSB_VERSION "0.1" - -#define ROCKUSB_INTERFACE_CLASS 0xff -#define ROCKUSB_INTERFACE_SUB_CLASS 0x06 -#define ROCKUSB_INTERFACE_PROTOCOL 0x05 - -#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 0x0200 -#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 0x0040 -#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE 0x0040 - -#define EP_BUFFER_SIZE 4096 -/* - * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size - * (64 or 512 or 1024), else we break on certain controllers like DWC3 - * that expect bulk OUT requests to be divisible by maxpacket size. - */ - -#define RKUSB_BUF_SIZE EP_BUFFER_SIZE * 2 -#define RKBLOCK_BUF_SIZE 4096 - -#define RKUSB_STATUS_IDLE 0 -#define RKUSB_STATUS_CMD 1 -#define RKUSB_STATUS_RXDATA 2 -#define RKUSB_STATUS_TXDATA 3 -#define RKUSB_STATUS_CSW 4 -#define RKUSB_STATUS_RXDATA_PREPARE 5 -#define RKUSB_STATUS_TXDATA_PREPARE 6 - -enum rkusb_command { -K_FW_TEST_UNIT_READY = 0x00, -K_FW_READ_FLASH_ID = 0x01, -K_FW_SET_DEVICE_ID = 0x02, -K_FW_TEST_BAD_BLOCK = 0x03, -K_FW_READ_10 = 0x04, -K_FW_WRITE_10 = 0x05, -K_FW_ERASE_10 = 0x06, -K_FW_WRITE_SPARE = 0x07, -K_FW_READ_SPARE = 0x08, - -K_FW_ERASE_10_FORCE = 0x0b, -K_FW_GET_VERSION = 0x0c, - -K_FW_LBA_READ_10 = 0x14, -K_FW_LBA_WRITE_10 = 0x15, -K_FW_ERASE_SYS_DISK = 0x16, -K_FW_SDRAM_READ_10 = 0x17, -K_FW_SDRAM_WRITE_10 = 0x18, -K_FW_SDRAM_EXECUTE = 0x19, -K_FW_READ_FLASH_INFO = 0x1A, -K_FW_GET_CHIP_VER = 0x1B, -K_FW_LOW_FORMAT = 0x1C, -K_FW_SET_RESET_FLAG = 0x1E, -K_FW_SPI_READ_10 = 0x21, -K_FW_SPI_WRITE_10 = 0x22, -K_FW_LBA_ERASE_10 = 0x25, - -K_FW_SESSION = 0X30, -K_FW_RESET = 0xff, -}; - -#define CBW_DIRECTION_OUT 0x00 -#define CBW_DIRECTION_IN 0x80 - -struct cmd_dispatch_info { - enum rkusb_command cmd; - /* call back function to handle rockusb command */ - void (*cb)(struct usb_ep *ep, struct usb_request *req); -}; - -/* Bulk-only data structures */ - -/* Command Block Wrapper */ -struct fsg_bulk_cb_wrap { - __le32 signature; /* Contains 'USBC' */ - u32 tag; /* Unique per command id */ - __le32 data_transfer_length; /* Size of the data */ - u8 flags; /* Direction in bit 7 */ - u8 lun; /* lun (normally 0) */ - u8 length; /* Of the CDB, <= MAX_COMMAND_SIZE */ - u8 CDB[16]; /* Command Data Block */ -}; - -#define USB_BULK_CB_WRAP_LEN 31 -#define USB_BULK_CB_SIG 0x43425355 /* Spells out USBC */ -#define USB_BULK_IN_FLAG 0x80 - -/* Command status Wrapper */ -struct bulk_cs_wrap { - __le32 signature; /* Should = 'USBS' */ - u32 tag; /* Same as original command */ - __le32 residue; /* Amount not transferred */ - u8 status; /* See below */ -}; - -#define USB_BULK_CS_WRAP_LEN 13 -#define USB_BULK_CS_SIG 0x53425355 /* Spells out 'USBS' */ -#define USB_STATUS_PASS 0 -#define USB_STATUS_FAIL 1 -#define USB_STATUS_PHASE_ERROR 2 - -#define CSW_GOOD 0x00 -#define CSW_FAIL 0x01 - -struct f_rockusb { - struct usb_function usb_function; - struct usb_ep *in_ep, *out_ep; - struct usb_request *in_req, *out_req; - char *dev_type; - unsigned int dev_index; - unsigned int tag; - unsigned int lba; - unsigned int dl_size; - unsigned int dl_bytes; - unsigned int ul_size; - unsigned int ul_bytes; - struct blk_desc *desc; - int reboot_flag; - void *buf; - void *buf_head; -}; - -/* init rockusb device, tell rockusb which device you want to read/write*/ -void rockusb_dev_init(char *dev_type, int dev_index); -#endif /* _F_ROCKUSB_H_ */ - diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h deleted file mode 100644 index 1aaec5f..0000000 --- a/arch/arm/include/asm/arch-rockchip/gpio.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef _ASM_ARCH_GPIO_H -#define _ASM_ARCH_GPIO_H - -struct rockchip_gpio_regs { - u32 swport_dr; - u32 swport_ddr; - u32 reserved0[(0x30 - 0x08) / 4]; - u32 inten; - u32 intmask; - u32 inttype_level; - u32 int_polarity; - u32 int_status; - u32 int_rawstatus; - u32 debounce; - u32 porta_eoi; - u32 ext_port; - u32 reserved1[(0x60 - 0x54) / 4]; - u32 ls_sync; -}; -check_member(rockchip_gpio_regs, ls_sync, 0x60); - -enum gpio_pu_pd { - GPIO_PULL_NORMAL = 0, - GPIO_PULL_UP, - GPIO_PULL_DOWN, - GPIO_PULL_REPEAT, -}; - -/* These defines are only used by spl_gpio.h */ -enum { - /* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */ - GPIO_BANK_SHIFT = 3, - GPIO_BANK_MASK = 3 << GPIO_BANK_SHIFT, - - GPIO_OFFSET_MASK = 0x1f, -}; - -#define GPIO(bank, offset) ((bank) << GPIO_BANK_SHIFT | (offset)) - -enum gpio_bank_t { - BANK_A = 0, - BANK_B, - BANK_C, - BANK_D, -}; - -enum gpio_dir_t { - GPIO_INPUT = 0, - GPIO_OUTPUT, -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h deleted file mode 100644 index 5f12ebf..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ -#ifndef _ASM_ARCH_GRF_RK3036_H -#define _ASM_ARCH_GRF_RK3036_H - -#include <common.h> - -struct rk3036_grf { - unsigned int reserved[0x2a]; - unsigned int gpio0a_iomux; - unsigned int gpio0b_iomux; - unsigned int gpio0c_iomux; - unsigned int gpio0d_iomux; - - unsigned int gpio1a_iomux; - unsigned int gpio1b_iomux; - unsigned int gpio1c_iomux; - unsigned int gpio1d_iomux; - - unsigned int gpio2a_iomux; - unsigned int gpio2b_iomux; - unsigned int gpio2c_iomux; - unsigned int gpio2d_iomux; - - unsigned int reserved2[0x0a]; - unsigned int gpiods; - unsigned int reserved3[0x05]; - unsigned int gpio0l_pull; - unsigned int gpio0h_pull; - unsigned int gpio1l_pull; - unsigned int gpio1h_pull; - unsigned int gpio2l_pull; - unsigned int gpio2h_pull; - unsigned int reserved4[4]; - unsigned int soc_con0; - unsigned int soc_con1; - unsigned int soc_con2; - unsigned int soc_status0; - unsigned int reserved5; - unsigned int soc_con3; - unsigned int reserved6; - unsigned int dmac_con0; - unsigned int dmac_con1; - unsigned int dmac_con2; - unsigned int reserved7[5]; - unsigned int uoc0_con5; - unsigned int reserved8[4]; - unsigned int uoc1_con4; - unsigned int uoc1_con5; - unsigned int reserved9; - unsigned int ddrc_stat; - unsigned int uoc_con6; - unsigned int soc_status1; - unsigned int cpu_con0; - unsigned int cpu_con1; - unsigned int cpu_con2; - unsigned int cpu_con3; - unsigned int reserved10; - unsigned int reserved11; - unsigned int cpu_status0; - unsigned int cpu_status1; - unsigned int os_reg[8]; - unsigned int reserved12[6]; - unsigned int dll_con[4]; - unsigned int dll_status[4]; - unsigned int dfi_wrnum; - unsigned int dfi_rdnum; - unsigned int dfi_actnum; - unsigned int dfi_timerval; - unsigned int nfi_fifo[4]; - unsigned int reserved13[0x10]; - unsigned int usbphy0_con[8]; - unsigned int usbphy1_con[8]; - unsigned int reserved14[0x10]; - unsigned int chip_tag; - unsigned int sdmmc_det_cnt; -}; -check_member(rk3036_grf, sdmmc_det_cnt, 0x304); - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h deleted file mode 100644 index 519b36a..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h +++ /dev/null @@ -1,550 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ -#ifndef _ASM_ARCH_GRF_RK3128_H -#define _ASM_ARCH_GRF_RK3128_H - -#include <common.h> - -struct rk3128_grf { - unsigned int reserved[0x2a]; - unsigned int gpio0a_iomux; - unsigned int gpio0b_iomux; - unsigned int gpio0c_iomux; - unsigned int gpio0d_iomux; - unsigned int gpio1a_iomux; - unsigned int gpio1b_iomux; - unsigned int gpio1c_iomux; - unsigned int gpio1d_iomux; - unsigned int gpio2a_iomux; - unsigned int gpio2b_iomux; - unsigned int gpio2c_iomux; - unsigned int gpio2d_iomux; - unsigned int gpio3a_iomux; - unsigned int gpio3b_iomux; - unsigned int gpio3c_iomux; - unsigned int gpio3d_iomux; - unsigned int gpio2c_iomux2; - unsigned int grf_cif_iomux; - unsigned int grf_cif_iomux1; - unsigned int reserved1[(0x118 - 0xf0) / 4 - 1]; - unsigned int gpio0l_pull; - unsigned int gpio0h_pull; - unsigned int gpio1l_pull; - unsigned int gpio1h_pull; - unsigned int gpio2l_pull; - unsigned int gpio2h_pull; - unsigned int gpio3l_pull; - unsigned int gpio3h_pull; - unsigned int reserved2; - unsigned int soc_con0; - unsigned int soc_con1; - unsigned int soc_con2; - unsigned int soc_status0; - unsigned int reserved3[6]; - unsigned int mac_con0; - unsigned int mac_con1; - unsigned int reserved4[4]; - unsigned int uoc0_con0; - unsigned int reserved5; - unsigned int uoc1_con1; - unsigned int uoc1_con2; - unsigned int uoc1_con3; - unsigned int uoc1_con4; - unsigned int uoc1_con5; - unsigned int reserved6; - unsigned int ddrc_stat; - unsigned int reserved9; - unsigned int soc_status1; - unsigned int cpu_con0; - unsigned int cpu_con1; - unsigned int cpu_con2; - unsigned int cpu_con3; - unsigned int reserved10; - unsigned int reserved11; - unsigned int cpu_status0; - unsigned int cpu_status1; - unsigned int os_reg[8]; - unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1]; - unsigned int usbphy0_con[8]; - unsigned int usbphy1_con[8]; - unsigned int uoc_status0; - unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1]; - unsigned int chip_tag; - unsigned int sdmmc_det_cnt; -}; -check_member(rk3128_grf, sdmmc_det_cnt, 0x304); - -struct rk3128_pmu { - unsigned int wakeup_cfg; - unsigned int pwrdn_con; - unsigned int pwrdn_st; - unsigned int idle_req; - unsigned int idle_st; - unsigned int pwrmode_con; - unsigned int pwr_state; - unsigned int osc_cnt; - unsigned int core_pwrdwn_cnt; - unsigned int core_pwrup_cnt; - unsigned int sft_con; - unsigned int ddr_sref_st; - unsigned int int_con; - unsigned int int_st; - unsigned int sys_reg[4]; -}; -check_member(rk3128_pmu, int_st, 0x34); - -/* GRF_GPIO0A_IOMUX */ -enum { - GPIO0A7_SHIFT = 14, - GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, - GPIO0A7_GPIO = 0, - GPIO0A7_I2C3_SDA, - - GPIO0A6_SHIFT = 12, - GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, - GPIO0A6_GPIO = 0, - GPIO0A6_I2C3_SCL, - - GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, - GPIO0A3_GPIO = 0, - GPIO0A3_I2C1_SDA, - - GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, - GPIO0A2_GPIO = 0, - GPIO0A2_I2C1_SCL, - - GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 1 << GPIO0A1_SHIFT, - GPIO0A1_GPIO = 0, - GPIO0A1_I2C0_SDA, - - GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 1 << GPIO0A0_SHIFT, - GPIO0A0_GPIO = 0, - GPIO0A0_I2C0_SCL, -}; - -/* GRF_GPIO0B_IOMUX */ -enum { - GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, - GPIO0B6_GPIO = 0, - GPIO0B6_I2S_SDI, - GPIO0B6_SPI_CSN0, - - GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, - GPIO0B5_GPIO = 0, - GPIO0B5_I2S_SDO, - GPIO0B5_SPI_RXD, - - GPIO0B4_SHIFT = 8, - GPIO0B4_MASK = 1 << GPIO0B4_SHIFT, - GPIO0B4_GPIO = 0, - GPIO0B4_I2S_LRCKTX, - - GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, - GPIO0B3_GPIO = 0, - GPIO0B3_I2S_LRCKRX, - GPIO0B3_SPI_TXD, - - GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3, - GPIO0B1_GPIO = 0, - GPIO0B1_I2S_SCLK, - GPIO0B1_SPI_CLK, - - GPIO0B0_SHIFT = 0, - GPIO0B0_MASK = 3, - GPIO0B0_GPIO = 0, - GPIO0B0_I2S1_MCLK, -}; - -/* GRF_GPIO0D_IOMUX */ -enum { - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_PWM2, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_PWM1, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_PWM0, - - GPIO0D1_SHIFT = 2, - GPIO0D1_MASK = 1 << GPIO0D1_SHIFT, - GPIO0D1_GPIO = 0, - GPIO0D1_UART2_CTSN, - - GPIO0D0_SHIFT = 0, - GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, - GPIO0D0_GPIO = 0, - GPIO0D0_UART2_RTSN, - GPIO0D0_PMIC_SLEEP, -}; - -/* GRF_GPIO1A_IOMUX */ -enum { - GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 3 << GPIO1A5_SHIFT, - GPIO1A5_GPIO = 0, - GPIO1A5_I2S_SDI, - GPIO1A5_SDMMC_DATA3, - - GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 3 << GPIO1A4_SHIFT, - GPIO1A4_GPIO = 0, - GPIO1A4_I2S_SD0, - GPIO1A4_SDMMC_DATA2, - - GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, - GPIO1A3_GPIO = 0, - GPIO1A3_I2S_LRCKTX, - - GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, - GPIO1A2_GPIO = 0, - GPIO1A2_I2S_LRCKRX, - GPIO1A2_SDMMC_DATA1, - - GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 3 << GPIO1A1_SHIFT, - GPIO1A1_GPIO = 0, - GPIO1A1_I2S_SCLK, - GPIO1A1_SDMMC_DATA0, - GPIO1A1_PMIC_SLEEP, - - GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 3, - GPIO1A0_GPIO = 0, - GPIO1A0_I2S_MCLK, - GPIO1A0_SDMMC_CLKOUT, - GPIO1A0_XIN32K, - -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, - GPIO1B7_GPIO = 0, - GPIO1B7_MMC0_CMD, - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = 1 << GPIO1B6_SHIFT, - GPIO1B6_GPIO = 0, - GPIO1B6_MMC_PWREN, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_SPI_RXD, - GPIO1B2_UART1_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_SPI_TXD, - GPIO1B1_UART1_SOUT, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 3 << GPIO1B0_SHIFT, - GPIO1B0_GPIO = 0, - GPIO1B0_SPI_CLK, - GPIO1B0_UART1_CTSN -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C6_SHIFT = 12, - GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, - GPIO1C6_GPIO = 0, - GPIO1C6_NAND_CS2, - GPIO1C6_EMMC_CMD, - - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, - GPIO1C5_GPIO = 0, - GPIO1C5_MMC0_D3, - GPIO1C5_JTAG_TMS, - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, - GPIO1C4_GPIO = 0, - GPIO1C4_MMC0_D2, - GPIO1C4_JTAG_TCK, - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, - GPIO1C3_GPIO = 0, - GPIO1C3_MMC0_D1, - GPIO1C3_UART2_RX, - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, - GPIO1C2_GPIO = 0, - GPIO1C2_MMC0_D0, - GPIO1C2_UART2_TX, - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, - GPIO1C1_GPIO = 0, - GPIO1C1_MMC0_DETN, - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, - GPIO1C0_GPIO = 0, - GPIO1C0_MMC0_CLKOUT, -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, - GPIO1D7_GPIO = 0, - GPIO1D7_NAND_D7, - GPIO1D7_EMMC_D7, - GPIO1D7_SPI_CSN1, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, - GPIO1D6_GPIO = 0, - GPIO1D6_NAND_D6, - GPIO1D6_EMMC_D6, - GPIO1D6_SPI_CSN0, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, - GPIO1D5_GPIO = 0, - GPIO1D5_NAND_D5, - GPIO1D5_EMMC_D5, - GPIO1D5_SPI_TXD1, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, - GPIO1D4_GPIO = 0, - GPIO1D4_NAND_D4, - GPIO1D4_EMMC_D4, - GPIO1D4_SPI_RXD1, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_NAND_D3, - GPIO1D3_EMMC_D3, - GPIO1D3_SFC_SIO3, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_NAND_D2, - GPIO1D2_EMMC_D2, - GPIO1D2_SFC_SIO2, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, - GPIO1D1_GPIO = 0, - GPIO1D1_NAND_D1, - GPIO1D1_EMMC_D1, - GPIO1D1_SFC_SIO1, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, - GPIO1D0_GPIO = 0, - GPIO1D0_NAND_D0, - GPIO1D0_EMMC_D0, - GPIO1D0_SFC_SIO0, -}; - -/* GRF_GPIO2A_IOMUX */ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_NAND_DQS, - GPIO2A7_EMMC_CLKOUT, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_NAND_CS0, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_NAND_WP, - GPIO2A5_EMMC_PWREN, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_NAND_RDY, - GPIO2A4_EMMC_CMD, - GPIO2A3_SFC_CLK, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_NAND_RDN, - GPIO2A4_SFC_CSN1, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_NAND_WRN, - GPIO2A4_SFC_CSN0, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_NAND_CLE, - GPIO2A1_EMMC_CLKOUT, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_NAND_ALE, - GPIO2A0_SPI_CLK, -}; - -/* GRF_GPIO2B_IOMUX */ -enum { - GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, - GPIO2B7_GPIO = 0, - GPIO2B7_LCDC0_D13, - GPIO2B7_EBC_SDCE5, - GPIO2B7_GMAC_RXER, - - GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, - GPIO2B6_GPIO = 0, - GPIO2B6_LCDC0_D12, - GPIO2B6_EBC_SDCE4, - GPIO2B6_GMAC_CLK, - - GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, - GPIO2B5_GPIO = 0, - GPIO2B5_LCDC0_D11, - GPIO2B5_EBC_SDCE3, - GPIO2B5_GMAC_TXEN, - - GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, - GPIO2B4_GPIO = 0, - GPIO2B4_LCDC0_D10, - GPIO2B4_EBC_SDCE2, - GPIO2B4_GMAC_MDIO, - - GPIO2B3_SHIFT = 6, - GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, - GPIO2B3_GPIO = 0, - GPIO2B3_LCDC0_DEN, - GPIO2B3_EBC_GDCLK, - GPIO2B3_GMAC_RXCLK, - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, - GPIO2B2_GPIO = 0, - GPIO2B2_LCDC0_VSYNC, - GPIO2B2_EBC_SDOE, - GPIO2B2_GMAC_CRS, - - GPIO2B1_SHIFT = 2, - GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, - GPIO2B1_GPIO = 0, - GPIO2B1_LCDC0_HSYNC, - GPIO2B1_EBC_SDLE, - GPIO2B1_GMAC_TXCLK, - - GPIO2B0_SHIFT = 0, - GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, - GPIO2B0_GPIO = 0, - GPIO2B0_LCDC0_DCLK, - GPIO2B0_EBC_SDCLK, - GPIO2B0_GMAC_RXDV, -}; - -/* GRF_GPIO2C_IOMUX */ -enum { - GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, - GPIO2C3_GPIO = 0, - GPIO2C3_LCDC0_D17, - GPIO2C3_EBC_GDPWR0, - GPIO2C3_GMAC_TXD0, - - GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, - GPIO2C2_GPIO = 0, - GPIO2C2_LCDC0_D16, - GPIO2C2_EBC_GDSP, - GPIO2C2_GMAC_TXD1, - - GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, - GPIO2C1_GPIO = 0, - GPIO2C1_LCDC0_D15, - GPIO2C1_EBC_GDOE, - GPIO2C1_GMAC_RXD0, - - GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, - GPIO2C0_GPIO = 0, - GPIO2C0_LCDC0_D14, - GPIO2C0_EBC_VCOM, - GPIO2C0_GMAC_RXD1, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_LCDC0_D22, - GPIO2D6_GMAC_COL = 4, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_GMAC_MDC = 3, -}; - -/* GRF_GPIO2C_IOMUX2 */ -enum { - GPIO2C7_SHIFT = 12, - GPIO2C7_MASK = 7 << GPIO2C7_SHIFT, - GPIO2C7_GPIO = 0, - GPIO2C7_GMAC_TXD3 = 4, - - GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 7 << GPIO2C6_SHIFT, - GPIO2C6_GPIO = 0, - GPIO2C6_GMAC_TXD2 = 4, - - GPIO2C5_SHIFT = 4, - GPIO2C5_MASK = 7 << GPIO2C5_SHIFT, - GPIO2C5_GPIO = 0, - GPIO2C5_I2C2_SCL = 3, - GPIO2C5_GMAC_RXD2, - - GPIO2C4_SHIFT = 0, - GPIO2C4_MASK = 7 << GPIO2C4_SHIFT, - GPIO2C4_GPIO = 0, - GPIO2C4_I2C2_SDA = 3, - GPIO2C4_GMAC_RXD2, -}; -#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h deleted file mode 100644 index d051976..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _ASM_ARCH_GRF_RK3188_H -#define _ASM_ARCH_GRF_RK3188_H - -struct rk3188_grf_gpio_lh { - u32 l; - u32 h; -}; - -struct rk3188_grf { - struct rk3188_grf_gpio_lh gpio_dir[4]; - struct rk3188_grf_gpio_lh gpio_do[4]; - struct rk3188_grf_gpio_lh gpio_en[4]; - - u32 reserved[2]; - u32 gpio0c_iomux; - u32 gpio0d_iomux; - - u32 gpio1a_iomux; - u32 gpio1b_iomux; - u32 gpio1c_iomux; - u32 gpio1d_iomux; - - u32 gpio2a_iomux; - u32 gpio2b_iomux; - u32 gpio2c_iomux; - u32 gpio2d_iomux; - - u32 gpio3a_iomux; - u32 gpio3b_iomux; - u32 gpio3c_iomux; - u32 gpio3d_iomux; - - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_status0; - - u32 busdmac_con[3]; - u32 peridmac_con[4]; - - u32 cpu_con[6]; - u32 reserved0[2]; - - u32 ddrc_con0; - u32 ddrc_stat; - - u32 io_con[5]; - u32 soc_status1; - - u32 uoc0_con[4]; - u32 uoc1_con[4]; - u32 uoc2_con[2]; - u32 reserved1; - u32 uoc3_con[2]; - u32 hsic_stat; - u32 os_reg[8]; - - u32 gpio0_p[3]; - u32 gpio1_p[3][4]; - - u32 flash_data_p; - u32 flash_cmd_p; -}; -check_member(rk3188_grf, flash_cmd_p, 0x01a4); - -/* GRF_SOC_CON0 */ -enum { - HSADC_CLK_DIR_SHIFT = 15, - HSADC_CLK_DIR_MASK = 1, - - HSADC_SEL_SHIFT = 14, - HSADC_SEL_MASK = 1, - - NOC_REMAP_SHIFT = 12, - NOC_REMAP_MASK = 1, - - EMMC_FLASH_SEL_SHIFT = 11, - EMMC_FLASH_SEL_MASK = 1, - - TZPC_REVISION_SHIFT = 7, - TZPC_REVISION_MASK = 0xf, - - L2CACHE_ACC_SHIFT = 5, - L2CACHE_ACC_MASK = 3, - - L2RD_WAIT_SHIFT = 3, - L2RD_WAIT_MASK = 3, - - IMEMRD_WAIT_SHIFT = 1, - IMEMRD_WAIT_MASK = 3, -}; - -/* GRF_SOC_CON1 */ -enum { - RKI2C4_SEL_SHIFT = 15, - RKI2C4_SEL_MASK = 1, - - RKI2C3_SEL_SHIFT = 14, - RKI2C3_SEL_MASK = 1, - - RKI2C2_SEL_SHIFT = 13, - RKI2C2_SEL_MASK = 1, - - RKI2C1_SEL_SHIFT = 12, - RKI2C1_SEL_MASK = 1, - - RKI2C0_SEL_SHIFT = 11, - RKI2C0_SEL_MASK = 1, - - VCODEC_SEL_SHIFT = 10, - VCODEC_SEL_MASK = 1, - - PERI_EMEM_PAUSE_SHIFT = 9, - PERI_EMEM_PAUSE_MASK = 1, - - PERI_USB_PAUSE_SHIFT = 8, - PERI_USB_PAUSE_MASK = 1, - - SMC_MUX_MODE_0_SHIFT = 6, - SMC_MUX_MODE_0_MASK = 1, - - SMC_SRAM_MW_0_SHIFT = 4, - SMC_SRAM_MW_0_MASK = 3, - - SMC_REMAP_0_SHIFT = 3, - SMC_REMAP_0_MASK = 1, - - SMC_A_GT_M0_SYNC_SHIFT = 2, - SMC_A_GT_M0_SYNC_MASK = 1, - - EMAC_SPEED_SHIFT = 1, - EMAC_SPEEC_MASK = 1, - - EMAC_MODE_SHIFT = 0, - EMAC_MODE_MASK = 1, -}; - -/* GRF_SOC_CON2 */ -enum { - SDIO_CLK_OUT_SR_SHIFT = 15, - SDIO_CLK_OUT_SR_MASK = 1, - - MEM_EMA_L2C_SHIFT = 11, - MEM_EMA_L2C_MASK = 7, - - MEM_EMA_A9_SHIFT = 8, - MEM_EMA_A9_MASK = 7, - - MSCH4_MAINDDR3_SHIFT = 7, - MSCH4_MAINDDR3_MASK = 1, - MSCH4_MAINDDR3_DDR3 = 1, - - EMAC_NEWRCV_EN_SHIFT = 6, - EMAC_NEWRCV_EN_MASK = 1, - - SW_ADDR15_EN_SHIFT = 5, - SW_ADDR15_EN_MASK = 1, - - SW_ADDR16_EN_SHIFT = 4, - SW_ADDR16_EN_MASK = 1, - - SW_ADDR17_EN_SHIFT = 3, - SW_ADDR17_EN_MASK = 1, - - BANK2_TO_RANK_EN_SHIFT = 2, - BANK2_TO_RANK_EN_MASK = 1, - - RANK_TO_ROW15_EN_SHIFT = 1, - RANK_TO_ROW15_EN_MASK = 1, - - UPCTL_C_ACTIVE_IN_SHIFT = 0, - UPCTL_C_ACTIVE_IN_MASK = 1, - UPCTL_C_ACTIVE_IN_MAY = 0, - UPCTL_C_ACTIVE_IN_WILL, -}; - -/* GRF_DDRC_CON0 */ -enum { - DDR_16BIT_EN_SHIFT = 15, - DDR_16BIT_EN_MASK = 1, - - DTO_LB_SHIFT = 11, - DTO_LB_MASK = 3, - - DTO_TE_SHIFT = 9, - DTO_TE_MASK = 3, - - DTO_PDR_SHIFT = 7, - DTO_PDR_MASK = 3, - - DTO_PDD_SHIFT = 5, - DTO_PDD_MASK = 3, - - DTO_IOM_SHIFT = 3, - DTO_IOM_MASK = 3, - - DTO_OE_SHIFT = 1, - DTO_OE_MASK = 3, - - ATO_AE_SHIFT = 0, - ATO_AE_MASK = 1, -}; - -/* GRF_UOC_CON0 */ -enum { - SIDDQ_SHIFT = 13, - SIDDQ_MASK = 1 << SIDDQ_SHIFT, - - BYPASSSEL_SHIFT = 9, - BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT, - - BYPASSDMEN_SHIFT = 8, - BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT, - - UOC_DISABLE_SHIFT = 4, - UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT, - - COMMON_ON_N_SHIFT = 0, - COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT, -}; - -/* GRF_UOC_CON2 */ -enum { - SOFT_CON_SEL_SHIFT = 2, - SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT, -}; - -/* GRF_UOC0_CON3 */ -enum { - TERMSEL_FULLSPEED_SHIFT = 5, - TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT, - - XCVRSELECT_SHIFT = 3, - XCVRSELECT_FSTRANSC = 1, - XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT, - - OPMODE_SHIFT = 1, - OPMODE_NODRIVING = 1, - OPMODE_MASK = 3 << OPMODE_SHIFT, - - SUSPENDN_SHIFT = 0, - SUSPENDN_MASK = 1 << SUSPENDN_SHIFT, -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h deleted file mode 100644 index a99d137..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ -#ifndef _ASM_ARCH_GRF_RK322X_H -#define _ASM_ARCH_GRF_RK322X_H - -#include <common.h> - -struct rk322x_grf { - unsigned int gpio0a_iomux; - unsigned int gpio0b_iomux; - unsigned int gpio0c_iomux; - unsigned int gpio0d_iomux; - - unsigned int gpio1a_iomux; - unsigned int gpio1b_iomux; - unsigned int gpio1c_iomux; - unsigned int gpio1d_iomux; - - unsigned int gpio2a_iomux; - unsigned int gpio2b_iomux; - unsigned int gpio2c_iomux; - unsigned int gpio2d_iomux; - - unsigned int gpio3a_iomux; - unsigned int gpio3b_iomux; - unsigned int gpio3c_iomux; - unsigned int gpio3d_iomux; - - unsigned int reserved1[4]; - unsigned int con_iomux; - unsigned int reserved2[(0x100 - 0x50) / 4 - 1]; - unsigned int gpio0_p[4]; - unsigned int gpio1_p[4]; - unsigned int gpio2_p[4]; - unsigned int gpio3_p[4]; - unsigned int reserved3[(0x200 - 0x13c) / 4 - 1]; - unsigned int gpio0_e[4]; - unsigned int gpio1_e[4]; - unsigned int gpio2_e[4]; - unsigned int gpio3_e[4]; - unsigned int reserved4[(0x400 - 0x23c) / 4 - 1]; - unsigned int soc_con[7]; - unsigned int reserved5[(0x480 - 0x418) / 4 - 1]; - unsigned int soc_status[3]; - unsigned int chip_id; - unsigned int reserved6[(0x500 - 0x48c) / 4 - 1]; - unsigned int cpu_con[4]; - unsigned int reserved7[4]; - unsigned int cpu_status[2]; - unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1]; - unsigned int os_reg[8]; - unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1]; - unsigned int ddrc_stat; - unsigned int reserved10[(0x680 - 0x604) / 4 - 1]; - unsigned int sig_detect_con[2]; - unsigned int reserved11[(0x690 - 0x684) / 4 - 1]; - unsigned int sig_detect_status[2]; - unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1]; - unsigned int sig_detect_clr[2]; - unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1]; - unsigned int emmc_det; - unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1]; - unsigned int host0_con[3]; - unsigned int reserved15; - unsigned int host1_con[3]; - unsigned int reserved16; - unsigned int host2_con[3]; - unsigned int reserved17[(0x760 - 0x728) / 4 - 1]; - unsigned int usbphy0_con[27]; - unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1]; - unsigned int usbphy1_con[27]; - unsigned int reserved19[(0x880 - 0x868) / 4 - 1]; - unsigned int otg_con0; - unsigned int uoc_status0; - unsigned int reserved20[(0x900 - 0x884) / 4 - 1]; - unsigned int mac_con[2]; - unsigned int reserved21[(0xb00 - 0x904) / 4 - 1]; - unsigned int macphy_con[4]; - unsigned int macphy_status; -}; -check_member(rk322x_grf, ddrc_stat, 0x604); - -struct rk322x_sgrf { - unsigned int soc_con[11]; - unsigned int busdmac_con[4]; -}; - -/* GRF_MACPHY_CON0 */ -enum { - MACPHY_CFG_ENABLE_SHIFT = 0, - MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT, -}; -#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h deleted file mode 100644 index 894d3a4..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ /dev/null @@ -1,1155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2015 Google, Inc - * Copyright 2014 Rockchip Inc. - */ - -#ifndef _ASM_ARCH_GRF_RK3288_H -#define _ASM_ARCH_GRF_RK3288_H - -struct rk3288_grf_gpio_lh { - u32 l; - u32 h; -}; - -struct rk3288_grf { - u32 reserved[3]; - u32 gpio1d_iomux; - u32 gpio2a_iomux; - u32 gpio2b_iomux; - - u32 gpio2c_iomux; - u32 reserved2; - u32 gpio3a_iomux; - u32 gpio3b_iomux; - - u32 gpio3c_iomux; - u32 gpio3dl_iomux; - u32 gpio3dh_iomux; - u32 gpio4al_iomux; - - u32 gpio4ah_iomux; - u32 gpio4bl_iomux; - u32 reserved3; - u32 gpio4c_iomux; - - u32 gpio4d_iomux; - u32 reserved4; - u32 gpio5b_iomux; - u32 gpio5c_iomux; - - u32 reserved5; - u32 gpio6a_iomux; - u32 gpio6b_iomux; - u32 gpio6c_iomux; - u32 reserved6; - u32 gpio7a_iomux; - u32 gpio7b_iomux; - u32 gpio7cl_iomux; - u32 gpio7ch_iomux; - u32 reserved7; - u32 gpio8a_iomux; - u32 gpio8b_iomux; - u32 reserved8[30]; - struct rk3288_grf_gpio_lh gpio_sr[8]; - u32 gpio1_p[8][4]; - u32 gpio1_e[8][4]; - u32 gpio_smt; - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_status[22]; - u32 reserved9[2]; - u32 peridmac_con[4]; - u32 ddrc0_con0; - u32 ddrc1_con0; - u32 cpu_con[5]; - u32 reserved10[3]; - u32 cpu_status0; - u32 reserved11; - u32 uoc0_con[5]; - u32 uoc1_con[5]; - u32 uoc2_con[4]; - u32 uoc3_con[2]; - u32 uoc4_con[2]; - u32 pvtm_con[3]; - u32 pvtm_status[3]; - u32 io_vsel; - u32 saradc_testbit; - u32 tsadc_testbit_l; - u32 tsadc_testbit_h; - u32 os_reg[4]; - u32 reserved12; - u32 soc_con15; - u32 soc_con16; -}; - -struct rk3288_sgrf { - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 reserved1[(0x20-0x18)/4]; - u32 busdmac_con[2]; - u32 reserved2[(0x40-0x28)/4]; - u32 cpu_con[3]; - u32 reserved3[(0x50-0x4c)/4]; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_con15; - u32 soc_con16; - u32 soc_con17; - u32 soc_con18; - u32 soc_con19; - u32 soc_con20; - u32 soc_con21; - u32 reserved4[(0x100-0x90)/4]; - u32 soc_status[2]; - u32 reserved5[(0x120-0x108)/4]; - u32 fast_boot_addr; -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 1, - GPIO1D3_GPIO = 0, - GPIO1D3_LCDC0_DCLK, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 1, - GPIO1D2_GPIO = 0, - GPIO1D2_LCDC0_DEN, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 1, - GPIO1D1_GPIO = 0, - GPIO1D1_LCDC0_VSYNC, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 1, - GPIO1D0_GPIO = 0, - GPIO1D0_LCDC0_HSYNC, -}; - -/* GRF_GPIO2C_IOMUX */ -enum { - GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 1, - GPIO2C1_GPIO = 0, - GPIO2C1_I2C3CAM_SDA, - - GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 1, - GPIO2C0_GPIO = 0, - GPIO2C0_I2C3CAM_SCL, -}; - -/* GRF_GPIO3A_IOMUX */ -enum { - GPIO3A7_SHIFT = 14, - GPIO3A7_MASK = 3, - GPIO3A7_GPIO = 0, - GPIO3A7_FLASH0_DATA7, - GPIO3A7_EMMC_DATA7, - - GPIO3A6_SHIFT = 12, - GPIO3A6_MASK = 3, - GPIO3A6_GPIO = 0, - GPIO3A6_FLASH0_DATA6, - GPIO3A6_EMMC_DATA6, - - GPIO3A5_SHIFT = 10, - GPIO3A5_MASK = 3, - GPIO3A5_GPIO = 0, - GPIO3A5_FLASH0_DATA5, - GPIO3A5_EMMC_DATA5, - - GPIO3A4_SHIFT = 8, - GPIO3A4_MASK = 3, - GPIO3A4_GPIO = 0, - GPIO3A4_FLASH0_DATA4, - GPIO3A4_EMMC_DATA4, - - GPIO3A3_SHIFT = 6, - GPIO3A3_MASK = 3, - GPIO3A3_GPIO = 0, - GPIO3A3_FLASH0_DATA3, - GPIO3A3_EMMC_DATA3, - - GPIO3A2_SHIFT = 4, - GPIO3A2_MASK = 3, - GPIO3A2_GPIO = 0, - GPIO3A2_FLASH0_DATA2, - GPIO3A2_EMMC_DATA2, - - GPIO3A1_SHIFT = 2, - GPIO3A1_MASK = 3, - GPIO3A1_GPIO = 0, - GPIO3A1_FLASH0_DATA1, - GPIO3A1_EMMC_DATA1, - - GPIO3A0_SHIFT = 0, - GPIO3A0_MASK = 3, - GPIO3A0_GPIO = 0, - GPIO3A0_FLASH0_DATA0, - GPIO3A0_EMMC_DATA0, -}; - -/* GRF_GPIO3B_IOMUX */ -enum { - GPIO3B7_SHIFT = 14, - GPIO3B7_MASK = 1, - GPIO3B7_GPIO = 0, - GPIO3B7_FLASH0_CSN1, - - GPIO3B6_SHIFT = 12, - GPIO3B6_MASK = 1, - GPIO3B6_GPIO = 0, - GPIO3B6_FLASH0_CSN0, - - GPIO3B5_SHIFT = 10, - GPIO3B5_MASK = 1, - GPIO3B5_GPIO = 0, - GPIO3B5_FLASH0_WRN, - - GPIO3B4_SHIFT = 8, - GPIO3B4_MASK = 1, - GPIO3B4_GPIO = 0, - GPIO3B4_FLASH0_CLE, - - GPIO3B3_SHIFT = 6, - GPIO3B3_MASK = 1, - GPIO3B3_GPIO = 0, - GPIO3B3_FLASH0_ALE, - - GPIO3B2_SHIFT = 4, - GPIO3B2_MASK = 1, - GPIO3B2_GPIO = 0, - GPIO3B2_FLASH0_RDN, - - GPIO3B1_SHIFT = 2, - GPIO3B1_MASK = 3, - GPIO3B1_GPIO = 0, - GPIO3B1_FLASH0_WP, - GPIO3B1_EMMC_PWREN, - - GPIO3B0_SHIFT = 0, - GPIO3B0_MASK = 1, - GPIO3B0_GPIO = 0, - GPIO3B0_FLASH0_RDY, -}; - -/* GRF_GPIO3C_IOMUX */ -enum { - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3, - GPIO3C2_GPIO = 0, - GPIO3C2_FLASH0_DQS, - GPIO3C2_EMMC_CLKOUT, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3, - GPIO3C1_GPIO = 0, - GPIO3C1_FLASH0_CSN3, - GPIO3C1_EMMC_RSTNOUT, - - GPIO3C0_SHIFT = 0, - GPIO3C0_MASK = 3, - GPIO3C0_GPIO = 0, - GPIO3C0_FLASH0_CSN2, - GPIO3C0_EMMC_CMD, -}; - -/* GRF_GPIO3DL_IOMUX */ -enum { - GPIO3D3_SHIFT = 12, - GPIO3D3_MASK = 7, - GPIO3D3_GPIO = 0, - GPIO3D3_FLASH1_DATA3, - GPIO3D3_HOST_DOUT3, - GPIO3D3_MAC_RXD3, - GPIO3D3_SDIO1_DATA3, - - GPIO3D2_SHIFT = 8, - GPIO3D2_MASK = 7, - GPIO3D2_GPIO = 0, - GPIO3D2_FLASH1_DATA2, - GPIO3D2_HOST_DOUT2, - GPIO3D2_MAC_RXD2, - GPIO3D2_SDIO1_DATA2, - - GPIO3D1_SHIFT = 4, - GPIO3D1_MASK = 7, - GPIO3D1_GPIO = 0, - GPIO3DL1_FLASH1_DATA1, - GPIO3D1_HOST_DOUT1, - GPIO3D1_MAC_TXD3, - GPIO3D1_SDIO1_DATA1, - - GPIO3D0_SHIFT = 0, - GPIO3D0_MASK = 7, - GPIO3D0_GPIO = 0, - GPIO3D0_FLASH1_DATA0, - GPIO3D0_HOST_DOUT0, - GPIO3D0_MAC_TXD2, - GPIO3D0_SDIO1_DATA0, -}; - -/* GRF_GPIO3HL_IOMUX */ -enum { - GPIO3D7_SHIFT = 12, - GPIO3D7_MASK = 7, - GPIO3D7_GPIO = 0, - GPIO3D7_FLASH1_DATA7, - GPIO3D7_HOST_DOUT7, - GPIO3D7_MAC_RXD1, - GPIO3D7_SDIO1_INTN, - - GPIO3D6_SHIFT = 8, - GPIO3D6_MASK = 7, - GPIO3D6_GPIO = 0, - GPIO3D6_FLASH1_DATA6, - GPIO3D6_HOST_DOUT6, - GPIO3D6_MAC_RXD0, - GPIO3D6_SDIO1_BKPWR, - - GPIO3D5_SHIFT = 4, - GPIO3D5_MASK = 7, - GPIO3D5_GPIO = 0, - GPIO3D5_FLASH1_DATA5, - GPIO3D5_HOST_DOUT5, - GPIO3D5_MAC_TXD1, - GPIO3D5_SDIO1_WRPRT, - - GPIO3D4_SHIFT = 0, - GPIO3D4_MASK = 7, - GPIO3D4_GPIO = 0, - GPIO3D4_FLASH1_DATA4, - GPIO3D4_HOST_DOUT4, - GPIO3D4_MAC_TXD0, - GPIO3D4_SDIO1_DETECTN, -}; - -/* GRF_GPIO4AL_IOMUX */ -enum { - GPIO4A3_SHIFT = 12, - GPIO4A3_MASK = 7, - GPIO4A3_GPIO = 0, - GPIO4A3_FLASH1_ALE, - GPIO4A3_HOST_DOUT9, - GPIO4A3_MAC_CLK, - GPIO4A3_FLASH0_CSN6, - - GPIO4A2_SHIFT = 8, - GPIO4A2_MASK = 7, - GPIO4A2_GPIO = 0, - GPIO4A2_FLASH1_RDN, - GPIO4A2_HOST_DOUT8, - GPIO4A2_MAC_RXER, - GPIO4A2_FLASH0_CSN5, - - GPIO4A1_SHIFT = 4, - GPIO4A1_MASK = 7, - GPIO4A1_GPIO = 0, - GPIO4A1_FLASH1_WP, - GPIO4A1_HOST_CKOUTN, - GPIO4A1_MAC_TXDV, - GPIO4A1_FLASH0_CSN4, - - GPIO4A0_SHIFT = 0, - GPIO4A0_MASK = 3, - GPIO4A0_GPIO = 0, - GPIO4A0_FLASH1_RDY, - GPIO4A0_HOST_CKOUTP, - GPIO4A0_MAC_MDC, -}; - -/* GRF_GPIO4AH_IOMUX */ -enum { - GPIO4A7_SHIFT = 12, - GPIO4A7_MASK = 7, - GPIO4A7_GPIO = 0, - GPIO4A7_FLASH1_CSN1, - GPIO4A7_HOST_DOUT13, - GPIO4A7_MAC_CSR, - GPIO4A7_SDIO1_CLKOUT, - - GPIO4A6_SHIFT = 8, - GPIO4A6_MASK = 7, - GPIO4A6_GPIO = 0, - GPIO4A6_FLASH1_CSN0, - GPIO4A6_HOST_DOUT12, - GPIO4A6_MAC_RXCLK, - GPIO4A6_SDIO1_CMD, - - GPIO4A5_SHIFT = 4, - GPIO4A5_MASK = 3, - GPIO4A5_GPIO = 0, - GPIO4A5_FLASH1_WRN, - GPIO4A5_HOST_DOUT11, - GPIO4A5_MAC_MDIO, - - GPIO4A4_SHIFT = 0, - GPIO4A4_MASK = 7, - GPIO4A4_GPIO = 0, - GPIO4A4_FLASH1_CLE, - GPIO4A4_HOST_DOUT10, - GPIO4A4_MAC_TXEN, - GPIO4A4_FLASH0_CSN7, -}; - -/* GRF_GPIO4BL_IOMUX */ -enum { - GPIO4B1_SHIFT = 4, - GPIO4B1_MASK = 7, - GPIO4B1_GPIO = 0, - GPIO4B1_FLASH1_CSN2, - GPIO4B1_HOST_DOUT15, - GPIO4B1_MAC_TXCLK, - GPIO4B1_SDIO1_PWREN, - - GPIO4B0_SHIFT = 0, - GPIO4B0_MASK = 7, - GPIO4B0_GPIO = 0, - GPIO4B0_FLASH1_DQS, - GPIO4B0_HOST_DOUT14, - GPIO4B0_MAC_COL, - GPIO4B0_FLASH1_CSN3, -}; - -/* GRF_GPIO4C_IOMUX */ -enum { - GPIO4C7_SHIFT = 14, - GPIO4C7_MASK = 1, - GPIO4C7_GPIO = 0, - GPIO4C7_SDIO0_DATA3, - - GPIO4C6_SHIFT = 12, - GPIO4C6_MASK = 1, - GPIO4C6_GPIO = 0, - GPIO4C6_SDIO0_DATA2, - - GPIO4C5_SHIFT = 10, - GPIO4C5_MASK = 1, - GPIO4C5_GPIO = 0, - GPIO4C5_SDIO0_DATA1, - - GPIO4C4_SHIFT = 8, - GPIO4C4_MASK = 1, - GPIO4C4_GPIO = 0, - GPIO4C4_SDIO0_DATA0, - - GPIO4C3_SHIFT = 6, - GPIO4C3_MASK = 1, - GPIO4C3_GPIO = 0, - GPIO4C3_UART0BT_RTSN, - - GPIO4C2_SHIFT = 4, - GPIO4C2_MASK = 1, - GPIO4C2_GPIO = 0, - GPIO4C2_UART0BT_CTSN, - - GPIO4C1_SHIFT = 2, - GPIO4C1_MASK = 1, - GPIO4C1_GPIO = 0, - GPIO4C1_UART0BT_SOUT, - - GPIO4C0_SHIFT = 0, - GPIO4C0_MASK = 1, - GPIO4C0_GPIO = 0, - GPIO4C0_UART0BT_SIN, -}; - -/* GRF_GPIO5B_IOMUX */ -enum { - GPIO5B7_SHIFT = 14, - GPIO5B7_MASK = 3, - GPIO5B7_GPIO = 0, - GPIO5B7_SPI0_RXD, - GPIO5B7_TS0_DATA7, - GPIO5B7_UART4EXP_SIN, - - GPIO5B6_SHIFT = 12, - GPIO5B6_MASK = 3, - GPIO5B6_GPIO = 0, - GPIO5B6_SPI0_TXD, - GPIO5B6_TS0_DATA6, - GPIO5B6_UART4EXP_SOUT, - - GPIO5B5_SHIFT = 10, - GPIO5B5_MASK = 3, - GPIO5B5_GPIO = 0, - GPIO5B5_SPI0_CSN0, - GPIO5B5_TS0_DATA5, - GPIO5B5_UART4EXP_RTSN, - - GPIO5B4_SHIFT = 8, - GPIO5B4_MASK = 3, - GPIO5B4_GPIO = 0, - GPIO5B4_SPI0_CLK, - GPIO5B4_TS0_DATA4, - GPIO5B4_UART4EXP_CTSN, - - GPIO5B3_SHIFT = 6, - GPIO5B3_MASK = 3, - GPIO5B3_GPIO = 0, - GPIO5B3_UART1BB_RTSN, - GPIO5B3_TS0_DATA3, - - GPIO5B2_SHIFT = 4, - GPIO5B2_MASK = 3, - GPIO5B2_GPIO = 0, - GPIO5B2_UART1BB_CTSN, - GPIO5B2_TS0_DATA2, - - GPIO5B1_SHIFT = 2, - GPIO5B1_MASK = 3, - GPIO5B1_GPIO = 0, - GPIO5B1_UART1BB_SOUT, - GPIO5B1_TS0_DATA1, - - GPIO5B0_SHIFT = 0, - GPIO5B0_MASK = 3, - GPIO5B0_GPIO = 0, - GPIO5B0_UART1BB_SIN, - GPIO5B0_TS0_DATA0, -}; - -/* GRF_GPIO5C_IOMUX */ -enum { - GPIO5C3_SHIFT = 6, - GPIO5C3_MASK = 1, - GPIO5C3_GPIO = 0, - GPIO5C3_TS0_ERR, - - GPIO5C2_SHIFT = 4, - GPIO5C2_MASK = 1, - GPIO5C2_GPIO = 0, - GPIO5C2_TS0_CLK, - - GPIO5C1_SHIFT = 2, - GPIO5C1_MASK = 1, - GPIO5C1_GPIO = 0, - GPIO5C1_TS0_VALID, - - GPIO5C0_SHIFT = 0, - GPIO5C0_MASK = 3, - GPIO5C0_GPIO = 0, - GPIO5C0_SPI0_CSN1, - GPIO5C0_TS0_SYNC, -}; - -/* GRF_GPIO6A_IOMUX */ -enum { - GPIO6A7_SHIFT = 0xe, - GPIO6A7_MASK = 1, - GPIO6A7_GPIO = 0, - GPIO6A7_I2S_SDO3, - - GPIO6A6_SHIFT = 0xc, - GPIO6A6_MASK = 1, - GPIO6A6_GPIO = 0, - GPIO6A6_I2S_SDO2, - - GPIO6A5_SHIFT = 0xa, - GPIO6A5_MASK = 1, - GPIO6A5_GPIO = 0, - GPIO6A5_I2S_SDO1, - - GPIO6A4_SHIFT = 8, - GPIO6A4_MASK = 1, - GPIO6A4_GPIO = 0, - GPIO6A4_I2S_SDO0, - - GPIO6A3_SHIFT = 6, - GPIO6A3_MASK = 1, - GPIO6A3_GPIO = 0, - GPIO6A3_I2S_SDI, - - GPIO6A2_SHIFT = 4, - GPIO6A2_MASK = 1, - GPIO6A2_GPIO = 0, - GPIO6A2_I2S_LRCKTX, - - GPIO6A1_SHIFT = 2, - GPIO6A1_MASK = 1, - GPIO6A1_GPIO = 0, - GPIO6A1_I2S_LRCKRX, - - GPIO6A0_SHIFT = 0, - GPIO6A0_MASK = 1, - GPIO6A0_GPIO = 0, - GPIO6A0_I2S_SCLK, -}; - -/* GRF_GPIO6B_IOMUX */ -enum { - GPIO6B3_SHIFT = 6, - GPIO6B3_MASK = 1, - GPIO6B3_GPIO = 0, - GPIO6B3_SPDIF_TX, - - GPIO6B2_SHIFT = 4, - GPIO6B2_MASK = 1, - GPIO6B2_GPIO = 0, - GPIO6B2_I2C1AUDIO_SCL, - - GPIO6B1_SHIFT = 2, - GPIO6B1_MASK = 1, - GPIO6B1_GPIO = 0, - GPIO6B1_I2C1AUDIO_SDA, - - GPIO6B0_SHIFT = 0, - GPIO6B0_MASK = 1, - GPIO6B0_GPIO = 0, - GPIO6B0_I2S_CLK, -}; - -/* GRF_GPIO6C_IOMUX */ -enum { - GPIO6C6_SHIFT = 12, - GPIO6C6_MASK = 1, - GPIO6C6_GPIO = 0, - GPIO6C6_SDMMC0_DECTN, - - GPIO6C5_SHIFT = 10, - GPIO6C5_MASK = 1, - GPIO6C5_GPIO = 0, - GPIO6C5_SDMMC0_CMD, - - GPIO6C4_SHIFT = 8, - GPIO6C4_MASK = 3, - GPIO6C4_GPIO = 0, - GPIO6C4_SDMMC0_CLKOUT, - GPIO6C4_JTAG_TDO, - - GPIO6C3_SHIFT = 6, - GPIO6C3_MASK = 3, - GPIO6C3_GPIO = 0, - GPIO6C3_SDMMC0_DATA3, - GPIO6C3_JTAG_TCK, - - GPIO6C2_SHIFT = 4, - GPIO6C2_MASK = 3, - GPIO6C2_GPIO = 0, - GPIO6C2_SDMMC0_DATA2, - GPIO6C2_JTAG_TDI, - - GPIO6C1_SHIFT = 2, - GPIO6C1_MASK = 3, - GPIO6C1_GPIO = 0, - GPIO6C1_SDMMC0_DATA1, - GPIO6C1_JTAG_TRSTN, - - GPIO6C0_SHIFT = 0, - GPIO6C0_MASK = 3, - GPIO6C0_GPIO = 0, - GPIO6C0_SDMMC0_DATA0, - GPIO6C0_JTAG_TMS, -}; - -/* GRF_GPIO7A_IOMUX */ -enum { - GPIO7A7_SHIFT = 14, - GPIO7A7_MASK = 3, - GPIO7A7_GPIO = 0, - GPIO7A7_UART3GPS_SIN, - GPIO7A7_GPS_MAG, - GPIO7A7_HSADCT1_DATA0, - - GPIO7A1_SHIFT = 2, - GPIO7A1_MASK = 1, - GPIO7A1_GPIO = 0, - GPIO7A1_PWM_1, - - GPIO7A0_SHIFT = 0, - GPIO7A0_MASK = 3, - GPIO7A0_GPIO = 0, - GPIO7A0_PWM_0, - GPIO7A0_VOP0_PWM, - GPIO7A0_VOP1_PWM, -}; - -/* GRF_GPIO7B_IOMUX */ -enum { - GPIO7B7_SHIFT = 14, - GPIO7B7_MASK = 3, - GPIO7B7_GPIO = 0, - GPIO7B7_ISP_SHUTTERTRIG, - GPIO7B7_SPI1_TXD, - - GPIO7B6_SHIFT = 12, - GPIO7B6_MASK = 3, - GPIO7B6_GPIO = 0, - GPIO7B6_ISP_PRELIGHTTRIG, - GPIO7B6_SPI1_RXD, - - GPIO7B5_SHIFT = 10, - GPIO7B5_MASK = 3, - GPIO7B5_GPIO = 0, - GPIO7B5_ISP_FLASHTRIGOUT, - GPIO7B5_SPI1_CSN0, - - GPIO7B4_SHIFT = 8, - GPIO7B4_MASK = 3, - GPIO7B4_GPIO = 0, - GPIO7B4_ISP_SHUTTEREN, - GPIO7B4_SPI1_CLK, - - GPIO7B3_SHIFT = 6, - GPIO7B3_MASK = 3, - GPIO7B3_GPIO = 0, - GPIO7B3_USB_DRVVBUS1, - GPIO7B3_EDP_HOTPLUG, - - GPIO7B2_SHIFT = 4, - GPIO7B2_MASK = 3, - GPIO7B2_GPIO = 0, - GPIO7B2_UART3GPS_RTSN, - GPIO7B2_USB_DRVVBUS0, - - GPIO7B1_SHIFT = 2, - GPIO7B1_MASK = 3, - GPIO7B1_GPIO = 0, - GPIO7B1_UART3GPS_CTSN, - GPIO7B1_GPS_RFCLK, - GPIO7B1_GPST1_CLK, - - GPIO7B0_SHIFT = 0, - GPIO7B0_MASK = 3, - GPIO7B0_GPIO = 0, - GPIO7B0_UART3GPS_SOUT, - GPIO7B0_GPS_SIG, - GPIO7B0_HSADCT1_DATA1, -}; - -/* GRF_GPIO7CL_IOMUX */ -enum { - GPIO7C3_SHIFT = 12, - GPIO7C3_MASK = 3, - GPIO7C3_GPIO = 0, - GPIO7C3_I2C5HDMI_SDA, - GPIO7C3_EDPHDMII2C_SDA, - - GPIO7C2_SHIFT = 8, - GPIO7C2_MASK = 1, - GPIO7C2_GPIO = 0, - GPIO7C2_I2C4TP_SCL, - - GPIO7C1_SHIFT = 4, - GPIO7C1_MASK = 1, - GPIO7C1_GPIO = 0, - GPIO7C1_I2C4TP_SDA, - - GPIO7C0_SHIFT = 0, - GPIO7C0_MASK = 3, - GPIO7C0_GPIO = 0, - GPIO7C0_ISP_FLASHTRIGIN, - GPIO7C0_EDPHDMI_CECINOUTT1, -}; - -/* GRF_GPIO7CH_IOMUX */ -enum { - GPIO7C7_SHIFT = 12, - GPIO7C7_MASK = 7, - GPIO7C7_GPIO = 0, - GPIO7C7_UART2DBG_SOUT, - GPIO7C7_UART2DBG_SIROUT, - GPIO7C7_PWM_3, - GPIO7C7_EDPHDMI_CECINOUT, - - GPIO7C6_SHIFT = 8, - GPIO7C6_MASK = 3, - GPIO7C6_GPIO = 0, - GPIO7C6_UART2DBG_SIN, - GPIO7C6_UART2DBG_SIRIN, - GPIO7C6_PWM_2, - - GPIO7C4_SHIFT = 0, - GPIO7C4_MASK = 3, - GPIO7C4_GPIO = 0, - GPIO7C4_I2C5HDMI_SCL, - GPIO7C4_EDPHDMII2C_SCL, -}; - -/* GRF_GPIO8A_IOMUX */ -enum { - GPIO8A7_SHIFT = 14, - GPIO8A7_MASK = 3, - GPIO8A7_GPIO = 0, - GPIO8A7_SPI2_CSN0, - GPIO8A7_SC_DETECT, - GPIO8A7_RESERVE, - - GPIO8A6_SHIFT = 12, - GPIO8A6_MASK = 3, - GPIO8A6_GPIO = 0, - GPIO8A6_SPI2_CLK, - GPIO8A6_SC_IO, - GPIO8A6_RESERVE, - - GPIO8A5_SHIFT = 10, - GPIO8A5_MASK = 3, - GPIO8A5_GPIO = 0, - GPIO8A5_I2C2SENSOR_SCL, - GPIO8A5_SC_CLK, - - GPIO8A4_SHIFT = 8, - GPIO8A4_MASK = 3, - GPIO8A4_GPIO = 0, - GPIO8A4_I2C2SENSOR_SDA, - GPIO8A4_SC_RST, - - GPIO8A3_SHIFT = 6, - GPIO8A3_MASK = 3, - GPIO8A3_GPIO = 0, - GPIO8A3_SPI2_CSN1, - GPIO8A3_SC_IOT1, - - GPIO8A2_SHIFT = 4, - GPIO8A2_MASK = 1, - GPIO8A2_GPIO = 0, - GPIO8A2_SC_DETECTT1, - - GPIO8A1_SHIFT = 2, - GPIO8A1_MASK = 3, - GPIO8A1_GPIO = 0, - GPIO8A1_PS2_DATA, - GPIO8A1_SC_VCC33V, - - GPIO8A0_SHIFT = 0, - GPIO8A0_MASK = 3, - GPIO8A0_GPIO = 0, - GPIO8A0_PS2_CLK, - GPIO8A0_SC_VCC18V, -}; - -/* GRF_GPIO8B_IOMUX */ -enum { - GPIO8B1_SHIFT = 2, - GPIO8B1_MASK = 3, - GPIO8B1_GPIO = 0, - GPIO8B1_SPI2_TXD, - GPIO8B1_SC_CLK, - - GPIO8B0_SHIFT = 0, - GPIO8B0_MASK = 3, - GPIO8B0_GPIO = 0, - GPIO8B0_SPI2_RXD, - GPIO8B0_SC_RST, -}; - -/* GRF_SOC_CON0 */ -enum { - PAUSE_MMC_PERI_SHIFT = 0xf, - PAUSE_MMC_PERI_MASK = 1, - - PAUSE_EMEM_PERI_SHIFT = 0xe, - PAUSE_EMEM_PERI_MASK = 1, - - PAUSE_USB_PERI_SHIFT = 0xd, - PAUSE_USB_PERI_MASK = 1, - - GRF_FORCE_JTAG_SHIFT = 0xc, - GRF_FORCE_JTAG_MASK = 1, - - GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb, - GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1, - - GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa, - GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1, - - DDR1_16BIT_EN_SHIFT = 9, - DDR1_16BIT_EN_MASK = 1, - - DDR0_16BIT_EN_SHIFT = 8, - DDR0_16BIT_EN_MASK = 1, - - VCODEC_SHIFT = 7, - VCODEC_MASK = 1, - VCODEC_SELECT_VEPU_ACLK = 0, - VCODEC_SELECT_VDPU_ACLK, - - UPCTL1_C_ACTIVE_IN_SHIFT = 6, - UPCTL1_C_ACTIVE_IN_MASK = 1, - UPCTL1_C_ACTIVE_IN_MAY = 0, - UPCTL1_C_ACTIVE_IN_WILL, - - UPCTL0_C_ACTIVE_IN_SHIFT = 5, - UPCTL0_C_ACTIVE_IN_MASK = 1, - UPCTL0_C_ACTIVE_IN_MAY = 0, - UPCTL0_C_ACTIVE_IN_WILL, - - MSCH1_MAINDDR3_SHIFT = 4, - MSCH1_MAINDDR3_MASK = 1, - MSCH1_MAINDDR3_DDR3 = 1, - - MSCH0_MAINDDR3_SHIFT = 3, - MSCH0_MAINDDR3_MASK = 1, - MSCH0_MAINDDR3_DDR3 = 1, - - MSCH1_MAINPARTIALPOP_SHIFT = 2, - MSCH1_MAINPARTIALPOP_MASK = 1, - - MSCH0_MAINPARTIALPOP_SHIFT = 1, - MSCH0_MAINPARTIALPOP_MASK = 1, -}; - -/* GRF_SOC_CON1 */ -enum { - RK3288_RMII_MODE_SHIFT = 14, - RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT), - RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT), - - RK3288_GMAC_CLK_SEL_SHIFT = 12, - RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT), - RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT), - RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT), - RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT), - - RK3288_RMII_CLK_SEL_SHIFT = 11, - RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT), - RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), - RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT), - - GMAC_SPEED_SHIFT = 0xa, - GMAC_SPEED_MASK = 1, - GMAC_SPEED_10M = 0, - GMAC_SPEED_100M, - - GMAC_FLOWCTRL_SHIFT = 0x9, - GMAC_FLOWCTRL_MASK = 1, - - RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, - RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), - RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), - RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), - - HOST_REMAP_SHIFT = 0x5, - HOST_REMAP_MASK = 1 -}; - -/* GRF_SOC_CON2 */ -enum { - UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd, - UPCTL1_LPDDR3_ODT_EN_MASK = 1, - UPCTL1_LPDDR3_ODT_EN_ODT = 1, - - UPCTL1_BST_DIABLE_SHIFT = 0xc, - UPCTL1_BST_DIABLE_MASK = 1, - UPCTL1_BST_DIABLE_DISABLE = 1, - - LPDDR3_EN1_SHIFT = 0xb, - LPDDR3_EN1_MASK = 1, - LPDDR3_EN1_LPDDR3 = 1, - - UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa, - UPCTL0_LPDDR3_ODT_EN_MASK = 1, - UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1, - - UPCTL0_BST_DIABLE_SHIFT = 9, - UPCTL0_BST_DIABLE_MASK = 1, - UPCTL0_BST_DIABLE_DISABLE = 1, - - LPDDR3_EN0_SHIFT = 8, - LPDDR3_EN0_MASK = 1, - LPDDR3_EN0_LPDDR3 = 1, - - GRF_POC_FLASH0_CTRL_SHIFT = 7, - GRF_POC_FLASH0_CTRL_MASK = 1, - GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0, - GRF_POC_FLASH0_CTRL_GRF_IO_VSEL, - - SIMCARD_MUX_SHIFT = 6, - SIMCARD_MUX_MASK = 1, - SIMCARD_MUX_USE_A = 1, - SIMCARD_MUX_USE_B = 0, - - GRF_SPDIF_2CH_EN_SHIFT = 1, - GRF_SPDIF_2CH_EN_MASK = 1, - GRF_SPDIF_2CH_EN_8CH = 0, - GRF_SPDIF_2CH_EN_2CH, - - PWM_SHIFT = 0, - PWM_MASK = 1, - PWM_RK = 1, - PWM_PWM = 0, -}; - -/* GRF_SOC_CON3 */ -enum { - RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, - RK3288_RXCLK_DLY_ENA_GMAC_MASK = - (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), - RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0, - RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), - - RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, - RK3288_TXCLK_DLY_ENA_GMAC_MASK = - (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), - RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, - RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), - - RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, - RK3288_CLK_RX_DL_CFG_GMAC_MASK = - (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT), - - RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, - RK3288_CLK_TX_DL_CFG_GMAC_MASK = - (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT), -}; - -/* GRF_SOC_CON6 */ -enum GRF_SOC_CON6 { - RK3288_HDMI_EDP_SEL_SHIFT = 0xf, - RK3288_HDMI_EDP_SEL_MASK = - 1 << RK3288_HDMI_EDP_SEL_SHIFT, - RK3288_HDMI_EDP_SEL_EDP = 0, - RK3288_HDMI_EDP_SEL_HDMI, - - RK3288_DSI0_DPICOLORM_SHIFT = 0x8, - RK3288_DSI0_DPICOLORM_MASK = - 1 << RK3288_DSI0_DPICOLORM_SHIFT, - - RK3288_DSI0_DPISHUTDN_SHIFT = 0x7, - RK3288_DSI0_DPISHUTDN_MASK = - 1 << RK3288_DSI0_DPISHUTDN_SHIFT, - - RK3288_DSI0_LCDC_SEL_SHIFT = 0x6, - RK3288_DSI0_LCDC_SEL_MASK = - 1 << RK3288_DSI0_LCDC_SEL_SHIFT, - RK3288_DSI0_LCDC_SEL_BIG = 0, - RK3288_DSI0_LCDC_SEL_LIT = 1, - - RK3288_EDP_LCDC_SEL_SHIFT = 0x5, - RK3288_EDP_LCDC_SEL_MASK = - 1 << RK3288_EDP_LCDC_SEL_SHIFT, - RK3288_EDP_LCDC_SEL_BIG = 0, - RK3288_EDP_LCDC_SEL_LIT = 1, - - RK3288_HDMI_LCDC_SEL_SHIFT = 0x4, - RK3288_HDMI_LCDC_SEL_MASK = - 1 << RK3288_HDMI_LCDC_SEL_SHIFT, - RK3288_HDMI_LCDC_SEL_BIG = 0, - RK3288_HDMI_LCDC_SEL_LIT = 1, - - RK3288_LVDS_LCDC_SEL_SHIFT = 0x3, - RK3288_LVDS_LCDC_SEL_MASK = - 1 << RK3288_LVDS_LCDC_SEL_SHIFT, - RK3288_LVDS_LCDC_SEL_BIG = 0, - RK3288_LVDS_LCDC_SEL_LIT = 1, -}; - -/* RK3288_SOC_CON8 */ -enum GRF_SOC_CON8 { - RK3288_DPHY_TX0_RXMODE_SHIFT = 4, - RK3288_DPHY_TX0_RXMODE_MASK = - 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT, - RK3288_DPHY_TX0_RXMODE_EN = 0xf, - RK3288_DPHY_TX0_RXMODE_DIS = 0, - - RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8, - RK3288_DPHY_TX0_TXSTOPMODE_MASK = - 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT, - RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf, - RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0, - - RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0, - RK3288_DPHY_TX0_TURNREQUEST_MASK = - 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT, - RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf, - RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, -}; - -/* GRF_IO_VSEL */ -enum { - GPIO1830_V18SEL_SHIFT = 9, - GPIO1830_V18SEL_MASK = 1, - GPIO1830_V18SEL_3_3V = 0, - GPIO1830_V18SEL_1_8V, - - GPIO30_V18SEL_SHIFT = 8, - GPIO30_V18SEL_MASK = 1, - GPIO30_V18SEL_3_3V = 0, - GPIO30_V18SEL_1_8V, - - SDCARD_V18SEL_SHIFT = 7, - SDCARD_V18SEL_MASK = 1, - SDCARD_V18SEL_3_3V = 0, - SDCARD_V18SEL_1_8V, - - AUDIO_V18SEL_SHIFT = 6, - AUDIO_V18SEL_MASK = 1, - AUDIO_V18SEL_3_3V = 0, - AUDIO_V18SEL_1_8V, - - BB_V18SEL_SHIFT = 5, - BB_V18SEL_MASK = 1, - BB_V18SEL_3_3V = 0, - BB_V18SEL_1_8V, - - WIFI_V18SEL_SHIFT = 4, - WIFI_V18SEL_MASK = 1, - WIFI_V18SEL_3_3V = 0, - WIFI_V18SEL_1_8V, - - FLASH1_V18SEL_SHIFT = 3, - FLASH1_V18SEL_MASK = 1, - FLASH1_V18SEL_3_3V = 0, - FLASH1_V18SEL_1_8V, - - FLASH0_V18SEL_SHIFT = 2, - FLASH0_V18SEL_MASK = 1, - FLASH0_V18SEL_3_3V = 0, - FLASH0_V18SEL_1_8V, - - DVP_V18SEL_SHIFT = 1, - DVP_V18SEL_MASK = 1, - DVP_V18SEL_3_3V = 0, - DVP_V18SEL_1_8V, - - LCDC_V18SEL_SHIFT = 0, - LCDC_V18SEL_MASK = 1, - LCDC_V18SEL_3_3V = 0, - LCDC_V18SEL_1_8V, -}; - -/* GPIO Bias settings */ -enum GPIO_BIAS { - GPIO_BIAS_2MA = 0, - GPIO_BIAS_4MA, - GPIO_BIAS_8MA, - GPIO_BIAS_12MA, -}; - -#define GPIO_BIAS_MASK 0x3 -#define GPIO_BIAS_SHIFT(x) ((x) * 2) - -#define GPIO_PULL_MASK 0x3 -#define GPIO_PULL_SHIFT(x) ((x) * 2) - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h deleted file mode 100644 index d8a4680..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__ -#define __SOC_ROCKCHIP_RK3328_GRF_H__ - -struct rk3328_grf_regs { - u32 gpio0a_iomux; - u32 gpio0b_iomux; - u32 gpio0c_iomux; - u32 gpio0d_iomux; - u32 gpio1a_iomux; - u32 gpio1b_iomux; - u32 gpio1c_iomux; - u32 gpio1d_iomux; - u32 gpio2a_iomux; - u32 gpio2bl_iomux; - u32 gpio2bh_iomux; - u32 gpio2cl_iomux; - u32 gpio2ch_iomux; - u32 gpio2d_iomux; - u32 gpio3al_iomux; - u32 gpio3ah_iomux; - u32 gpio3bl_iomux; - u32 gpio3bh_iomux; - u32 gpio3c_iomux; - u32 gpio3d_iomux; - u32 com_iomux; - u32 reserved1[(0x100 - 0x54) / 4]; - - u32 gpio0a_p; - u32 gpio0b_p; - u32 gpio0c_p; - u32 gpio0d_p; - u32 gpio1a_p; - u32 gpio1b_p; - u32 gpio1c_p; - u32 gpio1d_p; - u32 gpio2a_p; - u32 gpio2b_p; - u32 gpio2c_p; - u32 gpio2d_p; - u32 gpio3a_p; - u32 gpio3b_p; - u32 gpio3c_p; - u32 gpio3d_p; - u32 reserved2[(0x200 - 0x140) / 4]; - u32 gpio0a_e; - u32 gpio0b_e; - u32 gpio0c_e; - u32 gpio0d_e; - u32 gpio1a_e; - u32 gpio1b_e; - u32 gpio1c_e; - u32 gpio1d_e; - u32 gpio2a_e; - u32 gpio2b_e; - u32 gpio2c_e; - u32 gpio2d_e; - u32 gpio3a_e; - u32 gpio3b_e; - u32 gpio3c_e; - u32 gpio3d_e; - u32 reserved3[(0x300 - 0x240) / 4]; - u32 gpio0l_sr; - u32 gpio0h_sr; - u32 gpio1l_sr; - u32 gpio1h_sr; - u32 gpio2l_sr; - u32 gpio2h_sr; - u32 gpio3l_sr; - u32 gpio3h_sr; - u32 reserved4[(0x380 - 0x320) / 4]; - u32 gpio0l_smt; - u32 gpio0h_smt; - u32 gpio1l_smt; - u32 gpio1h_smt; - u32 gpio2l_smt; - u32 gpio2h_smt; - u32 gpio3l_smt; - u32 gpio3h_smt; - u32 reserved5[(0x400 - 0x3a0) / 4]; - u32 soc_con[11]; - u32 reserved6[(0x480 - 0x42c) / 4]; - u32 soc_status[5]; - u32 reserved7[(0x4c0 - 0x494) / 4]; - u32 otg3_con[2]; - u32 reserved8[(0x500 - 0x4c8) / 4]; - u32 cpu_con[2]; - u32 reserved9[(0x520 - 0x508) / 4]; - u32 cpu_status[2]; - u32 reserved10[(0x5c8 - 0x528) / 4]; - u32 os_reg[8]; - u32 reserved11[(0x680 - 0x5e8) / 4]; - u32 sig_detect_con; - u32 reserved12[3]; - u32 sig_detect_status; - u32 reserved13[3]; - u32 sig_detect_status_clr; - u32 reserved14[3]; - - u32 sdmmc_det_counter; - u32 reserved15[(0x700 - 0x6b4) / 4]; - u32 host0_con[3]; - u32 reserved16[(0x880 - 0x70c) / 4]; - u32 otg_con0; - u32 reserved17[3]; - u32 host0_status; - u32 reserved18[(0x900 - 0x894) / 4]; - u32 mac_con[3]; - u32 reserved19[(0xb00 - 0x90c) / 4]; - u32 macphy_con[4]; - u32 macphy_status; -}; -check_member(rk3328_grf_regs, macphy_status, 0xb10); - -struct rk3328_sgrf_regs { - u32 soc_con[6]; - u32 reserved0[(0x100 - 0x18) / 4]; - u32 dmac_con[6]; - u32 reserved1[(0x180 - 0x118) / 4]; - u32 fast_boot_addr; - u32 reserved2[(0x200 - 0x184) / 4]; - u32 chip_fuse_con; - u32 reserved3[(0x280 - 0x204) / 4]; - u32 hdcp_key_reg[8]; - u32 hdcp_key_access_mask; -}; -check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); - -#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h deleted file mode 100644 index b70b08f..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ -#ifndef _ASM_ARCH_GRF_RK3368_H -#define _ASM_ARCH_GRF_RK3368_H - -#include <common.h> - -struct rk3368_grf { - u32 gpio1a_iomux; - u32 gpio1b_iomux; - u32 gpio1c_iomux; - u32 gpio1d_iomux; - u32 gpio2a_iomux; - u32 gpio2b_iomux; - u32 gpio2c_iomux; - u32 gpio2d_iomux; - u32 gpio3a_iomux; - u32 gpio3b_iomux; - u32 gpio3c_iomux; - u32 gpio3d_iomux; - u32 reserved[0x34]; - u32 gpio1a_pull; - u32 gpio1b_pull; - u32 gpio1c_pull; - u32 gpio1d_pull; - u32 gpio2a_pull; - u32 gpio2b_pull; - u32 gpio2c_pull; - u32 gpio2d_pull; - u32 gpio3a_pull; - u32 gpio3b_pull; - u32 gpio3c_pull; - u32 gpio3d_pull; - u32 reserved1[0x34]; - u32 gpio1a_drv; - u32 gpio1b_drv; - u32 gpio1c_drv; - u32 gpio1d_drv; - u32 gpio2a_drv; - u32 gpio2b_drv; - u32 gpio2c_drv; - u32 gpio2d_drv; - u32 gpio3a_drv; - u32 gpio3b_drv; - u32 gpio3c_drv; - u32 gpio3d_drv; - u32 reserved2[0x34]; - u32 gpio1l_sr; - u32 gpio1h_sr; - u32 gpio2l_sr; - u32 gpio2h_sr; - u32 gpio3l_sr; - u32 gpio3h_sr; - u32 reserved3[0x1a]; - u32 gpio_smt; - u32 reserved4[0x1f]; - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_con15; - u32 soc_con16; - u32 soc_con17; - u32 reserved5[0x6e]; - u32 ddrc0_con0; -}; -check_member(rk3368_grf, soc_con17, 0x444); -check_member(rk3368_grf, ddrc0_con0, 0x600); - -struct rk3368_pmu_grf { - u32 gpio0a_iomux; - u32 gpio0b_iomux; - u32 gpio0c_iomux; - u32 gpio0d_iomux; - u32 gpio0a_pull; - u32 gpio0b_pull; - u32 gpio0c_pull; - u32 gpio0d_pull; - u32 gpio0a_drv; - u32 gpio0b_drv; - u32 gpio0c_drv; - u32 gpio0d_drv; - u32 gpio0l_sr; - u32 gpio0h_sr; - u32 reserved[0x72]; - u32 os_reg[4]; -}; -check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); -check_member(rk3368_pmu_grf, os_reg[0], 0x200); - -/*GRF_SOC_CON11/12/13*/ -enum { - MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0, - MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), -}; - -/*GRF_SOC_CON12*/ -enum { - MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0, - MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), -}; - -/*GRF_SOC_CON13*/ -enum { - MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0, - MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), -}; - -/*GRF_SOC_CON14*/ -enum { - MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12, - MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12), - MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8, - MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8), - MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4, - MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4), - MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, - MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h deleted file mode 100644 index dd89cd2..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ /dev/null @@ -1,672 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ -#define __SOC_ROCKCHIP_RK3399_GRF_H__ - -struct rk3399_grf_regs { - u32 reserved[0x800]; - u32 usb3_perf_con0; - u32 usb3_perf_con1; - u32 usb3_perf_con2; - u32 usb3_perf_rd_max_latency_num; - u32 usb3_perf_rd_latency_samp_num; - u32 usb3_perf_rd_latency_acc_num; - u32 usb3_perf_rd_axi_total_byte; - u32 usb3_perf_wr_axi_total_byte; - u32 usb3_perf_working_cnt; - u32 reserved1[0x103]; - u32 usb3otg0_con0; - u32 usb3otg0_con1; - u32 reserved2[2]; - u32 usb3otg1_con0; - u32 usb3otg1_con1; - u32 reserved3[2]; - u32 usb3otg0_status_lat0; - u32 usb3otg0_status_lat1; - u32 usb3otg0_status_cb; - u32 reserved4; - u32 usb3otg1_status_lat0; - u32 usb3otg1_status_lat1; - u32 usb3ogt1_status_cb; - u32 reserved5[0x6e5]; - u32 pcie_perf_con0; - u32 pcie_perf_con1; - u32 pcie_perf_con2; - u32 pcie_perf_rd_max_latency_num; - u32 pcie_perf_rd_latency_samp_num; - u32 pcie_perf_rd_laterncy_acc_num; - u32 pcie_perf_rd_axi_total_byte; - u32 pcie_perf_wr_axi_total_byte; - u32 pcie_perf_working_cnt; - u32 reserved6[0x37]; - u32 usb20_host0_con0; - u32 usb20_host0_con1; - u32 reserved7[2]; - u32 usb20_host1_con0; - u32 usb20_host1_con1; - u32 reserved8[2]; - u32 hsic_con0; - u32 hsic_con1; - u32 reserved9[6]; - u32 grf_usbhost0_status; - u32 grf_usbhost1_Status; - u32 grf_hsic_status; - u32 reserved10[0xc9]; - u32 hsicphy_con0; - u32 reserved11[3]; - u32 usbphy0_ctrl[26]; - u32 reserved12[6]; - u32 usbphy1[26]; - u32 reserved13[0x72f]; - u32 soc_con9; - u32 reserved14[0x0a]; - u32 soc_con20; - u32 soc_con21; - u32 soc_con22; - u32 soc_con23; - u32 soc_con24; - u32 soc_con25; - u32 soc_con26; - u32 reserved15[0xf65]; - u32 cpu_con[4]; - u32 reserved16[0x1c]; - u32 cpu_status[6]; - u32 reserved17[0x1a]; - u32 a53_perf_con[4]; - u32 a53_perf_rd_mon_st; - u32 a53_perf_rd_mon_end; - u32 a53_perf_wr_mon_st; - u32 a53_perf_wr_mon_end; - u32 a53_perf_rd_max_latency_num; - u32 a53_perf_rd_latency_samp_num; - u32 a53_perf_rd_laterncy_acc_num; - u32 a53_perf_rd_axi_total_byte; - u32 a53_perf_wr_axi_total_byte; - u32 a53_perf_working_cnt; - u32 a53_perf_int_status; - u32 reserved18[0x31]; - u32 a72_perf_con[4]; - u32 a72_perf_rd_mon_st; - u32 a72_perf_rd_mon_end; - u32 a72_perf_wr_mon_st; - u32 a72_perf_wr_mon_end; - u32 a72_perf_rd_max_latency_num; - u32 a72_perf_rd_latency_samp_num; - u32 a72_perf_rd_laterncy_acc_num; - u32 a72_perf_rd_axi_total_byte; - u32 a72_perf_wr_axi_total_byte; - u32 a72_perf_working_cnt; - u32 a72_perf_int_status; - u32 reserved19[0x7f6]; - u32 soc_con5; - u32 soc_con6; - u32 reserved20[0x779]; - u32 gpio2a_iomux; - union { - u32 iomux_spi2; - u32 gpio2b_iomux; - }; - union { - u32 gpio2c_iomux; - u32 iomux_spi5; - }; - u32 gpio2d_iomux; - union { - u32 gpio3a_iomux; - u32 iomux_spi0; - }; - u32 gpio3b_iomux; - u32 gpio3c_iomux; - union { - u32 iomux_i2s0; - u32 gpio3d_iomux; - }; - union { - u32 iomux_i2sclk; - u32 gpio4a_iomux; - }; - union { - u32 iomux_sdmmc; - u32 iomux_uart2a; - u32 gpio4b_iomux; - }; - union { - u32 iomux_pwm_0; - u32 iomux_pwm_1; - u32 iomux_uart2b; - u32 iomux_uart2c; - u32 iomux_edp_hotplug; - u32 gpio4c_iomux; - }; - u32 gpio4d_iomux; - u32 reserved21[4]; - u32 gpio2_p[4]; - u32 gpio3_p[4]; - u32 gpio4_p[4]; - u32 reserved22[4]; - u32 gpio2_sr[3][4]; - u32 reserved23[4]; - u32 gpio2_smt[3][4]; - u32 reserved24[(0xe100 - 0xe0ec)/4 - 1]; - u32 gpio2_e[4]; - u32 gpio3_e[7]; - u32 gpio4_e[5]; - u32 reserved24a[(0xe200 - 0xe13c)/4 - 1]; - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5_pcie; - u32 reserved25; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9_pcie; - u32 reserved26[0x1e]; - u32 soc_status[6]; - u32 reserved27[0x32]; - u32 ddrc0_con0; - u32 ddrc0_con1; - u32 ddrc1_con0; - u32 ddrc1_con1; - u32 reserved28[0xac]; - u32 io_vsel; - u32 saradc_testbit; - u32 tsadc_testbit_l; - u32 tsadc_testbit_h; - u32 reserved29[0x6c]; - u32 chip_id_addr; - u32 reserved30[0x1f]; - u32 fast_boot_addr; - u32 reserved31[0x1df]; - u32 emmccore_con[12]; - u32 reserved32[4]; - u32 emmccore_status[4]; - u32 reserved33[0x1cc]; - u32 emmcphy_con[7]; - u32 reserved34; - u32 emmcphy_status; -}; -check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0); - -struct rk3399_pmugrf_regs { - union { - u32 iomux_pwm_3a; - u32 gpio0a_iomux; - }; - u32 gpio0b_iomux; - u32 reserved0[2]; - union { - u32 spi1_rxd; - u32 tsadc_int; - u32 gpio1a_iomux; - }; - union { - u32 spi1_csclktx; - u32 iomux_pwm_3b; - u32 iomux_i2c0_sda; - u32 gpio1b_iomux; - }; - union { - u32 iomux_pwm_2; - u32 iomux_i2c0_scl; - u32 gpio1c_iomux; - }; - u32 gpio1d_iomux; - u32 reserved1[8]; - u32 gpio0_p[2]; - u32 reserved2[2]; - u32 gpio1_p[4]; - u32 reserved3[8]; - u32 gpio0a_e; - u32 reserved4; - u32 gpio0b_e; - u32 reserved5[5]; - u32 gpio1a_e; - u32 reserved6; - u32 gpio1b_e; - u32 reserved7; - u32 gpio1c_e; - u32 reserved8; - u32 gpio1d_e; - u32 reserved9[0x11]; - u32 gpio0l_sr; - u32 reserved10; - u32 gpio1l_sr; - u32 gpio1h_sr; - u32 reserved11[4]; - u32 gpio0a_smt; - u32 gpio0b_smt; - u32 reserved12[2]; - u32 gpio1a_smt; - u32 gpio1b_smt; - u32 gpio1c_smt; - u32 gpio1d_smt; - u32 reserved13[8]; - u32 gpio0l_he; - u32 reserved14; - u32 gpio1l_he; - u32 gpio1h_he; - u32 reserved15[4]; - u32 soc_con0; - u32 reserved16[9]; - u32 soc_con10; - u32 soc_con11; - u32 reserved17[0x24]; - u32 pmupvtm_con0; - u32 pmupvtm_con1; - u32 pmupvtm_status0; - u32 pmupvtm_status1; - u32 grf_osc_e; - u32 reserved18[0x2b]; - u32 os_reg0; - u32 os_reg1; - u32 os_reg2; - u32 os_reg3; -}; -check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); - -struct rk3399_pmusgrf_regs { - u32 ddr_rgn_con[35]; - u32 reserved[0x1fe5]; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_con15; - u32 reserved1[3]; - u32 soc_con19; - u32 soc_con20; - u32 soc_con21; - u32 soc_con22; - u32 reserved2[0x29]; - u32 perilp_con[9]; - u32 reserved4[7]; - u32 perilp_status; - u32 reserved5[0xfaf]; - u32 soc_con0; - u32 soc_con1; - u32 reserved6[0x3e]; - u32 pmu_con[9]; - u32 reserved7[0x17]; - u32 fast_boot_addr; - u32 reserved8[0x1f]; - u32 efuse_prg_mask; - u32 efuse_read_mask; - u32 reserved9[0x0e]; - u32 pmu_slv_con0; - u32 pmu_slv_con1; - u32 reserved10[0x771]; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 soc_con6; - u32 soc_con7; - u32 reserved11[8]; - u32 soc_con16; - u32 soc_con17; - u32 soc_con18; - u32 reserved12[0xdd]; - u32 slv_secure_con0; - u32 slv_secure_con1; - u32 reserved13; - u32 slv_secure_con2; - u32 slv_secure_con3; - u32 slv_secure_con4; -}; -check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); - -enum { - /* GRF_GPIO2A_IOMUX */ - GRF_GPIO2A0_SEL_SHIFT = 0, - GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, - GRF_I2C2_SDA = 2, - GRF_GPIO2A1_SEL_SHIFT = 2, - GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, - GRF_I2C2_SCL = 2, - GRF_GPIO2A7_SEL_SHIFT = 14, - GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, - GRF_I2C7_SDA = 2, - - /* GRF_GPIO2B_IOMUX */ - GRF_GPIO2B0_SEL_SHIFT = 0, - GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT, - GRF_I2C7_SCL = 2, - GRF_GPIO2B1_SEL_SHIFT = 2, - GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, - GRF_SPI2TPM_RXD = 1, - GRF_I2C6_SDA = 2, - GRF_GPIO2B2_SEL_SHIFT = 4, - GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, - GRF_SPI2TPM_TXD = 1, - GRF_I2C6_SCL = 2, - GRF_GPIO2B3_SEL_SHIFT = 6, - GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, - GRF_SPI2TPM_CLK = 1, - GRF_GPIO2B4_SEL_SHIFT = 8, - GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, - GRF_SPI2TPM_CSN0 = 1, - - /* GRF_GPIO2C_IOMUX */ - GRF_GPIO2C0_SEL_SHIFT = 0, - GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT, - GRF_UART0BT_SIN = 1, - GRF_GPIO2C1_SEL_SHIFT = 2, - GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT, - GRF_UART0BT_SOUT = 1, - GRF_GPIO2C4_SEL_SHIFT = 8, - GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT, - GRF_SPI5EXPPLUS_RXD = 2, - GRF_GPIO2C5_SEL_SHIFT = 10, - GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT, - GRF_SPI5EXPPLUS_TXD = 2, - GRF_GPIO2C6_SEL_SHIFT = 12, - GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT, - GRF_SPI5EXPPLUS_CLK = 2, - GRF_GPIO2C7_SEL_SHIFT = 14, - GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT, - GRF_SPI5EXPPLUS_CSN0 = 2, - - /* GRF_GPIO3A_IOMUX */ - GRF_GPIO3A0_SEL_SHIFT = 0, - GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, - GRF_MAC_TXD2 = 1, - GRF_GPIO3A1_SEL_SHIFT = 2, - GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT, - GRF_MAC_TXD3 = 1, - GRF_GPIO3A2_SEL_SHIFT = 4, - GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT, - GRF_MAC_RXD2 = 1, - GRF_GPIO3A3_SEL_SHIFT = 6, - GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT, - GRF_MAC_RXD3 = 1, - GRF_GPIO3A4_SEL_SHIFT = 8, - GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, - GRF_MAC_TXD0 = 1, - GRF_SPI0NORCODEC_RXD = 2, - GRF_GPIO3A5_SEL_SHIFT = 10, - GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, - GRF_MAC_TXD1 = 1, - GRF_SPI0NORCODEC_TXD = 2, - GRF_GPIO3A6_SEL_SHIFT = 12, - GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, - GRF_MAC_RXD0 = 1, - GRF_SPI0NORCODEC_CLK = 2, - GRF_GPIO3A7_SEL_SHIFT = 14, - GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, - GRF_MAC_RXD1 = 1, - GRF_SPI0NORCODEC_CSN0 = 2, - - /* GRF_GPIO3B_IOMUX */ - GRF_GPIO3B0_SEL_SHIFT = 0, - GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, - GRF_MAC_MDC = 1, - GRF_SPI0NORCODEC_CSN1 = 2, - GRF_GPIO3B1_SEL_SHIFT = 2, - GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT, - GRF_MAC_RXDV = 1, - GRF_GPIO3B3_SEL_SHIFT = 6, - GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT, - GRF_MAC_CLK = 1, - GRF_GPIO3B4_SEL_SHIFT = 8, - GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT, - GRF_MAC_TXEN = 1, - GRF_GPIO3B5_SEL_SHIFT = 10, - GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT, - GRF_MAC_MDIO = 1, - GRF_GPIO3B6_SEL_SHIFT = 12, - GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT, - GRF_MAC_RXCLK = 1, - GRF_UART3_SIN = 2, - GRF_GPIO3B7_SEL_SHIFT = 14, - GRF_GPIO3B7_SEL_MASK = 3 << GRF_GPIO3B7_SEL_SHIFT, - GRF_UART3_SOUT = 2, - - /* GRF_GPIO3C_IOMUX */ - GRF_GPIO3C1_SEL_SHIFT = 2, - GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, - GRF_MAC_TXCLK = 1, - - /* GRF_GPIO4A_IOMUX */ - GRF_GPIO4A1_SEL_SHIFT = 2, - GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT, - GRF_I2C1_SDA = 1, - GRF_GPIO4A2_SEL_SHIFT = 4, - GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT, - GRF_I2C1_SCL = 1, - - /* GRF_GPIO4B_IOMUX */ - GRF_GPIO4B0_SEL_SHIFT = 0, - GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, - GRF_SDMMC_DATA0 = 1, - GRF_UART2DBGA_SIN = 2, - GRF_GPIO4B1_SEL_SHIFT = 2, - GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, - GRF_SDMMC_DATA1 = 1, - GRF_UART2DBGA_SOUT = 2, - GRF_GPIO4B2_SEL_SHIFT = 4, - GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, - GRF_SDMMC_DATA2 = 1, - GRF_GPIO4B3_SEL_SHIFT = 6, - GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, - GRF_SDMMC_DATA3 = 1, - GRF_GPIO4B4_SEL_SHIFT = 8, - GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, - GRF_SDMMC_CLKOUT = 1, - GRF_GPIO4B5_SEL_SHIFT = 10, - GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, - GRF_SDMMC_CMD = 1, - - /* GRF_GPIO4C_IOMUX */ - GRF_GPIO4C0_SEL_SHIFT = 0, - GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, - GRF_UART2DGBB_SIN = 2, - GRF_HDMII2C_SCL = 3, - GRF_GPIO4C1_SEL_SHIFT = 2, - GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, - GRF_UART2DGBB_SOUT = 2, - GRF_HDMII2C_SDA = 3, - GRF_GPIO4C2_SEL_SHIFT = 4, - GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, - GRF_PWM_0 = 1, - GRF_GPIO4C3_SEL_SHIFT = 6, - GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, - GRF_UART2DGBC_SIN = 1, - GRF_GPIO4C4_SEL_SHIFT = 8, - GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, - GRF_UART2DBGC_SOUT = 1, - GRF_GPIO4C6_SEL_SHIFT = 12, - GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, - GRF_PWM_1 = 1, - - /* GRF_GPIO3A_E01 */ - GRF_GPIO3A0_E_SHIFT = 0, - GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT, - GRF_GPIO3A1_E_SHIFT = 3, - GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT, - GRF_GPIO3A2_E_SHIFT = 6, - GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT, - GRF_GPIO3A3_E_SHIFT = 9, - GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT, - GRF_GPIO3A4_E_SHIFT = 12, - GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT, - GRF_GPIO3A5_E0_SHIFT = 15, - GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT, - - /* GRF_GPIO3A_E2 */ - GRF_GPIO3A5_E12_SHIFT = 0, - GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT, - GRF_GPIO3A6_E_SHIFT = 2, - GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT, - GRF_GPIO3A7_E_SHIFT = 5, - GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT, - - /* GRF_GPIO3B_E01 */ - GRF_GPIO3B0_E_SHIFT = 0, - GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT, - GRF_GPIO3B1_E_SHIFT = 3, - GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT, - GRF_GPIO3B2_E_SHIFT = 6, - GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT, - GRF_GPIO3B3_E_SHIFT = 9, - GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT, - GRF_GPIO3B4_E_SHIFT = 12, - GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT, - GRF_GPIO3B5_E0_SHIFT = 15, - GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT, - - /* GRF_GPIO3A_E2 */ - GRF_GPIO3B5_E12_SHIFT = 0, - GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT, - GRF_GPIO3B6_E_SHIFT = 2, - GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT, - GRF_GPIO3B7_E_SHIFT = 5, - GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT, - - /* GRF_GPIO3C_E01 */ - GRF_GPIO3C0_E_SHIFT = 0, - GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT, - GRF_GPIO3C1_E_SHIFT = 3, - GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT, - GRF_GPIO3C2_E_SHIFT = 6, - GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT, - GRF_GPIO3C3_E_SHIFT = 9, - GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT, - GRF_GPIO3C4_E_SHIFT = 12, - GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT, - GRF_GPIO3C5_E0_SHIFT = 15, - GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT, - - /* GRF_GPIO3C_E2 */ - GRF_GPIO3C5_E12_SHIFT = 0, - GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT, - GRF_GPIO3C6_E_SHIFT = 2, - GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT, - GRF_GPIO3C7_E_SHIFT = 5, - GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT, - - /* GRF_SOC_CON7 */ - GRF_UART_DBG_SEL_SHIFT = 10, - GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, - GRF_UART_DBG_SEL_C = 2, - - /* GRF_SOC_CON20 */ - GRF_DSI0_VOP_SEL_SHIFT = 0, - GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, - GRF_DSI0_VOP_SEL_B = 0, - GRF_DSI0_VOP_SEL_L = 1, - GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6, - GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6, - GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6, - - /* GRF_SOC_CON22 */ - GRF_DPHY_TX0_RXMODE_SHIFT = 0, - GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT, - GRF_DPHY_TX0_RXMODE_EN = 0xb, - GRF_DPHY_TX0_RXMODE_DIS = 0, - - GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4, - GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT, - GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc, - GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, - - GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, - GRF_DPHY_TX0_TURNREQUEST_MASK = - 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT, - GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, - GRF_DPHY_TX0_TURNREQUEST_DIS = 0, - - /* PMUGRF_GPIO0A_IOMUX */ - PMUGRF_GPIO0A6_SEL_SHIFT = 12, - PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, - PMUGRF_PWM_3A = 1, - - /* PMUGRF_GPIO1A_IOMUX */ - PMUGRF_GPIO1A7_SEL_SHIFT = 14, - PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, - PMUGRF_SPI1EC_RXD = 2, - - /* PMUGRF_GPIO1B_IOMUX */ - PMUGRF_GPIO1B0_SEL_SHIFT = 0, - PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, - PMUGRF_SPI1EC_TXD = 2, - PMUGRF_GPIO1B1_SEL_SHIFT = 2, - PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, - PMUGRF_SPI1EC_CLK = 2, - PMUGRF_GPIO1B2_SEL_SHIFT = 4, - PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, - PMUGRF_SPI1EC_CSN0 = 2, - PMUGRF_GPIO1B3_SEL_SHIFT = 6, - PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT, - PMUGRF_I2C4_SDA = 1, - PMUGRF_GPIO1B4_SEL_SHIFT = 8, - PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT, - PMUGRF_I2C4_SCL = 1, - PMUGRF_GPIO1B6_SEL_SHIFT = 12, - PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, - PMUGRF_PWM_3B = 1, - PMUGRF_GPIO1B7_SEL_SHIFT = 14, - PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, - PMUGRF_I2C0PMU_SDA = 2, - - /* PMUGRF_GPIO1C_IOMUX */ - PMUGRF_GPIO1C0_SEL_SHIFT = 0, - PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, - PMUGRF_I2C0PMU_SCL = 2, - PMUGRF_GPIO1C3_SEL_SHIFT = 6, - PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, - PMUGRF_PWM_2 = 1, - PMUGRF_GPIO1C4_SEL_SHIFT = 8, - PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT, - PMUGRF_I2C8PMU_SDA = 1, - PMUGRF_GPIO1C5_SEL_SHIFT = 10, - PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT, - PMUGRF_I2C8PMU_SCL = 1, -}; - -/* GRF_SOC_CON5 */ -enum { - RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9, - RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), - RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), - RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), - - RK3399_GMAC_CLK_SEL_SHIFT = 4, - RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT), - RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT), - RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT), - RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT), -}; - -/* GRF_SOC_CON6 */ -enum { - RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15, - RK3399_RXCLK_DLY_ENA_GMAC_MASK = - (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), - RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0, - RK3399_RXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), - - RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7, - RK3399_TXCLK_DLY_ENA_GMAC_MASK = - (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), - RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0, - RK3399_TXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), - - RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8, - RK3399_CLK_RX_DL_CFG_GMAC_MASK = - (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT), - - RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0, - RK3399_CLK_TX_DL_CFG_GMAC_MASK = - (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT), -}; - -#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h deleted file mode 100644 index 9f42fbd..0000000 --- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h +++ /dev/null @@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ -#ifndef _ASM_ARCH_GRF_RV1108_H -#define _ASM_ARCH_GRF_RV1108_H - -#include <common.h> - -struct rv1108_grf { - u32 reserved[4]; - u32 gpio1a_iomux; - u32 gpio1b_iomux; - u32 gpio1c_iomux; - u32 gpio1d_iomux; - u32 gpio2a_iomux; - u32 gpio2b_iomux; - u32 gpio2c_iomux; - u32 gpio2d_iomux; - u32 gpio3a_iomux; - u32 gpio3b_iomux; - u32 gpio3c_iomux; - u32 gpio3d_iomux; - u32 reserved1[52]; - u32 gpio1a_pull; - u32 gpio1b_pull; - u32 gpio1c_pull; - u32 gpio1d_pull; - u32 gpio2a_pull; - u32 gpio2b_pull; - u32 gpio2c_pull; - u32 gpio2d_pull; - u32 gpio3a_pull; - u32 gpio3b_pull; - u32 gpio3c_pull; - u32 gpio3d_pull; - u32 reserved2[52]; - u32 gpio1a_drv; - u32 gpio1b_drv; - u32 gpio1c_drv; - u32 gpio1d_drv; - u32 gpio2a_drv; - u32 gpio2b_drv; - u32 gpio2c_drv; - u32 gpio2d_drv; - u32 gpio3a_drv; - u32 gpio3b_drv; - u32 gpio3c_drv; - u32 gpio3d_drv; - u32 reserved3[50]; - u32 gpio1l_sr; - u32 gpio1h_sr; - u32 gpio2l_sr; - u32 gpio2h_sr; - u32 gpio3l_sr; - u32 gpio3h_sr; - u32 reserved4[26]; - u32 gpio1l_smt; - u32 gpio1h_smt; - u32 gpio2l_smt; - u32 gpio2h_smt; - u32 gpio3l_smt; - u32 gpio3h_smt; - u32 reserved5[24]; - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 reserved6[20]; - u32 soc_status0; - u32 soc_status1; - u32 reserved7[30]; - u32 cpu_con0; - u32 cpu_con1; - u32 reserved8[30]; - u32 os_reg0; - u32 os_reg1; - u32 os_reg2; - u32 os_reg3; - u32 reserved9[29]; - u32 ddr_status; - u32 reserved10[30]; - u32 sig_det_con; - u32 reserved11[3]; - u32 sig_det_status; - u32 reserved12[3]; - u32 sig_det_clr; - u32 reserved13[23]; - u32 host_con0; - u32 host_con1; - u32 reserved14[2]; - u32 dma_con0; - u32 dma_con1; - u32 reserved15[59]; - u32 uoc_status; - u32 reserved16[2]; - u32 host_status; - u32 reserved17[59]; - u32 gmac_con0; - u32 reserved18[191]; - u32 chip_id; -}; - -check_member(rv1108_grf, chip_id, 0x0c00); -#endif diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h deleted file mode 100644 index 62e8bed..0000000 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Google, Inc - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) -#define RK_SETBITS(set) RK_CLRSETBITS(0, set) -#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) - -#define rk_clrsetreg(addr, clr, set) \ - writel(((clr) | (set)) << 16 | (set), addr) -#define rk_clrreg(addr, clr) writel((clr) << 16, addr) -#define rk_setreg(addr, set) writel((set) << 16 | (set), addr) - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/i2c.h b/arch/arm/include/asm/arch-rockchip/i2c.h deleted file mode 100644 index b0e1936..0000000 --- a/arch/arm/include/asm/arch-rockchip/i2c.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 SAMSUNG Electronics - * Jaehoon Chung <jh80.chung@samsung.com> - */ - -#ifndef __ASM_ARCH_I2C_H -#define __ASM_ARCH_I2C_H - -struct i2c_regs { - u32 con; - u32 clkdiv; - u32 mrxaddr; - u32 mrxraddr; - u32 mtxcnt; - u32 mrxcnt; - u32 ien; - u32 ipd; - u32 fcnt; - u32 reserved0[0x37]; - u32 txdata[8]; - u32 reserved1[0x38]; - u32 rxdata[8]; -}; - -/* Control register */ -#define I2C_CON_EN (1 << 0) -#define I2C_CON_MOD(mod) ((mod) << 1) -#define I2C_MODE_TX 0x00 -#define I2C_MODE_TRX 0x01 -#define I2C_MODE_RX 0x02 -#define I2C_MODE_RRX 0x03 -#define I2C_CON_MASK (3 << 1) - -#define I2C_CON_START (1 << 3) -#define I2C_CON_STOP (1 << 4) -#define I2C_CON_LASTACK (1 << 5) -#define I2C_CON_ACTACK (1 << 6) - -/* Clock dividor register */ -#define I2C_CLKDIV_VAL(divl, divh) \ - (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) - -/* the slave address accessed for master rx mode */ -#define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) - -/* the slave register address accessed for master rx mode */ -#define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) - -/* interrupt enable register */ -#define I2C_BTFIEN (1 << 0) -#define I2C_BRFIEN (1 << 1) -#define I2C_MBTFIEN (1 << 2) -#define I2C_MBRFIEN (1 << 3) -#define I2C_STARTIEN (1 << 4) -#define I2C_STOPIEN (1 << 5) -#define I2C_NAKRCVIEN (1 << 6) - -/* interrupt pending register */ -#define I2C_BTFIPD (1 << 0) -#define I2C_BRFIPD (1 << 1) -#define I2C_MBTFIPD (1 << 2) -#define I2C_MBRFIPD (1 << 3) -#define I2C_STARTIPD (1 << 4) -#define I2C_STOPIPD (1 << 5) -#define I2C_NAKRCVIPD (1 << 6) -#define I2C_IPD_ALL_CLEAN 0x7f - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h deleted file mode 100644 index 0f00df6..0000000 --- a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Rockchip Inc. - */ - -#ifndef _ASM_ARCH_LVDS_RK3288_H -#define _ASM_ARCH_LVDS_RK3288_H - -#define RK3288_LVDS_CH0_REG0 0x00 -#define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7) -#define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6) -#define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5) -#define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4) -#define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3) -#define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2) -#define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1) -#define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0) - -#define RK3288_LVDS_CH0_REG1 0x04 -#define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5) -#define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4) -#define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3) -#define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2) -#define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1) -#define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0) - -#define RK3288_LVDS_CH0_REG2 0x08 -#define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7) -#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6) -#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5) -#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4) -#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3) -#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2) -#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1) -#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0) - -#define RK3288_LVDS_CH0_REG3 0x0c -#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff - -#define RK3288_LVDS_CH0_REG4 0x10 -#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5) -#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4) -#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3) -#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2) -#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1) -#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0) - -#define RK3288_LVDS_CH0_REG5 0x14 -#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5) -#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4) -#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3) -#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2) -#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1) -#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0) - -#define RK3288_LVDS_CFG_REGC 0x30 -#define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00 -#define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff - -#define RK3288_LVDS_CH0_REGD 0x34 -#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f - -#define RK3288_LVDS_CH0_REG20 0x80 -#define RK3288_LVDS_CH0_REG20_MSB 0x45 -#define RK3288_LVDS_CH0_REG20_LSB 0x44 - -#define RK3288_LVDS_CFG_REG21 0x84 -#define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92 -#define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00 - -/* fbdiv value is split over 2 registers, with bit8 in reg2 */ -#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \ - (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0) -#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \ - (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK) -#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \ - (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK) - -#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3) - -#define LVDS_FMT_MASK (7 << 16) -#define LVDS_MSB (1 << 3) -#define LVDS_DUAL (1 << 4) -#define LVDS_FMT_1 (1 << 5) -#define LVDS_TTL_EN (1 << 6) -#define LVDS_START_PHASE_RST_1 (1 << 7) -#define LVDS_DCLK_INV (1 << 8) -#define LVDS_CH0_EN (1 << 11) -#define LVDS_CH1_EN (1 << 12) -#define LVDS_PWRDN (1 << 15) - -#define LVDS_24BIT (0 << 1) -#define LVDS_18BIT (1 << 1) - - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h deleted file mode 100644 index b6b03c9..0000000 --- a/arch/arm/include/asm/arch-rockchip/misc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * RK3399: Architecture common definitions - * - * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ - * Rohan Garg <rohan.garg@collabora.com> - */ - -int rockchip_cpuid_from_efuse(const u32 cpuid_offset, - const u32 cpuid_length, - u8 *cpuid); -int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); -int rockchip_setup_macaddr(void); diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h deleted file mode 100644 index 2191b7d..0000000 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef _ASM_ARCH_PERIPH_H -#define _ASM_ARCH_PERIPH_H - -/* - * The peripherals supported by the hardware. This is used to specify clocks - * and pinctrl settings. Some SoCs will not support all of these, but it - * provides a common reference for common drivers to use. - */ -enum periph_id { - PERIPH_ID_PWM0, - PERIPH_ID_PWM1, - PERIPH_ID_PWM2, - PERIPH_ID_PWM3, - PERIPH_ID_PWM4, - PERIPH_ID_I2C0, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_I2C8, - PERIPH_ID_SPI0, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_SPI3, - PERIPH_ID_SPI4, - PERIPH_ID_SPI5, - PERIPH_ID_UART0, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_UART4, - PERIPH_ID_LCDC0, - PERIPH_ID_LCDC1, - PERIPH_ID_SDMMC0, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC2, - PERIPH_ID_HDMI, - PERIPH_ID_GMAC, - PERIPH_ID_SFC, - PERIPH_ID_I2S, - - PERIPH_ID_COUNT, - - /* Some aliases */ - PERIPH_ID_EMMC = PERIPH_ID_SDMMC0, - PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1, - PERIPH_ID_UART_BT = PERIPH_ID_UART0, - PERIPH_ID_UART_BB = PERIPH_ID_UART1, - PERIPH_ID_UART_DBG = PERIPH_ID_UART2, - PERIPH_ID_UART_GPS = PERIPH_ID_UART3, - PERIPH_ID_UART_EXP = PERIPH_ID_UART4, -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h deleted file mode 100644 index f7b9a06..0000000 --- a/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _ASM_ARCH_PMU_RK3188_H -#define _ASM_ARCH_PMU_RK3188_H - -struct rk3188_pmu { - u32 wakeup_cfg[2]; - u32 pwrdn_con; - u32 pwrdn_st; - - u32 int_con; - u32 int_st; - u32 misc_con; - - u32 osc_cnt; - u32 pll_cnt; - u32 pmu_cnt; - u32 ddrio_pwron_cnt; - u32 wakeup_rst_clr_cnt; - u32 scu_pwrdwn_cnt; - u32 scu_pwrup_cnt; - u32 misc_con1; - u32 gpio0_con; - - u32 sys_reg[4]; - u32 reserved0[4]; - u32 stop_int_dly; - u32 gpio0_p[2]; -}; -check_member(rk3188_pmu, gpio0_p[1], 0x0068); - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h deleted file mode 100644 index 8553d2e..0000000 --- a/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - * - * Copyright 2014 Rockchip Inc. - */ - -#ifndef _ASM_ARCH_PMU_RK3288_H -#define _ASM_ARCH_PMU_RK3288_H - -struct rk3288_pmu { - u32 wakeup_cfg[2]; - u32 pwrdn_con; - u32 pwrdn_st; - - u32 idle_req; - u32 idle_st; - u32 pwrmode_con; - u32 pwr_state; - - u32 osc_cnt; - u32 pll_cnt; - u32 stabl_cnt; - u32 ddr0io_pwron_cnt; - - u32 ddr1io_pwron_cnt; - u32 core_pwrdn_cnt; - u32 core_pwrup_cnt; - u32 gpu_pwrdn_cnt; - - u32 gpu_pwrup_cnt; - u32 wakeup_rst_clr_cnt; - u32 sft_con; - u32 ddr_sref_st; - - u32 int_con; - u32 int_st; - u32 boot_addr_sel; - u32 grf_con; - - u32 gpio_sr; - u32 gpio0pull[3]; - - u32 gpio0drv[3]; - u32 gpio_op; - - u32 gpio0_sel18; /* 0x80 */ - u32 gpio0_iomux[4]; /* a, b, c, d */ - u32 sys_reg[4]; -}; -check_member(rk3288_pmu, sys_reg[3], 0x00a0); - -enum { - PMU_GPIO0_A = 0, - PMU_GPIO0_B, - PMU_GPIO0_C, - PMU_GPIO0_D, -}; - -/* PMU_GPIO0_B_IOMUX */ -enum { - GPIO0_B7_SHIFT = 14, - GPIO0_B7_MASK = 1, - GPIO0_B7_GPIOB7 = 0, - GPIO0_B7_I2C0PMU_SDA, - - GPIO0_B5_SHIFT = 10, - GPIO0_B5_MASK = 1, - GPIO0_B5_GPIOB5 = 0, - GPIO0_B5_CLK_27M, - - GPIO0_B2_SHIFT = 4, - GPIO0_B2_MASK = 1, - GPIO0_B2_GPIOB2 = 0, - GPIO0_B2_TSADC_INT, -}; - -/* PMU_GPIO0_C_IOMUX */ -enum { - GPIO0_C1_SHIFT = 2, - GPIO0_C1_MASK = 3, - GPIO0_C1_GPIOC1 = 0, - GPIO0_C1_TEST_CLKOUT, - GPIO0_C1_CLKT1_27M, - - GPIO0_C0_SHIFT = 0, - GPIO0_C0_MASK = 1, - GPIO0_C0_GPIOC0 = 0, - GPIO0_C0_I2C0PMU_SCL, -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h deleted file mode 100644 index f1096dc..0000000 --- a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2018 Rockchip Electronics Co., Ltd. - * - */ - -#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ -#define __SOC_ROCKCHIP_RK3399_PMU_H__ - -struct rk3399_pmu_regs { - u32 pmu_wakeup_cfg[5]; - u32 pmu_pwrdn_con; - u32 pmu_pwrdn_st; - u32 pmu_pll_con; - u32 pmu_pwrmode_con; - u32 pmu_sft_con; - u32 pmu_int_con; - u32 pmu_int_st; - u32 pmu_gpio0_pos_int_con; - u32 pmu_gpio0_net_int_con; - u32 pmu_gpio1_pos_int_con; - u32 pmu_gpio1_net_int_con; - u32 pmu_gpio0_pos_int_st; - u32 pmu_gpio0_net_int_st; - u32 pmu_gpio1_pos_int_st; - u32 pmu_gpio1_net_int_st; - u32 pmu_pwrdn_inten; - u32 pmu_pwrdn_status; - u32 pmu_wakeup_status; - u32 pmu_bus_clr; - u32 pmu_bus_idle_req; - u32 pmu_bus_idle_st; - u32 pmu_bus_idle_ack; - u32 pmu_cci500_con; - u32 pmu_adb400_con; - u32 pmu_adb400_st; - u32 pmu_power_st; - u32 pmu_core_pwr_st; - u32 pmu_osc_cnt; - u32 pmu_plllock_cnt; - u32 pmu_pllrst_cnt; - u32 pmu_stable_cnt; - u32 pmu_ddrio_pwron_cnt; - u32 pmu_wakeup_rst_clr_cnt; - u32 pmu_ddr_sref_st; - u32 pmu_scu_l_pwrdn_cnt; - u32 pmu_scu_l_pwrup_cnt; - u32 pmu_scu_b_pwrdn_cnt; - u32 pmu_scu_b_pwrup_cnt; - u32 pmu_gpu_pwrdn_cnt; - u32 pmu_gpu_pwrup_cnt; - u32 pmu_center_pwrdn_cnt; - u32 pmu_center_pwrup_cnt; - u32 pmu_timeout_cnt; - u32 pmu_cpu0apm_con; - u32 pmu_cpu1apm_con; - u32 pmu_cpu2apm_con; - u32 pmu_cpu3apm_con; - u32 pmu_cpu0bpm_con; - u32 pmu_cpu1bpm_con; - u32 pmu_noc_auto_ena; - u32 pmu_pwrdn_con1; - u32 reserved0[0x4]; - u32 pmu_sys_reg_reg0; - u32 pmu_sys_reg_reg1; - u32 pmu_sys_reg_reg2; - u32 pmu_sys_reg_reg3; -}; - -check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); - -#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h deleted file mode 100644 index b5178db..0000000 --- a/arch/arm/include/asm/arch-rockchip/pwm.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Google, Inc - * (C) Copyright 2008-2014 Rockchip Electronics - */ - -#ifndef _ASM_ARCH_PWM_H -#define _ASM_ARCH_PWM_H - -struct rk3288_pwm { - u32 cnt; - u32 period_hpr; - u32 duty_lpr; - u32 ctrl; -}; -check_member(rk3288_pwm, ctrl, 0xc); - -#define RK_PWM_DISABLE (0 << 0) -#define RK_PWM_ENABLE (1 << 0) - -#define PWM_ONE_SHOT (0 << 1) -#define PWM_CONTINUOUS (1 << 1) -#define RK_PWM_CAPTURE (1 << 2) - -#define PWM_DUTY_POSTIVE (1 << 3) -#define PWM_DUTY_NEGATIVE (0 << 3) -#define PWM_DUTY_MASK (1 << 3) - -#define PWM_INACTIVE_POSTIVE (1 << 4) -#define PWM_INACTIVE_NEGATIVE (0 << 4) -#define PWM_INACTIVE_MASK (1 << 4) - -#define PWM_OUTPUT_LEFT (0 << 5) -#define PWM_OUTPUT_CENTER (1 << 5) - -#define PWM_LP_ENABLE (1 << 8) -#define PWM_LP_DISABLE (0 << 8) - -#define PWM_SEL_SCALE_CLK (1 << 9) -#define PWM_SEL_SRC_CLK (0 << 9) - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h deleted file mode 100644 index c24b090..0000000 --- a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Rockchip Inc. - */ -#ifndef _ASM_ARCH_QOS_RK3288_H -#define _ASM_ARCH_QOS_RK3288_H - -#define PRIORITY_HIGH_SHIFT 2 -#define PRIORITY_LOW_SHIFT 0 - -#define CPU_AXI_QOS_PRIORITY 0x08 - -#define VIO0_VOP_QOS 0xffad0400 -#define VIO1_VOP_QOS 0xffad0000 -#define VIO1_ISP_R_QOS 0xffad0900 -#define VIO1_ISP_W0_QOS 0xffad0100 -#define VIO1_ISP_W1_QOS 0xffad0180 - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h deleted file mode 100644 index c13957a..0000000 --- a/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd - * author: Eric Gao <eric.gao@rock-chips.com> - */ - -#ifndef ROCKCHIP_MIPI_DSI_H -#define ROCKCHIP_MIPI_DSI_H - -/* - * All these mipi controller register declaration provide reg address offset, - * bits width, bit offset for a specified register bits. With these message, we - * can set or clear every bits individually for a 32bit widthregister. We use - * DSI_HOST_BITS macro definition to combinat these message using the following - * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit) - * For example: - * #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) - * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr - * offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0 - */ -#define ADDR_SHIFT 16 -#define BITS_SHIFT 8 -#define OFFSET_SHIFT 0 -#define DSI_HOST_BITS(addr, bits, bit_offset) \ -((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT)) - -/* DWC_DSI_VERSION_0x3133302A */ -#define VERSION DSI_HOST_BITS(0x000, 32, 0) -#define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) -#define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8) -#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0) -#define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0) -#define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8) -#define DPI_COLOR_CODING DSI_HOST_BITS(0x010, 4, 0) -#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 4) -#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 3) -#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 2) -#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 1) -#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 0) -#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16) -#define INVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 0) -#define CRC_RX_EN DSI_HOST_BITS(0x02c, 1, 4) -#define ECC_RX_EN DSI_HOST_BITS(0x02c, 1, 3) -#define BTA_EN DSI_HOST_BITS(0x02c, 1, 2) -#define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1) -#define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0) -#define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0) -#define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0) -#define VPG_ORIENTATION DSI_HOST_BITS(0x038, 1, 24) -#define VPG_MODE DSI_HOST_BITS(0x038, 1, 20) -#define VPG_EN DSI_HOST_BITS(0x038, 1, 16) -#define LP_CMD_EN DSI_HOST_BITS(0x038, 1, 15) -#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0x038, 1, 14) -#define LP_HFP_EN DSI_HOST_BITS(0x038, 1, 13) -#define LP_HBP_EN DSI_HOST_BITS(0x038, 1, 12) -#define LP_VACT_EN DSI_HOST_BITS(0x038, 1, 11) -#define LP_VFP_EN DSI_HOST_BITS(0x038, 1, 10) -#define LP_VBP_EN DSI_HOST_BITS(0x038, 1, 9) -#define LP_VSA_EN DSI_HOST_BITS(0x038, 1, 8) -#define VID_MODE_TYPE DSI_HOST_BITS(0x038, 2, 0) -#define VID_PKT_SIZE DSI_HOST_BITS(0x03c, 14, 0) -#define NUM_CHUNKS DSI_HOST_BITS(0x040, 13, 0) -#define NULL_PKT_SIZE DSI_HOST_BITS(0x044, 13, 0) -#define VID_HSA_TIME DSI_HOST_BITS(0x048, 12, 0) -#define VID_HBP_TIME DSI_HOST_BITS(0x04c, 12, 0) -#define VID_HLINE_TIME DSI_HOST_BITS(0x050, 15, 0) -#define VID_VSA_LINES DSI_HOST_BITS(0x054, 10, 0) -#define VID_VBP_LINES DSI_HOST_BITS(0x058, 10, 0) -#define VID_VFP_LINES DSI_HOST_BITS(0x05c, 10, 0) -#define VID_ACTIVE_LINES DSI_HOST_BITS(0x060, 14, 0) -#define EDPI_CMD_SIZE DSI_HOST_BITS(0x064, 16, 0) -#define MAX_RD_PKT_SIZE DSI_HOST_BITS(0x068, 1, 24) -#define DCS_LW_TX DSI_HOST_BITS(0x068, 1, 19) -#define DCS_SR_0P_TX DSI_HOST_BITS(0x068, 1, 18) -#define DCS_SW_1P_TX DSI_HOST_BITS(0x068, 1, 17) -#define DCS_SW_0P_TX DSI_HOST_BITS(0x068, 1, 16) -#define GEN_LW_TX DSI_HOST_BITS(0x068, 1, 14) -#define GEN_SR_2P_TX DSI_HOST_BITS(0x068, 1, 13) -#define GEN_SR_1P_TX DSI_HOST_BITS(0x068, 1, 12) -#define GEN_SR_0P_TX DSI_HOST_BITS(0x068, 1, 11) -#define GEN_SW_2P_TX DSI_HOST_BITS(0x068, 1, 10) -#define GEN_SW_1P_TX DSI_HOST_BITS(0x068, 1, 9) -#define GEN_SW_0P_TX DSI_HOST_BITS(0x068, 1, 8) -#define ACK_RQST_EN DSI_HOST_BITS(0x068, 1, 1) -#define TEAR_FX_EN DSI_HOST_BITS(0x068, 1, 0) -#define GEN_WC_MSBYTE DSI_HOST_BITS(0x06c, 14, 16) -#define GEN_WC_LSBYTE DSI_HOST_BITS(0x06c, 8, 8) -#define GEN_VC DSI_HOST_BITS(0x06c, 2, 6) -#define GEN_DT DSI_HOST_BITS(0x06c, 6, 0) -#define GEN_PLD_DATA DSI_HOST_BITS(0x070, 32, 0) -#define GEN_RD_CMD_BUSY DSI_HOST_BITS(0x074, 1, 6) -#define GEN_PLD_R_FULL DSI_HOST_BITS(0x074, 1, 5) -#define GEN_PLD_R_EMPTY DSI_HOST_BITS(0x074, 1, 4) -#define GEN_PLD_W_FULL DSI_HOST_BITS(0x074, 1, 3) -#define GEN_PLD_W_EMPTY DSI_HOST_BITS(0x074, 1, 2) -#define GEN_CMD_FULL DSI_HOST_BITS(0x074, 1, 1) -#define GEN_CMD_EMPTY DSI_HOST_BITS(0x074, 1, 0) -#define HSTX_TO_CNT DSI_HOST_BITS(0x078, 16, 16) -#define LPRX_TO_CNT DSI_HOST_BITS(0x078, 16, 0) -#define HS_RD_TO_CNT DSI_HOST_BITS(0x07c, 16, 0) -#define LP_RD_TO_CNT DSI_HOST_BITS(0x080, 16, 0) -#define PRESP_TO_MODE DSI_HOST_BITS(0x084, 1, 24) -#define HS_WR_TO_CNT DSI_HOST_BITS(0x084, 16, 0) -#define LP_WR_TO_CNT DSI_HOST_BITS(0x088, 16, 0) -#define BTA_TO_CNT DSI_HOST_BITS(0x08c, 16, 0) -#define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0x094, 1, 1) -#define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0x094, 1, 0) -#define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 16) -#define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 0) -#define PHY_HS2LP_TIME DSI_HOST_BITS(0x09c, 8, 24) -#define PHY_LP2HS_TIME DSI_HOST_BITS(0x09c, 8, 16) -#define MAX_RD_TIME DSI_HOST_BITS(0x09c, 15, 0) -#define PHY_FORCEPLL DSI_HOST_BITS(0x0a0, 1, 3) -#define PHY_ENABLECLK DSI_HOST_BITS(0x0a0, 1, 2) -#define PHY_RSTZ DSI_HOST_BITS(0x0a0, 1, 1) -#define PHY_SHUTDOWNZ DSI_HOST_BITS(0x0a0, 1, 0) -#define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0x0a4, 8, 8) -#define N_LANES DSI_HOST_BITS(0x0a4, 2, 0) -#define PHY_TXEXITULPSLAN DSI_HOST_BITS(0x0a8, 1, 3) -#define PHY_TXREQULPSLAN DSI_HOST_BITS(0x0a8, 1, 2) -#define PHY_TXEXITULPSCLK DSI_HOST_BITS(0x0a8, 1, 1) -#define PHY_TXREQULPSCLK DSI_HOST_BITS(0x0a8, 1, 0) -#define PHY_TX_TRIGGERS DSI_HOST_BITS(0x0ac, 4, 0) -#define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0x0b0, 1, 2) -#define PHYLOCK DSI_HOST_BITS(0x0b0, 1, 0) -#define PHY_TESTCLK DSI_HOST_BITS(0x0b4, 1, 1) -#define PHY_TESTCLR DSI_HOST_BITS(0x0b4, 1, 0) -#define PHY_TESTEN DSI_HOST_BITS(0x0b8, 1, 16) -#define PHY_TESTDOUT DSI_HOST_BITS(0x0b8, 8, 8) -#define PHY_TESTDIN DSI_HOST_BITS(0x0b8, 8, 0) -#define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0) -#define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0) -#define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0) -#define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0) -#define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0) -#define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0) -#define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0) -#define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0) - -#define CODE_HS_RX_CLOCK 0x34 -#define CODE_HS_RX_LANE0 0x44 -#define CODE_HS_RX_LANE1 0x54 -#define CODE_HS_RX_LANE2 0x84 -#define CODE_HS_RX_LANE3 0x94 - -#define CODE_PLL_VCORANGE_VCOCAP 0x10 -#define CODE_PLL_CPCTRL 0x11 -#define CODE_PLL_LPF_CP 0x12 -#define CODE_PLL_INPUT_DIV_RAT 0x17 -#define CODE_PLL_LOOP_DIV_RAT 0x18 -#define CODE_PLL_INPUT_LOOP_DIV_RAT 0x19 -#define CODE_BANDGAP_BIAS_CTRL 0x20 -#define CODE_TERMINATION_CTRL 0x21 -#define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22 - -#define CODE_HSTXDATALANEREQUSETSTATETIME 0x70 -#define CODE_HSTXDATALANEPREPARESTATETIME 0x71 -#define CODE_HSTXDATALANEHSZEROSTATETIME 0x72 - -/* Transmission mode between vop and MIPI controller */ -enum vid_mode_type_t { - NON_BURST_SYNC_PLUSE = 0, - NON_BURST_SYNC_EVENT, - BURST_MODE, -}; - -enum cmd_video_mode { - VIDEO_MODE = 0, - CMD_MODE, -}; - -/* Indicate MIPI DSI color mode */ -enum dpi_color_coding { - DPI_16BIT_CFG_1 = 0, - DPI_16BIT_CFG_2, - DPI_16BIT_CFG_3, - DPI_18BIT_CFG_1, - DPI_18BIT_CFG_2, - DPI_24BIT, - DPI_20BIT_YCBCR_422_LP, - DPI_24BIT_YCBCR_422, - DPI_16BIT_YCBCR_422, - DPI_30BIT, - DPI_36BIT, - DPI_12BIT_YCBCR_420, -}; - -/* Indicate which VOP the MIPI DSI use, bit or little one */ -enum vop_id { - VOP_B = 0, - VOP_L, -}; - -#endif /* end of ROCKCHIP_MIPI_DSI_H */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h deleted file mode 100644 index 9220763..0000000 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015 Google, Inc - * - * Copyright 2014 Rockchip Inc. - */ - -#ifndef _ASM_ARCH_RK3288_SDRAM_H__ -#define _ASM_ARCH_RK3288_SDRAM_H__ - -struct rk3288_sdram_channel { - /* - * bit width in address, eg: - * 8 banks using 3 bit to address, - * 2 cs using 1 bit to address. - */ - u8 rank; - u8 col; - u8 bk; - u8 bw; - u8 dbw; - u8 row_3_4; - u8 cs0_row; - u8 cs1_row; -#if CONFIG_IS_ENABLED(OF_PLATDATA) - /* - * For of-platdata, which would otherwise convert this into two - * byte-swapped integers. With a size of 9 bytes, this struct will - * appear in of-platdata as a byte array. - * - * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) - */ - u8 dummy; -#endif -}; - -struct rk3288_sdram_pctl_timing { - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; -}; -check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); - -struct rk3288_sdram_phy_timing { - u32 dtpr0; - u32 dtpr1; - u32 dtpr2; - u32 mr[4]; -}; - -struct rk3288_base_params { - u32 noc_timing; - u32 noc_activate; - u32 ddrconfig; - u32 ddr_freq; - u32 dramtype; - /* - * DDR Stride is address mapping for DRAM space - * Stride Ch 0 range Ch1 range Total - * 0x00 0-256MB 256MB-512MB 512MB - * 0x05 0-1GB 0-1GB 1GB - * 0x09 0-2GB 0-2GB 2GB - * 0x0d 0-4GB 0-4GB 4GB - * 0x17 N/A 0-4GB 4GB - * 0x1a 0-4GB 4GB-8GB 8GB - */ - u32 stride; - u32 odt; -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h deleted file mode 100644 index 8027b53..0000000 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Rockchip Electronics Co., Ltd. - */ - -#ifndef _ASM_ARCH_SDRAM_COMMON_H -#define _ASM_ARCH_SDRAM_COMMON_H - -enum { - DDR4 = 0, - DDR3 = 0x3, - LPDDR2 = 0x5, - LPDDR3 = 0x6, - LPDDR4 = 0x7, - UNUSED = 0xFF -}; - -struct sdram_cap_info { - unsigned int rank; - /* dram column number, 0 means this channel is invalid */ - unsigned int col; - /* dram bank number, 3:8bank, 2:4bank */ - unsigned int bk; - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int bw; - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int dbw; - /* - * row_3_4 = 1: 6Gb or 12Gb die - * row_3_4 = 0: normal die, power of 2 - */ - unsigned int row_3_4; - unsigned int cs0_row; - unsigned int cs1_row; - unsigned int ddrconfig; -}; - -struct sdram_base_params { - unsigned int ddr_freq; - unsigned int dramtype; - unsigned int num_channels; - unsigned int stride; - unsigned int odt; -}; - -/* - * sys_reg bitfield struct - * [31] row_3_4_ch1 - * [30] row_3_4_ch0 - * [29:28] chinfo - * [27] rank_ch1 - * [26:25] col_ch1 - * [24] bk_ch1 - * [23:22] cs0_row_ch1 - * [21:20] cs1_row_ch1 - * [19:18] bw_ch1 - * [17:16] dbw_ch1; - * [15:13] ddrtype - * [12] channelnum - * [11] rank_ch0 - * [10:9] col_ch0 - * [8] bk_ch0 - * [7:6] cs0_row_ch0 - * [5:4] cs1_row_ch0 - * [3:2] bw_ch0 - * [1:0] dbw_ch0 -*/ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define DDR_SYS_REG_VERSION 2 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 -#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch)) -#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT) -#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \ - SYS_REG_NUM_CH_SHIFT) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \ - SYS_REG_RANK_SHIFT(ch)) -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch)) -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 -#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ - SYS_REG_BK_SHIFT(ch)) -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch)) -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 -#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) - -#define SYS_REG_ENC_VERSION(n) ((n) << 28) -#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ - (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ - (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ - (5 + 2 * (ch)); \ - } while (0) - -#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ - (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ - (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ - (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ - (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ - (4 + 2 * (ch)); \ - } while (0) - -#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch)) -#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch)) - -/* Get sdram size decode from reg */ -size_t rockchip_sdram_size(phys_addr_t reg); - -/* Called by U-Boot board_init_r for Rockchip SoCs */ -int dram_init(void); - -#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG) -inline void sdram_print_dram_type(unsigned char dramtype) -{ -} - -inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, - struct sdram_base_params *base) -{ -} - -inline void sdram_print_stride(unsigned int stride) -{ -} -#else -void sdram_print_dram_type(unsigned char dramtype); -void sdram_print_ddr_info(struct sdram_cap_info *cap_info, - struct sdram_base_params *base); -void sdram_print_stride(unsigned int stride); -#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h deleted file mode 100644 index 5de3220..0000000 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h +++ /dev/null @@ -1,340 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ -#ifndef _ASM_ARCH_SDRAM_RK3036_H -#define _ASM_ARCH_SDRAM_RK3036_H - -#include <common.h> - -struct rk3036_ddr_pctl { - u32 scfg; - u32 sctl; - u32 stat; - u32 intrstat; - u32 reserved0[12]; - u32 mcmd; - u32 powctl; - u32 powstat; - u32 cmdtstat; - u32 cmdtstaten; - u32 reserved1[3]; - u32 mrrcfg0; - u32 mrrstat0; - u32 mrrstat1; - u32 reserved2[4]; - u32 mcfg1; - u32 mcfg; - u32 ppcfg; - u32 mstat; - u32 lpddr2zqcfg; - u32 reserved3; - u32 dtupdes; - u32 dtuna; - u32 dtune; - u32 dtuprd0; - u32 dtuprd1; - u32 dtuprd2; - u32 dtuprd3; - u32 dtuawdt; - u32 reserved4[3]; - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 reserved5[47]; - u32 dtuwactl; - u32 dturactl; - u32 dtucfg; - u32 dtuectl; - u32 dtuwd0; - u32 dtuwd1; - u32 dtuwd2; - u32 dtuwd3; - u32 dtuwdm; - u32 dturd0; - u32 dturd1; - u32 dturd2; - u32 dturd3; - u32 dtulfsrwd; - u32 dtulfsrrd; - u32 dtueaf; - u32 dfitctrldelay; - u32 dfiodtcfg; - u32 dfiodtcfg1; - u32 dfiodtrankmap; - u32 dfitphywrdata; - u32 dfitphywrlat; - u32 reserved7[2]; - u32 dfitrddataen; - u32 dfitphyrdlat; - u32 reserved8[2]; - u32 dfitphyupdtype0; - u32 dfitphyupdtype1; - u32 dfitphyupdtype2; - u32 dfitphyupdtype3; - u32 dfitctrlupdmin; - u32 dfitctrlupdmax; - u32 dfitctrlupddly; - u32 reserved9; - u32 dfiupdcfg; - u32 dfitrefmski; - u32 dfitctrlupdi; - u32 reserved10[4]; - u32 dfitrcfg0; - u32 dfitrstat0; - u32 dfitrwrlvlen; - u32 dfitrrdlvlen; - u32 dfitrrdlvlgateen; - u32 dfiststat0; - u32 dfistcfg0; - u32 dfistcfg1; - u32 reserved11; - u32 dfitdramclken; - u32 dfitdramclkdis; - u32 dfistcfg2; - u32 dfistparclr; - u32 dfistparlog; - u32 reserved12[3]; - u32 dfilpcfg0; - u32 reserved13[3]; - u32 dfitrwrlvlresp0; - u32 dfitrwrlvlresp1; - u32 dfitrwrlvlresp2; - u32 dfitrrdlvlresp0; - u32 dfitrrdlvlresp1; - u32 dfitrrdlvlresp2; - u32 dfitrwrlvldelay0; - u32 dfitrwrlvldelay1; - u32 dfitrwrlvldelay2; - u32 dfitrrdlvldelay0; - u32 dfitrrdlvldelay1; - u32 dfitrrdlvldelay2; - u32 dfitrrdlvlgatedelay0; - u32 dfitrrdlvlgatedelay1; - u32 dfitrrdlvlgatedelay2; - u32 dfitrcmd; - u32 reserved14[46]; - u32 ipvr; - u32 iptr; -}; -check_member(rk3036_ddr_pctl, iptr, 0x03fc); - -struct rk3036_ddr_phy { - u32 ddrphy_reg1; - u32 ddrphy_reg3; - u32 ddrphy_reg2; - u32 reserve[11]; - u32 ddrphy_reg4a; - u32 ddrphy_reg4b; - u32 reserve1[5]; - u32 ddrphy_reg16; - u32 reserve2; - u32 ddrphy_reg18; - u32 ddrphy_reg19; - u32 reserve3; - u32 ddrphy_reg21; - u32 reserve4; - u32 ddrphy_reg22; - u32 reserve5[3]; - u32 ddrphy_reg25; - u32 ddrphy_reg26; - u32 ddrphy_reg27; - u32 ddrphy_reg28; - u32 reserve6[17]; - u32 ddrphy_reg6; - u32 ddrphy_reg7; - u32 reserve7; - u32 ddrphy_reg8; - u32 ddrphy_reg0e4; - u32 reserve8[11]; - u32 ddrphy_reg9; - u32 ddrphy_reg10; - u32 reserve9; - u32 ddrphy_reg11; - u32 ddrphy_reg124; - u32 reserve10[38]; - u32 ddrphy_reg29; - u32 reserve11[40]; - u32 ddrphy_reg264; - u32 reserve12[18]; - u32 ddrphy_reg2a; - u32 reserve13[4]; - u32 ddrphy_reg30; - u32 ddrphy_reg31; - u32 ddrphy_reg32; - u32 ddrphy_reg33; - u32 ddrphy_reg34; - u32 ddrphy_reg35; - u32 ddrphy_reg36; - u32 ddrphy_reg37; - u32 ddrphy_reg38; - u32 ddrphy_reg39; - u32 ddrphy_reg40; - u32 ddrphy_reg41; - u32 ddrphy_reg42; - u32 ddrphy_reg43; - u32 ddrphy_reg44; - u32 ddrphy_reg45; - u32 ddrphy_reg46; - u32 ddrphy_reg47; - u32 ddrphy_reg48; - u32 ddrphy_reg49; - u32 ddrphy_reg50; - u32 ddrphy_reg51; - u32 ddrphy_reg52; - u32 ddrphy_reg53; - u32 reserve14; - u32 ddrphy_reg54; - u32 ddrphy_reg55; - u32 ddrphy_reg56; - u32 ddrphy_reg57; - u32 ddrphy_reg58; - u32 ddrphy_reg59; - u32 ddrphy_reg5a; - u32 ddrphy_reg5b; - u32 ddrphy_reg5c; - u32 ddrphy_reg5d; - u32 ddrphy_reg5e; - u32 reserve15[28]; - u32 ddrphy_reg5f; - u32 reserve16[6]; - u32 ddrphy_reg60; - u32 ddrphy_reg61; - u32 ddrphy_reg62; -}; -check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8); - -struct rk3036_pctl_timing { - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; -}; - -struct rk3036_phy_timing { - u32 mr[4]; - u32 bl; - u32 cl_al; -}; - -typedef union { - u32 noc_timing; - struct { - u32 acttoact:6; - u32 rdtomiss:6; - u32 wrtomiss:6; - u32 burstlen:3; - u32 rdtowr:5; - u32 wrtord:5; - u32 bwratio:1; - }; -} rk3036_noc_timing; - -struct rk3036_ddr_timing { - u32 freq; - struct rk3036_pctl_timing pctl_timing; - struct rk3036_phy_timing phy_timing; - rk3036_noc_timing noc_timing; -}; - -struct rk3036_service_sys { - u32 id_coreid; - u32 id_revisionid; - u32 ddrconf; - u32 ddrtiming; - u32 ddrmode; - u32 readlatency; -}; - -struct rk3036_ddr_config { - /* - * 000: lpddr - * 001: ddr - * 010: ddr2 - * 011: ddr3 - * 100: lpddr2-s2 - * 101: lpddr2-s4 - * 110: lpddr3 - */ - u32 ddr_type; - u32 rank; - u32 cs0_row; - u32 cs1_row; - - /* 2: 4bank, 3: 8bank */ - u32 bank; - u32 col; - - /* bw(0: 8bit, 1: 16bit, 2: 32bit) */ - u32 bw; -}; - -/* rk3036 sdram initial */ -void sdram_init(void); - -/* get ddr die config, implement in specific board */ -void get_ddr_config(struct rk3036_ddr_config *config); - -/* get ddr size on board */ -size_t sdram_size(void); -#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h deleted file mode 100644 index 336c5d7..0000000 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h +++ /dev/null @@ -1,573 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ -#ifndef _ASM_ARCH_SDRAM_RK322X_H -#define _ASM_ARCH_SDRAM_RK322X_H - -#include <common.h> - -struct rk322x_sdram_channel { - /* - * bit width in address, eg: - * 8 banks using 3 bit to address, - * 2 cs using 1 bit to address. - */ - u8 rank; - u8 col; - u8 bk; - u8 bw; - u8 dbw; - u8 row_3_4; - u8 cs0_row; - u8 cs1_row; -#if CONFIG_IS_ENABLED(OF_PLATDATA) - /* - * For of-platdata, which would otherwise convert this into two - * byte-swapped integers. With a size of 9 bytes, this struct will - * appear in of-platdata as a byte array. - * - * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) - */ - u8 dummy; -#endif -}; - -struct rk322x_ddr_pctl { - u32 scfg; - u32 sctl; - u32 stat; - u32 intrstat; - u32 reserved0[(0x40 - 0x10) / 4]; - u32 mcmd; - u32 powctl; - u32 powstat; - u32 cmdtstat; - u32 cmdtstaten; - u32 reserved1[(0x60 - 0x54) / 4]; - u32 mrrcfg0; - u32 mrrstat0; - u32 mrrstat1; - u32 reserved2[(0x7c - 0x6c) / 4]; - - u32 mcfg1; - u32 mcfg; - u32 ppcfg; - u32 mstat; - u32 lpddr2zqcfg; - u32 reserved3; - - u32 dtupdes; - u32 dtuna; - u32 dtune; - u32 dtuprd0; - u32 dtuprd1; - u32 dtuprd2; - u32 dtuprd3; - u32 dtuawdt; - u32 reserved4[(0xc0 - 0xb4) / 4]; - - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; - u32 tref_mem_ddr3; - u32 reserved5[(0x180 - 0x14c) / 4]; - u32 ecccfg; - u32 ecctst; - u32 eccclr; - u32 ecclog; - u32 reserved6[(0x200 - 0x190) / 4]; - u32 dtuwactl; - u32 dturactl; - u32 dtucfg; - u32 dtuectl; - u32 dtuwd0; - u32 dtuwd1; - u32 dtuwd2; - u32 dtuwd3; - u32 dtuwdm; - u32 dturd0; - u32 dturd1; - u32 dturd2; - u32 dturd3; - u32 dtulfsrwd; - u32 dtulfsrrd; - u32 dtueaf; - /* dfi control registers */ - u32 dfitctrldelay; - u32 dfiodtcfg; - u32 dfiodtcfg1; - u32 dfiodtrankmap; - /* dfi write data registers */ - u32 dfitphywrdata; - u32 dfitphywrlat; - u32 reserved7[(0x260 - 0x258) / 4]; - u32 dfitrddataen; - u32 dfitphyrdlat; - u32 reserved8[(0x270 - 0x268) / 4]; - u32 dfitphyupdtype0; - u32 dfitphyupdtype1; - u32 dfitphyupdtype2; - u32 dfitphyupdtype3; - u32 dfitctrlupdmin; - u32 dfitctrlupdmax; - u32 dfitctrlupddly; - u32 reserved9; - u32 dfiupdcfg; - u32 dfitrefmski; - u32 dfitctrlupdi; - u32 reserved10[(0x2ac - 0x29c) / 4]; - u32 dfitrcfg0; - u32 dfitrstat0; - u32 dfitrwrlvlen; - u32 dfitrrdlvlen; - u32 dfitrrdlvlgateen; - u32 dfiststat0; - u32 dfistcfg0; - u32 dfistcfg1; - u32 reserved11; - u32 dfitdramclken; - u32 dfitdramclkdis; - u32 dfistcfg2; - u32 dfistparclr; - u32 dfistparlog; - u32 reserved12[(0x2f0 - 0x2e4) / 4]; - - u32 dfilpcfg0; - u32 reserved13[(0x300 - 0x2f4) / 4]; - u32 dfitrwrlvlresp0; - u32 dfitrwrlvlresp1; - u32 dfitrwrlvlresp2; - u32 dfitrrdlvlresp0; - u32 dfitrrdlvlresp1; - u32 dfitrrdlvlresp2; - u32 dfitrwrlvldelay0; - u32 dfitrwrlvldelay1; - u32 dfitrwrlvldelay2; - u32 dfitrrdlvldelay0; - u32 dfitrrdlvldelay1; - u32 dfitrrdlvldelay2; - u32 dfitrrdlvlgatedelay0; - u32 dfitrrdlvlgatedelay1; - u32 dfitrrdlvlgatedelay2; - u32 dfitrcmd; - u32 reserved14[(0x3f8 - 0x340) / 4]; - u32 ipvr; - u32 iptr; -}; -check_member(rk322x_ddr_pctl, iptr, 0x03fc); - -struct rk322x_ddr_phy { - u32 ddrphy_reg[0x100]; -}; - -struct rk322x_pctl_timing { - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; - u32 trefi_mem_ddr3; -}; - -struct rk322x_phy_timing { - u32 mr[4]; - u32 mr11; - u32 bl; - u32 cl_al; -}; - -struct rk322x_msch_timings { - u32 ddrtiming; - u32 ddrmode; - u32 readlatency; - u32 activate; - u32 devtodev; -}; - -struct rk322x_service_sys { - u32 id_coreid; - u32 id_revisionid; - u32 ddrconf; - u32 ddrtiming; - u32 ddrmode; - u32 readlatency; - u32 activate; - u32 devtodev; -}; - -struct rk322x_base_params { - struct rk322x_msch_timings noc_timing; - u32 ddrconfig; - u32 ddr_freq; - u32 dramtype; - /* - * unused for rk322x - */ - u32 stride; - u32 odt; -}; - -/* PCT_DFISTCFG0 */ -#define DFI_INIT_START BIT(0) -#define DFI_DATA_BYTE_DISABLE_EN BIT(2) - -/* PCT_DFISTCFG1 */ -#define DFI_DRAM_CLK_SR_EN BIT(0) -#define DFI_DRAM_CLK_DPD_EN BIT(1) - -/* PCT_DFISTCFG2 */ -#define DFI_PARITY_INTR_EN BIT(0) -#define DFI_PARITY_EN BIT(1) - -/* PCT_DFILPCFG0 */ -#define TLP_RESP_TIME_SHIFT 16 -#define LP_SR_EN BIT(8) -#define LP_PD_EN BIT(0) - -/* PCT_DFITCTRLDELAY */ -#define TCTRL_DELAY_TIME_SHIFT 0 - -/* PCT_DFITPHYWRDATA */ -#define TPHY_WRDATA_TIME_SHIFT 0 - -/* PCT_DFITPHYRDLAT */ -#define TPHY_RDLAT_TIME_SHIFT 0 - -/* PCT_DFITDRAMCLKDIS */ -#define TDRAM_CLK_DIS_TIME_SHIFT 0 - -/* PCT_DFITDRAMCLKEN */ -#define TDRAM_CLK_EN_TIME_SHIFT 0 - -/* PCTL_DFIODTCFG */ -#define RANK0_ODT_WRITE_SEL BIT(3) -#define RANK1_ODT_WRITE_SEL BIT(11) - -/* PCTL_DFIODTCFG1 */ -#define ODT_LEN_BL8_W_SHIFT 16 - -/* PUBL_ACDLLCR */ -#define ACDLLCR_DLLDIS BIT(31) -#define ACDLLCR_DLLSRST BIT(30) - -/* PUBL_DXDLLCR */ -#define DXDLLCR_DLLDIS BIT(31) -#define DXDLLCR_DLLSRST BIT(30) - -/* PUBL_DLLGCR */ -#define DLLGCR_SBIAS BIT(30) - -/* PUBL_DXGCR */ -#define DQSRTT BIT(9) -#define DQRTT BIT(10) - -/* PIR */ -#define PIR_INIT BIT(0) -#define PIR_DLLSRST BIT(1) -#define PIR_DLLLOCK BIT(2) -#define PIR_ZCAL BIT(3) -#define PIR_ITMSRST BIT(4) -#define PIR_DRAMRST BIT(5) -#define PIR_DRAMINIT BIT(6) -#define PIR_QSTRN BIT(7) -#define PIR_RVTRN BIT(8) -#define PIR_ICPC BIT(16) -#define PIR_DLLBYP BIT(17) -#define PIR_CTLDINIT BIT(18) -#define PIR_CLRSR BIT(28) -#define PIR_LOCKBYP BIT(29) -#define PIR_ZCALBYP BIT(30) -#define PIR_INITBYP BIT(31) - -/* PGCR */ -#define PGCR_DFTLMT_SHIFT 3 -#define PGCR_DFTCMP_SHIFT 2 -#define PGCR_DQSCFG_SHIFT 1 -#define PGCR_ITMDMD_SHIFT 0 - -/* PGSR */ -#define PGSR_IDONE BIT(0) -#define PGSR_DLDONE BIT(1) -#define PGSR_ZCDONE BIT(2) -#define PGSR_DIDONE BIT(3) -#define PGSR_DTDONE BIT(4) -#define PGSR_DTERR BIT(5) -#define PGSR_DTIERR BIT(6) -#define PGSR_DFTERR BIT(7) -#define PGSR_RVERR BIT(8) -#define PGSR_RVEIRR BIT(9) - -/* PTR0 */ -#define PRT_ITMSRST_SHIFT 18 -#define PRT_DLLLOCK_SHIFT 6 -#define PRT_DLLSRST_SHIFT 0 - -/* PTR1 */ -#define PRT_DINIT0_SHIFT 0 -#define PRT_DINIT1_SHIFT 19 - -/* PTR2 */ -#define PRT_DINIT2_SHIFT 0 -#define PRT_DINIT3_SHIFT 17 - -/* DCR */ -#define DDRMD_LPDDR 0 -#define DDRMD_DDR 1 -#define DDRMD_DDR2 2 -#define DDRMD_DDR3 3 -#define DDRMD_LPDDR2_LPDDR3 4 -#define DDRMD_MASK 7 -#define DDRMD_SHIFT 0 -#define PDQ_MASK 7 -#define PDQ_SHIFT 4 - -/* DXCCR */ -#define DQSNRES_MASK 0xf -#define DQSNRES_SHIFT 8 -#define DQSRES_MASK 0xf -#define DQSRES_SHIFT 4 - -/* DTPR */ -#define TDQSCKMAX_SHIFT 27 -#define TDQSCKMAX_MASK 7 -#define TDQSCK_SHIFT 24 -#define TDQSCK_MASK 7 - -/* DSGCR */ -#define DQSGX_SHIFT 5 -#define DQSGX_MASK 7 -#define DQSGE_SHIFT 8 -#define DQSGE_MASK 7 - -/* SCTL */ -#define INIT_STATE 0 -#define CFG_STATE 1 -#define GO_STATE 2 -#define SLEEP_STATE 3 -#define WAKEUP_STATE 4 - -/* STAT */ -#define LP_TRIG_SHIFT 4 -#define LP_TRIG_MASK 7 -#define PCTL_STAT_MASK 7 -#define INIT_MEM 0 -#define CONFIG 1 -#define CONFIG_REQ 2 -#define ACCESS 3 -#define ACCESS_REQ 4 -#define LOW_POWER 5 -#define LOW_POWER_ENTRY_REQ 6 -#define LOW_POWER_EXIT_REQ 7 - -/* ZQCR*/ -#define PD_OUTPUT_SHIFT 0 -#define PU_OUTPUT_SHIFT 5 -#define PD_ONDIE_SHIFT 10 -#define PU_ONDIE_SHIFT 15 -#define ZDEN_SHIFT 28 - -/* DDLGCR */ -#define SBIAS_BYPASS BIT(23) - -/* MCFG */ -#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 -#define PD_IDLE_SHIFT 8 -#define MDDR_EN (2 << 22) -#define LPDDR2_EN (3 << 22) -#define LPDDR3_EN (1 << 22) -#define DDR2_EN (0 << 5) -#define DDR3_EN (1 << 5) -#define LPDDR2_S2 (0 << 6) -#define LPDDR2_S4 (1 << 6) -#define MDDR_LPDDR2_BL_2 (0 << 20) -#define MDDR_LPDDR2_BL_4 (1 << 20) -#define MDDR_LPDDR2_BL_8 (2 << 20) -#define MDDR_LPDDR2_BL_16 (3 << 20) -#define DDR2_DDR3_BL_4 0 -#define DDR2_DDR3_BL_8 1 -#define TFAW_SHIFT 18 -#define PD_EXIT_SLOW (0 << 17) -#define PD_EXIT_FAST (1 << 17) -#define PD_TYPE_SHIFT 16 -#define BURSTLENGTH_SHIFT 20 - -/* POWCTL */ -#define POWER_UP_START BIT(0) - -/* POWSTAT */ -#define POWER_UP_DONE BIT(0) - -/* MCMD */ -enum { - DESELECT_CMD = 0, - PREA_CMD, - REF_CMD, - MRS_CMD, - ZQCS_CMD, - ZQCL_CMD, - RSTL_CMD, - MRR_CMD = 8, - DPDE_CMD, -}; - -#define BANK_ADDR_MASK 7 -#define BANK_ADDR_SHIFT 17 -#define CMD_ADDR_MASK 0x1fff -#define CMD_ADDR_SHIFT 4 - -#define LPDDR23_MA_SHIFT 4 -#define LPDDR23_MA_MASK 0xff -#define LPDDR23_OP_SHIFT 12 -#define LPDDR23_OP_MASK 0xff - -#define START_CMD (1u << 31) - -/* DDRPHY REG */ -enum { - /* DDRPHY_REG0 */ - SOFT_RESET_MASK = 3, - SOFT_DERESET_ANALOG = 1 << 2, - SOFT_DERESET_DIGITAL = 1 << 3, - SOFT_RESET_SHIFT = 2, - - /* DDRPHY REG1 */ - PHY_DDR3 = 0, - PHY_DDR2 = 1, - PHY_LPDDR3 = 2, - PHY_LPDDR2 = 3, - - PHT_BL_8 = 1 << 2, - PHY_BL_4 = 0 << 2, - - /* DDRPHY_REG2 */ - MEMORY_SELECT_DDR3 = 0 << 0, - MEMORY_SELECT_LPDDR3 = 2 << 0, - MEMORY_SELECT_LPDDR2 = 3 << 0, - DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4, - DQS_SQU_CAL_SEL_CS1 = 1 << 4, - DQS_SQU_CAL_SEL_CS0 = 2 << 4, - DQS_SQU_CAL_NORMAL_MODE = 0 << 1, - DQS_SQU_CAL_BYPASS_MODE = 1 << 1, - DQS_SQU_CAL_START = 1 << 0, - DQS_SQU_NO_CAL = 0 << 0, -}; - -/* CK pull up/down driver strength control */ -enum { - PHY_RON_RTT_DISABLE = 0, - PHY_RON_RTT_451OHM = 1, - PHY_RON_RTT_225OHM, - PHY_RON_RTT_150OHM, - PHY_RON_RTT_112OHM, - PHY_RON_RTT_90OHM, - PHY_RON_RTT_75OHM, - PHY_RON_RTT_64OHM = 7, - - PHY_RON_RTT_56OHM = 16, - PHY_RON_RTT_50OHM, - PHY_RON_RTT_45OHM, - PHY_RON_RTT_41OHM, - PHY_RON_RTT_37OHM, - PHY_RON_RTT_34OHM, - PHY_RON_RTT_33OHM, - PHY_RON_RTT_30OHM = 23, - - PHY_RON_RTT_28OHM = 24, - PHY_RON_RTT_26OHM, - PHY_RON_RTT_25OHM, - PHY_RON_RTT_23OHM, - PHY_RON_RTT_22OHM, - PHY_RON_RTT_21OHM, - PHY_RON_RTT_20OHM, - PHY_RON_RTT_19OHM = 31, -}; - -/* DQS squelch DLL delay */ -enum { - DQS_DLL_NO_DELAY = 0, - DQS_DLL_22P5_DELAY, - DQS_DLL_45_DELAY, - DQS_DLL_67P5_DELAY, - DQS_DLL_90_DELAY, - DQS_DLL_112P5_DELAY, - DQS_DLL_135_DELAY, - DQS_DLL_157P5_DELAY, -}; - -/* GRF_SOC_CON0 */ -#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0)) -#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0)) -#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7)) -#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7)) - -#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8)) -#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8)) - -#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6)) -#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6)) - -#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n)) -#define DDR3_DLL_RESET (1 << 8) - -#endif /* _ASM_ARCH_SDRAM_RK322X_H */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h deleted file mode 100644 index 11411ea..0000000 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_SDRAM_RK3328_H -#define _ASM_ARCH_SDRAM_RK3328_H - -#define SR_IDLE 93 -#define PD_IDLE 13 -#define SDRAM_ADDR 0x00000000 -#define PATTERN (0x5aa5f00f) - -/* ddr pctl registers define */ -#define DDR_PCTL2_MSTR 0x0 -#define DDR_PCTL2_STAT 0x4 -#define DDR_PCTL2_MSTR1 0x8 -#define DDR_PCTL2_MRCTRL0 0x10 -#define DDR_PCTL2_MRCTRL1 0x14 -#define DDR_PCTL2_MRSTAT 0x18 -#define DDR_PCTL2_MRCTRL2 0x1c -#define DDR_PCTL2_DERATEEN 0x20 -#define DDR_PCTL2_DERATEINT 0x24 -#define DDR_PCTL2_PWRCTL 0x30 -#define DDR_PCTL2_PWRTMG 0x34 -#define DDR_PCTL2_HWLPCTL 0x38 -#define DDR_PCTL2_RFSHCTL0 0x50 -#define DDR_PCTL2_RFSHCTL1 0x54 -#define DDR_PCTL2_RFSHCTL2 0x58 -#define DDR_PCTL2_RFSHCTL4 0x5c -#define DDR_PCTL2_RFSHCTL3 0x60 -#define DDR_PCTL2_RFSHTMG 0x64 -#define DDR_PCTL2_RFSHTMG1 0x68 -#define DDR_PCTL2_RFSHCTL5 0x6c -#define DDR_PCTL2_INIT0 0xd0 -#define DDR_PCTL2_INIT1 0xd4 -#define DDR_PCTL2_INIT2 0xd8 -#define DDR_PCTL2_INIT3 0xdc -#define DDR_PCTL2_INIT4 0xe0 -#define DDR_PCTL2_INIT5 0xe4 -#define DDR_PCTL2_INIT6 0xe8 -#define DDR_PCTL2_INIT7 0xec -#define DDR_PCTL2_DIMMCTL 0xf0 -#define DDR_PCTL2_RANKCTL 0xf4 -#define DDR_PCTL2_CHCTL 0xfc -#define DDR_PCTL2_DRAMTMG0 0x100 -#define DDR_PCTL2_DRAMTMG1 0x104 -#define DDR_PCTL2_DRAMTMG2 0x108 -#define DDR_PCTL2_DRAMTMG3 0x10c -#define DDR_PCTL2_DRAMTMG4 0x110 -#define DDR_PCTL2_DRAMTMG5 0x114 -#define DDR_PCTL2_DRAMTMG6 0x118 -#define DDR_PCTL2_DRAMTMG7 0x11c -#define DDR_PCTL2_DRAMTMG8 0x120 -#define DDR_PCTL2_DRAMTMG9 0x124 -#define DDR_PCTL2_DRAMTMG10 0x128 -#define DDR_PCTL2_DRAMTMG11 0x12c -#define DDR_PCTL2_DRAMTMG12 0x130 -#define DDR_PCTL2_DRAMTMG13 0x134 -#define DDR_PCTL2_DRAMTMG14 0x138 -#define DDR_PCTL2_DRAMTMG15 0x13c -#define DDR_PCTL2_DRAMTMG16 0x140 -#define DDR_PCTL2_ZQCTL0 0x180 -#define DDR_PCTL2_ZQCTL1 0x184 -#define DDR_PCTL2_ZQCTL2 0x188 -#define DDR_PCTL2_ZQSTAT 0x18c -#define DDR_PCTL2_DFITMG0 0x190 -#define DDR_PCTL2_DFITMG1 0x194 -#define DDR_PCTL2_DFILPCFG0 0x198 -#define DDR_PCTL2_DFILPCFG1 0x19c -#define DDR_PCTL2_DFIUPD0 0x1a0 -#define DDR_PCTL2_DFIUPD1 0x1a4 -#define DDR_PCTL2_DFIUPD2 0x1a8 -#define DDR_PCTL2_DFIMISC 0x1b0 -#define DDR_PCTL2_DFITMG2 0x1b4 -#define DDR_PCTL2_DFITMG3 0x1b8 -#define DDR_PCTL2_DFISTAT 0x1bc -#define DDR_PCTL2_DBICTL 0x1c0 -#define DDR_PCTL2_ADDRMAP0 0x200 -#define DDR_PCTL2_ADDRMAP1 0x204 -#define DDR_PCTL2_ADDRMAP2 0x208 -#define DDR_PCTL2_ADDRMAP3 0x20c -#define DDR_PCTL2_ADDRMAP4 0x210 -#define DDR_PCTL2_ADDRMAP5 0x214 -#define DDR_PCTL2_ADDRMAP6 0x218 -#define DDR_PCTL2_ADDRMAP7 0x21c -#define DDR_PCTL2_ADDRMAP8 0x220 -#define DDR_PCTL2_ADDRMAP9 0x224 -#define DDR_PCTL2_ADDRMAP10 0x228 -#define DDR_PCTL2_ADDRMAP11 0x22c -#define DDR_PCTL2_ODTCFG 0x240 -#define DDR_PCTL2_ODTMAP 0x244 -#define DDR_PCTL2_SCHED 0x250 -#define DDR_PCTL2_SCHED1 0x254 -#define DDR_PCTL2_PERFHPR1 0x25c -#define DDR_PCTL2_PERFLPR1 0x264 -#define DDR_PCTL2_PERFWR1 0x26c -#define DDR_PCTL2_DQMAP0 0x280 -#define DDR_PCTL2_DQMAP1 0x284 -#define DDR_PCTL2_DQMAP2 0x288 -#define DDR_PCTL2_DQMAP3 0x28c -#define DDR_PCTL2_DQMAP4 0x290 -#define DDR_PCTL2_DQMAP5 0x294 -#define DDR_PCTL2_DBG0 0x300 -#define DDR_PCTL2_DBG1 0x304 -#define DDR_PCTL2_DBGCAM 0x308 -#define DDR_PCTL2_DBGCMD 0x30c -#define DDR_PCTL2_DBGSTAT 0x310 -#define DDR_PCTL2_SWCTL 0x320 -#define DDR_PCTL2_SWSTAT 0x324 -#define DDR_PCTL2_POISONCFG 0x36c -#define DDR_PCTL2_POISONSTAT 0x370 -#define DDR_PCTL2_ADVECCINDEX 0x374 -#define DDR_PCTL2_ADVECCSTAT 0x378 -#define DDR_PCTL2_PSTAT 0x3fc -#define DDR_PCTL2_PCCFG 0x400 -#define DDR_PCTL2_PCFGR_n 0x404 -#define DDR_PCTL2_PCFGW_n 0x408 -#define DDR_PCTL2_PCTRL_n 0x490 - -/* PCTL2_MRSTAT */ -#define MR_WR_BUSY BIT(0) - -/* PHY_REG0 */ -#define DIGITAL_DERESET BIT(3) -#define ANALOG_DERESET BIT(2) -#define DIGITAL_RESET (0 << 3) -#define ANALOG_RESET (0 << 2) - -/* PHY_REG1 */ -#define PHY_DDR2 (0) -#define PHY_LPDDR2 (1) -#define PHY_DDR3 (2) -#define PHY_LPDDR3 (3) -#define PHY_DDR4 (4) -#define PHY_BL_4 (0 << 2) -#define PHY_BL_8 BIT(2) - -/* PHY_REG2 */ -#define PHY_DTT_EN BIT(0) -#define PHY_DTT_DISB (0 << 0) -#define PHY_WRITE_LEVELING_EN BIT(2) -#define PHY_WRITE_LEVELING_DISB (0 << 2) -#define PHY_SELECT_CS0 (2) -#define PHY_SELECT_CS1 (1) -#define PHY_SELECT_CS0_1 (0) -#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6) -#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4) - -#define PHY_DDR3_RON_RTT_DISABLE (0) -#define PHY_DDR3_RON_RTT_451ohm (1) -#define PHY_DDR3_RON_RTT_225ohm (2) -#define PHY_DDR3_RON_RTT_150ohm (3) -#define PHY_DDR3_RON_RTT_112ohm (4) -#define PHY_DDR3_RON_RTT_90ohm (5) -#define PHY_DDR3_RON_RTT_75ohm (6) -#define PHY_DDR3_RON_RTT_64ohm (7) -#define PHY_DDR3_RON_RTT_56ohm (16) -#define PHY_DDR3_RON_RTT_50ohm (17) -#define PHY_DDR3_RON_RTT_45ohm (18) -#define PHY_DDR3_RON_RTT_41ohm (19) -#define PHY_DDR3_RON_RTT_37ohm (20) -#define PHY_DDR3_RON_RTT_34ohm (21) -#define PHY_DDR3_RON_RTT_33ohm (22) -#define PHY_DDR3_RON_RTT_30ohm (23) -#define PHY_DDR3_RON_RTT_28ohm (24) -#define PHY_DDR3_RON_RTT_26ohm (25) -#define PHY_DDR3_RON_RTT_25ohm (26) -#define PHY_DDR3_RON_RTT_23ohm (27) -#define PHY_DDR3_RON_RTT_22ohm (28) -#define PHY_DDR3_RON_RTT_21ohm (29) -#define PHY_DDR3_RON_RTT_20ohm (30) -#define PHY_DDR3_RON_RTT_19ohm (31) - -#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) -#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) -#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) -#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) -#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) -#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) -#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) -#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) -#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) -#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) -#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) -#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) -#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) -#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) -#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) -#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) -#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) -#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) -#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) -#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) -#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) -#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) -#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) -#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) - -/* noc registers define */ -#define DDRCONF 0x8 -#define DDRTIMING 0xc -#define DDRMODE 0x10 -#define READLATENCY 0x14 -#define AGING0 0x18 -#define AGING1 0x1c -#define AGING2 0x20 -#define AGING3 0x24 -#define AGING4 0x28 -#define AGING5 0x2c -#define ACTIVATE 0x38 -#define DEVTODEV 0x3c -#define DDR4TIMING 0x40 - -/* DDR GRF */ -#define DDR_GRF_CON(n) (0 + (n) * 4) -#define DDR_GRF_STATUS_BASE (0X100) -#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) - -/* CRU_SOFTRESET_CON5 */ -#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15)) -#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14)) -#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13)) -#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12)) -#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11)) -#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9)) -#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8)) -#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7)) -/* CRU_SOFTRESET_CON9 */ -#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9)) - -/* CRU register */ -#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) -#define CRU_MODE (0x80) -#define CRU_GLB_CNT_TH (0x90) -#define CRU_CLKSEL_CON_BASE 0x100 -#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) -#define CRU_CLKGATE_CON_BASE 0x200 -#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) -#define CRU_CLKSFTRST_CON_BASE 0x300 -#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) - -/* CRU_PLL_CON0 */ -#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) -#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) -#define FBDIV(n) ((0xFFF << 16) | (n)) - -/* CRU_PLL_CON1 */ -#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) -#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) -#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) -#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) -#define LOCK(n) (((n) >> 10) & 0x1) -#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) -#define REFDIV(n) ((0x3F << 16) | (n)) - -union noc_ddrtiming { - u32 d32; - struct { - unsigned acttoact:6; - unsigned rdtomiss:6; - unsigned wrtomiss:6; - unsigned burstlen:3; - unsigned rdtowr:5; - unsigned wrtord:5; - unsigned bwratio:1; - } b; -} NOC_TIMING_T; - -union noc_activate { - u32 d32; - struct { - unsigned rrd:4; - unsigned faw:6; - unsigned fawbank:1; - unsigned reserved1:21; - } b; -}; - -union noc_devtodev { - u32 d32; - struct { - unsigned busrdtord:2; - unsigned busrdtowr:2; - unsigned buswrtord:2; - unsigned reserved2:26; - } b; -}; - -union noc_ddr4timing { - u32 d32; - struct { - unsigned ccdl:3; - unsigned wrtordl:5; - unsigned rrdl:4; - unsigned reserved2:20; - } b; -}; - -union noc_ddrmode { - u32 d32; - struct { - unsigned autoprecharge:1; - unsigned bwratioextended:1; - unsigned reserved3:30; - } b; -}; - -u32 addrmap[21][9] = { - /* map0 map1 map2 map3 map4 map5 map6 map7 map8 */ - {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, - 0x06060606, 0x00000f0f, 0x3f3f}, - {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, - 0x07070707, 0x00000f0f, 0x3f3f}, - {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, - 0x0f080808, 0x00000f0f, 0x3f3f}, - {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, - 0x08080808, 0x00000f0f, 0x3f3f}, - {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, - 0x0f090909, 0x00000f0f, 0x3f3f}, - {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707, - 0x07070707, 0x00000f0f, 0x3f3f}, - {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808, - 0x08080808, 0x00000f0f, 0x3f3f}, - {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909, - 0x0f090909, 0x00000f0f, 0x3f3f}, - {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, - 0x06060606, 0x00000f0f, 0x3f3f}, - {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, - 0x0f070707, 0x00000f0f, 0x3f3f}, - - {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, - 0x08080808, 0x00000f0f, 0x0801}, - {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, - 0x0f080808, 0x00000f0f, 0x0801}, - {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, - 0x07070707, 0x00000f07, 0x0700}, - {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, - 0x07070707, 0x00000f0f, 0x0700}, - {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, - 0x07070707, 0x00000f07, 0x3f01}, - {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, - 0x07070707, 0x00000f0f, 0x3f01}, - {24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, - 0x06060606, 0x00000f06, 0x3f00}, - {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909, - 0x0f090909, 0x00000f0f, 0x0801}, - {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808, - 0x08080808, 0x00000f0f, 0x0700}, - {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, - 0x08080808, 0x00000f0f, 0x3f01}, - - {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, - 0x07070707, 0x00000f07, 0x3f00} -}; - -struct rk3328_msch_timings { - union noc_ddrtiming ddrtiming; - union noc_ddrmode ddrmode; - u32 readlatency; - union noc_activate activate; - union noc_devtodev devtodev; - union noc_ddr4timing ddr4timing; - u32 agingx0; -}; - -struct rk3328_msch_regs { - u32 coreid; - u32 revisionid; - u32 ddrconf; - u32 ddrtiming; - u32 ddrmode; - u32 readlatency; - u32 aging0; - u32 aging1; - u32 aging2; - u32 aging3; - u32 aging4; - u32 aging5; - u32 reserved[2]; - u32 activate; - u32 devtodev; - u32 ddr4_timing; -}; - -struct rk3328_ddr_grf_regs { - u32 ddr_grf_con[4]; - u32 reserved[(0x100 - 0x10) / 4]; - u32 ddr_grf_status[11]; -}; - -struct rk3328_ddr_pctl_regs { - u32 pctl[30][2]; -}; - -struct rk3328_ddr_phy_regs { - u32 phy[5][2]; -}; - -struct rk3328_ddr_skew { - u32 a0_a1_skew[15]; - u32 cs0_dm0_skew[11]; - u32 cs0_dm1_skew[11]; - u32 cs0_dm2_skew[11]; - u32 cs0_dm3_skew[11]; - u32 cs1_dm0_skew[11]; - u32 cs1_dm1_skew[11]; - u32 cs1_dm2_skew[11]; - u32 cs1_dm3_skew[11]; -}; - -struct rk3328_sdram_channel { - unsigned int rank; - unsigned int col; - /* 3:8bank, 2:4bank */ - unsigned int bk; - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int bw; - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int dbw; - unsigned int row_3_4; - unsigned int cs0_row; - unsigned int cs1_row; - unsigned int ddrconfig; - struct rk3328_msch_timings noc_timings; -}; - -struct rk3328_sdram_params { - struct rk3328_sdram_channel ch; - unsigned int ddr_freq; - unsigned int dramtype; - unsigned int odt; - struct rk3328_ddr_pctl_regs pctl_regs; - struct rk3328_ddr_phy_regs phy_regs; - struct rk3328_ddr_skew skew; -}; - -#define PHY_REG(base, n) (base + 4 * (n)) - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h deleted file mode 100644 index dc65ae7..0000000 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd - */ - -#ifndef _ASM_ARCH_SDRAM_RK3399_H -#define _ASM_ARCH_SDRAM_RK3399_H - -struct rk3399_ddr_pctl_regs { - u32 denali_ctl[332]; -}; - -struct rk3399_ddr_publ_regs { - u32 denali_phy[959]; -}; - -struct rk3399_ddr_pi_regs { - u32 denali_pi[200]; -}; - -union noc_ddrtimingc0 { - u32 d32; - struct { - unsigned burstpenalty : 4; - unsigned reserved0 : 4; - unsigned wrtomwr : 6; - unsigned reserved1 : 18; - } b; -}; - -union noc_ddrmode { - u32 d32; - struct { - unsigned autoprecharge : 1; - unsigned bypassfiltering : 1; - unsigned fawbank : 1; - unsigned burstsize : 2; - unsigned mwrsize : 2; - unsigned reserved2 : 1; - unsigned forceorder : 8; - unsigned forceorderstate : 8; - unsigned reserved3 : 8; - } b; -}; - -struct rk3399_msch_regs { - u32 coreid; - u32 revisionid; - u32 ddrconf; - u32 ddrsize; - u32 ddrtiminga0; - u32 ddrtimingb0; - u32 ddrtimingc0; - u32 devtodev0; - u32 reserved0[(0x110 - 0x20) / 4]; - u32 ddrmode; - u32 reserved1[(0x1000 - 0x114) / 4]; - u32 agingx0; -}; - -struct rk3399_msch_timings { - u32 ddrtiminga0; - u32 ddrtimingb0; - union noc_ddrtimingc0 ddrtimingc0; - u32 devtodev0; - union noc_ddrmode ddrmode; - u32 agingx0; -}; - -struct rk3399_ddr_cic_regs { - u32 cic_ctrl0; - u32 cic_ctrl1; - u32 cic_idle_th; - u32 cic_cg_wait_th; - u32 cic_status0; - u32 cic_status1; - u32 cic_ctrl2; - u32 cic_ctrl3; - u32 cic_ctrl4; -}; - -/* DENALI_CTL_00 */ -#define START 1 - -/* DENALI_CTL_68 */ -#define PWRUP_SREFRESH_EXIT (1 << 16) - -/* DENALI_CTL_274 */ -#define MEM_RST_VALID 1 - -struct rk3399_sdram_channel { - struct sdram_cap_info cap_info; - struct rk3399_msch_timings noc_timings; -}; - -struct rk3399_sdram_params { - struct rk3399_sdram_channel ch[2]; - struct sdram_base_params base; - struct rk3399_ddr_pctl_regs pctl_regs; - struct rk3399_ddr_pi_regs pi_regs; - struct rk3399_ddr_publ_regs phy_regs; -}; - -#define PI_CA_TRAINING (1 << 0) -#define PI_WRITE_LEVELING (1 << 1) -#define PI_READ_GATE_TRAINING (1 << 2) -#define PI_READ_LEVELING (1 << 3) -#define PI_WDQ_LEVELING (1 << 4) -#define PI_FULL_TRAINING 0xff - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h deleted file mode 100644 index de5a8f1..0000000 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co.,Ltd - */ - -#ifndef _ASM_ARCH_SYS_PROTO_H -#define _ASM_ARCH_SYS_PROTO_H - -#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h deleted file mode 100644 index 77b5422..0000000 --- a/arch/arm/include/asm/arch-rockchip/timer.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_TIMER_H -#define __ASM_ARCH_TIMER_H - -struct rk_timer { - u32 timer_load_count0; - u32 timer_load_count1; - u32 timer_curr_value0; - u32 timer_curr_value1; - u32 timer_ctrl_reg; - u32 timer_int_status; -}; - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/uart.h b/arch/arm/include/asm/arch-rockchip/uart.h deleted file mode 100644 index feede5e..0000000 --- a/arch/arm/include/asm/arch-rockchip/uart.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_UART_H -#define __ASM_ARCH_UART_H -struct rk_uart { - unsigned int rbr; /* Receive buffer register. */ - unsigned int ier; /* Interrupt enable register. */ - unsigned int fcr; /* FIFO control register. */ - unsigned int lcr; /* Line control register. */ - unsigned int mcr; /* Modem control register. */ - unsigned int lsr; /* Line status register. */ - unsigned int msr; /* Modem status register. */ - unsigned int scr; - unsigned int reserved1[(0x30 - 0x20) / 4]; - unsigned int srbr[(0x70 - 0x30) / 4]; - unsigned int far; - unsigned int tfr; - unsigned int rfw; - unsigned int usr; - unsigned int tfl; - unsigned int rfl; - unsigned int srr; - unsigned int srts; - unsigned int sbcr; - unsigned int sdmam; - unsigned int sfe; - unsigned int srt; - unsigned int stet; - unsigned int htx; - unsigned int dmasa; - unsigned int reserver2[(0xf4 - 0xac) / 4]; - unsigned int cpr; - unsigned int ucv; - unsigned int ctr; -}; - -void rk_uart_init(void *base); -void print_hex(unsigned int n); -void print(char *s); -#endif diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h deleted file mode 100644 index 8398249..0000000 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ /dev/null @@ -1,361 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - * Copyright 2014 Rockchip Inc. - */ - -#ifndef _ASM_ARCH_VOP_RK3288_H -#define _ASM_ARCH_VOP_RK3288_H - -struct rk3288_vop { - u32 reg_cfg_done; - u32 version_info; - u32 sys_ctrl; - u32 sys_ctrl1; - u32 dsp_ctrl0; - u32 dsp_ctrl1; - u32 dsp_bg; - u32 mcu_ctrl; - u32 intr_ctrl0; - u32 intr_ctrl1; - u32 intr_reserved0; - u32 intr_reserved1; - - u32 win0_ctrl0; - u32 win0_ctrl1; - u32 win0_color_key; - u32 win0_vir; - u32 win0_yrgb_mst; - u32 win0_cbr_mst; - u32 win0_act_info; - u32 win0_dsp_info; - u32 win0_dsp_st; - u32 win0_scl_factor_yrgb; - u32 win0_scl_factor_cbr; - u32 win0_scl_offset; - u32 win0_src_alpha_ctrl; - u32 win0_dst_alpha_ctrl; - u32 win0_fading_ctrl; - u32 win0_reserved0; - - u32 win1_ctrl0; - u32 win1_ctrl1; - u32 win1_color_key; - u32 win1_vir; - u32 win1_yrgb_mst; - u32 win1_cbr_mst; - u32 win1_act_info; - u32 win1_dsp_info; - u32 win1_dsp_st; - u32 win1_scl_factor_yrgb; - u32 win1_scl_factor_cbr; - u32 win1_scl_offset; - u32 win1_src_alpha_ctrl; - u32 win1_dst_alpha_ctrl; - u32 win1_fading_ctrl; - u32 win1_reservd0; - u32 reserved2[48]; - u32 post_dsp_hact_info; - u32 post_dsp_vact_info; - u32 post_scl_factor_yrgb; - u32 post_reserved; - u32 post_scl_ctrl; - u32 post_dsp_vact_info_f1; - u32 dsp_htotal_hs_end; - u32 dsp_hact_st_end; - u32 dsp_vtotal_vs_end; - u32 dsp_vact_st_end; - u32 dsp_vs_st_end_f1; - u32 dsp_vact_st_end_f1; -}; -check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c); - -enum rockchip_fb_data_format_t { - ARGB8888 = 0, - RGB888 = 1, - RGB565 = 2, -}; - -enum { - LB_YUV_3840X5 = 0x0, - LB_YUV_2560X8 = 0x1, - LB_RGB_3840X2 = 0x2, - LB_RGB_2560X4 = 0x3, - LB_RGB_1920X5 = 0x4, - LB_RGB_1280X8 = 0x5 -}; - -enum vop_modes { - VOP_MODE_EDP = 0, - VOP_MODE_HDMI, - VOP_MODE_LVDS, - VOP_MODE_MIPI, - VOP_MODE_NONE, - VOP_MODE_AUTO_DETECT, - VOP_MODE_UNKNOWN, -}; - -/* VOP_VERSION_INFO */ -#define M_FPGA_VERSION (0xffff << 16) -#define M_RTL_VERSION (0xffff) - -/* VOP_SYS_CTRL */ -#define M_AUTO_GATING_EN (1 << 23) -#define M_STANDBY_EN (1 << 22) -#define M_DMA_STOP (1 << 21) -#define M_MMU_EN (1 << 20) -#define M_DAM_BURST_LENGTH (0x3 << 18) -#define M_MIPI_OUT_EN (1 << 15) -#define M_EDP_OUT_EN (1 << 14) -#define M_HDMI_OUT_EN (1 << 13) -#define M_RGB_OUT_EN (1 << 12) -#define M_ALL_OUT_EN \ - (M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN) -#define M_EDPI_WMS_FS (1 << 10) -#define M_EDPI_WMS_MODE (1 << 9) -#define M_EDPI_HALT_EN (1 << 8) -#define M_DOUB_CH_OVERLAP_NUM (0xf << 4) -#define M_DOUB_CHANNEL_EN (1 << 3) -#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1) -#define M_DIRECT_PATH_EN (1) - -#define V_AUTO_GATING_EN(x) (((x) & 1) << 23) -#define V_STANDBY_EN(x) (((x) & 1) << 22) -#define V_DMA_STOP(x) (((x) & 1) << 21) -#define V_MMU_EN(x) (((x) & 1) << 20) -#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) -#define V_MIPI_OUT_EN(x) (((x) & 1) << 15) -#define V_EDP_OUT_EN(x) (((x) & 1) << 14) -#define V_HDMI_OUT_EN(x) (((x) & 1) << 13) -#define V_RGB_OUT_EN(x) (((x) & 1) << 12) -#define V_EDPI_WMS_FS(x) (((x) & 1) << 10) -#define V_EDPI_WMS_MODE(x) (((x) & 1) << 9) -#define V_EDPI_HALT_EN(x) (((x)&1)<<8) -#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4) -#define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3) -#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1) -#define V_DIRECT_PATH_EN(x) ((x) & 1) - -/* VOP_SYS_CTRL1 */ -#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13) -#define M_AXI_MAX_OUTSTANDING_EN (1 << 12) -#define M_NOC_WIN_QOS (3 << 10) -#define M_NOC_QOS_EN (1 << 9) -#define M_NOC_HURRY_THRESHOLD (0x3f << 3) -#define M_NOC_HURRY_VALUE (0x3 << 1) -#define M_NOC_HURRY_EN (1) - -#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13) -#define V_AXI_MAX_OUTSTANDING_EN(x) (((x) & 1) << 12) -#define V_NOC_WIN_QOS(x) (((x) & 3) << 10) -#define V_NOC_QOS_EN(x) (((x) & 1) << 9) -#define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3) -#define V_NOC_HURRY_VALUE(x) (((x) & 3) << 1) -#define V_NOC_HURRY_EN(x) ((x) & 1) - -/* VOP_DSP_CTRL0 */ -#define M_DSP_Y_MIR_EN (1 << 23) -#define M_DSP_X_MIR_EN (1 << 22) -#define M_DSP_YUV_CLIP (1 << 21) -#define M_DSP_CCIR656_AVG (1 << 20) -#define M_DSP_BLACK_EN (1 << 19) -#define M_DSP_BLANK_EN (1 << 18) -#define M_DSP_OUT_ZERO (1 << 17) -#define M_DSP_DUMMY_SWAP (1 << 16) -#define M_DSP_DELTA_SWAP (1 << 15) -#define M_DSP_RG_SWAP (1 << 14) -#define M_DSP_RB_SWAP (1 << 13) -#define M_DSP_BG_SWAP (1 << 12) -#define M_DSP_FIELD_POL (1 << 11) -#define M_DSP_INTERLACE (1 << 10) -#define M_DSP_DDR_PHASE (1 << 9) -#define M_DSP_DCLK_DDR (1 << 8) -#define M_DSP_DCLK_POL (1 << 7) -#define M_DSP_DEN_POL (1 << 6) -#define M_DSP_VSYNC_POL (1 << 5) -#define M_DSP_HSYNC_POL (1 << 4) -#define M_DSP_OUT_MODE (0xf) - -#define V_DSP_Y_MIR_EN(x) (((x) & 1) << 23) -#define V_DSP_X_MIR_EN(x) (((x) & 1) << 22) -#define V_DSP_YUV_CLIP(x) (((x) & 1) << 21) -#define V_DSP_CCIR656_AVG(x) (((x) & 1) << 20) -#define V_DSP_BLACK_EN(x) (((x) & 1) << 19) -#define V_DSP_BLANK_EN(x) (((x) & 1) << 18) -#define V_DSP_OUT_ZERO(x) (((x) & 1) << 17) -#define V_DSP_DUMMY_SWAP(x) (((x) & 1) << 16) -#define V_DSP_DELTA_SWAP(x) (((x) & 1) << 15) -#define V_DSP_RG_SWAP(x) (((x) & 1) << 14) -#define V_DSP_RB_SWAP(x) (((x) & 1) << 13) -#define V_DSP_BG_SWAP(x) (((x) & 1) << 12) -#define V_DSP_FIELD_POL(x) (((x) & 1) << 11) -#define V_DSP_INTERLACE(x) (((x) & 1) << 10) -#define V_DSP_DDR_PHASE(x) (((x) & 1) << 9) -#define V_DSP_DCLK_DDR(x) (((x) & 1) << 8) -#define V_DSP_DCLK_POL(x) (((x) & 1) << 7) -#define V_DSP_DEN_POL(x) (((x) & 1) << 6) -#define V_DSP_VSYNC_POL(x) (((x) & 1) << 5) -#define V_DSP_HSYNC_POL(x) (((x) & 1) << 4) -#define V_DSP_PIN_POL(x) (((x) & 0xf) << 4) -#define V_DSP_OUT_MODE(x) ((x) & 0xf) - -/* VOP_DSP_CTRL1 */ -#define V_RK3399_DSP_MIPI_POL(x) ((x) << 28) -#define V_RK3399_DSP_EDP_POL(x) ((x) << 24) -#define V_RK3399_DSP_HDMI_POL(x) ((x) << 20) -#define V_RK3399_DSP_LVDS_POL(x) ((x) << 16) - -#define M_RK3399_DSP_MIPI_POL (V_RK3399_DSP_MIPI_POL(0xf)) -#define M_RK3399_DSP_EDP_POL (V_RK3399_DSP_EDP_POL(0xf)) -#define M_RK3399_DSP_HDMI_POL (V_RK3399_DSP_HDMI_POL(0xf)) -#define M_RK3399_DSP_LVDS_POL (V_RK3399_DSP_LVDS_POL(0xf)) - -#define M_DSP_LAYER3_SEL (3 << 14) -#define M_DSP_LAYER2_SEL (3 << 12) -#define M_DSP_LAYER1_SEL (3 << 10) -#define M_DSP_LAYER0_SEL (3 << 8) -#define M_DITHER_UP_EN (1 << 6) -#define M_DITHER_DOWN_SEL (1 << 4) -#define M_DITHER_DOWN_MODE (1 << 3) -#define M_DITHER_DOWN_EN (1 << 2) -#define M_PRE_DITHER_DOWN_EN (1 << 1) -#define M_DSP_LUT_EN (1) - -#define V_DSP_LAYER3_SEL(x) (((x) & 3) << 14) -#define V_DSP_LAYER2_SEL(x) (((x) & 3) << 12) -#define V_DSP_LAYER1_SEL(x) (((x) & 3) << 10) -#define V_DSP_LAYER0_SEL(x) (((x) & 3) << 8) -#define V_DITHER_UP_EN(x) (((x) & 1) << 6) -#define V_DITHER_DOWN_SEL(x) (((x) & 1) << 4) -#define V_DITHER_DOWN_MODE(x) (((x) & 1) << 3) -#define V_DITHER_DOWN_EN(x) (((x) & 1) << 2) -#define V_PRE_DITHER_DOWN_EN(x) (((x) & 1) << 1) -#define V_DSP_LUT_EN(x) ((x)&1) - -/* VOP_DSP_BG */ -#define M_DSP_BG_RED (0x3f << 20) -#define M_DSP_BG_GREEN (0x3f << 10) -#define M_DSP_BG_BLUE (0x3f << 0) - -#define V_DSP_BG_RED(x) (((x) & 0x3f) << 20) -#define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10) -#define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0) - -/* VOP_WIN0_CTRL0 */ -#define M_WIN0_YUV_CLIP (1 << 20) -#define M_WIN0_CBR_DEFLICK (1 << 19) -#define M_WIN0_YRGB_DEFLICK (1 << 18) -#define M_WIN0_PPAS_ZERO_EN (1 << 16) -#define M_WIN0_UV_SWAP (1 << 15) -#define M_WIN0_MID_SWAP (1 << 14) -#define M_WIN0_ALPHA_SWAP (1 << 13) -#define M_WIN0_RB_SWAP (1 << 12) -#define M_WIN0_CSC_MODE (3 << 10) -#define M_WIN0_NO_OUTSTANDING (1 << 9) -#define M_WIN0_INTERLACE_READ (1 << 8) -#define M_WIN0_LB_MODE (7 << 5) -#define M_WIN0_FMT_10 (1 << 4) -#define M_WIN0_DATA_FMT (7 << 1) -#define M_WIN0_EN (1 << 0) - -#define V_WIN0_YUV_CLIP(x) (((x) & 1) << 20) -#define V_WIN0_CBR_DEFLICK(x) (((x) & 1) << 19) -#define V_WIN0_YRGB_DEFLICK(x) (((x) & 1) << 18) -#define V_WIN0_PPAS_ZERO_EN(x) (((x) & 1) << 16) -#define V_WIN0_UV_SWAP(x) (((x) & 1) << 15) -#define V_WIN0_MID_SWAP(x) (((x) & 1) << 14) -#define V_WIN0_ALPHA_SWAP(x) (((x) & 1) << 13) -#define V_WIN0_RB_SWAP(x) (((x) & 1) << 12) -#define V_WIN0_CSC_MODE(x) (((x) & 3) << 10) -#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9) -#define V_WIN0_INTERLACE_READ(x) (((x) & 1) << 8) -#define V_WIN0_LB_MODE(x) (((x) & 7) << 5) -#define V_WIN0_FMT_10(x) (((x) & 1) << 4) -#define V_WIN0_DATA_FMT(x) (((x) & 7) << 1) -#define V_WIN0_EN(x) ((x) & 1) - -/* VOP_WIN0_CTRL1 */ -#define M_WIN0_CBR_VSD_MODE (1 << 31) -#define M_WIN0_CBR_VSU_MODE (1 << 30) -#define M_WIN0_CBR_HSD_MODE (3 << 28) -#define M_WIN0_CBR_VER_SCL_MODE (3 << 26) -#define M_WIN0_CBR_HOR_SCL_MODE (3 << 24) -#define M_WIN0_YRGB_VSD_MODE (1 << 23) -#define M_WIN0_YRGB_VSU_MODE (1 << 22) -#define M_WIN0_YRGB_HSD_MODE (3 << 20) -#define M_WIN0_YRGB_VER_SCL_MODE (3 << 18) -#define M_WIN0_YRGB_HOR_SCL_MODE (3 << 16) -#define M_WIN0_LINE_LOAD_MODE (1 << 15) -#define M_WIN0_CBR_AXI_GATHER_NUM (7 << 12) -#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8) -#define M_WIN0_VSD_CBR_GT2 (1 << 7) -#define M_WIN0_VSD_CBR_GT4 (1 << 6) -#define M_WIN0_VSD_YRGB_GT2 (1 << 5) -#define M_WIN0_VSD_YRGB_GT4 (1 << 4) -#define M_WIN0_BIC_COE_SEL (3 << 2) -#define M_WIN0_CBR_AXI_GATHER_EN (1 << 1) -#define M_WIN0_YRGB_AXI_GATHER_EN (1) - -#define V_WIN0_CBR_VSD_MODE(x) (((x) & 1) << 31) -#define V_WIN0_CBR_VSU_MODE(x) (((x) & 1) << 30) -#define V_WIN0_CBR_HSD_MODE(x) (((x) & 3) << 28) -#define V_WIN0_CBR_VER_SCL_MODE(x) (((x) & 3) << 26) -#define V_WIN0_CBR_HOR_SCL_MODE(x) (((x) & 3) << 24) -#define V_WIN0_YRGB_VSD_MODE(x) (((x) & 1) << 23) -#define V_WIN0_YRGB_VSU_MODE(x) (((x) & 1) << 22) -#define V_WIN0_YRGB_HSD_MODE(x) (((x) & 3) << 20) -#define V_WIN0_YRGB_VER_SCL_MODE(x) (((x) & 3) << 18) -#define V_WIN0_YRGB_HOR_SCL_MODE(x) (((x) & 3) << 16) -#define V_WIN0_LINE_LOAD_MODE(x) (((x) & 1) << 15) -#define V_WIN0_CBR_AXI_GATHER_NUM(x) (((x) & 7) << 12) -#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8) -#define V_WIN0_VSD_CBR_GT2(x) (((x) & 1) << 7) -#define V_WIN0_VSD_CBR_GT4(x) (((x) & 1) << 6) -#define V_WIN0_VSD_YRGB_GT2(x) (((x) & 1) << 5) -#define V_WIN0_VSD_YRGB_GT4(x) (((x) & 1) << 4) -#define V_WIN0_BIC_COE_SEL(x) (((x) & 3) << 2) -#define V_WIN0_CBR_AXI_GATHER_EN(x) (((x) & 1) << 1) -#define V_WIN0_YRGB_AXI_GATHER_EN(x) ((x) & 1) - -/*VOP_WIN0_COLOR_KEY*/ -#define M_WIN0_KEY_EN (1 << 31) -#define M_WIN0_KEY_COLOR (0x3fffffff) - -#define V_WIN0_KEY_EN(x) (((x) & 1) << 31) -#define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff) - -/* VOP_WIN0_VIR */ -#define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0) -#define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0) -#define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0) -#define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0) - -/* VOP_WIN0_ACT_INFO */ -#define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16) -#define V_ACT_WIDTH(x) ((x) & 0x1fff) - -/* VOP_WIN0_DSP_INFO */ -#define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16) -#define V_DSP_WIDTH(x) ((x) & 0xfff) - -/* VOP_WIN0_DSP_ST */ -#define V_DSP_YST(x) (((x) & 0x1fff) << 16) -#define V_DSP_XST(x) ((x) & 0x1fff) - -/* VOP_WIN0_SCL_OFFSET */ -#define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24) -#define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16) -#define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8) -#define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff) - -#define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */ -#define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */ -#define V_VSYNC(x) (((x)&0x1fff)<<0) -#define V_VERPRD(x) (((x)&0x1fff)<<16) - -#define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */ -#define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */ -#define V_VAEP(x) (((x)&0x1fff)<<0) -#define V_VASP(x) (((x)&0x1fff)<<16) - -#endif diff --git a/arch/arm/include/asm/arch-rv1108/boot0.h b/arch/arm/include/asm/arch-rv1108/boot0.h deleted file mode 100644 index 2e78b07..0000000 --- a/arch/arm/include/asm/arch-rv1108/boot0.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_BOOT0_H__ -#define __ASM_ARCH_BOOT0_H__ - -#include <asm/arch-rockchip/boot0.h> - -#endif diff --git a/arch/arm/include/asm/arch-rv1108/gpio.h b/arch/arm/include/asm/arch-rv1108/gpio.h deleted file mode 100644 index eca79d5..0000000 --- a/arch/arm/include/asm/arch-rv1108/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#ifndef __ASM_ARCH_GPIO_H__ -#define __ASM_ARCH_GPIO_H__ - -#include <asm/arch-rockchip/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h deleted file mode 100644 index c600654..0000000 --- a/arch/arm/include/asm/arch-s32v234/clock.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_PERIPHERALS_CLK, - MXC_UART_CLK, - MXC_USDHC_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, -}; -enum pll_type { - ARM_PLL = 0, - PERIPH_PLL, - ENET_PLL, - DDR_PLL, - VIDEO_PLL, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -void clock_init(void); - -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h deleted file mode 100644 index 8c709af..0000000 --- a/arch/arm/include/asm/arch-s32v234/ddr.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__ -#define __ARCH_ARM_MACH_S32V234_DDR_H__ - -#define DDR0 0 -#define DDR1 1 - -/* DDR offset in MSCR register */ -#define _DDR0_RESET 168 -#define _DDR0_CLK0 169 -#define _DDR0_CAS 170 -#define _DDR0_RAS 171 -#define _DDR0_WE_B 172 -#define _DDR0_CKE0 173 -#define _DDR0_CKE1 174 -#define _DDR0_CS_B0 175 -#define _DDR0_CS_B1 176 -#define _DDR0_BA0 177 -#define _DDR0_BA1 178 -#define _DDR0_BA2 179 -#define _DDR0_A0 180 -#define _DDR0_A1 181 -#define _DDR0_A2 182 -#define _DDR0_A3 183 -#define _DDR0_A4 184 -#define _DDR0_A5 185 -#define _DDR0_A6 186 -#define _DDR0_A7 187 -#define _DDR0_A8 188 -#define _DDR0_A9 189 -#define _DDR0_A10 190 -#define _DDR0_A11 191 -#define _DDR0_A12 192 -#define _DDR0_A13 193 -#define _DDR0_A14 194 -#define _DDR0_A15 195 -#define _DDR0_DM0 196 -#define _DDR0_DM1 197 -#define _DDR0_DM2 198 -#define _DDR0_DM3 199 -#define _DDR0_DQS0 200 -#define _DDR0_DQS1 201 -#define _DDR0_DQS2 202 -#define _DDR0_DQS3 203 -#define _DDR0_D0 204 -#define _DDR0_D1 205 -#define _DDR0_D2 206 -#define _DDR0_D3 207 -#define _DDR0_D4 208 -#define _DDR0_D5 209 -#define _DDR0_D6 210 -#define _DDR0_D7 211 -#define _DDR0_D8 212 -#define _DDR0_D9 213 -#define _DDR0_D10 214 -#define _DDR0_D11 215 -#define _DDR0_D12 216 -#define _DDR0_D13 217 -#define _DDR0_D14 218 -#define _DDR0_D15 219 -#define _DDR0_D16 220 -#define _DDR0_D17 221 -#define _DDR0_D18 222 -#define _DDR0_D19 223 -#define _DDR0_D20 224 -#define _DDR0_D21 225 -#define _DDR0_D22 226 -#define _DDR0_D23 227 -#define _DDR0_D24 228 -#define _DDR0_D25 229 -#define _DDR0_D26 230 -#define _DDR0_D27 231 -#define _DDR0_D28 232 -#define _DDR0_D29 233 -#define _DDR0_D30 234 -#define _DDR0_D31 235 -#define _DDR0_ODT0 236 -#define _DDR0_ODT1 237 -#define _DDR0_ZQ 238 -#define _DDR1_RESET 239 -#define _DDR1_CLK0 240 -#define _DDR1_CAS 241 -#define _DDR1_RAS 242 -#define _DDR1_WE_B 243 -#define _DDR1_CKE0 244 -#define _DDR1_CKE1 245 -#define _DDR1_CS_B0 246 -#define _DDR1_CS_B1 247 -#define _DDR1_BA0 248 -#define _DDR1_BA1 249 -#define _DDR1_BA2 250 -#define _DDR1_A0 251 -#define _DDR1_A1 252 -#define _DDR1_A2 253 -#define _DDR1_A3 254 -#define _DDR1_A4 255 -#define _DDR1_A5 256 -#define _DDR1_A6 257 -#define _DDR1_A7 258 -#define _DDR1_A8 259 -#define _DDR1_A9 260 -#define _DDR1_A10 261 -#define _DDR1_A11 262 -#define _DDR1_A12 263 -#define _DDR1_A13 264 -#define _DDR1_A14 265 -#define _DDR1_A15 266 -#define _DDR1_DM0 267 -#define _DDR1_DM1 268 -#define _DDR1_DM2 269 -#define _DDR1_DM3 270 -#define _DDR1_DQS0 271 -#define _DDR1_DQS1 272 -#define _DDR1_DQS2 273 -#define _DDR1_DQS3 274 -#define _DDR1_D0 275 -#define _DDR1_D1 276 -#define _DDR1_D2 277 -#define _DDR1_D3 278 -#define _DDR1_D4 279 -#define _DDR1_D5 280 -#define _DDR1_D6 281 -#define _DDR1_D7 282 -#define _DDR1_D8 283 -#define _DDR1_D9 284 -#define _DDR1_D10 285 -#define _DDR1_D11 286 -#define _DDR1_D12 287 -#define _DDR1_D13 288 -#define _DDR1_D14 289 -#define _DDR1_D15 290 -#define _DDR1_D16 291 -#define _DDR1_D17 292 -#define _DDR1_D18 293 -#define _DDR1_D19 294 -#define _DDR1_D20 295 -#define _DDR1_D21 296 -#define _DDR1_D22 297 -#define _DDR1_D23 298 -#define _DDR1_D24 299 -#define _DDR1_D25 300 -#define _DDR1_D26 301 -#define _DDR1_D27 302 -#define _DDR1_D28 303 -#define _DDR1_D29 304 -#define _DDR1_D30 305 -#define _DDR1_D31 306 -#define _DDR1_ODT0 307 -#define _DDR1_ODT1 308 -#define _DDR1_ZQ 309 - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h deleted file mode 100644 index 9a779cc..0000000 --- a/arch/arm/include/asm/arch-s32v234/imx-regs.h +++ /dev/null @@ -1,328 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX_REGS_H__ -#define __ASM_ARCH_IMX_REGS_H__ - -#define ARCH_MXC - -#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */ -#define IRAM_SIZE 0x00400000 /* 4MB */ - -#define AIPS0_BASE_ADDR (0x40000000UL) -#define AIPS1_BASE_ADDR (0x40080000UL) - -/* AIPS 0 */ -#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000) -#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) -#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) -#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000) -#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) -#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) -#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) -#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) -#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000) -#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000) -#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000) -#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000) -#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) -#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) -#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) -#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) -#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) -#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) -#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) -#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) -#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000) -#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000) -#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000) -#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) -#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000) -#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) -#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000) -#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000) -#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000) -#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000) -#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000) -#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000) -#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000) -#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000) -#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000) -#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000) -#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000) -#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000) -#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) -#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000) -#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000) -#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) -#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000) -#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000) -#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000) -#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000) - -/* AIPS 1 */ -#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000) -#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000) -#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000) -#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000) -#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000) -#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000) -#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000) -#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000) -#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000) -#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000) -#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000) -#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000) -#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000) -#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000) -#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000) -#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000) -#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000) -#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000) -#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000) -#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000) -#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000) -#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000) -#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000) -#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000) -#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000) -#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000) -#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000) -#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000) -#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000) -#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000) -#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000) -#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000) -#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000) -#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000) -#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000) -#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000) -#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000) -#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000) -#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000) -#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000) -#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000) -#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000) -#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000) - -/* TODO Remove this after the IOMUX framework is implemented */ -#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR - -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - -#define FEC_QUIRK_ENET_MAC -#define I2C_QUIRK_REG - -/* MSCM interrupt router */ -#define MSCM_IRSPRC_CPn_EN 3 -#define MSCM_IRSPRC_NUM 176 -#define MSCM_CPXTYPE_RYPZ_MASK 0xFF -#define MSCM_CPXTYPE_RYPZ_OFFSET 0 -#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00 -#define MSCM_CPXTYPE_PERS_OFFSET 8 -#define MSCM_CPXTYPE_PERS_A53 0x413533 -#define MSCM_CPXTYPE_PERS_CM4 0x434d34 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* System Reset Controller (SRC) */ -struct src { - u32 bmr1; - u32 bmr2; - u32 gpr1_boot; - u32 reserved_0x00C[61]; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 reserved_0x11C[1]; - u32 gpr9; - u32 gpr10; - u32 gpr11; - u32 gpr12; - u32 gpr13; - u32 gpr14; - u32 gpr15; - u32 gpr16; - u32 reserved_0x140[1]; - u32 gpr17; - u32 gpr18; - u32 gpr19; - u32 gpr20; - u32 gpr21; - u32 gpr22; - u32 gpr23; - u32 gpr24; - u32 gpr25; - u32 gpr26; - u32 gpr27; - u32 reserved_0x16C[5]; - u32 pcie_config1; - u32 ddr_self_ref_ctrl; - u32 pcie_config0; - u32 reserved_0x18C[4]; - u32 soc_misc_config2; -}; - -/* SRC registers definitions */ - -/* SRC_GPR1 */ -#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \ - (SRC_GPR1_PLL_OFFSET + (pll)) ) -#define SRC_GPR1_PLL_SOURCE_MASK (0x1) - -#define SRC_GPR1_PLL_OFFSET (27) -#define SRC_GPR1_FIRC_CLK_SOURCE (0x0) -#define SRC_GPR1_XOSC_CLK_SOURCE (0x1) - -/* Periodic Interrupt Timer (PIT) */ -struct pit_reg { - u32 mcr; - u32 recv0[55]; - u32 ltmr64h; - u32 ltmr64l; - u32 recv1[6]; - u32 ldval0; - u32 cval0; - u32 tctrl0; - u32 tflg0; - u32 ldval1; - u32 cval1; - u32 tctrl1; - u32 tflg1; - u32 ldval2; - u32 cval2; - u32 tctrl2; - u32 tflg2; - u32 ldval3; - u32 cval3; - u32 tctrl3; - u32 tflg3; - u32 ldval4; - u32 cval4; - u32 tctrl4; - u32 tflg4; - u32 ldval5; - u32 cval5; - u32 tctrl5; - u32 tflg5; -}; - -/* Watchdog Timer (WDOG) */ -struct wdog_regs { - u32 cr; - u32 ir; - u32 to; - u32 wn; - u32 sr; - u32 co; - u32 sk; -}; - -/* UART */ -struct linflex_fsl { - u32 lincr1; - u32 linier; - u32 linsr; - u32 linesr; - u32 uartcr; - u32 uartsr; - u32 lintcsr; - u32 linocr; - u32 lintocr; - u32 linfbrr; - u32 linibrr; - u32 lincfr; - u32 lincr2; - u32 bidr; - u32 bdrl; - u32 bdrm; - u32 ifer; - u32 ifmi; - u32 ifmr; - u32 ifcr0; - u32 ifcr1; - u32 ifcr2; - u32 ifcr3; - u32 ifcr4; - u32 ifcr5; - u32 ifcr6; - u32 ifcr7; - u32 ifcr8; - u32 ifcr9; - u32 ifcr10; - u32 ifcr11; - u32 ifcr12; - u32 ifcr13; - u32 ifcr14; - u32 ifcr15; - u32 gcr; - u32 uartpto; - u32 uartcto; - u32 dmatxe; - u32 dmarxe; -}; - -/* MSCM Interrupt Router */ -struct mscm_ir { - u32 cpxtype; /* Processor x Type Register */ - u32 cpxnum; /* Processor x Number Register */ - u32 cpxmaster; /* Processor x Master Number Register */ - u32 cpxcount; /* Processor x Count Register */ - u32 cpxcfg0; /* Processor x Configuration 0 Register */ - u32 cpxcfg1; /* Processor x Configuration 1 Register */ - u32 cpxcfg2; /* Processor x Configuration 2 Register */ - u32 cpxcfg3; /* Processor x Configuration 3 Register */ - u32 cp0type; /* Processor 0 Type Register */ - u32 cp0num; /* Processor 0 Number Register */ - u32 cp0master; /* Processor 0 Master Number Register */ - u32 cp0count; /* Processor 0 Count Register */ - u32 cp0cfg0; /* Processor 0 Configuration 0 Register */ - u32 cp0cfg1; /* Processor 0 Configuration 1 Register */ - u32 cp0cfg2; /* Processor 0 Configuration 2 Register */ - u32 cp0cfg3; /* Processor 0 Configuration 3 Register */ - u32 cp1type; /* Processor 1 Type Register */ - u32 cp1num; /* Processor 1 Number Register */ - u32 cp1master; /* Processor 1 Master Number Register */ - u32 cp1count; /* Processor 1 Count Register */ - u32 cp1cfg0; /* Processor 1 Configuration 0 Register */ - u32 cp1cfg1; /* Processor 1 Configuration 1 Register */ - u32 cp1cfg2; /* Processor 1 Configuration 2 Register */ - u32 cp1cfg3; /* Processor 1 Configuration 3 Register */ - u32 reserved_0x060[232]; - u32 ocmdr0; /* On-Chip Memory Descriptor Register */ - u32 reserved_0x404[2]; - u32 ocmdr3; /* On-Chip Memory Descriptor Register */ - u32 reserved_0x410[28]; - u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */ - u32 reserved_0x490[28]; - u32 cpce0; /* Core Parity Checking Enable Register 0 */ - u32 reserved_0x504[191]; - u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */ - u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */ - u32 reserved_0x808[6]; - u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */ - u32 reserved_0x824[23]; - u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */ - u32 reserved_0x9e0[136]; - u32 iahbbe0; /* Gasket Burst Enable Register */ - u32 reserved_0xc04[63]; - u32 ipcge; /* Interconnect Parity Checking Global Enable Register */ - u32 reserved_0xd04[3]; - u32 ipce[4]; /* Interconnect Parity Checking Enable Register */ - u32 reserved_0xd20[8]; - u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */ - u32 reserved_0xd44[3]; - u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */ -}; - -#endif /* __ASSEMBLER__ */ - -#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h deleted file mode 100644 index c5efee5..0000000 --- a/arch/arm/include/asm/arch-s32v234/lpddr2.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__ -#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__ - -/* definitions for LPDDR2 PAD values */ -#define LPDDR2_CLK0_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \ - SIUL2_MSCR_DCYCLE_TRIM_NONE) -#define LPDDR2_CKEn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_CS_Bn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_DMn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) -#define LPDDR2_DQSn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \ - SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE) -#define LPDDR2_An_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ - SIUL2_MSCR_PUS_100K_UP) -#define LPDDR2_Dn_PAD \ - (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ - SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ - SIUL2_MSCR_PUS_100K_UP) - -#define _MDCTL 0x03010000 - -#define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */ -#define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */ -#define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */ -#define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */ -#define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */ -#define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */ -#define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */ -#define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */ -#define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */ -#define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */ -#define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */ -#define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */ -#define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */ -#define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */ -#define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */ -#define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */ -#define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */ -#define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */ -#define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */ -#define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ -#define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */ -#define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */ -#define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */ -#define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */ -#define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ -#define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */ -#define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */ -#define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */ -#define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */ -#define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */ -#define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */ - -/* set I/O pads for DDR */ -void lpddr2_config_iomux(uint8_t module); -void config_mmdc(uint8_t module); - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h deleted file mode 100644 index 957d48f..0000000 --- a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ - -#ifndef __ASSEMBLY__ - -/* MC_CGM registers definitions */ -/* MC_CGM_SC_SS */ -#define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) ) -#define MC_CGM_SC_SEL_FIRC (0x0) -#define MC_CGM_SC_SEL_XOSC (0x1) -#define MC_CGM_SC_SEL_ARMPLL (0x2) -#define MC_CGM_SC_SEL_CLKDISABLE (0xF) - -/* MC_CGM_SC_DCn */ -#define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) ) -#define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET)) -#define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000) -#define MC_CGM_SC_DCn_PREDIV_OFFSET (16) -#define MC_CGM_SC_DCn_DE (1 << 31) -#define MC_CGM_SC_SEL_MASK (0x0F000000) -#define MC_CGM_SC_SEL_OFFSET (24) - -/* MC_CGM_ACn_DCm */ -#define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) ) -#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET)) - -/* - * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown - * that the 5th bit is always ignored during writes if the current - * MC_CGM_ACn_DCm_PREDIV field has only 4 bits - * - * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits - * - * This should be changed if any problems occur. - */ -#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) -#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) -#define MC_CGM_ACn_DCm_DE (1 << 31) - -/* - * MC_CGM_ACn_SC/MC_CGM_ACn_SS - */ -#define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20)) -#define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20)) -#define MC_CGM_ACn_SEL_MASK (0x07000000) -#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET)) -#define MC_CGM_ACn_SEL_OFFSET (24) - -#define MC_CGM_ACn_SEL_FIRC (0x0) -#define MC_CGM_ACn_SEL_XOSC (0x1) -#define MC_CGM_ACn_SEL_ARMPLL (0x2) -/* - * According to the manual some PLL can be divided by X (X={1,3,5}): - * PERPLLDIVX, VIDEOPLLDIVX. - */ -#define MC_CGM_ACn_SEL_PERPLLDIVX (0x3) -#define MC_CGM_ACn_SEL_ENETPLL (0x4) -#define MC_CGM_ACn_SEL_DDRPLL (0x5) -#define MC_CGM_ACn_SEL_EXTSRCPAD (0x7) -#define MC_CGM_ACn_SEL_SYSCLK (0x8) -#define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9) -#define MC_CGM_ACn_SEL_PERCLK (0xA) - -/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ -#define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) -#define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div)) -#define PLLDIG_PLLDV_MFD_MASK (0x000000FF) - -/* - * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to - * the reference manual. This other value respect the formula 2^[RFDPHIBY+1] - */ -#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET)) -#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) -#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) -#define PLLDIG_PLLDV_RFDPHI_OFFSET (16) - -#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET)) -#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) -#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) -#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) - -#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET)) -#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) -#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) -#define PLLDIG_PLLDV_PREDIV_OFFSET (12) - -/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ -#define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) -#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) -#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) -#define PLLDIG_PLLFD_SMDEN (1 << 30) - -/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ -#define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) -#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET)) -#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) -#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) - -/* Digital Frequency Synthesizer (DFS) */ -/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */ -#define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040) - -/* DFS DLL Program Register 1 */ -#define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) - -#define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET)) -#define DFS_DLLPRG1_V2IGC_OFFSET (0) -#define DFS_DLLPRG1_V2IGC_MASK (0x00000007) - -#define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET)) -#define DFS_DLLPRG1_LCKWT_OFFSET (4) -#define DFS_DLLPRG1_LCKWT_MASK (0x00000030) - -#define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET)) -#define DFS_DLLPRG1_DACIN_OFFSET (6) -#define DFS_DLLPRG1_DACIN_MASK (0x000001C0) - -#define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET)) -#define DFS_DLLPRG1_CALBYPEN_OFFSET (9) -#define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200) - -#define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET)) -#define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10) -#define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00) - -#define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET)) -#define DFS_DLLPRG1_CPICTRL_OFFSET (12) -#define DFS_DLLPRG1_CPICTRL_MASK (0x00007000) - -/* DFS Control Register (DFS_CTRL) */ -#define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) -#define DFS_CTRL_DLL_LOLIE (1 << 0) -#define DFS_CTRL_DLL_RESET (1 << 1) - -/* DFS Port Status Register (DFS_PORTSR) */ -#define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) -/* DFS Port Reset Register (DFS_PORTRESET) */ -#define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) -#define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET)) -#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) -#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) -#define DFS_PORTRESET_PORTRESET_OFFSET (0) - -/* DFS Divide Register Portn (DFS_DVPORTn) */ -#define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) - -/* - * The mathematical formula for fdfs_clockout is the following: - * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) ) - */ -#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) ) -#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) ) -#define DFS_DVPORTn_MFI_MASK (0x0000FF00) -#define DFS_DVPORTn_MFN_MASK (0x000000FF) -#define DFS_DVPORTn_MFI_MAXVAL (0xFF) -#define DFS_DVPORTn_MFN_MAXVAL (0xFF) -#define DFS_DVPORTn_MFI_OFFSET (8) -#define DFS_DVPORTn_MFN_OFFSET (0) -#define DFS_MAXNUMBER (4) - -#define DFS_PARAMS_Nr (3) - -/* Frequencies are in Hz */ -#define FIRC_CLK_FREQ (48000000) -#define XOSC_CLK_FREQ (40000000) - -#define PLL_MIN_FREQ (650000000) -#define PLL_MAX_FREQ (1300000000) - -#define ARM_PLL_PHI0_FREQ (1000000000) -#define ARM_PLL_PHI1_FREQ (1000000000) -/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */ -#define ARM_PLL_PHI1_DFS1_EN (1) -#define ARM_PLL_PHI1_DFS1_MFI (3) -#define ARM_PLL_PHI1_DFS1_MFN (194) -/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */ -#define ARM_PLL_PHI1_DFS2_EN (1) -#define ARM_PLL_PHI1_DFS2_MFI (1) -#define ARM_PLL_PHI1_DFS2_MFN (170) -/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */ -#define ARM_PLL_PHI1_DFS3_EN (1) -#define ARM_PLL_PHI1_DFS3_MFI (1) -#define ARM_PLL_PHI1_DFS3_MFN (170) -#define ARM_PLL_PHI1_DFS_Nr (3) -#define ARM_PLL_PLLDV_PREDIV (2) -#define ARM_PLL_PLLDV_MFD (50) -#define ARM_PLL_PLLDV_MFN (0) - -#define PERIPH_PLL_PHI0_FREQ (400000000) -#define PERIPH_PLL_PHI1_FREQ (100000000) -#define PERIPH_PLL_PHI1_DFS_Nr (0) -#define PERIPH_PLL_PLLDV_PREDIV (1) -#define PERIPH_PLL_PLLDV_MFD (30) -#define PERIPH_PLL_PLLDV_MFN (0) - -#define ENET_PLL_PHI0_FREQ (500000000) -#define ENET_PLL_PHI1_FREQ (1000000000) -/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/ -#define ENET_PLL_PHI1_DFS1_EN (1) -#define ENET_PLL_PHI1_DFS1_MFI (2) -#define ENET_PLL_PHI1_DFS1_MFN (219) -/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/ -#define ENET_PLL_PHI1_DFS2_EN (1) -#define ENET_PLL_PHI1_DFS2_MFI (2) -#define ENET_PLL_PHI1_DFS2_MFN (219) -/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/ -#define ENET_PLL_PHI1_DFS3_EN (1) -#define ENET_PLL_PHI1_DFS3_MFI (3) -#define ENET_PLL_PHI1_DFS3_MFN (32) -/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/ -#define ENET_PLL_PHI1_DFS4_EN (1) -#define ENET_PLL_PHI1_DFS4_MFI (2) -#define ENET_PLL_PHI1_DFS4_MFN (0) -#define ENET_PLL_PHI1_DFS_Nr (4) -#define ENET_PLL_PLLDV_PREDIV (2) -#define ENET_PLL_PLLDV_MFD (50) -#define ENET_PLL_PLLDV_MFN (0) - -#define DDR_PLL_PHI0_FREQ (533000000) -#define DDR_PLL_PHI1_FREQ (1066000000) -/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */ -#define DDR_PLL_PHI1_DFS1_EN (1) -#define DDR_PLL_PHI1_DFS1_MFI (2) -#define DDR_PLL_PHI1_DFS1_MFN (33) -/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */ -#define DDR_PLL_PHI1_DFS2_EN (1) -#define DDR_PLL_PHI1_DFS2_MFI (2) -#define DDR_PLL_PHI1_DFS2_MFN (33) -/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */ -#define DDR_PLL_PHI1_DFS3_EN (1) -#define DDR_PLL_PHI1_DFS3_MFI (3) -#define DDR_PLL_PHI1_DFS3_MFN (11) -#define DDR_PLL_PHI1_DFS_Nr (3) -#define DDR_PLL_PLLDV_PREDIV (2) -#define DDR_PLL_PLLDV_MFD (53) -#define DDR_PLL_PLLDV_MFN (6144) - -#define VIDEO_PLL_PHI0_FREQ (600000000) -#define VIDEO_PLL_PHI1_FREQ (0) -#define VIDEO_PLL_PHI1_DFS_Nr (0) -#define VIDEO_PLL_PLLDV_PREDIV (1) -#define VIDEO_PLL_PLLDV_MFD (30) -#define VIDEO_PLL_PLLDV_MFN (0) - -#endif - -#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h deleted file mode 100644 index 1671af4..0000000 --- a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h +++ /dev/null @@ -1,198 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ - -#ifndef __ASSEMBLY__ - -/* MC_ME registers definitions */ - -/* MC_ME_GS */ -#define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000) - -#define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0) -#define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0) -#define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0) -#define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0) -#define MC_ME_GS_S_FIRC (1 << 4) -#define MC_ME_GS_S_XOSC (1 << 5) -#define MC_ME_GS_S_ARMPLL (1 << 6) -#define MC_ME_GS_S_PERPLL (1 << 7) -#define MC_ME_GS_S_ENETPLL (1 << 8) -#define MC_ME_GS_S_DDRPLL (1 << 9) -#define MC_ME_GS_S_VIDEOPLL (1 << 10) -#define MC_ME_GS_S_MVR (1 << 20) -#define MC_ME_GS_S_PDO (1 << 23) -#define MC_ME_GS_S_MTRANS (1 << 27) -#define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28) -#define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28) -#define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28) -#define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28) - -/* MC_ME_MCTL */ -#define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004) - -#define MC_ME_MCTL_KEY (0x00005AF0) -#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) -#define MC_ME_MCTL_RESET (0x0 << 28) -#define MC_ME_MCTL_TEST (0x1 << 28) -#define MC_ME_MCTL_DRUN (0x3 << 28) -#define MC_ME_MCTL_RUN0 (0x4 << 28) -#define MC_ME_MCTL_RUN1 (0x5 << 28) -#define MC_ME_MCTL_RUN2 (0x6 << 28) -#define MC_ME_MCTL_RUN3 (0x7 << 28) - -/* MC_ME_ME */ -#define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008) - -#define MC_ME_ME_RESET_FUNC (1 << 0) -#define MC_ME_ME_TEST (1 << 1) -#define MC_ME_ME_DRUN (1 << 3) -#define MC_ME_ME_RUN0 (1 << 4) -#define MC_ME_ME_RUN1 (1 << 5) -#define MC_ME_ME_RUN2 (1 << 6) -#define MC_ME_ME_RUN3 (1 << 7) - -/* MC_ME_RUN_PCn */ -#define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n)) - -#define MC_ME_RUN_PCn_RESET (1 << 0) -#define MC_ME_RUN_PCn_TEST (1 << 1) -#define MC_ME_RUN_PCn_DRUN (1 << 3) -#define MC_ME_RUN_PCn_RUN0 (1 << 4) -#define MC_ME_RUN_PCn_RUN1 (1 << 5) -#define MC_ME_RUN_PCn_RUN2 (1 << 6) -#define MC_ME_RUN_PCn_RUN3 (1 << 7) - -/* - * MC_ME_RESET_MC/MC_ME_TEST_MC - * MC_ME_DRUN_MC - * MC_ME_RUNn_MC - */ -#define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020) -#define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024) -#define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C) -#define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n)) - -#define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val)) -#define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F) -#define MC_ME_RUNMODE_MC_FIRCON (1 << 4) -#define MC_ME_RUNMODE_MC_XOSCON (1 << 5) -#define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll))) -#define MC_ME_RUNMODE_MC_MVRON (1 << 20) -#define MC_ME_RUNMODE_MC_PDO (1 << 23) -#define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28) -#define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29) -#define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30) - -/* MC_ME_DRUN_SEC_CC_I */ -#define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260) -/* MC_ME_RUNn_SEC_CC_I */ -#define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12) -#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3) - -/* - * ME_PCTLn - * Please note that these registers are 8 bits width, so - * the operations over them should be done using 8 bits operations. - */ -#define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK ) -#define MC_ME_PCTLn_RUNPCm_MASK (0x7) - -/* DEC200 Peripheral Control Register */ -#define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4) -/* 2D-ACE Peripheral Control Register */ -#define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB) -/* ENET Peripheral Control Register */ -#define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1) -/* DMACHMUX0 Peripheral Control Register */ -#define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2) -/* CSI0 Peripheral Control Register */ -#define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3) -/* MMDC0 Peripheral Control Register */ -#define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5) -/* FRAY Peripheral Control Register */ -#define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7) -/* PIT0 Peripheral Control Register */ -#define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9) -/* FlexTIMER0 Peripheral Control Register */ -#define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C) -/* SARADC0 Peripheral Control Register */ -#define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E) -/* LINFLEX0 Peripheral Control Register */ -#define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110) -/* IIC0 Peripheral Control Register */ -#define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112) -/* DSPI0 Peripheral Control Register */ -#define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114) -/* CANFD0 Peripheral Control Register */ -#define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116) -/* CRC0 Peripheral Control Register */ -#define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118) -/* DSPI2 Peripheral Control Register */ -#define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A) -/* SDHC Peripheral Control Register */ -#define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E) -/* VIU0 Peripheral Control Register */ -#define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127) -/* HPSMI Peripheral Control Register */ -#define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B) -/* SIPI Peripheral Control Register */ -#define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137) -/* LFAST Peripheral Control Register */ -#define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B) -/* MMDC1 Peripheral Control Register */ -#define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161) -/* DMACHMUX1 Peripheral Control Register */ -#define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162) -/* CSI1 Peripheral Control Register */ -#define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163) -/* QUADSPI0 Peripheral Control Register */ -#define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165) -/* PIT1 Peripheral Control Register */ -#define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169) -/* FlexTIMER1 Peripheral Control Register */ -#define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175) -/* IIC2 Peripheral Control Register */ -#define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179) -/* IIC1 Peripheral Control Register */ -#define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B) -/* CANFD1 Peripheral Control Register */ -#define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D) -/* LINFLEX1 Peripheral Control Register */ -#define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F) -/* DSPI3 Peripheral Control Register */ -#define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181) -/* DSPI1 Peripheral Control Register */ -#define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183) -/* TSENS Peripheral Control Register */ -#define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D) -/* CRC1 Peripheral Control Register */ -#define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F) -/* VIU1 Peripheral Control Register */ -#define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193) -/* JPEG Peripheral Control Register */ -#define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197) -/* H264_DEC Peripheral Control Register */ -#define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B) -/* H264_ENC Peripheral Control Register */ -#define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F) -/* MBIST Peripheral Control Register */ -#define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9) - -/* Core status register */ -#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0) - -#endif - -#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h deleted file mode 100644 index 34501b2..0000000 --- a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ -#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ - -#define MC_RGM_DES (MC_RGM_BASE_ADDR) -#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300) -#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310) -#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330) -#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340) -#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350) -#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354) -#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358) -#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600) -#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607) -#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B) - -/* function reset sources mask */ -#define F_SWT4 0x8000 -#define F_JTAG 0x400 -#define F_FCCU_SOFT 0x40 -#define F_FCCU_HARD 0x20 -#define F_SOFT_FUNC 0x8 -#define F_ST_DONE 0x4 -#define F_EXT_RST 0x1 - -#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h deleted file mode 100644 index 8d74ae0..0000000 --- a/arch/arm/include/asm/arch-s32v234/mmdc.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__ -#define __ARCH_ARM_MACH_S32V234_MMDC_H__ - -#define MMDC0 0 -#define MMDC1 1 - -#define MMDC_MDCTL 0x0 -#define MMDC_MDPDC 0x4 -#define MMDC_MDOTC 0x8 -#define MMDC_MDCFG0 0xC -#define MMDC_MDCFG1 0x10 -#define MMDC_MDCFG2 0x14 -#define MMDC_MDMISC 0x18 -#define MMDC_MDSCR 0x1C -#define MMDC_MDREF 0x20 -#define MMDC_MDRWD 0x2C -#define MMDC_MDOR 0x30 -#define MMDC_MDMRR 0x34 -#define MMDC_MDCFG3LP 0x38 -#define MMDC_MDMR4 0x3C -#define MMDC_MDASP 0x40 -#define MMDC_MAARCR 0x400 -#define MMDC_MAPSR 0x404 -#define MMDC_MAEXIDR0 0x408 -#define MMDC_MAEXIDR1 0x40C -#define MMDC_MADPCR0 0x410 -#define MMDC_MADPCR1 0x414 -#define MMDC_MADPSR0 0x418 -#define MMDC_MADPSR1 0x41C -#define MMDC_MADPSR2 0x420 -#define MMDC_MADPSR3 0x424 -#define MMDC_MADPSR4 0x428 -#define MMDC_MADPSR5 0x42C -#define MMDC_MASBS0 0x430 -#define MMDC_MASBS1 0x434 -#define MMDC_MAGENP 0x440 -#define MMDC_MPZQHWCTRL 0x800 -#define MMDC_MPWLGCR 0x808 -#define MMDC_MPWLDECTRL0 0x80C -#define MMDC_MPWLDECTRL1 0x810 -#define MMDC_MPWLDLST 0x814 -#define MMDC_MPODTCTRL 0x818 -#define MMDC_MPRDDQBY0DL 0x81C -#define MMDC_MPRDDQBY1DL 0x820 -#define MMDC_MPRDDQBY2DL 0x824 -#define MMDC_MPRDDQBY3DL 0x828 -#define MMDC_MPDGCTRL0 0x83C -#define MMDC_MPDGCTRL1 0x840 -#define MMDC_MPDGDLST0 0x844 -#define MMDC_MPRDDLCTL 0x848 -#define MMDC_MPRDDLST 0x84C -#define MMDC_MPWRDLCTL 0x850 -#define MMDC_MPWRDLST 0x854 -#define MMDC_MPZQLP2CTL 0x85C -#define MMDC_MPRDDLHWCTL 0x860 -#define MMDC_MPWRDLHWCTL 0x864 -#define MMDC_MPRDDLHWST0 0x868 -#define MMDC_MPRDDLHWST1 0x86C -#define MMDC_MPWRDLHWST1 0x870 -#define MMDC_MPWRDLHWST2 0x874 -#define MMDC_MPWLHWERR 0x878 -#define MMDC_MPDGHWST0 0x87C -#define MMDC_MPDGHWST1 0x880 -#define MMDC_MPDGHWST2 0x884 -#define MMDC_MPDGHWST3 0x888 -#define MMDC_MPPDCMPR1 0x88C -#define MMDC_MPPDCMPR2 0x890 -#define MMDC_MPSWDAR0 0x894 -#define MMDC_MPSWDRDR0 0x898 -#define MMDC_MPSWDRDR1 0x89C -#define MMDC_MPSWDRDR2 0x8A0 -#define MMDC_MPSWDRDR3 0x8A4 -#define MMDC_MPSWDRDR4 0x8A8 -#define MMDC_MPSWDRDR5 0x8AC -#define MMDC_MPSWDRDR6 0x8B0 -#define MMDC_MPSWDRDR7 0x8B4 -#define MMDC_MPMUR0 0x8B8 -#define MMDC_MPDCCR 0x8C0 - -#define MMDC_MPMUR0_FRC_MSR (1 << 11) -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16) - -#endif diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h deleted file mode 100644 index 7572581..0000000 --- a/arch/arm/include/asm/arch-s32v234/siul.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__ -#define __ARCH_ARM_MACH_S32V234_SIUL_H__ - -#include "ddr.h" - -#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004) -#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008) -#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010) -#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018) -#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020) -#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028) -#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030) -#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038) - -#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040) -#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i)) - -#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0) - -/* SIUL2_MSCR specifications as stated in Reference Manual: - * 0 - 359 Output Multiplexed Signal Configuration Registers - * 512- 1023 Input Multiplexed Signal Configuration Registers */ -#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240) -#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i)) - -#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40) -#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i)) - -#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300) -#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i)) - -#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500) -#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i)) - -#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700) -#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i)) - -#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740) -#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i)) - -#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780) -#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i)) - -/* SIUL2_MSCR masks */ -#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000) -#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30) -#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30) - -#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000) -#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29) -#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29) - -#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000) -#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27) -#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27) - -#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000) -#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24) -#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24) -#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24) -#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24) -#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24) -#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24) -#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24) - -#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000) -#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22) -#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22) -#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22) - -#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000) -#define SIUL2_MSCR_OBE_EN (1 << 21) - -#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000) -#define SIUL2_MSCR_ODE_EN (1 << 20) - -#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000) -#define SIUL2_MSCR_IBE_EN (1 << 19) - -#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000) -#define SIUL2_MSCR_HYS_EN (1 << 18) - -#define SIUL2_MSCR_INV(v) ((v) & 0x00020000) -#define SIUL2_MSCR_INV_EN (1 << 17) - -#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000) -#define SIUL2_MSCR_PKE_EN (1 << 16) - -#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000) -#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14) -#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14) -#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14) -#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14) - -#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000) -#define SIUL2_MSCR_PUE_EN (1 << 13) - -#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800) -#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11) -#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11) -#define SIUL2_MSCR_PUS_100K_UP (2 << 11) -#define SIUL2_MSCR_PUS_33K_UP (3 << 11) - -#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700) -#define SIUL2_MSCR_DSE_240ohm (1 << 8) -#define SIUL2_MSCR_DSE_120ohm (2 << 8) -#define SIUL2_MSCR_DSE_80ohm (3 << 8) -#define SIUL2_MSCR_DSE_60ohm (4 << 8) -#define SIUL2_MSCR_DSE_48ohm (5 << 8) -#define SIUL2_MSCR_DSE_40ohm (6 << 8) -#define SIUL2_MSCR_DSE_34ohm (7 << 8) - -#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0) -#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6) - -#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020) -#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f) -#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1) -#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2) -#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3) - -/* UART settings */ -#define SIUL2_UART0_TXD_PAD 12 -#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \ - SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1) - -#define SIUL2_UART0_MSCR_RXD_PAD 11 -#define SIUL2_UART0_IMCR_RXD_PAD 200 - -#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT) -#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2) - -/* uSDHC settings */ -#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \ - SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \ - SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN ) -#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1) -#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2) -#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2) -#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3) - -#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */ diff --git a/arch/arm/include/asm/arch-sa1100/bitfield.h b/arch/arm/include/asm/arch-sa1100/bitfield.h deleted file mode 100644 index 104a21c..0000000 --- a/arch/arm/include/asm/arch-sa1100/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h deleted file mode 100644 index b193f76..0000000 --- a/arch/arm/include/asm/arch-spear/clk.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010, STMicroelectronics - All Rights Reserved - * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics. - */ - -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return 83000000; -} diff --git a/arch/arm/include/asm/arch-spear/gpio.h b/arch/arm/include/asm/arch-spear/gpio.h deleted file mode 100644 index 4c8c40b..0000000 --- a/arch/arm/include/asm/arch-spear/gpio.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Stefan Roese <sr@denx.de> - */ - - -#ifndef __ASM_ARCH_SPEAR_GPIO_H -#define __ASM_ARCH_SPEAR_GPIO_H - -enum gpio_direction { - GPIO_DIRECTION_IN, - GPIO_DIRECTION_OUT, -}; - -struct gpio_regs { - u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ - u32 gpiodir; /* 0x400 */ -}; - -#define SPEAR_GPIO_COUNT 8 -#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) - -#endif /* __ASM_ARCH_SPEAR_GPIO_H */ diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h deleted file mode 100644 index c05bd44..0000000 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009, STMicroelectronics - All Rights Reserved - * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -#define CONFIG_SYS_USBD_BASE 0xE1100000 -#define CONFIG_SYS_PLUG_BASE 0xE1200000 -#define CONFIG_SYS_FIFO_BASE 0xE1000800 -#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000 -#define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000 -#define CONFIG_SYS_SMI_BASE 0xFC000000 -#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 -#define CONFIG_SPEAR_TIMERBASE 0xFC800000 -#define CONFIG_SPEAR_MISCBASE 0xFCA80000 -#define CONFIG_SPEAR_ETHBASE 0xE0800000 -#define CONFIG_SPEAR_MPMCBASE 0xFC600000 -#define CONFIG_SSP1_BASE 0xD0100000 -#define CONFIG_SSP2_BASE 0xD0180000 -#define CONFIG_SSP3_BASE 0xD8180000 -#define CONFIG_GPIO_BASE 0xD8100000 - -#define CONFIG_SYS_NAND_CLE (1 << 16) -#define CONFIG_SYS_NAND_ALE (1 << 17) - -#if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_FSMC_BASE 0xD1800000 -#define CONFIG_FSMC_NAND_BASE 0xD2000000 - -#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 -#define CONFIG_SPEAR_BOOTSTRAPSHFT 16 -#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB -#define CONFIG_SPEAR_ONLYSNORBOOT 0xA -#define CONFIG_SPEAR_NORNANDBOOT 0xB -#define CONFIG_SPEAR_NORNAND8BOOT 0x8 -#define CONFIG_SPEAR_NORNAND16BOOT 0x9 -#define CONFIG_SPEAR_USBBOOT 0x8 - -#define CONFIG_SPEAR_MPMCREGS 100 - -#elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_FSMC_BASE 0x94000000 - -#elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_FSMC_BASE 0x44000000 - -#undef CONFIG_SYS_NAND_CLE -#undef CONFIG_SYS_NAND_ALE -#define CONFIG_SYS_NAND_CLE (1 << 17) -#define CONFIG_SYS_NAND_ALE (1 << 16) - -#define CONFIG_SPEAR_EMIBASE 0x4F000000 -#define CONFIG_SPEAR_RASBASE 0xB4000000 - -#define CONFIG_SYS_MACB0_BASE 0xB0000000 -#define CONFIG_SYS_MACB1_BASE 0xB0800000 -#define CONFIG_SYS_MACB2_BASE 0xB1000000 -#define CONFIG_SYS_MACB3_BASE 0xB1800000 - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_FSMC_BASE 0x4C000000 - -#define CONFIG_SPEAR_EMIBASE 0x40000000 -#define CONFIG_SPEAR_RASBASE 0xB3000000 - -#define CONFIG_SYS_MACB0_BASE 0xAA000000 - -#endif -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h deleted file mode 100644 index d09e7eb..0000000 --- a/arch/arm/include/asm/arch-spear/spr_defs.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - */ - -#ifndef __SPR_DEFS_H__ -#define __SPR_DEFS_H__ - -extern int spear_board_init(ulong); -extern void setfreq(unsigned int, unsigned int); -extern unsigned int setfreq_sz; - -void plat_ddr_init(void); -void spear_late_init(void); - -int snor_boot_selected(void); -int nand_boot_selected(void); -int pnor_boot_selected(void); -int usb_boot_selected(void); -int uart_boot_selected(void); -int tftp_boot_selected(void); -int i2c_boot_selected(void); -int spi_boot_selected(void); -int mmc_boot_selected(void); - -extern u32 mpmc_conf_vals[]; - -struct chip_data { - int cpufreq; - int dramfreq; - int dramtype; - uchar version[32]; -}; - -/* HW mac id in i2c memory definitions */ -#define MAGIC_OFF 0x0 -#define MAGIC_LEN 0x2 -#define MAGIC_BYTE0 0x55 -#define MAGIC_BYTE1 0xAA -#define MAC_OFF 0x2 -#define MAC_LEN 0x6 - -#define PNOR_WIDTH_8 0 -#define PNOR_WIDTH_16 1 -#define PNOR_WIDTH_32 2 -#define PNOR_WIDTH_NUM 3 -#define PNOR_WIDTH_SEARCH 0xff - -#endif diff --git a/arch/arm/include/asm/arch-spear/spr_emi.h b/arch/arm/include/asm/arch-spear/spr_emi.h deleted file mode 100644 index 7b1cf35..0000000 --- a/arch/arm/include/asm/arch-spear/spr_emi.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com - */ - -#ifndef __SPEAR_EMI_H__ -#define __SPEAR_EMI_H__ - -#ifdef CONFIG_SPEAR_EMI - -struct emi_bank_regs { - u32 tap; - u32 tsdp; - u32 tdpw; - u32 tdpr; - u32 tdcs; - u32 control; -}; - -struct emi_regs { - struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; - u32 tout; - u32 ack; - u32 irq; -}; - -#define EMI_ACKMSK 0x40 - -/* control register definitions */ -#define EMI_CNTL_ENBBYTEW (1 << 2) -#define EMI_CNTL_ENBBYTER (1 << 3) -#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) - -#endif - -#endif diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h deleted file mode 100644 index dced0a1..0000000 --- a/arch/arm/include/asm/arch-spear/spr_gpt.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - */ - -#ifndef _SPR_GPT_H -#define _SPR_GPT_H - -struct gpt_regs { - u8 reserved[0x80]; - u32 control; - u32 status; - u32 compare; - u32 count; - u32 capture_re; - u32 capture_fe; -}; - -/* - * TIMER_CONTROL register settings - */ - -#define GPT_PRESCALER_MASK 0x000F -#define GPT_PRESCALER_1 0x0000 -#define GPT_PRESCALER_2 0x0001 -#define GPT_PRESCALER_4 0x0002 -#define GPT_PRESCALER_8 0x0003 -#define GPT_PRESCALER_16 0x0004 -#define GPT_PRESCALER_32 0x0005 -#define GPT_PRESCALER_64 0x0006 -#define GPT_PRESCALER_128 0x0007 -#define GPT_PRESCALER_256 0x0008 - -#define GPT_MODE_SINGLE_SHOT 0x0010 -#define GPT_MODE_AUTO_RELOAD 0x0000 - -#define GPT_ENABLE 0x0020 - -#define GPT_CAPT_MODE_MASK 0x00C0 -#define GPT_CAPT_MODE_NONE 0x0000 -#define GPT_CAPT_MODE_RE 0x0040 -#define GPT_CAPT_MODE_FE 0x0080 -#define GPT_CAPT_MODE_BOTH 0x00C0 - -#define GPT_INT_MATCH 0x0100 -#define GPT_INT_FE 0x0200 -#define GPT_INT_RE 0x0400 - -/* - * TIMER_STATUS register settings - */ - -#define GPT_STS_MATCH 0x0001 -#define GPT_STS_FE 0x0002 -#define GPT_STS_RE 0x0004 - -/* - * TIMER_COMPARE register settings - */ - -#define GPT_FREE_RUNNING 0xFFFF - -/* Timer, HZ specific defines */ -#define CONFIG_SPEAR_HZ 1000 -#define CONFIG_SPEAR_HZ_CLOCK 8300000 - -#endif diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h deleted file mode 100644 index 0171119..0000000 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ /dev/null @@ -1,260 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - */ - -#ifndef _SPR_MISC_H -#define _SPR_MISC_H - -struct misc_regs { - u32 auto_cfg_reg; /* 0x0 */ - u32 armdbg_ctr_reg; /* 0x4 */ - u32 pll1_cntl; /* 0x8 */ - u32 pll1_frq; /* 0xc */ - u32 pll1_mod; /* 0x10 */ - u32 pll2_cntl; /* 0x14 */ - u32 pll2_frq; /* 0x18 */ - u32 pll2_mod; /* 0x1C */ - u32 pll_ctr_reg; /* 0x20 */ - u32 amba_clk_cfg; /* 0x24 */ - u32 periph_clk_cfg; /* 0x28 */ - u32 periph1_clken; /* 0x2C */ - u32 soc_core_id; /* 0x30 */ - u32 ras_clken; /* 0x34 */ - u32 periph1_rst; /* 0x38 */ - u32 periph2_rst; /* 0x3C */ - u32 ras_rst; /* 0x40 */ - u32 prsc1_clk_cfg; /* 0x44 */ - u32 prsc2_clk_cfg; /* 0x48 */ - u32 prsc3_clk_cfg; /* 0x4C */ - u32 amem_cfg_ctrl; /* 0x50 */ - u32 expi_clk_cfg; /* 0x54 */ - u32 reserved_1; /* 0x58 */ - u32 clcd_synth_clk; /* 0x5C */ - u32 irda_synth_clk; /* 0x60 */ - u32 uart_synth_clk; /* 0x64 */ - u32 gmac_synth_clk; /* 0x68 */ - u32 ras_synth1_clk; /* 0x6C */ - u32 ras_synth2_clk; /* 0x70 */ - u32 ras_synth3_clk; /* 0x74 */ - u32 ras_synth4_clk; /* 0x78 */ - u32 arb_icm_ml1; /* 0x7C */ - u32 arb_icm_ml2; /* 0x80 */ - u32 arb_icm_ml3; /* 0x84 */ - u32 arb_icm_ml4; /* 0x88 */ - u32 arb_icm_ml5; /* 0x8C */ - u32 arb_icm_ml6; /* 0x90 */ - u32 arb_icm_ml7; /* 0x94 */ - u32 arb_icm_ml8; /* 0x98 */ - u32 arb_icm_ml9; /* 0x9C */ - u32 dma_src_sel; /* 0xA0 */ - u32 uphy_ctr_reg; /* 0xA4 */ - u32 gmac_ctr_reg; /* 0xA8 */ - u32 port_bridge_ctrl; /* 0xAC */ - u32 reserved_2[4]; /* 0xB0--0xBC */ - u32 prc1_ilck_ctrl_reg; /* 0xC0 */ - u32 prc2_ilck_ctrl_reg; /* 0xC4 */ - u32 prc3_ilck_ctrl_reg; /* 0xC8 */ - u32 prc4_ilck_ctrl_reg; /* 0xCC */ - u32 prc1_intr_ctrl_reg; /* 0xD0 */ - u32 prc2_intr_ctrl_reg; /* 0xD4 */ - u32 prc3_intr_ctrl_reg; /* 0xD8 */ - u32 prc4_intr_ctrl_reg; /* 0xDC */ - u32 powerdown_cfg_reg; /* 0xE0 */ - u32 ddr_1v8_compensation; /* 0xE4 */ - u32 ddr_2v5_compensation; /* 0xE8 */ - u32 core_3v3_compensation; /* 0xEC */ - u32 ddr_pad; /* 0xF0 */ - u32 bist1_ctr_reg; /* 0xF4 */ - u32 bist2_ctr_reg; /* 0xF8 */ - u32 bist3_ctr_reg; /* 0xFC */ - u32 bist4_ctr_reg; /* 0x100 */ - u32 bist5_ctr_reg; /* 0x104 */ - u32 bist1_rslt_reg; /* 0x108 */ - u32 bist2_rslt_reg; /* 0x10C */ - u32 bist3_rslt_reg; /* 0x110 */ - u32 bist4_rslt_reg; /* 0x114 */ - u32 bist5_rslt_reg; /* 0x118 */ - u32 syst_error_reg; /* 0x11C */ - u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */ - u32 ras_gpp1_in; /* 0x8000 */ - u32 ras_gpp2_in; /* 0x8004 */ - u32 ras_gpp1_out; /* 0x8008 */ - u32 ras_gpp2_out; /* 0x800C */ -}; - -/* SYNTH_CLK value*/ -#define SYNTH23 0x00020003 - -/* PLLx_FRQ value */ -#if defined(CONFIG_SPEAR3XX) -#define FREQ_332 0xA600010C -#define FREQ_266 0x8500010C -#elif defined(CONFIG_SPEAR600) -#define FREQ_332 0xA600010F -#define FREQ_266 0x8500010F -#endif - -/* PLL_CTR_REG */ -#define MEM_CLK_SEL_MSK 0x70000000 -#define MEM_CLK_HCLK 0x00000000 -#define MEM_CLK_2HCLK 0x10000000 -#define MEM_CLK_PLL2 0x30000000 - -#define EXPI_CLK_CFG_LOW_COMPR 0x2000 -#define EXPI_CLK_CFG_CLK_EN 0x0400 -#define EXPI_CLK_CFG_RST 0x0200 -#define EXPI_CLK_SYNT_EN 0x0010 -#define EXPI_CLK_CFG_SEL_PLL2 0x0004 -#define EXPI_CLK_CFG_INT_CLK_EN 0x0001 - -#define PLL2_CNTL_6UA 0x1c00 -#define PLL2_CNTL_SAMPLE 0x0008 -#define PLL2_CNTL_ENABLE 0x0004 -#define PLL2_CNTL_RESETN 0x0002 -#define PLL2_CNTL_LOCK 0x0001 - -/* AUTO_CFG_REG value */ -#define MISC_SOCCFGMSK 0x0000003F -#define MISC_SOCCFG30 0x0000000C -#define MISC_SOCCFG31 0x0000000D -#define MISC_NANDDIS 0x00020000 - -/* PERIPH_CLK_CFG value */ -#define MISC_GPT3SYNTH 0x00000400 -#define MISC_GPT4SYNTH 0x00000800 -#define CONFIG_SPEAR_UART48M 0 -#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4) - -/* PRSC_CLK_CFG value */ -/* - * Fout = Fin / (2^(N+1) * (M + 1)) - */ -#define MISC_PRSC_N_1 0x00001000 -#define MISC_PRSC_M_9 0x00000009 -#define MISC_PRSC_N_4 0x00004000 -#define MISC_PRSC_M_399 0x0000018F -#define MISC_PRSC_N_6 0x00006000 -#define MISC_PRSC_M_2593 0x00000A21 -#define MISC_PRSC_M_124 0x0000007C -#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9) - -/* PERIPH1_CLKEN, PERIPH1_RST value */ -#define MISC_USBDENB 0x01000000 -#define MISC_ETHENB 0x00800000 -#define MISC_SMIENB 0x00200000 -#define MISC_GPIO3ENB 0x00040000 -#define MISC_GPT3ENB 0x00010000 -#define MISC_SSP3ENB 0x00004000 -#define MISC_GPIO4ENB 0x00002000 -#define MISC_GPT2ENB 0x00000800 -#define MISC_FSMCENB 0x00000200 -#define MISC_I2CENB 0x00000080 -#define MISC_SSP2ENB 0x00000040 -#define MISC_SSP1ENB 0x00000020 -#define MISC_UART0ENB 0x00000008 - -/* PERIPH_CLK_CFG */ -#define XTALTIMEEN 0x00000001 -#define PLLTIMEEN 0x00000002 -#define CLCDCLK_SYNTH 0x00000000 -#define CLCDCLK_48MHZ 0x00000004 -#define CLCDCLK_EXT 0x00000008 -#define UARTCLK_MASK (0x1 << 4) -#define UARTCLK_48MHZ 0x00000000 -#define UARTCLK_SYNTH 0x00000010 -#define IRDACLK_48MHZ 0x00000000 -#define IRDACLK_SYNTH 0x00000020 -#define IRDACLK_EXT 0x00000040 -#define RTC_DISABLE 0x00000080 -#define GPT1CLK_48MHZ 0x00000000 -#define GPT1CLK_SYNTH 0x00000100 -#define GPT2CLK_48MHZ 0x00000000 -#define GPT2CLK_SYNTH 0x00000200 -#define GPT3CLK_48MHZ 0x00000000 -#define GPT3CLK_SYNTH 0x00000400 -#define GPT4CLK_48MHZ 0x00000000 -#define GPT4CLK_SYNTH 0x00000800 -#define GPT5CLK_48MHZ 0x00000000 -#define GPT5CLK_SYNTH 0x00001000 -#define GPT1_FREEZE 0x00002000 -#define GPT2_FREEZE 0x00004000 -#define GPT3_FREEZE 0x00008000 -#define GPT4_FREEZE 0x00010000 -#define GPT5_FREEZE 0x00020000 - -/* PERIPH1_CLKEN bits */ -#define PERIPH_ARM1_WE 0x00000001 -#define PERIPH_ARM1 0x00000002 -#define PERIPH_ARM2 0x00000004 -#define PERIPH_UART1 0x00000008 -#define PERIPH_UART2 0x00000010 -#define PERIPH_SSP1 0x00000020 -#define PERIPH_SSP2 0x00000040 -#define PERIPH_I2C 0x00000080 -#define PERIPH_JPEG 0x00000100 -#define PERIPH_FSMC 0x00000200 -#define PERIPH_FIRDA 0x00000400 -#define PERIPH_GPT4 0x00000800 -#define PERIPH_GPT5 0x00001000 -#define PERIPH_GPIO4 0x00002000 -#define PERIPH_SSP3 0x00004000 -#define PERIPH_ADC 0x00008000 -#define PERIPH_GPT3 0x00010000 -#define PERIPH_RTC 0x00020000 -#define PERIPH_GPIO3 0x00040000 -#define PERIPH_DMA 0x00080000 -#define PERIPH_ROM 0x00100000 -#define PERIPH_SMI 0x00200000 -#define PERIPH_CLCD 0x00400000 -#define PERIPH_GMAC 0x00800000 -#define PERIPH_USBD 0x01000000 -#define PERIPH_USBH1 0x02000000 -#define PERIPH_USBH2 0x04000000 -#define PERIPH_MPMC 0x08000000 -#define PERIPH_RAMW 0x10000000 -#define PERIPH_MPMC_EN 0x20000000 -#define PERIPH_MPMC_WE 0x40000000 -#define PERIPH_MPMCMSK 0x60000000 - -#define PERIPH_CLK_ALL 0x0FFFFFF8 -#define PERIPH_RST_ALL 0x00000004 - -/* DDR_PAD values */ -#define DDR_PAD_CNF_MSK 0x0000ffff -#define DDR_PAD_SW_CONF 0x00060000 -#define DDR_PAD_SSTL_SEL 0x00000001 -#define DDR_PAD_DRAM_TYPE 0x00008000 - -/* DDR_COMP values */ -#define DDR_COMP_ACCURATE 0x00000010 - -/* SoC revision stuff */ -#define SOC_PRI_SHFT 16 -#define SOC_SEC_SHFT 8 - -/* Revision definitions */ -#define SOC_SPEAR_NA 0 - -/* - * The definitons have started from - * 101 for SPEAr6xx - * 201 for SPEAr3xx - * 301 for SPEAr13xx - */ -#define SOC_SPEAR600_AA 101 -#define SOC_SPEAR600_AB 102 -#define SOC_SPEAR600_BA 103 -#define SOC_SPEAR600_BB 104 -#define SOC_SPEAR600_BC 105 -#define SOC_SPEAR600_BD 106 - -#define SOC_SPEAR300 201 -#define SOC_SPEAR310 202 -#define SOC_SPEAR320 203 - -extern int get_socrev(void); -int fsmc_nand_switch_ecc(uint32_t eccstrength); - -#endif diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spr_ssp.h deleted file mode 100644 index 088d34b..0000000 --- a/arch/arm/include/asm/arch-spear/spr_ssp.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Stefan Roese <sr@denx.de> - */ - -#ifndef _SPR_SSP_H -#define _SPR_SSP_H - -struct ssp_regs { - u32 sspcr0; - u32 sspcr1; - u32 sspdr; - u32 sspsr; - u32 sspcpsr; - u32 sspimsc; - u32 sspicr; - u32 sspdmacr; -}; - -#define SSPCR0_FRF_MOT_SPI 0x0000 -#define SSPCR0_DSS_16BITS 0x000f - -#define SSPCR1_SSE 0x0002 - -#define SSPSR_TNF 0x2 -#define SSPSR_TFE 0x1 - -#endif diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h deleted file mode 100644 index 6a83d87..0000000 --- a/arch/arm/include/asm/arch-spear/spr_syscntl.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com - */ - -#ifndef __SYSCTRL_H -#define __SYSCTRL_H - -struct syscntl_regs { - u32 scctrl; - u32 scsysstat; - u32 scimctrl; - u32 scimsysstat; - u32 scxtalctrl; - u32 scpllctrl; - u32 scpllfctrl; - u32 scperctrl0; - u32 scperctrl1; - u32 scperen; - u32 scperdis; - const u32 scperclken; - const u32 scperstat; -}; - -#define MODE_SHIFT 0x00000003 - -#define NORMAL 0x00000004 -#define SLOW 0x00000002 -#define DOZE 0x00000001 -#define SLEEP 0x00000000 - -#define PLL_TIM 0x01FFFFFF - -#endif diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h b/arch/arm/include/asm/arch-stih410/sdhci.h deleted file mode 100644 index 105d358..0000000 --- a/arch/arm/include/asm/arch-stih410/sdhci.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. - */ - -#ifndef __STI_SDHCI_H__ -#define __STI_SDHCI_H__ - -#define FLASHSS_MMC_CORE_CONFIG_1 0x400 -#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24) -#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12) - -#define STI_FLASHSS_MMC_CORE_CONFIG_1 \ - (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \ - FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN) - -#define FLASHSS_MMC_CORE_CONFIG_2 0x404 -#define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28) -#define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20) -#define MAX_BLK_LENGTH_1024 BIT(16) -#define BASE_CLK_FREQ_200 0xc8 - -#define STI_FLASHSS_MMC_CORE_CONFIG2 \ - (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ - FLASHSS_MMC_CORECFG_8BIT_EMMC | \ - MAX_BLK_LENGTH_1024 | \ - BASE_CLK_FREQ_200 << 0) - -#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \ - (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ - MAX_BLK_LENGTH_1024 | \ - BASE_CLK_FREQ_200) - -#define FLASHSS_MMC_CORE_CONFIG_3 0x408 -#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28) -#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20) -#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8) -#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4) -#define FLASHSS_MMC_CORECFG_SDMA BIT(0) - -#define STI_FLASHSS_MMC_CORE_CONFIG3 \ - (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \ - FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ - FLASHSS_MMC_CORECFG_3P3_VOLT | \ - FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ - FLASHSS_MMC_CORECFG_SDMA) - -#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \ - (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ - FLASHSS_MMC_CORECFG_3P3_VOLT | \ - FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ - FLASHSS_MMC_CORECFG_SDMA) - -#define FLASHSS_MMC_CORE_CONFIG_4 0x40c -#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20) -#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16) -#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12) - -#define STI_FLASHSS_MMC_CORE_CONFIG4 \ - (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \ - FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \ - FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT) - -#define ST_MMC_CCONFIG_REG_5 0x210 -#define SYSCONF_MMC1_ENABLE_BIT 3 - -#endif /* _STI_SDHCI_H_ */ diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h b/arch/arm/include/asm/arch-stih410/sys_proto.h deleted file mode 100644 index f9e8d37..0000000 --- a/arch/arm/include/asm/arch-stih410/sys_proto.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_SYS_PROTO_H -#define _ASM_ARCH_SYS_PROTO_H - -#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-stm32/gpio.h b/arch/arm/include/asm/arch-stm32/gpio.h deleted file mode 100644 index 570e80a..0000000 --- a/arch/arm/include/asm/arch-stm32/gpio.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _GPIO_H_ -#define _GPIO_H_ - -#define STM32_GPIOS_PER_BANK 16 - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, - STM32_GPIO_PORT_H, - STM32_GPIO_PORT_I -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - -enum stm32_gpio_mode { - STM32_GPIO_MODE_IN = 0, - STM32_GPIO_MODE_OUT, - STM32_GPIO_MODE_AF, - STM32_GPIO_MODE_AN -}; - -enum stm32_gpio_otype { - STM32_GPIO_OTYPE_PP = 0, - STM32_GPIO_OTYPE_OD -}; - -enum stm32_gpio_speed { - STM32_GPIO_SPEED_2M = 0, - STM32_GPIO_SPEED_25M, - STM32_GPIO_SPEED_50M, - STM32_GPIO_SPEED_100M -}; - -enum stm32_gpio_pupd { - STM32_GPIO_PUPD_NO = 0, - STM32_GPIO_PUPD_UP, - STM32_GPIO_PUPD_DOWN -}; - -enum stm32_gpio_af { - STM32_GPIO_AF0 = 0, - STM32_GPIO_AF1, - STM32_GPIO_AF2, - STM32_GPIO_AF3, - STM32_GPIO_AF4, - STM32_GPIO_AF5, - STM32_GPIO_AF6, - STM32_GPIO_AF7, - STM32_GPIO_AF8, - STM32_GPIO_AF9, - STM32_GPIO_AF10, - STM32_GPIO_AF11, - STM32_GPIO_AF12, - STM32_GPIO_AF13, - STM32_GPIO_AF14, - STM32_GPIO_AF15 -}; - -struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; -}; - -struct stm32_gpio_ctl { - enum stm32_gpio_mode mode; - enum stm32_gpio_otype otype; - enum stm32_gpio_speed speed; - enum stm32_gpio_pupd pupd; - enum stm32_gpio_af af; -}; - -struct stm32_gpio_regs { - u32 moder; /* GPIO port mode */ - u32 otyper; /* GPIO port output type */ - u32 ospeedr; /* GPIO port output speed */ - u32 pupdr; /* GPIO port pull-up/pull-down */ - u32 idr; /* GPIO port input data */ - u32 odr; /* GPIO port output data */ - u32 bsrr; /* GPIO port bit set/reset */ - u32 lckr; /* GPIO port configuration lock */ - u32 afr[2]; /* GPIO alternate function */ -}; - -struct stm32_gpio_priv { - struct stm32_gpio_regs *regs; - unsigned int gpio_range; -}; - -int stm32_offset_to_index(struct udevice *dev, unsigned int offset); - -#endif /* _GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h deleted file mode 100644 index bd3f4fd..0000000 --- a/arch/arm/include/asm/arch-stm32/stm32f.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_STM32F_H -#define _ASM_ARCH_STM32F_H - -#define STM32_PERIPH_BASE 0x40000000UL - -#define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) -#define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) - -#define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800) -#define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00) - -void stm32_flash_latency_cfg(int latency); - -#endif /* _ASM_ARCH_STM32F_H */ - diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h deleted file mode 100644 index 490f686..0000000 --- a/arch/arm/include/asm/arch-stm32f4/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - */ - -#ifndef _STM32_GPIO_H_ -#define _STM32_GPIO_H_ - -#include <asm/arch-stm32/gpio.h> - -#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h deleted file mode 100644 index 2094bd7..0000000 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - */ - -#ifndef _MACH_STM32_H_ -#define _MACH_STM32_H_ - -#include <asm/arch-stm32/stm32f.h> - -/* - * Peripheral memory map - */ -#define STM32_SYSMEM_BASE 0x1FFF0000 - -/* - * Register maps - */ -struct stm32_u_id_regs { - u32 u_id_low; - u32 u_id_mid; - u32 u_id_high; -}; - -/* - * Registers access macros - */ -#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) -#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) -static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { - [0 ... 3] = 16 * 1024, - [4] = 64 * 1024, - [5 ... 11] = 128 * 1024 -}; - -#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h deleted file mode 100644 index de42996..0000000 --- a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. - */ - -#ifndef __STM32_PWR_H_ - -/* - * Offsets of some PWR registers - */ -#define PWR_CR1_ODEN BIT(16) -#define PWR_CR1_ODSWEN BIT(17) -#define PWR_CSR1_ODRDY BIT(16) -#define PWR_CSR1_ODSWRDY BIT(17) - -struct stm32_pwr_regs { - u32 cr1; /* power control register 1 */ - u32 csr1; /* power control/status register 2 */ -}; - -#endif /* __STM32_PWR_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h deleted file mode 100644 index 21f4e0f..0000000 --- a/arch/arm/include/asm/arch-stm32f7/gpio.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STM32_GPIO_H_ -#define _STM32_GPIO_H_ - -#include <asm/arch-stm32/gpio.h> - -#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h deleted file mode 100644 index 3451e74..0000000 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -#include <asm/arch-stm32/stm32f.h> - -static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { - [0 ... 3] = 32 * 1024, - [4] = 128 * 1024, - [5 ... 7] = 256 * 1024 -}; - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h deleted file mode 100644 index c93fc5a..0000000 --- a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. - */ - -#ifndef __STM32_PWR_H_ - -/* - * Offsets of some PWR registers - */ -#define PWR_CR1_ODEN BIT(16) -#define PWR_CR1_ODSWEN BIT(17) -#define PWR_CSR1_ODRDY BIT(16) -#define PWR_CSR1_ODSWRDY BIT(17) - -struct stm32_pwr_regs { - u32 cr1; /* power control register 1 */ - u32 csr1; /* power control/status register 2 */ - u32 cr2; /* power control register 2 */ - u32 csr2; /* power control/status register 2 */ -}; - -#endif /* __STM32_PWR_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/syscfg.h b/arch/arm/include/asm/arch-stm32f7/syscfg.h deleted file mode 100644 index ce2a952..0000000 --- a/arch/arm/include/asm/arch-stm32f7/syscfg.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 - * Michael Kurz, michi.kurz@gmail.com. - */ - -#ifndef _STM32_SYSCFG_H -#define _STM32_SYSCFG_H - -struct stm32_syscfg_regs { - u32 memrmp; - u32 pmc; - u32 exticr1; - u32 exticr2; - u32 exticr3; - u32 exticr4; - u32 cmpcr; -}; - -/* - * SYSCFG registers base - */ -#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE) - -/* SYSCFG peripheral mode configuration register */ -#define SYSCFG_PMC_MII_RMII_SEL BIT(23) - -#endif diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h deleted file mode 100644 index 2dad52a..0000000 --- a/arch/arm/include/asm/arch-stm32h7/gpio.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. - */ - -#ifndef _STM32_GPIO_H_ -#define _STM32_GPIO_H_ - -#include <asm/arch-stm32/gpio.h> - -#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32h7/stm32.h b/arch/arm/include/asm/arch-stm32h7/stm32.h deleted file mode 100644 index 458baca..0000000 --- a/arch/arm/include/asm/arch-stm32h7/stm32.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -/* - * This empty files is needed to not break compilation - * Some common drivers to STM32F4/F7 and H7 include a stm32.h file - * Some cleanup need to be done to communalize all the following - * stm32.h files: - * - * arch/arm/include/asm/arch-stm32f1/stm32.h - * arch/arm/include/asm/arch-stm32f4/stm32.h - * arch/arm/include/asm/arch-stm32f7/stm32.h - */ -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h deleted file mode 100644 index b27f407..0000000 --- a/arch/arm/include/asm/arch-stv0991/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __ASM_ARCH_STV0991_GPIO_H -#define __ASM_ARCH_STV0991_GPIO_H - -enum gpio_direction { - GPIO_DIRECTION_IN, - GPIO_DIRECTION_OUT, -}; - -struct gpio_regs { - u32 data; /* offset 0x0 */ - u32 reserved[0xff]; /* 0x4--0x3fc */ - u32 dir; /* offset 0x400 */ -}; - -#endif /* __ASM_ARCH_STV0991_GPIO_H */ diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h deleted file mode 100644 index ea8f820..0000000 --- a/arch/arm/include/asm/arch-stv0991/hardware.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -/* STV0991 */ -#define SRAM0_BASE_ADDR 0x00000000UL -#define SRAM1_BASE_ADDR 0x00068000UL -#define SRAM2_BASE_ADDR 0x000D0000UL -#define SRAM3_BASE_ADDR 0x00138000UL -#define CFS_SRAM0_BASE_ADDR 0x00198000UL -#define CFS_SRAM1_BASE_ADDR 0x001B8000UL -#define FAST_SRAM_BASE_ADDR 0x001D8000UL -#define FLASH_BASE_ADDR 0x40000000UL -#define PL310_BASE_ADDR 0x70000000UL -#define HSAXIM_BASE_ADDR 0x70100000UL -#define IMGSS_BASE_ADDR 0x70200000UL -#define ADC_BASE_ADDR 0x80000000UL -#define GPIOA_BASE_ADDR 0x80001000UL -#define GPIOB_BASE_ADDR 0x80002000UL -#define GPIOC_BASE_ADDR 0x80003000UL -#define HDM_BASE_ADDR 0x80004000UL -#define THSENS_BASE_ADDR 0x80200000UL -#define GPTIMER2_BASE_ADDR 0x80201000UL -#define GPTIMER1_BASE_ADDR 0x80202000UL -#define QSPI_BASE_ADDR 0x80203000UL -#define CGU_BASE_ADDR 0x80204000UL -#define CREG_BASE_ADDR 0x80205000UL -#define PEC_BASE_ADDR 0x80206000UL -#define WDRU_BASE_ADDR 0x80207000UL -#define BSEC_BASE_ADDR 0x80208000UL -#define DAP_ROM_BASE_ADDR 0x80210000UL -#define SOC_CTI_BASE_ADDR 0x80211000UL -#define TPIU_BASE_ADDR 0x80212000UL -#define TMC_ETF_BASE_ADDR 0x80213000UL -#define R4_ETM_BASE_ADDR 0x80214000UL -#define R4_CTI_BASE_ADDR 0x80215000UL -#define R4_DBG_BASE_ADDR 0x80216000UL -#define GMAC_BASE_ADDR 0x80300000UL -#define RNSS_BASE_ADDR 0x80302000UL -#define CRYP_BASE_ADDR 0x80303000UL -#define HASH_BASE_ADDR 0x80304000UL -#define GPDMA_BASE_ADDR 0x80305000UL -#define ISA_BASE_ADDR 0x8032A000UL -#define HCI_BASE_ADDR 0x80400000UL -#define I2C1_BASE_ADDR 0x80401000UL -#define I2C2_BASE_ADDR 0x80402000UL -#define SAI_BASE_ADDR 0x80403000UL -#define USI_BASE_ADDR 0x80404000UL -#define SPI1_BASE_ADDR 0x80405000UL -#define UART_BASE_ADDR 0x80406000UL -#define SPI2_BASE_ADDR 0x80500000UL -#define CAN_BASE_ADDR 0x80501000UL -#define USART1_BASE_ADDR 0x80502000UL -#define USART2_BASE_ADDR 0x80503000UL -#define USART3_BASE_ADDR 0x80504000UL -#define USART4_BASE_ADDR 0x80505000UL -#define USART5_BASE_ADDR 0x80506000UL -#define USART6_BASE_ADDR 0x80507000UL -#define SDI2_BASE_ADDR 0x80600000UL -#define SDI1_BASE_ADDR 0x80601000UL -#define VICA_BASE_ADDR 0x81000000UL -#define VICB_BASE_ADDR 0x81001000UL -#define STM_CHANNELS_BASE_ADDR 0x81100000UL -#define STM_BASE_ADDR 0x81110000UL -#define SROM_BASE_ADDR 0xFFFF0000UL - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h deleted file mode 100644 index df9dd54..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_CGU_H -#define _STV0991_CGU_H - -struct stv0991_cgu_regs { - u32 cpu_freq; /* offset 0x0 */ - u32 icn2_freq; /* offset 0x4 */ - u32 dma_freq; /* offset 0x8 */ - u32 isp_freq; /* offset 0xc */ - u32 h264_freq; /* offset 0x10 */ - u32 osif_freq; /* offset 0x14 */ - u32 ren_freq; /* offset 0x18 */ - u32 tim_freq; /* offset 0x1c */ - u32 sai_freq; /* offset 0x20 */ - u32 eth_freq; /* offset 0x24 */ - u32 i2c_freq; /* offset 0x28 */ - u32 spi_freq; /* offset 0x2c */ - u32 uart_freq; /* offset 0x30 */ - u32 qspi_freq; /* offset 0x34 */ - u32 sdio_freq; /* offset 0x38 */ - u32 usi_freq; /* offset 0x3c */ - u32 can_line_freq; /* offset 0x40 */ - u32 debug_freq; /* offset 0x44 */ - u32 trace_freq; /* offset 0x48 */ - u32 stm_freq; /* offset 0x4c */ - u32 eth_ctrl; /* offset 0x50 */ - u32 reserved[3]; /* offset 0x54 */ - u32 osc_ctrl; /* offset 0x60 */ - u32 pll1_ctrl; /* offset 0x64 */ - u32 pll1_freq; /* offset 0x68 */ - u32 pll1_fract; /* offset 0x6c */ - u32 pll1_spread; /* offset 0x70 */ - u32 pll1_status; /* offset 0x74 */ - u32 pll2_ctrl; /* offset 0x78 */ - u32 pll2_freq; /* offset 0x7c */ - u32 pll2_fract; /* offset 0x80 */ - u32 pll2_spread; /* offset 0x84 */ - u32 pll2_status; /* offset 0x88 */ - u32 cgu_enable_1; /* offset 0x8c */ - u32 cgu_enable_2; /* offset 0x90 */ - u32 cgu_isp_pulse; /* offset 0x94 */ - u32 cgu_h264_pulse; /* offset 0x98 */ - u32 cgu_osif_pulse; /* offset 0x9c */ - u32 cgu_ren_pulse; /* offset 0xa0 */ - -}; - -/* CGU Timer */ -#define CLK_TMR_OSC 0 -#define CLK_TMR_MCLK 1 -#define CLK_TMR_PLL1 2 -#define CLK_TMR_PLL2 3 -#define MDIV_SHIFT_TMR 3 -#define DIV_SHIFT_TMR 6 - -#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ - | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) - -/* Clock Enable/Disable */ - -#define TIMER1_CLK_EN (1 << 15) - -/* CGU Uart config */ -#define CLK_UART_MCLK 0 -#define CLK_UART_PLL1 1 -#define CLK_UART_PLL2 2 - -#define MDIV_SHIFT_UART 3 -#define DIV_SHIFT_UART 6 - -#define UART_CLK_CFG (4 << DIV_SHIFT_UART \ - | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) - -/* CGU Ethernet clock config */ -#define CLK_ETH_MCLK 0 -#define CLK_ETH_PLL1 1 -#define CLK_ETH_PLL2 2 - -#define MDIV_SHIFT_ETH 3 -#define DIV_SHIFT_ETH 6 -#define DIV_ETH_125 9 -#define DIV_ETH_50 12 -#define DIV_ETH_P2P 15 - -#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ - | 1 << DIV_ETH_125 \ - | 0 << DIV_SHIFT_ETH \ - | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) - /* CGU Ethernet control */ - -#define ETH_CLK_TX_EXT_PHY 0 -#define ETH_CLK_TX_125M 1 -#define ETH_CLK_TX_25M 2 -#define ETH_CLK_TX_2M5 3 -#define ETH_CLK_TX_DIS 7 - -#define ETH_CLK_RX_EXT_PHY 0 -#define ETH_CLK_RX_25M 1 -#define ETH_CLK_RX_2M5 2 -#define ETH_CLK_RX_DIS 3 -#define RX_CLK_SHIFT 3 -#define ETH_CLK_MASK ~(0x1F) - -#define ETH_PHY_MODE_GMII 0 -#define ETH_PHY_MODE_RMII 1 -#define ETH_PHY_CLK_DIS 1 - -#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ - | ETH_CLK_TX_EXT_PHY) -/* CGU qspi clock */ -#define DIV_HCLK1_SHIFT 9 -#define DIV_CRYP_SHIFT 6 -#define MDIV_QSPI_SHIFT 3 - -#define CLK_QSPI_OSC 0 -#define CLK_QSPI_MCLK 1 -#define CLK_QSPI_PLL1 2 -#define CLK_QSPI_PLL2 3 - -#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \ - | 1 << DIV_CRYP_SHIFT \ - | 0 << MDIV_QSPI_SHIFT \ - | CLK_QSPI_OSC) - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h deleted file mode 100644 index 4d444a6..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_CREG_H -#define _STV0991_CREG_H - -struct stv0991_creg { - u32 version; /* offset 0x0 */ - u32 hdpctl; /* offset 0x4 */ - u32 hdpval; /* offset 0x8 */ - u32 hdpgposet; /* offset 0xc */ - u32 hdpgpoclr; /* offset 0x10 */ - u32 hdpgpoval; /* offset 0x14 */ - u32 stm_mux; /* offset 0x18 */ - u32 sysctrl_1; /* offset 0x1c */ - u32 sysctrl_2; /* offset 0x20 */ - u32 sysctrl_3; /* offset 0x24 */ - u32 sysctrl_4; /* offset 0x28 */ - u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ - u32 mux1; /* offset 0x100 */ - u32 mux2; /* offset 0x104 */ - u32 mux3; /* offset 0x108 */ - u32 mux4; /* offset 0x10c */ - u32 mux5; /* offset 0x110 */ - u32 mux6; /* offset 0x114 */ - u32 mux7; /* offset 0x118 */ - u32 mux8; /* offset 0x11c */ - u32 mux9; /* offset 0x120 */ - u32 mux10; /* offset 0x124 */ - u32 mux11; /* offset 0x128 */ - u32 mux12; /* offset 0x12c */ - u32 mux13; /* offset 0x130 */ - u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ - u32 cfg_pad1; /* offset 0x200 */ - u32 cfg_pad2; /* offset 0x204 */ - u32 cfg_pad3; /* offset 0x208 */ - u32 cfg_pad4; /* offset 0x20c */ - u32 cfg_pad5; /* offset 0x210 */ - u32 cfg_pad6; /* offset 0x214 */ - u32 cfg_pad7; /* offset 0x218 */ - u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ - u32 vdd_pad1; /* offset 0x300 */ - u32 vdd_pad2; /* offset 0x304 */ - u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ - u32 vdd_comp1; /* offset 0x400 */ -}; - -/* CREG MUX 13 register */ -#define FLASH_CS_NC_SHIFT 4 -#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT) -#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT) - -#define FLASH_CLK_SHIFT 0 -#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT) -#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT) - -/* CREG MUX 12 register */ -#define GPIOC_30_MUX_SHIFT 24 -#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) -#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) - -#define GPIOC_31_MUX_SHIFT 28 -#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) -#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) - -/* CREG MUX 7 register */ -#define GPIOB_16_MUX_SHIFT 0 -#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) -#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) - -#define GPIOB_17_MUX_SHIFT 4 -#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) -#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) - -/* CREG CFG_PAD6 register */ - -#define GPIOC_31_MODE_SHIFT 30 -#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) -#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) -#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) - -#define GPIOC_30_MODE_SHIFT 28 -#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) -#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) -#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) - -/* CREG Ethernet pad config */ - -#define VDD_ETH_PS_1V8 0 -#define VDD_ETH_PS_2V5 2 -#define VDD_ETH_PS_3V3 3 -#define VDD_ETH_PS_MASK 0x3 - -#define VDD_ETH_PS_SHIFT 12 -#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) - -#define VDD_ETH_M_PS_SHIFT 28 -#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h deleted file mode 100644 index 97d28b2..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __STV0991_DEFS_H__ -#define __STV0991_DEFS_H__ -#include <asm/arch/stv0991_periph.h> - -extern int stv0991_pinmux_config(enum periph_id); -extern int clock_setup(enum periph_clock); - -#endif - diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h deleted file mode 100644 index cd27472..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_GPT_H -#define _STV0991_GPT_H - -#include <asm/arch-stv0991/hardware.h> - -struct gpt_regs { - u32 cr1; - u32 cr2; - u32 reserved_1; - u32 dier; /* dma_int_en */ - u32 sr; /* status reg */ - u32 egr; /* event gen */ - u32 reserved_2[3]; /* offset 0x18--0x20*/ - u32 cnt; - u32 psc; - u32 arr; -}; - -struct gpt_regs *const gpt1_regs_ptr = - (struct gpt_regs *) GPTIMER1_BASE_ADDR; - -/* Timer control1 register */ -#define GPT_CR1_CEN 0x0001 -#define GPT_MODE_AUTO_RELOAD (1 << 7) - -/* Timer prescalar reg */ -#define GPT_PRESCALER_128 0x128 - -/* Auto reload register for free running config */ -#define GPT_FREE_RUNNING 0xFFFF - -/* Timer, HZ specific defines */ -#define CONFIG_STV0991_HZ 1000 -#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h deleted file mode 100644 index 7a50be1..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - UART_GPIOC_30_31 = 0, - UART_GPIOB_16_17, - ETH_GPIOB_10_31_C_0_4, - QSPI_CS_CLK_PAD, - PERIPH_ID_I2C0, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_SPI0, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_SDMMC0, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC2, - PERIPH_ID_SDMMC3, - PERIPH_ID_I2S1, -}; - -enum periph_clock { - UART_CLOCK_CFG = 0, - ETH_CLOCK_CFG, - QSPI_CLOCK_CFG, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h deleted file mode 100644 index 8cb8a8a..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_WD_RST_H -#define _STV0991_WD_RST_H -#include <asm/arch-stv0991/hardware.h> - -struct stv0991_wd_ru { - u32 wdru_config; - u32 wdru_ctrl1; - u32 wdru_ctrl2; - u32 wdru_tim; - u32 wdru_count; - u32 wdru_stat; - u32 wdru_wrlock; -}; - -struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \ - (struct stv0991_wd_ru *)WDRU_BASE_ADDR; - -/* Watchdog control register */ -#define WDRU_RST_SYS 0x1 - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h deleted file mode 100644 index 54c144a..0000000 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Allwinner A64 (sun50i) CPU - */ - -#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) -/* reserve space for BOOT0 header information */ - b reset - .space 1532 -#elif defined(CONFIG_ARM_BOOT_HOOK_RMR) -/* - * Switch into AArch64 if needed. - * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source. - */ - tst x0, x0 // this is "b #0x84" in ARM - b reset - .space 0x7c - .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0 - .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE - .word 0xe5810000 // str r0, [r1] - .word 0xf57ff04f // dsb sy - .word 0xf57ff06f // isb sy - .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR - .word 0xe3800003 // orr r0, r0, #3 - .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR - .word 0xf57ff06f // isb sy - .word 0xe320f003 // wfi - .word 0xeafffffd // b @wfi -#ifndef CONFIG_MACH_SUN50I_H6 - .word 0x017000a0 // writeable RVBAR mapping address -#else - .word 0x09010040 // writeable RVBAR mapping address -#endif -#ifdef CONFIG_SPL_BUILD - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif -#else -/* normal execution */ - b reset -#endif diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h deleted file mode 100644 index 5dd97ab..0000000 --- a/arch/arm/include/asm/arch-sunxi/ccu.h +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Amarula Solutions. - * Author: Jagan Teki <jagan@amarulasolutions.com> - */ - -#ifndef _ASM_ARCH_CCU_H -#define _ASM_ARCH_CCU_H - -/** - * enum ccu_flags - ccu clock/reset flags - * - * @CCU_CLK_F_IS_VALID: is given clock gate is valid? - * @CCU_RST_F_IS_VALID: is given reset control is valid? - */ -enum ccu_flags { - CCU_CLK_F_IS_VALID = BIT(0), - CCU_RST_F_IS_VALID = BIT(1), -}; - -/** - * struct ccu_clk_gate - ccu clock gate - * @off: gate offset - * @bit: gate bit - * @flags: ccu clock gate flags - */ -struct ccu_clk_gate { - u16 off; - u32 bit; - enum ccu_flags flags; -}; - -#define GATE(_off, _bit) { \ - .off = _off, \ - .bit = _bit, \ - .flags = CCU_CLK_F_IS_VALID, \ -} - -/** - * struct ccu_reset - ccu reset - * @off: reset offset - * @bit: reset bit - * @flags: ccu reset control flags - */ -struct ccu_reset { - u16 off; - u32 bit; - enum ccu_flags flags; -}; - -#define RESET(_off, _bit) { \ - .off = _off, \ - .bit = _bit, \ - .flags = CCU_RST_F_IS_VALID, \ -} - -/** - * struct ccu_desc - clock control unit descriptor - * - * @gates: clock gates - * @resets: reset unit - */ -struct ccu_desc { - const struct ccu_clk_gate *gates; - const struct ccu_reset *resets; -}; - -/** - * struct ccu_priv - sunxi clock control unit - * - * @base: base address - * @desc: ccu descriptor - */ -struct ccu_priv { - void *base; - const struct ccu_desc *desc; -}; - -/** - * sunxi_clk_probe - common sunxi clock probe - * @dev: clock device - */ -int sunxi_clk_probe(struct udevice *dev); - -extern struct clk_ops sunxi_clk_ops; - -/** - * sunxi_reset_bind() - reset binding - * - * @dev: reset device - * @count: reset count - * @return 0 success, or error value - */ -int sunxi_reset_bind(struct udevice *dev, ulong count); - -#endif /* _ASM_ARCH_CCU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h deleted file mode 100644 index 5994130..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CLOCK_H -#define _SUNXI_CLOCK_H - -#include <linux/types.h> - -#define CLK_GATE_OPEN 0x1 -#define CLK_GATE_CLOSE 0x0 - -/* clock control module regs definition */ -#if defined(CONFIG_MACH_SUN8I_A83T) -#include <asm/arch/clock_sun8i_a83t.h> -#elif defined(CONFIG_MACH_SUN50I_H6) -#include <asm/arch/clock_sun50i_h6.h> -#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ - defined(CONFIG_MACH_SUN50I) -#include <asm/arch/clock_sun6i.h> -#elif defined(CONFIG_MACH_SUN9I) -#include <asm/arch/clock_sun9i.h> -#else -#include <asm/arch/clock_sun4i.h> -#endif - -#ifndef __ASSEMBLY__ -int clock_init(void); -int clock_twi_onoff(int port, int state); -void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); -void clock_init_safe(void); -void clock_init_sec(void); -void clock_init_uart(void); -#endif - -#endif /* _SUNXI_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h deleted file mode 100644 index 2cec91c..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun4i, sun5i and sun7i clock register definitions - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CLOCK_SUN4I_H -#define _SUNXI_CLOCK_SUN4I_H - -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x00 pll1 control */ - u32 pll1_tun; /* 0x04 pll1 tuning */ - u32 pll2_cfg; /* 0x08 pll2 control */ - u32 pll2_tun; /* 0x0c pll2 tuning */ - u32 pll3_cfg; /* 0x10 pll3 control */ - u8 res0[0x4]; - u32 pll4_cfg; /* 0x18 pll4 control */ - u8 res1[0x4]; - u32 pll5_cfg; /* 0x20 pll5 control */ - u32 pll5_tun; /* 0x24 pll5 tuning */ - u32 pll6_cfg; /* 0x28 pll6 control */ - u32 pll6_tun; /* 0x2c pll6 tuning */ - u32 pll7_cfg; /* 0x30 pll7 control */ - u32 pll1_tun2; /* 0x34 pll5 tuning2 */ - u8 res2[0x4]; - u32 pll5_tun2; /* 0x3c pll5 tuning2 */ - u8 res3[0xc]; - u32 pll_lock_dbg; /* 0x4c pll lock time debug */ - u32 osc24m_cfg; /* 0x50 osc24m control */ - u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ - u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ - u32 axi_gate; /* 0x5c axi module clock gating */ - u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ - u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ - u32 apb0_gate; /* 0x68 apb0 module clock gating */ - u32 apb1_gate; /* 0x6c apb1 module clock gating */ - u8 res4[0x10]; - u32 nand0_clk_cfg; /* 0x80 nand sub clock control */ - u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ - u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ - u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ - u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ - u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ - u32 ts_clk_cfg; /* 0x98 transport stream clock control */ - u32 ss_clk_cfg; /* 0x9c */ - u32 spi0_clk_cfg; /* 0xa0 */ - u32 spi1_clk_cfg; /* 0xa4 */ - u32 spi2_clk_cfg; /* 0xa8 */ - u32 pata_clk_cfg; /* 0xac */ - u32 ir0_clk_cfg; /* 0xb0 */ - u32 ir1_clk_cfg; /* 0xb4 */ - u32 iis_clk_cfg; /* 0xb8 */ - u32 ac97_clk_cfg; /* 0xbc */ - u32 spdif_clk_cfg; /* 0xc0 */ - u32 keypad_clk_cfg; /* 0xc4 */ - u32 sata_clk_cfg; /* 0xc8 */ - u32 usb_clk_cfg; /* 0xcc */ - u32 gps_clk_cfg; /* 0xd0 */ - u32 spi3_clk_cfg; /* 0xd4 */ - u8 res5[0x28]; - u32 dram_clk_gate; /* 0x100 */ - u32 be0_clk_cfg; /* 0x104 */ - u32 be1_clk_cfg; /* 0x108 */ - u32 fe0_clk_cfg; /* 0x10c */ - u32 fe1_clk_cfg; /* 0x110 */ - u32 mp_clk_cfg; /* 0x114 */ - u32 lcd0_ch0_clk_cfg; /* 0x118 */ - u32 lcd1_ch0_clk_cfg; /* 0x11c */ - u32 csi_isp_clk_cfg; /* 0x120 */ - u8 res6[0x4]; - u32 tvd_clk_reg; /* 0x128 */ - u32 lcd0_ch1_clk_cfg; /* 0x12c */ - u32 lcd1_ch1_clk_cfg; /* 0x130 */ - u32 csi0_clk_cfg; /* 0x134 */ - u32 csi1_clk_cfg; /* 0x138 */ - u32 ve_clk_cfg; /* 0x13c */ - u32 audio_codec_clk_cfg; /* 0x140 */ - u32 avs_clk_cfg; /* 0x144 */ - u32 ace_clk_cfg; /* 0x148 */ - u32 lvds_clk_cfg; /* 0x14c */ - u32 hdmi_clk_cfg; /* 0x150 */ - u32 mali_clk_cfg; /* 0x154 */ - u8 res7[0x4]; - u32 mbus_clk_cfg; /* 0x15c */ - u8 res8[0x4]; - u32 gmac_clk_cfg; /* 0x164 */ -}; - -/* apb1 bit field */ -#define APB1_CLK_SRC_OSC24M (0x0 << 24) -#define APB1_CLK_SRC_PLL6 (0x1 << 24) -#define APB1_CLK_SRC_LOSC (0x2 << 24) -#define APB1_CLK_SRC_MASK (0x3 << 24) -#define APB1_CLK_RATE_N_1 (0x0 << 16) -#define APB1_CLK_RATE_N_2 (0x1 << 16) -#define APB1_CLK_RATE_N_4 (0x2 << 16) -#define APB1_CLK_RATE_N_8 (0x3 << 16) -#define APB1_CLK_RATE_N_MASK (3 << 16) -#define APB1_CLK_RATE_M(m) (((m)-1) << 0) -#define APB1_CLK_RATE_M_MASK (0x1f << 0) - -/* apb1 gate field */ -#define APB1_GATE_UART_SHIFT (16) -#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) -#define APB1_GATE_TWI_SHIFT (0) -#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) - -/* clock divide */ -#define AXI_DIV_SHIFT (0) -#define AXI_DIV_1 0 -#define AXI_DIV_2 1 -#define AXI_DIV_3 2 -#define AXI_DIV_4 3 -#define AHB_DIV_SHIFT (4) -#define AHB_DIV_1 0 -#define AHB_DIV_2 1 -#define AHB_DIV_4 2 -#define AHB_DIV_8 3 -#define APB0_DIV_SHIFT (8) -#define APB0_DIV_1 0 -#define APB0_DIV_2 1 -#define APB0_DIV_4 2 -#define APB0_DIV_8 3 -#define CPU_CLK_SRC_SHIFT (16) -#define CPU_CLK_SRC_OSC24M 1 -#define CPU_CLK_SRC_PLL1 2 - -#define CCM_PLL1_CFG_ENABLE_SHIFT 31 -#define CCM_PLL1_CFG_VCO_RST_SHIFT 30 -#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26 -#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25 -#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20 -#define CCM_PLL1_CFG_DIVP_SHIFT 16 -#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13 -#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8 -#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4 -#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3 -#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2 -#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0 - -#define PLL1_CFG_DEFAULT 0xa1005000 - -#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I -/* - * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, - * halving the mbus frequency, so set it to 300 MHz ourselves and base the - * mbus divider on that. - */ -#define PLL6_CFG_DEFAULT 0xa1009900 -#else -#define PLL6_CFG_DEFAULT 0xa1009911 -#endif - -/* nand clock */ -#define NAND_CLK_SRC_OSC24 0 -#define NAND_CLK_DIV_N 0 -#define NAND_CLK_DIV_M 0 - -/* gps clock */ -#define GPS_SCLK_GATING_OFF 0 -#define GPS_RESET 0 - -/* ahb clock gate bit offset */ -#define AHB_GATE_OFFSET_GPS 26 -#define AHB_GATE_OFFSET_SATA 25 -#define AHB_GATE_OFFSET_PATA 24 -#define AHB_GATE_OFFSET_SPI3 23 -#define AHB_GATE_OFFSET_SPI2 22 -#define AHB_GATE_OFFSET_SPI1 21 -#define AHB_GATE_OFFSET_SPI0 20 -#define AHB_GATE_OFFSET_TS0 18 -#define AHB_GATE_OFFSET_EMAC 17 -#define AHB_GATE_OFFSET_ACE 16 -#define AHB_GATE_OFFSET_DLL 15 -#define AHB_GATE_OFFSET_SDRAM 14 -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_MS 12 -#define AHB_GATE_OFFSET_MMC3 11 -#define AHB_GATE_OFFSET_MMC2 10 -#define AHB_GATE_OFFSET_MMC1 9 -#define AHB_GATE_OFFSET_MMC0 8 -#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) -#define AHB_GATE_OFFSET_BIST 7 -#define AHB_GATE_OFFSET_DMA 6 -#define AHB_GATE_OFFSET_SS 5 -#define AHB_GATE_OFFSET_USB_OHCI1 4 -#define AHB_GATE_OFFSET_USB_EHCI1 3 -#define AHB_GATE_OFFSET_USB_OHCI0 2 -#define AHB_GATE_OFFSET_USB_EHCI0 1 -#define AHB_GATE_OFFSET_USB0 0 - -/* ahb clock gate bit offset (second register) */ -#define AHB_GATE_OFFSET_GMAC 17 -#define AHB_GATE_OFFSET_DE_FE0 14 -#define AHB_GATE_OFFSET_DE_BE0 12 -#define AHB_GATE_OFFSET_HDMI 11 -#define AHB_GATE_OFFSET_LCD1 5 -#define AHB_GATE_OFFSET_LCD0 4 -#define AHB_GATE_OFFSET_TVE1 3 -#define AHB_GATE_OFFSET_TVE0 2 - -#define CCM_AHB_GATE_GPS (0x1 << 26) -#define CCM_AHB_GATE_SDRAM (0x1 << 14) -#define CCM_AHB_GATE_DLL (0x1 << 15) -#define CCM_AHB_GATE_ACE (0x1 << 16) - -#define CCM_PLL3_CTRL_M_SHIFT 0 -#define CCM_PLL3_CTRL_M_MASK (0x7f << CCM_PLL3_CTRL_M_SHIFT) -#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) -#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15) -#define CCM_PLL3_CTRL_EN (0x1 << 31) - -#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) -#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) -#define CCM_PLL5_CTRL_M_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) -#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) -#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) -#define CCM_PLL5_CTRL_K_SHIFT 4 -#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) -#define CCM_PLL5_CTRL_K_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_LDO (0x1 << 7) -#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) -#define CCM_PLL5_CTRL_N_SHIFT 8 -#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) -#define CCM_PLL5_CTRL_N_X(n) (n) -#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) -#define CCM_PLL5_CTRL_P_SHIFT 16 -#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) -#define CCM_PLL5_CTRL_P_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_BW (0x1 << 18) -#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) -#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20) -#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f) -#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25) -#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) -#define CCM_PLL5_CTRL_BYPASS (0x1 << 30) -#define CCM_PLL5_CTRL_EN (0x1 << 31) - -#define CCM_PLL6_CTRL_EN 31 -#define CCM_PLL6_CTRL_BYPASS_EN 30 -#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14 -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_K_SHIFT 4 -#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) - -#define CCM_GPS_CTRL_RESET (0x1 << 0) -#define CCM_GPS_CTRL_GATE (0x1 << 1) - -#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15) - -#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) -#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) -#define CCM_MBUS_CTRL_M_X(n) ((n) - 1) -#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) -#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) -#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) -#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) -#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) -#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 -#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 -#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 -#define CCM_MBUS_CTRL_GATE (0x1 << 31) - -#define CCM_NAND_CTRL_M(x) ((x) - 1) -#define CCM_NAND_CTRL_N(x) ((x) << 16) -#define CCM_NAND_CTRL_OSCM24 (0x0 << 24) -#define CCM_NAND_CTRL_PLL6 (0x1 << 24) -#define CCM_NAND_CTRL_PLL5 (0x2 << 24) -#define CCM_NAND_CTRL_ENABLE (0x1 << 31) - -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6 (0x1 << 24) -#define CCM_MMC_CTRL_PLL5 (0x2 << 24) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) - -#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */ -#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */ -#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 -#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - -#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) -#define CCM_LCD_CH0_CTRL_MIPI_PLL 0 /* No mipi pll on sun4i/5i/7i */ -#ifdef CONFIG_MACH_SUN5I -#define CCM_LCD_CH0_CTRL_TVE_RST (0x1 << 29) -#else -#define CCM_LCD_CH0_CTRL_TVE_RST 0 /* No separate tve-rst on sun4i/7i */ -#endif -#define CCM_LCD_CH0_CTRL_RST (0x1 << 30) -#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) - -#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_LCD_CH1_CTRL_HALF_SCLK1 (1 << 11) -#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) -/* Enable / disable both ch1 sclk1 and sclk2 at the same time */ -#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15) - -#define CCM_LVDS_CTRL_RST (1 << 0) - -#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) -#define CCM_HDMI_CTRL_PLL3 (0 << 24) -#define CCM_HDMI_CTRL_PLL7 (1 << 24) -#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) -#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) -/* No separate ddc gate on sun4i, sun5i and sun7i */ -#define CCM_HDMI_CTRL_DDC_GATE 0 -#define CCM_HDMI_CTRL_GATE (0x1 << 31) - -#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 -#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 -#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 -#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) -#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) -#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) -#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) - -#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) -#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7) -#define CCM_USB_CTRL_PHYGATE (0x1 << 8) -/* These 3 are sun6i only, define them as 0 on sun4i */ -#define CCM_USB_CTRL_PHY0_CLK 0 -#define CCM_USB_CTRL_PHY1_CLK 0 -#define CCM_USB_CTRL_PHY2_CLK 0 - -/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ -#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_DE_CTRL_PLL_MASK (3 << 24) -#define CCM_DE_CTRL_PLL3 (0 << 24) -#define CCM_DE_CTRL_PLL7 (1 << 24) -#define CCM_DE_CTRL_PLL5P (2 << 24) -#define CCM_DE_CTRL_RST (1 << 30) -#define CCM_DE_CTRL_GATE (1 << 31) - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -void clock_set_pll3(unsigned int hz); -unsigned int clock_get_pll3(void); -unsigned int clock_get_pll5p(void); -unsigned int clock_get_pll6(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h deleted file mode 100644 index e369370..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Allwinner H6 clock register definitions - * - * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_CLOCK_SUN50I_H6_H -#define _SUNXI_CLOCK_SUN50I_H6_H - -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ - u8 reserved_0x004[12]; - u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ - u8 reserved_0x014[12]; - u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ - u8 reserved_0x020[4]; - u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ - u8 reserved_0x028[4]; - u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ - u8 reserved_0x034[12]; - u32 pll3_cfg; /* 0x040 pll3 (video0) control */ - u8 reserved_0x044[4]; - u32 pll_video1_cfg; /* 0x048 pll video1 control */ - u8 reserved_0x04c[12]; - u32 pll4_cfg; /* 0x058 pll4 (ve) control */ - u8 reserved_0x05c[4]; - u32 pll10_cfg; /* 0x060 pll10 (de) control */ - u8 reserved_0x064[12]; - u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ - u8 reserved_0x074[4]; - u32 pll2_cfg; /* 0x078 pll2 (audio) control */ - u8 reserved_0x07c[148]; - u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ - u8 reserved_0x114[20]; - u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ - u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ - u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ - u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ - u8 reserved_0x138[8]; - u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ - u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ - u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ - u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ - u8 reserved_0x150[8]; - u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ - u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ - u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ - u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ - u8 reserved_0x168[8]; - u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ - u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ - u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ - u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ - u8 reserved_0x180[384]; - u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ - u8 reserved_0x304[12]; - u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ - u8 reserved_0x314[12]; - u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ - u8 reserved_0x324[4]; - u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ - u8 reserved_0x32c[4]; - u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ - u8 reserved_0x334[12]; - u32 pll3_bias; /* 0x340 pll3 (video0) bias */ - u8 reserved_0x344[4]; - u32 pll_video1_bias; /* 0x348 pll video1 bias */ - u8 reserved_0x34c[12]; - u32 pll4_bias; /* 0x358 pll4 (ve) bias */ - u8 reserved_0x35c[4]; - u32 pll10_bias; /* 0x360 pll10 (de) bias */ - u8 reserved_0x364[12]; - u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ - u8 reserved_0x374[4]; - u32 pll2_bias; /* 0x378 pll2 (audio) bias */ - u8 reserved_0x37c[132]; - u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ - u8 reserved_0x404[252]; - u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ - u8 reserved_0x504[12]; - u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ - u8 reserved_0x514[8]; - u32 ahb3_cfg; /* 0x51c AHB3 clock control */ - u32 apb1_cfg; /* 0x520 APB1 clock control */ - u32 apb2_cfg; /* 0x524 APB2 clock control */ - u8 reserved_0x528[24]; - u32 mbus_cfg; /* 0x540 MBUS clock control */ - u8 reserved_0x544[188]; - u32 de_clk_cfg; /* 0x600 DE clock control */ - u8 reserved_0x604[8]; - u32 de_gate_reset; /* 0x60c DE gate/reset control */ - u8 reserved_0x610[16]; - u32 di_clk_cfg; /* 0x620 DI clock control */ - u8 reserved_0x024[8]; - u32 di_gate_reset; /* 0x62c DI gate/reset control */ - u8 reserved_0x630[64]; - u32 gpu_clk_cfg; /* 0x670 GPU clock control */ - u8 reserved_0x674[8]; - u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ - u32 ce_clk_cfg; /* 0x680 CE clock control */ - u8 reserved_0x684[8]; - u32 ce_gate_reset; /* 0x68c CE gate/reset control */ - u32 ve_clk_cfg; /* 0x690 VE clock control */ - u8 reserved_0x694[8]; - u32 ve_gate_reset; /* 0x69c VE gate/reset control */ - u8 reserved_0x6a0[16]; - u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ - u8 reserved_0x6b4[8]; - u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ - u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ - u8 reserved_0x6c4[8]; - u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ - u8 reserved_0x6d0[60]; - u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ - u8 reserved_0x710[12]; - u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ - u8 reserved_0x720[12]; - u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ - u8 reserved_0x730[12]; - u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ - u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ - u8 reserved_0x744[72]; - u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ - u8 reserved_0x790[12]; - u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ - u8 reserved_0x7a0[12]; - u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ - u8 reserved_0x7b0[12]; - u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ - u8 reserved_0x7c0[64]; - u32 dram_clk_cfg; /* 0x800 DRAM clock control */ - u32 mbus_gate; /* 0x804 MBUS gate control */ - u8 reserved_0x808[4]; - u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ - u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ - u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ - u8 reserved_0x818[20]; - u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ - u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ - u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ - u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ - u8 reserved_0x83c[16]; - u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ - u8 reserved_0x850[188]; - u32 uart_gate_reset; /* 0x90c UART gate/reset control */ - u8 reserved_0x910[12]; - u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ - u8 reserved_0x920[28]; - u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ - u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ - u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ - u8 reserved_0x948[36]; - u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ - u8 reserved_0x970[12]; - u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ - u8 reserved_0x980[48]; - u32 ts_clk_cfg; /* 0x9b0 TS clock control */ - u8 reserved_0x9b4[8]; - u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ - u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ - u8 reserved_0x9c4[8]; - u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ - u8 reserved_0x9d0[44]; - u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ - u8 reserved_0xa00[12]; - u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ - u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ - u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ - u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ - u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ - u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ - u8 reserved_0xa24[8]; - u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ - u8 reserved_0xa30[16]; - u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ - u8 reserved_0xa44[8]; - u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ - u8 reserved_0xa50[16]; - u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ - u8 reserved_0xa64[8]; - u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ - u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ - u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ - u8 reserved_0xa78[4]; - u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ - u8 reserved_0xa80[12]; - u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ - u8 reserved_0xa90[32]; - u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ - u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ - u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ - u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ - u8 reserved_0xac0[64]; - u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ - u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ - u8 reserved_0xb08[8]; - u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ - u8 reserved_0xb14[8]; - u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ - u8 reserved_0xb20[60]; - u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ - u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ - u8 reserved_0xb64[24]; - u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ - u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ - u8 reserved_0xb84[24]; - u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ - u8 reserved_0xba0[96]; - u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ - u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ - u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ - u8 reserved_0xc0c[32]; - u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ - u8 reserved_0xc30[16]; - u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ - u8 reserved_0xc44[8]; - u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ - u8 reserved_0xc50[688]; - u32 ccu_sec_switch; /* 0xf00 CCU security switch */ - u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ -}; - -/* pll1 bit field */ -#define CCM_PLL1_CTRL_EN BIT(31) -#define CCM_PLL1_LOCK_EN BIT(29) -#define CCM_PLL1_LOCK BIT(28) -#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) -#define CCM_PLL1_CTRL_P(p) ((p) << 16) -#define CCM_PLL1_CTRL_N(n) ((n) << 8) - -/* pll5 bit field */ -#define CCM_PLL5_CTRL_EN BIT(31) -#define CCM_PLL5_LOCK_EN BIT(29) -#define CCM_PLL5_LOCK BIT(28) -#define CCM_PLL5_CTRL_N(n) ((n) << 8) -#define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) -#define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) - -/* pll6 bit field */ -#define CCM_PLL6_CTRL_EN BIT(31) -#define CCM_PLL6_LOCK_EN BIT(29) -#define CCM_PLL6_LOCK BIT(28) -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_DIV1_SHIFT 0 -#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) -#define CCM_PLL6_CTRL_DIV2_SHIFT 1 -#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) -#define CCM_PLL6_DEFAULT 0xa0006300 - -/* cpu_axi bit field*/ -#define CCM_CPU_AXI_MUX_MASK (0x3 << 24) -#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24) -#define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24) -#define CCM_CPU_AXI_APB_MASK 0x300 -#define CCM_CPU_AXI_AXI_MASK 0x3 -#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 - -/* psi_ahb1_ahb2 bit field */ -#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 - -/* ahb3 bit field */ -#define CCM_AHB3_DEFAULT 0x03000002 - -/* apb1 bit field */ -#define CCM_APB1_DEFAULT 0x03000102 - -/* apb2 bit field */ -#define APB2_CLK_SRC_OSC24M (0x0 << 24) -#define APB2_CLK_SRC_OSC32K (0x1 << 24) -#define APB2_CLK_SRC_PSI (0x2 << 24) -#define APB2_CLK_SRC_PLL6 (0x3 << 24) -#define APB2_CLK_SRC_MASK (0x3 << 24) -#define APB2_CLK_RATE_N_1 (0x0 << 8) -#define APB2_CLK_RATE_N_2 (0x1 << 8) -#define APB2_CLK_RATE_N_4 (0x2 << 8) -#define APB2_CLK_RATE_N_8 (0x3 << 8) -#define APB2_CLK_RATE_N_MASK (3 << 8) -#define APB2_CLK_RATE_M(m) (((m)-1) << 0) -#define APB2_CLK_RATE_M_MASK (3 << 0) - -/* MBUS clock bit field */ -#define MBUS_ENABLE BIT(31) -#define MBUS_RESET BIT(30) -#define MBUS_CLK_SRC_MASK GENMASK(25, 24) -#define MBUS_CLK_SRC_OSCM24 (0 << 24) -#define MBUS_CLK_SRC_PLL6X2 (1 << 24) -#define MBUS_CLK_SRC_PLL5 (2 << 24) -#define MBUS_CLK_SRC_PLL6X4 (3 << 24) -#define MBUS_CLK_M(m) (((m)-1) << 0) - -/* Module gate/reset shift*/ -#define RESET_SHIFT (16) - -/* DRAM clock bit field */ -#define DRAM_MOD_RESET BIT(30) -#define DRAM_CLK_UPDATE BIT(27) -#define DRAM_CLK_SRC_MASK GENMASK(25, 24) -#define DRAM_CLK_SRC_PLL5 (0 << 24) -#define DRAM_CLK_M(m) (((m)-1) << 0) - -/* MMC clock bit field */ -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_N(x) ((x) << 8) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24) -#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) -/* H6 doesn't have these delays */ -#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) -#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -unsigned int clock_get_pll6(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN50I_H6_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h deleted file mode 100644 index ee38712..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ /dev/null @@ -1,533 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun6i clock register definitions - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CLOCK_SUN6I_H -#define _SUNXI_CLOCK_SUN6I_H - -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x00 pll1 control */ - u32 reserved0; - u32 pll2_cfg; /* 0x08 pll2 control */ - u32 reserved1; - u32 pll3_cfg; /* 0x10 pll3 control */ - u32 reserved2; - u32 pll4_cfg; /* 0x18 pll4 control */ - u32 reserved3; - u32 pll5_cfg; /* 0x20 pll5 control */ - u32 reserved4; - u32 pll6_cfg; /* 0x28 pll6 control */ - u32 reserved5; - u32 pll7_cfg; /* 0x30 pll7 control */ - u32 sata_pll_cfg; /* 0x34 SATA pll control (R40 only) */ - u32 pll8_cfg; /* 0x38 pll8 control */ - u32 reserved7; - u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ - u32 pll9_cfg; /* 0x44 pll9 control */ - u32 pll10_cfg; /* 0x48 pll10 control */ - u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */ - u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ - u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ - u32 apb2_div; /* 0x58 APB2 divide ratio */ - u32 axi_gate; /* 0x5c axi module clock gating */ - u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ - u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ - u32 apb1_gate; /* 0x68 apb1 module clock gating */ - u32 apb2_gate; /* 0x6c apb2 module clock gating */ - u32 bus_gate4; /* 0x70 gate 4 module clock gating */ - u8 res3[0xc]; - u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ - u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ - u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ - u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ - u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ - u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ - u32 ts_clk_cfg; /* 0x98 transport stream clock control */ - u32 ss_clk_cfg; /* 0x9c security system clock control */ - u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ - u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ - u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ - u32 spi3_clk_cfg; /* 0xac spi3 clock control */ - u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ - u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ - u32 reserved10[2]; - u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ - u32 reserved11; - u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */ - u32 usb_clk_cfg; /* 0xcc USB clock control */ -#ifdef CONFIG_MACH_SUN8I_R40 - u32 cir0_clk_cfg; /* 0xd0 CIR0 clock control (R40 only) */ -#else - u32 gmac_clk_cfg; /* 0xd0 GMAC clock control (not for R40) */ -#endif - u32 reserved12[7]; - u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ - u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ - u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */ - u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */ - u32 dram_clk_gate; /* 0x100 DRAM module gating */ -#ifdef CONFIG_SUNXI_DE2 - u32 de_clk_cfg; /* 0x104 DE module clock */ -#else - u32 be0_clk_cfg; /* 0x104 BE0 module clock */ -#endif - u32 be1_clk_cfg; /* 0x108 BE1 module clock */ - u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ - u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ - u32 mp_clk_cfg; /* 0x114 MP module clock */ -#ifdef CONFIG_SUNXI_DE2 - u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ - u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ -#else - u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ - u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ -#endif - u32 tve_clk_cfg; /* 0x120 H3/H5 TVE module clock */ - u32 reserved14[2]; - u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ - u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ - u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ - u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ - u32 ve_clk_cfg; /* 0x13c VE module clock */ - u32 adda_clk_cfg; /* 0x140 ADDA module clock */ - u32 avs_clk_cfg; /* 0x144 AVS module clock */ - u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ - u32 reserved15; - u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ -#ifdef CONFIG_SUNXI_DE2 - u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ -#else - u32 ps_clk_cfg; /* 0x154 PS module clock */ -#endif - u32 mtc_clk_cfg; /* 0x158 MTC module clock */ - u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ - u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ -#ifdef CONFIG_MACH_SUN8I_R40 - u32 gmac_clk_cfg; /* 0x164 GMAC clock control (R40 only) */ -#else - u32 reserved16; -#endif - u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ - u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ - u32 reserved17[4]; - u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ - u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ - u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ - u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ - u32 reserved18[4]; - u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ - u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ - u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ - u32 reserved19[21]; - u32 pll_lock; /* 0x200 PLL Lock Time */ - u32 pll1_lock; /* 0x204 PLL1 Lock Time */ - u32 reserved20[6]; - u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ - u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ - u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ - u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ - u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ - u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ - u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ - u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ - u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ - u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ - u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ - u32 reserved21[5]; - u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */ - u32 reserved21_5[7]; - u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ - u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ - u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ - u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ - u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ - u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ - u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ - u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ - u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ - u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ - u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ - u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */ - u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */ - u32 reserved22[3]; - u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ - u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ - u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ - u32 reserved23; - u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ - u32 reserved24; - u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ - u32 reserved25[5]; - u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */ - u32 reserved26[11]; - u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */ -}; - -/* apb2 bit field */ -#define APB2_CLK_SRC_LOSC (0x0 << 24) -#define APB2_CLK_SRC_OSC24M (0x1 << 24) -#define APB2_CLK_SRC_PLL6 (0x2 << 24) -#define APB2_CLK_SRC_MASK (0x3 << 24) -#define APB2_CLK_RATE_N_1 (0x0 << 16) -#define APB2_CLK_RATE_N_2 (0x1 << 16) -#define APB2_CLK_RATE_N_4 (0x2 << 16) -#define APB2_CLK_RATE_N_8 (0x3 << 16) -#define APB2_CLK_RATE_N_MASK (3 << 16) -#define APB2_CLK_RATE_M(m) (((m)-1) << 0) -#define APB2_CLK_RATE_M_MASK (0x1f << 0) - -/* apb2 gate field */ -#define APB2_GATE_UART_SHIFT (16) -#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) -#define APB2_GATE_TWI_SHIFT (0) -#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) - -/* cpu_axi_cfg bits */ -#define AXI_DIV_SHIFT 0 -#define ATB_DIV_SHIFT 8 -#define CPU_CLK_SRC_SHIFT 16 - -#define AXI_DIV_1 0 -#define AXI_DIV_2 1 -#define AXI_DIV_3 2 -#define AXI_DIV_4 3 -#define ATB_DIV_1 0 -#define ATB_DIV_2 1 -#define ATB_DIV_4 2 -#define AHB_DIV_1 0 -#define CPU_CLK_SRC_OSC24M 1 -#define CPU_CLK_SRC_PLL1 2 - -#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0) -#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4) -#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) -#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) -#define CCM_PLL1_CTRL_EN (0x1 << 31) - -#define CCM_PLL3_CTRL_M_SHIFT 0 -#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) -#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_PLL3_CTRL_N_SHIFT 8 -#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT) -#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) -#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) -#define CCM_PLL3_CTRL_LOCK (0x1 << 28) -#define CCM_PLL3_CTRL_EN (0x1 << 31) - -#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) -#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) -#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) -#define CCM_PLL5_CTRL_UPD (0x1 << 20) -#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) -#define CCM_PLL5_CTRL_EN (0x1 << 31) - -#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ - -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_K_SHIFT 4 -#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) -#define CCM_PLL6_CTRL_LOCK (1 << 28) - -#define CCM_SATA_PLL_DEFAULT 0x90005811 /* 100 MHz */ - -#define CCM_MIPI_PLL_CTRL_M_SHIFT 0 -#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) -#define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_MIPI_PLL_CTRL_K_SHIFT 4 -#define CCM_MIPI_PLL_CTRL_K_MASK (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT) -#define CCM_MIPI_PLL_CTRL_K(n) ((((n) - 1) & 0x3) << 4) -#define CCM_MIPI_PLL_CTRL_N_SHIFT 8 -#define CCM_MIPI_PLL_CTRL_N_MASK (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT) -#define CCM_MIPI_PLL_CTRL_N(n) ((((n) - 1) & 0xf) << 8) -#define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22) -#define CCM_MIPI_PLL_CTRL_EN (0x1 << 31) - -#define CCM_PLL10_CTRL_M_SHIFT 0 -#define CCM_PLL10_CTRL_M_MASK (0xf << CCM_PLL10_CTRL_M_SHIFT) -#define CCM_PLL10_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_PLL10_CTRL_N_SHIFT 8 -#define CCM_PLL10_CTRL_N_MASK (0x7f << CCM_PLL10_CTRL_N_SHIFT) -#define CCM_PLL10_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) -#define CCM_PLL10_CTRL_INTEGER_MODE (0x1 << 24) -#define CCM_PLL10_CTRL_LOCK (0x1 << 28) -#define CCM_PLL10_CTRL_EN (0x1 << 31) - -#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8) -#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24) -#define CCM_PLL11_CTRL_UPD (0x1 << 30) -#define CCM_PLL11_CTRL_EN (0x1 << 31) - -#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24) -#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7) -#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16) -#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f) - -#if defined(CONFIG_MACH_SUN50I) -/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ -#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ -#else -#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ -#endif - -#define AXI_GATE_OFFSET_DRAM 0 - -/* ahb_gate0 offsets */ -#ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define AHB_GATE_OFFSET_USB_OHCI3 31 -#define AHB_GATE_OFFSET_USB_OHCI2 30 -#define AHB_GATE_OFFSET_USB_OHCI1 29 -#define AHB_GATE_OFFSET_USB_OHCI0 28 -#define AHB_GATE_OFFSET_USB_EHCI3 27 -#define AHB_GATE_OFFSET_USB_EHCI2 26 -#define AHB_GATE_OFFSET_USB_EHCI1 25 -#define AHB_GATE_OFFSET_USB_EHCI0 24 -#elif defined(CONFIG_MACH_SUN50I) -#define AHB_GATE_OFFSET_USB_OHCI0 28 -#define AHB_GATE_OFFSET_USB_OHCI1 29 -#define AHB_GATE_OFFSET_USB_EHCI0 24 -#define AHB_GATE_OFFSET_USB_EHCI1 25 -#else -#define AHB_GATE_OFFSET_USB_OHCI1 30 -#define AHB_GATE_OFFSET_USB_OHCI0 29 -#define AHB_GATE_OFFSET_USB_EHCI1 27 -#define AHB_GATE_OFFSET_USB_EHCI0 26 -#endif -#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5) -#define AHB_GATE_OFFSET_USB0 23 -#elif !defined(CONFIG_MACH_SUN8I_R40) -#define AHB_GATE_OFFSET_USB0 24 -#else -#define AHB_GATE_OFFSET_USB0 25 -#define AHB_GATE_OFFSET_SATA 24 -#endif -#define AHB_GATE_OFFSET_MCTL 14 -#define AHB_GATE_OFFSET_GMAC 17 -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_NAND1 12 -#define AHB_GATE_OFFSET_MMC3 11 -#define AHB_GATE_OFFSET_MMC2 10 -#define AHB_GATE_OFFSET_MMC1 9 -#define AHB_GATE_OFFSET_MMC0 8 -#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) -#define AHB_GATE_OFFSET_DMA 6 -#define AHB_GATE_OFFSET_SS 5 - -/* ahb_gate1 offsets */ -#define AHB_GATE_OFFSET_DRC0 25 -#define AHB_GATE_OFFSET_DE_FE0 14 -#define AHB_GATE_OFFSET_DE_BE0 12 -#define AHB_GATE_OFFSET_DE 12 -#define AHB_GATE_OFFSET_HDMI 11 -#define AHB_GATE_OFFSET_TVE 9 -#ifndef CONFIG_SUNXI_DE2 -#define AHB_GATE_OFFSET_LCD1 5 -#define AHB_GATE_OFFSET_LCD0 4 -#else -#define AHB_GATE_OFFSET_LCD1 4 -#define AHB_GATE_OFFSET_LCD0 3 -#endif - -#define CCM_NAND_CTRL_M(x) ((x) - 1) -#define CCM_NAND_CTRL_N(x) ((x) << 16) -#define CCM_NAND_CTRL_PLL6 (0x1 << 24) -#define CCM_NAND_CTRL_ENABLE (0x1 << 31) - -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6 (0x1 << 24) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) - -#define CCM_SATA_CTRL_ENABLE (0x1 << 31) -#define CCM_SATA_CTRL_USE_EXTCLK (0x1 << 24) - -#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) -#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) -#define CCM_USB_CTRL_PHY3_RST (0x1 << 3) -/* There is no global phy clk gate on sun6i, define as 0 */ -#define CCM_USB_CTRL_PHYGATE 0 -#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) -#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) -#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) -#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) -#ifdef CONFIG_MACH_SUNXI_H3_H5 -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) -#else -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) -#endif - -#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 -#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 -#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 -#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) -#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) -#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) -#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) - -#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ - -#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) -#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) -#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) -#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) -#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20) -#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20) -#define CCM_DRAMCLK_CFG_SRC_PLL11 (0x1 << 20) /* A64 only */ -#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20) -#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) -#define CCM_DRAMCLK_CFG_RST (0x1 << 31) - -#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ -#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ -#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) - -#define CCM_MBUS_RESET_RESET (0x1 << 31) - -#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 -#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 -#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 -#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - -#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) -#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24) -/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */ -#define CCM_LCD_CH0_CTRL_RST 0 -#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) - -#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_LCD_CH1_CTRL_HALF_SCLK1 0 /* no seperate sclk1 & 2 on sun6i */ -#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) -#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31) - -#define CCM_LCD0_CTRL_GATE (0x1 << 31) -#define CCM_LCD0_CTRL_M(n) ((((n) - 1) & 0xf) << 0) - -#define CCM_LCD1_CTRL_GATE (0x1 << 31) -#define CCM_LCD1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) - -#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) -#define CCM_HDMI_CTRL_PLL3 (0 << 24) -#define CCM_HDMI_CTRL_PLL7 (1 << 24) -#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) -#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) -#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) -#define CCM_HDMI_CTRL_GATE (0x1 << 31) - -#define CCM_HDMI_SLOW_CTRL_DDC_GATE (1 << 31) - -#define CCM_TVE_CTRL_GATE (0x1 << 31) -#define CCM_TVE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) - -#if defined(CONFIG_MACH_SUN50I) -#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */ -#elif defined(CONFIG_MACH_SUN8I) -#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */ -#else -#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ -#endif -#define MBUS_CLK_GATE (0x1 << 31) - -#define CCM_PLL5_PATTERN 0xd1303333 -#define CCM_PLL11_PATTERN 0xf5860000 - -/* ahb_reset0 offsets */ -#ifdef CONFIG_MACH_SUN8I_R40 -#define AHB_RESET_OFFSET_SATA 24 -#endif -#define AHB_RESET_OFFSET_GMAC 17 -#define AHB_RESET_OFFSET_MCTL 14 -#define AHB_RESET_OFFSET_MMC3 11 -#define AHB_RESET_OFFSET_MMC2 10 -#define AHB_RESET_OFFSET_MMC1 9 -#define AHB_RESET_OFFSET_MMC0 8 -#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) -#define AHB_RESET_OFFSET_SS 5 - -/* ahb_reset1 offsets */ -#define AHB_RESET_OFFSET_SAT 26 -#define AHB_RESET_OFFSET_DRC0 25 -#define AHB_RESET_OFFSET_DE_FE0 14 -#define AHB_RESET_OFFSET_DE_BE0 12 -#define AHB_RESET_OFFSET_DE 12 -#define AHB_RESET_OFFSET_HDMI 11 -#define AHB_RESET_OFFSET_HDMI2 10 -#define AHB_RESET_OFFSET_TVE 9 -#ifndef CONFIG_SUNXI_DE2 -#define AHB_RESET_OFFSET_LCD1 5 -#define AHB_RESET_OFFSET_LCD0 4 -#else -#define AHB_RESET_OFFSET_LCD1 4 -#define AHB_RESET_OFFSET_LCD0 3 -#endif - -/* ahb_reset2 offsets */ -#define AHB_RESET_OFFSET_EPHY 2 -#define AHB_RESET_OFFSET_LVDS 0 - -/* apb2 reset */ -#define APB2_RESET_UART_SHIFT (16) -#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) -#define APB2_RESET_TWI_SHIFT (0) -#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) - -/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ -#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_DE_CTRL_PLL_MASK (0xf << 24) -#define CCM_DE_CTRL_PLL3 (0 << 24) -#define CCM_DE_CTRL_PLL7 (1 << 24) -#define CCM_DE_CTRL_PLL6_2X (2 << 24) -#define CCM_DE_CTRL_PLL8 (3 << 24) -#define CCM_DE_CTRL_PLL9 (4 << 24) -#define CCM_DE_CTRL_PLL10 (5 << 24) -#define CCM_DE_CTRL_GATE (1 << 31) - -/* CCM bits common to all Display Engine 2.0 clock ctrl regs */ -#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_DE2_CTRL_PLL_MASK (3 << 24) -#define CCM_DE2_CTRL_PLL6_2X (0 << 24) -#define CCM_DE2_CTRL_PLL10 (1 << 24) -#define CCM_DE2_CTRL_GATE (0x1 << 31) - -/* CCU security switch, H3 only */ -#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2) -#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1) -#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0) - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -void clock_set_pll3(unsigned int hz); -void clock_set_pll3_factors(int m, int n); -void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); -void clock_set_pll10(unsigned int hz); -void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); -void clock_set_mipi_pll(unsigned int hz); -unsigned int clock_get_pll3(void); -unsigned int clock_get_pll6(void); -unsigned int clock_get_mipi_pll(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h deleted file mode 100644 index 14df3cc..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ /dev/null @@ -1,305 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun8i a83t clock register definitions - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * from sun6i.h - */ - -#ifndef _SUNXI_CLOCK_SUN8I_A83T_H -#define _SUNXI_CLOCK_SUN8I_A83T_H - -struct sunxi_ccm_reg { - u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ - u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ - u32 pll2_cfg; /* 0x08 pll2 audio control */ - u32 reserved1; - u32 pll3_cfg; /* 0x10 pll3 video0 control */ - u32 reserved2; - u32 pll4_cfg; /* 0x18 pll4 ve control */ - u32 reserved3; - u32 pll5_cfg; /* 0x20 pll5 ddr control */ - u32 reserved4; - u32 pll6_cfg; /* 0x28 pll6 peripheral control */ - u32 reserved5[3]; /* 0x2c */ - u32 pll7_cfg; /* 0x38 pll7 gpu control */ - u32 reserved6[2]; /* 0x3c */ - u32 pll8_cfg; /* 0x44 pll8 hsic control */ - u32 pll9_cfg; /* 0x48 pll9 de control */ - u32 pll10_cfg; /* 0x4c pll10 video1 control */ - u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ - u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ - u32 apb2_div; /* 0x58 APB2 divide ratio */ - u32 ahb2_div; /* 0x5c AHB2 divide ratio */ - u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ - u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ - u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */ - u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */ - u32 reserved7[2]; /* 0x70 */ - u32 cci400_cfg; /* 0x78 cci400 clock configuration A83T only */ - u32 reserved8; /* 0x7c */ - u32 nand0_clk_cfg; /* 0x80 nand clock control */ - u32 reserved9; /* 0x84 */ - u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ - u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ - u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ - u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ - u32 reserved10; /* 0x98 */ - u32 ss_clk_cfg; /* 0x9c security system clock control */ - u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ - u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ - u32 reserved11[2]; /* 0xa8 */ - u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control */ - u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ - u32 i2s2_clk_cfg; /* 0xb8 I2S2 clock control */ - u32 tdm_clk_cfg; /* 0xbc TDM clock control */ - u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ - u32 reserved12[2]; /* 0xc4 */ - u32 usb_clk_cfg; /* 0xcc USB clock control */ - u32 reserved13[9]; /* 0xd0 */ - u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ - u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register */ - u32 mbus_reset; /* 0xfc MBUS reset control */ - u32 dram_clk_gate; /* 0x100 DRAM module gating */ - u32 reserved14[5]; /* 0x104 BE0 */ - u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ - u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ - u32 reserved15[4]; /* 0x120 */ - u32 mipi_csi_clk_cfg; /* 0x130 MIPI CSI module clock */ - u32 csi_clk_cfg; /* 0x134 CSI module clock */ - u32 reserved16; /* 0x138 */ - u32 ve_clk_cfg; /* 0x13c VE module clock */ - u32 reserved17; /* 0x140 */ - u32 avs_clk_cfg; /* 0x144 AVS module clock */ - u32 reserved18[2]; /* 0x148 */ - u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ - u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ - u32 reserved19; /* 0x158 */ - u32 mbus_clk_cfg; /* 0x15c MBUS module clock */ - u32 reserved20[2]; /* 0x160 */ - u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ - u32 reserved21[13]; /* 0x16c */ - u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ - u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ - u32 gpu_hyd_clk_cfg; /* 0x1a8 GPU HYD clock config */ - u32 reserved22[21]; /* 0x1ac */ - u32 pll_stable0; /* 0x200 PLL stable time 0 */ - u32 pll_stable1; /* 0x204 PLL stable time 1 */ - u32 reserved23; /* 0x208 */ - u32 pll_stable_status; /* 0x20c PLL stable status register */ - u32 reserved24[4]; /* 0x210 */ - u32 pll1_c0_bias_cfg; /* 0x220 PLL1 c0cpu# Bias config */ - u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */ - u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */ - u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */ - u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */ - u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */ - u32 pll1_c1_bias_cfg; /* 0x238 PLL1 c1cpu# Bias config */ - u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */ - u32 reserved25; /* 0x240 */ - u32 pll9_bias_cfg; /* 0x244 PLL9 hsic Bias config */ - u32 de_bias_cfg; /* 0x248 display engine Bias config */ - u32 video1_bias_cfg; /* 0x24c pll video1 bias register */ - u32 c0_tuning_cfg; /* 0x250 pll c0cpu# tuning register */ - u32 c1_tuning_cfg; /* 0x254 pll c1cpu# tuning register */ - u32 reserved26[11]; /* 0x258 */ - u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */ - u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */ - u32 reserved27; /* 0x28c */ - u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/ - u32 reserved28[4]; /* 0x294 */ - u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */ - u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */ - u32 reserved29; /* 0x2ac */ - u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */ - u32 reserved30[3]; /* 0x2b4 */ - u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ - u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ - u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ - u32 reserved31; - u32 ahb_reset3_cfg; /* 0x2d0 AHB1 Reset 3 config */ - u32 reserved32; /* 0x2d4 */ - u32 apb2_reset_cfg; /* 0x2d8 BUS Reset 4 config */ -}; - -/* apb2 bit field */ -#define APB2_CLK_SRC_LOSC (0x0 << 24) -#define APB2_CLK_SRC_OSC24M (0x1 << 24) -#define APB2_CLK_SRC_PLL6 (0x2 << 24) -#define APB2_CLK_SRC_MASK (0x3 << 24) -#define APB2_CLK_RATE_N_1 (0x0 << 16) -#define APB2_CLK_RATE_N_2 (0x1 << 16) -#define APB2_CLK_RATE_N_4 (0x2 << 16) -#define APB2_CLK_RATE_N_8 (0x3 << 16) -#define APB2_CLK_RATE_N_MASK (3 << 16) -#define APB2_CLK_RATE_M(m) (((m)-1) << 0) -#define APB2_CLK_RATE_M_MASK (0x1f << 0) - -/* apb2 gate field */ -#define APB2_GATE_UART_SHIFT (16) -#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) -#define APB2_GATE_TWI_SHIFT (0) -#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) - -/* cpu_axi_cfg bits */ -#define AXI0_DIV_SHIFT 0 -#define AXI1_DIV_SHIFT 16 -#define C0_CPUX_CLK_SRC_SHIFT 12 -#define C1_CPUX_CLK_SRC_SHIFT 28 - -#define AXI_DIV_1 0 -#define AXI_DIV_2 1 -#define AXI_DIV_3 2 -#define AXI_DIV_4 3 -#define CPU_CLK_SRC_OSC24M 0 -#define CPU_CLK_SRC_PLL1 1 - -#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) -#define CCM_PLL1_CTRL_EN (0x1 << 31) -#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24) - -#define PLL8_CFG_DEFAULT 0x42800 -#define CCM_CCI400_CLK_SEL_HSIC (0x2<<24) - -#define CCM_PLL5_DIV1_SHIFT 16 -#define CCM_PLL5_DIV2_SHIFT 18 -#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) -#define CCM_PLL5_CTRL_UPD (0x1 << 30) -#define CCM_PLL5_CTRL_EN (0x1 << 31) - -#define PLL6_CFG_DEFAULT 0x80001900 /* 600 MHz */ -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_DIV1_SHIFT 16 -#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) -#define CCM_PLL6_CTRL_DIV2_SHIFT 18 -#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) - -#define AHB1_ABP1_DIV_DEFAULT 0x00002190 -#define AHB1_CLK_SRC_MASK (0x3<<12) -#define AHB1_CLK_SRC_INTOSC (0x0<<12) -#define AHB1_CLK_SRC_OSC24M (0x1<<12) -#define AHB1_CLK_SRC_PLL6 (0x2<<12) - -#define AXI_GATE_OFFSET_DRAM 0 - -/* ahb_gate0 offsets */ -#define AHB_GATE_OFFSET_USB_OHCI1 30 -#define AHB_GATE_OFFSET_USB_OHCI0 29 -#define AHB_GATE_OFFSET_USB_EHCI1 27 -#define AHB_GATE_OFFSET_USB_EHCI0 26 -#define AHB_GATE_OFFSET_USB0 24 -#define AHB_GATE_OFFSET_SPI1 21 -#define AHB_GATE_OFFSET_SPI0 20 -#define AHB_GATE_OFFSET_HSTIMER 19 -#define AHB_GATE_OFFSET_EMAC 17 -#define AHB_GATE_OFFSET_MCTL 14 -#define AHB_GATE_OFFSET_GMAC 17 -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_MMC0 8 -#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) -#define AHB_GATE_OFFSET_DMA 6 -#define AHB_GATE_OFFSET_SS 5 - -/* ahb_gate1 offsets */ -#define AHB_GATE_OFFSET_DRC0 25 -#define AHB_GATE_OFFSET_DE_FE0 14 -#define AHB_GATE_OFFSET_DE_BE0 12 -#define AHB_GATE_OFFSET_HDMI 11 -#define AHB_GATE_OFFSET_LCD1 5 -#define AHB_GATE_OFFSET_LCD0 4 - -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6 (0x1 << 24) -#define CCM_MMC_CTRL_MODE_SEL_NEW (0x1 << 30) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) - -#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) -#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_HSIC_RST (0x1 << 2) -/* There is no global phy clk gate on sun6i, define as 0 */ -#define CCM_USB_CTRL_PHYGATE 0 -#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) -#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) -#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10) -#define CCM_USB_CTRL_12M_CLK (0x1 << 11) -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) - -#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 -#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 -#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 -#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) -#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) -#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) -#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) - -#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ - -#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) -#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) -#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) -#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) -#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) -#define CCM_DRAMCLK_CFG_RST (0x1 << 31) - -#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ -#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ -#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) - -#define CCM_MBUS_RESET_RESET (0x1 << 31) - -#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 -#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 -#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 -#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - - -#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ - -#define MBUS_CLK_GATE (0x1 << 31) - -/* ahb_reset0 offsets */ -#define AHB_RESET_OFFSET_GMAC 17 -#define AHB_RESET_OFFSET_MCTL 14 -#define AHB_RESET_OFFSET_MMC3 11 -#define AHB_RESET_OFFSET_MMC2 10 -#define AHB_RESET_OFFSET_MMC1 9 -#define AHB_RESET_OFFSET_MMC0 8 -#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) -#define AHB_RESET_OFFSET_SS 5 - -/* ahb_reset1 offsets */ -#define AHB_RESET_OFFSET_SAT 26 -#define AHB_RESET_OFFSET_DRC0 25 -#define AHB_RESET_OFFSET_DE_FE0 14 -#define AHB_RESET_OFFSET_DE_BE0 12 -#define AHB_RESET_OFFSET_HDMI 11 -#define AHB_RESET_OFFSET_LCD1 5 -#define AHB_RESET_OFFSET_LCD0 4 - -/* ahb_reset2 offsets */ -#define AHB_RESET_OFFSET_LVDS 0 - -/* apb2 reset */ -#define APB2_RESET_UART_SHIFT (16) -#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) -#define APB2_RESET_TWI_SHIFT (0) -#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) - - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -void clock_set_pll5(unsigned int clk); -unsigned int clock_get_pll6(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h deleted file mode 100644 index 530e0dd..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun9i clock register definitions - * - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_CLOCK_SUN9I_H -#define _SUNXI_CLOCK_SUN9I_H - -struct sunxi_ccm_reg { - u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ - u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ - u32 pll3_audio_cfg; /* 0x08 audio pll configuration */ - u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ - u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */ - u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */ - u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */ - u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */ - u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */ - u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */ - u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */ - u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */ - u8 reserved1[0x20]; /* 0x30 */ - u32 cpu_clk_source; /* 0x50 cpu clk source configuration */ - u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */ - u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */ - u32 gtbus_cfg; /* 0x5c gtbus clock configuration */ - u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */ - u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */ - u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */ - u8 reserved2[0x04]; /* 0x6c */ - u32 apb0_cfg; /* 0x70 apb0 clock configuration */ - u32 apb1_cfg; /* 0x74 apb1 clock configuration */ - u32 cci400_cfg; /* 0x78 cci400 clock configuration */ - u8 reserved3[0x04]; /* 0x7c */ - u32 ats_cfg; /* 0x80 ats clock configuration */ - u32 trace_cfg; /* 0x84 trace clock configuration */ - u8 reserved4[0x14]; /* 0x88 */ - u32 pll_stable_status; /* 0x9c */ - u8 reserved5[0xe0]; /* 0xa0 */ - u32 clk_output_a; /* 0x180 clk_output_a */ - u32 clk_output_b; /* 0x184 clk_output_a */ - u8 reserved6[0x278]; /* 0x188 */ - - u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ - u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ - u8 reserved7[0x08]; /* 0x408 */ - u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ - u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */ - u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */ - u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */ - u8 reserved8[0x08]; /* 0x420 */ - u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */ - u32 ss_clk_cfg; /* 0x42c security system clock cfg */ - u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */ - u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */ - u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */ - u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */ - u8 reserved9[0x44]; /* 0x440 */ - u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */ - u8 reserved10[0x8]; /* 0x488 */ - u32 de_clk_cfg; /* 0x490 display engine clock configuration */ - u8 reserved11[0x04]; /* 0x494 */ - u32 mp_clk_cfg; /* 0x498 mp clock configuration */ - u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */ - u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */ - u8 reserved12[0x1c]; /* 0x4a4 */ - u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */ - u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */ - u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */ - u32 fd_clk_cfg; /* 0x4cc FD module clock */ - u32 ve_clk_cfg; /* 0x4d0 VE module clock */ - u32 avs_clk_cfg; /* 0x4d4 AVS module clock */ - u8 reserved13[0x18]; /* 0x4d8 */ - u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */ - u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */ - u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */ - u8 reserved14[0x10]; /* 0x4fc */ - u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */ - u8 reserved15[0x70]; /* 0x510 */ - - u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ - u32 ahb_gate1; /* 0x584 AHB1 Gating Register */ - u32 ahb_gate2; /* 0x588 AHB2 Gating Register */ - u8 reserved16[0x04]; /* 0x58c */ - u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */ - u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */ - u8 reserved17[0x08]; /* 0x598 */ - u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ - u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ - u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */ - u8 reserved18[0x04]; /* 0x5ac */ - u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */ - u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ -}; - -#define CCM_PLL4_CTRL_N_SHIFT 8 -#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) -#define CCM_PLL4_CTRL_P_SHIFT 16 -#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT) -#define CCM_PLL4_CTRL_M_SHIFT 18 -#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) - -/* pllx_cfg bits */ -#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) -#define CCM_PLL1_CTRL_EN (1 << 31) -#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) - -#define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16) -#define CCM_PLL2_CTRL_EN (1 << 31) -#define CCM_PLL2_CLOCK_TIME_2 (2 << 24) - -#define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL4_CTRL_EN (1 << 31) - -#define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16) -#define CCM_PLL6_CTRL_EN (1 << 31) -#define CCM_PLL6_CFG_UPDATE (1 << 30) - -#define CCM_PLL12_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL12_CTRL_EN (1 << 31) - -#define PLL_C0CPUX_STATUS (1 << 0) -#define PLL_C1CPUX_STATUS (1 << 1) -#define PLL_DDR_STATUS (1 << 5) -#define PLL_PERIPH1_STATUS (1 << 11) - -/* cpu_clk_source bits */ -#define C0_CPUX_CLK_SRC_SHIFT 0 -#define C1_CPUX_CLK_SRC_SHIFT 8 -#define C0_CPUX_CLK_SRC_MASK (1 << C0_CPUX_CLK_SRC_SHIFT) -#define C1_CPUX_CLK_SRC_MASK (1 << C1_CPUX_CLK_SRC_SHIFT) -#define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT) -#define C0_CPUX_CLK_SRC_PLL1 (1 << C0_CPUX_CLK_SRC_SHIFT) -#define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT) -#define C1_CPUX_CLK_SRC_PLL2 (1 << C1_CPUX_CLK_SRC_SHIFT) - -/* c0_cfg */ -#define C0_CFG_AXI0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) -#define C0_CFG_APB0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 8) - -/* ahbx_cfg */ -#define AHBx_SRC_CLK_SELECT_SHIFT 24 -#define AHBx_SRC_MASK (0x3 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHB0_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHB1_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHB2_SRC_OSC24M (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHBx_SRC_PLL_PERIPH0 (0x1 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHBx_SRC_PLL_PERIPH1 (0x2 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHBx_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) - -/* apb0_cfg */ -#define APB0_SRC_CLK_SELECT_SHIFT 24 -#define APB0_SRC_MASK (0x1 << APB0_SRC_CLK_SELECT_SHIFT) -#define APB0_SRC_OSC24M (0x0 << APB0_SRC_CLK_SELECT_SHIFT) -#define APB0_SRC_PLL_PERIPH0 (0x1 << APB0_SRC_CLK_SELECT_SHIFT) -#define APB0_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) - -/* gtbus_clk_cfg */ -#define GTBUS_SRC_CLK_SELECT_SHIFT 24 -#define GTBUS_SRC_MASK (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_SRC_OSC24M (0x0 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_SRC_PLL_PERIPH0 (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_SRC_PLL_PERIPH1 (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) - -/* cci400_clk_cfg */ -#define CCI400_SRC_CLK_SELECT_SHIFT 24 -#define CCI400_SRC_MASK (0x3 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_SRC_OSC24M (0x0 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_SRC_PLL_PERIPH0 (0x1 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_SRC_PLL_PERIPH1 (0x2 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) - -/* sd#_clk_cfg fields */ -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0 << 24) -#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) -#define CCM_MMC_CTRL_ENABLE (1 << 31) - -/* ahb_gate0 fields */ -#define AHB_GATE_OFFSET_MCTL 14 - -/* On sun9i all sdc-s share their ahb gate, so ignore (x) */ -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_MMC(x) 8 - -/* ahb gate1 field */ -#define AHB_GATE_OFFSET_DMA 24 - -/* apb1_gate fields */ -#define APB1_GATE_UART_SHIFT 16 -#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) -#define APB1_GATE_TWI_SHIFT 0 -#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) - -/* ahb_reset0_cfg fields */ -#define AHB_RESET_OFFSET_MCTL 14 - -/* On sun9i all sdc-s share their ahb reset, so ignore (x) */ -#define AHB_RESET_OFFSET_MMC(x) 8 - -/* apb1_reset_cfg fields */ -#define APB1_RESET_UART_SHIFT 16 -#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT) -#define APB1_RESET_TWI_SHIFT 0 -#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) - - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int clk); -void clock_set_pll2(unsigned int clk); -void clock_set_pll4(unsigned int clk); -void clock_set_pll6(unsigned int clk); -void clock_set_pll12(unsigned int clk); -unsigned int clock_get_pll4_periph0(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h deleted file mode 100644 index 4c399b0..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_CPU_H -#define _SUNXI_CPU_H - -#if defined(CONFIG_MACH_SUN9I) -#include <asm/arch/cpu_sun9i.h> -#elif defined(CONFIG_MACH_SUN50I_H6) -#include <asm/arch/cpu_sun50i_h6.h> -#else -#include <asm/arch/cpu_sun4i.h> -#endif - -#define SOCID_A64 0x1689 -#define SOCID_H3 0x1680 -#define SOCID_H5 0x1718 -#define SOCID_R40 0x1701 - -#endif /* _SUNXI_CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h deleted file mode 100644 index 02ce739..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CPU_SUN4I_H -#define _SUNXI_CPU_SUN4I_H - -#define SUNXI_SRAM_A1_BASE 0x00000000 -#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ - -#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ -#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ -#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ -#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ -#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ - -#define SUNXI_DE2_BASE 0x01000000 - -#ifdef CONFIG_MACH_SUN8I_A83T -#define SUNXI_CPUCFG_BASE 0x01700000 -#endif - -#define SUNXI_SRAMC_BASE 0x01c00000 -#define SUNXI_DRAMC_BASE 0x01c01000 -#define SUNXI_DMA_BASE 0x01c02000 -#define SUNXI_NFC_BASE 0x01c03000 -#define SUNXI_TS_BASE 0x01c04000 -#define SUNXI_SPI0_BASE 0x01c05000 -#define SUNXI_SPI1_BASE 0x01c06000 -#define SUNXI_MS_BASE 0x01c07000 -#define SUNXI_TVD_BASE 0x01c08000 -#define SUNXI_CSI0_BASE 0x01c09000 -#ifndef CONFIG_MACH_SUNXI_H3_H5 -#define SUNXI_TVE0_BASE 0x01c0a000 -#endif -#define SUNXI_EMAC_BASE 0x01c0b000 -#define SUNXI_LCD0_BASE 0x01c0C000 -#define SUNXI_LCD1_BASE 0x01c0d000 -#define SUNXI_VE_BASE 0x01c0e000 -#define SUNXI_MMC0_BASE 0x01c0f000 -#define SUNXI_MMC1_BASE 0x01c10000 -#define SUNXI_MMC2_BASE 0x01c11000 -#define SUNXI_MMC3_BASE 0x01c12000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_USB0_BASE 0x01c13000 -#define SUNXI_USB1_BASE 0x01c14000 -#endif -#define SUNXI_SS_BASE 0x01c15000 -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) -#define SUNXI_HDMI_BASE 0x01c16000 -#endif -#define SUNXI_SPI2_BASE 0x01c17000 -#define SUNXI_SATA_BASE 0x01c18000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_PATA_BASE 0x01c19000 -#define SUNXI_ACE_BASE 0x01c1a000 -#define SUNXI_TVE1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 -#endif -#ifdef CONFIG_SUNXI_GEN_SUN6I -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) -#define SUNXI_USBPHY_BASE 0x01c19000 -#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#define SUNXI_USB3_BASE 0x01c1c000 -#define SUNXI_USB4_BASE 0x01c1d000 -#else -#define SUNXI_USB0_BASE 0x01c19000 -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#endif -#endif -#define SUNXI_CSI1_BASE 0x01c1d000 -#define SUNXI_TZASC_BASE 0x01c1e000 -#define SUNXI_SPI3_BASE 0x01c1f000 - -#define SUNXI_CCM_BASE 0x01c20000 -#define SUNXI_INTC_BASE 0x01c20400 -#define SUNXI_PIO_BASE 0x01c20800 -#define SUNXI_TIMER_BASE 0x01c20c00 -#ifndef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_PWM_BASE 0x01c20e00 -#endif -#define SUNXI_SPDIF_BASE 0x01c21000 -#ifdef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_PWM_BASE 0x01c21400 -#else -#define SUNXI_AC97_BASE 0x01c21400 -#endif -#define SUNXI_IR0_BASE 0x01c21800 -#define SUNXI_IR1_BASE 0x01c21c00 - -#define SUNXI_IIS_BASE 0x01c22400 -#define SUNXI_LRADC_BASE 0x01c22800 -#define SUNXI_AD_DA_BASE 0x01c22c00 -#define SUNXI_KEYPAD_BASE 0x01c23000 -#define SUNXI_TZPC_BASE 0x01c23400 - -#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ -defined(CONFIG_MACH_SUN50I) -/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ -#define SUNXI_SIDC_BASE 0x01c14000 -#define SUNXI_SID_BASE 0x01c14200 -#else -#define SUNXI_SID_BASE 0x01c23800 -#endif - -#define SUNXI_SJTAG_BASE 0x01c23c00 - -#define SUNXI_TP_BASE 0x01c25000 -#define SUNXI_PMU_BASE 0x01c25400 - -#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 -#define SUNXI_CPUCFG_BASE 0x01c25c00 -#endif - -#define SUNXI_UART0_BASE 0x01c28000 -#define SUNXI_UART1_BASE 0x01c28400 -#define SUNXI_UART2_BASE 0x01c28800 -#define SUNXI_UART3_BASE 0x01c28c00 -#define SUNXI_UART4_BASE 0x01c29000 -#define SUNXI_UART5_BASE 0x01c29400 -#define SUNXI_UART6_BASE 0x01c29800 -#define SUNXI_UART7_BASE 0x01c29c00 -#define SUNXI_PS2_0_BASE 0x01c2a000 -#define SUNXI_PS2_1_BASE 0x01c2a400 - -#define SUNXI_TWI0_BASE 0x01c2ac00 -#define SUNXI_TWI1_BASE 0x01c2b000 -#define SUNXI_TWI2_BASE 0x01c2b400 -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_TWI3_BASE 0x01c0b800 -#endif -#ifdef CONFIG_MACH_SUN7I -#define SUNXI_TWI3_BASE 0x01c2b800 -#define SUNXI_TWI4_BASE 0x01c2c000 -#endif - -#define SUNXI_CAN_BASE 0x01c2bc00 - -#define SUNXI_SCR_BASE 0x01c2c400 - -#ifndef CONFIG_MACH_SUN6I -#define SUNXI_GPS_BASE 0x01c30000 -#define SUNXI_MALI400_BASE 0x01c40000 -#define SUNXI_GMAC_BASE 0x01c50000 -#else -#define SUNXI_GMAC_BASE 0x01c30000 -#endif - -#define SUNXI_DRAM_COM_BASE 0x01c62000 -#define SUNXI_DRAM_CTL0_BASE 0x01c63000 -#define SUNXI_DRAM_CTL1_BASE 0x01c64000 -#define SUNXI_DRAM_PHY0_BASE 0x01c65000 -#define SUNXI_DRAM_PHY1_BASE 0x01c66000 - -#define SUNXI_GIC400_BASE 0x01c80000 - -/* module sram */ -#define SUNXI_SRAM_C_BASE 0x01d00000 - -#ifndef CONFIG_MACH_SUN8I_H3 -#define SUNXI_DE_FE0_BASE 0x01e00000 -#else -#define SUNXI_TVE0_BASE 0x01e00000 -#endif -#define SUNXI_DE_FE1_BASE 0x01e20000 -#define SUNXI_DE_BE0_BASE 0x01e60000 -#ifndef CONFIG_MACH_SUN50I_H5 -#define SUNXI_DE_BE1_BASE 0x01e40000 -#else -#define SUNXI_TVE0_BASE 0x01e40000 -#endif -#define SUNXI_MP_BASE 0x01e80000 -#define SUNXI_AVG_BASE 0x01ea0000 - -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) -#define SUNXI_HDMI_BASE 0x01ee0000 -#endif - -#define SUNXI_RTC_BASE 0x01f00000 -#define SUNXI_PRCM_BASE 0x01f01400 - -#if defined CONFIG_SUNXI_GEN_SUN6I && \ - !defined CONFIG_MACH_SUN8I_A83T && \ - !defined CONFIG_MACH_SUN8I_R40 -#define SUNXI_CPUCFG_BASE 0x01f01c00 -#endif - -#define SUNXI_R_TWI_BASE 0x01f02400 -#define SUNXI_R_UART_BASE 0x01f02800 -#define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUN6I_P2WI_BASE 0x01f03400 -#define SUNXI_RSB_BASE 0x01f03400 - -/* CoreSight Debug Module */ -#define SUNXI_CSDM_BASE 0x3f500000 - -#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ - -#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ - -#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) - -/* SS bonding ids used for cpu identification */ -#define SUNXI_SS_BOND_ID_A31 4 -#define SUNXI_SS_BOND_ID_A31S 5 - -#ifndef __ASSEMBLY__ -void sunxi_board_init(void); -void sunxi_reset(void); -int sunxi_get_ss_bonding_id(void); -int sunxi_get_sid(unsigned int *sid); -#endif /* __ASSEMBLY__ */ - -#endif /* _SUNXI_CPU_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h deleted file mode 100644 index 6392cb0..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_CPU_SUN50I_H6_H -#define _SUNXI_CPU_SUN50I_H6_H - -#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS -#define SUNXI_SRAM_C_BASE 0x00028000 -#define SUNXI_SRAM_A2_BASE 0x00100000 - -#define SUNXI_DE3_BASE 0x01000000 -#define SUNXI_SS_BASE 0x01904000 -#define SUNXI_EMCE_BASE 0x01905000 - -#define SUNXI_SRAMC_BASE 0x03000000 -#define SUNXI_CCM_BASE 0x03001000 -#define SUNXI_DMA_BASE 0x03002000 -/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ -#define SUNXI_SIDC_BASE 0x03006000 -#define SUNXI_SID_BASE 0x03006200 -#define SUNXI_TIMER_BASE 0x03009000 -#define SUNXI_PIO_BASE 0x0300B000 -#define SUNXI_PSI_BASE 0x0300C000 - -#define SUNXI_GIC400_BASE 0x03020000 -#define SUNXI_IOMMU_BASE 0x030F0000 - -#define SUNXI_DRAM_COM_BASE 0x04002000 -#define SUNXI_DRAM_CTL0_BASE 0x04003000 -#define SUNXI_DRAM_PHY0_BASE 0x04005000 -#define SUNXI_NFC_BASE 0x04011000 -#define SUNXI_MMC0_BASE 0x04020000 -#define SUNXI_MMC1_BASE 0x04021000 -#define SUNXI_MMC2_BASE 0x04022000 - -#define SUNXI_UART0_BASE 0x05000000 -#define SUNXI_UART1_BASE 0x05000400 -#define SUNXI_UART2_BASE 0x05000800 -#define SUNXI_UART3_BASE 0x05000C00 -#define SUNXI_TWI0_BASE 0x05002000 -#define SUNXI_TWI1_BASE 0x05002400 -#define SUNXI_TWI2_BASE 0x05002800 -#define SUNXI_TWI3_BASE 0x05002C00 -#define SUNXI_SPI0_BASE 0x05010000 -#define SUNXI_SPI1_BASE 0x05011000 -#define SUNXI_GMAC_BASE 0x05020000 -#define SUNXI_USB0_BASE 0x05100000 -#define SUNXI_XHCI_BASE 0x05200000 -#define SUNXI_USB3_BASE 0x05311000 -#define SUNXI_PCIE_BASE 0x05400000 - -#define SUNXI_HDMI_BASE 0x06000000 -#define SUNXI_TCON_TOP_BASE 0x06510000 -#define SUNXI_TCON_LCD0_BASE 0x06511000 -#define SUNXI_TCON_TV0_BASE 0x06515000 - -#define SUNXI_RTC_BASE 0x07000000 -#define SUNXI_R_CPUCFG_BASE 0x07000400 -#define SUNXI_PRCM_BASE 0x07010000 -#define SUNXI_R_WDOG_BASE 0x07020400 -#define SUNXI_R_PIO_BASE 0x07022000 -#define SUNXI_R_UART_BASE 0x07080000 -#define SUNXI_R_TWI_BASE 0x07081400 - -#ifndef __ASSEMBLY__ -void sunxi_board_init(void); -void sunxi_reset(void); -int sunxi_get_sid(unsigned int *sid); -#endif - -#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h deleted file mode 100644 index 9c2d11b..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Jerry Wang <wangflord@allwinnertech.com> - */ - -#ifndef _SUNXI_CPU_SUN9I_H -#define _SUNXI_CPU_SUN9I_H - -#define REGS_AHB0_BASE 0x01C00000 -#define REGS_AHB1_BASE 0x00800000 -#define REGS_AHB2_BASE 0x03000000 -#define REGS_APB0_BASE 0x06000000 -#define REGS_APB1_BASE 0x07000000 -#define REGS_RCPUS_BASE 0x08000000 - -#define SUNXI_SRAM_D_BASE 0x08100000 - -/* AHB0 Module */ -#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) -#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) - -#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) -/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ -#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200) - -#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) -#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) -#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) -#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) -#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) - -#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) -#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) -#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) -#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) - -#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) -#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) -#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) - -#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) -#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) -#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) -#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) -#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) - -/* AHB1 Module */ -#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) -#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) -#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) -#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) -#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) - -/* AHB2 Module */ -#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) -#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) -#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) -#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) -#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) - -#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) -#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) -#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) - -#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) -#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) -#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) -#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) - -#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) -#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) -#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) -#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) -/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ -#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) -#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) - -/* APB0 Module */ -#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) -#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) -#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) -#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) -#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) -#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) - -/* APB1 Module */ -#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) -#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) -#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) -#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) -#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) -#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) -#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) -#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) -#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) -#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) -#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) - -/* RCPUS Module */ -#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) -#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) -#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) -#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) - -/* Misc. */ -#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ -#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) - -#ifndef __ASSEMBLY__ -void sunxi_board_init(void); -void sunxi_reset(void); -int sunxi_get_sid(unsigned int *sid); -#endif - -#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h deleted file mode 100644 index 4aaebe0..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpucfg.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi A31 CPUCFG register definition. - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com - */ - -#ifndef _SUNXI_CPUCFG_H -#define _SUNXI_CPUCFG_H - -#include <linux/compiler.h> -#include <linux/types.h> - -#ifndef __ASSEMBLY__ - -struct __packed sunxi_cpucfg_cpu { - u32 rst; /* base + 0x0 */ - u32 ctrl; /* base + 0x4 */ - u32 status; /* base + 0x8 */ - u8 res[0x34]; /* base + 0xc */ -}; - -struct __packed sunxi_cpucfg_reg { - u8 res0[0x40]; /* 0x000 */ - struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */ - u8 res1[0x44]; /* 0x140 */ - u32 gen_ctrl; /* 0x184 */ - u32 l2_status; /* 0x188 */ - u8 res2[0x4]; /* 0x18c */ - u32 event_in; /* 0x190 */ - u8 res3[0xc]; /* 0x194 */ - u32 super_standy_flag; /* 0x1a0 */ - u32 priv0; /* 0x1a4 */ - u32 priv1; /* 0x1a8 */ - u8 res4[0x4]; /* 0x1ac */ - u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */ - u32 cpu1_pwroff; /* 0x1b4 sun7i only */ - u8 res5[0x2c]; /* 0x1b8 */ - u32 dbg_ctrl1; /* 0x1e4 */ - u8 res6[0x18]; /* 0x1e8 */ - u32 idle_cnt0_low; /* 0x200 */ - u32 idle_cnt0_high; /* 0x204 */ - u32 idle_cnt0_ctrl; /* 0x208 */ - u8 res8[0x4]; /* 0x20c */ - u32 idle_cnt1_low; /* 0x210 */ - u32 idle_cnt1_high; /* 0x214 */ - u32 idle_cnt1_ctrl; /* 0x218 */ - u8 res9[0x4]; /* 0x21c */ - u32 idle_cnt2_low; /* 0x220 */ - u32 idle_cnt2_high; /* 0x224 */ - u32 idle_cnt2_ctrl; /* 0x228 */ - u8 res10[0x4]; /* 0x22c */ - u32 idle_cnt3_low; /* 0x230 */ - u32 idle_cnt3_high; /* 0x234 */ - u32 idle_cnt3_ctrl; /* 0x238 */ - u8 res11[0x4]; /* 0x23c */ - u32 idle_cnt4_low; /* 0x240 */ - u32 idle_cnt4_high; /* 0x244 */ - u32 idle_cnt4_ctrl; /* 0x248 */ - u8 res12[0x34]; /* 0x24c */ - u32 cnt64_ctrl; /* 0x280 */ - u32 cnt64_low; /* 0x284 */ - u32 cnt64_high; /* 0x288 */ -}; - -#endif /* __ASSEMBLY__ */ -#endif /* _SUNXI_CPUCFG_H */ diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h deleted file mode 100644 index 525f9cb..0000000 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ /dev/null @@ -1,352 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform display controller register and constant defines - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DISPLAY_H -#define _SUNXI_DISPLAY_H - -struct sunxi_de_fe_reg { - u32 enable; /* 0x000 */ - u32 frame_ctrl; /* 0x004 */ - u32 bypass; /* 0x008 */ - u32 algorithm_sel; /* 0x00c */ - u32 line_int_ctrl; /* 0x010 */ - u8 res0[0x0c]; /* 0x014 */ - u32 ch0_addr; /* 0x020 */ - u32 ch1_addr; /* 0x024 */ - u32 ch2_addr; /* 0x028 */ - u32 field_sequence; /* 0x02c */ - u32 ch0_offset; /* 0x030 */ - u32 ch1_offset; /* 0x034 */ - u32 ch2_offset; /* 0x038 */ - u8 res1[0x04]; /* 0x03c */ - u32 ch0_stride; /* 0x040 */ - u32 ch1_stride; /* 0x044 */ - u32 ch2_stride; /* 0x048 */ - u32 input_fmt; /* 0x04c */ - u32 ch3_addr; /* 0x050 */ - u32 ch4_addr; /* 0x054 */ - u32 ch5_addr; /* 0x058 */ - u32 output_fmt; /* 0x05c */ - u32 int_enable; /* 0x060 */ - u32 int_status; /* 0x064 */ - u32 status; /* 0x068 */ - u8 res2[0x04]; /* 0x06c */ - u32 csc_coef00; /* 0x070 */ - u32 csc_coef01; /* 0x074 */ - u32 csc_coef02; /* 0x078 */ - u32 csc_coef03; /* 0x07c */ - u32 csc_coef10; /* 0x080 */ - u32 csc_coef11; /* 0x084 */ - u32 csc_coef12; /* 0x088 */ - u32 csc_coef13; /* 0x08c */ - u32 csc_coef20; /* 0x090 */ - u32 csc_coef21; /* 0x094 */ - u32 csc_coef22; /* 0x098 */ - u32 csc_coef23; /* 0x09c */ - u32 deinterlace_ctrl; /* 0x0a0 */ - u32 deinterlace_diag; /* 0x0a4 */ - u32 deinterlace_tempdiff; /* 0x0a8 */ - u32 deinterlace_sawtooth; /* 0x0ac */ - u32 deinterlace_spatcomp; /* 0x0b0 */ - u32 deinterlace_burstlen; /* 0x0b4 */ - u32 deinterlace_preluma; /* 0x0b8 */ - u32 deinterlace_tile_addr; /* 0x0bc */ - u32 deinterlace_tile_stride; /* 0x0c0 */ - u8 res3[0x0c]; /* 0x0c4 */ - u32 wb_stride_enable; /* 0x0d0 */ - u32 ch3_stride; /* 0x0d4 */ - u32 ch4_stride; /* 0x0d8 */ - u32 ch5_stride; /* 0x0dc */ - u32 fe_3d_ctrl; /* 0x0e0 */ - u32 fe_3d_ch0_addr; /* 0x0e4 */ - u32 fe_3d_ch1_addr; /* 0x0e8 */ - u32 fe_3d_ch2_addr; /* 0x0ec */ - u32 fe_3d_ch0_offset; /* 0x0f0 */ - u32 fe_3d_ch1_offset; /* 0x0f4 */ - u32 fe_3d_ch2_offset; /* 0x0f8 */ - u8 res4[0x04]; /* 0x0fc */ - u32 ch0_insize; /* 0x100 */ - u32 ch0_outsize; /* 0x104 */ - u32 ch0_horzfact; /* 0x108 */ - u32 ch0_vertfact; /* 0x10c */ - u32 ch0_horzphase; /* 0x110 */ - u32 ch0_vertphase0; /* 0x114 */ - u32 ch0_vertphase1; /* 0x118 */ - u8 res5[0x04]; /* 0x11c */ - u32 ch0_horztapoffset0; /* 0x120 */ - u32 ch0_horztapoffset1; /* 0x124 */ - u32 ch0_verttapoffset; /* 0x128 */ - u8 res6[0xd4]; /* 0x12c */ - u32 ch1_insize; /* 0x200 */ - u32 ch1_outsize; /* 0x204 */ - u32 ch1_horzfact; /* 0x208 */ - u32 ch1_vertfact; /* 0x20c */ - u32 ch1_horzphase; /* 0x210 */ - u32 ch1_vertphase0; /* 0x214 */ - u32 ch1_vertphase1; /* 0x218 */ - u8 res7[0x04]; /* 0x21c */ - u32 ch1_horztapoffset0; /* 0x220 */ - u32 ch1_horztapoffset1; /* 0x224 */ - u32 ch1_verttapoffset; /* 0x228 */ - u8 res8[0x1d4]; /* 0x22c */ - u32 ch0_horzcoef0[32]; /* 0x400 */ - u32 ch0_horzcoef1[32]; /* 0x480 */ - u32 ch0_vertcoef[32]; /* 0x500 */ - u8 res9[0x80]; /* 0x580 */ - u32 ch1_horzcoef0[32]; /* 0x600 */ - u32 ch1_horzcoef1[32]; /* 0x680 */ - u32 ch1_vertcoef[32]; /* 0x700 */ - u8 res10[0x280]; /* 0x780 */ - u32 vpp_enable; /* 0xa00 */ - u32 vpp_dcti; /* 0xa04 */ - u32 vpp_lp1; /* 0xa08 */ - u32 vpp_lp2; /* 0xa0c */ - u32 vpp_wle; /* 0xa10 */ - u32 vpp_ble; /* 0xa14 */ -}; - -struct sunxi_de_be_reg { - u8 res0[0x800]; /* 0x000 */ - u32 mode; /* 0x800 */ - u32 backcolor; /* 0x804 */ - u32 disp_size; /* 0x808 */ - u8 res1[0x4]; /* 0x80c */ - u32 layer0_size; /* 0x810 */ - u32 layer1_size; /* 0x814 */ - u32 layer2_size; /* 0x818 */ - u32 layer3_size; /* 0x81c */ - u32 layer0_pos; /* 0x820 */ - u32 layer1_pos; /* 0x824 */ - u32 layer2_pos; /* 0x828 */ - u32 layer3_pos; /* 0x82c */ - u8 res2[0x10]; /* 0x830 */ - u32 layer0_stride; /* 0x840 */ - u32 layer1_stride; /* 0x844 */ - u32 layer2_stride; /* 0x848 */ - u32 layer3_stride; /* 0x84c */ - u32 layer0_addr_low32b; /* 0x850 */ - u32 layer1_addr_low32b; /* 0x854 */ - u32 layer2_addr_low32b; /* 0x858 */ - u32 layer3_addr_low32b; /* 0x85c */ - u32 layer0_addr_high4b; /* 0x860 */ - u32 layer1_addr_high4b; /* 0x864 */ - u32 layer2_addr_high4b; /* 0x868 */ - u32 layer3_addr_high4b; /* 0x86c */ - u32 reg_ctrl; /* 0x870 */ - u8 res3[0xc]; /* 0x874 */ - u32 color_key_max; /* 0x880 */ - u32 color_key_min; /* 0x884 */ - u32 color_key_config; /* 0x888 */ - u8 res4[0x4]; /* 0x88c */ - u32 layer0_attr0_ctrl; /* 0x890 */ - u32 layer1_attr0_ctrl; /* 0x894 */ - u32 layer2_attr0_ctrl; /* 0x898 */ - u32 layer3_attr0_ctrl; /* 0x89c */ - u32 layer0_attr1_ctrl; /* 0x8a0 */ - u32 layer1_attr1_ctrl; /* 0x8a4 */ - u32 layer2_attr1_ctrl; /* 0x8a8 */ - u32 layer3_attr1_ctrl; /* 0x8ac */ - u8 res5[0x110]; /* 0x8b0 */ - u32 output_color_ctrl; /* 0x9c0 */ - u8 res6[0xc]; /* 0x9c4 */ - u32 output_color_coef[12]; /* 0x9d0 */ -}; - -struct sunxi_hdmi_reg { - u32 version_id; /* 0x000 */ - u32 ctrl; /* 0x004 */ - u32 irq; /* 0x008 */ - u32 hpd; /* 0x00c */ - u32 video_ctrl; /* 0x010 */ - u32 video_size; /* 0x014 */ - u32 video_bp; /* 0x018 */ - u32 video_fp; /* 0x01c */ - u32 video_spw; /* 0x020 */ - u32 video_polarity; /* 0x024 */ - u8 res0[0x58]; /* 0x028 */ - u8 avi_info_frame[0x14]; /* 0x080 */ - u8 res1[0x4c]; /* 0x094 */ - u32 qcp_packet0; /* 0x0e0 */ - u32 qcp_packet1; /* 0x0e4 */ - u8 res2[0x118]; /* 0x0e8 */ - u32 pad_ctrl0; /* 0x200 */ - u32 pad_ctrl1; /* 0x204 */ - u32 pll_ctrl; /* 0x208 */ - u32 pll_dbg0; /* 0x20c */ - u32 pll_dbg1; /* 0x210 */ - u32 hpd_cec; /* 0x214 */ - u8 res3[0x28]; /* 0x218 */ - u8 vendor_info_frame[0x14]; /* 0x240 */ - u8 res4[0x9c]; /* 0x254 */ - u32 pkt_ctrl0; /* 0x2f0 */ - u32 pkt_ctrl1; /* 0x2f4 */ - u8 res5[0x8]; /* 0x2f8 */ - u32 unknown; /* 0x300 */ - u8 res6[0xc]; /* 0x304 */ - u32 audio_sample_count; /* 0x310 */ - u8 res7[0xec]; /* 0x314 */ - u32 audio_tx_fifo; /* 0x400 */ - u8 res8[0xfc]; /* 0x404 */ -#ifndef CONFIG_MACH_SUN6I - u32 ddc_ctrl; /* 0x500 */ - u32 ddc_addr; /* 0x504 */ - u32 ddc_int_mask; /* 0x508 */ - u32 ddc_int_status; /* 0x50c */ - u32 ddc_fifo_ctrl; /* 0x510 */ - u32 ddc_fifo_status; /* 0x514 */ - u32 ddc_fifo_data; /* 0x518 */ - u32 ddc_byte_count; /* 0x51c */ - u32 ddc_cmnd; /* 0x520 */ - u32 ddc_exreg; /* 0x524 */ - u32 ddc_clock; /* 0x528 */ - u8 res9[0x14]; /* 0x52c */ - u32 ddc_line_ctrl; /* 0x540 */ -#else - u32 ddc_ctrl; /* 0x500 */ - u32 ddc_exreg; /* 0x504 */ - u32 ddc_cmnd; /* 0x508 */ - u32 ddc_addr; /* 0x50c */ - u32 ddc_int_mask; /* 0x510 */ - u32 ddc_int_status; /* 0x514 */ - u32 ddc_fifo_ctrl; /* 0x518 */ - u32 ddc_fifo_status; /* 0x51c */ - u32 ddc_clock; /* 0x520 */ - u32 ddc_timeout; /* 0x524 */ - u8 res9[0x18]; /* 0x528 */ - u32 ddc_dbg; /* 0x540 */ - u8 res10[0x3c]; /* 0x544 */ - u32 ddc_fifo_data; /* 0x580 */ -#endif -}; - -/* - * DE-FE register constants. - */ -#define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) -#define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16) -#define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16) -#define SUNXI_DE_FE_ENABLE_EN (1 << 0) -#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0) -#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1) -#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16) -#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1) -#define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151 -#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002 - -/* - * DE-BE register constants. - */ -#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) -#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16) -#define SUNXI_DE_BE_MODE_ENABLE (1 << 0) -#define SUNXI_DE_BE_MODE_START (1 << 1) -#define SUNXI_DE_BE_MODE_DEFLICKER_ENABLE (1 << 4) -#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) -#define SUNXI_DE_BE_MODE_INTERLACE_ENABLE (1 << 28) -#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) -#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) -#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002 -#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) -#define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE 1 - -/* - * HDMI register constants. - */ -#define SUNXI_HDMI_X(x) (((x) - 1) << 0) -#define SUNXI_HDMI_Y(y) (((y) - 1) << 16) -#define SUNXI_HDMI_CTRL_ENABLE (1 << 31) -#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0) -#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1) -#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73 -#define SUNXI_HDMI_HPD_DETECT (1 << 0) -#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31) -#define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30) -#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0) -#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1) -#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16) -#define SUNXI_HDMI_QCP_PACKET0 3 -#define SUNXI_HDMI_QCP_PACKET1 0 - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f -#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff -#else -#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000 -#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000 -#endif - -#ifdef CONFIG_MACH_SUN4I -#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820 -#elif defined CONFIG_MACH_SUN6I -#define SUNXI_HDMI_PAD_CTRL1 0x01ded030 -#else -#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830 -#endif -#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6) - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_PLL_CTRL 0xba48a308 -#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4) -#else -#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708 -#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4) -#endif -#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4) - -#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21) -#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21) - -#define SUNXI_HDMI_PKT_CTRL0 0x00000f21 -#define SUNXI_HDMI_PKT_CTRL1 0x0000000f -#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000 - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0) -#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4) -#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6) -#define SUNXI_HMDI_DDC_CTRL_START (1 << 27) -#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31) -#else -#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0) -/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */ -#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0 -#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0 -#define SUNXI_HMDI_DDC_CTRL_START (1 << 30) -#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31) -#endif - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0) -#else -#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0) -#endif -#define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8) -#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16) -#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24) - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15) -#else -#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31) -#endif - -#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6 -#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7 - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_DDC_CLOCK 0x61 -#else -/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */ -#define SUNXI_HDMI_DDC_CLOCK 0x0d -#endif - -#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8) -#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9) - -int sunxi_simplefb_setup(void *blob); - -#endif /* _SUNXI_DISPLAY_H */ diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h deleted file mode 100644 index 7202d27..0000000 --- a/arch/arm/include/asm/arch-sunxi/display2.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform display controller register and constant defines - * - * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> - * - * Based on out of tree Linux DRM driver defines: - * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr> - * Copyright (c) 2016 Allwinnertech Co., Ltd. - */ - -#ifndef _SUNXI_DISPLAY2_H -#define _SUNXI_DISPLAY2_H - -/* internal clock settings */ -struct de_clk { - u32 gate_cfg; - u32 bus_cfg; - u32 rst_cfg; - u32 div_cfg; - u32 sel_cfg; -}; - -/* global control */ -struct de_glb { - u32 ctl; - u32 status; - u32 dbuff; - u32 size; -}; - -/* alpha blending */ -struct de_bld { - u32 fcolor_ctl; - struct { - u32 fcolor; - u32 insize; - u32 offset; - u32 dum; - } attr[4]; - u32 dum0[15]; - u32 route; - u32 premultiply; - u32 bkcolor; - u32 output_size; - u32 bld_mode[4]; - u32 dum1[4]; - u32 ck_ctl; - u32 ck_cfg; - u32 dum2[2]; - u32 ck_max[4]; - u32 dum3[4]; - u32 ck_min[4]; - u32 dum4[3]; - u32 out_ctl; -}; - -/* VI channel */ -struct de_vi { - struct { - u32 attr; - u32 size; - u32 coord; - u32 pitch[3]; - u32 top_laddr[3]; - u32 bot_laddr[3]; - } cfg[4]; - u32 fcolor[4]; - u32 top_haddr[3]; - u32 bot_haddr[3]; - u32 ovl_size[2]; - u32 hori[2]; - u32 vert[2]; -}; - -struct de_ui { - struct { - u32 attr; - u32 size; - u32 coord; - u32 pitch; - u32 top_laddr; - u32 bot_laddr; - u32 fcolor; - u32 dum; - } cfg[4]; - u32 top_haddr; - u32 bot_haddr; - u32 ovl_size; -}; - -struct de_csc { - u32 csc_ctl; - u8 res[0xc]; - u32 coef11; - u32 coef12; - u32 coef13; - u32 coef14; - u32 coef21; - u32 coef22; - u32 coef23; - u32 coef24; - u32 coef31; - u32 coef32; - u32 coef33; - u32 coef34; -}; - -/* - * DE register constants. - */ -#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) -#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) - -#define SUNXI_DE2_MUX_GLB_REGS 0x00000 -#define SUNXI_DE2_MUX_BLD_REGS 0x01000 -#define SUNXI_DE2_MUX_CHAN_REGS 0x02000 -#define SUNXI_DE2_MUX_CHAN_SZ 0x1000 -#define SUNXI_DE2_MUX_VSU_REGS 0x20000 -#define SUNXI_DE2_MUX_GSU1_REGS 0x30000 -#define SUNXI_DE2_MUX_GSU2_REGS 0x40000 -#define SUNXI_DE2_MUX_GSU3_REGS 0x50000 -#define SUNXI_DE2_MUX_FCE_REGS 0xa0000 -#define SUNXI_DE2_MUX_BWS_REGS 0xa2000 -#define SUNXI_DE2_MUX_LTI_REGS 0xa4000 -#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 -#define SUNXI_DE2_MUX_ASE_REGS 0xa8000 -#define SUNXI_DE2_MUX_FCC_REGS 0xaa000 -#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 - -#define SUNXI_DE2_FORMAT_XRGB_8888 4 -#define SUNXI_DE2_FORMAT_RGB_565 10 - -#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) -#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) -#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) - -#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) - -#endif /* _SUNXI_DISPLAY2_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dma.h b/arch/arm/include/asm/arch-sunxi/dma.h deleted file mode 100644 index bd4c84f..0000000 --- a/arch/arm/include/asm/arch-sunxi/dma.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> - */ - -#ifndef _SUNXI_DMA_H -#define _SUNXI_DMA_H - -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) -#include <asm/arch/dma_sun4i.h> -#else -#error "DMA definition not available for this architecture" -#endif - -#endif /* _SUNXI_DMA_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h deleted file mode 100644 index 309dc4f..0000000 --- a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> - */ - -#ifndef _SUNXI_DMA_SUN4I_H -#define _SUNXI_DMA_SUN4I_H - -struct sunxi_dma_cfg -{ - u32 ctl; /* 0x00 Control */ - u32 src_addr; /* 0x04 Source address */ - u32 dst_addr; /* 0x08 Destination address */ - u32 bc; /* 0x0C Byte counter */ - u32 res0[2]; - u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ - u32 res1; -}; - -struct sunxi_dma -{ - u32 irq_en; /* 0x000 IRQ enable */ - u32 irq_pend; /* 0x004 IRQ pending */ - u32 auto_gate; /* 0x008 auto gating */ - u32 res0[61]; - struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ - u32 res1[64]; - struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ -}; - -enum ddma_drq_type { - DDMA_DST_DRQ_SRAM = 0, - DDMA_SRC_DRQ_SRAM = 0, - DDMA_DST_DRQ_SDRAM = 1, - DDMA_SRC_DRQ_SDRAM = 1, - DDMA_DST_DRQ_PATA = 2, - DDMA_SRC_DRQ_PATA = 2, - DDMA_DST_DRQ_NAND = 3, - DDMA_SRC_DRQ_NAND = 3, - DDMA_DST_DRQ_USB0 = 4, - DDMA_SRC_DRQ_USB0 = 4, - DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, - DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, - DDMA_DST_DRQ_SPI1_TX = 8, - DDMA_SRC_DRQ_SPI1_RX = 9, - DDMA_DST_DRQ_SECURITY_SYS_TX = 10, - DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, - DDMA_DST_DRQ_TCON0 = 14, - DDMA_DST_DRQ_TCON1 = 15, - DDMA_DST_DRQ_MSC = 23, - DDMA_SRC_DRQ_MSC = 23, - DDMA_DST_DRQ_SPI0_TX = 26, - DDMA_SRC_DRQ_SPI0_RX = 27, - DDMA_DST_DRQ_SPI2_TX = 28, - DDMA_SRC_DRQ_SPI2_RX = 29, - DDMA_DST_DRQ_SPI3_TX = 30, - DDMA_SRC_DRQ_SPI3_RX = 31, -}; - -#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) -#define SUNXI_DMA_CTL_MODE_IO (1 << 5) -#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) -#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) -#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) -#define SUNXI_DMA_CTL_TRIGGER (1 << 31) - -#endif /* _SUNXI_DMA_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h deleted file mode 100644 index 8002b7e..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * Sunxi platform dram register definition. - */ - -#ifndef _SUNXI_DRAM_H -#define _SUNXI_DRAM_H - -#include <asm/io.h> -#include <linux/types.h> - -/* dram regs definition */ -#if defined(CONFIG_MACH_SUN6I) -#include <asm/arch/dram_sun6i.h> -#elif defined(CONFIG_MACH_SUN8I_A23) -#include <asm/arch/dram_sun8i_a23.h> -#elif defined(CONFIG_MACH_SUN8I_A33) -#include <asm/arch/dram_sun8i_a33.h> -#elif defined(CONFIG_MACH_SUN8I_A83T) -#include <asm/arch/dram_sun8i_a83t.h> -#elif defined(CONFIG_SUNXI_DRAM_DW) -#include <asm/arch/dram_sunxi_dw.h> -#elif defined(CONFIG_MACH_SUN9I) -#include <asm/arch/dram_sun9i.h> -#elif defined(CONFIG_MACH_SUN50I_H6) -#include <asm/arch/dram_sun50i_h6.h> -#else -#include <asm/arch/dram_sun4i.h> -#endif - -unsigned long sunxi_dram_init(void); -void mctl_await_completion(u32 *reg, u32 mask, u32 val); -bool mctl_mem_matches(u32 offset); - -#endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h deleted file mode 100644 index 69c6600..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * Sunxi platform dram register definition. - */ - -#ifndef _SUNXI_DRAM_SUN4I_H -#define _SUNXI_DRAM_SUN4I_H - -struct sunxi_dram_reg { - u32 ccr; /* 0x00 controller configuration register */ - u32 dcr; /* 0x04 dram configuration register */ - u32 iocr; /* 0x08 i/o configuration register */ - u32 csr; /* 0x0c controller status register */ - u32 drr; /* 0x10 dram refresh register */ - u32 tpr0; /* 0x14 dram timing parameters register 0 */ - u32 tpr1; /* 0x18 dram timing parameters register 1 */ - u32 tpr2; /* 0x1c dram timing parameters register 2 */ - u32 gdllcr; /* 0x20 global dll control register */ - u8 res0[0x28]; - u32 rslr0; /* 0x4c rank system latency register */ - u32 rslr1; /* 0x50 rank system latency register */ - u8 res1[0x8]; - u32 rdgr0; /* 0x5c rank dqs gating register */ - u32 rdgr1; /* 0x60 rank dqs gating register */ - u8 res2[0x34]; - u32 odtcr; /* 0x98 odt configuration register */ - u32 dtr0; /* 0x9c data training register 0 */ - u32 dtr1; /* 0xa0 data training register 1 */ - u32 dtar; /* 0xa4 data training address register */ - u32 zqcr0; /* 0xa8 zq control register 0 */ - u32 zqcr1; /* 0xac zq control register 1 */ - u32 zqsr; /* 0xb0 zq status register */ - u32 idcr; /* 0xb4 initializaton delay configure reg */ - u8 res3[0x138]; - u32 mr; /* 0x1f0 mode register */ - u32 emr; /* 0x1f4 extended mode register */ - u32 emr2; /* 0x1f8 extended mode register */ - u32 emr3; /* 0x1fc extended mode register */ - u32 dllctr; /* 0x200 dll control register */ - u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ - /* 0x208 dll control register 1(byte 1) */ - /* 0x20c dll control register 2(byte 2) */ - /* 0x210 dll control register 3(byte 3) */ - /* 0x214 dll control register 4(byte 4) */ - u32 dqtr0; /* 0x218 dq timing register */ - u32 dqtr1; /* 0x21c dq timing register */ - u32 dqtr2; /* 0x220 dq timing register */ - u32 dqtr3; /* 0x224 dq timing register */ - u32 dqstr; /* 0x228 dqs timing register */ - u32 dqsbtr; /* 0x22c dqsb timing register */ - u32 mcr; /* 0x230 mode configure register */ - u8 res[0x8]; - u32 ppwrsctl; /* 0x23c pad power save control */ - u32 apr; /* 0x240 arbiter period register */ - u32 pldtr; /* 0x244 priority level data threshold reg */ - u8 res5[0x8]; - u32 hpcr[32]; /* 0x250 host port configure register */ - u8 res6[0x10]; - u32 csel; /* 0x2e0 controller select register */ -}; - -struct dram_para { - u32 clock; - u32 mbus_clock; - u32 type; - u32 rank_num; - u32 density; - u32 io_width; - u32 bus_width; - u32 cas; - u32 zq; - u32 odt_en; - u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */ - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 tpr3; - u32 tpr4; - u32 tpr5; - u32 emr1; - u32 emr2; - u32 emr3; - u32 dqs_gating_delay; - u32 active_windowing; -}; - -#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) -#define DRAM_CCR_DQS_GATE (0x1 << 14) -#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) -#define DRAM_CCR_ITM_OFF (0x1 << 28) -#define DRAM_CCR_DATA_TRAINING (0x1 << 30) -#define DRAM_CCR_INIT (0x1 << 31) - -#define DRAM_MEMORY_TYPE_DDR1 1 -#define DRAM_MEMORY_TYPE_DDR2 2 -#define DRAM_MEMORY_TYPE_DDR3 3 -#define DRAM_MEMORY_TYPE_LPDDR2 4 -#define DRAM_MEMORY_TYPE_LPDDR 5 -#define DRAM_DCR_TYPE (0x1 << 0) -#define DRAM_DCR_TYPE_DDR2 0x0 -#define DRAM_DCR_TYPE_DDR3 0x1 -#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) -#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) -#define DRAM_DCR_IO_WIDTH_8BIT 0x0 -#define DRAM_DCR_IO_WIDTH_16BIT 0x1 -#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) -#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) -#define DRAM_DCR_CHIP_DENSITY_256M 0x0 -#define DRAM_DCR_CHIP_DENSITY_512M 0x1 -#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 -#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 -#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 -#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 -#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) -#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) -#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 -#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 -#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 -#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) -#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) -#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) -#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) -#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) -#define DRAM_DCR_MODE_SEQ 0x0 -#define DRAM_DCR_MODE_INTERLEAVE 0x1 - -#define DRAM_CSR_DTERR (0x1 << 20) -#define DRAM_CSR_DTIERR (0x1 << 21) -#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR) - -#define DRAM_DRR_TRFC(n) ((n) & 0xff) -#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) -#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) - -#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) -#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) -#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) -#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) -#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) -#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) -#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) -#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) -#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) -#define DRAM_MCR_RESET (0x1 << 12) -#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) -#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) -#define DRAM_MCR_DCLK_OUT (0x1 << 16) - -#define DRAM_DLLCR_NRESET (0x1 << 30) -#define DRAM_DLLCR_DISABLE (0x1 << 31) - -#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) -#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) -#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */ -#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */ - -#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ - -#define DRAM_IOCR_ODT_EN ((3 << 30) | (3 << 0)) - -#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) -#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) -#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) -#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) -#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) -#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) -#define DRAM_MR_POWER_DOWN (0x1 << 12) - -#define DRAM_CSEL_MAGIC 0x16237495 - -unsigned long dramc_init(struct dram_para *para); - -#endif /* _SUNXI_DRAM_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h deleted file mode 100644 index 0a1da02..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * H6 dram controller register and constant defines - * - * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_DRAM_SUN50I_H6_H -#define _SUNXI_DRAM_SUN50I_H6_H - -#include <stdbool.h> - -enum sunxi_dram_type { - SUNXI_DRAM_TYPE_DDR3 = 3, - SUNXI_DRAM_TYPE_DDR4, - SUNXI_DRAM_TYPE_LPDDR2 = 6, - SUNXI_DRAM_TYPE_LPDDR3, -}; - -static inline bool sunxi_dram_is_lpddr(int type) -{ - return type >= SUNXI_DRAM_TYPE_LPDDR2; -} - -/* - * The following information is mainly retrieved by disassembly and some FPGA - * test code of sun50iw3 platform. - */ -struct sunxi_mctl_com_reg { - u32 cr; /* 0x000 control register */ - u8 reserved_0x004[4]; /* 0x004 */ - u32 unk_0x008; /* 0x008 */ - u32 tmr; /* 0x00c timer register */ - u8 reserved_0x010[4]; /* 0x010 */ - u32 unk_0x014; /* 0x014 */ - u8 reserved_0x018[8]; /* 0x018 */ - u32 maer0; /* 0x020 master enable register 0 */ - u32 maer1; /* 0x024 master enable register 1 */ - u32 maer2; /* 0x028 master enable register 2 */ - u8 reserved_0x02c[468]; /* 0x02c */ - u32 bwcr; /* 0x200 bandwidth control register */ - u8 reserved_0x204[12]; /* 0x204 */ - /* - * The last master configured by BSP libdram is at 0x49x, so the - * size of this struct array is set to 41 (0x29) now. - */ - struct { - u32 cfg0; /* 0x0 */ - u32 cfg1; /* 0x4 */ - u8 reserved_0x8[8]; /* 0x8 */ - } master[41]; /* 0x210 + index * 0x10 */ -}; -check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498); - -/* - * The following register information are retrieved from some similar DRAM - * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs, - * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs. - * - * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems - * to be older than the one in Allwinner H6, as the DRAMTMG9 register - * is missing in these SoCs. (From the product specifications of these - * SoCs they're not capable of DDR4) - * - * Information sources: - * - dram_sun9i.h and dram_sun8i_a23.h in the same directory. - * - sdram_rk3328.h from the RK3328 TPL DRAM patchset - * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM) - * - Zynq UltraScale+ MPSoC Register Reference (UG1087) - */ -struct sunxi_mctl_ctl_reg { - u32 mstr; /* 0x000 */ - u32 statr; /* 0x004 unused */ - u32 mstr1; /* 0x008 unused */ - u32 unk_0x00c; /* 0x00c */ - u32 mrctrl0; /* 0x010 unused */ - u32 mrctrl1; /* 0x014 unused */ - u32 mrstatr; /* 0x018 unused */ - u32 mrctrl2; /* 0x01c unused */ - u32 derateen; /* 0x020 unused */ - u32 derateint; /* 0x024 unused */ - u8 reserved_0x028[8]; /* 0x028 */ - u32 pwrctl; /* 0x030 unused */ - u32 pwrtmg; /* 0x034 unused */ - u32 hwlpctl; /* 0x038 unused */ - u8 reserved_0x03c[20]; /* 0x03c */ - u32 rfshctl0; /* 0x050 unused */ - u32 rfshctl1; /* 0x054 unused */ - u8 reserved_0x058[8]; /* 0x05c */ - u32 rfshctl3; /* 0x060 */ - u32 rfshtmg; /* 0x064 */ - u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */ - u32 init[8]; /* 0x0d0 */ - u32 dimmctl; /* 0x0f0 unused */ - u32 rankctl; /* 0x0f4 */ - u8 reserved_0x0f8[8]; /* 0x0f8 */ - u32 dramtmg[17]; /* 0x100 */ - u8 reserved_0x144[60]; /* 0x144 */ - u32 zqctl[3]; /* 0x180 */ - u32 zqstat; /* 0x18c unused */ - u32 dfitmg0; /* 0x190 */ - u32 dfitmg1; /* 0x194 */ - u32 dfilpcfg[2]; /* 0x198 unused */ - u32 dfiupd[3]; /* 0x1a0 */ - u32 reserved_0x1ac; /* 0x1ac */ - u32 dfimisc; /* 0x1b0 */ - u32 dfitmg2; /* 0x1b4 unused, may not exist */ - u8 reserved_0x1b8[8]; /* 0x1b8 */ - u32 dbictl; /* 0x1c0 */ - u8 reserved_0x1c4[60]; /* 0x1c4 */ - u32 addrmap[12]; /* 0x200 */ - u8 reserved_0x230[16]; /* 0x230 */ - u32 odtcfg; /* 0x240 */ - u32 odtmap; /* 0x244 */ - u8 reserved_0x248[8]; /* 0x248 */ - u32 sched[2]; /* 0x250 */ - u8 reserved_0x258[180]; /* 0x258 */ - u32 dbgcmd; /* 0x30c unused */ - u32 dbgstat; /* 0x310 unused */ - u8 reserved_0x314[12]; /* 0x314 */ - u32 swctl; /* 0x320 */ - u32 swstat; /* 0x324 */ -}; -check_member(sunxi_mctl_ctl_reg, swstat, 0x324); - -#define MSTR_DEVICETYPE_DDR3 BIT(0) -#define MSTR_DEVICETYPE_LPDDR2 BIT(2) -#define MSTR_DEVICETYPE_LPDDR3 BIT(3) -#define MSTR_DEVICETYPE_DDR4 BIT(4) -#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) -#define MSTR_2TMODE BIT(10) -#define MSTR_BUSWIDTH_FULL (0 << 12) -#define MSTR_BUSWIDTH_HALF (1 << 12) -#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24) -#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) - -/* - * The following register information is based on Zynq UltraScale+ - * MPSoC Register Reference, as it's the currently only known - * DDR PHY similar to the one used in H6; however although the - * map is similar, the bit fields definitions are different. - * - * Other DesignWare DDR PHY's have similar register names, but the - * offset and definitions are both different. - */ -struct sunxi_mctl_phy_reg { - u32 ver; /* 0x000 guess based on similar PHYs */ - u32 pir; /* 0x004 */ - u8 reserved_0x008[8]; /* 0x008 */ - /* - * The ZynqMP manual didn't document PGCR1, however this register - * exists on H6 and referenced by libdram. - */ - u32 pgcr[8]; /* 0x010 */ - /* - * By comparing the hardware and the ZynqMP manual, the PGSR seems - * to start at 0x34 on H6. - */ - u8 reserved_0x030[4]; /* 0x030 */ - u32 pgsr[3]; /* 0x034 */ - u32 ptr[7]; /* 0x040 */ - /* - * According to ZynqMP reference there's PLLCR0~6 in this area, - * but they're tagged "Type B PLL Only" and H6 seems to have - * no them. - * 0x080 is not present in ZynqMP reference but it seems to be - * present on H6. - */ - u8 reserved_0x05c[36]; /* 0x05c */ - u32 unk_0x080; /* 0x080 */ - u8 reserved_0x084[4]; /* 0x084 */ - u32 dxccr; /* 0x088 */ - u8 reserved_0x08c[4]; /* 0x08c */ - u32 dsgcr; /* 0x090 */ - u8 reserved_0x094[4]; /* 0x094 */ - u32 odtcr; /* 0x098 */ - u8 reserved_0x09c[4]; /* 0x09c */ - u32 aacr; /* 0x0a0 */ - u8 reserved_0x0a4[32]; /* 0x0a4 */ - u32 gpr1; /* 0x0c4 */ - u8 reserved_0x0c8[56]; /* 0x0c8 */ - u32 dcr; /* 0x100 */ - u8 reserved_0x104[12]; /* 0x104 */ - u32 dtpr[7]; /* 0x110 */ - u8 reserved_0x12c[20]; /* 0x12c */ - u32 rdimmgcr[3]; /* 0x140 */ - u8 reserved_0x14c[4]; /* 0x14c */ - u32 rdimmcr[5]; /* 0x150 */ - u8 reserved_0x164[4]; /* 0x164 */ - u32 schcr[2]; /* 0x168 */ - u8 reserved_0x170[16]; /* 0x170 */ - /* - * The ZynqMP manual documents MR0~7, 11~14 and 22. - */ - u32 mr[23]; /* 0x180 */ - u8 reserved_0x1dc[36]; /* 0x1dc */ - u32 dtcr[2]; /* 0x200 */ - u32 dtar[3]; /* 0x208 */ - u8 reserved_0x214[4]; /* 0x214 */ - u32 dtdr[2]; /* 0x218 */ - u8 reserved_0x220[16]; /* 0x220 */ - u32 dtedr0; /* 0x230 */ - u32 dtedr1; /* 0x234 */ - u32 dtedr2; /* 0x238 */ - u32 vtdr; /* 0x23c */ - u32 catr[2]; /* 0x240 */ - u8 reserved_0x248[8]; - u32 dqsdr[3]; /* 0x250 */ - u32 dtedr3; /* 0x25c */ - u8 reserved_0x260[160]; /* 0x260 */ - u32 dcuar; /* 0x300 */ - u32 dcudr; /* 0x304 */ - u32 dcurr; /* 0x308 */ - u32 dculr; /* 0x30c */ - u32 dcugcr; /* 0x310 */ - u32 dcutpr; /* 0x314 */ - u32 dcusr[2]; /* 0x318 */ - u8 reserved_0x320[444]; /* 0x320 */ - u32 rankidr; /* 0x4dc */ - u32 riocr[6]; /* 0x4e0 */ - u8 reserved_0x4f8[8]; /* 0x4f8 */ - u32 aciocr[6]; /* 0x500 */ - u8 reserved_0x518[8]; /* 0x518 */ - u32 iovcr[2]; /* 0x520 */ - u32 vtcr[2]; /* 0x528 */ - u8 reserved_0x530[16]; /* 0x530 */ - u32 acbdlr[17]; /* 0x540 */ - u32 aclcdlr; /* 0x584 */ - u8 reserved_0x588[24]; /* 0x588 */ - u32 acmdlr[2]; /* 0x5a0 */ - u8 reserved_0x5a8[216]; /* 0x5a8 */ - struct { - u32 zqcr; /* 0x00 only the first one valid */ - u32 zqpr[2]; /* 0x04 */ - u32 zqdr[2]; /* 0x0c */ - u32 zqor[2]; /* 0x14 */ - u32 zqsr; /* 0x1c */ - } zq[2]; /* 0x680, 0x6a0 */ - u8 reserved_0x6c0[64]; /* 0x6c0 */ - struct { - u32 gcr[7]; /* 0x00 */ - u8 reserved_0x1c[36]; /* 0x1c */ - u32 bdlr0; /* 0x40 */ - u32 bdlr1; /* 0x44 */ - u32 bdlr2; /* 0x48 */ - u8 reserved_0x4c[4]; /* 0x4c */ - u32 bdlr3; /* 0x50 */ - u32 bdlr4; /* 0x54 */ - u32 bdlr5; /* 0x58 */ - u8 reserved_0x5c[4]; /* 0x5c */ - u32 bdlr6; /* 0x60 */ - u8 reserved_0x64[28]; /* 0x64 */ - u32 lcdlr[6]; /* 0x80 */ - u8 reserved_0x98[8]; /* 0x98 */ - u32 mdlr[2]; /* 0xa0 */ - u8 reserved_0xa8[24]; /* 0xa8 */ - u32 gtr0; /* 0xc0 */ - u8 reserved_0xc4[12]; /* 0xc4 */ - /* - * DXnRSR0 is not documented in ZynqMP manual but - * it's used in libdram. - */ - u32 rsr[4]; /* 0xd0 */ - u32 gsr[4]; /* 0xe0 */ - u8 reserved_0xf0[16]; /* 0xf0 */ - } dx[4]; /* 0x700, 0x800, 0x900, 0xa00 */ -}; -check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); - -#define PIR_INIT BIT(0) -#define PIR_ZCAL BIT(1) -#define PIR_CA BIT(2) -#define PIR_PLLINIT BIT(4) -#define PIR_DCAL BIT(5) -#define PIR_PHYRST BIT(6) -#define PIR_DRAMRST BIT(7) -#define PIR_DRAMINIT BIT(8) -#define PIR_WL BIT(9) -#define PIR_QSGATE BIT(10) -#define PIR_WLADJ BIT(11) -#define PIR_RDDSKW BIT(12) -#define PIR_WRDSKW BIT(13) -#define PIR_RDEYE BIT(14) -#define PIR_WREYE BIT(15) -#define PIR_VREF BIT(17) -#define PIR_CTLDINIT BIT(18) -#define PIR_DQS2DQ BIT(20) -#define PIR_DCALPSE BIT(29) -#define PIR_ZCALBYP BIT(30) - -#define DCR_LPDDR3 (1 << 0) -#define DCR_DDR3 (3 << 0) -#define DCR_DDR4 (4 << 0) -#define DCR_DDR8BANK BIT(3) -#define DCR_DDR2T BIT(28) - -/* - * The delay parameters allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ -#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) -/* - * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, - * Termination and Power down - */ -#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) -struct dram_para { - u32 clk; - enum sunxi_dram_type type; - u8 cols; - u8 rows; - u8 ranks; - const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; -}; - - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - -void mctl_set_timing_params(struct dram_para *para); - -#endif /* _SUNXI_DRAM_SUN50I_H6_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h deleted file mode 100644 index 929450f..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h +++ /dev/null @@ -1,358 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun6i platform dram controller register and constant defines - * - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN6I_H -#define _SUNXI_DRAM_SUN6I_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u32 dbgcr1; /* 0x0c */ - u32 rmcr[8]; /* 0x10 */ - u32 mmcr[16]; /* 0x30 */ - u32 mbagcr[6]; /* 0x70 */ - u32 maer; /* 0x88 */ - u8 res0[0x14]; /* 0x8c */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ - u32 mdfsmrmr; /* 0x108 */ - u32 mdfstr0; /* 0x10c */ - u32 mdfstr1; /* 0x110 */ - u32 mdfstr2; /* 0x114 */ - u32 mdfstr3; /* 0x118 */ - u32 mdfsgcr; /* 0x11c */ - u8 res1[0x1c]; /* 0x120 */ - u32 mdfsivr; /* 0x13c */ - u8 res2[0x0c]; /* 0x140 */ - u32 mdfstcr; /* 0x14c */ -}; - -struct sunxi_mctl_ctl_reg { - u8 res0[0x04]; /* 0x00 */ - u32 sctl; /* 0x04 */ - u32 sstat; /* 0x08 */ - u8 res1[0x34]; /* 0x0c */ - u32 mcmd; /* 0x40 */ - u8 res2[0x08]; /* 0x44 */ - u32 cmdstat; /* 0x4c */ - u32 cmdstaten; /* 0x50 */ - u8 res3[0x0c]; /* 0x54 */ - u32 mrrcfg0; /* 0x60 */ - u32 mrrstat0; /* 0x64 */ - u32 mrrstat1; /* 0x68 */ - u8 res4[0x10]; /* 0x6c */ - u32 mcfg1; /* 0x7c */ - u32 mcfg; /* 0x80 */ - u32 ppcfg; /* 0x84 */ - u32 mstat; /* 0x88 */ - u32 lp2zqcfg; /* 0x8c */ - u8 res5[0x04]; /* 0x90 */ - u32 dtustat; /* 0x94 */ - u32 dtuna; /* 0x98 */ - u32 dtune; /* 0x9c */ - u32 dtuprd0; /* 0xa0 */ - u32 dtuprd1; /* 0xa4 */ - u32 dtuprd2; /* 0xa8 */ - u32 dtuprd3; /* 0xac */ - u32 dtuawdt; /* 0xb0 */ - u8 res6[0x0c]; /* 0xb4 */ - u32 togcnt1u; /* 0xc0 */ - u8 res7[0x08]; /* 0xc4 */ - u32 togcnt100n; /* 0xcc */ - u32 trefi; /* 0xd0 */ - u32 tmrd; /* 0xd4 */ - u32 trfc; /* 0xd8 */ - u32 trp; /* 0xdc */ - u32 trtw; /* 0xe0 */ - u32 tal; /* 0xe4 */ - u32 tcl; /* 0xe8 */ - u32 tcwl; /* 0xec */ - u32 tras; /* 0xf0 */ - u32 trc; /* 0xf4 */ - u32 trcd; /* 0xf8 */ - u32 trrd; /* 0xfc */ - u32 trtp; /* 0x100 */ - u32 twr; /* 0x104 */ - u32 twtr; /* 0x108 */ - u32 texsr; /* 0x10c */ - u32 txp; /* 0x110 */ - u32 txpdll; /* 0x114 */ - u32 tzqcs; /* 0x118 */ - u32 tzqcsi; /* 0x11c */ - u32 tdqs; /* 0x120 */ - u32 tcksre; /* 0x124 */ - u32 tcksrx; /* 0x128 */ - u32 tcke; /* 0x12c */ - u32 tmod; /* 0x130 */ - u32 trstl; /* 0x134 */ - u32 tzqcl; /* 0x138 */ - u32 tmrr; /* 0x13c */ - u32 tckesr; /* 0x140 */ - u32 tdpd; /* 0x144 */ - u8 res8[0xb8]; /* 0x148 */ - u32 dtuwactl; /* 0x200 */ - u32 dturactl; /* 0x204 */ - u32 dtucfg; /* 0x208 */ - u32 dtuectl; /* 0x20c */ - u32 dtuwd0; /* 0x210 */ - u32 dtuwd1; /* 0x214 */ - u32 dtuwd2; /* 0x218 */ - u32 dtuwd3; /* 0x21c */ - u32 dtuwdm; /* 0x220 */ - u32 dturd0; /* 0x224 */ - u32 dturd1; /* 0x228 */ - u32 dturd2; /* 0x22c */ - u32 dturd3; /* 0x230 */ - u32 dtulfsrwd; /* 0x234 */ - u32 dtulfsrrd; /* 0x238 */ - u32 dtueaf; /* 0x23c */ - u32 dfitctldly; /* 0x240 */ - u32 dfiodtcfg; /* 0x244 */ - u32 dfiodtcfg1; /* 0x248 */ - u32 dfiodtrmap; /* 0x24c */ - u32 dfitphywrd; /* 0x250 */ - u32 dfitphywrl; /* 0x254 */ - u8 res9[0x08]; /* 0x258 */ - u32 dfitrdden; /* 0x260 */ - u32 dfitphyrdl; /* 0x264 */ - u8 res10[0x08]; /* 0x268 */ - u32 dfitphyupdtype0; /* 0x270 */ - u32 dfitphyupdtype1; /* 0x274 */ - u32 dfitphyupdtype2; /* 0x278 */ - u32 dfitphyupdtype3; /* 0x27c */ - u32 dfitctrlupdmin; /* 0x280 */ - u32 dfitctrlupdmax; /* 0x284 */ - u32 dfitctrlupddly; /* 0x288 */ - u8 res11[4]; /* 0x28c */ - u32 dfiupdcfg; /* 0x290 */ - u32 dfitrefmski; /* 0x294 */ - u32 dfitcrlupdi; /* 0x298 */ - u8 res12[0x10]; /* 0x29c */ - u32 dfitrcfg0; /* 0x2ac */ - u32 dfitrstat0; /* 0x2b0 */ - u32 dfitrwrlvlen; /* 0x2b4 */ - u32 dfitrrdlvlen; /* 0x2b8 */ - u32 dfitrrdlvlgateen; /* 0x2bc */ - u8 res13[0x04]; /* 0x2c0 */ - u32 dfistcfg0; /* 0x2c4 */ - u32 dfistcfg1; /* 0x2c8 */ - u8 res14[0x04]; /* 0x2cc */ - u32 dfitdramclken; /* 0x2d0 */ - u32 dfitdramclkdis; /* 0x2d4 */ - u8 res15[0x18]; /* 0x2d8 */ - u32 dfilpcfg0; /* 0x2f0 */ -}; - -struct sunxi_mctl_phy_reg { - u8 res0[0x04]; /* 0x00 */ - u32 pir; /* 0x04 */ - u32 pgcr; /* 0x08 phy general configuration register */ - u32 pgsr; /* 0x0c */ - u32 dllgcr; /* 0x10 */ - u32 acdllcr; /* 0x14 */ - u32 ptr0; /* 0x18 */ - u32 ptr1; /* 0x1c */ - u32 ptr2; /* 0x20 */ - u32 aciocr; /* 0x24 */ - u32 dxccr; /* 0x28 DATX8 common configuration register */ - u32 dsgcr; /* 0x2c dram system general config register */ - u32 dcr; /* 0x30 */ - u32 dtpr0; /* 0x34 dram timing parameters register 0 */ - u32 dtpr1; /* 0x38 dram timing parameters register 1 */ - u32 dtpr2; /* 0x3c dram timing parameters register 2 */ - u32 mr0; /* 0x40 mode register 0 */ - u32 mr1; /* 0x44 mode register 1 */ - u32 mr2; /* 0x48 mode register 2 */ - u32 mr3; /* 0x4c mode register 3 */ - u32 odtcr; /* 0x50 */ - u32 dtar; /* 0x54 data training address register */ - u32 dtd0; /* 0x58 */ - u32 dtd1; /* 0x5c */ - u8 res1[0x60]; /* 0x60 */ - u32 dcuar; /* 0xc0 */ - u32 dcudr; /* 0xc4 */ - u32 dcurr; /* 0xc8 */ - u32 dculr; /* 0xcc */ - u32 dcugcr; /* 0xd0 */ - u32 dcutpr; /* 0xd4 */ - u32 dcusr0; /* 0xd8 */ - u32 dcusr1; /* 0xdc */ - u8 res2[0x20]; /* 0xe0 */ - u32 bistrr; /* 0x100 */ - u32 bistmskr0; /* 0x104 */ - u32 bistmskr1; /* 0x108 */ - u32 bistwcr; /* 0x10c */ - u32 bistlsr; /* 0x110 */ - u32 bistar0; /* 0x114 */ - u32 bistar1; /* 0x118 */ - u32 bistar2; /* 0x11c */ - u32 bistupdr; /* 0x120 */ - u32 bistgsr; /* 0x124 */ - u32 bistwer; /* 0x128 */ - u32 bistber0; /* 0x12c */ - u32 bistber1; /* 0x130 */ - u32 bistber2; /* 0x134 */ - u32 bistwcsr; /* 0x138 */ - u32 bistfwr0; /* 0x13c */ - u32 bistfwr1; /* 0x140 */ - u8 res3[0x3c]; /* 0x144 */ - u32 zq0cr0; /* 0x180 zq 0 control register 0 */ - u32 zq0cr1; /* 0x184 zq 0 control register 1 */ - u32 zq0sr0; /* 0x188 zq 0 status register 0 */ - u32 zq0sr1; /* 0x18c zq 0 status register 1 */ - u8 res4[0x30]; /* 0x190 */ - u32 dx0gcr; /* 0x1c0 */ - u32 dx0gsr0; /* 0x1c4 */ - u32 dx0gsr1; /* 0x1c8 */ - u32 dx0dllcr; /* 0x1cc */ - u32 dx0dqtr; /* 0x1d0 */ - u32 dx0dqstr; /* 0x1d4 */ - u8 res5[0x28]; /* 0x1d8 */ - u32 dx1gcr; /* 0x200 */ - u32 dx1gsr0; /* 0x204 */ - u32 dx1gsr1; /* 0x208 */ - u32 dx1dllcr; /* 0x20c */ - u32 dx1dqtr; /* 0x210 */ - u32 dx1dqstr; /* 0x214 */ - u8 res6[0x28]; /* 0x218 */ - u32 dx2gcr; /* 0x240 */ - u32 dx2gsr0; /* 0x244 */ - u32 dx2gsr1; /* 0x248 */ - u32 dx2dllcr; /* 0x24c */ - u32 dx2dqtr; /* 0x250 */ - u32 dx2dqstr; /* 0x254 */ - u8 res7[0x28]; /* 0x258 */ - u32 dx3gcr; /* 0x280 */ - u32 dx3gsr0; /* 0x284 */ - u32 dx3gsr1; /* 0x288 */ - u32 dx3dllcr; /* 0x28c */ - u32 dx3dqtr; /* 0x290 */ - u32 dx3dqstr; /* 0x294 */ -}; - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (3 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_BUSW32 (3 << 12) -#define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DDR3 (3 << 16) -#define MCTL_CR_CHANNEL_MASK (1 << 19) -#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) -#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) -#define MCTL_CCR_CH0_CLK_EN (1 << 0) -#define MCTL_CCR_CH1_CLK_EN (1 << 1) -#define MCTL_CCR_MASTER_CLK_EN (1 << 2) - -/* - * DRAM control (sunxi_mctl_ctl_reg) register constants. - * Note that we use constant values for a lot of the timings, this is what - * the original boot0 bootloader does. - */ -#define MCTL_SCTL_CONFIG 1 -#define MCTL_SCTL_ACCESS 2 -#define MCTL_MCMD_NOP 0x88000000 -#define MCTL_MCMD_BUSY 0x80000000 -#define MCTL_MCFG_DDR3 0x70061 -#define MCTL_TREFI 78 -#define MCTL_TMRD 4 -#define MCTL_TRFC 115 -#define MCTL_TRP 9 -#define MCTL_TPREA 0 -#define MCTL_TRTW 2 -#define MCTL_TAL 0 -#define MCTL_TCL 9 -#define MCTL_TCWL 8 -#define MCTL_TRAS 18 -#define MCTL_TRC 23 -#define MCTL_TRCD 9 -#define MCTL_TRRD 4 -#define MCTL_TRTP 4 -#define MCTL_TWR 8 -#define MCTL_TWTR 4 -#define MCTL_TEXSR 512 -#define MCTL_TXP 4 -#define MCTL_TXPDLL 14 -#define MCTL_TZQCS 64 -#define MCTL_TZQCSI 0 -#define MCTL_TDQS 1 -#define MCTL_TCKSRE 5 -#define MCTL_TCKSRX 5 -#define MCTL_TCKE 4 -#define MCTL_TMOD 12 -#define MCTL_TRSTL 80 -#define MCTL_TZQCL 512 -#define MCTL_TMRR 2 -#define MCTL_TCKESR 5 -#define MCTL_TDPD 0 -#define MCTL_DFITPHYRDL 15 -#define MCTL_DFIUPDCFG_UPD (1 << 1) -#define MCTL_DFISTCFG0 5 - -/* - * DRAM phy (sunxi_mctl_phy_reg) register values / constants. - */ -#define MCTL_PIR_CLEAR_STATUS (1 << 28) -#define MCTL_PIR_STEP1 0xe9 -#define MCTL_PIR_STEP2 0x81 -#define MCTL_PGCR_RANK (1 << 19) -#define MCTL_PGCR 0x018c0202 -#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) -/* constants for both acdllcr as well as dx#dllcr */ -#define MCTL_DLLCR_NRESET (1 << 30) -#define MCTL_DLLCR_DISABLE (1 << 31) -/* ptr constants these are or-ed together to get the final ptr# values */ -#define MCTL_TITMSRST 10 -#define MCTL_TDLLLOCK 2250 -#define MCTL_TDLLSRST 23 -#define MCTL_TDINIT0 217000 -#define MCTL_TDINIT1 160 -#define MCTL_TDINIT2 87000 -#define MCTL_TDINIT3 433 -/* end ptr constants */ -#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) -#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) -#define MCTL_DXCCR 0x800 -#define MCTL_DSGCR_ENABLE (1 << 28) -#define MCTL_DSGCR 0xf200001b -#define MCTL_DCR_DDR3 0x0b -/* dtpr constants these are or-ed together to get the final dtpr# values */ -#define MCTL_TCCD 0 -#define MCTL_TDQSCKMAX 1 -#define MCTL_TDQSCK 1 -#define MCTL_TRTODT 0 -#define MCTL_TFAW 20 -#define MCTL_TAOND 0 -#define MCTL_TDLLK 512 -/* end dtpr constants */ -#define MCTL_MR0 0x1a50 -#define MCTL_MR1 0x4 -#define MCTL_MR2 ((MCTL_TCWL - 5) << 3) -#define MCTL_MR3 0x0 -#define MCTL_DX_GCR_EN (1 << 0) -#define MCTL_DX_GCR 0x880 -#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) -#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) -#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) -#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) - -#endif /* _SUNXI_DRAM_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h deleted file mode 100644 index ca98597..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h +++ /dev/null @@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * CPL <cplanxy@allwinnertech.com> - * Jerry Wang <wangflord@allwinnertech.com> - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_H -#define _SUNXI_DRAM_SUN8I_H - -struct dram_para { - u32 clock; - u32 type; - u32 zq; - u32 odt_en; - s32 odt_correction; - u32 para1; - u32 para2; - u32 mr0; - u32 mr1; - u32 mr2; - u32 mr3; - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 tpr3; - u32 tpr4; - u32 tpr5; - u32 tpr6; - u32 tpr7; - u32 tpr8; - u32 tpr9; - u32 tpr10; - u32 tpr11; - u32 tpr12; - u32 tpr13; -}; - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u8 res0[0x4]; /* 0x0c */ - u32 mcr0_0; /* 0x10 */ - u32 mcr1_0; /* 0x14 */ - u32 mcr0_1; /* 0x18 */ - u32 mcr1_1; /* 0x1c */ - u32 mcr0_2; /* 0x20 */ - u32 mcr1_2; /* 0x24 */ - u32 mcr0_3; /* 0x28 */ - u32 mcr1_3; /* 0x2c */ - u32 mcr0_4; /* 0x30 */ - u32 mcr1_4; /* 0x34 */ - u32 mcr0_5; /* 0x38 */ - u32 mcr1_5; /* 0x3c */ - u32 mcr0_6; /* 0x40 */ - u32 mcr1_6; /* 0x44 */ - u32 mcr0_7; /* 0x48 */ - u32 mcr1_7; /* 0x4c */ - u32 mcr0_8; /* 0x50 */ - u32 mcr1_8; /* 0x54 */ - u32 mcr0_9; /* 0x58 */ - u32 mcr1_9; /* 0x5c */ - u32 mcr0_10; /* 0x60 */ - u32 mcr1_10; /* 0x64 */ - u32 mcr0_11; /* 0x68 */ - u32 mcr1_11; /* 0x6c */ - u32 mcr0_12; /* 0x70 */ - u32 mcr1_12; /* 0x74 */ - u32 mcr0_13; /* 0x78 */ - u32 mcr1_13; /* 0x7c */ - u32 mcr0_14; /* 0x80 */ - u32 mcr1_14; /* 0x84 */ - u32 mcr0_15; /* 0x88 */ - u32 mcr1_15; /* 0x8c */ - u32 bwcr; /* 0x90 */ - u32 maer; /* 0x94 */ - u8 res1[0x4]; /* 0x98 */ - u32 mcgcr; /* 0x9c */ - u32 bwctr; /* 0xa0 */ - u8 res2[0x4]; /* 0xa4 */ - u32 swonr; /* 0xa8 */ - u32 swoffr; /* 0xac */ -}; - -struct sunxi_mctl_ctl_reg { - u32 mstr; /* 0x00 */ - u32 statr; /* 0x04 */ - u8 res0[0x08]; /* 0x08 */ - u32 mrctrl0; /* 0x10 */ - u32 mrctrl1; /* 0x14 */ - u32 mrstatr; /* 0x18 */ - u8 res1[0x04]; /* 0x1c */ - u32 derateen; /* 0x20 */ - u32 deratenint; /* 0x24 */ - u8 res2[0x08]; /* 0x28 */ - u32 pwrctl; /* 0x30 */ - u32 pwrtmg; /* 0x34 */ - u8 res3[0x18]; /* 0x38 */ - u32 rfshctl0; /* 0x50 */ - u32 rfshctl1; /* 0x54 */ - u8 res4[0x8]; /* 0x58 */ - u32 rfshctl3; /* 0x60 */ - u32 rfshtmg; /* 0x64 */ - u8 res6[0x68]; /* 0x68 */ - u32 init0; /* 0xd0 */ - u32 init1; /* 0xd4 */ - u32 init2; /* 0xd8 */ - u32 init3; /* 0xdc */ - u32 init4; /* 0xe0 */ - u32 init5; /* 0xe4 */ - u8 res7[0x0c]; /* 0xe8 */ - u32 rankctl; /* 0xf4 */ - u8 res8[0x08]; /* 0xf8 */ - u32 dramtmg0; /* 0x100 */ - u32 dramtmg1; /* 0x104 */ - u32 dramtmg2; /* 0x108 */ - u32 dramtmg3; /* 0x10c */ - u32 dramtmg4; /* 0x110 */ - u32 dramtmg5; /* 0x114 */ - u32 dramtmg6; /* 0x118 */ - u32 dramtmg7; /* 0x11c */ - u32 dramtmg8; /* 0x120 */ - u8 res9[0x5c]; /* 0x124 */ - u32 zqctl0; /* 0x180 */ - u32 zqctl1; /* 0x184 */ - u32 zqctl2; /* 0x188 */ - u32 zqstat; /* 0x18c */ - u32 pitmg0; /* 0x190 */ - u32 pitmg1; /* 0x194 */ - u32 plpcfg0; /* 0x198 */ - u8 res10[0x04]; /* 0x19c */ - u32 upd0; /* 0x1a0 */ - u32 upd1; /* 0x1a4 */ - u32 upd2; /* 0x1a8 */ - u32 upd3; /* 0x1ac */ - u32 pimisc; /* 0x1b0 */ - u8 res11[0x1c]; /* 0x1b4 */ - u32 trainctl0; /* 0x1d0 */ - u32 trainctl1; /* 0x1d4 */ - u32 trainctl2; /* 0x1d8 */ - u32 trainstat; /* 0x1dc */ - u8 res12[0x60]; /* 0x1e0 */ - u32 odtcfg; /* 0x240 */ - u32 odtmap; /* 0x244 */ - u8 res13[0x08]; /* 0x248 */ - u32 sched; /* 0x250 */ - u8 res14[0x04]; /* 0x254 */ - u32 perfshpr0; /* 0x258 */ - u32 perfshpr1; /* 0x25c */ - u32 perflpr0; /* 0x260 */ - u32 perflpr1; /* 0x264 */ - u32 perfwr0; /* 0x268 */ - u32 perfwr1; /* 0x26c */ -}; - -struct sunxi_mctl_phy_reg { - u8 res0[0x04]; /* 0x00 */ - u32 pir; /* 0x04 */ - u32 pgcr0; /* 0x08 phy general configuration register */ - u32 pgcr1; /* 0x0c phy general configuration register */ - u32 pgsr0; /* 0x10 */ - u32 pgsr1; /* 0x14 */ - u32 dllgcr; /* 0x18 */ - u32 ptr0; /* 0x1c */ - u32 ptr1; /* 0x20 */ - u32 ptr2; /* 0x24 */ - u32 ptr3; /* 0x28 */ - u32 ptr4; /* 0x2c */ - u32 acmdlr; /* 0x30 */ - u32 acbdlr; /* 0x34 */ - u32 aciocr; /* 0x38 */ - u32 dxccr; /* 0x3c DATX8 common configuration register */ - u32 dsgcr; /* 0x40 dram system general config register */ - u32 dcr; /* 0x44 */ - u32 dtpr0; /* 0x48 dram timing parameters register 0 */ - u32 dtpr1; /* 0x4c dram timing parameters register 1 */ - u32 dtpr2; /* 0x50 dram timing parameters register 2 */ - u32 mr0; /* 0x54 mode register 0 */ - u32 mr1; /* 0x58 mode register 1 */ - u32 mr2; /* 0x5c mode register 2 */ - u32 mr3; /* 0x60 mode register 3 */ - u32 odtcr; /* 0x64 */ - u32 dtcr; /* 0x68 */ - u32 dtar0; /* 0x6c data training address register 0 */ - u32 dtar1; /* 0x70 data training address register 1 */ - u32 dtar2; /* 0x74 data training address register 2 */ - u32 dtar3; /* 0x78 data training address register 3 */ - u32 dtdr0; /* 0x7c */ - u32 dtdr1; /* 0x80 */ - u32 dtedr0; /* 0x84 */ - u32 dtedr1; /* 0x88 */ - u32 pgcr2; /* 0x8c */ - u8 res1[0x70]; /* 0x90 */ - u32 bistrr; /* 0x100 */ - u32 bistwcr; /* 0x104 */ - u32 bistmskr0; /* 0x108 */ - u32 bistmskr1; /* 0x10c */ - u32 bistmskr2; /* 0x110 */ - u32 bistlsr; /* 0x114 */ - u32 bistar0; /* 0x118 */ - u32 bistar1; /* 0x11c */ - u32 bistar2; /* 0x120 */ - u32 bistupdr; /* 0x124 */ - u32 bistgsr; /* 0x128 */ - u32 bistwer; /* 0x12c */ - u32 bistber0; /* 0x130 */ - u32 bistber1; /* 0x134 */ - u32 bistber2; /* 0x138 */ - u32 bistber3; /* 0x13c */ - u32 bistwcsr; /* 0x140 */ - u32 bistfwr0; /* 0x144 */ - u32 bistfwr1; /* 0x148 */ - u32 bistfwr2; /* 0x14c */ - u8 res2[0x30]; /* 0x150 */ - u32 zqcr0; /* 0x180 zq control register 0 */ - u32 zqcr1; /* 0x184 zq control register 1 */ - u32 zqsr0; /* 0x188 zq status register 0 */ - u32 zqsr1; /* 0x18c zq status register 1 */ - u32 zqcr2; /* 0x190 zq control register 2 */ - u8 res3[0x2c]; /* 0x194 */ - u32 dx0gcr; /* 0x1c0 */ - u32 dx0gsr0; /* 0x1c4 */ - u32 dx0gsr1; /* 0x1c8 */ - u32 dx0bdlr0; /* 0x1cc */ - u32 dx0bdlr1; /* 0x1d0 */ - u32 dx0bdlr2; /* 0x1d4 */ - u32 dx0bdlr3; /* 0x1d8 */ - u32 dx0bdlr4; /* 0x1dc */ - u32 dx0lcdlr0; /* 0x1e0 */ - u32 dx0lcdlr1; /* 0x1e4 */ - u32 dx0lcdlr2; /* 0x1e8 */ - u32 dx0mdlr; /* 0x1ec */ - u32 dx0gtr; /* 0x1f0 */ - u32 dx0gsr2; /* 0x1f4 */ - u8 res4[0x08]; /* 0x1f8 */ - u32 dx1gcr; /* 0x200 */ - u32 dx1gsr0; /* 0x204 */ - u32 dx1gsr1; /* 0x208 */ - u32 dx1bdlr0; /* 0x20c */ - u32 dx1bdlr1; /* 0x210 */ - u32 dx1bdlr2; /* 0x214 */ - u32 dx1bdlr3; /* 0x218 */ - u32 dx1bdlr4; /* 0x21c */ - u32 dx1lcdlr0; /* 0x220 */ - u32 dx1lcdlr1; /* 0x224 */ - u32 dx1lcdlr2; /* 0x228 */ - u32 dx1mdlr; /* 0x22c */ - u32 dx1gtr; /* 0x230 */ - u32 dx1gsr2; /* 0x234 */ -}; - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((x) << 8) - -#endif /* _SUNXI_DRAM_SUN8I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h deleted file mode 100644 index 49a6108..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_A33_H -#define _SUNXI_DRAM_SUN8I_A33_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u8 res0[0x4]; /* 0x0c */ - u32 mcr0_0; /* 0x10 */ - u32 mcr1_0; /* 0x14 */ - u32 mcr0_1; /* 0x18 */ - u32 mcr1_1; /* 0x1c */ - u32 mcr0_2; /* 0x20 */ - u32 mcr1_2; /* 0x24 */ - u32 mcr0_3; /* 0x28 */ - u32 mcr1_3; /* 0x2c */ - u32 mcr0_4; /* 0x30 */ - u32 mcr1_4; /* 0x34 */ - u32 mcr0_5; /* 0x38 */ - u32 mcr1_5; /* 0x3c */ - u32 mcr0_6; /* 0x40 */ - u32 mcr1_6; /* 0x44 */ - u32 mcr0_7; /* 0x48 */ - u32 mcr1_7; /* 0x4c */ - u32 mcr0_8; /* 0x50 */ - u32 mcr1_8; /* 0x54 */ - u32 mcr0_9; /* 0x58 */ - u32 mcr1_9; /* 0x5c */ - u32 mcr0_10; /* 0x60 */ - u32 mcr1_10; /* 0x64 */ - u32 mcr0_11; /* 0x68 */ - u32 mcr1_11; /* 0x6c */ - u32 mcr0_12; /* 0x70 */ - u32 mcr1_12; /* 0x74 */ - u32 mcr0_13; /* 0x78 */ - u32 mcr1_13; /* 0x7c */ - u32 mcr0_14; /* 0x80 */ - u32 mcr1_14; /* 0x84 */ - u32 mcr0_15; /* 0x88 */ - u32 mcr1_15; /* 0x8c */ - u32 bwcr; /* 0x90 */ - u32 maer; /* 0x94 */ - u32 mapr; /* 0x98 */ - u32 mcgcr; /* 0x9c */ - u32 bwctr; /* 0xa0 */ - u8 res2[0x8]; /* 0xa4 */ - u32 swoffr; /* 0xac */ - u8 res3[0x10]; /* 0xb0 */ - u32 swonr; /* 0xc0 */ - u8 res4[0x3c]; /* 0xc4 */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ -}; - -struct sunxi_mctl_ctl_reg { - u32 pir; /* 0x00 */ - u32 pwrctl; /* 0x04 */ - u32 mrctrl0; /* 0x08 */ - u32 clken; /* 0x0c */ - u32 pgsr0; /* 0x10 */ - u32 pgsr1; /* 0x14 */ - u32 statr; /* 0x18 */ - u8 res1[0x14]; /* 0x1c */ - u32 mr0; /* 0x30 */ - u32 mr1; /* 0x34 */ - u32 mr2; /* 0x38 */ - u32 mr3; /* 0x3c */ - u32 pllgcr; /* 0x40 */ - u32 ptr0; /* 0x44 */ - u32 ptr1; /* 0x48 */ - u32 ptr2; /* 0x4c */ - u32 ptr3; /* 0x50 */ - u32 ptr4; /* 0x54 */ - u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ - u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ - u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ - u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ - u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ - u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ - u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ - u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ - u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ - u32 odtcfg; /* 0x7c */ - u32 pitmg0; /* 0x80 */ - u32 pitmg1; /* 0x84 */ - u8 res2[0x4]; /* 0x88 */ - u32 rfshctl0; /* 0x8c */ - u32 rfshtmg; /* 0x90 */ - u32 rfshctl1; /* 0x94 */ - u32 pwrtmg; /* 0x98 */ - u8 res3[0x20]; /* 0x9c */ - u32 dqsgmr; /* 0xbc */ - u32 dtcr; /* 0xc0 */ - u32 dtar0; /* 0xc4 */ - u32 dtar1; /* 0xc8 */ - u32 dtar2; /* 0xcc */ - u32 dtar3; /* 0xd0 */ - u32 dtdr0; /* 0xd4 */ - u32 dtdr1; /* 0xd8 */ - u32 dtmr0; /* 0xdc */ - u32 dtmr1; /* 0xe0 */ - u32 dtbmr; /* 0xe4 */ - u32 catr0; /* 0xe8 */ - u32 catr1; /* 0xec */ - u32 dtedr0; /* 0xf0 */ - u32 dtedr1; /* 0xf4 */ - u8 res4[0x8]; /* 0xf8 */ - u32 pgcr0; /* 0x100 */ - u32 pgcr1; /* 0x104 */ - u32 pgcr2; /* 0x108 */ - u8 res5[0x4]; /* 0x10c */ - u32 iovcr0; /* 0x110 */ - u32 iovcr1; /* 0x114 */ - u32 dqsdr; /* 0x118 */ - u32 dxccr; /* 0x11c */ - u32 odtmap; /* 0x120 */ - u32 zqctl0; /* 0x124 */ - u32 zqctl1; /* 0x128 */ - u8 res6[0x14]; /* 0x12c */ - u32 zqcr0; /* 0x140 zq control register 0 */ - u32 zqcr1; /* 0x144 zq control register 1 */ - u32 zqcr2; /* 0x148 zq control register 2 */ - u32 zqsr0; /* 0x14c zq status register 0 */ - u32 zqsr1; /* 0x150 zq status register 1 */ - u8 res7[0x6c]; /* 0x154 */ - u32 sched; /* 0x1c0 */ - u32 perfhpr0; /* 0x1c4 */ - u32 perfhpr1; /* 0x1c8 */ - u32 perflpr0; /* 0x1cc */ - u32 perflpr1; /* 0x1d0 */ - u32 perfwr0; /* 0x1d4 */ - u32 perfwr1; /* 0x1d8 */ -}; - -#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) -#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) -#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) -#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) -#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (7 << 12) -#define MCTL_CR_BUSW8 (0 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DDR3 (3 << 16) -#define MCTL_CR_CHANNEL_MASK (1 << 19) -#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) -#define MCTL_CR_UNKNOWN (0x4 << 20) -#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) - -/* DRAM control (sunxi_mctl_ctl_reg) register constants */ -#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ -#define MCTL_MR1 0x40 -#define MCTL_MR2 0x18 /* CWL=8 */ -#define MCTL_MR3 0x0 - -#endif /* _SUNXI_DRAM_SUN8I_A33_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h deleted file mode 100644 index d4634e5..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_A83T_H -#define _SUNXI_DRAM_SUN8I_A83T_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u8 res0[0x4]; /* 0x0c */ - u32 mcr0_0; /* 0x10 */ - u32 mcr1_0; /* 0x14 */ - u32 mcr0_1; /* 0x18 */ - u32 mcr1_1; /* 0x1c */ - u32 mcr0_2; /* 0x20 */ - u32 mcr1_2; /* 0x24 */ - u32 mcr0_3; /* 0x28 */ - u32 mcr1_3; /* 0x2c */ - u32 mcr0_4; /* 0x30 */ - u32 mcr1_4; /* 0x34 */ - u32 mcr0_5; /* 0x38 */ - u32 mcr1_5; /* 0x3c */ - u32 mcr0_6; /* 0x40 */ - u32 mcr1_6; /* 0x44 */ - u32 mcr0_7; /* 0x48 */ - u32 mcr1_7; /* 0x4c */ - u32 mcr0_8; /* 0x50 */ - u32 mcr1_8; /* 0x54 */ - u32 mcr0_9; /* 0x58 */ - u32 mcr1_9; /* 0x5c */ - u32 mcr0_10; /* 0x60 */ - u32 mcr1_10; /* 0x64 */ - u32 mcr0_11; /* 0x68 */ - u32 mcr1_11; /* 0x6c */ - u32 mcr0_12; /* 0x70 */ - u32 mcr1_12; /* 0x74 */ - u32 mcr0_13; /* 0x78 */ - u32 mcr1_13; /* 0x7c */ - u32 mcr0_14; /* 0x80 */ - u32 mcr1_14; /* 0x84 */ - u32 mcr0_15; /* 0x88 */ - u32 mcr1_15; /* 0x8c */ - u32 bwcr; /* 0x90 */ - u32 maer; /* 0x94 */ - u32 mapr; /* 0x98 */ - u32 mcgcr; /* 0x9c */ - u32 bwctr; /* 0xa0 */ - u8 res2[0x8]; /* 0xa4 */ - u32 swoffr; /* 0xac */ - u8 res3[0x10]; /* 0xb0 */ - u32 swonr; /* 0xc0 */ - u8 res4[0x3c]; /* 0xc4 */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ -}; - -struct sunxi_mctl_ctl_reg { - u32 pir; /* 0x00 */ - u32 pwrctl; /* 0x04 */ - u32 mrctrl0; /* 0x08 */ - u32 clken; /* 0x0c */ - u32 pgsr0; /* 0x10 */ - u32 pgsr1; /* 0x14 */ - u32 statr; /* 0x18 */ - u8 res1[0x14]; /* 0x1c */ - u32 mr0; /* 0x30 */ - u32 mr1; /* 0x34 */ - u32 mr2; /* 0x38 */ - u32 mr3; /* 0x3c */ - u32 pllgcr; /* 0x40 */ - u32 ptr0; /* 0x44 */ - u32 ptr1; /* 0x48 */ - u32 ptr2; /* 0x4c */ - u32 ptr3; /* 0x50 */ - u32 ptr4; /* 0x54 */ - u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ - u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ - u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ - u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ - u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ - u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ - u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ - u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ - u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ - u32 odtcfg; /* 0x7c */ - u32 pitmg0; /* 0x80 */ - u32 pitmg1; /* 0x84 */ - u8 res2[0x4]; /* 0x88 */ - u32 rfshctl0; /* 0x8c */ - u32 rfshtmg; /* 0x90 */ - u32 rfshctl1; /* 0x94 */ - u32 pwrtmg; /* 0x98 */ - u8 res3[0x20]; /* 0x9c */ - u32 dqsgmr; /* 0xbc */ - u32 dtcr; /* 0xc0 */ - u32 dtar0; /* 0xc4 */ - u32 dtar1; /* 0xc8 */ - u32 dtar2; /* 0xcc */ - u32 dtar3; /* 0xd0 */ - u32 dtdr0; /* 0xd4 */ - u32 dtdr1; /* 0xd8 */ - u32 dtmr0; /* 0xdc */ - u32 dtmr1; /* 0xe0 */ - u32 dtbmr; /* 0xe4 */ - u32 catr0; /* 0xe8 */ - u32 catr1; /* 0xec */ - u32 dtedr0; /* 0xf0 */ - u32 dtedr1; /* 0xf4 */ - u8 res4[0x8]; /* 0xf8 */ - u32 pgcr0; /* 0x100 */ - u32 pgcr1; /* 0x104 */ - u32 pgcr2; /* 0x108 */ - u32 pgcr3; /* 0x10c */ - u32 iovcr0; /* 0x110 */ - u32 iovcr1; /* 0x114 */ - u32 dqsdr; /* 0x118 */ - u32 dxccr; /* 0x11c */ - u32 odtmap; /* 0x120 */ - u32 zqctl0; /* 0x124 */ - u32 zqctl1; /* 0x128 */ - u8 res6[0x14]; /* 0x12c */ - u32 zqncr; /* 0x140 zq control register 0 */ - u32 zqnpr; /* 0x144 zq control register 1 */ - u32 zqndr; /* 0x148 zq control register 2 */ - u32 zqnsr; /* 0x14c zq status register 0 */ - u32 res7; /* 0x150 zq status register 1 */ - u8 res8[0x6c]; /* 0x154 */ - u32 sched; /* 0x1c0 */ - u32 perfhpr0; /* 0x1c4 */ - u32 perfhpr1; /* 0x1c8 */ - u32 perflpr0; /* 0x1cc */ - u32 perflpr1; /* 0x1d0 */ - u32 perfwr0; /* 0x1d4 */ - u32 perfwr1; /* 0x1d8 */ -}; - - -#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) -#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) -#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) - -#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) -#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) -#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) -#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) -#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) - -#define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x)) -#define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x) -#define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300) -#define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x) -#define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x) -#define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x) -#define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x) -#define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x) -#define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x) -#define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x) -#define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880) -#define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888) - -#define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800) -#define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x) -#define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x) - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (7 << 12) -#define MCTL_CR_BUSW8 (0 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DRAM_TYPE(x) ((x) << 16) -#define MCTL_CR_CHANNEL_MASK (1 << 19) -#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) -#define MCTL_CR_UNKNOWN (0x4 << 20) -#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) - -/* DRAM control (sunxi_mctl_ctl_reg) register constants */ -#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ -#define MCTL_MR1 0x40 -#define MCTL_MR2 0x18 /* CWL=8 */ -#define MCTL_MR3 0x0 - -#define MCTL_LPDDR3_MR0 0x0 -#define MCTL_LPDDR3_MR1 0xc3 /* twr=8, bl=8 */ -#define MCTL_LPDDR3_MR2 0xa /* RL=12, CWL=6 */ -#define MCTL_LPDDR3_MR3 0x0 - -#define DRAM_TYPE_DDR3 3 -#define DRAM_TYPE_LPDDR3 7 -#endif /* _SUNXI_DRAM_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h deleted file mode 100644 index 603850b..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH - * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> - */ - -#ifndef _SUNXI_DRAM_SUN9I_H -#define _SUNXI_DRAM_SUN9I_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u32 dbgcr1; /* 0x0c */ - u32 rmcr; /* 0x10 */ - u8 res1[0x1c]; /* 0x14 */ - u32 mmcr; /* 0x30 */ - u8 res2[0x3c]; /* 0x34 */ - u32 mbagcr; /* 0x70 */ - u32 mbacr; /* 0x74 */ - u8 res3[0x10]; /* 0x78 */ - u32 maer; /* 0x88 */ - u8 res4[0x74]; /* 0x8c */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ - u32 mdfsmrmr; /* 0x108 */ - u32 mdfstr[4]; /* 0x10c */ - u32 mdfsgcr; /* 0x11c */ - u8 res5[0x1c]; /* 0x120 */ - u32 mdfsivr; /* 0x13c */ - u8 res6[0xc]; /* 0x140 */ - u32 mdfstcr; /* 0x14c */ -}; - - -struct sunxi_mctl_ctl_reg { - u32 mstr; /* 0x00 master register */ - u32 stat; /* 0x04 operating mode status register */ - u8 res1[0x8]; /* 0x08 */ - u32 mrctrl[2]; /* 0x10 mode register read/write control reg */ - u32 mstat; /* 0x18 mode register read/write status reg */ - u8 res2[0x4]; /* 0x1c */ - u32 derateen; /* 0x20 temperature derate enable register */ - u32 derateint; /* 0x24 temperature derate interval register */ - u8 res3[0x8]; /* 0x28 */ - u32 pwrctl; /* 0x30 low power control register */ - u32 pwrtmg; /* 0x34 low power timing register */ - u8 res4[0x18]; /* 0x38 */ - u32 rfshctl0; /* 0x50 refresh control register 0 */ - u32 rfshctl1; /* 0x54 refresh control register 1 */ - u8 res5[0x8]; /* 0x58 */ - u32 rfshctl3; /* 0x60 refresh control register 3 */ - u32 rfshtmg; /* 0x64 refresh timing register */ - u8 res6[0x68]; /* 0x68 */ - u32 init[6]; /* 0xd0 SDRAM initialisation register */ - u8 res7[0xc]; /* 0xe8 */ - u32 rankctl; /* 0xf4 rank control register */ - u8 res8[0x8]; /* 0xf8 */ - u32 dramtmg[9]; /* 0x100 DRAM timing register */ - u8 res9[0x5c]; /* 0x124 */ - u32 zqctrl[3]; /* 0x180 ZQ control register */ - u32 zqstat; /* 0x18c ZQ status register */ - u32 dfitmg[2]; /* 0x190 DFI timing register */ - u32 dfilpcfg; /* 0x198 DFI low power configuration register */ - u8 res10[0x4]; /* 0x19c */ - u32 dfiupd[4]; /* 0x1a0 DFI update register */ - u32 dfimisc; /* 0x1b0 DFI miscellaneous control register */ - u8 res11[0x1c]; /* 0x1b4 */ - u32 trainctl[3]; /* 0x1d0 */ - u32 trainstat; /* 0x1dc */ - u8 res12[0x20]; /* 0x1e0 */ - u32 addrmap[7]; /* 0x200 address map register */ - u8 res13[0x24]; /* 0x21c */ - u32 odtcfg; /* 0x240 ODT configuration register */ - u32 odtmap; /* 0x244 ODT/rank map register */ - u8 res14[0x8]; /* 0x248 */ - u32 sched; /* 0x250 scheduler control register */ - u8 res15[0x4]; /* 0x254 */ - u32 perfhpr0; /* 0x258 high priority read CAM register 0 */ - u32 perfhpr1; /* 0x25c high priority read CAM register 1 */ - u32 perflpr0; /* 0x260 low priority read CAM register 0 */ - u32 perflpr1; /* 0x264 low priority read CAM register 1 */ - u32 perfwr0; /* 0x268 write CAM register 0 */ - u32 perfwr1; /* 0x26c write CAM register 1 */ -}; - - -struct sunxi_mctl_phy_reg { - u8 res0[0x04]; /* 0x00 revision id ??? */ - u32 pir; /* 0x04 PHY initialisation register */ - u32 pgcr[4]; /* 0x08 PHY general configuration register */ - u32 pgsr[2]; /* 0x18 PHY general status register */ - u32 pllcr; /* 0x20 PLL control register */ - u32 ptr[5]; /* 0x24 PHY timing register */ - u32 acmdlr; /* 0x38 AC master delay line register */ - u32 aclcdlr; /* 0x3c AC local calibrated delay line reg */ - u32 acbdlr[10]; /* 0x40 AC bit delay line register */ - u32 aciocr[6]; /* 0x68 AC IO configuration register */ - u32 dxccr; /* 0x80 DATX8 common configuration register */ - u32 dsgcr; /* 0x84 DRAM system general config register */ - u32 dcr; /* 0x88 DRAM configuration register */ - u32 dtpr[4]; /* 0x8c DRAM timing parameters register */ - u32 mr0; /* 0x9c mode register 0 */ - u32 mr1; /* 0xa0 mode register 1 */ - u32 mr2; /* 0xa4 mode register 2 */ - u32 mr3; /* 0xa8 mode register 3 */ - u32 odtcr; /* 0xac ODT configuration register */ - u32 dtcr; /* 0xb0 data training configuration register */ - u32 dtar[4]; /* 0xb4 data training address register */ - u32 dtdr[2]; /* 0xc4 data training data register */ - u32 dtedr[2]; /* 0xcc data training eye data register */ - u32 rdimmgcr[2]; /* 0xd4 RDIMM general configuration register */ - u32 rdimmcr[2]; /* 0xdc RDIMM control register */ - u32 gpr[2]; /* 0xe4 general purpose register */ - u32 catr[2]; /* 0xec CA training register */ - u32 dqdsr; /* 0xf4 DQS drift register */ - u8 res1[0xc8]; /* 0xf8 */ - u32 bistrr; /* 0x1c0 BIST run register */ - u32 bistwcr; /* 0x1c4 BIST word count register */ - u32 bistmskr[3]; /* 0x1c8 BIST mask register */ - u32 bistlsr; /* 0x1d4 BIST LFSR seed register */ - u32 bistar[3]; /* 0x1d8 BIST address register */ - u32 bistupdr; /* 0x1e4 BIST user pattern data register */ - u32 bistgsr; /* 0x1e8 BIST general status register */ - u32 bistwer; /* 0x1dc BIST word error register */ - u32 bistber[4]; /* 0x1f0 BIST bit error register */ - u32 bistwcsr; /* 0x200 BIST word count status register */ - u32 bistfwr[3]; /* 0x204 BIST fail word register */ - u8 res2[0x28]; /* 0x210 */ - u32 iovcr[2]; /* 0x238 IO VREF control register */ - struct ddrphy_zq { - u32 cr; /* impedance control register */ - u32 pr; /* impedance control data register */ - u32 dr; /* impedance control data register */ - u32 sr; /* impedance control status register */ - } zq[4]; /* 0x240, 0x250, 0x260, 0x270 */ - struct ddrphy_dx { - u32 gcr[4]; /* DATX8 general configuration register */ - u32 gsr[3]; /* DATX8 general status register */ - u32 bdlr[7]; /* DATX8 bit delay line register */ - u32 lcdlr[3]; /* DATX8 local calibrated delay line reg */ - u32 mdlr; /* DATX8 master delay line register */ - u32 gtr; /* DATX8 general timing register */ - u8 res[0x34]; - } dx[4]; /* 0x280, 0x300, 0x380, 0x400 */ -}; - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (3 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_BUSW32 (3 << 12) -#define MCTL_CR_DRAMTYPE_MASK (7 << 16) -#define MCTL_CR_DRAMTYPE_DDR2 (2 << 16) -#define MCTL_CR_DRAMTYPE_DDR3 (3 << 16) -#define MCTL_CR_DRAMTYPE_LPDDR2 (6 << 16) - -#define MCTL_CR_CHANNEL_MASK ((1 << 22) | (1 << 20) | (1 << 19)) -#define MCTL_CR_CHANNEL_SINGLE (1 << 22) -#define MCTL_CR_CHANNEL_DUAL ((1 << 22) | (1 << 20) | (1 << 19)) - -#define MCTL_CCR_CH0_CLK_EN (1 << 15) -#define MCTL_CCR_CH1_CLK_EN (1 << 31) - -/* - * post_cke_x1024 [bits 16..25]: Cycles to wait after driving CKE high - * to start the SDRAM initialization sequence (in 1024s of cycles). - */ -#define MCTL_INIT0_POST_CKE_x1024(n) ((n & 0x0fff) << 16) -/* - * pre_cke_x1024 [bits 0..11] Cycles to wait after reset before driving - * CKE high to start the SDRAM initialization (in 1024s of cycles) - */ -#define MCTL_INIT0_PRE_CKE_x1024(n) ((n & 0x0fff) << 0) -#define MCTL_INIT1_DRAM_RSTN_x1024(n) ((n & 0xff) << 16) -#define MCTL_INIT1_FINAL_WAIT_x32(n) ((n & 0x3f) << 8) -#define MCTL_INIT1_PRE_OCD_x32(n) ((n & 0x0f) << 0) -#define MCTL_INIT2_IDLE_AFTER_RESET_x32(n) ((n & 0xff) << 8) -#define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n) ((n & 0x0f) << 0) -#define MCTL_INIT3_MR(n) ((n & 0xffff) << 16) -#define MCTL_INIT3_EMR(n) ((n & 0xffff) << 0) -#define MCTL_INIT4_EMR2(n) ((n & 0xffff) << 16) -#define MCTL_INIT4_EMR3(n) ((n & 0xffff) << 0) -#define MCTL_INIT5_DEV_ZQINIT_x32(n) ((n & 0x00ff) << 16) -#define MCTL_INIT5_MAX_AUTO_INIT_x1024(n) ((n & 0x03ff) << 0); - -#define MCTL_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) -#define MCTL_DFIUPD0_DIS_AUTO_CTRLUPD (1 << 31) - -#define MCTL_MSTR_DEVICETYPE_DDR3 1 -#define MCTL_MSTR_DEVICETYPE_LPDDR2 4 -#define MCTL_MSTR_DEVICETYPE_LPDDR3 8 -#define MCTL_MSTR_DEVICETYPE(type) \ - ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_DEVICETYPE_DDR3 : \ - ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_DEVICETYPE_LPDDR2 : \ - MCTL_MSTR_DEVICETYPE_LPDDR3)) -#define MCTL_MSTR_BURSTLENGTH4 (2 << 16) -#define MCTL_MSTR_BURSTLENGTH8 (4 << 16) -#define MCTL_MSTR_BURSTLENGTH16 (8 << 16) -#define MCTL_MSTR_BURSTLENGTH(type) \ - ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_BURSTLENGTH8 : \ - ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_BURSTLENGTH4 : \ - MCTL_MSTR_BURSTLENGTH8)) -#define MCTL_MSTR_ACTIVERANKS(x) (((x == 2) ? 3 : 1) << 24) -#define MCTL_MSTR_BUSWIDTH8 (2 << 12) -#define MCTL_MSTR_BUSWIDTH16 (1 << 12) -#define MCTL_MSTR_BUSWIDTH32 (0 << 12) -#define MCTL_MSTR_2TMODE (1 << 10) - -#define MCTL_RFSHCTL3_DIS_AUTO_REFRESH (1 << 0) - -#define MCTL_ZQCTRL0_TZQCS(x) (x << 0) -#define MCTL_ZQCTRL0_TZQCL(x) (x << 16) -#define MCTL_ZQCTRL0_ZQCL_DIS (1 << 30) -#define MCTL_ZQCTRL0_ZQCS_DIS (1 << 31) -#define MCTL_ZQCTRL1_TZQRESET(x) (x << 20) -#define MCTL_ZQCTRL1_TZQSI_x1024(x) (x << 0) -#define MCTL_ZQCTRL2_TZRESET_TRIGGER (1 << 0) - -#define MCTL_PHY_DCR_BYTEMASK (1 << 10) -#define MCTL_PHY_DCR_2TMODE (1 << 28) -#define MCTL_PHY_DCR_DDR8BNK (1 << 3) -#define MCTL_PHY_DRAMMODE_DDR3 3 -#define MCTL_PHY_DRAMMODE_LPDDR2 0 -#define MCTL_PHY_DRAMMODE_LPDDR3 1 - -#define MCTL_DTCR_DEFAULT 0x00003007 -#define MCTL_DTCR_RANKEN(n) (((n == 2) ? 3 : 1) << 24) - -#define MCTL_PGCR1_ZCKSEL_MASK (3 << 23) -#define MCTL_PGCR1_IODDRM_MASK (3 << 7) -#define MCTL_PGCR1_IODDRM_DDR3 (1 << 7) -#define MCTL_PGCR1_IODDRM_DDR3L (2 << 7) -#define MCTL_PGCR1_INHVT_EN (1 << 26) - -#define MCTL_PLLGCR_PLL_BYPASS (1 << 31) -#define MCTL_PLLGCR_PLL_POWERDOWN (1 << 29) - -#define MCTL_PIR_PLL_BYPASS (1 << 17) -#define MCTL_PIR_MASK (~(1 << 17)) -#define MCTL_PIR_INIT (1 << 0) - -#define MCTL_PGSR0_ERRORS (0x1ff << 20) - -/* Constants for assembling MR0 */ -#define DDR3_MR0_PPD_FAST_EXIT (1 << 12) -#define DDR3_MR0_WR(n) \ - ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) -#define DDR3_MR0_CL(n) \ - ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) -#define DDR3_MR0_BL8 (0 << 0) - -#define DDR3_MR1_RTT120OHM ((0 << 9) | (1 << 6) | (0 << 2)) - -#define DDR3_MR2_TWL(n) \ - (((n - 5) & 0x7) << 3) - -#define MCTL_NS2CYCLES_CEIL(ns) ((ns * (CONFIG_DRAM_CLK / 2) + 999) / 1000) - -#define DRAM_TYPE_DDR3 3 -#define DRAM_TYPE_LPDDR2 6 -#define DRAM_TYPE_LPDDR3 7 - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h deleted file mode 100644 index a5a7ebd..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ /dev/null @@ -1,238 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun8i H3 platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_H3_H -#define _SUNXI_DRAM_SUN8I_H3_H - -#include <linux/bitops.h> - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 control register */ - u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */ - u8 res0[0x4]; /* 0x08 */ - u32 tmr; /* 0x0c (unused on H3) */ - u32 mcr[16][2]; /* 0x10 */ - u32 bwcr; /* 0x90 bandwidth control register */ - u32 maer; /* 0x94 master enable register */ - u32 mapr; /* 0x98 master priority register */ - u32 mcgcr; /* 0x9c */ - u32 cpu_bwcr; /* 0xa0 */ - u32 gpu_bwcr; /* 0xa4 */ - u32 ve_bwcr; /* 0xa8 */ - u32 disp_bwcr; /* 0xac */ - u32 other_bwcr; /* 0xb0 */ - u32 total_bwcr; /* 0xb4 */ - u8 res1[0x8]; /* 0xb8 */ - u32 swonr; /* 0xc0 */ - u32 swoffr; /* 0xc4 */ - u8 res2[0x8]; /* 0xc8 */ - u32 cccr; /* 0xd0 */ - u8 res3[0x54]; /* 0xd4 */ - u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */ - u8 res4[0x6cc]; /* 0x134 */ - u32 protect; /* 0x800 */ -}; - -#define MCTL_CR_BL8 (0x4 << 20) - -#define MCTL_CR_1T (0x1 << 19) -#define MCTL_CR_2T (0x0 << 19) - -#define MCTL_CR_LPDDR3 (0x7 << 16) -#define MCTL_CR_LPDDR2 (0x6 << 16) -#define MCTL_CR_DDR3 (0x3 << 16) -#define MCTL_CR_DDR2 (0x2 << 16) - -#define MCTL_CR_SEQUENTIAL (0x1 << 15) -#define MCTL_CR_INTERLEAVED (0x0 << 15) - -#define MCTL_CR_FULL_WIDTH (0x1 << 12) -#define MCTL_CR_HALF_WIDTH (0x0 << 12) -#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12) - -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) -#define MCTL_CR_EIGHT_BANKS (0x1 << 2) -#define MCTL_CR_FOUR_BANKS (0x0 << 2) -#define MCTL_CR_DUAL_RANK (0x1 << 0) -#define MCTL_CR_SINGLE_RANK (0x0 << 0) - -/* - * CR_R1 is a register found in the R40's DRAM controller. It sets various - * parameters for rank 1. Bits [11:0] have the same meaning as the bits in - * MCTL_CR, but they apply to rank 1 only. This implies we can have - * different chips for rank 1 than rank 0. - * - * As address line A15 and CS1 chip select for rank 1 are muxed on the same - * pin, if single rank is used, A15 must be muxed in. - */ -#define MCTL_CR_R1_MUX_A15 (0x1 << 21) - -#define PROTECT_MAGIC (0x94be6fa3) - -struct sunxi_mctl_ctl_reg { - u32 pir; /* 0x00 PHY initialization register */ - u32 pwrctl; /* 0x04 */ - u32 mrctrl; /* 0x08 */ - u32 clken; /* 0x0c */ - u32 pgsr[2]; /* 0x10 PHY general status registers */ - u32 statr; /* 0x18 */ - u8 res1[0x10]; /* 0x1c */ - u32 lp3mr11; /* 0x2c */ - u32 mr[4]; /* 0x30 mode registers */ - u32 pllgcr; /* 0x40 */ - u32 ptr[5]; /* 0x44 PHY timing registers */ - u32 dramtmg[9]; /* 0x58 DRAM timing registers */ - u32 odtcfg; /* 0x7c */ - u32 pitmg[2]; /* 0x80 PHY interface timing registers */ - u8 res2[0x4]; /* 0x88 */ - u32 rfshctl0; /* 0x8c */ - u32 rfshtmg; /* 0x90 refresh timing */ - u32 rfshctl1; /* 0x94 */ - u32 pwrtmg; /* 0x98 */ - u8 res3[0x1c]; /* 0x9c */ - u32 vtfcr; /* 0xb8 (unused on H3) */ - u32 dqsgmr; /* 0xbc */ - u32 dtcr; /* 0xc0 */ - u32 dtar[4]; /* 0xc4 */ - u32 dtdr[2]; /* 0xd4 */ - u32 dtmr[2]; /* 0xdc */ - u32 dtbmr; /* 0xe4 */ - u32 catr[2]; /* 0xe8 */ - u32 dtedr[2]; /* 0xf0 */ - u8 res4[0x8]; /* 0xf8 */ - u32 pgcr[4]; /* 0x100 PHY general configuration registers */ - u32 iovcr[2]; /* 0x110 */ - u32 dqsdr; /* 0x118 */ - u32 dxccr; /* 0x11c */ - u32 odtmap; /* 0x120 */ - u32 zqctl[2]; /* 0x124 */ - u8 res6[0x14]; /* 0x12c */ - u32 zqcr; /* 0x140 ZQ control register */ - u32 zqsr; /* 0x144 ZQ status register */ - u32 zqdr[3]; /* 0x148 ZQ data registers */ - u8 res7[0x6c]; /* 0x154 */ - u32 sched; /* 0x1c0 */ - u32 perfhpr[2]; /* 0x1c4 */ - u32 perflpr[2]; /* 0x1cc */ - u32 perfwr[2]; /* 0x1d4 */ - u8 res8[0x24]; /* 0x1dc */ - u32 acmdlr; /* 0x200 AC master delay line register */ - u32 aclcdlr; /* 0x204 AC local calibrated delay line register */ - u32 aciocr; /* 0x208 AC I/O configuration register */ - u8 res9[0x4]; /* 0x20c */ - u32 acbdlr[31]; /* 0x210 AC bit delay line registers */ - u8 res10[0x74]; /* 0x28c */ - struct { /* 0x300 DATX8 modules*/ - u32 mdlr; /* 0x00 master delay line register */ - u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */ - u32 bdlr[11]; /* 0x10 bit delay line registers */ - u32 sdlr; /* 0x3c output enable bit delay registers */ - u32 gtr; /* 0x40 general timing register */ - u32 gcr; /* 0x44 general configuration register */ - u32 gsr[3]; /* 0x48 general status registers */ - u8 res0[0x2c]; /* 0x54 */ - } dx[4]; - u8 res11[0x388]; /* 0x500 */ - u32 upd2; /* 0x888 */ -}; - -#define PTR3_TDINIT1(x) ((x) << 20) -#define PTR3_TDINIT0(x) ((x) << 0) - -#define PTR4_TDINIT3(x) ((x) << 20) -#define PTR4_TDINIT2(x) ((x) << 0) - -#define DRAMTMG0_TWTP(x) ((x) << 24) -#define DRAMTMG0_TFAW(x) ((x) << 16) -#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) -#define DRAMTMG0_TRAS(x) ((x) << 0) - -#define DRAMTMG1_TXP(x) ((x) << 16) -#define DRAMTMG1_TRTP(x) ((x) << 8) -#define DRAMTMG1_TRC(x) ((x) << 0) - -#define DRAMTMG2_TCWL(x) ((x) << 24) -#define DRAMTMG2_TCL(x) ((x) << 16) -#define DRAMTMG2_TRD2WR(x) ((x) << 8) -#define DRAMTMG2_TWR2RD(x) ((x) << 0) - -#define DRAMTMG3_TMRW(x) ((x) << 16) -#define DRAMTMG3_TMRD(x) ((x) << 12) -#define DRAMTMG3_TMOD(x) ((x) << 0) - -#define DRAMTMG4_TRCD(x) ((x) << 24) -#define DRAMTMG4_TCCD(x) ((x) << 16) -#define DRAMTMG4_TRRD(x) ((x) << 8) -#define DRAMTMG4_TRP(x) ((x) << 0) - -#define DRAMTMG5_TCKSRX(x) ((x) << 24) -#define DRAMTMG5_TCKSRE(x) ((x) << 16) -#define DRAMTMG5_TCKESR(x) ((x) << 8) -#define DRAMTMG5_TCKE(x) ((x) << 0) - -#define RFSHTMG_TREFI(x) ((x) << 16) -#define RFSHTMG_TRFC(x) ((x) << 0) - -#define PIR_CLRSR (0x1 << 27) /* clear status registers */ -#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ -#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ -#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ -#define PIR_PHYRST (0x1 << 6) /* PHY reset */ -#define PIR_DCAL (0x1 << 5) /* DDL calibration */ -#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ -#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ -#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ - -#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ - -#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */ - -#define ACBDLR_WRITE_DELAY(x) ((x) << 8) - -#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */ -#define DXBDLR_DM 8 /* DM BDLR index */ -#define DXBDLR_DQS 9 /* DQS BDLR index */ -#define DXBDLR_DQSN 10 /* DQSN BDLR index */ - -#define DXBDLR_WRITE_DELAY(x) ((x) << 8) -#define DXBDLR_READ_DELAY(x) ((x) << 0) - -/* - * The delay parameters below allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS and DQSN */ -#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) -struct dram_para { - u16 page_size; - u8 bus_full_width; - u8 dual_rank; - u8 row_bits; - u8 bank_bits; - const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 ac_delays[31]; -}; - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - -void mctl_set_timing_params(uint16_t socid, struct dram_para *para); - -#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h deleted file mode 100644 index 40a3f84..0000000 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ /dev/null @@ -1,248 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_GPIO_H -#define _SUNXI_GPIO_H - -#include <linux/types.h> -#include <asm/arch/cpu.h> - -/* - * sunxi has 9 banks of gpio, they are: - * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 - * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 - * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 - */ - -#define SUNXI_GPIO_A 0 -#define SUNXI_GPIO_B 1 -#define SUNXI_GPIO_C 2 -#define SUNXI_GPIO_D 3 -#define SUNXI_GPIO_E 4 -#define SUNXI_GPIO_F 5 -#define SUNXI_GPIO_G 6 -#define SUNXI_GPIO_H 7 -#define SUNXI_GPIO_I 8 - -/* - * This defines the number of GPIO banks for the _main_ GPIO controller. - * You should fix up the padding in struct sunxi_gpio_reg below if you - * change this. - */ -#define SUNXI_GPIO_BANKS 9 - -/* - * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) - * at a different register offset. - * - * sun6i has 2 banks: - * PL0 - PL8 | PM0 - PM7 - * - * sun8i has 1 bank: - * PL0 - PL11 - * - * sun9i has 3 banks: - * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 - */ -#define SUNXI_GPIO_L 11 -#define SUNXI_GPIO_M 12 -#define SUNXI_GPIO_N 13 - -struct sunxi_gpio { - u32 cfg[4]; - u32 dat; - u32 drv[2]; - u32 pull[2]; -}; - -/* gpio interrupt control */ -struct sunxi_gpio_int { - u32 cfg[3]; - u32 ctl; - u32 sta; - u32 deb; /* interrupt debounce */ -}; - -struct sunxi_gpio_reg { - struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; - u8 res[0xbc]; - struct sunxi_gpio_int gpio_int; -}; - -#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ - &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) - -#define GPIO_BANK(pin) ((pin) >> 5) -#define GPIO_NUM(pin) ((pin) & 0x1f) - -#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) -#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) - -#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) -#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) - -#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) -#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) - -/* GPIO bank sizes */ -#define SUNXI_GPIO_A_NR 32 -#define SUNXI_GPIO_B_NR 32 -#define SUNXI_GPIO_C_NR 32 -#define SUNXI_GPIO_D_NR 32 -#define SUNXI_GPIO_E_NR 32 -#define SUNXI_GPIO_F_NR 32 -#define SUNXI_GPIO_G_NR 32 -#define SUNXI_GPIO_H_NR 32 -#define SUNXI_GPIO_I_NR 32 -#define SUNXI_GPIO_L_NR 32 -#define SUNXI_GPIO_M_NR 32 - -#define SUNXI_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + 0) - -enum sunxi_gpio_number { - SUNXI_GPIO_A_START = 0, - SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), - SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), - SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), - SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), - SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), - SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), - SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), - SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), - SUNXI_GPIO_L_START = 352, - SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), - SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), - SUNXI_GPIO_AXP0_START = 1024, -}; - -/* SUNXI GPIO number definitions */ -#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) -#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) -#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) -#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) -#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) -#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) -#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) -#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) -#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) -#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) -#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) -#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) - -#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) - -/* GPIO pin function config */ -#define SUNXI_GPIO_INPUT 0 -#define SUNXI_GPIO_OUTPUT 1 -#define SUNXI_GPIO_DISABLE 7 - -#define SUNXI_GPA_EMAC 2 -#define SUN6I_GPA_GMAC 2 -#define SUN7I_GPA_GMAC 5 -#define SUN6I_GPA_SDC2 5 -#define SUN6I_GPA_SDC3 4 -#define SUN8I_H3_GPA_UART0 2 - -#define SUN4I_GPB_PWM 2 -#define SUN4I_GPB_TWI0 2 -#define SUN4I_GPB_TWI1 2 -#define SUN5I_GPB_TWI1 2 -#define SUN4I_GPB_TWI2 2 -#define SUN5I_GPB_TWI2 2 -#define SUN4I_GPB_UART0 2 -#define SUN5I_GPB_UART0 2 -#define SUN8I_GPB_UART2 2 -#define SUN8I_A33_GPB_UART0 3 -#define SUN8I_A83T_GPB_UART0 2 -#define SUN8I_V3S_GPB_UART0 3 -#define SUN50I_GPB_UART0 4 - -#define SUNXI_GPC_NAND 2 -#define SUNXI_GPC_SPI0 3 -#define SUNXI_GPC_SDC2 3 -#define SUN6I_GPC_SDC3 4 -#define SUN50I_GPC_SPI0 4 - -#define SUN8I_GPD_SDC1 3 -#define SUNXI_GPD_LCD0 2 -#define SUNXI_GPD_LVDS0 3 -#define SUNXI_GPD_PWM 2 - -#define SUN5I_GPE_SDC2 3 -#define SUN8I_GPE_TWI2 3 -#define SUN50I_GPE_TWI2 3 - -#define SUNXI_GPF_SDC0 2 -#define SUNXI_GPF_UART0 4 -#define SUN8I_GPF_UART0 3 - -#define SUN4I_GPG_SDC1 4 -#define SUN5I_GPG_SDC1 2 -#define SUN6I_GPG_SDC1 2 -#define SUN8I_GPG_SDC1 2 -#define SUN6I_GPG_TWI3 2 -#define SUN5I_GPG_UART1 4 - -#define SUN6I_GPH_PWM 2 -#define SUN8I_GPH_PWM 2 -#define SUN4I_GPH_SDC1 5 -#define SUN6I_GPH_TWI0 2 -#define SUN8I_GPH_TWI0 2 -#define SUN50I_GPH_TWI0 2 -#define SUN6I_GPH_TWI1 2 -#define SUN8I_GPH_TWI1 2 -#define SUN50I_GPH_TWI1 2 -#define SUN6I_GPH_TWI2 2 -#define SUN6I_GPH_UART0 2 -#define SUN9I_GPH_UART0 2 -#define SUN50I_H6_GPH_UART0 2 - -#define SUNXI_GPI_SDC3 2 -#define SUN7I_GPI_TWI3 3 -#define SUN7I_GPI_TWI4 3 - -#define SUN6I_GPL0_R_P2WI_SCK 3 -#define SUN6I_GPL1_R_P2WI_SDA 3 - -#define SUN8I_GPL_R_RSB 2 -#define SUN8I_H3_GPL_R_TWI 2 -#define SUN8I_A23_GPL_R_TWI 3 -#define SUN8I_GPL_R_UART 2 -#define SUN50I_GPL_R_TWI 2 - -#define SUN9I_GPN_R_RSB 3 - -/* GPIO pin pull-up/down config */ -#define SUNXI_GPIO_PULL_DISABLE 0 -#define SUNXI_GPIO_PULL_UP 1 -#define SUNXI_GPIO_PULL_DOWN 2 - -/* Virtual AXP0 GPIOs */ -#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" -#define SUNXI_GPIO_AXP0_VBUS_DETECT 4 -#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 -#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 - -void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); -void sunxi_gpio_set_cfgpin(u32 pin, u32 val); -int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); -int sunxi_gpio_get_cfgpin(u32 pin); -int sunxi_gpio_set_drv(u32 pin, u32 val); -int sunxi_gpio_set_pull(u32 pin, u32 val); -int sunxi_name_to_gpio_bank(const char *name); -int sunxi_name_to_gpio(const char *name); -#define name_to_gpio(name) sunxi_name_to_gpio(name) - -#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO -int axp_gpio_init(void); -#else -static inline int axp_gpio_init(void) { return 0; } -#endif - -#endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h b/arch/arm/include/asm/arch-sunxi/gtbus.h deleted file mode 100644 index a89102e..0000000 --- a/arch/arm/include/asm/arch-sunxi/gtbus.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * GTBUS initialisation - * - * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH - * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> - */ - -#ifndef _SUNXI_GTBUS_H -#define _SUNXI_GTBUS_H - -#if defined(CONFIG_MACH_SUN9I) -#include <asm/arch/gtbus_sun9i.h> -#endif - -#ifndef __ASSEMBLY__ -void gtbus_init(void); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h deleted file mode 100644 index f962992..0000000 --- a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * GTBUS initialisation for sun9i - * - * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH - * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> - */ - -#ifndef _SUNXI_GTBUS_SUN9I_H -#define _SUNXI_GTBUS_SUN9I_H - -#include <linux/types.h> - -struct sunxi_gtbus_reg { - u32 mst_cfg[36]; /* 0x000 */ - u8 reserved1[0x70]; /* 0x090 */ - u32 bw_wdw_cfg; /* 0x100 */ - u32 mst_read_prio_cfg[2]; /* 0x104 */ - u32 lvl2_mst_cfg; /* 0x10c */ - u32 sw_clk_on; /* 0x110 */ - u32 sw_clk_off; /* 0x114 */ - u32 pmu_mst_en; /* 0x118 */ - u32 pmu_cfg; /* 0x11c */ - u32 pmu_cnt[19]; /* 0x120 */ - u32 reserved2[0x94]; /* 0x16c */ - u32 cci400_config[3]; /* 0x200 */ - u32 cci400_status[2]; /* 0x20c */ -}; - -/* for register GT_MST_CFG_REG(n) */ -#define GT_ENABLE_REQ (1<<31) /* clock on */ -#define GT_DISABLE_REQ (1<<30) /* clock off */ -#define GT_QOS_SHIFT 28 -#define GT_THD1_SHIFT 16 -#define GT_REQN_MAX 0xf /* max no master requests in one cycle */ -#define GT_REQN_SHIFT 12 -#define GT_THD0_SHIFT 0 - -#define GT_QOS_MAX 0x3 -#define GT_THD_MAX 0xfff -#define GT_BW_WDW_MAX 0xffff - -/* mst_read_prio_cfg */ -#define GT_PRIO_LOW 0 -#define GT_PRIO_HIGH 1 - -/* GTBUS port ids */ -#define GT_PORT_CPUM1 0 -#define GT_PORT_CPUM2 1 -#define GT_PORT_SATA 2 -#define GT_PORT_USB3 3 -#define GT_PORT_FE0 4 -#define GT_PORT_BE1 5 -#define GT_PORT_BE2 6 -#define GT_PORT_IEP0 7 -#define GT_PORT_FE1 8 -#define GT_PORT_BE0 9 -#define GT_PORT_FE2 10 -#define GT_PORT_IEP1 11 -#define GT_PORT_VED 12 -#define GT_PORT_VEE 13 -#define GT_PORT_FD 14 -#define GT_PORT_CSI 15 -#define GT_PORT_MP 16 -#define GT_PORT_HSI 17 -#define GT_PORT_SS 18 -#define GT_PORT_TS 19 -#define GT_PORT_DMA 20 -#define GT_PORT_NDFC0 21 -#define GT_PORT_NDFC1 22 -#define GT_PORT_CPUS 23 -#define GT_PORT_TH 24 -#define GT_PORT_GMAC 25 -#define GT_PORT_USB0 26 -#define GT_PORT_MSTG0 27 -#define GT_PORT_MSTG1 28 -#define GT_PORT_MSTG2 29 -#define GT_PORT_MSTG3 30 -#define GT_PORT_USB1 31 -#define GT_PORT_GPU0 32 -#define GT_PORT_GPU1 33 -#define GT_PORT_USB2 34 -#define GT_PORT_CPUM0 35 - -#define GP_MST_CFG_DEFAULT \ - ((GT_QOS_MAX << GT_QOS_SHIFT) | \ - (GT_THD_MAX << GT_THD1_SHIFT) | \ - (GT_REQN_MAX << GT_REQN_SHIFT) | \ - (GT_THD_MAX << GT_THD0_SHIFT)) - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h deleted file mode 100644 index 1cb2ba6..0000000 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> - */ -#ifndef _SUNXI_I2C_H_ -#define _SUNXI_I2C_H_ - -#include <asm/arch/cpu.h> - -#ifdef CONFIG_I2C0_ENABLE -#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE -#endif -#ifdef CONFIG_I2C1_ENABLE -#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE -#endif -#ifdef CONFIG_I2C2_ENABLE -#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE -#endif -#ifdef CONFIG_I2C3_ENABLE -#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE -#endif -#ifdef CONFIG_I2C4_ENABLE -#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE -#endif -#ifdef CONFIG_R_I2C_ENABLE -#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE -#endif - -/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ -#define CONFIG_SYS_TCLK 24000000 - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/lcdc.h b/arch/arm/include/asm/arch-sunxi/lcdc.h deleted file mode 100644 index 90216bc..0000000 --- a/arch/arm/include/asm/arch-sunxi/lcdc.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform timing controller register and constant defines - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> - */ - -#ifndef _LCDC_H -#define _LCDC_H - -#include <fdtdec.h> - -struct sunxi_lcdc_reg { - u32 ctrl; /* 0x00 */ - u32 int0; /* 0x04 */ - u32 int1; /* 0x08 */ - u8 res0[0x04]; /* 0x0c */ - u32 tcon0_frm_ctrl; /* 0x10 */ - u32 tcon0_frm_seed[6]; /* 0x14 */ - u32 tcon0_frm_table[4]; /* 0x2c */ - u8 res1[4]; /* 0x3c */ - u32 tcon0_ctrl; /* 0x40 */ - u32 tcon0_dclk; /* 0x44 */ - u32 tcon0_timing_active; /* 0x48 */ - u32 tcon0_timing_h; /* 0x4c */ - u32 tcon0_timing_v; /* 0x50 */ - u32 tcon0_timing_sync; /* 0x54 */ - u32 tcon0_hv_intf; /* 0x58 */ - u8 res2[0x04]; /* 0x5c */ - u32 tcon0_cpu_intf; /* 0x60 */ - u32 tcon0_cpu_wr_dat; /* 0x64 */ - u32 tcon0_cpu_rd_dat0; /* 0x68 */ - u32 tcon0_cpu_rd_dat1; /* 0x6c */ - u32 tcon0_ttl_timing0; /* 0x70 */ - u32 tcon0_ttl_timing1; /* 0x74 */ - u32 tcon0_ttl_timing2; /* 0x78 */ - u32 tcon0_ttl_timing3; /* 0x7c */ - u32 tcon0_ttl_timing4; /* 0x80 */ - u32 tcon0_lvds_intf; /* 0x84 */ - u32 tcon0_io_polarity; /* 0x88 */ - u32 tcon0_io_tristate; /* 0x8c */ - u32 tcon1_ctrl; /* 0x90 */ - u32 tcon1_timing_source; /* 0x94 */ - u32 tcon1_timing_scale; /* 0x98 */ - u32 tcon1_timing_out; /* 0x9c */ - u32 tcon1_timing_h; /* 0xa0 */ - u32 tcon1_timing_v; /* 0xa4 */ - u32 tcon1_timing_sync; /* 0xa8 */ - u8 res3[0x44]; /* 0xac */ - u32 tcon1_io_polarity; /* 0xf0 */ - u32 tcon1_io_tristate; /* 0xf4 */ - u8 res4[0x108]; /* 0xf8 */ - u32 mux_ctrl; /* 0x200 */ - u8 res5[0x1c]; /* 0x204 */ - u32 lvds_ana0; /* 0x220 */ - u32 lvds_ana1; /* 0x224 */ -}; - -/* - * LCDC register constants. - */ -#define SUNXI_LCDC_X(x) (((x) - 1) << 16) -#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) -#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) -#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) -#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) -#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) -#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) -#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) -#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) -#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 -#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 -#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 -#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 -#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 -#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) -#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) -#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) -#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) -#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) -#ifdef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) -#else -#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ -#endif -#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) -#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) -#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) -#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) -#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) -#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) -#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) -#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) -#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) -#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) -#ifdef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_LCDC_LVDS_ANA0 0x40040320 -#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) -#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) -#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) -#else -#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 -#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) -#endif -#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) -#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) - -void lcdc_init(struct sunxi_lcdc_reg * const lcdc); -void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); -void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, - const struct display_timing *mode, - int clk_div, bool for_ext_vga_dac, - int depth, int dclk_phase); -void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, - const struct display_timing *mode, - bool ext_hvsync, bool is_composite); -void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon, - int dotclock, int *clk_div, int *clk_double, - bool is_composite); - -#endif /* _LCDC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h deleted file mode 100644 index f2deafd..0000000 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Aaron <leafy.myeh@allwinnertech.com> - * - * MMC register definition for allwinner sunxi platform. - */ - -#ifndef _SUNXI_MMC_H -#define _SUNXI_MMC_H - -#include <linux/types.h> - -struct sunxi_mmc { - u32 gctrl; /* 0x00 global control */ - u32 clkcr; /* 0x04 clock control */ - u32 timeout; /* 0x08 time out */ - u32 width; /* 0x0c bus width */ - u32 blksz; /* 0x10 block size */ - u32 bytecnt; /* 0x14 byte count */ - u32 cmd; /* 0x18 command */ - u32 arg; /* 0x1c argument */ - u32 resp0; /* 0x20 response 0 */ - u32 resp1; /* 0x24 response 1 */ - u32 resp2; /* 0x28 response 2 */ - u32 resp3; /* 0x2c response 3 */ - u32 imask; /* 0x30 interrupt mask */ - u32 mint; /* 0x34 masked interrupt status */ - u32 rint; /* 0x38 raw interrupt status */ - u32 status; /* 0x3c status */ - u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ - u32 funcsel; /* 0x44 function select */ - u32 cbcr; /* 0x48 CIU byte count */ - u32 bbcr; /* 0x4c BIU byte count */ - u32 dbgc; /* 0x50 debug enable */ - u32 res0; /* 0x54 reserved */ - u32 a12a; /* 0x58 Auto command 12 argument */ - u32 ntsr; /* 0x5c New timing set register */ - u32 res1[8]; - u32 dmac; /* 0x80 internal DMA control */ - u32 dlba; /* 0x84 internal DMA descr list base address */ - u32 idst; /* 0x88 internal DMA status */ - u32 idie; /* 0x8c internal DMA interrupt enable */ - u32 chda; /* 0x90 */ - u32 cbda; /* 0x94 */ - u32 res2[26]; -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) - u32 res3[17]; - u32 samp_dl; - u32 res4[46]; -#endif - u32 fifo; /* 0x100 / 0x200 FIFO access address */ -}; - -#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) -#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) -#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) - -#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) -#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) -#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) -#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ - SUNXI_MMC_GCTRL_FIFO_RESET|\ - SUNXI_MMC_GCTRL_DMA_RESET) -#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) -#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) - -#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) -#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) -#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) -#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) -#define SUNXI_MMC_CMD_WRITE (0x1 << 10) -#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) -#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) -#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) -#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) -#define SUNXI_MMC_CMD_START (0x1 << 31) - -#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) -#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) -#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) -#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) -#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) -#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) -#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) -#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) -#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) -#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) -#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) -#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) -#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) -#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) -#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) -#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) -#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) -#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) -#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ - (SUNXI_MMC_RINT_RESP_ERROR | \ - SUNXI_MMC_RINT_RESP_CRC_ERROR | \ - SUNXI_MMC_RINT_DATA_CRC_ERROR | \ - SUNXI_MMC_RINT_RESP_TIMEOUT | \ - SUNXI_MMC_RINT_DATA_TIMEOUT | \ - SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ - SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ - SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ - SUNXI_MMC_RINT_START_BIT_ERROR | \ - SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ -#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ - (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ - SUNXI_MMC_RINT_DATA_OVER | \ - SUNXI_MMC_RINT_COMMAND_DONE | \ - SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) - -#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) -#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) -#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) -#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) -#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) -#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) -#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) - -#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) - -#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) -#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) -#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) - -#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) -#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) - -#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) -#define SUNXI_MMC_COMMON_RESET (1 << 18) - -#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) - -struct mmc *sunxi_mmc_init(int sdc_no); -#endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/p2wi.h b/arch/arm/include/asm/arch-sunxi/p2wi.h deleted file mode 100644 index 5f2a898..0000000 --- a/arch/arm/include/asm/arch-sunxi/p2wi.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform Push-Push i2c register definition. - * - * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> - * http://linux-sunxi.org - * - * (c)Copyright 2006-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_P2WI_H -#define _SUNXI_P2WI_H - -#include <linux/types.h> - -#define P2WI_CTRL_RESET (0x1 << 0) -#define P2WI_CTRL_IRQ_EN (0x1 << 1) -#define P2WI_CTRL_TRANS_ABORT (0x1 << 6) -#define P2WI_CTRL_TRANS_START (0x1 << 7) - -#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) -#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff) -#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) -#define P2WI_CC_CLK_DIV(n) \ - __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n)) -#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) -#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7) - -#define P2WI_IRQ_TRANS_DONE (0x1 << 0) -#define P2WI_IRQ_TRANS_ERR (0x1 << 1) -#define P2WI_IRQ_LOAD_BUSY (0x1 << 2) - -#define P2WI_STAT_TRANS_DONE (0x1 << 0) -#define P2WI_STAT_TRANS_ERR (0x1 << 1) -#define P2WI_STAT_LOAD_BUSY (0x1 << 2) -#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) -#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff) -#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01 -#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02 -#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04 -#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08 -#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10 -#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20 -#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40 -#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80 -#define P2WI_STAT_TRANS_ERR_BYTE_1 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1) -#define P2WI_STAT_TRANS_ERR_BYTE_2 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2) -#define P2WI_STAT_TRANS_ERR_BYTE_3 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3) -#define P2WI_STAT_TRANS_ERR_BYTE_4 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4) -#define P2WI_STAT_TRANS_ERR_BYTE_5 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5) -#define P2WI_STAT_TRANS_ERR_BYTE_6 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6) -#define P2WI_STAT_TRANS_ERR_BYTE_7 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7) -#define P2WI_STAT_TRANS_ERR_BYTE_8 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8) - -#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) -#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff) -#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) -#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff) -#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) -#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff) -#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) -#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff) -#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0) -#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff) -#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8) -#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff) -#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16) -#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff) -#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24) -#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff) - -#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0) -#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7) -#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1) -#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4) - -#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0) -#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff) -#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8) -#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff) -#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16) -#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff) -#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24) -#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff) -#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0) -#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff) -#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8) -#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff) -#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16) -#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff) -#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24) -#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff) - -#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0) -#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1) -#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2) -#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3) -#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4) -#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5) - -#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0) -#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff) -#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8) -#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff) -#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16) -#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff) -#define P2WI_PM_INIT_SEND (0x1 << 31) - -struct sunxi_p2wi_reg { - u32 ctrl; /* 0x00 control */ - u32 cc; /* 0x04 clock control */ - u32 irq; /* 0x08 interrupt */ - u32 status; /* 0x0c status */ - u32 dataddr0; /* 0x10 data address 0 */ - u32 dataddr1; /* 0x14 data address 1 */ - u32 numbytes; /* 0x18 num bytes */ - u32 data0; /* 0x1c data buffer 0 */ - u32 data1; /* 0x20 data buffer 1 */ - u32 linectrl; /* 0x24 line control */ - u32 pm; /* 0x28 power management */ -}; - -void p2wi_init(void); -int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data); -int p2wi_read(const u8 addr, u8 *data); -int p2wi_write(const u8 addr, u8 data); - -#endif /* _SUNXI_P2WI_H */ diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/arch/arm/include/asm/arch-sunxi/pmic_bus.h deleted file mode 100644 index 3ccfe13..0000000 --- a/arch/arm/include/asm/arch-sunxi/pmic_bus.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * Sunxi PMIC bus access helpers header - */ - -#ifndef _SUNXI_PMIC_BUS_H -#define _SUNXI_PMIS_BUS_H - -int pmic_bus_init(void); -int pmic_bus_read(u8 reg, u8 *data); -int pmic_bus_write(u8 reg, u8 data); -int pmic_bus_setbits(u8 reg, u8 bits); -int pmic_bus_clrbits(u8 reg, u8 bits); - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h deleted file mode 100644 index 58a3689..0000000 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi A31 Power Management Unit register definition. - * - * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> - * http://linux-sunxi.org - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_PRCM_H -#define _SUNXI_PRCM_H - -#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) -#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) -#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) -#define PRCM_CPUS_CFG_PRE_DIV(n) \ - __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) -#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) -#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) -#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) -#define PRCM_CPUS_CFG_POST_DIV(n) \ - __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) -#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) -#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) -#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 -#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 -#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 -#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 -#define PRCM_CPUS_CFG_CLK_SRC_LOSC \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) -#define PRCM_CPUS_CFG_CLK_SRC_HOSC \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) -#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) -#define PRCM_CPUS_CFG_CLK_SRC_PDIV \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) - -#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) -#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) -#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) -#define PRCM_APB0_RATIO_DIV(n) \ - __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) - -#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) -#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) - -#define PRCM_APB0_GATE_PIO (0x1 << 0) -#define PRCM_APB0_GATE_IR (0x1 << 1) -#define PRCM_APB0_GATE_TIMER01 (0x1 << 2) -#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ -#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ -#define PRCM_APB0_GATE_UART (0x1 << 4) -#define PRCM_APB0_GATE_1WIRE (0x1 << 5) -#define PRCM_APB0_GATE_I2C (0x1 << 6) - -#define PRCM_APB0_RESET_PIO (0x1 << 0) -#define PRCM_APB0_RESET_IR (0x1 << 1) -#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) -#define PRCM_APB0_RESET_P2WI (0x1 << 3) -#define PRCM_APB0_RESET_UART (0x1 << 4) -#define PRCM_APB0_RESET_1WIRE (0x1 << 5) -#define PRCM_APB0_RESET_I2C (0x1 << 6) - -#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) -#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) -#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) -#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ - __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) -#define __PRCM_PLL_CTRL_USB_CLK_0 0x0 -#define __PRCM_PLL_CTRL_USB_CLK_1 0x1 -#define __PRCM_PLL_CTRL_USB_CLK_2 0x2 -#define __PRCM_PLL_CTRL_USB_CLK_3 0x3 -#define PRCM_PLL_CTRL_USB_CLK_0 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) -#define PRCM_PLL_CTRL_USB_CLK_1 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) -#define PRCM_PLL_CTRL_USB_CLK_2 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) -#define PRCM_PLL_CTRL_USB_CLK_3 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) -#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) -#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ - __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) -#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ - __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) -#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) -#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) -#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 -#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 -#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 -#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 -#define PRCM_PLL_CTRL_HOSC_CLK_0 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) -#define PRCM_PLL_CTRL_HOSC_CLK_1 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) -#define PRCM_PLL_CTRL_HOSC_CLK_2 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) -#define PRCM_PLL_CTRL_HOSC_CLK_3 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) -#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) -#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) -#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) -#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) -#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) -#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ -#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) -#define PRCM_PLL_CTRL_LDO_OUT_MASK \ - __PRCM_PLL_CTRL_LDO_OUT(0x7) -/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ -#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) -#define PRCM_PLL_CTRL_LDO_OUT_H(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) -#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) -#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) -#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) -#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) - -#define PRCM_CLK_1WIRE_GATE (0x1 << 31) - -#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) -#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) -#define __PRCM_CLK_MOD0_M_X(n) (n - 1) -#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) -#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) -#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) -#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) -#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) -#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) -#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) -#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) -#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) -#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) -#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) -#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) - -#define PRCM_APB0_RESET_PIO (0x1 << 0) -#define PRCM_APB0_RESET_IR (0x1 << 1) -#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) -#define PRCM_APB0_RESET_P2WI (0x1 << 3) -#define PRCM_APB0_RESET_UART (0x1 << 4) -#define PRCM_APB0_RESET_1WIRE (0x1 << 5) -#define PRCM_APB0_RESET_I2C (0x1 << 6) - -#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) -#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) -#define __PRCM_CLK_OUTD_M_X() ((n) - 1) -#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) -#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) -#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) -#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) -#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) -#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) -#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) -#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 -#define __PRCM_CLK_OUTD_SRC_LOSC 0x1 -#define __PRCM_CLK_OUTD_SRC_HOSC 0x2 -#define __PRCM_CLK_OUTD_SRC_ERR 0x3 -#define PRCM_CLK_OUTD_SRC_LOSC2 \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) -#define PRCM_CLK_OUTD_SRC_LOSC \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) -#define PRCM_CLK_OUTD_SRC_HOSC \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) -#define PRCM_CLK_OUTD_SRC_ERR \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) -#define PRCM_CLK_OUTD_EN (0x1 << 31) - -#define PRCM_CPU0_PWROFF (0x1 << 0) -#define PRCM_CPU1_PWROFF (0x1 << 1) -#define PRCM_CPU2_PWROFF (0x1 << 2) -#define PRCM_CPU3_PWROFF (0x1 << 3) -#define PRCM_CPU_ALL_PWROFF (0xf << 0) - -#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) -#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) -#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) -#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) - -#define PRCM_VDD_GPU_PWROFF (0x1 << 0) - -#define PRCM_VDD_SYS_RESET (0x1 << 0) - -#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) -#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) - -#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) -#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) - -#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) -#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) - -#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0) -#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1) -#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2) - -#ifndef __ASSEMBLY__ -#include <linux/compiler.h> - -struct __packed sunxi_prcm_reg { - u32 cpus_cfg; /* 0x000 */ - u8 res0[0x8]; /* 0x004 */ - u32 apb0_ratio; /* 0x00c */ - u32 cpu0_cfg; /* 0x010 */ - u32 cpu1_cfg; /* 0x014 */ - u32 cpu2_cfg; /* 0x018 */ - u32 cpu3_cfg; /* 0x01c */ - u8 res1[0x8]; /* 0x020 */ - u32 apb0_gate; /* 0x028 */ - u8 res2[0x14]; /* 0x02c */ - u32 pll_ctrl0; /* 0x040 */ - u32 pll_ctrl1; /* 0x044 */ - u8 res3[0x8]; /* 0x048 */ - u32 clk_1wire; /* 0x050 */ - u32 clk_ir; /* 0x054 */ - u8 res4[0x58]; /* 0x058 */ - u32 apb0_reset; /* 0x0b0 */ - u8 res5[0x3c]; /* 0x0b4 */ - u32 clk_outd; /* 0x0f0 */ - u8 res6[0xc]; /* 0x0f4 */ - u32 cpu_pwroff; /* 0x100 */ - u8 res7[0xc]; /* 0x104 */ - u32 vdd_sys_pwroff; /* 0x110 */ - u8 res8[0x4]; /* 0x114 */ - u32 gpu_pwroff; /* 0x118 */ - u8 res9[0x4]; /* 0x11c */ - u32 vdd_pwr_reset; /* 0x120 */ - u8 res10[0x1c]; /* 0x124 */ - u32 cpu_pwr_clamp[4]; /* 0x140 but first one is actually unused */ - u8 res11[0x30]; /* 0x150 */ - u32 dram_pwr; /* 0x180 */ - u8 res12[0xc]; /* 0x184 */ - u32 dram_tst; /* 0x190 */ - u8 res13[0x3c]; /* 0x194 */ - u32 prcm_sec_switch; /* 0x1d0 */ -}; - -void prcm_apb0_enable(u32 flags); -void prcm_apb0_disable(u32 flags); - -#endif /* __ASSEMBLY__ */ -#endif /* _PRCM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h deleted file mode 100644 index dca283c..0000000 --- a/arch/arm/include/asm/arch-sunxi/pwm.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_PWM_H -#define _SUNXI_PWM_H - -#define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE + 0) -#define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4) - -#define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf) -#define SUNXI_PWM_CTRL_PRESCALE0_MASK 0xf -#define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4) -#define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5) -#define SUNXI_PWM_CTRL_CH0_ACT_STA BIT(5) -#define SUNXI_PWM_CTRL_CLK_GATE BIT(6) - -#define SUNXI_PWM_CH0_PERIOD_MAX (0xffff) -#define SUNXI_PWM_CH0_PERIOD_PRD(x) ((x & 0xffff) << 16) -#define SUNXI_PWM_CH0_PERIOD_DUTY(x) ((x) & 0xffff) - -#define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 - -#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I -#define SUNXI_PWM_PIN0 SUNXI_GPB(2) -#define SUNXI_PWM_MUX SUN4I_GPB_PWM -#endif - -#if defined CONFIG_MACH_SUN6I -#define SUNXI_PWM_PIN0 SUNXI_GPH(13) -#define SUNXI_PWM_MUX SUN6I_GPH_PWM -#endif - -#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33 -#define SUNXI_PWM_PIN0 SUNXI_GPH(0) -#define SUNXI_PWM_MUX SUN8I_GPH_PWM -#endif - -struct sunxi_pwm { - u32 ctrl; - u32 ch0_period; -}; - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h deleted file mode 100644 index 616b6e2..0000000 --- a/arch/arm/include/asm/arch-sunxi/rsb.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * - * Based on allwinner u-boot sources rsb code which is: - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * lixiang <lixiang@allwinnertech.com> - */ - -#ifndef __SUNXI_RSB_H -#define __SUNXI_RSB_H - -#include <common.h> -#include <asm/io.h> - -struct sunxi_rsb_reg { - u32 ctrl; /* 0x00 */ - u32 ccr; /* 0x04 */ - u32 inte; /* 0x08 */ - u32 stat; /* 0x0c */ - u32 addr; /* 0x10 */ - u8 res0[8]; /* 0x14 */ - u32 data; /* 0x1c */ - u8 res1[4]; /* 0x20 */ - u32 lcr; /* 0x24 */ - u32 dmcr; /* 0x28 */ - u32 cmd; /* 0x2c */ - u32 devaddr; /* 0x30 */ -}; - -#define RSB_CTRL_SOFT_RST (1 << 0) -#define RSB_CTRL_START_TRANS (1 << 7) - -#define RSB_STAT_TOVER_INT (1 << 0) -#define RSB_STAT_TERR_INT (1 << 1) -#define RSB_STAT_LBSY_INT (1 << 2) - -#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00 -#define RSB_DMCR_DEVICE_MODE_START (1 << 31) - -#define RSB_CMD_BYTE_WRITE 0x4e -#define RSB_CMD_BYTE_READ 0x8b -#define RSB_CMD_SET_RTSADDR 0xe8 - -#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16) -#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0) - -int rsb_init(void); -int rsb_set_device_address(u16 device_addr, u16 runtime_addr); -int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data); -int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data); - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h deleted file mode 100644 index 8c916e8..0000000 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT0_MAGIC "eGON.BT0" -#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ -#define SPL_MAJOR_BITS 3 -#define SPL_MINOR_BITS 5 -#define SPL_VERSION(maj, min) \ - ((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \ - ((min) & ((1U << SPL_MINOR_BITS) - 1))) - -#define SPL_HEADER_VERSION SPL_VERSION(0, 2) - -#define SPL_ENV_HEADER_VERSION SPL_VERSION(0, 1) -#define SPL_DT_HEADER_VERSION SPL_VERSION(0, 2) -#define SPL_DRAM_HEADER_VERSION SPL_VERSION(0, 3) - -#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS - -/* The low 8-bits of the 'boot_media' field in the SPL header */ -#define SUNXI_BOOTED_FROM_MMC0 0 -#define SUNXI_BOOTED_FROM_NAND 1 -#define SUNXI_BOOTED_FROM_MMC2 2 -#define SUNXI_BOOTED_FROM_SPI 3 -#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10 -#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12 - -/* boot head definition from sun4i boot code */ -struct boot_file_head { - uint32_t b_instruction; /* one intruction jumping to real code */ - uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ - uint32_t check_sum; /* generated by PC */ - uint32_t length; /* generated by PC */ - /* - * We use a simplified header, only filling in what is needed - * by the boot ROM. To be compatible with Allwinner tools we - * would need to implement the proper fields here instead of - * padding. - * - * Actually we want the ability to recognize our "sunxi" variant - * of the SPL. To do so, let's place a special signature into the - * "pub_head_size" field. We can reasonably expect Allwinner's - * boot0 to always have the upper 16 bits of this set to 0 (after - * all the value shouldn't be larger than the limit imposed by - * SRAM size). - * If the signature is present (at 0x14), then we know it's safe - * to use the remaining 8 bytes (at 0x18) for our own purposes. - * (E.g. sunxi-tools "fel" utility can pass information there.) - */ - union { - uint32_t pub_head_size; - uint8_t spl_signature[4]; - }; - uint32_t fel_script_address; /* since v0.1, set by sunxi-fel */ - /* - * If the fel_uEnv_length member below is set to a non-zero value, - * it specifies the size (byte count) of data at fel_script_address. - * At the same time this indicates that the data is in uEnv.txt - * compatible format, ready to be imported via "env import -t". - */ - uint32_t fel_uEnv_length; /* since v0.1, set by sunxi-fel */ - /* - * Offset of an ASCIIZ string (relative to the SPL header), which - * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE). - * This is optional and may be set to NULL. Is intended to be used - * by flash programming tools for providing nice informative messages - * to the users. - */ - uint32_t dt_name_offset; /* since v0.2, set by mksunxiboot */ - uint32_t dram_size; /* in MiB, since v0.3, set by SPL */ - uint32_t boot_media; /* written here by the boot ROM */ - /* A padding area (may be used for storing text strings) */ - uint32_t string_pool[13]; /* since v0.2, filled by mksunxiboot */ - /* The header must be a multiple of 32 bytes (for VBAR alignment) */ -}; - -/* Compile time check to assure proper alignment of structure */ -typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)]; - -#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) - -uint32_t sunxi_get_boot_device(void); - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h deleted file mode 100644 index 0646022..0000000 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <linux/types.h> - -void sdelay(unsigned long); - -/* return_to_fel() - Return to BROM from SPL - * - * This returns back into the BROM after U-Boot SPL has performed its initial - * init. It uses the provided lr and sp to do so. - * - * @lr: BROM link register value (return address) - * @sp: BROM stack pointer - */ -void return_to_fel(uint32_t lr, uint32_t sp); - -/* Board / SoC level designware gmac init */ -#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC -void eth_init_board(void); -#else -static inline void eth_init_board(void) {} -#endif - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h deleted file mode 100644 index 6f138d0..0000000 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * Configuration settings for the Allwinner A10-evb board. - */ - -#ifndef _SUNXI_TIMER_H_ -#define _SUNXI_TIMER_H_ - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> -#include <asm/arch/watchdog.h> - -/* General purpose timer */ -struct sunxi_timer { - u32 ctl; - u32 inter; - u32 val; - u8 res[4]; -}; - -/* Audio video sync*/ -struct sunxi_avs { - u32 ctl; /* 0x80 */ - u32 cnt0; /* 0x84 */ - u32 cnt1; /* 0x88 */ - u32 div; /* 0x8c */ -}; - -/* 64 bit counter */ -struct sunxi_64cnt { - u32 ctl; /* 0xa0 */ - u32 lo; /* 0xa4 */ - u32 hi; /* 0xa8 */ -}; - -/* Rtc */ -struct sunxi_rtc { - u32 ctl; /* 0x100 */ - u32 yymmdd; /* 0x104 */ - u32 hhmmss; /* 0x108 */ -}; - -/* Alarm */ -struct sunxi_alarm { - u32 ddhhmmss; /* 0x10c */ - u32 hhmmss; /* 0x110 */ - u32 en; /* 0x114 */ - u32 irqen; /* 0x118 */ - u32 irqsta; /* 0x11c */ -}; - -/* Timer general purpose register */ -struct sunxi_tgp { - u32 tgpd; -}; - -struct sunxi_timer_reg { - u32 tirqen; /* 0x00 */ - u32 tirqsta; /* 0x04 */ - u8 res1[8]; - struct sunxi_timer timer[6]; /* We have 6 timers */ - u8 res2[16]; - struct sunxi_avs avs; -#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) - struct sunxi_wdog wdog; /* 0x90 */ - /* XXX the following is not accurate for sun5i/sun7i */ - struct sunxi_64cnt cnt64; /* 0xa0 */ - u8 res4[0x58]; - struct sunxi_rtc rtc; - struct sunxi_alarm alarm; - struct sunxi_tgp tgp[4]; - u8 res5[8]; - u32 cpu_cfg; -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) - u8 res3[16]; - struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ -#endif -}; - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h deleted file mode 100644 index 46cd87e..0000000 --- a/arch/arm/include/asm/arch-sunxi/tve.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi TV encoder register and constant defines - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> - */ - -#ifndef _TVE_H -#define _TVE_H - -enum tve_mode { - tve_mode_vga, - tve_mode_composite_pal, - tve_mode_composite_ntsc, - tve_mode_composite_pal_m, - tve_mode_composite_pal_nc, -}; - -/* - * This is based on the A10s User Manual, and the A10s only supports - * composite video and not vga like the A10 / A20 does, still other - * than the removed vga out capability the tvencoder seems to be the same. - * "unknown#" registers are registers which are used in the A10 kernel code, - * but not documented in the A10s User Manual. - */ -struct sunxi_tve_reg { - u32 gctrl; /* 0x000 */ - u32 cfg0; /* 0x004 */ - u32 dac_cfg0; /* 0x008 */ - u32 filter; /* 0x00c */ - u32 chroma_freq; /* 0x010 */ - u32 porch_num; /* 0x014 */ - u32 unknown0; /* 0x018 */ - u32 line_num; /* 0x01c */ - u32 blank_black_level; /* 0x020 */ - u32 unknown1; /* 0x024, seems to be 1 byte per dac */ - u8 res0[0x08]; /* 0x028 */ - u32 auto_detect_en; /* 0x030 */ - u32 auto_detect_int_status; /* 0x034 */ - u32 auto_detect_status; /* 0x038 */ - u32 auto_detect_debounce; /* 0x03c */ - u32 csc_reg0; /* 0x040 */ - u32 csc_reg1; /* 0x044 */ - u32 csc_reg2; /* 0x048 */ - u32 csc_reg3; /* 0x04c */ - u8 res1[0xb0]; /* 0x050 */ - u32 color_burst; /* 0x100 */ - u32 vsync_num; /* 0x104 */ - u32 notch_freq; /* 0x108 */ - u32 cbr_level; /* 0x10c */ - u32 burst_phase; /* 0x110 */ - u32 burst_width; /* 0x114 */ - u32 unknown2; /* 0x118 */ - u32 sync_vbi_level; /* 0x11c */ - u32 white_level; /* 0x120 */ - u32 active_num; /* 0x124 */ - u32 chroma_bw_gain; /* 0x128 */ - u32 notch_width; /* 0x12c */ - u32 resync_num; /* 0x130 */ - u32 slave_para; /* 0x134 */ - u32 cfg1; /* 0x138 */ - u32 cfg2; /* 0x13c */ -}; - -/* - * TVE register constants. - */ -#define SUNXI_TVE_GCTRL_ENABLE (1 << 0) -/* - * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed - * dac from tve1. When using tve1 the mux value must be written to both tve0's - * and tve1's gctrl reg. - */ -#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4)) -#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) -#define SUNXI_TVE_CFG0_VGA 0x20000000 -#define SUNXI_TVE_CFG0_PAL 0x07030001 -#define SUNXI_TVE_CFG0_NTSC 0x07030000 -#define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 -#ifdef CONFIG_MACH_SUN5I -#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 -#else -#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 -#endif -#define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 -#define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 -#define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 -#define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018 -#define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020 -#define SUNXI_TVE_LINE_NUM_PAL 0x00160271 -#define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d -#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc -#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a -#define SUNXI_TVE_UNKNOWN1_VGA 0x00000000 -#define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818 -#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0)) -#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16)) -#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0)) -#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8) -#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8)) -#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0 -#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1 -#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 -#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) -#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) -#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) -#define SUNXI_TVE_CSC_REG0 0x08440832 -#define SUNXI_TVE_CSC_REG1 0x3b6dace1 -#define SUNXI_TVE_CSC_REG2 0x0e1d13dc -#define SUNXI_TVE_CSC_REG3 0x00108080 -#define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000 -#define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828 -#define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f -#define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000 -#define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e -#define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0 -#define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0 -#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0 -#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0 -#define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002 -#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101 -#define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c -#define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c -#define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000 - -void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode); -void tvencoder_enable(struct sunxi_tve_reg * const tve); - -#endif /* _TVE_H */ diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h deleted file mode 100644 index 7a6fcae..0000000 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org> - */ - -#ifndef _SUNXI_TZPC_H -#define _SUNXI_TZPC_H - -#ifndef __ASSEMBLY__ -struct sunxi_tzpc { - u32 r0size; /* 0x00 Size of secure RAM region */ - u32 decport0_status; /* 0x04 Status of decode protection port 0 */ - u32 decport0_set; /* 0x08 Set decode protection port 0 */ - u32 decport0_clear; /* 0x0c Clear decode protection port 0 */ - /* For A80 and later SoCs */ - u32 decport1_status; /* 0x10 Status of decode protection port 1 */ - u32 decport1_set; /* 0x14 Set decode protection port 1 */ - u32 decport1_clear; /* 0x18 Clear decode protection port 1 */ - u32 decport2_status; /* 0x1c Status of decode protection port 2 */ - u32 decport2_set; /* 0x20 Set decode protection port 2 */ - u32 decport2_clear; /* 0x24 Clear decode protection port 2 */ -}; -#endif - -#define SUN6I_TZPC_DECPORT0_RTC (1 << 1) - -#define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe -#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff -#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f - -void tzpc_init(void); - -#endif /* _SUNXI_TZPC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h deleted file mode 100644 index 38e2ef2..0000000 --- a/arch/arm/include/asm/arch-sunxi/watchdog.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Chen-Yu Tsai <wens@csie.org> - * - * Watchdog register definitions - */ - -#ifndef _SUNXI_WATCHDOG_H_ -#define _SUNXI_WATCHDOG_H_ - -#define WDT_CTRL_RESTART (0x1 << 0) -#define WDT_CTRL_KEY (0x0a57 << 1) - -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN5I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - -#define WDT_MODE_EN (0x1 << 0) -#define WDT_MODE_RESET_EN (0x1 << 1) - -struct sunxi_wdog { - u32 ctl; /* 0x00 */ - u32 mode; /* 0x04 */ - u32 res[2]; -}; - -#else - -#define WDT_CFG_RESET (0x1) -#define WDT_MODE_EN (0x1) - -struct sunxi_wdog { - u32 irq_en; /* 0x00 */ - u32 irq_sta; /* 0x04 */ - u32 res1[2]; - u32 ctl; /* 0x10 */ - u32 cfg; /* 0x14 */ - u32 mode; /* 0x18 */ - u32 res2; -}; - -#endif - -#endif /* _SUNXI_WATCHDOG_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h deleted file mode 100644 index de21dff..0000000 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - */ -#include <asm/types.h> - -/* Stabilization delays, in usec */ -#define PLL_STABILIZATION_DELAY (300) -#define IO_STABILIZATION_DELAY (1000) - -#define PLLX_ENABLED (1 << 30) -#define CCLK_BURST_POLICY 0x20008888 -#define SUPER_CCLK_DIVIDER 0x80000000 - -/* Calculate clock fractional divider value from ref and target frequencies */ -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) - -/* Calculate clock frequency value from reference and clock divider value */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) - -/* AVP/CPU ID */ -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ -#define PG_UP_TAG_0 0x0 - -/* AP base physical address of internal SRAM */ -#define NV_PA_BASE_SRAM 0x40000000 - -#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) -#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) -#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) - -#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) -#define FLOW_MODE_STOP 2 -#define HALT_COP_EVENT_JTAG (1 << 28) -#define HALT_COP_EVENT_IRQ_1 (1 << 11) -#define HALT_COP_EVENT_FIQ_1 (1 << 9) - -/* This is the main entry into U-Boot, used by the Cortex-A9 */ -extern void _start(void); - -/** - * Works out the SOC/SKU type used for clocks settings - * - * @return SOC type - see TEGRA_SOC... - */ -int tegra_get_chip_sku(void); - -/** - * Returns the pure SOC (chip ID) from the HIDREV register - * - * @return SOC ID - see CHIPID_TEGRAxx... - */ -int tegra_get_chip(void); - -/** - * Returns the SKU ID from the sku_info register - * - * @return SKU ID - see SKU_ID_Txx... - */ -int tegra_get_sku_info(void); - -/* Do any chip-specific cache config */ -void config_cache(void); - -#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) -bool tegra_cpu_is_non_secure(void); -#endif diff --git a/arch/arm/include/asm/arch-tegra/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h deleted file mode 100644 index d438966..0000000 --- a/arch/arm/include/asm/arch-tegra/apb_misc.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2012 The Chromium OS Authors. - */ - -#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ - -/* APB_MISC_PP registers */ -struct apb_misc_pp_ctlr { - u32 reserved0[2]; - u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ - u32 reserved1[6]; /* 0x0c .. 0x20 */ - u32 cfg_ctl; /* 0x24 */ -}; - -/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ -#define RAM_CODE_SHIFT 4 -#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) - -#endif diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h deleted file mode 100644 index 24d0db8..0000000 --- a/arch/arm/include/asm/arch-tegra/board.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA_BOARD_H_ -#define _TEGRA_BOARD_H_ - -/* Set up pinmux to make UART usable */ -void gpio_early_init_uart(void); - -/* Set up early UART output */ -void board_init_uart_f(void); - -/* Set up any early GPIOs the board might need for proper operation */ -void gpio_early_init(void); /* overrideable GPIO config */ - -/* - * Hooks to allow boards to set up the pinmux for a specific function. - * Has to be implemented in the board files as we don't yet support pinmux - * setup from FDT. If a board file does not implement one of those functions - * an empty stub function will be called. - */ - -void pinmux_init(void); /* overridable general pinmux setup */ -void pin_mux_usb(void); /* overridable USB pinmux setup */ -void pin_mux_spi(void); /* overridable SPI pinmux setup */ -void pin_mux_nand(void); /* overridable NAND pinmux setup */ -void pin_mux_mmc(void); /* overridable mmc pinmux setup */ -void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ - -#endif diff --git a/arch/arm/include/asm/arch-tegra/bpmp_abi.h b/arch/arm/include/asm/arch-tegra/bpmp_abi.h deleted file mode 100644 index 373da52..0000000 --- a/arch/arm/include/asm/arch-tegra/bpmp_abi.h +++ /dev/null @@ -1,1590 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. - */ - -#ifndef _ABI_BPMP_ABI_H_ -#define _ABI_BPMP_ABI_H_ - -#ifdef LK -#include <stdint.h> -#endif - -#ifndef __ABI_PACKED -#define __ABI_PACKED __attribute__((packed)) -#endif - -#ifdef NO_GCC_EXTENSIONS -#define EMPTY char empty; -#define EMPTY_ARRAY 1 -#else -#define EMPTY -#define EMPTY_ARRAY 0 -#endif - -#ifndef __UNION_ANON -#define __UNION_ANON -#endif -/** - * @file - */ - - -/** - * @defgroup MRQ MRQ Messages - * @brief Messages sent to/from BPMP via IPC - * @{ - * @defgroup MRQ_Format Message Format - * @defgroup MRQ_Codes Message Request (MRQ) Codes - * @defgroup MRQ_Payloads Message Payloads - * @defgroup Error_Codes Error Codes - * @} - */ - -/** - * @addtogroup MRQ_Format Message Format - * @{ - * The CPU requests the BPMP to perform a particular service by - * sending it an IVC frame containing a single MRQ message. An MRQ - * message consists of a @ref mrq_request followed by a payload whose - * format depends on mrq_request::mrq. - * - * The BPMP processes the data and replies with an IVC frame (on the - * same IVC channel) containing and MRQ response. An MRQ response - * consists of a @ref mrq_response followed by a payload whose format - * depends on the associated mrq_request::mrq. - * - * A well-defined subset of the MRQ messages that the CPU sends to the - * BPMP can lead to BPMP eventually sending an MRQ message to the - * CPU. For example, when the CPU uses an #MRQ_THERMAL message to set - * a thermal trip point, the BPMP may eventually send a single - * #MRQ_THERMAL message of its own to the CPU indicating that the trip - * point has been crossed. - * @} - */ - -/** - * @ingroup MRQ_Format - * @brief header for an MRQ message - * - * Provides the MRQ number for the MRQ message: #mrq. The remainder of - * the MRQ message is a payload (immediately following the - * mrq_request) whose format depends on mrq. - * - * @todo document the flags - */ -struct mrq_request { - /** @brief MRQ number of the request */ - uint32_t mrq; - /** @brief flags for the request */ - uint32_t flags; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Format - * @brief header for an MRQ response - * - * Provides an error code for the associated MRQ message. The - * remainder of the MRQ response is a payload (immediately following - * the mrq_response) whose format depends on the associated - * mrq_request::mrq - * - * @todo document the flags - */ -struct mrq_response { - /** @brief error code for the MRQ request itself */ - int32_t err; - /** @brief flags for the response */ - uint32_t flags; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Format - * Minimum needed size for an IPC message buffer - */ -#define MSG_MIN_SZ 128 -/** - * @ingroup MRQ_Format - * Minimum size guaranteed for data in an IPC message buffer - */ -#define MSG_DATA_MIN_SZ 120 - -/** - * @ingroup MRQ_Codes - * @name Legal MRQ codes - * These are the legal values for mrq_request::mrq - * @{ - */ - -#define MRQ_PING 0 -#define MRQ_QUERY_TAG 1 -#define MRQ_MODULE_LOAD 4 -#define MRQ_MODULE_UNLOAD 5 -#define MRQ_TRACE_MODIFY 7 -#define MRQ_WRITE_TRACE 8 -#define MRQ_THREADED_PING 9 -#define MRQ_MODULE_MAIL 11 -#define MRQ_DEBUGFS 19 -#define MRQ_RESET 20 -#define MRQ_I2C 21 -#define MRQ_CLK 22 -#define MRQ_QUERY_ABI 23 -#define MRQ_PG_READ_STATE 25 -#define MRQ_PG_UPDATE_STATE 26 -#define MRQ_THERMAL 27 -#define MRQ_CPU_VHINT 28 -#define MRQ_ABI_RATCHET 29 -#define MRQ_EMC_DVFS_LATENCY 31 -#define MRQ_TRACE_ITER 64 - -/** @} */ - -/** - * @ingroup MRQ_Codes - * @brief Maximum MRQ code to be sent by CPU software to - * BPMP. Subject to change in future - */ -#define MAX_CPU_MRQ_ID 64 - -/** - * @addtogroup MRQ_Payloads Message Payloads - * @{ - * @defgroup Ping - * @defgroup Query_Tag Query Tag - * @defgroup Module Loadable Modules - * @defgroup Trace - * @defgroup Debugfs - * @defgroup Reset - * @defgroup I2C - * @defgroup Clocks - * @defgroup ABI_info ABI Info - * @defgroup MC_Flush MC Flush - * @defgroup Powergating - * @defgroup Thermal - * @defgroup Vhint CPU Voltage hint - * @defgroup MRQ_Deprecated Deprecated MRQ messages - * @defgroup EMC - * @} - */ - - -/** - * @ingroup MRQ_Codes - * @def MRQ_PING - * @brief A simple ping - * - * * Platforms: All - * * Initiators: Any - * * Targets: Any - * * Request Payload: @ref mrq_ping_request - * * Response Payload: @ref mrq_ping_response - * - * @ingroup MRQ_Codes - * @def MRQ_THREADED_PING - * @brief A deeper ping - * - * * Platforms: All - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_ping_request - * * Response Payload: @ref mrq_ping_response - * - * Behavior is equivalent to a simple #MRQ_PING except that BPMP - * responds from a thread context (providing a slightly more robust - * sign of life). - * - */ - -/** - * @ingroup Ping - * @brief request with #MRQ_PING - * - * Used by the sender of an #MRQ_PING message to request a pong from - * recipient. The response from the recipient is computed based on - * #challenge. - */ -struct mrq_ping_request { -/** @brief arbitrarily chosen value */ - uint32_t challenge; -} __ABI_PACKED; - -/** - * @ingroup Ping - * @brief response to #MRQ_PING - * - * Sent in response to an #MRQ_PING message. #reply should be the - * mrq_ping_request challenge left shifted by 1 with the carry-bit - * dropped. - * - */ -struct mrq_ping_response { - /** @brief response to the MRQ_PING challege */ - uint32_t reply; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_QUERY_TAG - * @brief Query BPMP firmware's tag (i.e. version information) - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_query_tag_request - * * Response Payload: N/A - * - */ - -/** - * @ingroup Query_Tag - * @brief request with #MRQ_QUERY_TAG - * - * Used by #MRQ_QUERY_TAG call to ask BPMP to fill in the memory - * pointed by #addr with BPMP firmware header. - * - * The sender is reponsible for ensuring that #addr is mapped in to - * the recipient's address map. - */ -struct mrq_query_tag_request { - /** @brief base address to store the firmware header */ - uint32_t addr; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_MODULE_LOAD - * @brief dynamically load a BPMP code module - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_module_load_request - * * Response Payload: @ref mrq_module_load_response - * - * @note This MRQ is disabled on production systems - * - */ - -/** - * @ingroup Module - * @brief request with #MRQ_MODULE_LOAD - * - * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically - * load the code located at #phys_addr and having size #size - * bytes. #phys_addr is treated as a void pointer. - * - * The recipient copies the code from #phys_addr to locally allocated - * memory prior to responding to this message. - * - * @todo document the module header format - * - * The sender is responsible for ensuring that the code is mapped in - * the recipient's address map. - * - */ -struct mrq_module_load_request { - /** @brief base address of the code to load. Treated as (void *) */ - uint32_t phys_addr; /* (void *) */ - /** @brief size in bytes of code to load */ - uint32_t size; -} __ABI_PACKED; - -/** - * @ingroup Module - * @brief response to #MRQ_MODULE_LOAD - * - * @todo document mrq_response::err - */ -struct mrq_module_load_response { - /** @brief handle to the loaded module */ - uint32_t base; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_MODULE_UNLOAD - * @brief unload a previously loaded code module - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_module_unload_request - * * Response Payload: N/A - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Module - * @brief request with #MRQ_MODULE_UNLOAD - * - * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded - * module be unloaded. - */ -struct mrq_module_unload_request { - /** @brief handle of the module to unload */ - uint32_t base; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_TRACE_MODIFY - * @brief modify the set of enabled trace events - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_trace_modify_request - * * Response Payload: @ref mrq_trace_modify_response - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Trace - * @brief request with #MRQ_TRACE_MODIFY - * - * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace - * events. #set takes precedence for any bit set in both #set and - * #clr. - */ -struct mrq_trace_modify_request { - /** @brief bit mask of trace events to disable */ - uint32_t clr; - /** @brief bit mask of trace events to enable */ - uint32_t set; -} __ABI_PACKED; - -/** - * @ingroup Trace - * @brief response to #MRQ_TRACE_MODIFY - * - * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the - * state of which events are enabled after the recipient acted on the - * message. - * - */ -struct mrq_trace_modify_response { - /** @brief bit mask of trace event enable states */ - uint32_t mask; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_WRITE_TRACE - * @brief Write trace data to a buffer - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_write_trace_request - * * Response Payload: @ref mrq_write_trace_response - * - * mrq_response::err depends on the @ref mrq_write_trace_request field - * values. err is -#BPMP_EINVAL if size is zero or area is NULL or - * area is in an illegal range. A positive value for err indicates the - * number of bytes written to area. - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Trace - * @brief request with #MRQ_WRITE_TRACE - * - * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace - * data from the recipient's local buffer to the output buffer. #area - * is treated as a byte-aligned pointer in the recipient's address - * space. - * - * The sender is responsible for ensuring that the output - * buffer is mapped in the recipient's address map. The recipient is - * responsible for protecting its own code and data from accidental - * overwrites. - */ -struct mrq_write_trace_request { - /** @brief base address of output buffer */ - uint32_t area; - /** @brief size in bytes of the output buffer */ - uint32_t size; -} __ABI_PACKED; - -/** - * @ingroup Trace - * @brief response to #MRQ_WRITE_TRACE - * - * Once this response is sent, the respondent will not access the - * output buffer further. - */ -struct mrq_write_trace_response { - /** - * @brief flag whether more data remains in local buffer - * - * Value is 1 if the entire local trace buffer has been - * drained to the outputbuffer. Value is 0 otherwise. - */ - uint32_t eof; -} __ABI_PACKED; - -/** @private */ -struct mrq_threaded_ping_request { - uint32_t challenge; -} __ABI_PACKED; - -/** @private */ -struct mrq_threaded_ping_response { - uint32_t reply; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_MODULE_MAIL - * @brief send a message to a loadable module - * - * * Platforms: All - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_module_mail_request - * * Response Payload: @ref mrq_module_mail_response - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Module - * @brief request with #MRQ_MODULE_MAIL - */ -struct mrq_module_mail_request { - /** @brief handle to the previously loaded module */ - uint32_t base; - /** @brief module-specific mail payload - * - * The length of data[ ] is unknown to the BPMP core firmware - * but it is limited to the size of an IPC message. - */ - uint8_t data[EMPTY_ARRAY]; -} __ABI_PACKED; - -/** - * @ingroup Module - * @brief response to #MRQ_MODULE_MAIL - */ -struct mrq_module_mail_response { - /** @brief module-specific mail payload - * - * The length of data[ ] is unknown to the BPMP core firmware - * but it is limited to the size of an IPC message. - */ - uint8_t data[EMPTY_ARRAY]; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_DEBUGFS - * @brief Interact with BPMP's debugfs file nodes - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_debugfs_request - * * Response Payload: @ref mrq_debugfs_response - */ - -/** - * @addtogroup Debugfs - * @{ - * - * The BPMP firmware implements a pseudo-filesystem called - * debugfs. Any driver within the firmware may register with debugfs - * to expose an arbitrary set of "files" in the filesystem. When - * software on the CPU writes to a debugfs file, debugfs passes the - * written data to a callback provided by the driver. When software on - * the CPU reads a debugfs file, debugfs queries the driver for the - * data to return to the CPU. The intention of the debugfs filesystem - * is to provide information useful for debugging the system at - * runtime. - * - * @note The files exposed via debugfs are not part of the - * BPMP firmware's ABI. debugfs files may be added or removed in any - * given version of the firmware. Typically the semantics of a debugfs - * file are consistent from version to version but even that is not - * guaranteed. - * - * @} - */ -/** @ingroup Debugfs */ -enum mrq_debugfs_commands { - CMD_DEBUGFS_READ = 1, - CMD_DEBUGFS_WRITE = 2, - CMD_DEBUGFS_DUMPDIR = 3, - CMD_DEBUGFS_MAX -}; - -/** - * @ingroup Debugfs - * @brief parameters for CMD_DEBUGFS_READ/WRITE command - */ -struct cmd_debugfs_fileop_request { - /** @brief physical address pointing at filename */ - uint32_t fnameaddr; - /** @brief length in bytes of filename buffer */ - uint32_t fnamelen; - /** @brief physical address pointing to data buffer */ - uint32_t dataaddr; - /** @brief length in bytes of data buffer */ - uint32_t datalen; -} __ABI_PACKED; - -/** - * @ingroup Debugfs - * @brief parameters for CMD_DEBUGFS_READ/WRITE command - */ -struct cmd_debugfs_dumpdir_request { - /** @brief physical address pointing to data buffer */ - uint32_t dataaddr; - /** @brief length in bytes of data buffer */ - uint32_t datalen; -} __ABI_PACKED; - -/** - * @ingroup Debugfs - * @brief response data for CMD_DEBUGFS_READ/WRITE command - */ -struct cmd_debugfs_fileop_response { - /** @brief always 0 */ - uint32_t reserved; - /** @brief number of bytes read from or written to data buffer */ - uint32_t nbytes; -} __ABI_PACKED; - -/** - * @ingroup Debugfs - * @brief response data for CMD_DEBUGFS_DUMPDIR command - */ -struct cmd_debugfs_dumpdir_response { - /** @brief always 0 */ - uint32_t reserved; - /** @brief number of bytes read from or written to data buffer */ - uint32_t nbytes; -} __ABI_PACKED; - -/** - * @ingroup Debugfs - * @brief request with #MRQ_DEBUGFS. - * - * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs - * command to execute. Legal commands are the values of @ref - * mrq_debugfs_commands. Each command requires a specific additional - * payload of data. - * - * |command |payload| - * |-------------------|-------| - * |CMD_DEBUGFS_READ |fop | - * |CMD_DEBUGFS_WRITE |fop | - * |CMD_DEBUGFS_DUMPDIR|dumpdir| - */ -struct mrq_debugfs_request { - uint32_t cmd; - union { - struct cmd_debugfs_fileop_request fop; - struct cmd_debugfs_dumpdir_request dumpdir; - } __UNION_ANON; -} __ABI_PACKED; - -/** - * @ingroup Debugfs - */ -struct mrq_debugfs_response { - /** @brief always 0 */ - int32_t reserved; - union { - /** @brief response data for CMD_DEBUGFS_READ OR - * CMD_DEBUGFS_WRITE command - */ - struct cmd_debugfs_fileop_response fop; - /** @brief response data for CMD_DEBUGFS_DUMPDIR command */ - struct cmd_debugfs_dumpdir_response dumpdir; - } __UNION_ANON; -} __ABI_PACKED; - -/** - * @addtogroup Debugfs - * @{ - */ -#define DEBUGFS_S_ISDIR (1 << 9) -#define DEBUGFS_S_IRUSR (1 << 8) -#define DEBUGFS_S_IWUSR (1 << 7) -/** @} */ - - -/** - * @ingroup MRQ_Codes - * @def MRQ_RESET - * @brief reset an IP block - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_reset_request - * * Response Payload: N/A - */ - -/** - * @ingroup Reset - */ -enum mrq_reset_commands { - CMD_RESET_ASSERT = 1, - CMD_RESET_DEASSERT = 2, - CMD_RESET_MODULE = 3, - CMD_RESET_MAX, /* not part of ABI and subject to change */ -}; - -/** - * @ingroup Reset - * @brief request with MRQ_RESET - * - * Used by the sender of an #MRQ_RESET message to request BPMP to - * assert or or deassert a given reset line. - */ -struct mrq_reset_request { - /** @brief reset action to perform (@enum mrq_reset_commands) */ - uint32_t cmd; - /** @brief id of the reset to affected */ - uint32_t reset_id; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_I2C - * @brief issue an i2c transaction - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_i2c_request - * * Response Payload: @ref mrq_i2c_response - */ - -/** - * @addtogroup I2C - * @{ - */ -#define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE (MSG_DATA_MIN_SZ - 12) -#define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE (MSG_DATA_MIN_SZ - 4) -/** @} */ - -/** - * @ingroup I2C - * @name Serial I2C flags - * Use these flags with serial_i2c_request::flags - * @{ - */ -#define SERIALI2C_TEN 0x0010 -#define SERIALI2C_RD 0x0001 -#define SERIALI2C_STOP 0x8000 -#define SERIALI2C_NOSTART 0x4000 -#define SERIALI2C_REV_DIR_ADDR 0x2000 -#define SERIALI2C_IGNORE_NAK 0x1000 -#define SERIALI2C_NO_RD_ACK 0x0800 -#define SERIALI2C_RECV_LEN 0x0400 -/** @} */ -/** @ingroup I2C */ -enum { - CMD_I2C_XFER = 1 -}; - -/** - * @ingroup I2C - * @brief serializable i2c request - * - * Instances of this structure are packed (little-endian) into - * cmd_i2c_xfer_request::data_buf. Each instance represents a single - * transaction (or a portion of a transaction with repeated starts) on - * an i2c bus. - * - * Because these structures are packed, some instances are likely to - * be misaligned. Additionally because #data is variable length, it is - * not possible to iterate through a serialized list of these - * structures without inspecting #len in each instance. It may be - * easier to serialize or deserialize cmd_i2c_xfer_request::data_buf - * manually rather than using this structure definition. -*/ -struct serial_i2c_request { - /** @brief I2C slave address */ - uint16_t addr; - /** @brief bitmask of SERIALI2C_ flags */ - uint16_t flags; - /** @brief length of I2C transaction in bytes */ - uint16_t len; - /** @brief for write transactions only, #len bytes of data */ - uint8_t data[]; -} __ABI_PACKED; - -/** - * @ingroup I2C - * @brief trigger one or more i2c transactions - */ -struct cmd_i2c_xfer_request { - /** @brief valid bus number from mach-t186/i2c-t186.h*/ - uint32_t bus_id; - - /** @brief count of valid bytes in #data_buf*/ - uint32_t data_size; - - /** @brief serialized packed instances of @ref serial_i2c_request*/ - uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE]; -} __ABI_PACKED; - -/** - * @ingroup I2C - * @brief container for data read from the i2c bus - * - * Processing an cmd_i2c_xfer_request::data_buf causes BPMP to execute - * zero or more I2C reads. The data read from the bus is serialized - * into #data_buf. - */ -struct cmd_i2c_xfer_response { - /** @brief count of valid bytes in #data_buf*/ - uint32_t data_size; - /** @brief i2c read data */ - uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE]; -} __ABI_PACKED; - -/** - * @ingroup I2C - * @brief request with #MRQ_I2C - */ -struct mrq_i2c_request { - /** @brief always CMD_I2C_XFER (i.e. 1) */ - uint32_t cmd; - /** @brief parameters of the transfer request */ - struct cmd_i2c_xfer_request xfer; -} __ABI_PACKED; - -/** - * @ingroup I2C - * @brief response to #MRQ_I2C - */ -struct mrq_i2c_response { - struct cmd_i2c_xfer_response xfer; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_CLK - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_clk_request - * * Response Payload: @ref mrq_clk_response - * @addtogroup Clocks - * @{ - */ - -/** - * @name MRQ_CLK sub-commands - * @{ - */ -enum { - CMD_CLK_GET_RATE = 1, - CMD_CLK_SET_RATE = 2, - CMD_CLK_ROUND_RATE = 3, - CMD_CLK_GET_PARENT = 4, - CMD_CLK_SET_PARENT = 5, - CMD_CLK_IS_ENABLED = 6, - CMD_CLK_ENABLE = 7, - CMD_CLK_DISABLE = 8, - CMD_CLK_GET_ALL_INFO = 14, - CMD_CLK_GET_MAX_CLK_ID = 15, - CMD_CLK_MAX, -}; -/** @} */ - -#define MRQ_CLK_NAME_MAXLEN 40 -#define MRQ_CLK_MAX_PARENTS 16 - -/** @private */ -struct cmd_clk_get_rate_request { - EMPTY -} __ABI_PACKED; - -struct cmd_clk_get_rate_response { - int64_t rate; -} __ABI_PACKED; - -struct cmd_clk_set_rate_request { - int32_t unused; - int64_t rate; -} __ABI_PACKED; - -struct cmd_clk_set_rate_response { - int64_t rate; -} __ABI_PACKED; - -struct cmd_clk_round_rate_request { - int32_t unused; - int64_t rate; -} __ABI_PACKED; - -struct cmd_clk_round_rate_response { - int64_t rate; -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_get_parent_request { - EMPTY -} __ABI_PACKED; - -struct cmd_clk_get_parent_response { - uint32_t parent_id; -} __ABI_PACKED; - -struct cmd_clk_set_parent_request { - uint32_t parent_id; -} __ABI_PACKED; - -struct cmd_clk_set_parent_response { - uint32_t parent_id; -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_is_enabled_request { - EMPTY -} __ABI_PACKED; - -struct cmd_clk_is_enabled_response { - int32_t state; -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_enable_request { - EMPTY -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_enable_response { - EMPTY -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_disable_request { - EMPTY -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_disable_response { - EMPTY -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_get_all_info_request { - EMPTY -} __ABI_PACKED; - -struct cmd_clk_get_all_info_response { - uint32_t flags; - uint32_t parent; - uint32_t parents[MRQ_CLK_MAX_PARENTS]; - uint8_t num_parents; - uint8_t name[MRQ_CLK_NAME_MAXLEN]; -} __ABI_PACKED; - -/** @private */ -struct cmd_clk_get_max_clk_id_request { - EMPTY -} __ABI_PACKED; - -struct cmd_clk_get_max_clk_id_response { - uint32_t max_id; -} __ABI_PACKED; -/** @} */ - -/** - * @ingroup Clocks - * @brief request with #MRQ_CLK - * - * Used by the sender of an #MRQ_CLK message to control clocks. The - * clk_request is split into several sub-commands. Some sub-commands - * require no additional data. Others have a sub-command specific - * payload - * - * |sub-command |payload | - * |----------------------------|-----------------------| - * |CMD_CLK_GET_RATE |- | - * |CMD_CLK_SET_RATE |clk_set_rate | - * |CMD_CLK_ROUND_RATE |clk_round_rate | - * |CMD_CLK_GET_PARENT |- | - * |CMD_CLK_SET_PARENT |clk_set_parent | - * |CMD_CLK_IS_ENABLED |- | - * |CMD_CLK_ENABLE |- | - * |CMD_CLK_DISABLE |- | - * |CMD_CLK_GET_ALL_INFO |- | - * |CMD_CLK_GET_MAX_CLK_ID |- | - * - */ - -struct mrq_clk_request { - /** @brief sub-command and clock id concatenated to 32-bit word. - * - bits[31..24] is the sub-cmd. - * - bits[23..0] is the clock id - */ - uint32_t cmd_and_id; - - union { - /** @private */ - struct cmd_clk_get_rate_request clk_get_rate; - struct cmd_clk_set_rate_request clk_set_rate; - struct cmd_clk_round_rate_request clk_round_rate; - /** @private */ - struct cmd_clk_get_parent_request clk_get_parent; - struct cmd_clk_set_parent_request clk_set_parent; - /** @private */ - struct cmd_clk_enable_request clk_enable; - /** @private */ - struct cmd_clk_disable_request clk_disable; - /** @private */ - struct cmd_clk_is_enabled_request clk_is_enabled; - /** @private */ - struct cmd_clk_get_all_info_request clk_get_all_info; - /** @private */ - struct cmd_clk_get_max_clk_id_request clk_get_max_clk_id; - } __UNION_ANON; -} __ABI_PACKED; - -/** - * @ingroup Clocks - * @brief response to MRQ_CLK - * - * Each sub-command supported by @ref mrq_clk_request may return - * sub-command-specific data. Some do and some do not as indicated in - * the following table - * - * |sub-command |payload | - * |----------------------------|------------------------| - * |CMD_CLK_GET_RATE |clk_get_rate | - * |CMD_CLK_SET_RATE |clk_set_rate | - * |CMD_CLK_ROUND_RATE |clk_round_rate | - * |CMD_CLK_GET_PARENT |clk_get_parent | - * |CMD_CLK_SET_PARENT |clk_set_parent | - * |CMD_CLK_IS_ENABLED |clk_is_enabled | - * |CMD_CLK_ENABLE |- | - * |CMD_CLK_DISABLE |- | - * |CMD_CLK_GET_ALL_INFO |clk_get_all_info | - * |CMD_CLK_GET_MAX_CLK_ID |clk_get_max_id | - * - */ - -struct mrq_clk_response { - union { - struct cmd_clk_get_rate_response clk_get_rate; - struct cmd_clk_set_rate_response clk_set_rate; - struct cmd_clk_round_rate_response clk_round_rate; - struct cmd_clk_get_parent_response clk_get_parent; - struct cmd_clk_set_parent_response clk_set_parent; - /** @private */ - struct cmd_clk_enable_response clk_enable; - /** @private */ - struct cmd_clk_disable_response clk_disable; - struct cmd_clk_is_enabled_response clk_is_enabled; - struct cmd_clk_get_all_info_response clk_get_all_info; - struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; - } __UNION_ANON; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_QUERY_ABI - * @brief check if an MRQ is implemented - * - * * Platforms: All - * * Initiators: Any - * * Targets: Any - * * Request Payload: @ref mrq_query_abi_request - * * Response Payload: @ref mrq_query_abi_response - */ - -/** - * @ingroup ABI_info - * @brief request with MRQ_QUERY_ABI - * - * Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported - * by the recipient. - */ -struct mrq_query_abi_request { - /** @brief MRQ code to query */ - uint32_t mrq; -} __ABI_PACKED; - -/** - * @ingroup ABI_info - * @brief response to MRQ_QUERY_ABI - */ -struct mrq_query_abi_response { - /** @brief 0 if queried MRQ is supported. Else, -#BPMP_ENODEV */ - int32_t status; -} __ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_PG_READ_STATE - * @brief read the power-gating state of a partition - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_pg_read_state_request - * * Response Payload: @ref mrq_pg_read_state_response - * @addtogroup Powergating - * @{ - */ - -/** - * @brief request with #MRQ_PG_READ_STATE - * - * Used by MRQ_PG_READ_STATE call to read the current state of a - * partition. - */ -struct mrq_pg_read_state_request { - /** @brief ID of partition */ - uint32_t partition_id; -} __ABI_PACKED; - -/** - * @brief response to MRQ_PG_READ_STATE - * @todo define possible errors. - */ -struct mrq_pg_read_state_response { - /** @brief read as don't care */ - uint32_t sram_state; - /** @brief state of power partition - * * 0 : off - * * 1 : on - */ - uint32_t logic_state; -} __ABI_PACKED; - -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_PG_UPDATE_STATE - * @brief modify the power-gating state of a partition - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_pg_update_state_request - * * Response Payload: N/A - * @addtogroup Powergating - * @{ - */ - -/** - * @brief request with mrq_pg_update_state_request - * - * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the - * state of a power partition #partition_id. - */ -struct mrq_pg_update_state_request { - /** @brief ID of partition */ - uint32_t partition_id; - /** @brief secondary control of power partition - * @details Ignored by many versions of the BPMP - * firmware. For maximum compatibility, set the value - * according to @logic_state - * * 0x1: power ON partition (@ref logic_state == 0x3) - * * 0x3: power OFF partition (@ref logic_state == 0x1) - */ - uint32_t sram_state; - /** @brief controls state of power partition, legal values are - * * 0x1 : power OFF partition - * * 0x3 : power ON partition - */ - uint32_t logic_state; - /** @brief change state of clocks of the power partition, legal values - * * 0x0 : do not change clock state - * * 0x1 : disable partition clocks (only applicable when - * @ref logic_state == 0x1) - * * 0x3 : enable partition clocks (only applicable when - * @ref logic_state == 0x3) - */ - uint32_t clock_state; -} __ABI_PACKED; -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_THERMAL - * @brief interact with BPMP thermal framework - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: Any - * * Request Payload: TODO - * * Response Payload: TODO - * - * @addtogroup Thermal - * - * The BPMP firmware includes a thermal framework. Drivers within the - * bpmp firmware register with the framework to provide thermal - * zones. Each thermal zone corresponds to an entity whose temperature - * can be measured. The framework also has a notion of trip points. A - * trip point consists of a thermal zone id, a temperature, and a - * callback routine. The framework invokes the callback when the zone - * hits the indicated temperature. The BPMP firmware uses this thermal - * framework interally to implement various temperature-dependent - * functions. - * - * Software on the CPU can use #MRQ_THERMAL (with payload @ref - * mrq_thermal_host_to_bpmp_request) to interact with the BPMP thermal - * framework. The CPU must It can query the number of supported zones, - * query zone temperatures, and set trip points. - * - * When a trip point set by the CPU gets crossed, BPMP firmware issues - * an IPC to the CPU having mrq_request::mrq = #MRQ_THERMAL and a - * payload of @ref mrq_thermal_bpmp_to_host_request. - * @{ - */ -enum mrq_thermal_host_to_bpmp_cmd { - /** - * @brief Check whether the BPMP driver supports the specified - * request type. - * - * Host needs to supply request parameters. - * - * mrq_response::err is 0 if the specified request is - * supported and -#BPMP_ENODEV otherwise. - */ - CMD_THERMAL_QUERY_ABI = 0, - - /** - * @brief Get the current temperature of the specified zone. - * - * Host needs to supply request parameters. - * - * mrq_response::err is - * * 0: Temperature query succeeded. - * * -#BPMP_EINVAL: Invalid request parameters. - * * -#BPMP_ENOENT: No driver registered for thermal zone.. - * * -#BPMP_EFAULT: Problem reading temperature measurement. - */ - CMD_THERMAL_GET_TEMP = 1, - - /** - * @brief Enable or disable and set the lower and upper - * thermal limits for a thermal trip point. Each zone has - * one trip point. - * - * Host needs to supply request parameters. Once the - * temperature hits a trip point, the BPMP will send a message - * to the CPU having MRQ=MRQ_THERMAL and - * type=CMD_THERMAL_HOST_TRIP_REACHED - * - * mrq_response::err is - * * 0: Trip successfully set. - * * -#BPMP_EINVAL: Invalid request parameters. - * * -#BPMP_ENOENT: No driver registered for thermal zone. - * * -#BPMP_EFAULT: Problem setting trip point. - */ - CMD_THERMAL_SET_TRIP = 2, - - /** - * @brief Get the number of supported thermal zones. - * - * No request parameters required. - * - * mrq_response::err is always 0, indicating success. - */ - CMD_THERMAL_GET_NUM_ZONES = 3, - - /** @brief: number of supported host-to-bpmp commands. May - * increase in future - */ - CMD_THERMAL_HOST_TO_BPMP_NUM -}; - -enum mrq_thermal_bpmp_to_host_cmd { - /** - * @brief Indication that the temperature for a zone has - * exceeded the range indicated in the thermal trip point - * for the zone. - * - * BPMP needs to supply request parameters. Host only needs to - * acknowledge. - */ - CMD_THERMAL_HOST_TRIP_REACHED = 100, - - /** @brief: number of supported bpmp-to-host commands. May - * increase in future - */ - CMD_THERMAL_BPMP_TO_HOST_NUM -}; - -/* - * Host->BPMP request data for request type CMD_THERMAL_QUERY_ABI - * - * zone: Request type for which to check existence. - */ -struct cmd_thermal_query_abi_request { - uint32_t type; -} __ABI_PACKED; - -/* - * Host->BPMP request data for request type CMD_THERMAL_GET_TEMP - * - * zone: Number of thermal zone. - */ -struct cmd_thermal_get_temp_request { - uint32_t zone; -} __ABI_PACKED; - -/* - * BPMP->Host reply data for request CMD_THERMAL_GET_TEMP - * - * error: 0 if request succeeded. - * -BPMP_EINVAL if request parameters were invalid. - * -BPMP_ENOENT if no driver was registered for the specified thermal zone. - * -BPMP_EFAULT for other thermal zone driver errors. - * temp: Current temperature in millicelsius. - */ -struct cmd_thermal_get_temp_response { - int32_t temp; -} __ABI_PACKED; - -/* - * Host->BPMP request data for request type CMD_THERMAL_SET_TRIP - * - * zone: Number of thermal zone. - * low: Temperature of lower trip point in millicelsius - * high: Temperature of upper trip point in millicelsius - * enabled: 1 to enable trip point, 0 to disable trip point - */ -struct cmd_thermal_set_trip_request { - uint32_t zone; - int32_t low; - int32_t high; - uint32_t enabled; -} __ABI_PACKED; - -/* - * BPMP->Host request data for request type CMD_THERMAL_HOST_TRIP_REACHED - * - * zone: Number of thermal zone where trip point was reached. - */ -struct cmd_thermal_host_trip_reached_request { - uint32_t zone; -} __ABI_PACKED; - -/* - * BPMP->Host reply data for request type CMD_THERMAL_GET_NUM_ZONES - * - * num: Number of supported thermal zones. The thermal zones are indexed - * starting from zero. - */ -struct cmd_thermal_get_num_zones_response { - uint32_t num; -} __ABI_PACKED; - -/* - * Host->BPMP request data. - * - * Reply type is union mrq_thermal_bpmp_to_host_response. - * - * type: Type of request. Values listed in enum mrq_thermal_type. - * data: Request type specific parameters. - */ -struct mrq_thermal_host_to_bpmp_request { - uint32_t type; - union { - struct cmd_thermal_query_abi_request query_abi; - struct cmd_thermal_get_temp_request get_temp; - struct cmd_thermal_set_trip_request set_trip; - } __UNION_ANON; -} __ABI_PACKED; - -/* - * BPMP->Host request data. - * - * type: Type of request. Values listed in enum mrq_thermal_type. - * data: Request type specific parameters. - */ -struct mrq_thermal_bpmp_to_host_request { - uint32_t type; - union { - struct cmd_thermal_host_trip_reached_request host_trip_reached; - } __UNION_ANON; -} __ABI_PACKED; - -/* - * Data in reply to a Host->BPMP request. - */ -union mrq_thermal_bpmp_to_host_response { - struct cmd_thermal_get_temp_response get_temp; - struct cmd_thermal_get_num_zones_response get_num_zones; -} __ABI_PACKED; -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_CPU_VHINT - * @brief Query CPU voltage hint data - * - * * Platforms: T186 - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_cpu_vhint_request - * * Response Payload: N/A - * - * @addtogroup Vhint CPU Voltage hint - * @{ - */ - -/** - * @brief request with #MRQ_CPU_VHINT - * - * Used by #MRQ_CPU_VHINT call by CCPLEX to retrieve voltage hint data - * from BPMP to memory space pointed by #addr. CCPLEX is responsible - * to allocate sizeof(cpu_vhint_data) sized block of memory and - * appropriately map it for BPMP before sending the request. - */ -struct mrq_cpu_vhint_request { - /** @brief IOVA address for the #cpu_vhint_data */ - uint32_t addr; /* struct cpu_vhint_data * */ - /** @brief ID of the cluster whose data is requested */ - uint32_t cluster_id; /* enum cluster_id */ -} __ABI_PACKED; - -/** - * @brief description of the CPU v/f relation - * - * Used by #MRQ_CPU_VHINT call to carry data pointed by #addr of - * struct mrq_cpu_vhint_request - */ -struct cpu_vhint_data { - uint32_t ref_clk_hz; /**< reference frequency in Hz */ - uint16_t pdiv; /**< post divider value */ - uint16_t mdiv; /**< input divider value */ - uint16_t ndiv_max; /**< fMAX expressed with max NDIV value */ - /** table of ndiv values as a function of vINDEX (voltage index) */ - uint16_t ndiv[80]; - /** minimum allowed NDIV value */ - uint16_t ndiv_min; - /** minimum allowed voltage hint value (as in vINDEX) */ - uint16_t vfloor; - /** maximum allowed voltage hint value (as in vINDEX) */ - uint16_t vceil; - /** post-multiplier for vindex value */ - uint16_t vindex_mult; - /** post-divider for vindex value */ - uint16_t vindex_div; - /** reserved for future use */ - uint16_t reserved[328]; -} __ABI_PACKED; - -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_ABI_RATCHET - * @brief ABI ratchet value query - * - * * Platforms: T186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_abi_ratchet_request - * * Response Payload: @ref mrq_abi_ratchet_response - * @addtogroup ABI_info - * @{ - */ - -/** - * @brief an ABI compatibility mechanism - * - * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future - * revision of this header file. - * 1. That future revision deprecates some MRQ - * 2. That future revision introduces a breaking change to an existing - * MRQ or - * 3. A bug is discovered in an existing implementation of the BPMP-FW - * (or possibly one of its clients) which warrants deprecating that - * implementation. - */ -#define BPMP_ABI_RATCHET_VALUE 3 - -/** - * @brief request with #MRQ_ABI_RATCHET. - * - * #ratchet should be #BPMP_ABI_RATCHET_VALUE from the ABI header - * against which the requester was compiled. - * - * If ratchet is less than BPMP's #BPMP_ABI_RATCHET_VALUE, BPMP may - * reply with mrq_response::err = -#BPMP_ERANGE to indicate that - * BPMP-FW cannot interoperate correctly with the requester. Requester - * should cease further communication with BPMP. - * - * Otherwise, err shall be 0. - */ -struct mrq_abi_ratchet_request { - /** @brief requester's ratchet value */ - uint16_t ratchet; -}; - -/** - * @brief response to #MRQ_ABI_RATCHET - * - * #ratchet shall be #BPMP_ABI_RATCHET_VALUE from the ABI header - * against which BPMP firwmare was compiled. - * - * If #ratchet is less than the requester's #BPMP_ABI_RATCHET_VALUE, - * the requster must either interoperate with BPMP according to an ABI - * header version with BPMP_ABI_RATCHET_VALUE = ratchet or cease - * communication with BPMP. - * - * If mrq_response::err is 0 and ratchet is greater than or equal to the - * requester's BPMP_ABI_RATCHET_VALUE, the requester should continue - * normal operation. - */ -struct mrq_abi_ratchet_response { - /** @brief BPMP's ratchet value */ - uint16_t ratchet; -}; -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_EMC_DVFS_LATENCY - * @brief query frequency dependent EMC DVFS latency - * - * * Platforms: T186 - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: N/A - * * Response Payload: @ref mrq_emc_dvfs_latency_response - * @addtogroup EMC - * @{ - */ - -/** - * @brief used by @ref mrq_emc_dvfs_latency_response - */ -struct emc_dvfs_latency { - /** @brief EMC frequency in kHz */ - uint32_t freq; - /** @brief EMC DVFS latency in nanoseconds */ - uint32_t latency; -} __ABI_PACKED; - -#define EMC_DVFS_LATENCY_MAX_SIZE 14 -/** - * @brief response to #MRQ_EMC_DVFS_LATENCY - */ -struct mrq_emc_dvfs_latency_response { - /** @brief the number valid entries in #pairs */ - uint32_t num_pairs; - /** @brief EMC <frequency, latency> information */ - struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; -} __ABI_PACKED; - -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_TRACE_ITER - * @brief manage the trace iterator - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: N/A - * * Response Payload: @ref mrq_trace_iter_request - * @addtogroup Trace - * @{ - */ -enum { - /** @brief (re)start the tracing now. Ignore older events */ - TRACE_ITER_INIT = 0, - /** @brief clobber all events in the trace buffer */ - TRACE_ITER_CLEAN = 1 -}; - -/** - * @brief request with #MRQ_TRACE_ITER - */ -struct mrq_trace_iter_request { - /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ - uint32_t cmd; -} __ABI_PACKED; - -/** @} */ - -/* - * 4. Enumerations - */ - -/* - * 4.1 CPU enumerations - * - * See <mach-t186/system-t186.h> - * - * 4.2 CPU Cluster enumerations - * - * See <mach-t186/system-t186.h> - * - * 4.3 System low power state enumerations - * - * See <mach-t186/system-t186.h> - */ - -/* - * 4.4 Clock enumerations - * - * For clock enumerations, see <mach-t186/clk-t186.h> - */ - -/* - * 4.5 Reset enumerations - * - * For reset enumerations, see <mach-t186/reset-t186.h> - */ - -/* - * 4.6 Thermal sensor enumerations - * - * For thermal sensor enumerations, see <mach-t186/thermal-t186.h> - */ - -/** - * @defgroup Error_Codes - * Negative values for mrq_response::err generally indicate some - * error. The ABI defines the following error codes. Negating these - * defines is an exercise left to the user. - * @{ - */ -/** @brief No such file or directory */ -#define BPMP_ENOENT 2 -/** @brief No MRQ handler */ -#define BPMP_ENOHANDLER 3 -/** @brief I/O error */ -#define BPMP_EIO 5 -/** @brief Bad sub-MRQ command */ -#define BPMP_EBADCMD 6 -/** @brief Not enough memory */ -#define BPMP_ENOMEM 12 -/** @brief Permission denied */ -#define BPMP_EACCES 13 -/** @brief Bad address */ -#define BPMP_EFAULT 14 -/** @brief No such device */ -#define BPMP_ENODEV 19 -/** @brief Argument is a directory */ -#define BPMP_EISDIR 21 -/** @brief Invalid argument */ -#define BPMP_EINVAL 22 -/** @brief Timeout during operation */ -#define BPMP_ETIMEDOUT 23 -/** @brief Out of range */ -#define BPMP_ERANGE 34 -/** @} */ -/** @} */ -#endif diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h deleted file mode 100644 index 021c246..0000000 --- a/arch/arm/include/asm/arch-tegra/cboot.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 NVIDIA Corporation. All rights reserved. - */ - -#ifndef _TEGRA_CBOOT_H_ -#define _TEGRA_CBOOT_H_ - -#ifdef CONFIG_ARM64 -extern unsigned long cboot_boot_x0; - -void cboot_save_boot_params(unsigned long x0, unsigned long x1, - unsigned long x2, unsigned long x3); -int cboot_dram_init(void); -int cboot_dram_init_banksize(void); -ulong cboot_get_usable_ram_top(ulong total_size); -int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]); -#else -static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, - unsigned long x2, unsigned long x3) -{ -} - -static inline int cboot_dram_init(void) -{ - return -ENOSYS; -} - -static inline int cboot_dram_init_banksize(void) -{ - return -ENOSYS; -} - -static inline ulong cboot_get_usable_ram_top(ulong total_size) -{ - return 0; -} - -static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) -{ - return -ENOSYS; -} -#endif - -#endif diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h deleted file mode 100644 index 2359e14..0000000 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ /dev/null @@ -1,451 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA_CLK_RST_H_ -#define _TEGRA_CLK_RST_H_ - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll { - uint pll_base; /* the control register */ - /* pll_out[0] is output A control, pll_out[1] is output B control */ - uint pll_out[2]; - uint pll_misc; /* other misc things */ -}; - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll_simple { - uint pll_base; /* the control register */ - uint pll_misc; /* other misc things */ -}; - -struct clk_pllm { - uint pllm_base; /* the control register */ - uint pllm_out; /* output control */ - uint pllm_misc1; /* misc1 */ - uint pllm_misc2; /* misc2 */ -}; - -/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ -struct clk_set_clr { - uint set; - uint clr; -}; - -/* - * Most PLLs use the clk_pll structure, but some have a simpler two-member - * structure for which we use clk_pll_simple. The reason for this non- - * othogonal setup is not stated. - */ -enum { - TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ - TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ - TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ - TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ - TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ - TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ - TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */ -}; - -/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct clk_rst_ctlr { - uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ - uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ - uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ - uint crc_reserved0; /* reserved_0, 0x1C */ - uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ - uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ - uint crc_reserved1; /* reserved_1, 0x3C */ - uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ - - struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ - - /* PLLs from 0xe0 to 0xf4 */ - struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; - - uint crc_reserved10; /* _reserved_10, 0xF8 */ - uint crc_reserved11; /* _reserved_11, 0xFC */ - - uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - - uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */ - - uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - - uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - - uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ - uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ - uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ - - uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ - uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ - uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ - - uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */ - - uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - - uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ - - /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ - struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; - - uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */ - - /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ - struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS]; - - uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */ - - uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ - - /* Additional (T30) registers */ - uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - - uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */ - - uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */ - uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */ - uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ - uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ - uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ - /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ - struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; - /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ - struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; - /* Additional (T114+) registers */ - uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ - uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ - uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ - uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */ - uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ - uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - uint crc_reserved40[1]; /* _reserved_40, 0x474 */ - uint crc_intstatus; /* __INTSTATUS_0, 0x478 */ - uint crc_intmask; /* __INTMASK_0, 0x47C */ - uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - - uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */ - uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - - uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ - uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ - uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ - uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ - uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ - uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ - uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ - - uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ - uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ - uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ - uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ - uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ - uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ - uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ - uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ - uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ - uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ - uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ - uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ - uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ - uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ - uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ - uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ - uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ - uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ - uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ - uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ - uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ - uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - uint crc_reserved51[1]; /* _reserved_51, 0x538 */ - uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ - uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ - uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ - uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ - uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - uint crc_reserved52[1]; /* _reserved_52, 0x554 */ - uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ - u32 _rsv32[4]; /* 0x560-0x56c */ - u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ - u32 _rsv32_1[7]; /* 0x574-58c */ - struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */ - u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ - - /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */ - uint _rsrv32_2[25]; /* _0x59C - 0x5FC */ - uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */ - - /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */ - uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */ - /* - * NOTE: PLLA1 regs are in the middle of this Y region. Break this in - * two later if PLLA1 is needed, but for now this is cleaner. - */ - uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */ -}; - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ -#define CPU3_CLK_STP_SHIFT 11 -#define CPU2_CLK_STP_SHIFT 10 -#define CPU1_CLK_STP_SHIFT 9 -#define CPU0_CLK_STP_SHIFT 8 -#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_BASE_0 */ -#define PLL_BYPASS_SHIFT 31 -#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) - -#define PLL_ENABLE_SHIFT 30 -#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) - -#define PLL_BASE_OVRRIDE_MASK (1U << 28) - -#define PLL_LOCK_SHIFT 27 -#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ -#define PLL_OUT_RSTN (1 << 0) -#define PLL_OUT_CLKEN (1 << 1) -#define PLL_OUT_OVRRIDE (1 << 2) - -#define PLL_OUT_RATIO_SHIFT 8 -#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_MISC_0 */ -#define PLL_DCCON_SHIFT 20 -#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) - -#define PLLP_OUT1_OVR (1 << 2) -#define PLLP_OUT2_OVR (1 << 18) -#define PLLP_OUT3_OVR (1 << 2) -#define PLLP_OUT4_OVR (1 << 18) -#define PLLP_OUT1_RATIO 8 -#define PLLP_OUT2_RATIO 24 -#define PLLP_OUT3_RATIO 8 -#define PLLP_OUT4_RATIO 24 - -enum { - IN_408_OUT_204_DIVISOR = 2, - IN_408_OUT_102_DIVISOR = 6, - IN_408_OUT_48_DIVISOR = 15, - IN_408_OUT_9_6_DIVISOR = 83, -}; - -#define PLLP_OUT1_RSTN_DIS (1 << 0) -#define PLLP_OUT1_RSTN_EN (0 << 0) -#define PLLP_OUT1_CLKEN (1 << 1) -#define PLLP_OUT2_RSTN_DIS (1 << 16) -#define PLLP_OUT2_RSTN_EN (0 << 16) -#define PLLP_OUT2_CLKEN (1 << 17) - -#define PLLP_OUT3_RSTN_DIS (1 << 0) -#define PLLP_OUT3_RSTN_EN (0 << 0) -#define PLLP_OUT3_CLKEN (1 << 1) -#define PLLP_OUT4_RSTN_DIS (1 << 16) -#define PLLP_OUT4_RSTN_EN (0 << 16) -#define PLLP_OUT4_CLKEN (1 << 17) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ -#define PLLU_POWERDOWN (1 << 16) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLL_ACTIVE_POWERDOWN (1 << 12) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ -#define OSC_XOE_SHIFT 0 -#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) -#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) -#define OSC_XOBP_SHIFT 1 -#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) -#define OSC_XOFS_SHIFT 4 -#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) -#define OSC_DRIVE_STRENGTH 7 - -/* - * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits - * but can be 16. We could use knowledge we have to restrict the mask in - * the 8-bit cases (the divider_bits value returned by - * get_periph_clock_source()) but it does not seem worth it since the code - * already checks the ranges of values it is writing, in clk_get_divider(). - */ -#define OUT_CLK_DIVISOR_SHIFT 0 -#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) - -#define OUT_CLK_SOURCE_31_30_SHIFT 30 -#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT) - -#define OUT_CLK_SOURCE_31_29_SHIFT 29 -#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT) - -/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ -#define OUT_CLK_SOURCE_31_28_SHIFT 28 -#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT) - -/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ -#define SCLK_SYS_STATE_SHIFT 28U -#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) -enum { - SCLK_SYS_STATE_STDBY, - SCLK_SYS_STATE_IDLE, - SCLK_SYS_STATE_RUN, - SCLK_SYS_STATE_IRQ = 4U, - SCLK_SYS_STATE_FIQ = 8U, -}; -#define SCLK_COP_FIQ_MASK (1 << 27) -#define SCLK_CPU_FIQ_MASK (1 << 26) -#define SCLK_COP_IRQ_MASK (1 << 25) -#define SCLK_CPU_IRQ_MASK (1 << 24) - -#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12 -#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8 -#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4 -#define SCLK_SWAKEUP_RUN_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0 - -#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -enum { - SCLK_SOURCE_CLKM, - SCLK_SOURCE_PLLC_OUT1, - SCLK_SOURCE_PLLP_OUT4, - SCLK_SOURCE_PLLP_OUT3, - SCLK_SOURCE_PLLP_OUT2, - SCLK_SOURCE_CLKD, - SCLK_SOURCE_CLKS, - SCLK_SOURCE_PLLM_OUT1, -}; -#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) -#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) -#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) -#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) - -/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */ -#define SUPER_SCLK_ENB_SHIFT 31U -#define SUPER_SCLK_ENB_MASK (1U << 31) -#define SUPER_SCLK_DIVIDEND_SHIFT 8 -#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT) -#define SUPER_SCLK_DIVISOR_SHIFT 0 -#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) - -/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ -#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 -#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) -#define CLK_SYS_RATE_AHB_RATE_SHIFT 4 -#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) -#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3 -#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) -#define CLK_SYS_RATE_APB_RATE_SHIFT 0 -#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) - -/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_L2RESET (1 << 24) -#define CLR_NONCPURESET (1 << 29) -#define CLR_PRESETDBG (1 << 30) - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ -#define CLR_CPU0_CLK_STP (1 << 8) -#define CLR_CPU1_CLK_STP (1 << 9) -#define CLR_CPU2_CLK_STP (1 << 10) -#define CLR_CPU3_CLK_STP (1 << 11) - -/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ -#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) - -/* CRC_CLK_ENB_V_SET_0 0x440 */ -#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) -#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) -#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ -#define PLL_ACTIVE_POWERDOWN (1 << 12) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLLU_POWERDOWN (1 << 16) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) - -/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ -#define PLLX_IDDQ_SHIFT 3 -#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) - -/* CLK_RST_PLLDP_SS_CFG */ -#define PLLDP_SS_CFG_CLAMP (1 << 22) -#define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24) -#define PLLDP_SS_CFG_DITHER (1 << 28) - -/* CLK_RST_PLLD_MISC */ -#define PLLD_CLKENABLE 30 - -#endif /* _TEGRA_CLK_RST_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h deleted file mode 100644 index 8aa90d5..0000000 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ /dev/null @@ -1,421 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -/* Tegra clock control functions */ - -#ifndef _TEGRA_CLOCK_H_ -#define _TEGRA_CLOCK_H_ - -/* Set of oscillator frequencies supported in the internal API. */ -enum clock_osc_freq { - /* All in MHz, so 13_0 is 13.0MHz */ - CLOCK_OSC_FREQ_13_0, - CLOCK_OSC_FREQ_19_2, - CLOCK_OSC_FREQ_12_0, - CLOCK_OSC_FREQ_26_0, - CLOCK_OSC_FREQ_38_4, - CLOCK_OSC_FREQ_48_0, - - CLOCK_OSC_FREQ_COUNT, -}; - -/* - * Note that no Tegra clock register actually uses all of bits 31:28 as - * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in - * those cases, nothing is stored in the bits about the mux field, so it's - * safe to pretend that the mux field extends all the way to the end of the - * register. As such, the U-Boot clock driver is currently a bit lazy, and - * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps - * them all together and pretends they're all 31:28. - */ -enum { - MASK_BITS_31_30, - MASK_BITS_31_29, - MASK_BITS_31_28, -}; - -#include <asm/arch/clock-tables.h> -/* PLL stabilization delay in usec */ -#define CLOCK_PLL_STABLE_DELAY_US 300 - -/* return the current oscillator clock frequency */ -enum clock_osc_freq clock_get_osc_freq(void); - -/* return the clk_m frequency */ -unsigned int clk_m_get_rate(unsigned int parent_rate); - -/** - * Start PLL using the provided configuration parameters. - * - * @param id clock id - * @param divm input divider - * @param divn feedback divider - * @param divp post divider 2^n - * @param cpcon charge pump setup control - * @param lfcon loop filter setup control - * - * @returns monotonic time in us that the PLL will be stable - */ -unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, - u32 divp, u32 cpcon, u32 lfcon); - -/** - * Set PLL output frequency - * - * @param clkid clock id - * @param pllout pll output id - * @param rate desired output rate - * - * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) - */ -int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, - unsigned rate); - -/** - * Read low-level parameters of a PLL. - * - * @param id clock id to read (note: USB is not supported) - * @param divm returns input divider - * @param divn returns feedback divider - * @param divp returns post divider 2^n - * @param cpcon returns charge pump setup control - * @param lfcon returns loop filter setup control - * - * @returns 0 if ok, -1 on error (invalid clock id) - */ -int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, - u32 *divp, u32 *cpcon, u32 *lfcon); - -/* - * Enable a clock - * - * @param id clock id - */ -void clock_enable(enum periph_id clkid); - -/* - * Disable a clock - * - * @param id clock id - */ -void clock_disable(enum periph_id clkid); - -/* - * Set whether a clock is enabled or disabled. - * - * @param id clock id - * @param enable 1 to enable, 0 to disable - */ -void clock_set_enable(enum periph_id clkid, int enable); - -/** - * Reset a peripheral. This puts it in reset, waits for a delay, then takes - * it out of reset and waits for th delay again. - * - * @param periph_id peripheral to reset - * @param us_delay time to delay in microseconds - */ -void reset_periph(enum periph_id periph_id, int us_delay); - -/** - * Put a peripheral into or out of reset. - * - * @param periph_id peripheral to reset - * @param enable 1 to put into reset, 0 to take out of reset - */ -void reset_set_enable(enum periph_id periph_id, int enable); - - -/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ -enum crc_reset_id { - /* Things we can hold in reset for each CPU */ - crc_rst_cpu = 1, - crc_rst_de = 1 << 4, /* What is de? */ - crc_rst_watchdog = 1 << 8, - crc_rst_debug = 1 << 12, -}; - -/** - * Put parts of the CPU complex into or out of reset.\ - * - * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) - * @param which which parts of the complex to affect (OR of crc_reset_id) - * @param reset 1 to assert reset, 0 to de-assert - */ -void reset_cmplx_set_enable(int cpu, int which, int reset); - -/** - * Set the source for a peripheral clock. This plus the divisor sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - */ -void clock_ll_set_source(enum periph_id periph_id, unsigned source); - -/** - * This function is similar to clock_ll_set_source() except that it can be - * used for clocks with more than 2 mux bits. - * - * @param periph_id peripheral to adjust - * @param mux_bits number of mux bits for the clock - * @param source source clock (0-15 depending on mux_bits) - */ -int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, - unsigned source); - -/** - * Set the source and divisor for a peripheral clock. This sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - * @param divisor divisor value to use - */ -void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, - unsigned divisor); - -/** - * Returns the current parent clock ID of a given peripheral. This can be - * useful in order to call clock_*_periph_*() from generic code that has no - * specific knowledge of system-level clock tree structure. - * - * @param periph_id peripheral to query - * @return clock ID of the peripheral's current parent clock - */ -enum clock_id clock_get_periph_parent(enum periph_id periph_id); - -/** - * Start a peripheral PLL clock at the given rate. This also resets the - * peripheral. - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_start_periph_pll(enum periph_id periph_id, - enum clock_id parent, unsigned rate); - -/** - * Returns the rate of a peripheral clock in Hz. Since the caller almost - * certainly knows the parent clock (having just set it) we require that - * this be passed in so we don't need to work it out. - * - * @param periph_id peripheral to start - * @param parent PLL id of parent clock (used to calculate rate, you - * must know this!) - * @return clock rate of peripheral in Hz - */ -unsigned long clock_get_periph_rate(enum periph_id periph_id, - enum clock_id parent); - -/** - * Adjust peripheral PLL clock to the given rate. This does not reset the - * peripheral. If a second stage divisor is not available, pass NULL for - * extra_div. If it is available, then this parameter will return the - * divisor selected (which will be a power of 2 from 1 to 256). - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @param extra_div value for the second-stage divisor (NULL if one is - not available) - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, - enum clock_id parent, unsigned rate, int *extra_div); - -/** - * Returns the clock rate of a specified clock, in Hz. - * - * @param parent PLL id of clock to check - * @return rate of clock in Hz - */ -unsigned clock_get_rate(enum clock_id clkid); - -/** - * Start up a UART using low-level calls - * - * Prior to relocation clock_start_periph_pll() cannot be called. This - * function provides a way to set up a UART using low-level calls which - * do not require BSS. - * - * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) - */ -void clock_ll_start_uart(enum periph_id periph_id); - -/** - * Decode a peripheral ID from a device tree node. - * - * This works by looking up the peripheral's 'clocks' node and reading out - * the second cell, which is the clock number / peripheral ID. - * - * @param blob FDT blob to use - * @param node Node to look at - * @return peripheral ID, or PERIPH_ID_NONE if none - */ -int clock_decode_periph_id(struct udevice *dev); - -/** - * Checks if the oscillator bypass is enabled (XOBP bit) - * - * @return 1 if bypass is enabled, 0 if not - */ -int clock_get_osc_bypass(void); - -/* - * Checks that clocks are valid and prints a warning if not - * - * @return 0 if ok, -1 on error - */ -int clock_verify(void); - -/* Initialize the clocks */ -void clock_init(void); - -/* Initialize the PLLs */ -void clock_early_init(void); - -/* @return true if hardware indicates that clock_early_init() was called */ -bool clock_early_init_done(void); - -/* Returns a pointer to the clock source register for a peripheral */ -u32 *get_periph_source_reg(enum periph_id periph_id); - -/* Returns a pointer to the given 'simple' PLL */ -struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); - -/* - * Given a peripheral ID, determine where the mux bits are in the peripheral - * clock's register, the number of divider bits the clock has, and the SoC- - * specific clock type. - * - * This is an internal API between the core Tegra clock code and the SoC- - * specific clock code. - * - * @param periph_id peripheral to query - * @param mux_bits Set to number of bits in mux register - * @param divider_bits Set to the relevant MASK_BITS_* value - * @param type Set to the SoC-specific clock type - * @return 0 on success, -1 on error - */ -int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, - int *divider_bits, int *type); - -/* - * Given a peripheral ID and clock source mux value, determine the clock_id - * of that peripheral's parent. - * - * This is an internal API between the core Tegra clock code and the SoC- - * specific clock code. - * - * @param periph_id peripheral to query - * @param source raw clock source mux value - * @return the CLOCK_ID_* value @source represents - */ -enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); - -/** - * Given a peripheral ID and the required source clock, this returns which - * value should be programmed into the source mux for that peripheral. - * - * There is special code here to handle the one source type with 5 sources. - * - * @param periph_id peripheral to start - * @param source PLL id of required parent clock - * @param mux_bits Set to number of bits in mux register: 2 or 4 - * @param divider_bits Set to number of divider bits (8 or 16) - * @return mux value (0-4, or -1 if not found) - */ -int get_periph_clock_source(enum periph_id periph_id, - enum clock_id parent, int *mux_bits, int *divider_bits); - -/* - * Convert a device tree clock ID to our peripheral ID. They are mostly - * the same but we are very cautious so we check that a valid clock ID is - * provided. - * - * @param clk_id Clock ID according to tegra30 device tree binding - * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid - */ -enum periph_id clk_id_to_periph_id(int clk_id); - -/** - * Set the output frequency you want for each PLL clock. - * PLL output frequencies are programmed by setting their N, M and P values. - * The governing equations are: - * VCO = (Fi / m) * n, Fo = VCO / (2^p) - * where Fo is the output frequency from the PLL. - * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) - * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 - * Please see Tegra TRM section 5.3 to get the detail for PLL Programming - * - * @param n PLL feedback divider(DIVN) - * @param m PLL input divider(DIVN) - * @param p post divider(DIVP) - * @param cpcon base PLL charge pump(CPCON) - * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot - * be overridden), 1 if PLL is already correct - */ -int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); - -/* return 1 if a peripheral ID is in range */ -#define clock_type_id_isvalid(id) ((id) >= 0 && \ - (id) < CLOCK_TYPE_COUNT) - -/* return 1 if a periphc_internal_id is in range */ -#define periphc_internal_id_isvalid(id) ((id) >= 0 && \ - (id) < PERIPHC_COUNT) - -/* SoC-specific TSC init */ -void arch_timer_init(void); - -void tegra30_set_up_pllp(void); - -/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */ -#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3) - -struct clk_pll_info { - u32 m_shift:5; /* DIVM_SHIFT */ - u32 n_shift:5; /* DIVN_SHIFT */ - u32 p_shift:5; /* DIVP_SHIFT */ - u32 kcp_shift:5; /* KCP/cpcon SHIFT */ - u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ - u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ - u32 rsvd:1; - u32 m_mask:10; /* DIVM_MASK */ - u32 n_mask:12; /* DIVN_MASK */ - u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ - u32 kcp_mask:10; /* KCP/CPCON MASK */ - u32 kvco_mask:10; /* KVCO/LFCON MASK */ - u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ - u32 rsvd2:6; -}; -extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; - -struct periph_clk_init { - enum periph_id periph_id; - enum clock_id parent_clock_id; -}; -extern struct periph_clk_init periph_clk_init_table[]; - -/** - * Enable output clock for external peripherals - * - * @param clk_id Clock ID to output (1, 2 or 3) - * @return 0 if OK. -ve on error - */ -int clock_external_output(int clk_id); - -#endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h deleted file mode 100644 index 59347dd..0000000 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ /dev/null @@ -1,568 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DC_H -#define __ASM_ARCH_TEGRA_DC_H - -/* Register definitions for the Tegra display controller */ - -/* CMD register 0x000 ~ 0x43 */ -struct dc_cmd_reg { - /* Address 0x000 ~ 0x002 */ - uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ - uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ - uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ - - uint reserved0[5]; /* reserved_0[5] */ - - /* Address 0x008 ~ 0x00a */ - uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ - uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ - uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ - - uint reserved1[5]; /* reserved_1[5] */ - - /* Address 0x010 ~ 0x012 */ - uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ - uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ - uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ - - uint reserved2[5]; /* reserved_2[5] */ - - /* Address 0x018 ~ 0x01a */ - uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ - uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ - uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ - - uint reserved3[13]; /* reserved_3[13] */ - - /* Address 0x028 */ - uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ - - uint reserved4[7]; /* reserved_4[7] */ - - /* Address 0x030 ~ 0x033 */ - uint ctxsw; /* _CMD_CTXSW_0 */ - uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ - uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ - uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */ - - uint reserved5[2]; /* reserved_0[2] */ - - /* Address 0x036 ~ 0x03e */ - uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ - uint int_stat; /* _CMD_INT_STATUS_0 */ - uint int_mask; /* _CMD_INT_MASK_0 */ - uint int_enb; /* _CMD_INT_ENABLE_0 */ - uint int_type; /* _CMD_INT_TYPE_0 */ - uint int_polarity; /* _CMD_INT_POLARITY_0 */ - uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ - uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ - uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ - - uint reserved6; /* reserved_6 */ - - /* Address 0x040 ~ 0x043 */ - uint state_access; /* _CMD_STATE_ACCESS_0 */ - uint state_ctrl; /* _CMD_STATE_CONTROL_0 */ - uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ - uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ -}; - -enum { - PIN_REG_COUNT = 4, - PIN_OUTPUT_SEL_COUNT = 7, -}; - -/* COM register 0x300 ~ 0x329 */ -struct dc_com_reg { - /* Address 0x300 ~ 0x301 */ - uint crc_ctrl; /* _COM_CRC_CONTROL_0 */ - uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */ - - /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ - uint pin_output_enb[PIN_REG_COUNT]; - - /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ - uint pin_output_polarity[PIN_REG_COUNT]; - - /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ - uint pin_output_data[PIN_REG_COUNT]; - - /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ - uint pin_input_enb[PIN_REG_COUNT]; - - /* Address 0x312 ~ 0x313 */ - uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ - uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ - - /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ - uint pin_output_sel[PIN_OUTPUT_SEL_COUNT]; - - /* Address 0x31b ~ 0x329 */ - uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ - uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */ - uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ - uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */ - uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ - uint spi_ctrl; /* _COM_SPI_CONTROL_0 */ - uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */ - uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ - uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ - uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ - uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ - uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ - uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */ - uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ - uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ -}; - -enum dc_disp_h_pulse_pos { - H_PULSE0_POSITION_A, - H_PULSE0_POSITION_B, - H_PULSE0_POSITION_C, - H_PULSE0_POSITION_D, - H_PULSE0_POSITION_COUNT, -}; - -struct _disp_h_pulse { - /* _DISP_H_PULSE0/1/2_CONTROL_0 */ - uint h_pulse_ctrl; - /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ - uint h_pulse_pos[H_PULSE0_POSITION_COUNT]; -}; - -enum dc_disp_v_pulse_pos { - V_PULSE0_POSITION_A, - V_PULSE0_POSITION_B, - V_PULSE0_POSITION_C, - V_PULSE0_POSITION_COUNT, -}; - -struct _disp_v_pulse0 { - /* _DISP_H_PULSE0/1_CONTROL_0 */ - uint v_pulse_ctrl; - /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ - uint v_pulse_pos[V_PULSE0_POSITION_COUNT]; -}; - -struct _disp_v_pulse2 { - /* _DISP_H_PULSE2/3_CONTROL_0 */ - uint v_pulse_ctrl; - /* _DISP_H_PULSE2/3_POSITION_A_0 */ - uint v_pulse_pos_a; -}; - -enum dc_disp_h_pulse_reg { - H_PULSE0, - H_PULSE1, - H_PULSE2, - H_PULSE_COUNT, -}; - -enum dc_disp_pp_select { - PP_SELECT_A, - PP_SELECT_B, - PP_SELECT_C, - PP_SELECT_D, - PP_SELECT_COUNT, -}; - -/* DISP register 0x400 ~ 0x4c1 */ -struct dc_disp_reg { - /* Address 0x400 ~ 0x40a */ - uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ - uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */ - uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ - uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */ - uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */ - uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ - uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ - uint sync_width; /* _DISP_SYNC_WIDTH_0 */ - uint back_porch; /* _DISP_BACK_PORCH_0 */ - uint disp_active; /* _DISP_DISP_ACTIVE_0 */ - uint front_porch; /* _DISP_FRONT_PORCH_0 */ - - /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ - struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; - - /* Address 0x41a ~ 0x421 */ - struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ - struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ - - /* Address 0x422 ~ 0x425 */ - struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ - struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ - - /* Address 0x426 ~ 0x429 */ - uint m0_ctrl; /* _DISP_M0_CONTROL_0 */ - uint m1_ctrl; /* _DISP_M1_CONTROL_0 */ - uint di_ctrl; /* _DISP_DI_CONTROL_0 */ - uint pp_ctrl; /* _DISP_PP_CONTROL_0 */ - - /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */ - uint pp_select[PP_SELECT_COUNT]; - - /* Address 0x42e ~ 0x435 */ - uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ - uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ - uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ - uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */ - uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */ - uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */ - uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */ - uint border_color; /* _DISP_BORDER_COLOR_0 */ - - /* Address 0x436 ~ 0x439 */ - uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */ - uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ - uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ - uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ - - uint reserved0[2]; /* reserved_0[2] */ - - /* Address 0x43c ~ 0x442 */ - uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ - uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ - uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ - uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ - uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */ - uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ - uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ - - /* Address 0x443 ~ 0x446 */ - uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ - uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ - uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ - uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */ - - uint reserved1[0x39]; /* reserved1[0x39], */ - - /* Address 0x480 ~ 0x484 */ - uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ - uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ - uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ - uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ - uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */ - - uint reserved2[0x3b]; /* reserved2[0x3b] */ - - /* Address 0x4c0 ~ 0x4c1 */ - uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ - uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ - - u32 rsvd_4c2[34]; /* 4c2 - 4e3 */ - - /* Address 0x4e4 */ - u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */ -}; - -enum dc_winc_filter_p { - WINC_FILTER_COUNT = 0x10, -}; - -/* Window A/B/C register 0x500 ~ 0x628 */ -struct dc_winc_reg { - - /* Address 0x500 */ - uint color_palette; /* _WINC_COLOR_PALETTE_0 */ - - uint reserved0[0xff]; /* reserved_0[0xff] */ - - /* Address 0x600 */ - uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ - - /* _WINC_H_FILTER_P00~0F_0 */ - /* Address 0x601 ~ 0x610 */ - uint h_filter_p[WINC_FILTER_COUNT]; - - /* Address 0x611 ~ 0x618 */ - uint csc_yof; /* _WINC_CSC_YOF_0 */ - uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ - uint csc_kur; /* _WINC_CSC_KUR_0 */ - uint csc_kvr; /* _WINC_CSC_KVR_0 */ - uint csc_kug; /* _WINC_CSC_KUG_0 */ - uint csc_kvg; /* _WINC_CSC_KVG_0 */ - uint csc_kub; /* _WINC_CSC_KUB_0 */ - uint csc_kvb; /* _WINC_CSC_KVB_0 */ - - /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ - uint v_filter_p[WINC_FILTER_COUNT]; -}; - -/* WIN A/B/C Register 0x700 ~ 0x719*/ -struct dc_win_reg { - /* Address 0x700 ~ 0x719 */ - uint win_opt; /* _WIN_WIN_OPTIONS_0 */ - uint byte_swap; /* _WIN_BYTE_SWAP_0 */ - uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ - uint color_depth; /* _WIN_COLOR_DEPTH_0 */ - uint pos; /* _WIN_POSITION_0 */ - uint size; /* _WIN_SIZE_0 */ - uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ - uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ - uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ - uint dda_increment; /* _WIN_DDA_INCREMENT_0 */ - uint line_stride; /* _WIN_LINE_STRIDE_0 */ - uint buf_stride; /* _WIN_BUF_STRIDE_0 */ - uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ - uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ - uint dv_ctrl; /* _WIN_DV_CONTROL_0 */ - uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */ - uint blend_1win; /* _WIN_BLEND_1WIN_0 */ - uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ - uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ - uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ - uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ - uint global_alpha; /* _WIN_GLOBAL_ALPHA */ - uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */ - uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */ - uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */ - uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */ -}; - -/* WINBUF A/B/C Register 0x800 ~ 0x80d */ -struct dc_winbuf_reg { - /* Address 0x800 ~ 0x80d */ - uint start_addr; /* _WINBUF_START_ADDR_0 */ - uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ - uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */ - uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ - uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */ - uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ - uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ - uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ - uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ - uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ - uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ - uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */ - uint rsvd_80c; - uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */ -}; - -/* Display Controller (DC_) regs */ -struct dc_ctlr { - struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ - uint reserved0[0x2bc]; - - struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ - uint reserved1[0xd6]; - - struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */ - uint reserved2[0x1b]; - - struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ - uint reserved3[0xd7]; - - struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/ - uint reserved4[0xe6]; - - struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */ -}; - -/* DC_CMD_DISPLAY_COMMAND 0x032 */ -#define CTRL_MODE_SHIFT 5 -#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) -enum { - CTRL_MODE_STOP, - CTRL_MODE_C_DISPLAY, - CTRL_MODE_NC_DISPLAY, -}; - -/* _WIN_COLOR_DEPTH_0 */ -enum win_color_depth_id { - COLOR_DEPTH_P1, - COLOR_DEPTH_P2, - COLOR_DEPTH_P4, - COLOR_DEPTH_P8, - COLOR_DEPTH_B4G4R4A4, - COLOR_DEPTH_B5G5R5A, - COLOR_DEPTH_B5G6R5, - COLOR_DEPTH_AB5G5R5, - COLOR_DEPTH_B8G8R8A8 = 12, - COLOR_DEPTH_R8G8B8A8, - COLOR_DEPTH_B6x2G6x2R6x2A8, - COLOR_DEPTH_R6x2G6x2B6x2A8, - COLOR_DEPTH_YCbCr422, - COLOR_DEPTH_YUV422, - COLOR_DEPTH_YCbCr420P, - COLOR_DEPTH_YUV420P, - COLOR_DEPTH_YCbCr422P, - COLOR_DEPTH_YUV422P, - COLOR_DEPTH_YCbCr422R, - COLOR_DEPTH_YUV422R, - COLOR_DEPTH_YCbCr422RA, - COLOR_DEPTH_YUV422RA, -}; - -/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ -#define PW0_ENABLE BIT(0) -#define PW1_ENABLE BIT(2) -#define PW2_ENABLE BIT(4) -#define PW3_ENABLE BIT(6) -#define PW4_ENABLE BIT(8) -#define PM0_ENABLE BIT(16) -#define PM1_ENABLE BIT(18) -#define SPI_ENABLE BIT(24) -#define HSPI_ENABLE BIT(25) - -/* DC_CMD_STATE_ACCESS 0x040 */ -#define READ_MUX_ASSEMBLY (0 << 0) -#define READ_MUX_ACTIVE (1 << 0) -#define WRITE_MUX_ASSEMBLY (0 << 2) -#define WRITE_MUX_ACTIVE (1 << 2) - -/* DC_CMD_STATE_CONTROL 0x041 */ -#define GENERAL_ACT_REQ BIT(0) -#define WIN_A_ACT_REQ BIT(1) -#define WIN_B_ACT_REQ BIT(2) -#define WIN_C_ACT_REQ BIT(3) -#define WIN_D_ACT_REQ BIT(4) -#define WIN_H_ACT_REQ BIT(5) -#define CURSOR_ACT_REQ BIT(7) -#define GENERAL_UPDATE BIT(8) -#define WIN_A_UPDATE BIT(9) -#define WIN_B_UPDATE BIT(10) -#define WIN_C_UPDATE BIT(11) -#define WIN_D_UPDATE BIT(12) -#define WIN_H_UPDATE BIT(13) -#define CURSOR_UPDATE BIT(15) -#define NC_HOST_TRIG BIT(24) - -/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ -#define WINDOW_A_SELECT BIT(4) -#define WINDOW_B_SELECT BIT(5) -#define WINDOW_C_SELECT BIT(6) -#define WINDOW_D_SELECT BIT(7) -#define WINDOW_H_SELECT BIT(8) - -/* DC_DISP_DISP_WIN_OPTIONS 0x402 */ -#define CURSOR_ENABLE BIT(16) -#define SOR_ENABLE BIT(25) -#define TVO_ENABLE BIT(28) -#define DSI_ENABLE BIT(29) -#define HDMI_ENABLE BIT(30) - -/* DC_DISP_DISP_TIMING_OPTIONS 0x405 */ -#define VSYNC_H_POSITION(x) ((x) & 0xfff) - -/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ -#define SHIFT_CLK_DIVIDER_SHIFT 0 -#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) -#define PIXEL_CLK_DIVIDER_SHIFT 8 -#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) -enum { - PIXEL_CLK_DIVIDER_PCD1, - PIXEL_CLK_DIVIDER_PCD1H, - PIXEL_CLK_DIVIDER_PCD2, - PIXEL_CLK_DIVIDER_PCD3, - PIXEL_CLK_DIVIDER_PCD4, - PIXEL_CLK_DIVIDER_PCD6, - PIXEL_CLK_DIVIDER_PCD8, - PIXEL_CLK_DIVIDER_PCD9, - PIXEL_CLK_DIVIDER_PCD12, - PIXEL_CLK_DIVIDER_PCD16, - PIXEL_CLK_DIVIDER_PCD18, - PIXEL_CLK_DIVIDER_PCD24, - PIXEL_CLK_DIVIDER_PCD13, -}; - -/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */ -#define DATA_FORMAT_SHIFT 0 -#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT) -enum { - DATA_FORMAT_DF1P1C, - DATA_FORMAT_DF1P2C24B, - DATA_FORMAT_DF1P2C18B, - DATA_FORMAT_DF1P2C16B, - DATA_FORMAT_DF2S, - DATA_FORMAT_DF3S, - DATA_FORMAT_DFSPI, - DATA_FORMAT_DF1P3C24B, - DATA_FORMAT_DF1P3C18B, -}; -#define DATA_ALIGNMENT_SHIFT 8 -enum { - DATA_ALIGNMENT_MSB, - DATA_ALIGNMENT_LSB, -}; -#define DATA_ORDER_SHIFT 9 -enum { - DATA_ORDER_RED_BLUE, - DATA_ORDER_BLUE_RED, -}; - -/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ -#define DE_SELECT_SHIFT 0 -#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) -#define DE_SELECT_ACTIVE_BLANK 0x0 -#define DE_SELECT_ACTIVE 0x1 -#define DE_SELECT_ACTIVE_IS 0x2 -#define DE_CONTROL_SHIFT 2 -#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT) -enum { - DE_CONTROL_ONECLK, - DE_CONTROL_NORMAL, - DE_CONTROL_EARLY_EXT, - DE_CONTROL_EARLY, - DE_CONTROL_ACTIVE_BLANK, -}; - -/* DC_WIN_WIN_OPTIONS 0x700 */ -#define H_DIRECTION BIT(0) -enum { - H_DIRECTION_INCREMENT, - H_DIRECTION_DECREMENT, -}; -#define V_DIRECTION BIT(2) -enum { - V_DIRECTION_INCREMENT, - V_DIRECTION_DECREMENT, -}; -#define COLOR_EXPAND BIT(6) -#define CP_ENABLE BIT(16) -#define DV_ENABLE BIT(20) -#define WIN_ENABLE BIT(30) - -/* DC_WIN_BYTE_SWAP 0x701 */ -#define BYTE_SWAP_SHIFT 0 -#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT) -enum { - BYTE_SWAP_NOSWAP, - BYTE_SWAP_SWAP2, - BYTE_SWAP_SWAP4, - BYTE_SWAP_SWAP4HW -}; - -/* DC_WIN_POSITION 0x704 */ -#define H_POSITION_SHIFT 0 -#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT) -#define V_POSITION_SHIFT 16 -#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT) - -/* DC_WIN_SIZE 0x705 */ -#define H_SIZE_SHIFT 0 -#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT) -#define V_SIZE_SHIFT 16 -#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT) - -/* DC_WIN_PRESCALED_SIZE 0x706 */ -#define H_PRESCALED_SIZE_SHIFT 0 -#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE) -#define V_PRESCALED_SIZE_SHIFT 16 -#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE) - -/* DC_WIN_DDA_INCREMENT 0x709 */ -#define H_DDA_INC_SHIFT 0 -#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT) -#define V_DDA_INC_SHIFT 16 -#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) - -#define DC_POLL_TIMEOUT_MS 50 -#define DC_N_WINDOWS 5 -#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) - -#endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h deleted file mode 100644 index cf3ce3b..0000000 --- a/arch/arm/include/asm/arch-tegra/funcmux.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra high-level function multiplexing */ - -#ifndef _TEGRA_FUNCMUX_H_ -#define _TEGRA_FUNCMUX_H_ - -/** - * Select a config for a particular peripheral. - * - * Each peripheral can operate through a number of configurations, - * which are sets of pins that it uses to bring out its signals. - * The basic config is 0, and higher numbers indicate different - * pinmux settings to bring the peripheral out on other pins, - * - * This function also disables tristate for the function's pins, - * so that they operate in normal mode. - * - * @param id Peripheral id - * @param config Configuration to use (FUNCMUX_...), 0 for default - * @return 0 if ok, -1 on error (e.g. incorrect id or config) - */ -int funcmux_select(enum periph_id id, int config); - -#endif /* _TEGRA_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h deleted file mode 100644 index 5b8e0bd..0000000 --- a/arch/arm/include/asm/arch-tegra/fuse.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _FUSE_H_ -#define _FUSE_H_ - -/* FUSE registers */ -struct fuse_regs { - u32 reserved0[64]; /* 0x00 - 0xFC: */ - u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */ - u32 reserved1[3]; /* 0x104 - 0x10c: */ - u32 sku_info; /* 0x110 */ - u32 reserved2[13]; /* 0x114 - 0x144: */ - u32 fa; /* 0x148: FUSE_FA */ - u32 reserved3[21]; /* 0x14C - 0x19C: */ - u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ -}; - -#endif /* ifndef _FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h deleted file mode 100644 index 4362c53..0000000 --- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA_GP_PADCTRL_H_ -#define _TEGRA_GP_PADCTRL_H_ - -#define GP_HIDREV 0x804 - -/* bit fields definitions for APB_MISC_GP_HIDREV register */ -#define HIDREV_CHIPID_SHIFT 8 -#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) -#define HIDREV_MAJORPREV_SHIFT 4 -#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) - -/* CHIPID field returned from APB_MISC_GP_HIDREV register */ -#define CHIPID_TEGRA20 0x20 -#define CHIPID_TEGRA30 0x30 -#define CHIPID_TEGRA114 0x35 -#define CHIPID_TEGRA124 0x40 -#define CHIPID_TEGRA210 0x21 - -#endif /* _TEGRA_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h deleted file mode 100644 index fe7b3a5..0000000 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - */ - -#ifndef _TEGRA_GPIO_H_ -#define _TEGRA_GPIO_H_ - -#include <dt-bindings/gpio/tegra-gpio.h> - -#define TEGRA_GPIOS_PER_PORT 8 -#define TEGRA_PORTS_PER_BANK 4 -#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) -#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ - -#define GPIO_BANK(x) ((x) >> 5) -#define GPIO_PORT(x) (((x) >> 3) & 0x3) -#define GPIO_FULLPORT(x) ((x) >> 3) -#define GPIO_BIT(x) ((x) & 0x7) - -enum tegra_gpio_init { - TEGRA_GPIO_INIT_IN, - TEGRA_GPIO_INIT_OUT0, - TEGRA_GPIO_INIT_OUT1, -}; - -struct tegra_gpio_config { - u32 gpio:16; - u32 init:2; -}; - -/** - * Configure a list of GPIOs - * - * @param config List of GPIO configurations - * @param len Number of config items in list - */ -void gpio_config_table(const struct tegra_gpio_config *config, int len); - -#endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h deleted file mode 100644 index d4d6deb..0000000 --- a/arch/arm/include/asm/arch-tegra/gpu.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_GPU_H -#define __ASM_ARCH_TEGRA_GPU_H - -#if defined(CONFIG_TEGRA_GPU) - -void tegra_gpu_config(void); - -#else /* CONFIG_TEGRA_GPU */ - -static inline void tegra_gpu_config(void) -{ -} - -#endif /* CONFIG_TEGRA_GPU */ - -#if defined(CONFIG_OF_LIBFDT) - -int tegra_gpu_enable_node(void *blob, const char *gpupath); - -#else /* CONFIG_OF_LIBFDT */ - -static inline int tegra_gpu_enable_node(void *blob, const char *compat) -{ - return 0; -} - -#endif /* CONFIG_OF_LIBFDT */ - -#endif /* __ASM_ARCH_TEGRA_GPU_H */ diff --git a/arch/arm/include/asm/arch-tegra/ivc.h b/arch/arm/include/asm/arch-tegra/ivc.h deleted file mode 100644 index 53cb56d..0000000 --- a/arch/arm/include/asm/arch-tegra/ivc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. - */ - -#ifndef _ASM_ARCH_TEGRA_IVC_H -#define _ASM_ARCH_TEGRA_IVC_H - -#include <common.h> - -/* - * Tegra IVC is a communication protocol that transfers fixed-size frames - * bi-directionally and in-order between the local CPU and some remote entity. - * Communication is via a statically sized and allocated buffer in shared - * memory and a notification mechanism. - * - * This API handles all aspects of the shared memory buffer's metadata, and - * leaves all aspects of the frame content to the calling code; frames - * typically contain some higher-level protocol. The notification mechanism is - * also handled externally to this API, since it can vary from instance to - * instance. - * - * The client model is to first find some free (for TX) or filled (for RX) - * frame, process that frame's memory buffer (fill or read it), and then - * inform the protocol that the frame has been filled/read, i.e. advance the - * write/read pointer. If the channel is full, there may be no available frames - * to fill/read. In this case, client code may either poll for an available - * frame, or wait for the remote entity to send a notification to the local - * CPU. - */ - -/** - * struct tegra_ivc - In-memory shared memory layout. - * - * This is described in detail in ivc.c. - */ -struct tegra_ivc_channel_header; - -/** - * struct tegra_ivc - Software state of an IVC channel. - * - * This state is internal to the IVC code and should not be accessed directly - * by clients. It is public solely so clients can allocate storage for the - * structure. - */ -struct tegra_ivc { - /** - * rx_channel - Pointer to the shared memory region used to receive - * messages from the remote entity. - */ - struct tegra_ivc_channel_header *rx_channel; - /** - * tx_channel - Pointer to the shared memory region used to send - * messages to the remote entity. - */ - struct tegra_ivc_channel_header *tx_channel; - /** - * r_pos - The position in list of frames in rx_channel that we are - * reading from. - */ - uint32_t r_pos; - /** - * w_pos - The position in list of frames in tx_channel that we are - * writing to. - */ - uint32_t w_pos; - /** - * nframes - The number of frames allocated (in each direction) in - * shared memory. - */ - uint32_t nframes; - /** - * frame_size - The size of each frame in shared memory. - */ - uint32_t frame_size; - /** - * notify - Function to call to notify the remote processor of a - * change in channel state. - */ - void (*notify)(struct tegra_ivc *); -}; - -/** - * tegra_ivc_read_get_next_frame - Locate the next frame to receive. - * - * Locate the next frame to be received/processed, return the address of the - * frame, and do not remove it from the queue. Repeated calls to this function - * will return the same address until tegra_ivc_read_advance() is called. - * - * @ivc The IVC channel. - * @frame Pointer to be filled with the address of the frame to receive. - * - * @return 0 if a frame is available, else a negative error code. - */ -int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame); - -/** - * tegra_ivc_read_advance - Advance the read queue. - * - * Inform the protocol and remote entity that the frame returned by - * tegra_ivc_read_get_next_frame() has been processed. The remote end may then - * re-use it to transmit further data. Subsequent to this function returning, - * tegra_ivc_read_get_next_frame() will return a different frame. - * - * @ivc The IVC channel. - * - * @return 0 if OK, else a negative error code. - */ -int tegra_ivc_read_advance(struct tegra_ivc *ivc); - -/** - * tegra_ivc_write_get_next_frame - Locate the next frame to fill for transmit. - * - * Locate the next frame to be filled for transmit, return the address of the - * frame, and do not add it to the queue. Repeated calls to this function - * will return the same address until tegra_ivc_read_advance() is called. - * - * @ivc The IVC channel. - * @frame Pointer to be filled with the address of the frame to fill. - * - * @return 0 if a frame is available, else a negative error code. - */ -int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame); - -/** - * tegra_ivc_write_advance - Advance the write queue. - * - * Inform the protocol and remote entity that the frame returned by - * tegra_ivc_write_get_next_frame() has been filled and should be transmitted. - * The remote end may then read data from it. Subsequent to this function - * returning, tegra_ivc_write_get_next_frame() will return a different frame. - * - * @ivc The IVC channel. - * - * @return 0 if OK, else a negative error code. - */ -int tegra_ivc_write_advance(struct tegra_ivc *ivc); - -/** - * tegra_ivc_channel_notified - handle internal messages - * - * This function must be called following every notification. - * - * @ivc The IVC channel. - * - * @return 0 if the channel is ready for communication, or -EAGAIN if a - * channel reset is in progress. - */ -int tegra_ivc_channel_notified(struct tegra_ivc *ivc); - -/** - * tegra_ivc_channel_reset - initiates a reset of the shared memory state - * - * This function must be called after a channel is initialized but before it - * is used for communication. The channel will be ready for use when a - * subsequent call to notify the remote of the channel reset indicates the - * reset operation is complete. - * - * @ivc The IVC channel. - */ -void tegra_ivc_channel_reset(struct tegra_ivc *ivc); - -/** - * tegra_ivc_init - Initialize a channel's software state. - * - * @ivc The IVC channel. - * @rx_base Address of the the RX shared memory buffer. - * @tx_base Address of the the TX shared memory buffer. - * @nframes Number of frames in each shared memory buffer. - * @frame_size Size of each frame. - * - * @return 0 if OK, else a negative error code. - */ -int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, - uint32_t nframes, uint32_t frame_size, - void (*notify)(struct tegra_ivc *)); - -#endif diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h deleted file mode 100644 index 4b6e841..0000000 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ /dev/null @@ -1,249 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA_PINMUX_H_ -#define _TEGRA_PINMUX_H_ - -#include <linux/types.h> - -#include <asm/arch/tegra.h> - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; - -#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT -enum pmux_pin_io { - PMUX_PIN_OUTPUT = 0, - PMUX_PIN_INPUT = 1, - PMUX_PIN_NONE, -}; -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_LOCK -enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, - PMUX_PIN_LOCK_ENABLE, -}; -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_OD -enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, - PMUX_PIN_OD_ENABLE, -}; -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET -enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, - PMUX_PIN_IO_RESET_ENABLE, -}; -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL -enum pmux_pin_rcv_sel { - PMUX_PIN_RCV_SEL_DEFAULT = 0, - PMUX_PIN_RCV_SEL_NORMAL, - PMUX_PIN_RCV_SEL_HIGH, -}; -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV -enum pmux_pin_e_io_hv { - PMUX_PIN_E_IO_HV_DEFAULT = 0, - PMUX_PIN_E_IO_HV_NORMAL, - PMUX_PIN_E_IO_HV_HIGH, -}; -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD -/* Defines a pin group cfg's low-power mode select */ -enum pmux_lpmd { - PMUX_LPMD_X8 = 0, - PMUX_LPMD_X4, - PMUX_LPMD_X2, - PMUX_LPMD_X, - PMUX_LPMD_NONE = -1, -}; -#endif - -#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pmux_schmt { - PMUX_SCHMT_DISABLE = 0, - PMUX_SCHMT_ENABLE = 1, - PMUX_SCHMT_NONE = -1, -}; -#endif - -#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pmux_hsm { - PMUX_HSM_DISABLE = 0, - PMUX_HSM_ENABLE = 1, - PMUX_HSM_NONE = -1, -}; -#endif - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pmux_pingrp_config { - u32 pingrp:16; /* pin group PMUX_PINGRP_... */ - u32 func:8; /* function to assign PMUX_FUNC_... */ - u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ - u32 tristate:2; /* tristate or normal PMUX_TRI_... */ -#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT - u32 io:2; /* input or output PMUX_PIN_... */ -#endif -#ifdef TEGRA_PMX_PINS_HAVE_LOCK - u32 lock:2; /* lock enable/disable PMUX_PIN... */ -#endif -#ifdef TEGRA_PMX_PINS_HAVE_OD - u32 od:2; /* open-drain or push-pull driver */ -#endif -#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET - u32 ioreset:2; /* input/output reset PMUX_PIN... */ -#endif -#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL - u32 rcv_sel:2; /* select between High and Normal */ - /* VIL/VIH receivers */ -#endif -#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV - u32 e_io_hv:2; /* select 3.3v tolerant receivers */ -#endif -#ifdef TEGRA_PMX_PINS_HAVE_SCHMT - u32 schmt:2; /* schmitt enable */ -#endif -#ifdef TEGRA_PMX_PINS_HAVE_HSM - u32 hsm:2; /* high-speed mode enable */ -#endif -}; - -#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING -/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ -void pinmux_set_tristate_input_clamping(void); -void pinmux_clear_tristate_input_clamping(void); -#endif - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT -/* Set a pin group as input or output */ -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); -#endif - -/** - * Configure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, - int len); - -struct pmux_pingrp_desc { - u8 funcs[4]; -#if defined(CONFIG_TEGRA20) - u8 ctl_id; - u8 pull_id; -#endif /* CONFIG_TEGRA20 */ -}; - -extern const struct pmux_pingrp_desc *tegra_soc_pingroups; - -#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS - -#define PMUX_SLWF_MIN 0 -#define PMUX_SLWF_MAX 3 -#define PMUX_SLWF_NONE -1 - -#define PMUX_SLWR_MIN 0 -#define PMUX_SLWR_MAX 3 -#define PMUX_SLWR_NONE -1 - -#define PMUX_DRVUP_MIN 0 -#define PMUX_DRVUP_MAX 127 -#define PMUX_DRVUP_NONE -1 - -#define PMUX_DRVDN_MIN 0 -#define PMUX_DRVDN_MAX 127 -#define PMUX_DRVDN_NONE -1 - -/* - * This defines the configuration for a pin group's pad control config - */ -struct pmux_drvgrp_config { - u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ - u32 slwf:3; /* falling edge slew */ - u32 slwr:3; /* rising edge slew */ - u32 drvup:8; /* pull-up drive strength */ - u32 drvdn:8; /* pull-down drive strength */ -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD - u32 lpmd:3; /* low-power mode selection */ -#endif -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT - u32 schmt:2; /* schmidt enable */ -#endif -#ifdef TEGRA_PMX_GRPS_HAVE_HSM - u32 hsm:2; /* high-speed mode enable */ -#endif -}; - -/** - * Set the GP pad configs - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, - int len); - -#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ - -#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS -struct pmux_mipipadctrlgrp_config { - u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ - u32 func:8; /* function to assign PMUX_FUNC_... */ -}; - -void pinmux_config_mipipadctrlgrp_table( - const struct pmux_mipipadctrlgrp_config *config, int len); - -struct pmux_mipipadctrlgrp_desc { - u8 funcs[2]; -}; - -extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; -#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ - -#endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h deleted file mode 100644 index 1524bf2..0000000 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ /dev/null @@ -1,409 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2019 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _PMC_H_ -#define _PMC_H_ - -/* Power Management Controller (APBDEV_PMC_) registers */ -struct pmc_ctlr { - uint pmc_cntrl; /* _CNTRL_0, offset 00 */ - uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ - uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ - uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ - uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ - uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ - uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ - uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ - uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ - uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ - uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) - uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ -#else - uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */ -#endif - uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ - uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ - uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ - uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ - uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ - uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ - uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */ - uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ - - uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */ - uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */ - uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */ - uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */ - uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */ - uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */ - uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */ - uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */ - uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */ - uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */ - uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */ - uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */ - uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */ - uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */ - uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */ - uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */ - uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */ - uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */ - uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */ - uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */ - uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */ - uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */ - uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */ - uint pmc_scratch23; /* _SCRATCH23_0, offset AC */ - - uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ - uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ - uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ - uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ - uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ - uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ - - uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ - uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ - uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */ - uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ - uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ - uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ - uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ - uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ - uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ - uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ - uint pmc_usb_ao; /* _USB_AO_0, offset F0 */ - uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ - uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ - - uint pmc_scratch24; /* _SCRATCH24_0, offset FC */ - uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */ - uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */ - uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */ - uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */ - uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */ - uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */ - uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */ - uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */ - uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */ - uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */ - uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */ - uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */ - uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */ - uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */ - uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */ - uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */ - uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */ - uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */ - - uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ - uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ - uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ - uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ - uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ - uint pmc_gate; /* _GATE_0, offset 15C */ - /* The following fields are in Tegra124 and later only */ - uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ - uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ - uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ - uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ - uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ - uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ - uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ - uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ - uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ - uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ - uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ - uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ - uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ - uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ - uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ - uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ - uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ - uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ - uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ - uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ - uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ - uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ - uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ - uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ - uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ - uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ - uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ - uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ - - uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ - uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ - uint pmc_reserved0; /* _RESERVED, offset 1D8 */ - uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ - uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ - uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ - uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ - uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ - uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ - uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ - uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ - uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ - - uint pmc_todo_0[9]; /* offset 200-220 */ - uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ - uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ - uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */ - uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */ - uint pmc_scratch45; - uint pmc_scratch46; - uint pmc_scratch47; - uint pmc_scratch48; - uint pmc_scratch49; - uint pmc_scratch50; - uint pmc_scratch51; - uint pmc_scratch52; - uint pmc_scratch53; - uint pmc_scratch54; - uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */ - uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */ - uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */ - uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */ - uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ - uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ - uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ - uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ - uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ - uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ - uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ - uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ - uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ - uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ - uint pmc_secure_scratch9; - uint pmc_secure_scratch10; - uint pmc_secure_scratch11; - uint pmc_secure_scratch12; - uint pmc_secure_scratch13; - uint pmc_secure_scratch14; - uint pmc_secure_scratch15; - uint pmc_secure_scratch16; - uint pmc_secure_scratch17; - uint pmc_secure_scratch18; - uint pmc_secure_scratch19; - uint pmc_secure_scratch20; - uint pmc_secure_scratch21; - uint pmc_secure_scratch22; - uint pmc_secure_scratch23; - uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */ - uint pmc_secure_scratch25; - uint pmc_secure_scratch26; - uint pmc_secure_scratch27; - uint pmc_secure_scratch28; - uint pmc_secure_scratch29; - uint pmc_secure_scratch30; - uint pmc_secure_scratch31; - uint pmc_secure_scratch32; - uint pmc_secure_scratch33; - uint pmc_secure_scratch34; - uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */ - - uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */ - uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */ - uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */ - uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */ - uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */ - uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */ - uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */ - - uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */ - uint pmc_scratch57; - uint pmc_scratch58; - uint pmc_scratch59; - uint pmc_scratch60; - uint pmc_scratch61; - uint pmc_scratch62; - uint pmc_scratch63; - uint pmc_scratch64; - uint pmc_scratch65; - uint pmc_scratch66; - uint pmc_scratch67; - uint pmc_scratch68; - uint pmc_scratch69; - uint pmc_scratch70; - uint pmc_scratch71; - uint pmc_scratch72; - uint pmc_scratch73; - uint pmc_scratch74; - uint pmc_scratch75; - uint pmc_scratch76; - uint pmc_scratch77; - uint pmc_scratch78; - uint pmc_scratch79; - uint pmc_scratch80; - uint pmc_scratch81; - uint pmc_scratch82; - uint pmc_scratch83; - uint pmc_scratch84; - uint pmc_scratch85; - uint pmc_scratch86; - uint pmc_scratch87; - uint pmc_scratch88; - uint pmc_scratch89; - uint pmc_scratch90; - uint pmc_scratch91; - uint pmc_scratch92; - uint pmc_scratch93; - uint pmc_scratch94; - uint pmc_scratch95; - uint pmc_scratch96; - uint pmc_scratch97; - uint pmc_scratch98; - uint pmc_scratch99; - uint pmc_scratch100; - uint pmc_scratch101; - uint pmc_scratch102; - uint pmc_scratch103; - uint pmc_scratch104; - uint pmc_scratch105; - uint pmc_scratch106; - uint pmc_scratch107; - uint pmc_scratch108; - uint pmc_scratch109; - uint pmc_scratch110; - uint pmc_scratch111; - uint pmc_scratch112; - uint pmc_scratch113; - uint pmc_scratch114; - uint pmc_scratch115; - uint pmc_scratch116; - uint pmc_scratch117; - uint pmc_scratch118; - uint pmc_scratch119; - uint pmc_scratch1_eco; /* offset 700 */ -}; - -#define CPU_PWRED 1 -#define CPU_CLMP 1 - -#define PARTID_CP 0xFFFFFFF8 -#define START_CP (1 << 8) - -#define CPUPWRREQ_OE (1 << 16) -#define CPUPWRREQ_POL (1 << 15) - -#define CRAIL 0 -#define CE0 14 -#define C0NC 15 -#define SOR 17 - -#define PMC_XOFS_SHIFT 1 -#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) - -#if defined(CONFIG_TEGRA114) -#define TIMER_MULT_SHIFT 0 -#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) -#define TIMER_MULT_CPU_SHIFT 2 -#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) -#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) -#define TIMER_MULT_SHIFT 0 -#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT) -#define TIMER_MULT_CPU_SHIFT 3 -#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT) -#endif - -#define MULT_1 0 -#define MULT_2 1 -#define MULT_4 2 -#define MULT_8 3 -#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) -#define MULT_16 4 -#endif - -#define AMAP_WRITE_SHIFT 20 -#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) - -/* SEC_DISABLE_0, 0x04 */ -#define SEC_DISABLE_WRITE0_ON (1 << 4) -#define SEC_DISABLE_READ0_ON (1 << 5) -#define SEC_DISABLE_WRITE1_ON (1 << 6) -#define SEC_DISABLE_READ1_ON (1 << 7) -#define SEC_DISABLE_WRITE2_ON (1 << 8) -#define SEC_DISABLE_READ2_ON (1 << 9) -#define SEC_DISABLE_WRITE3_ON (1 << 10) -#define SEC_DISABLE_READ3_ON (1 << 11) -#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) - -/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ -#define PWRGATE_TOGGLE_PARTID_CRAIL 0 -#define PWRGATE_TOGGLE_PARTID_TD 1 -#define PWRGATE_TOGGLE_PARTID_VE 2 -#define PWRGATE_TOGGLE_PARTID_PCX 3 -#define PWRGATE_TOGGLE_PARTID_VDE 4 -#define PWRGATE_TOGGLE_PARTID_L2C 5 -#define PWRGATE_TOGGLE_PARTID_MPE 6 -#define PWRGATE_TOGGLE_PARTID_HEG 7 -#define PWRGATE_TOGGLE_PARTID_SAX 8 -#define PWRGATE_TOGGLE_PARTID_CE1 9 -#define PWRGATE_TOGGLE_PARTID_CE2 10 -#define PWRGATE_TOGGLE_PARTID_CE3 11 -#define PWRGATE_TOGGLE_PARTID_CELP 12 -#define PWRGATE_TOGGLE_PARTID_CE0 14 -#define PWRGATE_TOGGLE_PARTID_C0NC 15 -#define PWRGATE_TOGGLE_PARTID_C1NC 16 -#define PWRGATE_TOGGLE_PARTID_SOR 17 -#define PWRGATE_TOGGLE_PARTID_DIS 18 -#define PWRGATE_TOGGLE_PARTID_DISB 19 -#define PWRGATE_TOGGLE_PARTID_XUSBA 20 -#define PWRGATE_TOGGLE_PARTID_XUSBB 21 -#define PWRGATE_TOGGLE_PARTID_XUSBC 22 -#define PWRGATE_TOGGLE_PARTID_VIC 23 -#define PWRGATE_TOGGLE_PARTID_IRAM 24 -#define PWRGATE_TOGGLE_START (1 << 8) - -/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ -#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) -#define PWRGATE_STATUS_TD_ENABLE (1 << 1) -#define PWRGATE_STATUS_VE_ENABLE (1 << 2) -#define PWRGATE_STATUS_PCX_ENABLE (1 << 3) -#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) -#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) -#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) -#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) -#define PWRGATE_STATUS_SAX_ENABLE (1 << 8) -#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) -#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) -#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) -#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) -#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) -#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) -#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) -#define PWRGATE_STATUS_SOR_ENABLE (1 << 17) -#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) -#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) -#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) -#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) -#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) -#define PWRGATE_STATUS_VIC_ENABLE (1 << 23) -#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24) - -/* APBDEV_PMC_CNTRL2_0 0x440 */ -#define HOLD_CKE_LOW_EN (1 << 12) - -/* PMC read/write functions */ -u32 tegra_pmc_readl(unsigned long offset); -void tegra_pmc_writel(u32 value, unsigned long offset); - -#define PMC_CNTRL 0x0 -#define PMC_CNTRL_MAIN_RST BIT(4) - -#if IS_ENABLED(CONFIG_TEGRA186) -# define PMC_SCRATCH0 0x32000 -#else -# define PMC_SCRATCH0 0x00050 -#endif - -/* for secure PMC */ -#define TEGRA_SMC_PMC 0xc2fffe00 -#define TEGRA_SMC_PMC_READ 0xaa -#define TEGRA_SMC_PMC_WRITE 0xbb - -#endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra/pmu.h b/arch/arm/include/asm/arch-tegra/pmu.h deleted file mode 100644 index e850875..0000000 --- a/arch/arm/include/asm/arch-tegra/pmu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA_PMU_H_ -#define _TEGRA_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h deleted file mode 100644 index 2e491f1..0000000 --- a/arch/arm/include/asm/arch-tegra/powergate.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef _TEGRA_POWERGATE_H_ -#define _TEGRA_POWERGATE_H_ - -#include <asm/arch/clock.h> - -enum tegra_powergate { - TEGRA_POWERGATE_CPU, - TEGRA_POWERGATE_3D, - TEGRA_POWERGATE_VENC, - TEGRA_POWERGATE_PCIE, - TEGRA_POWERGATE_VDEC, - TEGRA_POWERGATE_L2, - TEGRA_POWERGATE_MPE, - TEGRA_POWERGATE_HEG, - TEGRA_POWERGATE_SATA, - TEGRA_POWERGATE_CPU1, - TEGRA_POWERGATE_CPU2, - TEGRA_POWERGATE_CPU3, - TEGRA_POWERGATE_CELP, - TEGRA_POWERGATE_3D1, - TEGRA_POWERGATE_CPU0, - TEGRA_POWERGATE_C0NC, - TEGRA_POWERGATE_C1NC, - TEGRA_POWERGATE_SOR, - TEGRA_POWERGATE_DIS, - TEGRA_POWERGATE_DISB, - TEGRA_POWERGATE_XUSBA, - TEGRA_POWERGATE_XUSBB, - TEGRA_POWERGATE_XUSBC, - TEGRA_POWERGATE_VIC, - TEGRA_POWERGATE_IRAM, -}; - -int tegra_powergate_sequence_power_up(enum tegra_powergate id, - enum periph_id periph); -int tegra_powergate_power_on(enum tegra_powergate id); -int tegra_powergate_power_off(enum tegra_powergate id); - -#endif diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h deleted file mode 100644 index eebd104..0000000 --- a/arch/arm/include/asm/arch-tegra/pwm.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Tegra pulse width frequency modulator definitions - * - * Copyright (c) 2011 The Chromium OS Authors. - */ - -#ifndef __ASM_ARCH_TEGRA_PWM_H -#define __ASM_ARCH_TEGRA_PWM_H - -/* This is a single PWM channel */ -struct pwm_ctlr { - uint control; /* Control register */ - uint reserved[3]; /* Space space */ -}; - -#define PWM_NUM_CHANNELS 4 - -/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ -#define PWM_ENABLE_SHIFT 31 -#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) - -#define PWM_WIDTH_SHIFT 16 -#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) - -#define PWM_DIVIDER_SHIFT 0 -#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) - -#endif /* __ASM_ARCH_TEGRA_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra/scu.h b/arch/arm/include/asm/arch-tegra/scu.h deleted file mode 100644 index afe0764..0000000 --- a/arch/arm/include/asm/arch-tegra/scu.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _SCU_H_ -#define _SCU_H_ - -/* ARM Snoop Control Unit (SCU) registers */ -struct scu_ctlr { - uint scu_ctrl; /* SCU Control Register, offset 00 */ - uint scu_cfg; /* SCU Config Register, offset 04 */ - uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ - uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ - uint scu_reserved0[12]; /* reserved, offset 10-3C */ - uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ - uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ - uint scu_reserved1[2]; /* reserved, offset 48-4C */ - uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ - uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ -}; - -#define SCU_CTRL_ENABLE (1 << 0) - -#endif /* SCU_H */ diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h deleted file mode 100644 index 62e1c7b..0000000 --- a/arch/arm/include/asm/arch-tegra/sys_proto.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -void invalidate_dcache(void); - -/** - * tegra_board_id() - Get the board iD - * - * @return a board ID, or -ve on error - */ -int tegra_board_id(void); - -/** - * tegra_lcd_pmic_init() - Set up the PMIC for a board - * - * @board_id: Board ID which may be used to select LCD type - * @return 0 if OK, -ve on error - */ -int tegra_lcd_pmic_init(int board_id); - -/** - * nvidia_board_init() - perform any board-specific init - * - * @return 0 if OK, -ve on error - */ -int nvidia_board_init(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h deleted file mode 100644 index 7a4e097..0000000 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA_H_ -#define _TEGRA_H_ - -#define NV_PA_ARM_PERIPHBASE 0x50040000 -#define NV_PA_PG_UP_BASE 0x60000000 -#define NV_PA_TMRUS_BASE 0x60005010 -#define NV_PA_CLK_RST_BASE 0x60006000 -#define NV_PA_FLOW_BASE 0x60007000 -#define NV_PA_GPIO_BASE 0x6000D000 -#define NV_PA_EVP_BASE 0x6000F000 -#define NV_PA_APB_MISC_BASE 0x70000000 -#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) -#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) -#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) -#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) -#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) -#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) -#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) -#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) -#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) -#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) -#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) -#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) -#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ - defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \ - defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210) -#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#else -#define NV_PA_PMC_BASE 0xc360000 -#endif -#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) -#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ - defined(CONFIG_TEGRA114) -#define NV_PA_CSITE_BASE 0x70040000 -#else -#define NV_PA_CSITE_BASE 0x70800000 -#endif -#define TEGRA_USB_ADDR_MASK 0xFFFFC000 - -#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE -#define LOW_LEVEL_SRAM_STACK 0x4000FFFC -#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) -#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) -#define PG_UP_TAG_AVP 0xAAAAAAAA - -#ifndef __ASSEMBLY__ -struct timerus { - unsigned int cntr_1us; -}; - -/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ -#define NV_WB_RUN_ADDRESS 0x40020000 - -#define NVBOOTTYPE_RECOVERY 2 /* BR entered RCM */ -#define NVBOOTINFOTABLE_BOOTTYPE 0xC /* Boot type in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ - -/* These are the available SKUs (product types) for Tegra */ -enum { - SKU_ID_T20_7 = 0x7, - SKU_ID_T20 = 0x8, - SKU_ID_T25SE = 0x14, - SKU_ID_AP25 = 0x17, - SKU_ID_T25 = 0x18, - SKU_ID_AP25E = 0x1b, - SKU_ID_T25E = 0x1c, - SKU_ID_T33 = 0x80, - SKU_ID_T30 = 0x81, /* Cardhu value */ - SKU_ID_TM30MQS_P_A3 = 0xb1, - SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ - SKU_ID_T114_1 = 0x01, - SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ - SKU_ID_T210_ENG = 0x00, /* unfused value TBD */ -}; - -/* - * These are used to distinguish SOC types for setting up clocks. Mostly - * we can tell the clocking required by looking at the SOC sku_id, but - * for T30 it is a user option as to whether to run PLLP in fast or slow - * mode, so we have two options there. - */ -enum { - TEGRA_SOC_T20, - TEGRA_SOC_T25, - TEGRA_SOC_T30, - TEGRA_SOC_T114, - TEGRA_SOC_T124, - TEGRA_SOC_T210, - - TEGRA_SOC_CNT, - TEGRA_SOC_UNKNOWN = -1, -}; - -/* Tegra system controller (SYSCON) devices */ -enum { - TEGRA_SYSCON_PMC, -}; - -#else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL NV_PA_PMC_BASE -#endif - -#endif /* TEGRA_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_ahub.h b/arch/arm/include/asm/arch-tegra/tegra_ahub.h deleted file mode 100644 index 96d542a..0000000 --- a/arch/arm/include/asm/arch-tegra/tegra_ahub.h +++ /dev/null @@ -1,475 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * tegra_ahub.h - Definitions for Tegra124 audio hub driver - * Taken from dc tegra_ahub.h - * - * Copyright 2018 Google LLC - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA_AHUB_H_ -#define _TEGRA_AHUB_H_ - -/* - * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio - * transmitted by a particular TX CIF. - */ -struct xbar_regs { - u32 apbif_rx0; /* AUDIO_APBIF_RX0, offset 0x00 */ - u32 apbif_rx1; /* AUDIO_APBIF_RX1, offset 0x04 */ - u32 apbif_rx2; /* AUDIO_APBIF_RX2, offset 0x08 */ - u32 apbif_rx3; /* AUDIO_APBIF_RX3, offset 0x0C */ - - u32 i2s0_rx0; /* AUDIO_I2S0_RX0, offset 0x10 */ - u32 i2s1_rx0; /* AUDIO_I2S1_RX0, offset 0x14 */ - u32 i2s2_rx0; /* AUDIO_I2S2_RX0, offset 0x18 */ - u32 i2s3_rx0; /* AUDIO_I2S3_RX0, offset 0x1C */ - u32 i2s4_rx0; /* AUDIO_I2S4_RX0, offset 0x20 */ - - u32 dam0_rx0; /* AUDIO_DAM0_RX0, offset 0x24 */ - u32 dam0_rx1; /* AUDIO_DAM0_RX1, offset 0x28 */ - u32 dam1_rx0; /* AUDIO_DAM1_RX0, offset 0x2C */ - u32 dam1_rx1; /* AUDIO_DAM1_RX1, offset 0x30 */ - u32 dam2_rx0; /* AUDIO_DAM2_RX0, offset 0x34 */ - u32 dam2_rx1; /* AUDIO_DAM2_RX1, offset 0x38 */ - - u32 spdif_rx0; /* AUDIO_SPDIF_RX0, offset 0x3C */ - u32 spdif_rx1; /* AUDIO_SPDIF_RX1, offset 0x40 */ - - u32 apbif_rx4; /* AUDIO_APBIF_RX4, offset 0x44 */ - u32 apbif_rx5; /* AUDIO_APBIF_RX4, offset 0x48 */ - u32 apbif_rx6; /* AUDIO_APBIF_RX4, offset 0x4C */ - u32 apbif_rx7; /* AUDIO_APBIF_RX4, offset 0x50 */ - u32 apbif_rx8; /* AUDIO_APBIF_RX4, offset 0x54 */ - u32 apbif_rx9; /* AUDIO_APBIF_RX4, offset 0x58 */ - - u32 amx0_rx0; /* AUDIO_AMX0_RX0, offset 0x5C */ - u32 amx0_rx1; /* AUDIO_AMX0_RX1, offset 0x60 */ - u32 amx0_rx2; /* AUDIO_AMX0_RX2, offset 0x64 */ - u32 amx0_rx3; /* AUDIO_AMX0_RX3, offset 0x68 */ - - u32 adx0_rx0; /* AUDIO_ADX0_RX0, offset 0x6C */ -}; - -struct apbif_regs { - u32 channel0_ctrl; /* APBIF_CHANNEL0_CTRL */ - u32 channel0_clr; /* APBIF_CHANNEL0_CLEAR */ - u32 channel0_stat; /* APBIF_CHANNEL0_STATUS */ - u32 channel0_txfifo; /* APBIF_CHANNEL0_TXFIFO */ - u32 channel0_rxfifo; /* APBIF_CHANNEL0_RXFIFO */ - u32 channel0_cif_tx0_ctrl; /* APBIF_AUDIOCIF_TX0_CTRL */ - u32 channel0_cif_rx0_ctrl; /* APBIF_AUDIOCIF_RX0_CTRL */ - u32 channel0_reserved0; /* RESERVED, offset 0x1C */ - /* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ - /* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ - /* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ - u32 reserved123[3 * 8]; - u32 config_link_ctrl; /* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */ - u32 misc_ctrl; /* APBIF_MISC_CTRL_0, offset 0x84 */ - u32 apbdma_live_stat; /* APBIF_APBDMA_LIVE_STATUS_0 */ - u32 i2s_live_stat; /* APBIF_I2S_LIVE_STATUS_0 */ - u32 dam0_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ - u32 dam1_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ - u32 dam2_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ - u32 spdif_live_stat; /* APBIF_SPDIF_LIVE_STATUS_0 */ - u32 i2s_int_mask; /* APBIF_I2S_INT_MASK_0, offset B0 */ - u32 dam_int_mask; /* APBIF_DAM_INT_MASK_0 */ - u32 reserved_int_mask; /* RESERVED, offset 0xB8 */ - u32 spdif_int_mask; /* APBIF_SPDIF_INT_MASK_0 */ - u32 apbif_int_mask; /* APBIF_APBIF_INT_MASK_0, off C0 */ - u32 reserved2_int_mask; /* RESERVED, offset 0xC4 */ - u32 i2s_int_stat; /* APBIF_I2S_INT_STATUS_0, offset C8 */ - u32 dam_int_stat; /* APBIF_DAM_INT_STATUS_0 */ - u32 reserved_int_stat; /* RESERVED, offset 0xD0 */ - u32 spdif_int_stat; /* APBIF_SPDIF_INT_STATUS_0 */ - u32 apbif_int_stat; /* APBIF_APBIF_INT_STATUS_0 */ - u32 reserved2_int_stat; /* RESERVED, offset 0xDC */ - u32 i2s_int_src; /* APBIF_I2S_INT_SOURCE_0, offset E0 */ - u32 dam_int_src; /* APBIF_DAM_INT_SOURCE_0 */ - u32 reserved_int_src; /* RESERVED, offset 0xE8 */ - u32 spdif_int_src; /* APBIF_SPDIF_INT_SOURCE_0 */ - u32 apbif_int_src; /* APBIF_APBIF_INT_SOURCE_0, off F0 */ - u32 reserved2_int_src; /* RESERVED, offset 0xF4 */ - u32 i2s_int_set; /* APBIF_I2S_INT_SET_0, offset 0xF8 */ - u32 dam_int_set; /* APBIF_DAM_INT_SET_0, offset 0xFC */ - u32 spdif_int_set; /* APBIF_SPDIF_INT_SET_0, off 0x100 */ - u32 apbif_int_set; /* APBIF_APBIF_INT_SET_0, off 0x104 */ -}; - -/* - * Tegra AHUB Registers Definition - */ -enum { - TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT = 24, - TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US = 0x3f, - TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK = - TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << - TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT, - - /* Channel count minus 1 */ - TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT = 20, - TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US = 0xf, - TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK = - TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << - TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT, - - /* Channel count minus 1 */ - TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT = 16, - TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US = 0xf, - TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK = - TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << - TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT, - - TEGRA_AUDIOCIF_BITS_4 = 0, - TEGRA_AUDIOCIF_BITS_8 = 1, - TEGRA_AUDIOCIF_BITS_12 = 2, - TEGRA_AUDIOCIF_BITS_16 = 3, - TEGRA_AUDIOCIF_BITS_20 = 4, - TEGRA_AUDIOCIF_BITS_24 = 5, - TEGRA_AUDIOCIF_BITS_28 = 6, - TEGRA_AUDIOCIF_BITS_32 = 7, - - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT = 12, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_MASK = - 7 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_4 = - TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_8 = - TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_12 = - TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_16 = - TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_20 = - TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_24 = - TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_28 = - TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_32 = - TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, - - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT = 8, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_MASK = - 7 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_4 = - TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_8 = - TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_12 = - TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_16 = - TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_20 = - TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_24 = - TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_28 = - TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_32 = - TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, - - TEGRA_AUDIOCIF_EXPAND_ZERO = 0, - TEGRA_AUDIOCIF_EXPAND_ONE = 1, - TEGRA_AUDIOCIF_EXPAND_LFSR = 2, - - TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT = 6, - TEGRA_AUDIOCIF_CTRL_EXPAND_MASK = 3 << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, - TEGRA_AUDIOCIF_CTRL_EXPAND_ZERO = - TEGRA_AUDIOCIF_EXPAND_ZERO << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, - TEGRA_AUDIOCIF_CTRL_EXPAND_ONE = - TEGRA_AUDIOCIF_EXPAND_ONE << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, - TEGRA_AUDIOCIF_CTRL_EXPAND_LFSR = - TEGRA_AUDIOCIF_EXPAND_LFSR << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, - - TEGRA_AUDIOCIF_STEREO_CONV_CH0 = 0, - TEGRA_AUDIOCIF_STEREO_CONV_CH1 = 1, - TEGRA_AUDIOCIF_STEREO_CONV_AVG = 2, - - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT = 4, - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_MASK = - 3 << TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH0 = - TEGRA_AUDIOCIF_STEREO_CONV_CH0 << - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH1 = - TEGRA_AUDIOCIF_STEREO_CONV_CH1 << - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_AVG = - TEGRA_AUDIOCIF_STEREO_CONV_AVG << - TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, - - TEGRA_AUDIOCIF_CTRL_REPLICATE = 3, - - TEGRA_AUDIOCIF_DIRECTION_TX = 0, - TEGRA_AUDIOCIF_DIRECTION_RX = 1, - - TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT = 2, - TEGRA_AUDIOCIF_CTRL_DIRECTION_MASK = - 1 << TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, - TEGRA_AUDIOCIF_CTRL_DIRECTION_TX = - TEGRA_AUDIOCIF_DIRECTION_TX << - TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, - TEGRA_AUDIOCIF_CTRL_DIRECTION_RX = - TEGRA_AUDIOCIF_DIRECTION_RX << - TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, - - TEGRA_AUDIOCIF_TRUNCATE_ROUND = 0, - TEGRA_AUDIOCIF_TRUNCATE_CHOP = 1, - - TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT = 1, - TEGRA_AUDIOCIF_CTRL_TRUNCATE_MASK = - 1 << TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, - TEGRA_AUDIOCIF_CTRL_TRUNCATE_ROUND = - TEGRA_AUDIOCIF_TRUNCATE_ROUND << - TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, - TEGRA_AUDIOCIF_CTRL_TRUNCATE_CHOP = - TEGRA_AUDIOCIF_TRUNCATE_CHOP << - TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, - - TEGRA_AUDIOCIF_MONO_CONV_ZERO = 0, - TEGRA_AUDIOCIF_MONO_CONV_COPY = 1, - - TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT = 0, - TEGRA_AUDIOCIF_CTRL_MONO_CONV_MASK = - 1 << TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, - TEGRA_AUDIOCIF_CTRL_MONO_CONV_ZERO = - TEGRA_AUDIOCIF_MONO_CONV_ZERO << - TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, - TEGRA_AUDIOCIF_CTRL_MONO_CONV_COPY = - TEGRA_AUDIOCIF_MONO_CONV_COPY << - TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, - - /* Registers within TEGRA_AUDIO_CLUSTER_BASE */ - - TEGRA_AHUB_CHANNEL_CTRL = 0x0, - TEGRA_AHUB_CHANNEL_CTRL_STRIDE = 0x20, - TEGRA_AHUB_CHANNEL_CTRL_COUNT = 4, - TEGRA_AHUB_CHANNEL_CTRL_TX_EN = 1 << 31, - TEGRA_AHUB_CHANNEL_CTRL_RX_EN = 1 << 30, - TEGRA_AHUB_CHANNEL_CTRL_LOOPBACK = 1 << 29, - - TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT = 16, - TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US = 0xff, - TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK = - TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << - TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT, - - TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT = 8, - TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US = 0xff, - TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK = - TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << - TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT, - - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN = 1 << 6, - - TEGRA_PACK_8_4 = 2, - TEGRA_PACK_16 = 3, - - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT = 4, - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US = 3, - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK = - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_8_4 = - TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, - TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 = - TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, - - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_EN = 1 << 2, - - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT = 0, - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US = 3, - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK = - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_8_4 = - TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, - TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_16 = - TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, - - /* TEGRA_AHUB_CHANNEL_CLEAR */ - - TEGRA_AHUB_CHANNEL_CLEAR = 0x4, - TEGRA_AHUB_CHANNEL_CLEAR_STRIDE = 0x20, - TEGRA_AHUB_CHANNEL_CLEAR_COUNT = 4, - TEGRA_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET = 1 << 31, - TEGRA_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET = 1 << 30, - - TEGRA_AHUB_CHANNEL_STATUS = 0x8, - TEGRA_AHUB_CHANNEL_STATUS_STRIDE = 0x20, - TEGRA_AHUB_CHANNEL_STATUS_COUNT = 4, - TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT = 24, - TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US = 0xff, - TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK = - TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << - TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT, - TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT = 16, - TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US = 0xff, - TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK = - TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << - TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT, - TEGRA_AHUB_CHANNEL_STATUS_TX_TRIG = 1 << 1, - TEGRA_AHUB_CHANNEL_STATUS_RX_TRIG = 1 << 0, - - TEGRA_AHUB_CHANNEL_TXFIFO = 0xc, - TEGRA_AHUB_CHANNEL_TXFIFO_STRIDE = 0x20, - TEGRA_AHUB_CHANNEL_TXFIFO_COUNT = 4, - - TEGRA_AHUB_CHANNEL_RXFIFO = 0x10, - TEGRA_AHUB_CHANNEL_RXFIFO_STRIDE = 0x20, - TEGRA_AHUB_CHANNEL_RXFIFO_COUNT = 4, - - TEGRA_AHUB_CIF_TX_CTRL = 0x14, - TEGRA_AHUB_CIF_TX_CTRL_STRIDE = 0x20, - TEGRA_AHUB_CIF_TX_CTRL_COUNT = 4, - /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ - - TEGRA_AHUB_CIF_RX_CTRL = 0x18, - TEGRA_AHUB_CIF_RX_CTRL_STRIDE = 0x20, - TEGRA_AHUB_CIF_RX_CTRL_COUNT = 4, - /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ - - TEGRA_AHUB_CONFIG_LINK_CTRL = 0x80, - TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT = 28, - TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US = 0xf, - TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK = - TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << - TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT, - TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT = 16, - TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US = 0xfff, - TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK = - TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << - TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT, - TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT = 4, - TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US = 0xfff, - TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK = - TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << - TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT, - TEGRA_AHUB_CONFIG_LINK_CTRL_CG_EN = 1 << 2, - TEGRA_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR = 1 << 1, - TEGRA_AHUB_CONFIG_LINK_CTRL_SOFT_RESET = 1 << 0, - - TEGRA_AHUB_MISC_CTRL = 0x84, - TEGRA_AHUB_MISC_CTRL_AUDIO_ACTIVE = 1 << 31, - TEGRA_AHUB_MISC_CTRL_AUDIO_CG_EN = 1 << 8, - TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT = 0, - TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK = - 0x1f << TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT, - - TEGRA_AHUB_APBDMA_LIVE_STATUS = 0x88, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL = 1 << 31, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL = 1 << 30, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL = 1 << 29, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL = 1 << 28, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL = 1 << 27, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL = 1 << 26, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL = 1 << 25, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL = 1 << 24, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY = 1 << 23, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY = 1 << 22, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY = 1 << 21, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY = 1 << 20, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY = 1 << 19, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY = 1 << 18, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY = 1 << 17, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY = 1 << 16, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL = 1 << 15, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL = 1 << 14, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL = 1 << 13, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL = 1 << 12, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL = 1 << 11, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL = 1 << 10, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL = 1 << 9, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL = 1 << 8, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY = 1 << 7, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY = 1 << 6, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY = 1 << 5, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY = 1 << 4, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY = 1 << 3, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY = 1 << 2, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY = 1 << 1, - TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY = 1 << 0, - - TEGRA_AHUB_I2S_LIVE_STATUS = 0x8c, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL = 1 << 29, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL = 1 << 28, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL = 1 << 27, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL = 1 << 26, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL = 1 << 25, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL = 1 << 24, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL = 1 << 23, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL = 1 << 22, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL = 1 << 21, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL = 1 << 20, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED = 1 << 19, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED = 1 << 18, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED = 1 << 17, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED = 1 << 16, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED = 1 << 15, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED = 1 << 14, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED = 1 << 13, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED = 1 << 12, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED = 1 << 11, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED = 1 << 10, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY = 1 << 9, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY = 1 << 8, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY = 1 << 7, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY = 1 << 6, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY = 1 << 5, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY = 1 << 4, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY = 1 << 3, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY = 1 << 2, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY = 1 << 1, - TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY = 1 << 0, - - TEGRA_AHUB_DAM_LIVE_STATUS = 0x90, - TEGRA_AHUB_DAM_LIVE_STATUS_STRIDE = 0x8, - TEGRA_AHUB_DAM_LIVE_STATUS_COUNT = 3, - TEGRA_AHUB_DAM_LIVE_STATUS_TX_ENABLED = 1 << 26, - TEGRA_AHUB_DAM_LIVE_STATUS_RX1_ENABLED = 1 << 25, - TEGRA_AHUB_DAM_LIVE_STATUS_RX0_ENABLED = 1 << 24, - TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL = 1 << 15, - TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL = 1 << 9, - TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL = 1 << 8, - TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY = 1 << 7, - TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY = 1 << 1, - TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY = 1 << 0, - - TEGRA_AHUB_SPDIF_LIVE_STATUS = 0xa8, - TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED = 1 << 11, - TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED = 1 << 10, - TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED = 1 << 9, - TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED = 1 << 8, - TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL = 1 << 7, - TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL = 1 << 6, - TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL = 1 << 5, - TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL = 1 << 4, - TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY = 1 << 3, - TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY = 1 << 2, - TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY = 1 << 1, - TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY = 1 << 0, - - TEGRA_AHUB_I2S_INT_MASK = 0xb0, - TEGRA_AHUB_DAM_INT_MASK = 0xb4, - TEGRA_AHUB_SPDIF_INT_MASK = 0xbc, - TEGRA_AHUB_APBIF_INT_MASK = 0xc0, - TEGRA_AHUB_I2S_INT_STATUS = 0xc8, - TEGRA_AHUB_DAM_INT_STATUS = 0xcc, - TEGRA_AHUB_SPDIF_INT_STATUS = 0xd4, - TEGRA_AHUB_APBIF_INT_STATUS = 0xd8, - TEGRA_AHUB_I2S_INT_SOURCE = 0xe0, - TEGRA_AHUB_DAM_INT_SOURCE = 0xe4, - TEGRA_AHUB_SPDIF_INT_SOURCE = 0xec, - TEGRA_AHUB_APBIF_INT_SOURCE = 0xf0, - TEGRA_AHUB_I2S_INT_SET = 0xf8, - TEGRA_AHUB_DAM_INT_SET = 0xfc, - TEGRA_AHUB_SPDIF_INT_SET = 0x100, - TEGRA_AHUB_APBIF_INT_SET = 0x104, - - TEGRA_AHUB_AUDIO_RX = 0x0, - TEGRA_AHUB_AUDIO_RX_STRIDE = 0x4, - TEGRA_AHUB_AUDIO_RX_COUNT = 17, -}; - -#endif /* _TEGRA_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h deleted file mode 100644 index 5316bc4..0000000 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * NVIDIA Tegra I2C controller - * - * Copyright 2010-2011 NVIDIA Corporation - */ - -#ifndef _TEGRA_I2C_H_ -#define _TEGRA_I2C_H_ - -#include <asm/types.h> - -enum { - I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ - I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ -}; - -enum i2c_transaction_flags { - I2C_IS_WRITE = 0x1, /* for I2C write operation */ - I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ - I2C_USE_REPEATED_START = 0x4, /* for repeat start */ - I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ - I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ - I2C_NO_STOP = 0x20, -}; - -/* Contians the I2C transaction details */ -struct i2c_trans_info { - /* flags to indicate the transaction details */ - enum i2c_transaction_flags flags; - u32 address; /* I2C slave device address */ - u32 num_bytes; /* number of bytes to be transferred */ - /* - * Send/receive buffer. For the I2C send operation this buffer should - * be filled with the data to be sent to the slave device. For the I2C - * receive operation this buffer is filled with the data received from - * the slave device. - */ - u8 *buf; - int is_10bit_address; -}; - -struct i2c_control { - u32 tx_fifo; - u32 rx_fifo; - u32 packet_status; - u32 fifo_control; - u32 fifo_status; - u32 int_mask; - u32 int_status; -}; - -struct dvc_ctlr { - u32 ctrl1; /* 00: DVC_CTRL_REG1 */ - u32 ctrl2; /* 04: DVC_CTRL_REG2 */ - u32 ctrl3; /* 08: DVC_CTRL_REG3 */ - u32 status; /* 0C: DVC_STATUS_REG */ - u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ - u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ - u32 reserved_0[2]; /* 18: */ - u32 req; /* 20: DVC_REQ_REGISTER */ - u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ - u32 reserved_1[6]; /* 28: */ - u32 cnfg; /* 40: DVC_I2C_CNFG */ - u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ - u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ - u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ - u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ - u32 reserved_2[2]; /* 54: */ - u32 i2c_status; /* 5C: DVC_I2C_STATUS */ - struct i2c_control control; /* 60 ~ 78 */ -}; - -struct i2c_ctlr { - u32 cnfg; /* 00: I2C_I2C_CNFG */ - u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ - u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ - u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ - u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ - u32 reserved_0[2]; /* 14: */ - u32 status; /* 1C: I2C_I2C_STATUS */ - u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ - u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ - u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ - u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ - u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ - u32 reserved_1[2]; /* 34: */ - u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ - u32 reserved_2[4]; /* 40: */ - struct i2c_control control; /* 50 ~ 68 */ - u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ -}; - -/* bit fields definitions for IO Packet Header 1 format */ -#define PKT_HDR1_PROTOCOL_SHIFT 4 -#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) -#define PKT_HDR1_CTLR_ID_SHIFT 12 -#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) -#define PKT_HDR1_PKT_ID_SHIFT 16 -#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) -#define PROTOCOL_TYPE_I2C 1 - -/* bit fields definitions for IO Packet Header 2 format */ -#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 -#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) - -/* bit fields definitions for IO Packet Header 3 format */ -#define PKT_HDR3_READ_MODE_SHIFT 19 -#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) -#define PKT_HDR3_REPEAT_START_SHIFT 16 -#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT) -#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 -#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) - -#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 -#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ - (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) - -/* I2C_CNFG */ -#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 -#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) -#define I2C_CNFG_PACKET_MODE_SHIFT 10 -#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) - -/* I2C_SL_CNFG */ -#define I2C_SL_CNFG_NEWSL_SHIFT 2 -#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) - -/* I2C_FIFO_STATUS */ -#define TX_FIFO_FULL_CNT_SHIFT 0 -#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) -#define TX_FIFO_EMPTY_CNT_SHIFT 4 -#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) - -/* I2C_INTERRUPT_STATUS */ -#define I2C_INT_XFER_COMPLETE_SHIFT 7 -#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) -#define I2C_INT_NO_ACK_SHIFT 3 -#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) -#define I2C_INT_ARBITRATION_LOST_SHIFT 2 -#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) - -/* I2C_CLK_DIVISOR_REGISTER */ -#define CLK_DIV_STD_FAST_MODE 0x19 -#define CLK_DIV_HS_MODE 1 -#define CLK_MULT_STD_FAST_MODE 8 - -/** - * Returns the bus number of the DVC controller - * - * @return number of bus, or -1 if there is no DVC active - */ -int tegra_i2c_get_dvc_bus(struct udevice **busp); - -#endif /* _TEGRA_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2s.h b/arch/arm/include/asm/arch-tegra/tegra_i2s.h deleted file mode 100644 index 9319383..0000000 --- a/arch/arm/include/asm/arch-tegra/tegra_i2s.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * tegra_i2s.h - Definitions for Tegra124 I2S driver. - * Note, some structures (ex, CIF) are different in Tegra114. - * - * NVIDIA Tegra I2S controller - * Modified from dc tegra_regs.h - * - * Copyright 2018 Google LLC - * - * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA_I2S_H_ -#define _TEGRA_I2S_H_ - -struct i2s_ctlr { - u32 ctrl; /* I2S_CTRL_0, 0x00 */ - u32 timing; /* I2S_TIMING_0, 0x04 */ - u32 offset; /* I2S_OFFSET_0, 0x08 */ - u32 ch_ctrl; /* I2S_CH_CTRL_0, 0x0C */ - u32 slot_ctrl; /* I2S_SLOT_CTRL_0, 0x10 */ - u32 cif_tx_ctrl; /* I2S_CIF_TX_CTRL_0, 0x14 */ - u32 cif_rx_ctrl; /* I2S_CIF_RX_CTRL_0, 0x18 */ - u32 flowctl; /* I2S_FLOWCTL_0, 0x1C */ - u32 tx_step; /* I2S_TX_STEP_0, 0x20 */ - u32 flow_status; /* I2S_FLOW_STATUS_0, 0x24 */ - u32 flow_total; /* I2S_FLOW_TOTAL_0, 0x28 */ - u32 flow_over; /* I2S_FLOW_OVER_0, 0x2C */ - u32 flow_under; /* I2S_FLOW_UNDER_0, 0x30 */ - u32 reserved[12]; /* RESERVED, 0x34 - 0x60 */ - u32 slot_ctrl2; /* I2S_SLOT_CTRL2_0, 0x64*/ -}; - -enum { - I2S_CTRL_XFER_EN_TX = 1 << 31, - I2S_CTRL_XFER_EN_RX = 1 << 30, - I2S_CTRL_CG_EN = 1 << 29, - I2S_CTRL_SOFT_RESET = 1 << 28, - I2S_CTRL_TX_FLOWCTL_EN = 1 << 27, - - I2S_CTRL_OBS_SEL_SHIFT = 24, - I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT, - - I2S_FRAME_FORMAT_LRCK = 0, - I2S_FRAME_FORMAT_FSYNC = 1, - - I2S_CTRL_FRAME_FORMAT_SHIFT = 12, - I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT, - I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK << - I2S_CTRL_FRAME_FORMAT_SHIFT, - I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC << - I2S_CTRL_FRAME_FORMAT_SHIFT, - - I2S_CTRL_MASTER_ENABLE = 1 << 10, - - I2S_LRCK_LEFT_LOW = 0, - I2S_LRCK_RIGHT_LOW = 1, - - I2S_CTRL_LRCK_SHIFT = 9, - I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT, - I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW << I2S_CTRL_LRCK_SHIFT, - I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT, - - I2S_CTRL_LPBK_ENABLE = 1 << 8, - - I2S_BIT_CODE_LINEAR = 0, - I2S_BIT_CODE_ULAW = 1, - I2S_BIT_CODE_ALAW = 2, - - I2S_CTRL_BIT_CODE_SHIFT = 4, - I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT, - I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR << - I2S_CTRL_BIT_CODE_SHIFT, - I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT, - I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT, - - I2S_BITS_8 = 1, - I2S_BITS_12 = 2, - I2S_BITS_16 = 3, - I2S_BITS_20 = 4, - I2S_BITS_24 = 5, - I2S_BITS_28 = 6, - I2S_BITS_32 = 7, - - /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */ - I2S_CTRL_BIT_SIZE_SHIFT = 0, - I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT, - I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8 << I2S_CTRL_BIT_SIZE_SHIFT, - I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT, - I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT, - I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT, - I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT, - I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT, - I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT, - - I2S_TIMING_NON_SYM_ENABLE = 1 << 12, - I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0, - I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff, - I2S_TIMING_CHANNEL_BIT_COUNT_MASK = - I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << - I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT, - - I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16, - I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff, - I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US << - I2S_OFFSET_RX_DATA_OFFSET_SHIFT, - I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0, - I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff, - I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US << - I2S_OFFSET_TX_DATA_OFFSET_SHIFT, - - /* FSYNC width - 1 in bit clocks */ - I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24, - I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff, - I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << - I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, - - I2S_HIGHZ_NO = 0, - I2S_HIGHZ_YES = 1, - I2S_HIGHZ_ON_HALF_BIT_CLK = 2, - - I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12, - I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, - I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO << - I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, - I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES << - I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, - I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK << - I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, - - I2S_MSB_FIRST = 0, - I2S_LSB_FIRST = 1, - - I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10, - I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, - I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST << - I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, - I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST << - I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, - I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9, - I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, - I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST << - I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, - I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST << - I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, - - I2S_POS_EDGE = 0, - I2S_NEG_EDGE = 1, - - I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8, - I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT, - I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE << - I2S_CH_CTRL_EGDE_CTRL_SHIFT, - I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE << - I2S_CH_CTRL_EGDE_CTRL_SHIFT, - - /* Sample size is # bits from BIT_SIZE minus this field */ - I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4, - I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7, - I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US << - I2S_CH_CTRL_RX_MASK_BITS_SHIFT, - - I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0, - I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7, - I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US << - I2S_CH_CTRL_TX_MASK_BITS_SHIFT, - - /* Number of slots in frame, minus 1 */ - I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16, - I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7, - I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << - I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT, - - /* TDM mode slot enable bitmask */ - I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8, - I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK = - 0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT, - - I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0, - I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff << - I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT, - - I2S_FILTER_LINEAR = 0, - I2S_FILTER_QUAD = 1, - - I2S_FLOWCTL_FILTER_SHIFT = 31, - I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT, - I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR << - I2S_FLOWCTL_FILTER_SHIFT, - I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT, - - I2S_TX_STEP_SHIFT = 0, - I2S_TX_STEP_MASK_US = 0xffff, - I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT, - - I2S_FLOW_STATUS_UNDERFLOW = 1 << 31, - I2S_FLOW_STATUS_OVERFLOW = 1 << 30, - I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4, - I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3, - I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2, - I2S_FLOW_STATUS_COUNTER_EN = 1 << 1, - I2S_FLOW_STATUS_MONITOR_EN = 1 << 0, -}; - -#endif /* _TEGRA_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h deleted file mode 100644 index a2b6f63..0000000 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Portions Copyright (C) 2011-2012 NVIDIA Corporation - */ - -#ifndef __TEGRA_MMC_H_ -#define __TEGRA_MMC_H_ - -#include <common.h> -#include <clk.h> -#include <reset.h> -#include <fdtdec.h> -#include <asm/gpio.h> - -/* for mmc_config definition */ -#include <mmc.h> - -#ifndef __ASSEMBLY__ -struct tegra_mmc { - unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ - unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ - unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ - unsigned int argument; /* _ARGUMENT_0 */ - unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ - unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ - unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ - unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ - unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ - unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ - unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ - unsigned int prnsts; /* _PRESENT_STATE_0 */ - unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ - unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ - unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ - unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ - unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ - unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ - unsigned char swrst; /* _SW_RESET_ 31:24 */ - unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ - unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ - unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ - unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ - unsigned char res1[2]; /* _RESERVED 31:16 */ - unsigned int capareg; /* _CAPABILITIES_0 */ - unsigned char res2[4]; /* RESERVED, offset 44h-47h */ - unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ - unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ - unsigned short setacmd12err; /* offset 50h */ - unsigned short setinterr; /* offset 52h */ - unsigned char admaerr; /* offset 54h */ - unsigned char res4[3]; /* RESERVED, offset 55h-57h */ - unsigned long admaaddr; /* offset 58h-5Fh */ - unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ - unsigned short slotintstatus; /* offset FCh */ - unsigned short hcver; /* HOST Version */ - unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ - unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ - unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ - unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ - unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ - unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ - unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ - unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ - unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ - unsigned int res6[47]; /* 0x124 ~ 0x1DC */ - unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ - unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ - unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ - unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ -}; - -#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) -#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) -#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) -#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) - -#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) - -#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) -#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) -#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) -#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) -#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) - -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) - -#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) -#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) -#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) - -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) - -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) -#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) - -#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 -#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) - -#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17) - -#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) - -#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) -#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) - -#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) - -#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) - -/* SDMMC1/3 settings from section 24.6 of T30 TRM */ -#define MEMCOMP_PADCTRL_VREF 7 -#define AUTO_CAL_ENABLED (1 << 29) -#define AUTO_CAL_PD_OFFSET (0x70 << 8) -#define AUTO_CAL_PU_OFFSET (0x62 << 0) - -#endif /* __ASSEMBLY__ */ -#endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/timer.h b/arch/arm/include/asm/arch-tegra/timer.h deleted file mode 100644 index 1c4deca..0000000 --- a/arch/arm/include/asm/arch-tegra/timer.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -/* Tegra20 timer functions */ - -#ifndef _TEGRA_TIMER_H -#define _TEGRA_TIMER_H - -/* returns the current monotonic timer value in microseconds */ -unsigned long timer_get_us(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra/uart.h b/arch/arm/include/asm/arch-tegra/uart.h deleted file mode 100644 index 24f0bdd..0000000 --- a/arch/arm/include/asm/arch-tegra/uart.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _UART_H_ -#define _UART_H_ - -/* UART registers */ -struct uart_ctlr { - uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ - uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ - uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ - uint uart_lcr; /* UART_LCR_0, offset 0C */ - uint uart_mcr; /* UART_MCR_0, offset 10 */ - uint uart_lsr; /* UART_LSR_0, offset 14 */ - uint uart_msr; /* UART_MSR_0, offset 18 */ - uint uart_spr; /* UART_SPR_0, offset 1C */ - uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ - uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ - uint uart_asr; /* UART_ASR_0, offset 3C */ -}; - -#define NVRM_PLLP_FIXED_FREQ_KHZ 216000 -#define NV_DEFAULT_DEBUG_BAUD 115200 - -#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ - -#endif /* UART_H */ diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h deleted file mode 100644 index 6e6ea14..0000000 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ /dev/null @@ -1,360 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - */ - -#ifndef _TEGRA_USB_H_ -#define _TEGRA_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - -#ifdef CONFIG_TEGRA20 - /* 0x130 */ - uint reserved4_2[4]; - - /* 0x140 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x150 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint async_tt_sts; - - /* 0x160 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; /* is this port_sc1 on some controllers? */ - uint icusb_ctrl; - - /* 0x170 */ - uint ulpi_viewport; - uint reserved7; - uint endpt_nak; - uint endpt_nak_enable; - - /* 0x180 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x1a0 */ - uint reserved9; - uint otgsc; - uint usb_mode; - uint endpt_setup_stat; - - /* 0x1b0 */ - uint reserved10[20]; - - /* 0x200 */ - uint reserved11[0x80]; -#else - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7[3]; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; -#endif - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - -#ifdef CONFIG_TEGRA20 - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[4]; - - /* 0x424 */ - uint ulpi_timing_ctrl_0; - uint ulpi_timing_ctrl_1; - uint reserved13[53]; -#else - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; -#endif - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB1_LEGACY_CTRL */ -#define USB1_NO_LEGACY_MODE 1 - -#define VBUS_SENSE_CTL_SHIFT 1 -#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) -#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 -#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 -#define VBUS_SENSE_CTL_AB_SESS_VLD 2 -#define VBUS_SENSE_CTL_A_SESS_VLD 3 - -/* USBx_IF_USB_SUSP_CTRL_0 */ -#define UTMIP_PHY_ENB (1 << 12) -#define UTMIP_RESET (1 << 11) -#define USB_PHY_CLK_VALID (1 << 7) -#define USB_SUSP_CLR (1 << 5) - -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) -/* USB2_IF_USB_SUSP_CTRL_0 */ -#define ULPI_PHY_ENB (1 << 13) - -/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) -#endif - -/* USBx_UTMIP_MISC_CFG0 */ -#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) - -/* USBx_UTMIP_MISC_CFG1 */ -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) - -/* - * Tegra 3 and later: Moved to Clock and Reset register space, see - * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 - */ -#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 -#define UTMIP_PLLU_STABLE_COUNT_MASK \ - (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) -/* - * Tegra 3 and later: Moved to Clock and Reset register space, see - * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 - */ -#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 -#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) - -/* USBx_UTMIP_PLL_CFG1_0 */ -/* Tegra 3 and later: Moved to Clock and Reset register space */ -#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 -#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) -#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 -#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff - -/* USBx_UTMIP_BIAS_CFG0_0 */ -#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) -#define UTMIP_OTGPD (1 << 11) -#define UTMIP_BIASPD (1 << 10) -#define UTMIP_HSDISCON_LEVEL_SHIFT 2 -#define UTMIP_HSDISCON_LEVEL_MASK \ - (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) -#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 -#define UTMIP_HSSQUELCH_LEVEL_MASK \ - (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) - -/* USBx_UTMIP_BIAS_CFG1_0 */ -#define UTMIP_FORCE_PDTRK_POWERDOWN 1 -#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8 -#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \ - (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT) -#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 -#define UTMIP_BIAS_PDTRK_COUNT_MASK \ - (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) - -/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ -#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 -#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff - -/* USBx_UTMIP_TX_CFG0_0 */ -#define UTMIP_FS_PREAMBLE_J (1 << 19) - -/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ -#define UTMIP_PD_CHRG 1 - -/* USBx_UTMIP_SPARE_CFG0_0 */ -#define FUSE_SETUP_SEL (1 << 3) - -/* USBx_UTMIP_HSRX_CFG0_0 */ -#define UTMIP_IDLE_WAIT_SHIFT 15 -#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) -#define UTMIP_ELASTIC_LIMIT_SHIFT 10 -#define UTMIP_ELASTIC_LIMIT_MASK \ - (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) - -/* USBx_UTMIP_HSRX_CFG1_0 */ -#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 -#define UTMIP_HS_SYNC_START_DLY_MASK \ - (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) - -/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ -#define IC_ENB1 (1 << 3) - -#ifdef CONFIG_TEGRA20 -/* PORTSC1, USB1 */ -#define PTS1_SHIFT 31 -#define PTS1_MASK (1 << PTS1_SHIFT) -#define STS1 (1 << 30) - -/* PORTSC, USB2, USB3 */ -#define PTS_SHIFT 30 -#define PTS_MASK (3U << PTS_SHIFT) -#define STS (1 << 29) -#else -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) -#define STS (1 << 28) -#endif - -#define PTS_UTMI 0 -#define PTS_RESERVED 1 -#define PTS_ULPI 2 -#define PTS_ICUSB_SER 3 -#define PTS_HSIC 4 - -/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ -#define WKOC (1 << 22) -#define WKDS (1 << 21) -#define WKCN (1 << 20) - -/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) -#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) -#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) -#define UTMIP_XCVR_LSBIAS_SE (1 << 21) -#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 -#define UTMIP_XCVR_HSSLEW_MSB_MASK \ - (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 -#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_SHIFT 0 -#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) - -/* USBx_UTMIP_XCVR_CFG1_0 */ -#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 -#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ - (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) -#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) - -/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ -#define VBUS_VLD_STS (1 << 26) -#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) -#define VBUS_B_SESS_VLD_SW_EN (1 << 11) - -/* Setup USB on the board */ -int usb_process_devicetree(const void *blob); - -#endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h deleted file mode 100644 index 3f02073..0000000 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _WARM_BOOT_H_ -#define _WARM_BOOT_H_ - -#define STRAP_OPT_A_RAM_CODE_SHIFT 4 -#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) - -/* Defines the supported operating modes */ -enum fuse_operating_mode { - MODE_PRODUCTION = 3, - MODE_UNDEFINED, -}; - -/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ -enum { - HASH_LENGTH = 4 -}; - -/* Defines the storage for a hash value (128 bits) */ -struct hash { - u32 hash[HASH_LENGTH]; -}; - -/* - * Defines the code header information for the boot rom. - * - * The code immediately follows the code header. - * - * Note that the code header needs to be 16 bytes aligned to preserve - * the alignment of relevant data for hash and decryption computations without - * requiring extra copies to temporary memory areas. - */ -struct wb_header { - u32 length_insecure; /* length of the code header */ - u32 reserved[3]; - struct hash hash; /* hash of header+code, starts next field*/ - struct hash random_aes_block; /* a data block to aid security. */ - u32 length_secure; /* length of the code header */ - u32 destination; /* destination address to put the wb code */ - u32 entry_point; /* execution address of the wb code */ - u32 code_length; /* length of the code */ -}; - -/* - * The warm boot code needs direct access to these registers since it runs in - * SRAM and cannot call other U-Boot code. - */ -union osc_ctrl_reg { - struct { - u32 xoe:1; - u32 xobp:1; - u32 reserved0:2; - u32 xofs:6; - u32 reserved1:2; - u32 xods:5; - u32 reserved2:3; - u32 oscfi_spare:8; - u32 pll_ref_div:2; - u32 osc_freq:2; - }; - u32 word; -}; - -union pllx_base_reg { - struct { - u32 divm:5; - u32 reserved0:3; - u32 divn:10; - u32 reserved1:2; - u32 divp:3; - u32 reserved2:4; - u32 lock:1; - u32 reserved3:1; - u32 ref_dis:1; - u32 enable:1; - u32 bypass:1; - }; - u32 word; -}; - -union pllx_misc_reg { - struct { - u32 vcocon:4; - u32 lfcon:4; - u32 cpcon:4; - u32 lock_sel:6; - u32 reserved0:1; - u32 lock_enable:1; - u32 reserved1:1; - u32 dccon:1; - u32 pts:2; - u32 reserved2:6; - u32 out1_div_byp:1; - u32 out1_inv_clk:1; - }; - u32 word; -}; - -/* - * TODO: This register is not documented in the TRM yet. We could move this - * into the EMC and give it a proper interface, but not while it is - * undocumented. - */ -union scratch3_reg { - struct { - u32 pllx_base_divm:5; - u32 pllx_base_divn:10; - u32 pllx_base_divp:3; - u32 pllx_misc_lfcon:4; - u32 pllx_misc_cpcon:4; - }; - u32 word; -}; - - -/** - * Save warmboot memory settings for a later resume - * - * @return 0 if ok, -1 on error - */ -int warmboot_save_sdram_params(void); - -int warmboot_prepare_code(u32 seg_address, u32 seg_length); -int sign_data_block(u8 *source, u32 length, u8 *signature); -void wb_start(void); /* Start of WB assembly code */ -void wb_end(void); /* End of WB assembly code */ - -#endif diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h deleted file mode 100644 index deccdf4..0000000 --- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _TEGRA_XUSB_PADCTL_H_ -#define _TEGRA_XUSB_PADCTL_H_ - -struct tegra_xusb_phy; - -/** - * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY - * @type: the type of PHY to obtain - * - * The type of PHY varies between SoC generations. Typically there are XUSB, - * PCIe and SATA PHYs, though not all generations support all of them. The - * value of type can usually be directly parsed from a device tree. - * - * Return: a pointer to the PHY or NULL if no such PHY exists - */ -struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); - -void tegra_xusb_padctl_init(void); -int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); -int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); -int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); -int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy); - -#endif diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h deleted file mode 100644 index 9b95b33..0000000 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ /dev/null @@ -1,392 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra114 clock PLL tables */ - -#ifndef _TEGRA114_CLOCK_TABLES_H_ -#define _TEGRA114_CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - CLOCK_ID_CLK_M, - - CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 (DEVICES_L) */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_COP, - PERIPH_ID_TRIGSYS, - PERIPH_ID_RESERVED3, - PERIPH_ID_RTC, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_RESERVED16, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_RESERVED24, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_I2S0, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 (DEVICES_H) */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_RESERVED43, - PERIPH_ID_SBC2, - PERIPH_ID_RESERVED45, - PERIPH_ID_SBC3, - PERIPH_ID_I2C5, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_DTV, - - /* 80 */ - PERIPH_ID_NANDSPEED, - PERIPH_ID_I2CSLOW, - PERIPH_ID_DSIB, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_RESERVED89, - PERIPH_ID_MDOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUSOUT, - PERIPH_ID_RESERVED93, - PERIPH_ID_RESERVED94, - PERIPH_ID_RESERVED95, - - PERIPH_ID_VW_FIRST, - /* V word: 31:0 */ - PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, - PERIPH_ID_CPULP, - PERIPH_ID_3D2, - PERIPH_ID_MSELECT, - PERIPH_ID_TSENSOR, - PERIPH_ID_I2S3, - PERIPH_ID_I2S4, - PERIPH_ID_I2C4, - - /* 104 */ - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - PERIPH_ID_AUDIO, - PERIPH_ID_APBIF, - PERIPH_ID_DAM0, - PERIPH_ID_DAM1, - PERIPH_ID_DAM2, - PERIPH_ID_HDA2CODEC2X, - - /* 112 */ - PERIPH_ID_ATOMICS, - PERIPH_ID_EX_RESERVED17, - PERIPH_ID_EX_RESERVED18, - PERIPH_ID_EX_RESERVED19, - PERIPH_ID_EX_RESERVED20, - PERIPH_ID_EX_RESERVED21, - PERIPH_ID_EX_RESERVED22, - PERIPH_ID_ACTMON, - - /* 120 */ - PERIPH_ID_EX_RESERVED24, - PERIPH_ID_EX_RESERVED25, - PERIPH_ID_EX_RESERVED26, - PERIPH_ID_EX_RESERVED27, - PERIPH_ID_SATA, - PERIPH_ID_HDA, - PERIPH_ID_EX_RESERVED30, - PERIPH_ID_EX_RESERVED31, - - /* W word: 31:0 */ - PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_RESERVED1_SATACOLD, - PERIPH_ID_RESERVED2_PCIERX0, - PERIPH_ID_RESERVED3_PCIERX1, - PERIPH_ID_RESERVED4_PCIERX2, - PERIPH_ID_RESERVED5_PCIERX3, - PERIPH_ID_RESERVED6_PCIERX4, - PERIPH_ID_RESERVED7_PCIERX5, - - /* 136 */ - PERIPH_ID_CEC, - PERIPH_ID_PCIE2_IOBIST, - PERIPH_ID_EMC_IOBIST, - PERIPH_ID_HDMI_IOBIST, - PERIPH_ID_SATA_IOBIST, - PERIPH_ID_MIPI_IOBIST, - PERIPH_ID_EMC1_IOBIST, - PERIPH_ID_XUSB, - - /* 144 */ - PERIPH_ID_CILAB, - PERIPH_ID_CILCD, - PERIPH_ID_CILE, - PERIPH_ID_DSIA_LP, - PERIPH_ID_DSIB_LP, - PERIPH_ID_RESERVED21_ENTROPY, - PERIPH_ID_RESERVED22_W, - PERIPH_ID_RESERVED23_W, - - /* 152 */ - PERIPH_ID_RESERVED24_W, - PERIPH_ID_AMX0, - PERIPH_ID_ADX0, - PERIPH_ID_DVFS, - PERIPH_ID_XUSB_SS, - PERIPH_ID_EMC_DLL, - PERIPH_ID_MC1, - PERIPH_ID_EMC1, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid - * confusion bewteen PERIPH_ID_... and PERIPHC_... - * - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be - * confusing. - */ -enum periphc_internal_id { - /* 0x00 */ - PERIPHC_I2S1, - PERIPHC_I2S2, - PERIPHC_SPDIF_OUT, - PERIPHC_SPDIF_IN, - PERIPHC_PWM, - PERIPHC_05h, - PERIPHC_SBC2, - PERIPHC_SBC3, - - /* 0x08 */ - PERIPHC_08h, - PERIPHC_I2C1, - PERIPHC_I2C5, - PERIPHC_0bh, - PERIPHC_0ch, - PERIPHC_SBC1, - PERIPHC_DISP1, - PERIPHC_DISP2, - - /* 0x10 */ - PERIPHC_CVE, - PERIPHC_11h, - PERIPHC_VI, - PERIPHC_13h, - PERIPHC_SDMMC1, - PERIPHC_SDMMC2, - PERIPHC_G3D, - PERIPHC_G2D, - - /* 0x18 */ - PERIPHC_NDFLASH, - PERIPHC_SDMMC4, - PERIPHC_VFIR, - PERIPHC_EPP, - PERIPHC_MPE, - PERIPHC_MIPI, - PERIPHC_UART1, - PERIPHC_UART2, - - /* 0x20 */ - PERIPHC_HOST1X, - PERIPHC_21h, - PERIPHC_TVO, - PERIPHC_HDMI, - PERIPHC_24h, - PERIPHC_TVDAC, - PERIPHC_I2C2, - PERIPHC_EMC, - - /* 0x28 */ - PERIPHC_UART3, - PERIPHC_29h, - PERIPHC_VI_SENSOR, - PERIPHC_2bh, - PERIPHC_2ch, - PERIPHC_SBC4, - PERIPHC_I2C3, - PERIPHC_SDMMC3, - - /* 0x30 */ - PERIPHC_UART4, - PERIPHC_UART5, - PERIPHC_VDE, - PERIPHC_OWR, - PERIPHC_NOR, - PERIPHC_CSITE, - PERIPHC_I2S0, - PERIPHC_37h, - - PERIPHC_VW_FIRST, - /* 0x38 */ - PERIPHC_G3D2 = PERIPHC_VW_FIRST, - PERIPHC_MSELECT, - PERIPHC_TSENSOR, - PERIPHC_I2S3, - PERIPHC_I2S4, - PERIPHC_I2C4, - PERIPHC_SBC5, - PERIPHC_SBC6, - - /* 0x40 */ - PERIPHC_AUDIO, - PERIPHC_41h, - PERIPHC_DAM0, - PERIPHC_DAM1, - PERIPHC_DAM2, - PERIPHC_HDA2CODEC2X, - PERIPHC_ACTMON, - PERIPHC_EXTPERIPH1, - - /* 0x48 */ - PERIPHC_EXTPERIPH2, - PERIPHC_EXTPERIPH3, - PERIPHC_NANDSPEED, - PERIPHC_I2CSLOW, - PERIPHC_SYS, - PERIPHC_SPEEDO, - PERIPHC_4eh, - PERIPHC_4fh, - - /* 0x50 */ - PERIPHC_50h, - PERIPHC_51h, - PERIPHC_52h, - PERIPHC_53h, - PERIPHC_SATAOOB, - PERIPHC_SATA, - PERIPHC_HDA, - - PERIPHC_COUNT, - - PERIPHC_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ -#define PERIPH_REG(id) \ - (id < PERIPH_ID_VW_FIRST) ? \ - ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _TEGRA114_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h deleted file mode 100644 index 84e1da4..0000000 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra114 clock control functions */ - -#ifndef _TEGRA114_CLOCK_H_ -#define _TEGRA114_CLOCK_H_ - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) - -/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ -#define PLLC_IDDQ (1 << 26) - -#endif /* _TEGRA114_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h deleted file mode 100644 index 4f0fc3b..0000000 --- a/arch/arm/include/asm/arch-tegra114/flow.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_FLOW_H_ -#define _TEGRA114_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 xrq_events; - u32 halt_cpu1_events; - u32 cpu1_csr; - u32 halt_cpu2_events; - u32 cpu2_csr; - u32 halt_cpu3_events; - u32 cpu3_csr; - u32 cluster_control; -}; - -#endif /* _TEGRA114_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h deleted file mode 100644 index f3b1bd4..0000000 --- a/arch/arm/include/asm/arch-tegra114/funcmux.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra114 high-level function multiplexing */ - -#ifndef _TEGRA114_FUNCMUX_H_ -#define _TEGRA114_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART4_GMI = 0, -}; -#endif /* _TEGRA114_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h deleted file mode 100644 index 69b35a1..0000000 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_GP_PADCTRL_H_ -#define _TEGRA114_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - -#endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h deleted file mode 100644 index 4f084e2..0000000 --- a/arch/arm/include/asm/arch-tegra114/gpio.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_GPIO_H_ -#define _TEGRA114_GPIO_H_ - -/* - * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> -#include <asm/arch-tegra30/gpio.h> - -#endif /* _TEGRA114_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/include/asm/arch-tegra114/mc.h deleted file mode 100644 index 3930bab..0000000 --- a/arch/arm/include/asm/arch-tegra114/mc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA114_MC_H_ -#define _TEGRA114_MC_H_ - -/** - * Defines the memory controller registers we need/care about - */ -struct mc_ctlr { - u32 reserved0[4]; /* offset 0x00 - 0x0C */ - u32 mc_smmu_config; /* offset 0x10 */ - u32 mc_smmu_tlb_config; /* offset 0x14 */ - u32 mc_smmu_ptc_config; /* offset 0x18 */ - u32 mc_smmu_ptb_asid; /* offset 0x1C */ - u32 mc_smmu_ptb_data; /* offset 0x20 */ - u32 reserved1[3]; /* offset 0x24 - 0x2C */ - u32 mc_smmu_tlb_flush; /* offset 0x30 */ - u32 mc_smmu_ptc_flush; /* offset 0x34 */ - u32 reserved2[6]; /* offset 0x38 - 0x4C */ - u32 mc_emem_cfg; /* offset 0x50 */ - u32 mc_emem_adr_cfg; /* offset 0x54 */ - u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ - u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ - u32 reserved3[12]; /* offset 0x60 - 0x8C */ - u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ - u32 reserved4[338]; /* offset 0x100 - 0x644 */ - u32 mc_video_protect_bom; /* offset 0x648 */ - u32 mc_video_protect_size_mb; /* offset 0x64c */ - u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ -}; - -#endif /* _TEGRA114_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h deleted file mode 100644 index 414b22e..0000000 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ /dev/null @@ -1,328 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_PINMUX_H_ -#define _TEGRA114_PINMUX_H_ - -enum pmux_pingrp { - PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_PINGRP_ULPI_DATA4_PO5, - PMUX_PINGRP_ULPI_DATA5_PO6, - PMUX_PINGRP_ULPI_DATA6_PO7, - PMUX_PINGRP_ULPI_DATA7_PO0, - PMUX_PINGRP_ULPI_CLK_PY0, - PMUX_PINGRP_ULPI_DIR_PY1, - PMUX_PINGRP_ULPI_NXT_PY2, - PMUX_PINGRP_ULPI_STP_PY3, - PMUX_PINGRP_DAP3_FS_PP0, - PMUX_PINGRP_DAP3_DIN_PP1, - PMUX_PINGRP_DAP3_DOUT_PP2, - PMUX_PINGRP_DAP3_SCLK_PP3, - PMUX_PINGRP_PV0, - PMUX_PINGRP_PV1, - PMUX_PINGRP_SDMMC1_CLK_PZ0, - PMUX_PINGRP_SDMMC1_CMD_PZ1, - PMUX_PINGRP_SDMMC1_DAT3_PY4, - PMUX_PINGRP_SDMMC1_DAT2_PY5, - PMUX_PINGRP_SDMMC1_DAT1_PY6, - PMUX_PINGRP_SDMMC1_DAT0_PY7, - PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), - PMUX_PINGRP_CLK2_REQ_PCC5, - PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), - PMUX_PINGRP_DDC_SCL_PV4, - PMUX_PINGRP_DDC_SDA_PV5, - PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), - PMUX_PINGRP_UART2_TXD_PC2, - PMUX_PINGRP_UART2_RTS_N_PJ6, - PMUX_PINGRP_UART2_CTS_N_PJ5, - PMUX_PINGRP_UART3_TXD_PW6, - PMUX_PINGRP_UART3_RXD_PW7, - PMUX_PINGRP_UART3_CTS_N_PA1, - PMUX_PINGRP_UART3_RTS_N_PC0, - PMUX_PINGRP_PU0, - PMUX_PINGRP_PU1, - PMUX_PINGRP_PU2, - PMUX_PINGRP_PU3, - PMUX_PINGRP_PU4, - PMUX_PINGRP_PU5, - PMUX_PINGRP_PU6, - PMUX_PINGRP_GEN1_I2C_SDA_PC5, - PMUX_PINGRP_GEN1_I2C_SCL_PC4, - PMUX_PINGRP_DAP4_FS_PP4, - PMUX_PINGRP_DAP4_DIN_PP5, - PMUX_PINGRP_DAP4_DOUT_PP6, - PMUX_PINGRP_DAP4_SCLK_PP7, - PMUX_PINGRP_CLK3_OUT_PEE0, - PMUX_PINGRP_CLK3_REQ_PEE1, - PMUX_PINGRP_GMI_WP_N_PC7, - PMUX_PINGRP_GMI_IORDY_PI5, - PMUX_PINGRP_GMI_WAIT_PI7, - PMUX_PINGRP_GMI_ADV_N_PK0, - PMUX_PINGRP_GMI_CLK_PK1, - PMUX_PINGRP_GMI_CS0_N_PJ0, - PMUX_PINGRP_GMI_CS1_N_PJ2, - PMUX_PINGRP_GMI_CS2_N_PK3, - PMUX_PINGRP_GMI_CS3_N_PK4, - PMUX_PINGRP_GMI_CS4_N_PK2, - PMUX_PINGRP_GMI_CS6_N_PI3, - PMUX_PINGRP_GMI_CS7_N_PI6, - PMUX_PINGRP_GMI_AD0_PG0, - PMUX_PINGRP_GMI_AD1_PG1, - PMUX_PINGRP_GMI_AD2_PG2, - PMUX_PINGRP_GMI_AD3_PG3, - PMUX_PINGRP_GMI_AD4_PG4, - PMUX_PINGRP_GMI_AD5_PG5, - PMUX_PINGRP_GMI_AD6_PG6, - PMUX_PINGRP_GMI_AD7_PG7, - PMUX_PINGRP_GMI_AD8_PH0, - PMUX_PINGRP_GMI_AD9_PH1, - PMUX_PINGRP_GMI_AD10_PH2, - PMUX_PINGRP_GMI_AD11_PH3, - PMUX_PINGRP_GMI_AD12_PH4, - PMUX_PINGRP_GMI_AD13_PH5, - PMUX_PINGRP_GMI_AD14_PH6, - PMUX_PINGRP_GMI_AD15_PH7, - PMUX_PINGRP_GMI_A16_PJ7, - PMUX_PINGRP_GMI_A17_PB0, - PMUX_PINGRP_GMI_A18_PB1, - PMUX_PINGRP_GMI_A19_PK7, - PMUX_PINGRP_GMI_WR_N_PI0, - PMUX_PINGRP_GMI_OE_N_PI1, - PMUX_PINGRP_GMI_DQS_P_PJ3, - PMUX_PINGRP_GMI_RST_N_PI4, - PMUX_PINGRP_GEN2_I2C_SCL_PT5, - PMUX_PINGRP_GEN2_I2C_SDA_PT6, - PMUX_PINGRP_SDMMC4_CLK_PCC4, - PMUX_PINGRP_SDMMC4_CMD_PT7, - PMUX_PINGRP_SDMMC4_DAT0_PAA0, - PMUX_PINGRP_SDMMC4_DAT1_PAA1, - PMUX_PINGRP_SDMMC4_DAT2_PAA2, - PMUX_PINGRP_SDMMC4_DAT3_PAA3, - PMUX_PINGRP_SDMMC4_DAT4_PAA4, - PMUX_PINGRP_SDMMC4_DAT5_PAA5, - PMUX_PINGRP_SDMMC4_DAT6_PAA6, - PMUX_PINGRP_SDMMC4_DAT7_PAA7, - PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), - PMUX_PINGRP_PCC1, - PMUX_PINGRP_PBB0, - PMUX_PINGRP_CAM_I2C_SCL_PBB1, - PMUX_PINGRP_CAM_I2C_SDA_PBB2, - PMUX_PINGRP_PBB3, - PMUX_PINGRP_PBB4, - PMUX_PINGRP_PBB5, - PMUX_PINGRP_PBB6, - PMUX_PINGRP_PBB7, - PMUX_PINGRP_PCC2, - PMUX_PINGRP_JTAG_RTCK, - PMUX_PINGRP_PWR_I2C_SCL_PZ6, - PMUX_PINGRP_PWR_I2C_SDA_PZ7, - PMUX_PINGRP_KB_ROW0_PR0, - PMUX_PINGRP_KB_ROW1_PR1, - PMUX_PINGRP_KB_ROW2_PR2, - PMUX_PINGRP_KB_ROW3_PR3, - PMUX_PINGRP_KB_ROW4_PR4, - PMUX_PINGRP_KB_ROW5_PR5, - PMUX_PINGRP_KB_ROW6_PR6, - PMUX_PINGRP_KB_ROW7_PR7, - PMUX_PINGRP_KB_ROW8_PS0, - PMUX_PINGRP_KB_ROW9_PS1, - PMUX_PINGRP_KB_ROW10_PS2, - PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4), - PMUX_PINGRP_KB_COL1_PQ1, - PMUX_PINGRP_KB_COL2_PQ2, - PMUX_PINGRP_KB_COL3_PQ3, - PMUX_PINGRP_KB_COL4_PQ4, - PMUX_PINGRP_KB_COL5_PQ5, - PMUX_PINGRP_KB_COL6_PQ6, - PMUX_PINGRP_KB_COL7_PQ7, - PMUX_PINGRP_CLK_32K_OUT_PA0, - PMUX_PINGRP_SYS_CLK_REQ_PZ5, - PMUX_PINGRP_CORE_PWR_REQ, - PMUX_PINGRP_CPU_PWR_REQ, - PMUX_PINGRP_PWR_INT_N, - PMUX_PINGRP_CLK_32K_IN, - PMUX_PINGRP_OWR, - PMUX_PINGRP_DAP1_FS_PN0, - PMUX_PINGRP_DAP1_DIN_PN1, - PMUX_PINGRP_DAP1_DOUT_PN2, - PMUX_PINGRP_DAP1_SCLK_PN3, - PMUX_PINGRP_CLK1_REQ_PEE2, - PMUX_PINGRP_CLK1_OUT_PW4, - PMUX_PINGRP_SPDIF_IN_PK6, - PMUX_PINGRP_SPDIF_OUT_PK5, - PMUX_PINGRP_DAP2_FS_PA2, - PMUX_PINGRP_DAP2_DIN_PA4, - PMUX_PINGRP_DAP2_DOUT_PA5, - PMUX_PINGRP_DAP2_SCLK_PA3, - PMUX_PINGRP_DVFS_PWM_PX0, - PMUX_PINGRP_GPIO_X1_AUD_PX1, - PMUX_PINGRP_GPIO_X3_AUD_PX3, - PMUX_PINGRP_DVFS_CLK_PX2, - PMUX_PINGRP_GPIO_X4_AUD_PX4, - PMUX_PINGRP_GPIO_X5_AUD_PX5, - PMUX_PINGRP_GPIO_X6_AUD_PX6, - PMUX_PINGRP_GPIO_X7_AUD_PX7, - PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), - PMUX_PINGRP_SDMMC3_CMD_PA7, - PMUX_PINGRP_SDMMC3_DAT0_PB7, - PMUX_PINGRP_SDMMC3_DAT1_PB6, - PMUX_PINGRP_SDMMC3_DAT2_PB5, - PMUX_PINGRP_SDMMC3_DAT3_PB4, - PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), - PMUX_PINGRP_SDMMC1_WP_N_PV3, - PMUX_PINGRP_SDMMC3_CD_N_PV2, - PMUX_PINGRP_GPIO_W2_AUD_PW2, - PMUX_PINGRP_GPIO_W3_AUD_PW3, - PMUX_PINGRP_USB_VBUS_EN0_PN4, - PMUX_PINGRP_USB_VBUS_EN1_PN5, - PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, - PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, - PMUX_PINGRP_GMI_CLK_LB, - PMUX_PINGRP_RESET_OUT_N, - PMUX_PINGRP_COUNT, -}; - -enum pmux_drvgrp { - PMUX_DRVGRP_AO1, - PMUX_DRVGRP_AO2, - PMUX_DRVGRP_AT1, - PMUX_DRVGRP_AT2, - PMUX_DRVGRP_AT3, - PMUX_DRVGRP_AT4, - PMUX_DRVGRP_AT5, - PMUX_DRVGRP_CDEV1, - PMUX_DRVGRP_CDEV2, - PMUX_DRVGRP_DAP1 = (0x28 / 4), - PMUX_DRVGRP_DAP2, - PMUX_DRVGRP_DAP3, - PMUX_DRVGRP_DAP4, - PMUX_DRVGRP_DBG, - PMUX_DRVGRP_SDIO3 = (0x48 / 4), - PMUX_DRVGRP_SPI, - PMUX_DRVGRP_UAA, - PMUX_DRVGRP_UAB, - PMUX_DRVGRP_UART2, - PMUX_DRVGRP_UART3, - PMUX_DRVGRP_SDIO1 = (0x84 / 4), - PMUX_DRVGRP_DDC = (0x94 / 4), - PMUX_DRVGRP_GMA, - PMUX_DRVGRP_GME = (0xa8 / 4), - PMUX_DRVGRP_GMF, - PMUX_DRVGRP_GMG, - PMUX_DRVGRP_GMH, - PMUX_DRVGRP_OWR, - PMUX_DRVGRP_UDA, - PMUX_DRVGRP_DEV3 = (0xc4 / 4), - PMUX_DRVGRP_CEC = (0xd0 / 4), - PMUX_DRVGRP_AT6 = (0x12c / 4), - PMUX_DRVGRP_DAP5, - PMUX_DRVGRP_USB_VBUS_EN, - PMUX_DRVGRP_AO3, - PMUX_DRVGRP_HV0, - PMUX_DRVGRP_SDIO4, - PMUX_DRVGRP_AO0, - PMUX_DRVGRP_COUNT, -}; - -enum pmux_func { - PMUX_FUNC_DEFAULT, - PMUX_FUNC_BLINK, - PMUX_FUNC_CEC, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_CLK, - PMUX_FUNC_CLK12, - PMUX_FUNC_CPU, - PMUX_FUNC_DAP, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DEV3, - PMUX_FUNC_DISPLAYA, - PMUX_FUNC_DISPLAYA_ALT, - PMUX_FUNC_DISPLAYB, - PMUX_FUNC_DTV, - PMUX_FUNC_EMC_DLL, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_IRDA, - PMUX_FUNC_KBC, - PMUX_FUNC_NAND, - PMUX_FUNC_NAND_ALT, - PMUX_FUNC_OWR, - PMUX_FUNC_PMI, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_PWRON, - PMUX_FUNC_RESET_OUT_N, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SOC, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYSCLK, - PMUX_FUNC_TRACE, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_ULPI, - PMUX_FUNC_USB, - PMUX_FUNC_VGP1, - PMUX_FUNC_VGP2, - PMUX_FUNC_VGP3, - PMUX_FUNC_VGP4, - PMUX_FUNC_VGP5, - PMUX_FUNC_VGP6, - PMUX_FUNC_VI, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 -#define TEGRA_PMX_SOC_HAS_IO_CLAMPING -#define TEGRA_PMX_SOC_HAS_DRVGRPS -#define TEGRA_PMX_GRPS_HAVE_LPMD -#define TEGRA_PMX_GRPS_HAVE_SCHMT -#define TEGRA_PMX_GRPS_HAVE_HSM -#define TEGRA_PMX_PINS_HAVE_E_INPUT -#define TEGRA_PMX_PINS_HAVE_LOCK -#define TEGRA_PMX_PINS_HAVE_OD -#define TEGRA_PMX_PINS_HAVE_IO_RESET -#define TEGRA_PMX_PINS_HAVE_RCV_SEL -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA114_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/powergate.h b/arch/arm/include/asm/arch-tegra114/powergate.h deleted file mode 100644 index 260ea80..0000000 --- a/arch/arm/include/asm/arch-tegra114/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA114_POWERGATE_H_ -#define _TEGRA114_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA114_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h deleted file mode 100644 index 228f423..0000000 --- a/arch/arm/include/asm/arch-tegra114/sysctr.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_SYSCTR_H_ -#define _TEGRA114_SYSCTR_H_ - -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ - -#endif /* _TEGRA114_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h deleted file mode 100644 index 317b4bc..0000000 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_H_ -#define _TEGRA114_H_ - -#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ -#define NV_PA_MC_BASE 0x70019000 - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 - -#endif /* TEGRA114_H */ diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h deleted file mode 100644 index d88cdfe..0000000 --- a/arch/arm/include/asm/arch-tegra124/ahb.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA124_AHB_H_ -#define _TEGRA124_AHB_H_ - -struct ahb_ctlr { - u32 reserved0; /* 00h */ - u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ - u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ - u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ - u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ - u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ - u32 reserved6[2]; /* 18h, 1ch */ - u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ - u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ - u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ - u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ - u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ - u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ - u32 reserved13[2]; /* 38h, 3ch */ - u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ - u32 reserved15; /* 44h */ - u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ - u32 reserved17; /* 4ch */ - u32 gizmo_se; /* _GIZMO_SE_0, 50h */ - u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ - u32 reserved20[3]; /* 58h, 5ch, 60h */ - u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ - u32 reserved22[3]; /* 68h, 6ch, 70h */ - u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ - u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ - u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ - u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ - u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ - u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ - u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ - u32 reserved30[13]; /* 90h ~ c0h */ - u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ - u32 reserved32[5]; /* c8h ~ d8h */ - u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ - u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ - u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ - u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ - u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ - u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ - u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ - u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ - /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ - u32 arbitration_ahb_mem_wrque_mst_id; - u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ - u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ - u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ - u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ - u32 reserved46[4]; /* 110h ~ 11ch */ - u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ - u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ - u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ - u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ - u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ - u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ - /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ - u32 axicif_fastsync0_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ - u32 axicif_fastsync1_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ - u32 axicif_fastsync2_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ - u32 axicif_fastsync0_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ - u32 axicif_fastsync1_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ - u32 axicif_fastsync2_mcclk_to_cpuclk; -}; - -#define PPSB_STOPCLK_ENABLE (1 << 2) - -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) - -#define GIZ_USB_IMMEDIATE (1 << 18) - -/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) - -#endif /* _TEGRA124_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h deleted file mode 100644 index 9f53125..0000000 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ /dev/null @@ -1,497 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra124 clock PLL tables */ - -#ifndef _TEGRA124_CLOCK_TABLES_H_ -#define _TEGRA124_CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - CLOCK_ID_DP, /* Special for Tegra124 */ - - /* These are the base clocks (inputs to the Tegra SoC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - CLOCK_ID_CLK_M, - - CLOCK_ID_COUNT, /* number of PLLs */ - - /* - * These are clock IDs that are used in table clock_source[][] - * but will not be assigned as a clock source for any peripheral. - */ - CLOCK_ID_DISPLAY2, - CLOCK_ID_CGENERAL2, - CLOCK_ID_CGENERAL3, - CLOCK_ID_MEMORY2, - CLOCK_ID_SRC2, - - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 (DEVICES_L) */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_COP, - PERIPH_ID_TRIGSYS, - PERIPH_ID_ISPB, - PERIPH_ID_RESERVED4, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_RESERVED13, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_TCW, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_RESERVED19, - PERIPH_ID_VI, - PERIPH_ID_RESERVED21, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_RESERVED24, - PERIPH_ID_RESERVED25, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_I2S0, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 (DEVICES_H) */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_RESERVED36, - PERIPH_ID_STAT_MON, - PERIPH_ID_RESERVED38, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_RESERVED43, - PERIPH_ID_SBC2, - PERIPH_ID_XIO, - PERIPH_ID_SBC3, - PERIPH_ID_I2C5, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_RESERVED49, - PERIPH_ID_HSI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_RESERVED53, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_MIPI_CAL, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_RESERVED60, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_RESERVED64, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_LA, - PERIPH_ID_TRACECLKIN, - PERIPH_ID_SOC_THERM, - PERIPH_ID_DTV, - - /* 80 */ - PERIPH_ID_RESERVED80, - PERIPH_ID_I2CSLOW, - PERIPH_ID_DSIB, - PERIPH_ID_TSEC, - PERIPH_ID_RESERVED84, - PERIPH_ID_RESERVED85, - PERIPH_ID_RESERVED86, - PERIPH_ID_EMUCIF, - - /* 88 */ - PERIPH_ID_RESERVED88, - PERIPH_ID_XUSB_HOST, - PERIPH_ID_RESERVED90, - PERIPH_ID_MSENC, - PERIPH_ID_RESERVED92, - PERIPH_ID_RESERVED93, - PERIPH_ID_RESERVED94, - PERIPH_ID_XUSB_DEV, - - PERIPH_ID_VW_FIRST, - /* V word: 31:0 */ - PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, - PERIPH_ID_CPULP, - PERIPH_ID_V_RESERVED2, - PERIPH_ID_MSELECT, - PERIPH_ID_V_RESERVED4, - PERIPH_ID_I2S3, - PERIPH_ID_I2S4, - PERIPH_ID_I2C4, - - /* 104 */ - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - PERIPH_ID_AUDIO, - PERIPH_ID_APBIF, - PERIPH_ID_DAM0, - PERIPH_ID_DAM1, - PERIPH_ID_DAM2, - PERIPH_ID_HDA2CODEC2X, - - /* 112 */ - PERIPH_ID_ATOMICS, - PERIPH_ID_V_RESERVED17, - PERIPH_ID_V_RESERVED18, - PERIPH_ID_V_RESERVED19, - PERIPH_ID_V_RESERVED20, - PERIPH_ID_V_RESERVED21, - PERIPH_ID_V_RESERVED22, - PERIPH_ID_ACTMON, - - /* 120 */ - PERIPH_ID_EXTPERIPH1, - PERIPH_ID_EXTPERIPH2, - PERIPH_ID_EXTPERIPH3, - PERIPH_ID_OOB, - PERIPH_ID_SATA, - PERIPH_ID_HDA, - PERIPH_ID_V_RESERVED30, - PERIPH_ID_V_RESERVED31, - - /* W word: 31:0 */ - PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_SATACOLD, - PERIPH_ID_W_RESERVED2, - PERIPH_ID_W_RESERVED3, - PERIPH_ID_W_RESERVED4, - PERIPH_ID_W_RESERVED5, - PERIPH_ID_W_RESERVED6, - PERIPH_ID_W_RESERVED7, - - /* 136 */ - PERIPH_ID_CEC, - PERIPH_ID_W_RESERVED9, - PERIPH_ID_W_RESERVED10, - PERIPH_ID_W_RESERVED11, - PERIPH_ID_W_RESERVED12, - PERIPH_ID_W_RESERVED13, - PERIPH_ID_XUSB_PADCTL, - PERIPH_ID_W_RESERVED15, - - /* 144 */ - PERIPH_ID_W_RESERVED16, - PERIPH_ID_W_RESERVED17, - PERIPH_ID_W_RESERVED18, - PERIPH_ID_W_RESERVED19, - PERIPH_ID_W_RESERVED20, - PERIPH_ID_ENTROPY, - PERIPH_ID_DDS, - PERIPH_ID_W_RESERVED23, - - /* 152 */ - PERIPH_ID_DP2, - PERIPH_ID_AMX0, - PERIPH_ID_ADX0, - PERIPH_ID_DVFS, - PERIPH_ID_XUSB_SS, - PERIPH_ID_W_RESERVED29, - PERIPH_ID_W_RESERVED30, - PERIPH_ID_W_RESERVED31, - - PERIPH_ID_X_FIRST, - /* X word: 31:0 */ - PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, - PERIPH_ID_X_RESERVED1, - PERIPH_ID_X_RESERVED2, - PERIPH_ID_X_RESERVED3, - PERIPH_ID_CAM_MCLK, - PERIPH_ID_CAM_MCLK2, - PERIPH_ID_I2C6, - PERIPH_ID_X_RESERVED7, - - /* 168 */ - PERIPH_ID_X_RESERVED8, - PERIPH_ID_X_RESERVED9, - PERIPH_ID_X_RESERVED10, - PERIPH_ID_VIM2_CLK, - PERIPH_ID_X_RESERVED12, - PERIPH_ID_X_RESERVED13, - PERIPH_ID_EMC_DLL, - PERIPH_ID_X_RESERVED15, - - /* 176 */ - PERIPH_ID_HDMI_AUDIO, - PERIPH_ID_CLK72MHZ, - PERIPH_ID_VIC, - PERIPH_ID_X_RESERVED19, - PERIPH_ID_ADX1, - PERIPH_ID_DPAUX, - PERIPH_ID_SOR0, - PERIPH_ID_X_RESERVED23, - - /* 184 */ - PERIPH_ID_GPU, - PERIPH_ID_AMX1, - PERIPH_ID_AFC5, - PERIPH_ID_AFC4, - PERIPH_ID_AFC3, - PERIPH_ID_AFC2, - PERIPH_ID_AFC1, - PERIPH_ID_AFC0, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid - * confusion bewteen PERIPH_ID_... and PERIPHC_... - * - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be - * confusing. - */ -enum periphc_internal_id { - /* 0x00 */ - PERIPHC_I2S1, - PERIPHC_I2S2, - PERIPHC_SPDIF_OUT, - PERIPHC_SPDIF_IN, - PERIPHC_PWM, - PERIPHC_05h, - PERIPHC_SBC2, - PERIPHC_SBC3, - - /* 0x08 */ - PERIPHC_08h, - PERIPHC_I2C1, - PERIPHC_I2C5, - PERIPHC_0bh, - PERIPHC_0ch, - PERIPHC_SBC1, - PERIPHC_DISP1, - PERIPHC_DISP2, - - /* 0x10 */ - PERIPHC_10h, - PERIPHC_11h, - PERIPHC_VI, - PERIPHC_13h, - PERIPHC_SDMMC1, - PERIPHC_SDMMC2, - PERIPHC_G3D, - PERIPHC_G2D, - - /* 0x18 */ - PERIPHC_18h, - PERIPHC_SDMMC4, - PERIPHC_VFIR, - PERIPHC_1Bh, - PERIPHC_1Ch, - PERIPHC_HSI, - PERIPHC_UART1, - PERIPHC_UART2, - - /* 0x20 */ - PERIPHC_HOST1X, - PERIPHC_21h, - PERIPHC_22h, - PERIPHC_HDMI, - PERIPHC_24h, - PERIPHC_25h, - PERIPHC_I2C2, - PERIPHC_EMC, - - /* 0x28 */ - PERIPHC_UART3, - PERIPHC_29h, - PERIPHC_VI_SENSOR, - PERIPHC_2bh, - PERIPHC_2ch, - PERIPHC_SBC4, - PERIPHC_I2C3, - PERIPHC_SDMMC3, - - /* 0x30 */ - PERIPHC_UART4, - PERIPHC_UART5, - PERIPHC_VDE, - PERIPHC_OWR, - PERIPHC_NOR, - PERIPHC_CSITE, - PERIPHC_I2S0, - PERIPHC_DTV, - - /* 0x38 */ - PERIPHC_38h, - PERIPHC_39h, - PERIPHC_3ah, - PERIPHC_3bh, - PERIPHC_MSENC, - PERIPHC_TSEC, - PERIPHC_3eh, - PERIPHC_OSC, - - PERIPHC_VW_FIRST, - /* 0x40 */ - PERIPHC_40h = PERIPHC_VW_FIRST, - PERIPHC_MSELECT, - PERIPHC_TSENSOR, - PERIPHC_I2S3, - PERIPHC_I2S4, - PERIPHC_I2C4, - PERIPHC_SBC5, - PERIPHC_SBC6, - - /* 0x48 */ - PERIPHC_AUDIO, - PERIPHC_49h, - PERIPHC_DAM0, - PERIPHC_DAM1, - PERIPHC_DAM2, - PERIPHC_HDA2CODEC2X, - PERIPHC_ACTMON, - PERIPHC_EXTPERIPH1, - - /* 0x50 */ - PERIPHC_EXTPERIPH2, - PERIPHC_EXTPERIPH3, - PERIPHC_52h, - PERIPHC_I2CSLOW, - PERIPHC_SYS, - PERIPHC_55h, - PERIPHC_56h, - PERIPHC_57h, - - /* 0x58 */ - PERIPHC_58h, - PERIPHC_SOR, - PERIPHC_5ah, - PERIPHC_5bh, - PERIPHC_SATAOOB, - PERIPHC_SATA, - PERIPHC_HDA, /* 0x428 */ - PERIPHC_5fh, - - PERIPHC_X_FIRST, - /* 0x60 */ - PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ - PERIPHC_XUSB_FALCON, - PERIPHC_XUSB_FS, - PERIPHC_XUSB_CORE_DEV, - PERIPHC_XUSB_SS, - PERIPHC_CILAB, - PERIPHC_CILCD, - PERIPHC_CILE, - - /* 0x68 */ - PERIPHC_DSIA_LP, - PERIPHC_DSIB_LP, - PERIPHC_ENTROPY, - PERIPHC_DVFS_REF, - PERIPHC_DVFS_SOC, - PERIPHC_TRACECLKIN, - PERIPHC_ADX0, - PERIPHC_AMX0, - - /* 0x70 */ - PERIPHC_EMC_LATENCY, - PERIPHC_SOC_THERM, - PERIPHC_72h, - PERIPHC_73h, - PERIPHC_74h, - PERIPHC_75h, - PERIPHC_VI_SENSOR2, - PERIPHC_I2C6, - - /* 0x78 */ - PERIPHC_78h, - PERIPHC_EMC_DLL, - PERIPHC_HDMI_AUDIO, - PERIPHC_CLK72MHZ, - PERIPHC_ADX1, - PERIPHC_AMX1, - PERIPHC_VIC, - PERIPHC_7fh, - - PERIPHC_COUNT, - - PERIPHC_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ -#define PERIPH_REG(id) \ - (id < PERIPH_ID_VW_FIRST) ? \ - ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _TEGRA124_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h deleted file mode 100644 index 3f54d36..0000000 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra124 clock control definitions */ - -#ifndef _TEGRA124_CLOCK_H_ -#define _TEGRA124_CLOCK_H_ - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) - -/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ -#define PLLC_IDDQ (1 << 26) - -/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ -#define SOR0_CLK_SEL0 (1 << 14) -#define SOR0_CLK_SEL1 (1 << 15) - -int tegra_plle_enable(void); - -void clock_sor_enable_edp_clock(void); - -/** - * clock_set_display_rate() - Set the display clock rate - * - * @frequency: the requested PLLD frequency - * - * Return the PLLD frequenc (which may not quite what was requested), or 0 - * on failure - */ -u32 clock_set_display_rate(u32 frequency); - -/** - * clock_set_up_plldp() - Set up the EDP clock ready for use - */ -void clock_set_up_plldp(void); - -#endif /* _TEGRA124_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/display.h b/arch/arm/include/asm/arch-tegra124/display.h deleted file mode 100644 index 47e0056..0000000 --- a/arch/arm/include/asm/arch-tegra124/display.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -/** - * Register a new display based on device tree configuration. - * - * The frame buffer can be positioned by U-Boot or overridden by the fdt. - * You should pass in the U-Boot address here, and check the contents of - * struct fdt_disp_config to see what was actually chosen. - * - * @param blob Device tree blob - * @param default_lcd_base Default address of LCD frame buffer - * @return 0 if ok, -1 on error (unsupported bits per pixel) - */ -int tegra_display_probe(const void *blob, void *default_lcd_base); - -/** - * Return the current display configuration - * - * @return pointer to display configuration, or NULL if there is no valid - * config - */ -struct fdt_disp_config *tegra_display_get_config(void); - -/** - * Perform the next stage of the LCD init if it is time to do so. - * - * LCD init can be time-consuming because of the number of delays we need - * while waiting for the backlight power supply, etc. This function can - * be called at various times during U-Boot operation to advance the - * initialization of the LCD to the next stage if sufficient time has - * passed since the last stage. It keeps track of what stage it is up to - * and the time that it is permitted to move to the next stage. - * - * The final call should have wait=1 to complete the init. - * - * @param blob fdt blob containing LCD information - * @param wait 1 to wait until all init is complete, and then return - * 0 to return immediately, potentially doing nothing if it is - * not yet time for the next init. - */ -int tegra_lcd_check_next_stage(const void *blob, int wait); - -/** - * Set up the maximum LCD size so we can size the frame buffer. - * - * @param blob fdt blob containing LCD information - */ -void tegra_lcd_early_init(const void *blob); - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h deleted file mode 100644 index 62947bf..0000000 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA124_FLOW_H_ -#define _TEGRA124_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; /* offset 0x00 */ - u32 halt_cop_events; /* offset 0x04 */ - u32 cpu_csr; /* offset 0x08 */ - u32 cop_csr; /* offset 0x0c */ - u32 xrq_events; /* offset 0x10 */ - u32 halt_cpu1_events; /* offset 0x14 */ - u32 cpu1_csr; /* offset 0x18 */ - u32 halt_cpu2_events; /* offset 0x1c */ - u32 cpu2_csr; /* offset 0x20 */ - u32 halt_cpu3_events; /* offset 0x24 */ - u32 cpu3_csr; /* offset 0x28 */ - u32 cluster_control; /* offset 0x2c */ - u32 halt_cop1_events; /* offset 0x30 */ - u32 halt_cop1_csr; /* offset 0x34 */ - u32 cpu_pwr_csr; /* offset 0x38 */ - u32 mpid; /* offset 0x3c */ - u32 ram_repair; /* offset 0x40 */ - u32 flow_dbg_sel; /* offset 0x44 */ - u32 flow_dbg_cnt0; /* offset 0x48 */ - u32 flow_dbg_cnt1; /* offset 0x4c */ - u32 flow_dbg_qual; /* offset 0x50 */ - u32 flow_ctrl_spare; /* offset 0x54 */ - u32 ram_repair_cluster1;/* offset 0x58 */ -}; - -/* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) -#define EVENT_MODE_STOP (2 << 29) - -/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) - -/* CPUn_CSR_0 */ -#define CSR_ENABLE (1 << 0) -#define CSR_IMMEDIATE_WAKE (1 << 3) -#define CSR_WAIT_WFI_SHIFT 8 -#define CSR_PWR_OFF_STS (1 << 16) - -#define RAM_REPAIR_REQ BIT(0) -#define RAM_REPAIR_STS BIT(1) -#define RAM_REPAIR_BYPASS_EN BIT(2) - -#endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h deleted file mode 100644 index 8d4501e..0000000 --- a/arch/arm/include/asm/arch-tegra124/funcmux.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra124 high-level function multiplexing */ - -#ifndef _TEGRA124_FUNCMUX_H_ -#define _TEGRA124_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_KBC = 0, - FUNCMUX_UART4_GPIO = 0, -}; -#endif /* _TEGRA124_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h deleted file mode 100644 index 750a2dc..0000000 --- a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA124_GP_PADCTRL_H_ -#define _TEGRA124_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - -#endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h deleted file mode 100644 index e5ea281..0000000 --- a/arch/arm/include/asm/arch-tegra124/gpio.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA124_GPIO_H_ -#define _TEGRA124_GPIO_H_ - -/* - * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h deleted file mode 100644 index 617e55a..0000000 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA124_MC_H_ -#define _TEGRA124_MC_H_ - -/** - * Defines the memory controller registers we need/care about - */ -struct mc_ctlr { - u32 reserved0[4]; /* offset 0x00 - 0x0C */ - u32 mc_smmu_config; /* offset 0x10 */ - u32 mc_smmu_tlb_config; /* offset 0x14 */ - u32 mc_smmu_ptc_config; /* offset 0x18 */ - u32 mc_smmu_ptb_asid; /* offset 0x1C */ - u32 mc_smmu_ptb_data; /* offset 0x20 */ - u32 reserved1[3]; /* offset 0x24 - 0x2C */ - u32 mc_smmu_tlb_flush; /* offset 0x30 */ - u32 mc_smmu_ptc_flush; /* offset 0x34 */ - u32 reserved2[6]; /* offset 0x38 - 0x4C */ - u32 mc_emem_cfg; /* offset 0x50 */ - u32 mc_emem_adr_cfg; /* offset 0x54 */ - u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ - u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ - u32 reserved3[4]; /* offset 0x60 - 0x6C */ - u32 mc_security_cfg0; /* offset 0x70 */ - u32 mc_security_cfg1; /* offset 0x74 */ - u32 reserved4[6]; /* offset 0x7C - 0x8C */ - u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ - u32 reserved5[74]; /* offset 0x100 - 0x224 */ - u32 mc_smmu_translation_enable_0; /* offset 0x228 */ - u32 mc_smmu_translation_enable_1; /* offset 0x22C */ - u32 mc_smmu_translation_enable_2; /* offset 0x230 */ - u32 mc_smmu_translation_enable_3; /* offset 0x234 */ - u32 mc_smmu_afi_asid; /* offset 0x238 */ - u32 mc_smmu_avpc_asid; /* offset 0x23C */ - u32 mc_smmu_dc_asid; /* offset 0x240 */ - u32 mc_smmu_dcb_asid; /* offset 0x244 */ - u32 reserved6[2]; /* offset 0x248 - 0x24C */ - u32 mc_smmu_hc_asid; /* offset 0x250 */ - u32 mc_smmu_hda_asid; /* offset 0x254 */ - u32 mc_smmu_isp2_asid; /* offset 0x258 */ - u32 reserved7[2]; /* offset 0x25C - 0x260 */ - u32 mc_smmu_msenc_asid; /* offset 0x264 */ - u32 mc_smmu_nv_asid; /* offset 0x268 */ - u32 mc_smmu_nv2_asid; /* offset 0x26C */ - u32 mc_smmu_ppcs_asid; /* offset 0x270 */ - u32 mc_smmu_sata_asid; /* offset 0x274 */ - u32 reserved8[1]; /* offset 0x278 */ - u32 mc_smmu_vde_asid; /* offset 0x27C */ - u32 mc_smmu_vi_asid; /* offset 0x280 */ - u32 mc_smmu_vic_asid; /* offset 0x284 */ - u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ - u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ - u32 reserved9[1]; /* offset 0x290 */ - u32 mc_smmu_tsec_asid; /* offset 0x294 */ - u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ - u32 reserved10[235]; /* offset 0x29C - 0x644 */ - u32 mc_video_protect_bom; /* offset 0x648 */ - u32 mc_video_protect_size_mb; /* offset 0x64c */ - u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ -}; - -#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) - -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) - -#endif /* _TEGRA124_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h deleted file mode 100644 index 4c593aa..0000000 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ /dev/null @@ -1,359 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA124_PINMUX_H_ -#define _TEGRA124_PINMUX_H_ - -enum pmux_pingrp { - PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_PINGRP_ULPI_DATA4_PO5, - PMUX_PINGRP_ULPI_DATA5_PO6, - PMUX_PINGRP_ULPI_DATA6_PO7, - PMUX_PINGRP_ULPI_DATA7_PO0, - PMUX_PINGRP_ULPI_CLK_PY0, - PMUX_PINGRP_ULPI_DIR_PY1, - PMUX_PINGRP_ULPI_NXT_PY2, - PMUX_PINGRP_ULPI_STP_PY3, - PMUX_PINGRP_DAP3_FS_PP0, - PMUX_PINGRP_DAP3_DIN_PP1, - PMUX_PINGRP_DAP3_DOUT_PP2, - PMUX_PINGRP_DAP3_SCLK_PP3, - PMUX_PINGRP_PV0, - PMUX_PINGRP_PV1, - PMUX_PINGRP_SDMMC1_CLK_PZ0, - PMUX_PINGRP_SDMMC1_CMD_PZ1, - PMUX_PINGRP_SDMMC1_DAT3_PY4, - PMUX_PINGRP_SDMMC1_DAT2_PY5, - PMUX_PINGRP_SDMMC1_DAT1_PY6, - PMUX_PINGRP_SDMMC1_DAT0_PY7, - PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), - PMUX_PINGRP_CLK2_REQ_PCC5, - PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), - PMUX_PINGRP_DDC_SCL_PV4, - PMUX_PINGRP_DDC_SDA_PV5, - PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), - PMUX_PINGRP_UART2_TXD_PC2, - PMUX_PINGRP_UART2_RTS_N_PJ6, - PMUX_PINGRP_UART2_CTS_N_PJ5, - PMUX_PINGRP_UART3_TXD_PW6, - PMUX_PINGRP_UART3_RXD_PW7, - PMUX_PINGRP_UART3_CTS_N_PA1, - PMUX_PINGRP_UART3_RTS_N_PC0, - PMUX_PINGRP_PU0, - PMUX_PINGRP_PU1, - PMUX_PINGRP_PU2, - PMUX_PINGRP_PU3, - PMUX_PINGRP_PU4, - PMUX_PINGRP_PU5, - PMUX_PINGRP_PU6, - PMUX_PINGRP_GEN1_I2C_SDA_PC5, - PMUX_PINGRP_GEN1_I2C_SCL_PC4, - PMUX_PINGRP_DAP4_FS_PP4, - PMUX_PINGRP_DAP4_DIN_PP5, - PMUX_PINGRP_DAP4_DOUT_PP6, - PMUX_PINGRP_DAP4_SCLK_PP7, - PMUX_PINGRP_CLK3_OUT_PEE0, - PMUX_PINGRP_CLK3_REQ_PEE1, - PMUX_PINGRP_PC7, - PMUX_PINGRP_PI5, - PMUX_PINGRP_PI7, - PMUX_PINGRP_PK0, - PMUX_PINGRP_PK1, - PMUX_PINGRP_PJ0, - PMUX_PINGRP_PJ2, - PMUX_PINGRP_PK3, - PMUX_PINGRP_PK4, - PMUX_PINGRP_PK2, - PMUX_PINGRP_PI3, - PMUX_PINGRP_PI6, - PMUX_PINGRP_PG0, - PMUX_PINGRP_PG1, - PMUX_PINGRP_PG2, - PMUX_PINGRP_PG3, - PMUX_PINGRP_PG4, - PMUX_PINGRP_PG5, - PMUX_PINGRP_PG6, - PMUX_PINGRP_PG7, - PMUX_PINGRP_PH0, - PMUX_PINGRP_PH1, - PMUX_PINGRP_PH2, - PMUX_PINGRP_PH3, - PMUX_PINGRP_PH4, - PMUX_PINGRP_PH5, - PMUX_PINGRP_PH6, - PMUX_PINGRP_PH7, - PMUX_PINGRP_PJ7, - PMUX_PINGRP_PB0, - PMUX_PINGRP_PB1, - PMUX_PINGRP_PK7, - PMUX_PINGRP_PI0, - PMUX_PINGRP_PI1, - PMUX_PINGRP_PI2, - PMUX_PINGRP_PI4, - PMUX_PINGRP_GEN2_I2C_SCL_PT5, - PMUX_PINGRP_GEN2_I2C_SDA_PT6, - PMUX_PINGRP_SDMMC4_CLK_PCC4, - PMUX_PINGRP_SDMMC4_CMD_PT7, - PMUX_PINGRP_SDMMC4_DAT0_PAA0, - PMUX_PINGRP_SDMMC4_DAT1_PAA1, - PMUX_PINGRP_SDMMC4_DAT2_PAA2, - PMUX_PINGRP_SDMMC4_DAT3_PAA3, - PMUX_PINGRP_SDMMC4_DAT4_PAA4, - PMUX_PINGRP_SDMMC4_DAT5_PAA5, - PMUX_PINGRP_SDMMC4_DAT6_PAA6, - PMUX_PINGRP_SDMMC4_DAT7_PAA7, - PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), - PMUX_PINGRP_PCC1, - PMUX_PINGRP_PBB0, - PMUX_PINGRP_CAM_I2C_SCL_PBB1, - PMUX_PINGRP_CAM_I2C_SDA_PBB2, - PMUX_PINGRP_PBB3, - PMUX_PINGRP_PBB4, - PMUX_PINGRP_PBB5, - PMUX_PINGRP_PBB6, - PMUX_PINGRP_PBB7, - PMUX_PINGRP_PCC2, - PMUX_PINGRP_JTAG_RTCK, - PMUX_PINGRP_PWR_I2C_SCL_PZ6, - PMUX_PINGRP_PWR_I2C_SDA_PZ7, - PMUX_PINGRP_KB_ROW0_PR0, - PMUX_PINGRP_KB_ROW1_PR1, - PMUX_PINGRP_KB_ROW2_PR2, - PMUX_PINGRP_KB_ROW3_PR3, - PMUX_PINGRP_KB_ROW4_PR4, - PMUX_PINGRP_KB_ROW5_PR5, - PMUX_PINGRP_KB_ROW6_PR6, - PMUX_PINGRP_KB_ROW7_PR7, - PMUX_PINGRP_KB_ROW8_PS0, - PMUX_PINGRP_KB_ROW9_PS1, - PMUX_PINGRP_KB_ROW10_PS2, - PMUX_PINGRP_KB_ROW11_PS3, - PMUX_PINGRP_KB_ROW12_PS4, - PMUX_PINGRP_KB_ROW13_PS5, - PMUX_PINGRP_KB_ROW14_PS6, - PMUX_PINGRP_KB_ROW15_PS7, - PMUX_PINGRP_KB_COL0_PQ0, - PMUX_PINGRP_KB_COL1_PQ1, - PMUX_PINGRP_KB_COL2_PQ2, - PMUX_PINGRP_KB_COL3_PQ3, - PMUX_PINGRP_KB_COL4_PQ4, - PMUX_PINGRP_KB_COL5_PQ5, - PMUX_PINGRP_KB_COL6_PQ6, - PMUX_PINGRP_KB_COL7_PQ7, - PMUX_PINGRP_CLK_32K_OUT_PA0, - PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4), - PMUX_PINGRP_CPU_PWR_REQ, - PMUX_PINGRP_PWR_INT_N, - PMUX_PINGRP_CLK_32K_IN, - PMUX_PINGRP_OWR, - PMUX_PINGRP_DAP1_FS_PN0, - PMUX_PINGRP_DAP1_DIN_PN1, - PMUX_PINGRP_DAP1_DOUT_PN2, - PMUX_PINGRP_DAP1_SCLK_PN3, - PMUX_PINGRP_DAP_MCLK1_REQ_PEE2, - PMUX_PINGRP_DAP_MCLK1_PW4, - PMUX_PINGRP_SPDIF_IN_PK6, - PMUX_PINGRP_SPDIF_OUT_PK5, - PMUX_PINGRP_DAP2_FS_PA2, - PMUX_PINGRP_DAP2_DIN_PA4, - PMUX_PINGRP_DAP2_DOUT_PA5, - PMUX_PINGRP_DAP2_SCLK_PA3, - PMUX_PINGRP_DVFS_PWM_PX0, - PMUX_PINGRP_GPIO_X1_AUD_PX1, - PMUX_PINGRP_GPIO_X3_AUD_PX3, - PMUX_PINGRP_DVFS_CLK_PX2, - PMUX_PINGRP_GPIO_X4_AUD_PX4, - PMUX_PINGRP_GPIO_X5_AUD_PX5, - PMUX_PINGRP_GPIO_X6_AUD_PX6, - PMUX_PINGRP_GPIO_X7_AUD_PX7, - PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), - PMUX_PINGRP_SDMMC3_CMD_PA7, - PMUX_PINGRP_SDMMC3_DAT0_PB7, - PMUX_PINGRP_SDMMC3_DAT1_PB6, - PMUX_PINGRP_SDMMC3_DAT2_PB5, - PMUX_PINGRP_SDMMC3_DAT3_PB4, - PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4), - PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, - PMUX_PINGRP_PEX_WAKE_N_PDD3, - PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4), - PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, - PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), - PMUX_PINGRP_SDMMC1_WP_N_PV3, - PMUX_PINGRP_SDMMC3_CD_N_PV2, - PMUX_PINGRP_GPIO_W2_AUD_PW2, - PMUX_PINGRP_GPIO_W3_AUD_PW3, - PMUX_PINGRP_USB_VBUS_EN0_PN4, - PMUX_PINGRP_USB_VBUS_EN1_PN5, - PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, - PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, - PMUX_PINGRP_GMI_CLK_LB, - PMUX_PINGRP_RESET_OUT_N, - PMUX_PINGRP_KB_ROW16_PT0, - PMUX_PINGRP_KB_ROW17_PT1, - PMUX_PINGRP_USB_VBUS_EN2_PFF1, - PMUX_PINGRP_PFF2, - PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4), - PMUX_PINGRP_COUNT, -}; - -enum pmux_drvgrp { - PMUX_DRVGRP_AO1, - PMUX_DRVGRP_AO2, - PMUX_DRVGRP_AT1, - PMUX_DRVGRP_AT2, - PMUX_DRVGRP_AT3, - PMUX_DRVGRP_AT4, - PMUX_DRVGRP_AT5, - PMUX_DRVGRP_CDEV1, - PMUX_DRVGRP_CDEV2, - PMUX_DRVGRP_DAP1 = (0x28 / 4), - PMUX_DRVGRP_DAP2, - PMUX_DRVGRP_DAP3, - PMUX_DRVGRP_DAP4, - PMUX_DRVGRP_DBG, - PMUX_DRVGRP_SDIO3 = (0x48 / 4), - PMUX_DRVGRP_SPI, - PMUX_DRVGRP_UAA, - PMUX_DRVGRP_UAB, - PMUX_DRVGRP_UART2, - PMUX_DRVGRP_UART3, - PMUX_DRVGRP_SDIO1 = (0x84 / 4), - PMUX_DRVGRP_DDC = (0x94 / 4), - PMUX_DRVGRP_GMA, - PMUX_DRVGRP_GME = (0xa8 / 4), - PMUX_DRVGRP_GMF, - PMUX_DRVGRP_GMG, - PMUX_DRVGRP_GMH, - PMUX_DRVGRP_OWR, - PMUX_DRVGRP_UDA, - PMUX_DRVGRP_GPV, - PMUX_DRVGRP_DEV3, - PMUX_DRVGRP_CEC = (0xd0 / 4), - PMUX_DRVGRP_AT6 = (0x12c / 4), - PMUX_DRVGRP_DAP5, - PMUX_DRVGRP_USB_VBUS_EN, - PMUX_DRVGRP_AO3 = (0x140 / 4), - PMUX_DRVGRP_AO0 = (0x148 / 4), - PMUX_DRVGRP_HV0, - PMUX_DRVGRP_SDIO4 = (0x15c / 4), - PMUX_DRVGRP_AO4, - PMUX_DRVGRP_COUNT, -}; - -enum pmux_mipipadctrlgrp { - PMUX_MIPIPADCTRLGRP_DSI_B, - PMUX_MIPIPADCTRLGRP_COUNT, -}; - -enum pmux_func { - PMUX_FUNC_DEFAULT, - PMUX_FUNC_BLINK, - PMUX_FUNC_CCLA, - PMUX_FUNC_CEC, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_CLK, - PMUX_FUNC_CLK12, - PMUX_FUNC_CPU, - PMUX_FUNC_CSI, - PMUX_FUNC_DAP, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DEV3, - PMUX_FUNC_DISPLAYA, - PMUX_FUNC_DISPLAYA_ALT, - PMUX_FUNC_DISPLAYB, - PMUX_FUNC_DP, - PMUX_FUNC_DSI_B, - PMUX_FUNC_DTV, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_IRDA, - PMUX_FUNC_KBC, - PMUX_FUNC_OWR, - PMUX_FUNC_PE, - PMUX_FUNC_PE0, - PMUX_FUNC_PE1, - PMUX_FUNC_PMI, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_PWRON, - PMUX_FUNC_RESET_OUT_N, - PMUX_FUNC_RTCK, - PMUX_FUNC_SATA, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SOC, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYS, - PMUX_FUNC_TMDS, - PMUX_FUNC_TRACE, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_ULPI, - PMUX_FUNC_USB, - PMUX_FUNC_VGP1, - PMUX_FUNC_VGP2, - PMUX_FUNC_VGP3, - PMUX_FUNC_VGP4, - PMUX_FUNC_VGP5, - PMUX_FUNC_VGP6, - PMUX_FUNC_VI, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_VIMCLK2, - PMUX_FUNC_VIMCLK2_ALT, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 -#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 -#define TEGRA_PMX_SOC_HAS_IO_CLAMPING -#define TEGRA_PMX_SOC_HAS_DRVGRPS -#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS -#define TEGRA_PMX_GRPS_HAVE_LPMD -#define TEGRA_PMX_GRPS_HAVE_SCHMT -#define TEGRA_PMX_GRPS_HAVE_HSM -#define TEGRA_PMX_PINS_HAVE_E_INPUT -#define TEGRA_PMX_PINS_HAVE_LOCK -#define TEGRA_PMX_PINS_HAVE_OD -#define TEGRA_PMX_PINS_HAVE_IO_RESET -#define TEGRA_PMX_PINS_HAVE_RCV_SEL -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA124_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/powergate.h b/arch/arm/include/asm/arch-tegra124/powergate.h deleted file mode 100644 index 8a0cfba..0000000 --- a/arch/arm/include/asm/arch-tegra124/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA124_POWERGATE_H_ -#define _TEGRA124_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA124_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pwm.h b/arch/arm/include/asm/arch-tegra124/pwm.h deleted file mode 100644 index 9ab23e8..0000000 --- a/arch/arm/include/asm/arch-tegra124/pwm.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Tegra pulse width frequency modulator definitions - * - * Copyright (c) 2011 The Chromium OS Authors. - */ - -#ifndef __ASM_ARCH_TEGRA124_PWM_H -#define __ASM_ARCH_TEGRA124_PWM_H - -#include <asm/arch-tegra/pwm.h> - -#endif /* __ASM_ARCH_TEGRA124_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h deleted file mode 100644 index 6567104..0000000 --- a/arch/arm/include/asm/arch-tegra124/sysctr.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA124_SYSCTR_H_ -#define _TEGRA124_SYSCTR_H_ - -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ - -#endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h deleted file mode 100644 index 34070b8..0000000 --- a/arch/arm/include/asm/arch-tegra124/tegra.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA124_H_ -#define _TEGRA124_H_ - -#define NV_PA_SDRAM_BASE 0x80000000 -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ -#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ -#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 -#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) - -#define TEGRA_USB1_BASE 0x7D000000 - -#endif /* _TEGRA124_H_ */ diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h deleted file mode 100644 index 8b7e409..0000000 --- a/arch/arm/include/asm/arch-tegra186/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. - */ - -#ifndef _TEGRA186_GPIO_H_ -#define _TEGRA186_GPIO_H_ - -#endif diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h deleted file mode 100644 index d86cedb..0000000 --- a/arch/arm/include/asm/arch-tegra186/tegra.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2013-2016, NVIDIA CORPORATION. - */ - -#ifndef _TEGRA186_TEGRA_H_ -#define _TEGRA186_TEGRA_H_ - -#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ -#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ -#define NV_PA_SDRAM_BASE 0x80000000 - -#include <asm/arch-tegra/tegra.h> - -#endif diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h deleted file mode 100644 index 861b3d5..0000000 --- a/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra20 clock PLL tables */ - -#ifndef _CLOCK_TABLES_H_ -#define _CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - CLOCK_ID_CLK_M, - - CLOCK_ID_COUNT, /* number of clocks */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_RESERVED1, - PERIPH_ID_RESERVED2, - PERIPH_ID_AC97, - PERIPH_ID_RTC, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_TWC, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_IDE, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_RESERVED30, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_SPI1, - PERIPH_ID_SBC2, - PERIPH_ID_XIO, - PERIPH_ID_SBC3, - PERIPH_ID_DVC_I2C, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_RESERVED79, - - /* 80 */ - PERIPH_ID_RESERVED80, - PERIPH_ID_RESERVED81, - PERIPH_ID_RESERVED82, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_SYNC_CLK_DOUBLER, - PERIPH_ID_CLK_M_DOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUS_OUT, - PERIPH_ID_DEV2_OUT, - PERIPH_ID_DEV1_OUT, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ -#define PERIPH_REG(id) ((id) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range, and not a simple PLL */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ - (id) < CLOCK_ID_FIRST_SIMPLE) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h deleted file mode 100644 index 8158b83..0000000 --- a/arch/arm/include/asm/arch-tegra20/clock.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -/* Tegra20 clock control functions */ - -#ifndef _TEGRA20_CLOCK_H -#define _TEGRA20_CLOCK_H - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 30 -#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) - -int tegra_plle_enable(void); - -#endif /* _TEGRA20_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h deleted file mode 100644 index e7b3cff..0000000 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned x; /* Horizontal address offset (bytes) */ - unsigned y; /* Veritical address offset (bytes) */ - unsigned w; /* Width of source window */ - unsigned h; /* Height of source window */ - unsigned stride; /* Number of bytes per line */ - unsigned out_x; /* Left edge of output window (col) */ - unsigned out_y; /* Top edge of output window (row) */ - unsigned out_w; /* Width of output window in pixels */ - unsigned out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra20/emc.h b/arch/arm/include/asm/arch-tegra20/emc.h deleted file mode 100644 index 58ee08c..0000000 --- a/arch/arm/include/asm/arch-tegra20/emc.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _ARCH_EMC_H_ -#define _ARCH_EMC_H_ - -#include <asm/types.h> - -#define TEGRA_EMC_NUM_REGS 46 - -/* EMC Registers */ -struct emc_ctlr { - u32 cfg; /* 0x00: EMC_CFG */ - u32 reserved0[3]; /* 0x04 ~ 0x0C */ - u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ - u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ - u32 reserved1[2]; /* 0x18 ~ 0x18 */ - u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ - u32 pin; /* 0x24: EMC_PIN */ - u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ - u32 rc; /* 0x2C: EMC_RC */ - u32 rfc; /* 0x30: EMC_RFC */ - u32 ras; /* 0x34: EMC_RAS */ - u32 rp; /* 0x38: EMC_RP */ - u32 r2w; /* 0x3C: EMC_R2W */ - u32 w2r; /* 0x40: EMC_W2R */ - u32 r2p; /* 0x44: EMC_R2P */ - u32 w2p; /* 0x48: EMC_W2P */ - u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ - u32 wd_rcd; /* 0x50: EMC_WD_RCD */ - u32 rrd; /* 0x54: EMC_RRD */ - u32 rext; /* 0x58: EMC_REXT */ - u32 wdv; /* 0x5C: EMC_WDV */ - u32 quse; /* 0x60: EMC_QUSE */ - u32 qrst; /* 0x64: EMC_QRST */ - u32 qsafe; /* 0x68: EMC_QSAFE */ - u32 rdv; /* 0x6C: EMC_RDV */ - u32 refresh; /* 0x70: EMC_REFRESH */ - u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ - u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ - u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ - u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ - u32 act2pden; /* 0x84: EMC_ACT2PDEN */ - u32 ar2pden; /* 0x88: EMC_AR2PDEN */ - u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ - u32 txsr; /* 0x90: EMC_TXSR */ - u32 tcke; /* 0x94: EMC_TCKE */ - u32 tfaw; /* 0x98: EMC_TFAW */ - u32 trpab; /* 0x9C: EMC_TRPAB */ - u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ - u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ - u32 trefbw; /* 0xA8: EMC_TREFBW */ - u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ - u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ - u32 odt_read; /* 0xB4: EMC_ODT_READ */ - u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ - u32 mrs; /* 0xCC: EMC_MRS */ - u32 emrs; /* 0xD0: EMC_EMRS */ - u32 ref; /* 0xD4: EMC_REF */ - u32 pre; /* 0xD8: EMC_PRE */ - u32 nop; /* 0xDC: EMC_NOP */ - u32 self_ref; /* 0xE0: EMC_SELF_REF */ - u32 dpd; /* 0xE4: EMC_DPD */ - u32 mrw; /* 0xE8: EMC_MRW */ - u32 mrr; /* 0xEC: EMC_MRR */ - u32 reserved3; /* 0xF0: */ - u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ - u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ - u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ - u32 fbio_spare; /* 0x100: SBIO_SPARE */ - /* There are more registers ... */ -}; - -/** - * Set up the EMC for the given rate. The timing parameters are retrieved - * from the device tree "nvidia,tegra20-emc" node and its - * "nvidia,tegra20-emc-table" sub-nodes. - * - * @param blob Device tree blob - * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) - * @return 0 if ok, else -ve error code (look in emc.c to decode it) - */ -int tegra_set_emc(const void *blob, unsigned rate); - -/** - * Get a pointer to the EMC controller from the device tree. - * - * @param blob Device tree blob - * @return pointer to EMC controller - */ -struct emc_ctlr *emc_get_controller(const void *blob); - -#endif diff --git a/arch/arm/include/asm/arch-tegra20/flow.h b/arch/arm/include/asm/arch-tegra20/flow.h deleted file mode 100644 index 33be841..0000000 --- a/arch/arm/include/asm/arch-tegra20/flow.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _FLOW_H_ -#define _FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 halt_cpu1_events; - u32 cpu1_csr; -}; - -#endif diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h deleted file mode 100644 index e9e96c1..0000000 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -/* Tegra20 high-level function multiplexing */ - -#ifndef _TEGRA20_FUNCMUX_H_ -#define _TEGRA20_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_IRRX_IRTX = 0, - FUNCMUX_UART1_UAA_UAB, - FUNCMUX_UART1_GPU, - FUNCMUX_UART1_SDIO1, - FUNCMUX_UART2_UAD = 0, - FUNCMUX_UART4_GMC = 0, - - /* I2C configs */ - FUNCMUX_DVC_I2CP = 0, - FUNCMUX_I2C1_RM = 0, - FUNCMUX_I2C2_DDC = 0, - FUNCMUX_I2C2_PTA, - FUNCMUX_I2C3_DTF = 0, - - /* SDMMC configs */ - FUNCMUX_SDMMC1_SDIO1_4BIT = 0, - FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, - FUNCMUX_SDMMC3_SDB_4BIT = 0, - FUNCMUX_SDMMC3_SDB_SLXA_8BIT, - FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0, - FUNCMUX_SDMMC4_ATB_GMA_4_BIT, - FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT, - - /* USB configs */ - FUNCMUX_USB2_ULPI = 0, - - /* Serial Flash configs */ - FUNCMUX_SPI1_GMC_GMD = 0, - - /* NAND flags */ - FUNCMUX_NDFLASH_ATC = 0, - FUNCMUX_NDFLASH_KBC_8_BIT, -}; -#endif /* _TEGRA20_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h deleted file mode 100644 index dd2ee12..0000000 --- a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA20_GP_PADCTRL_H_ -#define _TEGRA20_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ - u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ - u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ - u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ - u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ - u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ - u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ - u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ - u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ - u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ -}; - -#endif /* _TEGRA20_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h deleted file mode 100644 index 6818c28..0000000 --- a/arch/arm/include/asm/arch-tegra20/gpio.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * Portions Copyright 2011-2012 NVIDIA Corporation - */ - -#ifndef _TEGRA20_GPIO_H_ -#define _TEGRA20_GPIO_H_ - -/* - * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 7 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* TEGRA20_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h deleted file mode 100644 index 71283e4..0000000 --- a/arch/arm/include/asm/arch-tegra20/mc.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA20_MC_H_ -#define _TEGRA20_MC_H_ - -/** - * Defines the memory controller registers we need/care about - */ -struct mc_ctlr { - u32 reserved0[3]; /* offset 0x00 - 0x08 */ - u32 mc_emem_cfg; /* offset 0x0C */ - u32 mc_emem_adr_cfg; /* offset 0x10 */ - u32 mc_emem_arb_cfg0; /* offset 0x14 */ - u32 mc_emem_arb_cfg1; /* offset 0x18 */ - u32 mc_emem_arb_cfg2; /* offset 0x1C */ - u32 reserved1; /* offset 0x20 */ - u32 mc_gart_cfg; /* offset 0x24 */ - u32 mc_gart_entry_addr; /* offset 0x28 */ - u32 mc_gart_entry_data; /* offset 0x2C */ - u32 mc_gart_error_req; /* offset 0x30 */ - u32 mc_gart_error_addr; /* offset 0x34 */ - u32 reserved2; /* offset 0x38 */ - u32 mc_timeout_ctrl; /* offset 0x3C */ - u32 reserved3[6]; /* offset 0x40 - 0x54 */ - u32 mc_decerr_emem_others_status; /* offset 0x58 */ - u32 mc_decerr_emem_others_adr; /* offset 0x5C */ - u32 reserved4[40]; /* offset 0x60 - 0xFC */ - u32 reserved5[93]; /* offset 0x100 - 0x270 */ -}; - -#endif /* _TEGRA20_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h deleted file mode 100644 index e9e3801..0000000 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ /dev/null @@ -1,238 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA20_PINMUX_H_ -#define _TEGRA20_PINMUX_H_ - -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ -enum pmux_pingrp { - /* APB_MISC_PP_TRISTATE_REG_A_0 */ - PMUX_PINGRP_ATA, - PMUX_PINGRP_ATB, - PMUX_PINGRP_ATC, - PMUX_PINGRP_ATD, - PMUX_PINGRP_CDEV1, - PMUX_PINGRP_CDEV2, - PMUX_PINGRP_CSUS, - PMUX_PINGRP_DAP1, - - PMUX_PINGRP_DAP2, - PMUX_PINGRP_DAP3, - PMUX_PINGRP_DAP4, - PMUX_PINGRP_DTA, - PMUX_PINGRP_DTB, - PMUX_PINGRP_DTC, - PMUX_PINGRP_DTD, - PMUX_PINGRP_DTE, - - PMUX_PINGRP_GPU, - PMUX_PINGRP_GPV, - PMUX_PINGRP_I2CP, - PMUX_PINGRP_IRTX, - PMUX_PINGRP_IRRX, - PMUX_PINGRP_KBCB, - PMUX_PINGRP_KBCA, - PMUX_PINGRP_PMC, - - PMUX_PINGRP_PTA, - PMUX_PINGRP_RM, - PMUX_PINGRP_KBCE, - PMUX_PINGRP_KBCF, - PMUX_PINGRP_GMA, - PMUX_PINGRP_GMC, - PMUX_PINGRP_SDIO1, - PMUX_PINGRP_OWC, - - /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ - PMUX_PINGRP_GME, - PMUX_PINGRP_SDC, - PMUX_PINGRP_SDD, - PMUX_PINGRP_RESERVED0, - PMUX_PINGRP_SLXA, - PMUX_PINGRP_SLXC, - PMUX_PINGRP_SLXD, - PMUX_PINGRP_SLXK, - - PMUX_PINGRP_SPDI, - PMUX_PINGRP_SPDO, - PMUX_PINGRP_SPIA, - PMUX_PINGRP_SPIB, - PMUX_PINGRP_SPIC, - PMUX_PINGRP_SPID, - PMUX_PINGRP_SPIE, - PMUX_PINGRP_SPIF, - - PMUX_PINGRP_SPIG, - PMUX_PINGRP_SPIH, - PMUX_PINGRP_UAA, - PMUX_PINGRP_UAB, - PMUX_PINGRP_UAC, - PMUX_PINGRP_UAD, - PMUX_PINGRP_UCA, - PMUX_PINGRP_UCB, - - PMUX_PINGRP_RESERVED1, - PMUX_PINGRP_ATE, - PMUX_PINGRP_KBCC, - PMUX_PINGRP_RESERVED2, - PMUX_PINGRP_RESERVED3, - PMUX_PINGRP_GMB, - PMUX_PINGRP_GMD, - PMUX_PINGRP_DDC, - - /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ - PMUX_PINGRP_LD0, - PMUX_PINGRP_LD1, - PMUX_PINGRP_LD2, - PMUX_PINGRP_LD3, - PMUX_PINGRP_LD4, - PMUX_PINGRP_LD5, - PMUX_PINGRP_LD6, - PMUX_PINGRP_LD7, - - PMUX_PINGRP_LD8, - PMUX_PINGRP_LD9, - PMUX_PINGRP_LD10, - PMUX_PINGRP_LD11, - PMUX_PINGRP_LD12, - PMUX_PINGRP_LD13, - PMUX_PINGRP_LD14, - PMUX_PINGRP_LD15, - - PMUX_PINGRP_LD16, - PMUX_PINGRP_LD17, - PMUX_PINGRP_LHP0, - PMUX_PINGRP_LHP1, - PMUX_PINGRP_LHP2, - PMUX_PINGRP_LVP0, - PMUX_PINGRP_LVP1, - PMUX_PINGRP_HDINT, - - PMUX_PINGRP_LM0, - PMUX_PINGRP_LM1, - PMUX_PINGRP_LVS, - PMUX_PINGRP_LSC0, - PMUX_PINGRP_LSC1, - PMUX_PINGRP_LSCK, - PMUX_PINGRP_LDC, - PMUX_PINGRP_LCSN, - - /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ - PMUX_PINGRP_LSPI, - PMUX_PINGRP_LSDA, - PMUX_PINGRP_LSDI, - PMUX_PINGRP_LPW0, - PMUX_PINGRP_LPW1, - PMUX_PINGRP_LPW2, - PMUX_PINGRP_LDI, - PMUX_PINGRP_LHS, - - PMUX_PINGRP_LPP, - PMUX_PINGRP_RESERVED4, - PMUX_PINGRP_KBCD, - PMUX_PINGRP_GPU7, - PMUX_PINGRP_DTF, - PMUX_PINGRP_UDA, - PMUX_PINGRP_CRTP, - PMUX_PINGRP_SDB, - - /* these pin groups only have pullup and pull down control */ - PMUX_PINGRP_CK32, - PMUX_PINGRP_DDRC, - PMUX_PINGRP_PMCA, - PMUX_PINGRP_PMCB, - PMUX_PINGRP_PMCC, - PMUX_PINGRP_PMCD, - PMUX_PINGRP_PMCE, - PMUX_PINGRP_XM2C, - PMUX_PINGRP_XM2D, - PMUX_PINGRP_COUNT, -}; - -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ -enum pmux_func { - PMUX_FUNC_DEFAULT, - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, - PMUX_FUNC_HDMI, - PMUX_FUNC_I2C, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, - PMUX_FUNC_NAND, - PMUX_FUNC_OSC, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDIO1, - PMUX_FUNC_SDIO2, - PMUX_FUNC_SDIO3, - PMUX_FUNC_SDIO4, - PMUX_FUNC_SFLASH, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA20_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/powergate.h b/arch/arm/include/asm/arch-tegra20/powergate.h deleted file mode 100644 index 439d88b..0000000 --- a/arch/arm/include/asm/arch-tegra20/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA20_POWERGATE_H_ -#define _TEGRA20_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA20_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h deleted file mode 100644 index 9467617..0000000 --- a/arch/arm/include/asm/arch-tegra20/pwm.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Tegra pulse width frequency modulator definitions - * - * Copyright (c) 2011 The Chromium OS Authors. - */ - -#ifndef __ASM_ARCH_TEGRA20_PWM_H -#define __ASM_ARCH_TEGRA20_PWM_H - -#include <asm/arch-tegra/pwm.h> - -#endif /* __ASM_ARCH_TEGRA20_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra20/sdram_param.h b/arch/arm/include/asm/arch-tegra20/sdram_param.h deleted file mode 100644 index 3d1405f..0000000 --- a/arch/arm/include/asm/arch-tegra20/sdram_param.h +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _SDRAM_PARAM_H_ -#define _SDRAM_PARAM_H_ - -/* - * Defines the number of 32-bit words provided in each set of SDRAM parameters - * for arbitration configuration data. - */ -#define BCT_SDRAM_ARB_CONFIG_WORDS 27 - -enum memory_type { - MEMORY_TYPE_NONE = 0, - MEMORY_TYPE_DDR, - MEMORY_TYPE_LPDDR, - MEMORY_TYPE_DDR2, - MEMORY_TYPE_LPDDR2, - MEMORY_TYPE_NUM, - MEMORY_TYPE_FORCE32 = 0x7FFFFFFF -}; - -/* Defines the SDRAM parameter structure */ -struct sdram_params { - enum memory_type memory_type; - u32 pllm_charge_pump_setup_control; - u32 pllm_loop_filter_setup_control; - u32 pllm_input_divider; - u32 pllm_feedback_divider; - u32 pllm_post_divider; - u32 pllm_stable_time; - u32 emc_clock_divider; - u32 emc_auto_cal_interval; - u32 emc_auto_cal_config; - u32 emc_auto_cal_wait; - u32 emc_pin_program_wait; - u32 emc_rc; - u32 emc_rfc; - u32 emc_ras; - u32 emc_rp; - u32 emc_r2w; - u32 emc_w2r; - u32 emc_r2p; - u32 emc_w2p; - u32 emc_rd_rcd; - u32 emc_wr_rcd; - u32 emc_rrd; - u32 emc_rext; - u32 emc_wdv; - u32 emc_quse; - u32 emc_qrst; - u32 emc_qsafe; - u32 emc_rdv; - u32 emc_refresh; - u32 emc_burst_refresh_num; - u32 emc_pdex2wr; - u32 emc_pdex2rd; - u32 emc_pchg2pden; - u32 emc_act2pden; - u32 emc_ar2pden; - u32 emc_rw2pden; - u32 emc_txsr; - u32 emc_tcke; - u32 emc_tfaw; - u32 emc_trpab; - u32 emc_tclkstable; - u32 emc_tclkstop; - u32 emc_trefbw; - u32 emc_quseextra; - u32 emc_fbioc_fg1; - u32 emc_fbio_dqsib_dly; - u32 emc_fbio_dqsib_dly_msb; - u32 emc_fbio_quse_dly; - u32 emc_fbio_quse_dly_msb; - u32 emc_fbio_cfg5; - u32 emc_fbio_cfg6; - u32 emc_fbio_spare; - u32 emc_mrs; - u32 emc_emrs; - u32 emc_mrw1; - u32 emc_mrw2; - u32 emc_mrw3; - u32 emc_mrw_reset_command; - u32 emc_mrw_reset_init_wait; - u32 emc_adr_cfg; - u32 emc_adr_cfg1; - u32 emc_emem_cfg; - u32 emc_low_latency_config; - u32 emc_cfg; - u32 emc_cfg2; - u32 emc_dbg; - u32 ahb_arbitration_xbar_ctrl; - u32 emc_cfg_dig_dll; - u32 emc_dll_xform_dqs; - u32 emc_dll_xform_quse; - u32 warm_boot_wait; - u32 emc_ctt_term_ctrl; - u32 emc_odt_write; - u32 emc_odt_read; - u32 emc_zcal_ref_cnt; - u32 emc_zcal_wait_cnt; - u32 emc_zcal_mrw_cmd; - u32 emc_mrs_reset_dll; - u32 emc_mrw_zq_init_dev0; - u32 emc_mrw_zq_init_dev1; - u32 emc_mrw_zq_init_wait; - u32 emc_mrs_reset_dll_wait; - u32 emc_emrs_emr2; - u32 emc_emrs_emr3; - u32 emc_emrs_ddr2_dll_enable; - u32 emc_mrs_ddr2_dll_reset; - u32 emc_emrs_ddr2_ocd_calib; - u32 emc_edr2_wait; - u32 emc_cfg_clktrim0; - u32 emc_cfg_clktrim1; - u32 emc_cfg_clktrim2; - u32 pmc_ddr_pwr; - u32 apb_misc_gp_xm2cfga_padctrl; - u32 apb_misc_gp_xm2cfgc_padctrl; - u32 apb_misc_gp_xm2cfgc_padctrl2; - u32 apb_misc_gp_xm2cfgd_padctrl; - u32 apb_misc_gp_xm2cfgd_padctrl2; - u32 apb_misc_gp_xm2clkcfg_padctrl; - u32 apb_misc_gp_xm2comp_padctrl; - u32 apb_misc_gp_xm2vttgen_padctrl; - u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; -}; -#endif diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h deleted file mode 100644 index 3fecbcd..0000000 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA20_H_ -#define _TEGRA20_H_ - -#define NV_PA_SDRAM_BASE 0x00000000 -#define NV_PA_MC_BASE 0x7000F000 - -#include <asm/arch-tegra/tegra.h> - -#define TEGRA_USB1_BASE 0xC5000000 - -#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ - -#define MAX_NUM_CPU 2 - -#endif /* TEGRA20_H */ diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h deleted file mode 100644 index 8ecd6d9..0000000 --- a/arch/arm/include/asm/arch-tegra210/ahb.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA210_AHB_H_ -#define _TEGRA210_AHB_H_ - -struct ahb_ctlr { - u32 reserved0; /* 00h */ - u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ - u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ - u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ - u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ - u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ - u32 reserved6[2]; /* 18h, 1ch */ - u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ - u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ - u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ - u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ - u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ - u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ - u32 reserved13[2]; /* 38h, 3ch */ - u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ - u32 reserved15; /* 44h */ - u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ - u32 reserved17; /* 4ch */ - u32 gizmo_se; /* _GIZMO_SE_0, 50h */ - u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ - u32 reserved20[3]; /* 58h, 5ch, 60h */ - u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ - u32 reserved22[3]; /* 68h, 6ch, 70h */ - u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ - u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ - u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ - u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ - u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ - u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ - u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ - u32 reserved30[13]; /* 90h ~ c0h */ - u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ - u32 reserved32[5]; /* c8h ~ d8h */ - u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ - u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ - u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ - u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ - u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ - u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ - u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ - u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ - /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ - u32 arbitration_ahb_mem_wrque_mst_id; - u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ - u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ - u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ - u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ - u32 reserved46[4]; /* 110h ~ 11ch */ - u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ - u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ - u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ - u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ - u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ - u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ - /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ - u32 axicif_fastsync0_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ - u32 axicif_fastsync1_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ - u32 axicif_fastsync2_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ - u32 axicif_fastsync0_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ - u32 axicif_fastsync1_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ - u32 axicif_fastsync2_mcclk_to_cpuclk; -}; - -#define PPSB_STOPCLK_ENABLE (1 << 2) - -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) - -#define GIZ_USB_IMMEDIATE (1 << 18) - -/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) - -#endif /* _TEGRA210_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h deleted file mode 100644 index c6d7487..0000000 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ /dev/null @@ -1,567 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra210 clock PLL tables */ - -#ifndef _TEGRA210_CLOCK_TABLES_H_ -#define _TEGRA210_CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - CLOCK_ID_DP, - - /* These are the base clocks (inputs to the Tegra SoC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - CLOCK_ID_CLK_M, - - CLOCK_ID_COUNT, /* number of PLLs */ - - /* - * These are clock IDs that are used in table clock_source[][] - * but will not be assigned as a clock source for any peripheral. - */ - CLOCK_ID_DISPLAY2, - CLOCK_ID_CGENERAL_0, - CLOCK_ID_CGENERAL_1, - CLOCK_ID_CGENERAL2, - CLOCK_ID_CGENERAL3, - CLOCK_ID_CGENERAL4_0, - CLOCK_ID_CGENERAL4_1, - CLOCK_ID_CGENERAL4_2, - CLOCK_ID_MEMORY2, - CLOCK_ID_SRC2, - - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 (DEVICES_L) */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_COP, - PERIPH_ID_TRIGSYS, - PERIPH_ID_ISPB, - PERIPH_ID_RESERVED4, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S2, - PERIPH_ID_I2C1, - PERIPH_ID_RESERVED13, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_TCW, - PERIPH_ID_PWM, - PERIPH_ID_I2S3, - PERIPH_ID_RESERVED19, - PERIPH_ID_VI, - PERIPH_ID_RESERVED21, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_RESERVED24, - PERIPH_ID_RESERVED25, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_I2S1, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 (DEVICES_H) */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_RESERVED36, - PERIPH_ID_STAT_MON, - PERIPH_ID_RESERVED38, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_RESERVED43, - PERIPH_ID_SBC2, - PERIPH_ID_XIO, - PERIPH_ID_SBC3, - PERIPH_ID_I2C5, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_RESERVED49, - PERIPH_ID_HSI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_RESERVED53, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_MIPI_CAL, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_RESERVED60, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_RESERVED64, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_LA, - PERIPH_ID_TRACECLKIN, - PERIPH_ID_SOC_THERM, - PERIPH_ID_DTV, - - /* 80 */ - PERIPH_ID_RESERVED80, - PERIPH_ID_I2CSLOW, - PERIPH_ID_DSIB, - PERIPH_ID_TSEC, - PERIPH_ID_RESERVED84, - PERIPH_ID_RESERVED85, - PERIPH_ID_RESERVED86, - PERIPH_ID_EMUCIF, - - /* 88 */ - PERIPH_ID_RESERVED88, - PERIPH_ID_XUSB_HOST, - PERIPH_ID_RESERVED90, - PERIPH_ID_MSENC, - PERIPH_ID_RESERVED92, - PERIPH_ID_RESERVED93, - PERIPH_ID_RESERVED94, - PERIPH_ID_XUSB_DEV, - - PERIPH_ID_VW_FIRST, - /* V word: 31:0 */ - PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, - PERIPH_ID_CPULP, - PERIPH_ID_V_RESERVED2, - PERIPH_ID_MSELECT, - PERIPH_ID_V_RESERVED4, - PERIPH_ID_I2S4, - PERIPH_ID_I2S5, - PERIPH_ID_I2C4, - - /* 104 */ - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - PERIPH_ID_AHUB, - PERIPH_ID_APB2APE, - PERIPH_ID_V_RESERVED12, - PERIPH_ID_V_RESERVED13, - PERIPH_ID_V_RESERVED14, - PERIPH_ID_HDA2CODEC2X, - - /* 112 */ - PERIPH_ID_ATOMICS, - PERIPH_ID_V_RESERVED17, - PERIPH_ID_V_RESERVED18, - PERIPH_ID_V_RESERVED19, - PERIPH_ID_V_RESERVED20, - PERIPH_ID_V_RESERVED21, - PERIPH_ID_V_RESERVED22, - PERIPH_ID_ACTMON, - - /* 120 */ - PERIPH_ID_EXTPERIPH1, - PERIPH_ID_EXTPERIPH2, - PERIPH_ID_EXTPERIPH3, - PERIPH_ID_OOB, - PERIPH_ID_SATA, - PERIPH_ID_HDA, - PERIPH_ID_V_RESERVED30, - PERIPH_ID_V_RESERVED31, - - /* W word: 31:0 */ - PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_SATACOLD, - PERIPH_ID_W_RESERVED2, - PERIPH_ID_W_RESERVED3, - PERIPH_ID_W_RESERVED4, - PERIPH_ID_W_RESERVED5, - PERIPH_ID_W_RESERVED6, - PERIPH_ID_W_RESERVED7, - - /* 136 */ - PERIPH_ID_CEC, - PERIPH_ID_W_RESERVED9, - PERIPH_ID_W_RESERVED10, - PERIPH_ID_W_RESERVED11, - PERIPH_ID_W_RESERVED12, - PERIPH_ID_W_RESERVED13, - PERIPH_ID_XUSB_PADCTL, - PERIPH_ID_W_RESERVED15, - - /* 144 */ - PERIPH_ID_W_RESERVED16, - PERIPH_ID_W_RESERVED17, - PERIPH_ID_W_RESERVED18, - PERIPH_ID_W_RESERVED19, - PERIPH_ID_W_RESERVED20, - PERIPH_ID_ENTROPY, - PERIPH_ID_DDS, - PERIPH_ID_W_RESERVED23, - - /* 152 */ - PERIPH_ID_W_RESERVED24, - PERIPH_ID_W_RESERVED25, - PERIPH_ID_W_RESERVED26, - PERIPH_ID_DVFS, - PERIPH_ID_XUSB_SS, - PERIPH_ID_W_RESERVED29, - PERIPH_ID_W_RESERVED30, - PERIPH_ID_W_RESERVED31, - - PERIPH_ID_X_FIRST, - /* X word: 31:0 */ - PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, - PERIPH_ID_X_RESERVED1, - PERIPH_ID_X_RESERVED2, - PERIPH_ID_X_RESERVED3, - PERIPH_ID_CAM_MCLK, - PERIPH_ID_CAM_MCLK2, - PERIPH_ID_I2C6, - PERIPH_ID_X_RESERVED7, - - /* 168 */ - PERIPH_ID_X_RESERVED8, - PERIPH_ID_X_RESERVED9, - PERIPH_ID_X_RESERVED10, - PERIPH_ID_VIM2_CLK, - PERIPH_ID_X_RESERVED12, - PERIPH_ID_X_RESERVED13, - PERIPH_ID_EMC_DLL, - PERIPH_ID_X_RESERVED15, - - /* 176 */ - PERIPH_ID_HDMI_AUDIO, - PERIPH_ID_CLK72MHZ, - PERIPH_ID_VIC, - PERIPH_ID_X_RESERVED19, - PERIPH_ID_X_RESERVED20, - PERIPH_ID_DPAUX, - PERIPH_ID_SOR0, - PERIPH_ID_X_RESERVED23, - - /* 184 */ - PERIPH_ID_GPU, - PERIPH_ID_X_RESERVED25, - PERIPH_ID_X_RESERVED26, - PERIPH_ID_X_RESERVED27, - PERIPH_ID_X_RESERVED28, - PERIPH_ID_X_RESERVED29, - PERIPH_ID_X_RESERVED30, - PERIPH_ID_X_RESERVED31, - - PERIPH_ID_Y_FIRST, - /* Y word: 31:0 (192:223) */ - PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST, - PERIPH_ID_Y_RESERVED1, - PERIPH_ID_Y_RESERVED2, - PERIPH_ID_Y_RESERVED3, - PERIPH_ID_Y_RESERVED4, - PERIPH_ID_Y_RESERVED5, - PERIPH_ID_APE, - PERIPH_ID_Y_RESERVED7, - - /* 200 */ - PERIPH_ID_MC_CDPA, - PERIPH_ID_Y_RESERVED9, - PERIPH_ID_Y_RESERVED10, - PERIPH_ID_Y_RESERVED11, - PERIPH_ID_Y_RESERVED12, - PERIPH_ID_PEX_USB_UPHY, - PERIPH_ID_Y_RESERVED14, - PERIPH_ID_Y_RESERVED15, - - /* 208 */ - PERIPH_ID_VI_I2C, - PERIPH_ID_Y_RESERVED17, - PERIPH_ID_Y_RESERVED18, - PERIPH_ID_QSPI, - PERIPH_ID_Y_RESERVED20, - PERIPH_ID_Y_RESERVED21, - PERIPH_ID_Y_RESERVED22, - PERIPH_ID_Y_RESERVED23, - - /* 216 */ - PERIPH_ID_Y_RESERVED24, - PERIPH_ID_Y_RESERVED25, - PERIPH_ID_Y_RESERVED26, - PERIPH_ID_Y_RESERVED27, - PERIPH_ID_Y_RESERVED28, - PERIPH_ID_Y_RESERVED29, - PERIPH_ID_Y_RESERVED30, - PERIPH_ID_Y_RESERVED31, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid - * confusion bewteen PERIPH_ID_... and PERIPHC_... - * - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be - * confusing. - */ -enum periphc_internal_id { - /* 0x00 */ - PERIPHC_I2S2, - PERIPHC_I2S3, - PERIPHC_SPDIF_OUT, - PERIPHC_SPDIF_IN, - PERIPHC_PWM, - PERIPHC_05h, - PERIPHC_SBC2, - PERIPHC_SBC3, - - /* 0x08 */ - PERIPHC_08h, - PERIPHC_I2C1, - PERIPHC_I2C5, - PERIPHC_0bh, - PERIPHC_0ch, - PERIPHC_SBC1, - PERIPHC_DISP1, - PERIPHC_DISP2, - - /* 0x10 */ - PERIPHC_10h, - PERIPHC_11h, - PERIPHC_VI, - PERIPHC_13h, - PERIPHC_SDMMC1, - PERIPHC_SDMMC2, - PERIPHC_G3D, - PERIPHC_G2D, - - /* 0x18 */ - PERIPHC_18h, - PERIPHC_SDMMC4, - PERIPHC_VFIR, - PERIPHC_1Bh, - PERIPHC_1Ch, - PERIPHC_HSI, - PERIPHC_UART1, - PERIPHC_UART2, - - /* 0x20 */ - PERIPHC_HOST1X, - PERIPHC_21h, - PERIPHC_22h, - PERIPHC_HDMI, - PERIPHC_24h, - PERIPHC_25h, - PERIPHC_I2C2, - PERIPHC_EMC, - - /* 0x28 */ - PERIPHC_UART3, - PERIPHC_29h, - PERIPHC_VI_SENSOR, - PERIPHC_2bh, - PERIPHC_2ch, - PERIPHC_SBC4, - PERIPHC_I2C3, - PERIPHC_SDMMC3, - - /* 0x30 */ - PERIPHC_UART4, - PERIPHC_UART5, - PERIPHC_VDE, - PERIPHC_OWR, - PERIPHC_NOR, - PERIPHC_CSITE, - PERIPHC_I2S1, - PERIPHC_DTV, - - /* 0x38 */ - PERIPHC_38h, - PERIPHC_39h, - PERIPHC_3ah, - PERIPHC_3bh, - PERIPHC_MSENC, - PERIPHC_TSEC, - PERIPHC_3eh, - PERIPHC_OSC, - - PERIPHC_VW_FIRST, - /* 0x40 */ - PERIPHC_40h = PERIPHC_VW_FIRST, - PERIPHC_MSELECT, - PERIPHC_TSENSOR, - PERIPHC_I2S4, - PERIPHC_I2S5, - PERIPHC_I2C4, - PERIPHC_SBC5, - PERIPHC_SBC6, - - /* 0x48 */ - PERIPHC_AUDIO, - PERIPHC_49h, - PERIPHC_4ah, - PERIPHC_4bh, - PERIPHC_4ch, - PERIPHC_HDA2CODEC2X, - PERIPHC_ACTMON, - PERIPHC_EXTPERIPH1, - - /* 0x50 */ - PERIPHC_EXTPERIPH2, - PERIPHC_EXTPERIPH3, - PERIPHC_52h, - PERIPHC_I2CSLOW, - PERIPHC_SYS, - PERIPHC_55h, - PERIPHC_56h, - PERIPHC_57h, - - /* 0x58 */ - PERIPHC_58h, - PERIPHC_59h, - PERIPHC_5ah, - PERIPHC_5bh, - PERIPHC_SATAOOB, - PERIPHC_SATA, - PERIPHC_HDA, /* 0x428 */ - PERIPHC_5fh, - - PERIPHC_X_FIRST, - /* 0x60 */ - PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ - PERIPHC_XUSB_FALCON, - PERIPHC_XUSB_FS, - PERIPHC_XUSB_CORE_DEV, - PERIPHC_XUSB_SS, - PERIPHC_CILAB, - PERIPHC_CILCD, - PERIPHC_CILE, - - /* 0x68 */ - PERIPHC_DSIA_LP, - PERIPHC_DSIB_LP, - PERIPHC_ENTROPY, - PERIPHC_DVFS_REF, - PERIPHC_DVFS_SOC, - PERIPHC_TRACECLKIN, - PERIPHC_6Eh, - PERIPHC_6Fh, - - /* 0x70 */ - PERIPHC_EMC_LATENCY, - PERIPHC_SOC_THERM, - PERIPHC_72h, - PERIPHC_73h, - PERIPHC_74h, - PERIPHC_75h, - PERIPHC_VI_SENSOR2, - PERIPHC_I2C6, - - /* 0x78 */ - PERIPHC_78h, - PERIPHC_EMC_DLL, - PERIPHC_7ah, - PERIPHC_CLK72MHZ, - PERIPHC_7ch, - PERIPHC_7dh, - PERIPHC_VIC, - PERIPHC_7fh, - - PERIPHC_Y_FIRST, - /* 0x80 */ - PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */ - PERIPHC_NVDEC, /* 0x698 */ - PERIPHC_NVJPG, /* 0x69c */ - PERIPHC_NVENC, /* 0x6a0 */ - PERIPHC_84h, - PERIPHC_85h, - PERIPHC_86h, - PERIPHC_87h, - - /* 0x88 */ - PERIPHC_88h, - PERIPHC_89h, - PERIPHC_DMIC3, /* 0x6bc: */ - PERIPHC_APE, /* 0x6c0: */ - PERIPHC_QSPI, /* 0x6c4: */ - PERIPHC_VI_I2C, /* 0x6c8: */ - PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */ - PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */ - - /* 0x90 */ - PERIPHC_MAUD, /* 0x6d4: */ - PERIPHC_TSECB, /* 0x6d8: */ - - PERIPHC_COUNT, - PERIPHC_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ -#define PERIPH_REG(id) \ - (id < PERIPH_ID_VW_FIRST) ? \ - ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _TEGRA210_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h deleted file mode 100644 index 438a6f4..0000000 --- a/arch/arm/include/asm/arch-tegra210/clock.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra210 clock control definitions */ - -#ifndef _TEGRA210_CLOCK_H_ -#define _TEGRA210_CLOCK_H_ - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) - -/* PLL bits that differ from generic clk_rst.h */ -#define PLLC_RESET 30 -#define PLLC_IDDQ 27 -#define PLLD_ENABLE_CLK 21 -#define PLLD_EN_LCKDET 28 - -int tegra_plle_enable(void); - -#endif /* _TEGRA210_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/include/asm/arch-tegra210/flow.h deleted file mode 100644 index ef0be19..0000000 --- a/arch/arm/include/asm/arch-tegra210/flow.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA210_FLOW_H_ -#define _TEGRA210_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; /* offset 0x00 */ - u32 halt_cop_events; /* offset 0x04 */ - u32 cpu_csr; /* offset 0x08 */ - u32 cop_csr; /* offset 0x0c */ - u32 xrq_events; /* offset 0x10 */ - u32 halt_cpu1_events; /* offset 0x14 */ - u32 cpu1_csr; /* offset 0x18 */ - u32 halt_cpu2_events; /* offset 0x1c */ - u32 cpu2_csr; /* offset 0x20 */ - u32 halt_cpu3_events; /* offset 0x24 */ - u32 cpu3_csr; /* offset 0x28 */ - u32 cluster_control; /* offset 0x2c */ - u32 halt_cop1_events; /* offset 0x30 */ - u32 halt_cop1_csr; /* offset 0x34 */ - u32 cpu_pwr_csr; /* offset 0x38 */ - u32 mpid; /* offset 0x3c */ - u32 ram_repair; /* offset 0x40 */ -}; - -/* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) -#define EVENT_MODE_STOP (2 << 29) - -/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) - -/* CPUn_CSR_0 */ -#define CSR_ENABLE (1 << 0) -#define CSR_IMMEDIATE_WAKE (1 << 3) -#define CSR_WAIT_WFI_SHIFT 8 - -#endif /* _TEGRA210_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h b/arch/arm/include/asm/arch-tegra210/funcmux.h deleted file mode 100644 index f6270e5..0000000 --- a/arch/arm/include/asm/arch-tegra210/funcmux.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra210 high-level function multiplexing */ - -#ifndef _TEGRA210_FUNCMUX_H_ -#define _TEGRA210_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_UART1 = 0, - FUNCMUX_UART4_UART4 = 0, -}; -#endif /* _TEGRA210_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h deleted file mode 100644 index e9ff903..0000000 --- a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA210_GP_PADCTRL_H_ -#define _TEGRA210_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - -#endif /* _TEGRA210_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h deleted file mode 100644 index cb91b10..0000000 --- a/arch/arm/include/asm/arch-tegra210/gpio.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA210_GPIO_H_ -#define _TEGRA210_GPIO_H_ - -/* - * The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* _TEGRA210_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h deleted file mode 100644 index 5a2a568..0000000 --- a/arch/arm/include/asm/arch-tegra210/mc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA210_MC_H_ -#define _TEGRA210_MC_H_ - -/** - * Defines the memory controller registers we need/care about - */ -struct mc_ctlr { - u32 reserved0[4]; /* offset 0x00 - 0x0C */ - u32 mc_smmu_config; /* offset 0x10 */ - u32 mc_smmu_tlb_config; /* offset 0x14 */ - u32 mc_smmu_ptc_config; /* offset 0x18 */ - u32 mc_smmu_ptb_asid; /* offset 0x1C */ - u32 mc_smmu_ptb_data; /* offset 0x20 */ - u32 reserved1[3]; /* offset 0x24 - 0x2C */ - u32 mc_smmu_tlb_flush; /* offset 0x30 */ - u32 mc_smmu_ptc_flush; /* offset 0x34 */ - u32 reserved2[6]; /* offset 0x38 - 0x4C */ - u32 mc_emem_cfg; /* offset 0x50 */ - u32 mc_emem_adr_cfg; /* offset 0x54 */ - u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ - u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ - u32 reserved3[4]; /* offset 0x60 - 0x6C */ - u32 mc_security_cfg0; /* offset 0x70 */ - u32 mc_security_cfg1; /* offset 0x74 */ - u32 reserved4[6]; /* offset 0x7C - 0x8C */ - u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ - u32 reserved5[74]; /* offset 0x100 - 0x224 */ - u32 mc_smmu_translation_enable_0; /* offset 0x228 */ - u32 mc_smmu_translation_enable_1; /* offset 0x22C */ - u32 mc_smmu_translation_enable_2; /* offset 0x230 */ - u32 mc_smmu_translation_enable_3; /* offset 0x234 */ - u32 mc_smmu_afi_asid; /* offset 0x238 */ - u32 mc_smmu_avpc_asid; /* offset 0x23C */ - u32 mc_smmu_dc_asid; /* offset 0x240 */ - u32 mc_smmu_dcb_asid; /* offset 0x244 */ - u32 reserved6[2]; /* offset 0x248 - 0x24C */ - u32 mc_smmu_hc_asid; /* offset 0x250 */ - u32 mc_smmu_hda_asid; /* offset 0x254 */ - u32 mc_smmu_isp2_asid; /* offset 0x258 */ - u32 reserved7[2]; /* offset 0x25C - 0x260 */ - u32 mc_smmu_msenc_asid; /* offset 0x264 */ - u32 mc_smmu_nv_asid; /* offset 0x268 */ - u32 mc_smmu_nv2_asid; /* offset 0x26C */ - u32 mc_smmu_ppcs_asid; /* offset 0x270 */ - u32 mc_smmu_sata_asid; /* offset 0x274 */ - u32 reserved8[1]; /* offset 0x278 */ - u32 mc_smmu_vde_asid; /* offset 0x27C */ - u32 mc_smmu_vi_asid; /* offset 0x280 */ - u32 mc_smmu_vic_asid; /* offset 0x284 */ - u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ - u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ - u32 reserved9[1]; /* offset 0x290 */ - u32 mc_smmu_tsec_asid; /* offset 0x294 */ - u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ - u32 reserved10[235]; /* offset 0x29C - 0x644 */ - u32 mc_video_protect_bom; /* offset 0x648 */ - u32 mc_video_protect_size_mb; /* offset 0x64c */ - u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ -}; - -#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) - -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) - -#endif /* _TEGRA210_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h deleted file mode 100644 index 9e94074..0000000 --- a/arch/arm/include/asm/arch-tegra210/pinmux.h +++ /dev/null @@ -1,415 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA210_PINMUX_H_ -#define _TEGRA210_PINMUX_H_ - -enum pmux_pingrp { - PMUX_PINGRP_SDMMC1_CLK_PM0, - PMUX_PINGRP_SDMMC1_CMD_PM1, - PMUX_PINGRP_SDMMC1_DAT3_PM2, - PMUX_PINGRP_SDMMC1_DAT2_PM3, - PMUX_PINGRP_SDMMC1_DAT1_PM4, - PMUX_PINGRP_SDMMC1_DAT0_PM5, - PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4), - PMUX_PINGRP_SDMMC3_CMD_PP1, - PMUX_PINGRP_SDMMC3_DAT0_PP5, - PMUX_PINGRP_SDMMC3_DAT1_PP4, - PMUX_PINGRP_SDMMC3_DAT2_PP3, - PMUX_PINGRP_SDMMC3_DAT3_PP2, - PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4), - PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1, - PMUX_PINGRP_PEX_WAKE_N_PA2, - PMUX_PINGRP_PEX_L1_RST_N_PA3, - PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4, - PMUX_PINGRP_SATA_LED_ACTIVE_PA5, - PMUX_PINGRP_SPI1_MOSI_PC0, - PMUX_PINGRP_SPI1_MISO_PC1, - PMUX_PINGRP_SPI1_SCK_PC2, - PMUX_PINGRP_SPI1_CS0_PC3, - PMUX_PINGRP_SPI1_CS1_PC4, - PMUX_PINGRP_SPI2_MOSI_PB4, - PMUX_PINGRP_SPI2_MISO_PB5, - PMUX_PINGRP_SPI2_SCK_PB6, - PMUX_PINGRP_SPI2_CS0_PB7, - PMUX_PINGRP_SPI2_CS1_PDD0, - PMUX_PINGRP_SPI4_MOSI_PC7, - PMUX_PINGRP_SPI4_MISO_PD0, - PMUX_PINGRP_SPI4_SCK_PC5, - PMUX_PINGRP_SPI4_CS0_PC6, - PMUX_PINGRP_QSPI_SCK_PEE0, - PMUX_PINGRP_QSPI_CS_N_PEE1, - PMUX_PINGRP_QSPI_IO0_PEE2, - PMUX_PINGRP_QSPI_IO1_PEE3, - PMUX_PINGRP_QSPI_IO2_PEE4, - PMUX_PINGRP_QSPI_IO3_PEE5, - PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4), - PMUX_PINGRP_DMIC1_DAT_PE1, - PMUX_PINGRP_DMIC2_CLK_PE2, - PMUX_PINGRP_DMIC2_DAT_PE3, - PMUX_PINGRP_DMIC3_CLK_PE4, - PMUX_PINGRP_DMIC3_DAT_PE5, - PMUX_PINGRP_GEN1_I2C_SCL_PJ1, - PMUX_PINGRP_GEN1_I2C_SDA_PJ0, - PMUX_PINGRP_GEN2_I2C_SCL_PJ2, - PMUX_PINGRP_GEN2_I2C_SDA_PJ3, - PMUX_PINGRP_GEN3_I2C_SCL_PF0, - PMUX_PINGRP_GEN3_I2C_SDA_PF1, - PMUX_PINGRP_CAM_I2C_SCL_PS2, - PMUX_PINGRP_CAM_I2C_SDA_PS3, - PMUX_PINGRP_PWR_I2C_SCL_PY3, - PMUX_PINGRP_PWR_I2C_SDA_PY4, - PMUX_PINGRP_UART1_TX_PU0, - PMUX_PINGRP_UART1_RX_PU1, - PMUX_PINGRP_UART1_RTS_PU2, - PMUX_PINGRP_UART1_CTS_PU3, - PMUX_PINGRP_UART2_TX_PG0, - PMUX_PINGRP_UART2_RX_PG1, - PMUX_PINGRP_UART2_RTS_PG2, - PMUX_PINGRP_UART2_CTS_PG3, - PMUX_PINGRP_UART3_TX_PD1, - PMUX_PINGRP_UART3_RX_PD2, - PMUX_PINGRP_UART3_RTS_PD3, - PMUX_PINGRP_UART3_CTS_PD4, - PMUX_PINGRP_UART4_TX_PI4, - PMUX_PINGRP_UART4_RX_PI5, - PMUX_PINGRP_UART4_RTS_PI6, - PMUX_PINGRP_UART4_CTS_PI7, - PMUX_PINGRP_DAP1_FS_PB0, - PMUX_PINGRP_DAP1_DIN_PB1, - PMUX_PINGRP_DAP1_DOUT_PB2, - PMUX_PINGRP_DAP1_SCLK_PB3, - PMUX_PINGRP_DAP2_FS_PAA0, - PMUX_PINGRP_DAP2_DIN_PAA2, - PMUX_PINGRP_DAP2_DOUT_PAA3, - PMUX_PINGRP_DAP2_SCLK_PAA1, - PMUX_PINGRP_DAP4_FS_PJ4, - PMUX_PINGRP_DAP4_DIN_PJ5, - PMUX_PINGRP_DAP4_DOUT_PJ6, - PMUX_PINGRP_DAP4_SCLK_PJ7, - PMUX_PINGRP_CAM1_MCLK_PS0, - PMUX_PINGRP_CAM2_MCLK_PS1, - PMUX_PINGRP_JTAG_RTCK, - PMUX_PINGRP_CLK_32K_IN, - PMUX_PINGRP_CLK_32K_OUT_PY5, - PMUX_PINGRP_BATT_BCL, - PMUX_PINGRP_CLK_REQ, - PMUX_PINGRP_CPU_PWR_REQ, - PMUX_PINGRP_PWR_INT_N, - PMUX_PINGRP_SHUTDOWN, - PMUX_PINGRP_CORE_PWR_REQ, - PMUX_PINGRP_AUD_MCLK_PBB0, - PMUX_PINGRP_DVFS_PWM_PBB1, - PMUX_PINGRP_DVFS_CLK_PBB2, - PMUX_PINGRP_GPIO_X1_AUD_PBB3, - PMUX_PINGRP_GPIO_X3_AUD_PBB4, - PMUX_PINGRP_PCC7, - PMUX_PINGRP_HDMI_CEC_PCC0, - PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1, - PMUX_PINGRP_SPDIF_OUT_PCC2, - PMUX_PINGRP_SPDIF_IN_PCC3, - PMUX_PINGRP_USB_VBUS_EN0_PCC4, - PMUX_PINGRP_USB_VBUS_EN1_PCC5, - PMUX_PINGRP_DP_HPD0_PCC6, - PMUX_PINGRP_WIFI_EN_PH0, - PMUX_PINGRP_WIFI_RST_PH1, - PMUX_PINGRP_WIFI_WAKE_AP_PH2, - PMUX_PINGRP_AP_WAKE_BT_PH3, - PMUX_PINGRP_BT_RST_PH4, - PMUX_PINGRP_BT_WAKE_AP_PH5, - PMUX_PINGRP_AP_WAKE_NFC_PH7, - PMUX_PINGRP_NFC_EN_PI0, - PMUX_PINGRP_NFC_INT_PI1, - PMUX_PINGRP_GPS_EN_PI2, - PMUX_PINGRP_GPS_RST_PI3, - PMUX_PINGRP_CAM_RST_PS4, - PMUX_PINGRP_CAM_AF_EN_PS5, - PMUX_PINGRP_CAM_FLASH_EN_PS6, - PMUX_PINGRP_CAM1_PWDN_PS7, - PMUX_PINGRP_CAM2_PWDN_PT0, - PMUX_PINGRP_CAM1_STROBE_PT1, - PMUX_PINGRP_LCD_TE_PY2, - PMUX_PINGRP_LCD_BL_PWM_PV0, - PMUX_PINGRP_LCD_BL_EN_PV1, - PMUX_PINGRP_LCD_RST_PV2, - PMUX_PINGRP_LCD_GPIO1_PV3, - PMUX_PINGRP_LCD_GPIO2_PV4, - PMUX_PINGRP_AP_READY_PV5, - PMUX_PINGRP_TOUCH_RST_PV6, - PMUX_PINGRP_TOUCH_CLK_PV7, - PMUX_PINGRP_MODEM_WAKE_AP_PX0, - PMUX_PINGRP_TOUCH_INT_PX1, - PMUX_PINGRP_MOTION_INT_PX2, - PMUX_PINGRP_ALS_PROX_INT_PX3, - PMUX_PINGRP_TEMP_ALERT_PX4, - PMUX_PINGRP_BUTTON_POWER_ON_PX5, - PMUX_PINGRP_BUTTON_VOL_UP_PX6, - PMUX_PINGRP_BUTTON_VOL_DOWN_PX7, - PMUX_PINGRP_BUTTON_SLIDE_SW_PY0, - PMUX_PINGRP_BUTTON_HOME_PY1, - PMUX_PINGRP_PA6, - PMUX_PINGRP_PE6, - PMUX_PINGRP_PE7, - PMUX_PINGRP_PH6, - PMUX_PINGRP_PK0, - PMUX_PINGRP_PK1, - PMUX_PINGRP_PK2, - PMUX_PINGRP_PK3, - PMUX_PINGRP_PK4, - PMUX_PINGRP_PK5, - PMUX_PINGRP_PK6, - PMUX_PINGRP_PK7, - PMUX_PINGRP_PL0, - PMUX_PINGRP_PL1, - PMUX_PINGRP_PZ0, - PMUX_PINGRP_PZ1, - PMUX_PINGRP_PZ2, - PMUX_PINGRP_PZ3, - PMUX_PINGRP_PZ4, - PMUX_PINGRP_PZ5, - PMUX_PINGRP_COUNT, -}; - -enum pmux_drvgrp { - PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4), - PMUX_DRVGRP_AP_READY, - PMUX_DRVGRP_AP_WAKE_BT, - PMUX_DRVGRP_AP_WAKE_NFC, - PMUX_DRVGRP_AUD_MCLK, - PMUX_DRVGRP_BATT_BCL, - PMUX_DRVGRP_BT_RST, - PMUX_DRVGRP_BT_WAKE_AP, - PMUX_DRVGRP_BUTTON_HOME, - PMUX_DRVGRP_BUTTON_POWER_ON, - PMUX_DRVGRP_BUTTON_SLIDE_SW, - PMUX_DRVGRP_BUTTON_VOL_DOWN, - PMUX_DRVGRP_BUTTON_VOL_UP, - PMUX_DRVGRP_CAM1_MCLK, - PMUX_DRVGRP_CAM1_PWDN, - PMUX_DRVGRP_CAM1_STROBE, - PMUX_DRVGRP_CAM2_MCLK, - PMUX_DRVGRP_CAM2_PWDN, - PMUX_DRVGRP_CAM_AF_EN, - PMUX_DRVGRP_CAM_FLASH_EN, - PMUX_DRVGRP_CAM_I2C_SCL, - PMUX_DRVGRP_CAM_I2C_SDA, - PMUX_DRVGRP_CAM_RST, - PMUX_DRVGRP_CLK_32K_IN, - PMUX_DRVGRP_CLK_32K_OUT, - PMUX_DRVGRP_CLK_REQ, - PMUX_DRVGRP_CORE_PWR_REQ, - PMUX_DRVGRP_CPU_PWR_REQ, - PMUX_DRVGRP_DAP1_DIN, - PMUX_DRVGRP_DAP1_DOUT, - PMUX_DRVGRP_DAP1_FS, - PMUX_DRVGRP_DAP1_SCLK, - PMUX_DRVGRP_DAP2_DIN, - PMUX_DRVGRP_DAP2_DOUT, - PMUX_DRVGRP_DAP2_FS, - PMUX_DRVGRP_DAP2_SCLK, - PMUX_DRVGRP_DAP4_DIN, - PMUX_DRVGRP_DAP4_DOUT, - PMUX_DRVGRP_DAP4_FS, - PMUX_DRVGRP_DAP4_SCLK, - PMUX_DRVGRP_DMIC1_CLK, - PMUX_DRVGRP_DMIC1_DAT, - PMUX_DRVGRP_DMIC2_CLK, - PMUX_DRVGRP_DMIC2_DAT, - PMUX_DRVGRP_DMIC3_CLK, - PMUX_DRVGRP_DMIC3_DAT, - PMUX_DRVGRP_DP_HPD0, - PMUX_DRVGRP_DVFS_CLK, - PMUX_DRVGRP_DVFS_PWM, - PMUX_DRVGRP_GEN1_I2C_SCL, - PMUX_DRVGRP_GEN1_I2C_SDA, - PMUX_DRVGRP_GEN2_I2C_SCL, - PMUX_DRVGRP_GEN2_I2C_SDA, - PMUX_DRVGRP_GEN3_I2C_SCL, - PMUX_DRVGRP_GEN3_I2C_SDA, - PMUX_DRVGRP_PA6, - PMUX_DRVGRP_PCC7, - PMUX_DRVGRP_PE6, - PMUX_DRVGRP_PE7, - PMUX_DRVGRP_PH6, - PMUX_DRVGRP_PK0, - PMUX_DRVGRP_PK1, - PMUX_DRVGRP_PK2, - PMUX_DRVGRP_PK3, - PMUX_DRVGRP_PK4, - PMUX_DRVGRP_PK5, - PMUX_DRVGRP_PK6, - PMUX_DRVGRP_PK7, - PMUX_DRVGRP_PL0, - PMUX_DRVGRP_PL1, - PMUX_DRVGRP_PZ0, - PMUX_DRVGRP_PZ1, - PMUX_DRVGRP_PZ2, - PMUX_DRVGRP_PZ3, - PMUX_DRVGRP_PZ4, - PMUX_DRVGRP_PZ5, - PMUX_DRVGRP_GPIO_X1_AUD, - PMUX_DRVGRP_GPIO_X3_AUD, - PMUX_DRVGRP_GPS_EN, - PMUX_DRVGRP_GPS_RST, - PMUX_DRVGRP_HDMI_CEC, - PMUX_DRVGRP_HDMI_INT_DP_HPD, - PMUX_DRVGRP_JTAG_RTCK, - PMUX_DRVGRP_LCD_BL_EN, - PMUX_DRVGRP_LCD_BL_PWM, - PMUX_DRVGRP_LCD_GPIO1, - PMUX_DRVGRP_LCD_GPIO2, - PMUX_DRVGRP_LCD_RST, - PMUX_DRVGRP_LCD_TE, - PMUX_DRVGRP_MODEM_WAKE_AP, - PMUX_DRVGRP_MOTION_INT, - PMUX_DRVGRP_NFC_EN, - PMUX_DRVGRP_NFC_INT, - PMUX_DRVGRP_PEX_L0_CLKREQ_N, - PMUX_DRVGRP_PEX_L0_RST_N, - PMUX_DRVGRP_PEX_L1_CLKREQ_N, - PMUX_DRVGRP_PEX_L1_RST_N, - PMUX_DRVGRP_PEX_WAKE_N, - PMUX_DRVGRP_PWR_I2C_SCL, - PMUX_DRVGRP_PWR_I2C_SDA, - PMUX_DRVGRP_PWR_INT_N, - PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4), - PMUX_DRVGRP_SATA_LED_ACTIVE, - PMUX_DRVGRP_SDMMC1, - PMUX_DRVGRP_SDMMC2, - PMUX_DRVGRP_SDMMC3 = (0x1dc / 4), - PMUX_DRVGRP_SDMMC4, - PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4), - PMUX_DRVGRP_SPDIF_IN, - PMUX_DRVGRP_SPDIF_OUT, - PMUX_DRVGRP_SPI1_CS0, - PMUX_DRVGRP_SPI1_CS1, - PMUX_DRVGRP_SPI1_MISO, - PMUX_DRVGRP_SPI1_MOSI, - PMUX_DRVGRP_SPI1_SCK, - PMUX_DRVGRP_SPI2_CS0, - PMUX_DRVGRP_SPI2_CS1, - PMUX_DRVGRP_SPI2_MISO, - PMUX_DRVGRP_SPI2_MOSI, - PMUX_DRVGRP_SPI2_SCK, - PMUX_DRVGRP_SPI4_CS0, - PMUX_DRVGRP_SPI4_MISO, - PMUX_DRVGRP_SPI4_MOSI, - PMUX_DRVGRP_SPI4_SCK, - PMUX_DRVGRP_TEMP_ALERT, - PMUX_DRVGRP_TOUCH_CLK, - PMUX_DRVGRP_TOUCH_INT, - PMUX_DRVGRP_TOUCH_RST, - PMUX_DRVGRP_UART1_CTS, - PMUX_DRVGRP_UART1_RTS, - PMUX_DRVGRP_UART1_RX, - PMUX_DRVGRP_UART1_TX, - PMUX_DRVGRP_UART2_CTS, - PMUX_DRVGRP_UART2_RTS, - PMUX_DRVGRP_UART2_RX, - PMUX_DRVGRP_UART2_TX, - PMUX_DRVGRP_UART3_CTS, - PMUX_DRVGRP_UART3_RTS, - PMUX_DRVGRP_UART3_RX, - PMUX_DRVGRP_UART3_TX, - PMUX_DRVGRP_UART4_CTS, - PMUX_DRVGRP_UART4_RTS, - PMUX_DRVGRP_UART4_RX, - PMUX_DRVGRP_UART4_TX, - PMUX_DRVGRP_USB_VBUS_EN0, - PMUX_DRVGRP_USB_VBUS_EN1, - PMUX_DRVGRP_WIFI_EN, - PMUX_DRVGRP_WIFI_RST, - PMUX_DRVGRP_WIFI_WAKE_AP, - PMUX_DRVGRP_COUNT, -}; - -enum pmux_func { - PMUX_FUNC_DEFAULT, - PMUX_FUNC_AUD, - PMUX_FUNC_BCL, - PMUX_FUNC_BLINK, - PMUX_FUNC_CCLA, - PMUX_FUNC_CEC, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_CLK, - PMUX_FUNC_CORE, - PMUX_FUNC_CPU, - PMUX_FUNC_DISPLAYA, - PMUX_FUNC_DISPLAYB, - PMUX_FUNC_DMIC1, - PMUX_FUNC_DMIC2, - PMUX_FUNC_DMIC3, - PMUX_FUNC_DP, - PMUX_FUNC_DTV, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_I2CPMU, - PMUX_FUNC_I2CVI, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4A, - PMUX_FUNC_I2S4B, - PMUX_FUNC_I2S5A, - PMUX_FUNC_I2S5B, - PMUX_FUNC_IQC0, - PMUX_FUNC_IQC1, - PMUX_FUNC_JTAG, - PMUX_FUNC_PE, - PMUX_FUNC_PE0, - PMUX_FUNC_PE1, - PMUX_FUNC_PMI, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_QSPI, - PMUX_FUNC_SATA, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SHUTDOWN, - PMUX_FUNC_SOC, - PMUX_FUNC_SOR0, - PMUX_FUNC_SOR1, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_SYS, - PMUX_FUNC_TOUCH, - PMUX_FUNC_UART, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_USB, - PMUX_FUNC_VGP1, - PMUX_FUNC_VGP2, - PMUX_FUNC_VGP3, - PMUX_FUNC_VGP4, - PMUX_FUNC_VGP5, - PMUX_FUNC_VGP6, - PMUX_FUNC_VIMCLK, - PMUX_FUNC_VIMCLK2, - PMUX_FUNC_RSVD0, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4 -#define TEGRA_PMX_SOC_HAS_IO_CLAMPING -#define TEGRA_PMX_SOC_HAS_DRVGRPS -#define TEGRA_PMX_PINS_HAVE_E_INPUT -#define TEGRA_PMX_PINS_HAVE_LOCK -#define TEGRA_PMX_PINS_HAVE_OD -#define TEGRA_PMX_PINS_HAVE_E_IO_HV -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA210_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/powergate.h b/arch/arm/include/asm/arch-tegra210/powergate.h deleted file mode 100644 index ec8f518..0000000 --- a/arch/arm/include/asm/arch-tegra210/powergate.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA210_POWERGATE_H_ -#define _TEGRA210_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA210_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/sysctr.h b/arch/arm/include/asm/arch-tegra210/sysctr.h deleted file mode 100644 index cb1c499..0000000 --- a/arch/arm/include/asm/arch-tegra210/sysctr.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA210_SYSCTR_H_ -#define _TEGRA210_SYSCTR_H_ - -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ - -#endif /* _TEGRA210_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h deleted file mode 100644 index 1c6fba6..0000000 --- a/arch/arm/include/asm/arch-tegra210/tegra.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA210_TEGRA_H_ -#define _TEGRA210_TEGRA_H_ - -#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ -#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ -#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ -#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ -#define NV_PA_SDRAM_BASE 0x80000000 - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 -#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) - -#define TEGRA_USB1_BASE 0x7D000000 - -#endif /* _TEGRA210_TEGRA_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h deleted file mode 100644 index 8588009..0000000 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ /dev/null @@ -1,372 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra30 clock PLL tables */ - -#ifndef _TEGRA30_CLOCK_TABLES_H_ -#define _TEGRA30_CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - CLOCK_ID_CLK_M, - - CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_COP, - PERIPH_ID_TRIGSYS, - PERIPH_ID_RESERVED3, - PERIPH_ID_RESERVED4, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_RESERVED16, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_RESERVED24, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_I2S0, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_RESERVED43, - PERIPH_ID_SBC2, - PERIPH_ID_RESERVED45, - PERIPH_ID_SBC3, - PERIPH_ID_DVC_I2C, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_DTV, - - /* 80 */ - PERIPH_ID_NANDSPEED, - PERIPH_ID_I2CSLOW, - PERIPH_ID_DSIB, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_RESERVED89, - PERIPH_ID_MDOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUSOUT, - PERIPH_ID_RESERVED93, - PERIPH_ID_RESERVED94, - PERIPH_ID_RESERVED95, - - PERIPH_ID_VW_FIRST, - /* V word: 31:0 */ - PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, - PERIPH_ID_CPULP, - PERIPH_ID_3D2, - PERIPH_ID_MSELECT, - PERIPH_ID_TSENSOR, - PERIPH_ID_I2S3, - PERIPH_ID_I2S4, - PERIPH_ID_I2C4, - - /* 08 */ - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - PERIPH_ID_AUDIO, - PERIPH_ID_APBIF, - PERIPH_ID_DAM0, - PERIPH_ID_DAM1, - PERIPH_ID_DAM2, - PERIPH_ID_HDA2CODEC2X, - - /* 16 */ - PERIPH_ID_ATOMICS, - PERIPH_ID_EX_RESERVED17, - PERIPH_ID_EX_RESERVED18, - PERIPH_ID_EX_RESERVED19, - PERIPH_ID_EX_RESERVED20, - PERIPH_ID_EX_RESERVED21, - PERIPH_ID_EX_RESERVED22, - PERIPH_ID_ACTMON, - - /* 24 */ - PERIPH_ID_EX_RESERVED24, - PERIPH_ID_EX_RESERVED25, - PERIPH_ID_EX_RESERVED26, - PERIPH_ID_EX_RESERVED27, - PERIPH_ID_SATA, - PERIPH_ID_HDA, - PERIPH_ID_EX_RESERVED30, - PERIPH_ID_EX_RESERVED31, - - /* W word: 31:0 */ - PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_SATACOLD, - PERIPH_ID_RESERVED0_PCIERX0, - PERIPH_ID_RESERVED1_PCIERX1, - PERIPH_ID_RESERVED2_PCIERX2, - PERIPH_ID_RESERVED3_PCIERX3, - PERIPH_ID_RESERVED4_PCIERX4, - PERIPH_ID_RESERVED5_PCIERX5, - - /* 40 */ - PERIPH_ID_CEC, - PERIPH_ID_RESERVED6_PCIE2, - PERIPH_ID_RESERVED7_EMC, - PERIPH_ID_RESERVED8_HDMI, - PERIPH_ID_RESERVED9_SATA, - PERIPH_ID_RESERVED10_MIPI, - PERIPH_ID_EX_RESERVED46, - PERIPH_ID_EX_RESERVED47, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid - * confusion bewteen PERIPH_ID_... and PERIPHC_... - * - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be - * confusing. - */ -enum periphc_internal_id { - /* 0x00 */ - PERIPHC_I2S1, - PERIPHC_I2S2, - PERIPHC_SPDIF_OUT, - PERIPHC_SPDIF_IN, - PERIPHC_PWM, - PERIPHC_05h, - PERIPHC_SBC2, - PERIPHC_SBC3, - - /* 0x08 */ - PERIPHC_08h, - PERIPHC_I2C1, - PERIPHC_DVC_I2C, - PERIPHC_0bh, - PERIPHC_0ch, - PERIPHC_SBC1, - PERIPHC_DISP1, - PERIPHC_DISP2, - - /* 0x10 */ - PERIPHC_CVE, - PERIPHC_11h, - PERIPHC_VI, - PERIPHC_13h, - PERIPHC_SDMMC1, - PERIPHC_SDMMC2, - PERIPHC_G3D, - PERIPHC_G2D, - - /* 0x18 */ - PERIPHC_NDFLASH, - PERIPHC_SDMMC4, - PERIPHC_VFIR, - PERIPHC_EPP, - PERIPHC_MPE, - PERIPHC_MIPI, - PERIPHC_UART1, - PERIPHC_UART2, - - /* 0x20 */ - PERIPHC_HOST1X, - PERIPHC_21h, - PERIPHC_TVO, - PERIPHC_HDMI, - PERIPHC_24h, - PERIPHC_TVDAC, - PERIPHC_I2C2, - PERIPHC_EMC, - - /* 0x28 */ - PERIPHC_UART3, - PERIPHC_29h, - PERIPHC_VI_SENSOR, - PERIPHC_2bh, - PERIPHC_2ch, - PERIPHC_SBC4, - PERIPHC_I2C3, - PERIPHC_SDMMC3, - - /* 0x30 */ - PERIPHC_UART4, - PERIPHC_UART5, - PERIPHC_VDE, - PERIPHC_OWR, - PERIPHC_NOR, - PERIPHC_CSITE, - PERIPHC_I2S0, - PERIPHC_37h, - - PERIPHC_VW_FIRST, - /* 0x38 */ - PERIPHC_G3D2 = PERIPHC_VW_FIRST, - PERIPHC_MSELECT, - PERIPHC_TSENSOR, - PERIPHC_I2S3, - PERIPHC_I2S4, - PERIPHC_I2C4, - PERIPHC_SBC5, - PERIPHC_SBC6, - - /* 0x40 */ - PERIPHC_AUDIO, - PERIPHC_41h, - PERIPHC_DAM0, - PERIPHC_DAM1, - PERIPHC_DAM2, - PERIPHC_HDA2CODEC2X, - PERIPHC_ACTMON, - PERIPHC_EXTPERIPH1, - - /* 0x48 */ - PERIPHC_EXTPERIPH2, - PERIPHC_EXTPERIPH3, - PERIPHC_NANDSPEED, - PERIPHC_I2CSLOW, - PERIPHC_SYS, - PERIPHC_SPEEDO, - PERIPHC_4eh, - PERIPHC_4fh, - - /* 0x50 */ - PERIPHC_50h, - PERIPHC_51h, - PERIPHC_52h, - PERIPHC_53h, - PERIPHC_SATAOOB, - PERIPHC_SATA, - PERIPHC_HDA, - - PERIPHC_COUNT, - - PERIPHC_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ -#define PERIPH_REG(id) \ - (id < PERIPH_ID_VW_FIRST) ? \ - ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _TEGRA30_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h deleted file mode 100644 index 7f5a115..0000000 --- a/arch/arm/include/asm/arch-tegra30/clock.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra30 clock control functions */ - -#ifndef _TEGRA30_CLOCK_H_ -#define _TEGRA30_CLOCK_H_ - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) - -int tegra_plle_enable(void); - -#endif /* _TEGRA30_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h deleted file mode 100644 index f3e947e..0000000 --- a/arch/arm/include/asm/arch-tegra30/flow.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA30_FLOW_H_ -#define _TEGRA30_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 xrq_events; - u32 halt_cpu1_events; - u32 cpu1_csr; - u32 halt_cpu2_events; - u32 cpu2_csr; - u32 halt_cpu3_events; - u32 cpu3_csr; - u32 cluster_control; -}; - -#endif /* _TEGRA30_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h deleted file mode 100644 index 2e8b335..0000000 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra30 high-level function multiplexing */ - -#ifndef _TEGRA30_FUNCMUX_H_ -#define _TEGRA30_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_ULPI = 0, -}; -#endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h deleted file mode 100644 index 4ff785d..0000000 --- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA30_GP_PADCTRL_H_ -#define _TEGRA30_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ - u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ - u32 reserved1[7]; /* 0xD0-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ -}; - -/* SDMMC1/3 settings from section 24.6 of T30 TRM */ -#define SDIOCFG_DRVUP_SLWF 1 -#define SDIOCFG_DRVDN_SLWR 1 -#define SDIOCFG_DRVUP 0x2E -#define SDIOCFG_DRVDN 0x2A - -#endif /* _TEGRA30_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h deleted file mode 100644 index 1dd2e42..0000000 --- a/arch/arm/include/asm/arch-tegra30/gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA30_GPIO_H_ -#define _TEGRA30_GPIO_H_ - -/* - * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#endif /* _TEGRA30_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h deleted file mode 100644 index bbb0fe7..0000000 --- a/arch/arm/include/asm/arch-tegra30/mc.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef _TEGRA30_MC_H_ -#define _TEGRA30_MC_H_ - -/** - * Defines the memory controller registers we need/care about - */ -struct mc_ctlr { - u32 reserved0[4]; /* offset 0x00 - 0x0C */ - u32 mc_smmu_config; /* offset 0x10 */ - u32 mc_smmu_tlb_config; /* offset 0x14 */ - u32 mc_smmu_ptc_config; /* offset 0x18 */ - u32 mc_smmu_ptb_asid; /* offset 0x1C */ - u32 mc_smmu_ptb_data; /* offset 0x20 */ - u32 reserved1[3]; /* offset 0x24 - 0x2C */ - u32 mc_smmu_tlb_flush; /* offset 0x30 */ - u32 mc_smmu_ptc_flush; /* offset 0x34 */ - u32 mc_smmu_asid_security; /* offset 0x38 */ - u32 reserved2[5]; /* offset 0x3C - 0x4C */ - u32 mc_emem_cfg; /* offset 0x50 */ - u32 mc_emem_adr_cfg; /* offset 0x54 */ - u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ - u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ - u32 reserved3[12]; /* offset 0x60 - 0x8C */ - u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ - u32 reserved4[338]; /* offset 0x100 - 0x644 */ - u32 mc_video_protect_bom; /* offset 0x648 */ - u32 mc_video_protect_size_mb; /* offset 0x64c */ - u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ -}; - -#endif /* _TEGRA30_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h deleted file mode 100644 index 1261943..0000000 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ /dev/null @@ -1,404 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA30_PINMUX_H_ -#define _TEGRA30_PINMUX_H_ - -enum pmux_pingrp { - PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_PINGRP_ULPI_DATA4_PO5, - PMUX_PINGRP_ULPI_DATA5_PO6, - PMUX_PINGRP_ULPI_DATA6_PO7, - PMUX_PINGRP_ULPI_DATA7_PO0, - PMUX_PINGRP_ULPI_CLK_PY0, - PMUX_PINGRP_ULPI_DIR_PY1, - PMUX_PINGRP_ULPI_NXT_PY2, - PMUX_PINGRP_ULPI_STP_PY3, - PMUX_PINGRP_DAP3_FS_PP0, - PMUX_PINGRP_DAP3_DIN_PP1, - PMUX_PINGRP_DAP3_DOUT_PP2, - PMUX_PINGRP_DAP3_SCLK_PP3, - PMUX_PINGRP_PV0, - PMUX_PINGRP_PV1, - PMUX_PINGRP_SDMMC1_CLK_PZ0, - PMUX_PINGRP_SDMMC1_CMD_PZ1, - PMUX_PINGRP_SDMMC1_DAT3_PY4, - PMUX_PINGRP_SDMMC1_DAT2_PY5, - PMUX_PINGRP_SDMMC1_DAT1_PY6, - PMUX_PINGRP_SDMMC1_DAT0_PY7, - PMUX_PINGRP_PV2, - PMUX_PINGRP_PV3, - PMUX_PINGRP_CLK2_OUT_PW5, - PMUX_PINGRP_CLK2_REQ_PCC5, - PMUX_PINGRP_LCD_PWR1_PC1, - PMUX_PINGRP_LCD_PWR2_PC6, - PMUX_PINGRP_LCD_SDIN_PZ2, - PMUX_PINGRP_LCD_SDOUT_PN5, - PMUX_PINGRP_LCD_WR_N_PZ3, - PMUX_PINGRP_LCD_CS0_N_PN4, - PMUX_PINGRP_LCD_DC0_PN6, - PMUX_PINGRP_LCD_SCK_PZ4, - PMUX_PINGRP_LCD_PWR0_PB2, - PMUX_PINGRP_LCD_PCLK_PB3, - PMUX_PINGRP_LCD_DE_PJ1, - PMUX_PINGRP_LCD_HSYNC_PJ3, - PMUX_PINGRP_LCD_VSYNC_PJ4, - PMUX_PINGRP_LCD_D0_PE0, - PMUX_PINGRP_LCD_D1_PE1, - PMUX_PINGRP_LCD_D2_PE2, - PMUX_PINGRP_LCD_D3_PE3, - PMUX_PINGRP_LCD_D4_PE4, - PMUX_PINGRP_LCD_D5_PE5, - PMUX_PINGRP_LCD_D6_PE6, - PMUX_PINGRP_LCD_D7_PE7, - PMUX_PINGRP_LCD_D8_PF0, - PMUX_PINGRP_LCD_D9_PF1, - PMUX_PINGRP_LCD_D10_PF2, - PMUX_PINGRP_LCD_D11_PF3, - PMUX_PINGRP_LCD_D12_PF4, - PMUX_PINGRP_LCD_D13_PF5, - PMUX_PINGRP_LCD_D14_PF6, - PMUX_PINGRP_LCD_D15_PF7, - PMUX_PINGRP_LCD_D16_PM0, - PMUX_PINGRP_LCD_D17_PM1, - PMUX_PINGRP_LCD_D18_PM2, - PMUX_PINGRP_LCD_D19_PM3, - PMUX_PINGRP_LCD_D20_PM4, - PMUX_PINGRP_LCD_D21_PM5, - PMUX_PINGRP_LCD_D22_PM6, - PMUX_PINGRP_LCD_D23_PM7, - PMUX_PINGRP_LCD_CS1_N_PW0, - PMUX_PINGRP_LCD_M1_PW1, - PMUX_PINGRP_LCD_DC1_PD2, - PMUX_PINGRP_HDMI_INT_PN7, - PMUX_PINGRP_DDC_SCL_PV4, - PMUX_PINGRP_DDC_SDA_PV5, - PMUX_PINGRP_CRT_HSYNC_PV6, - PMUX_PINGRP_CRT_VSYNC_PV7, - PMUX_PINGRP_VI_D0_PT4, - PMUX_PINGRP_VI_D1_PD5, - PMUX_PINGRP_VI_D2_PL0, - PMUX_PINGRP_VI_D3_PL1, - PMUX_PINGRP_VI_D4_PL2, - PMUX_PINGRP_VI_D5_PL3, - PMUX_PINGRP_VI_D6_PL4, - PMUX_PINGRP_VI_D7_PL5, - PMUX_PINGRP_VI_D8_PL6, - PMUX_PINGRP_VI_D9_PL7, - PMUX_PINGRP_VI_D10_PT2, - PMUX_PINGRP_VI_D11_PT3, - PMUX_PINGRP_VI_PCLK_PT0, - PMUX_PINGRP_VI_MCLK_PT1, - PMUX_PINGRP_VI_VSYNC_PD6, - PMUX_PINGRP_VI_HSYNC_PD7, - PMUX_PINGRP_UART2_RXD_PC3, - PMUX_PINGRP_UART2_TXD_PC2, - PMUX_PINGRP_UART2_RTS_N_PJ6, - PMUX_PINGRP_UART2_CTS_N_PJ5, - PMUX_PINGRP_UART3_TXD_PW6, - PMUX_PINGRP_UART3_RXD_PW7, - PMUX_PINGRP_UART3_CTS_N_PA1, - PMUX_PINGRP_UART3_RTS_N_PC0, - PMUX_PINGRP_PU0, - PMUX_PINGRP_PU1, - PMUX_PINGRP_PU2, - PMUX_PINGRP_PU3, - PMUX_PINGRP_PU4, - PMUX_PINGRP_PU5, - PMUX_PINGRP_PU6, - PMUX_PINGRP_GEN1_I2C_SDA_PC5, - PMUX_PINGRP_GEN1_I2C_SCL_PC4, - PMUX_PINGRP_DAP4_FS_PP4, - PMUX_PINGRP_DAP4_DIN_PP5, - PMUX_PINGRP_DAP4_DOUT_PP6, - PMUX_PINGRP_DAP4_SCLK_PP7, - PMUX_PINGRP_CLK3_OUT_PEE0, - PMUX_PINGRP_CLK3_REQ_PEE1, - PMUX_PINGRP_GMI_WP_N_PC7, - PMUX_PINGRP_GMI_IORDY_PI5, - PMUX_PINGRP_GMI_WAIT_PI7, - PMUX_PINGRP_GMI_ADV_N_PK0, - PMUX_PINGRP_GMI_CLK_PK1, - PMUX_PINGRP_GMI_CS0_N_PJ0, - PMUX_PINGRP_GMI_CS1_N_PJ2, - PMUX_PINGRP_GMI_CS2_N_PK3, - PMUX_PINGRP_GMI_CS3_N_PK4, - PMUX_PINGRP_GMI_CS4_N_PK2, - PMUX_PINGRP_GMI_CS6_N_PI3, - PMUX_PINGRP_GMI_CS7_N_PI6, - PMUX_PINGRP_GMI_AD0_PG0, - PMUX_PINGRP_GMI_AD1_PG1, - PMUX_PINGRP_GMI_AD2_PG2, - PMUX_PINGRP_GMI_AD3_PG3, - PMUX_PINGRP_GMI_AD4_PG4, - PMUX_PINGRP_GMI_AD5_PG5, - PMUX_PINGRP_GMI_AD6_PG6, - PMUX_PINGRP_GMI_AD7_PG7, - PMUX_PINGRP_GMI_AD8_PH0, - PMUX_PINGRP_GMI_AD9_PH1, - PMUX_PINGRP_GMI_AD10_PH2, - PMUX_PINGRP_GMI_AD11_PH3, - PMUX_PINGRP_GMI_AD12_PH4, - PMUX_PINGRP_GMI_AD13_PH5, - PMUX_PINGRP_GMI_AD14_PH6, - PMUX_PINGRP_GMI_AD15_PH7, - PMUX_PINGRP_GMI_A16_PJ7, - PMUX_PINGRP_GMI_A17_PB0, - PMUX_PINGRP_GMI_A18_PB1, - PMUX_PINGRP_GMI_A19_PK7, - PMUX_PINGRP_GMI_WR_N_PI0, - PMUX_PINGRP_GMI_OE_N_PI1, - PMUX_PINGRP_GMI_DQS_PI2, - PMUX_PINGRP_GMI_RST_N_PI4, - PMUX_PINGRP_GEN2_I2C_SCL_PT5, - PMUX_PINGRP_GEN2_I2C_SDA_PT6, - PMUX_PINGRP_SDMMC4_CLK_PCC4, - PMUX_PINGRP_SDMMC4_CMD_PT7, - PMUX_PINGRP_SDMMC4_DAT0_PAA0, - PMUX_PINGRP_SDMMC4_DAT1_PAA1, - PMUX_PINGRP_SDMMC4_DAT2_PAA2, - PMUX_PINGRP_SDMMC4_DAT3_PAA3, - PMUX_PINGRP_SDMMC4_DAT4_PAA4, - PMUX_PINGRP_SDMMC4_DAT5_PAA5, - PMUX_PINGRP_SDMMC4_DAT6_PAA6, - PMUX_PINGRP_SDMMC4_DAT7_PAA7, - PMUX_PINGRP_SDMMC4_RST_N_PCC3, - PMUX_PINGRP_CAM_MCLK_PCC0, - PMUX_PINGRP_PCC1, - PMUX_PINGRP_PBB0, - PMUX_PINGRP_CAM_I2C_SCL_PBB1, - PMUX_PINGRP_CAM_I2C_SDA_PBB2, - PMUX_PINGRP_PBB3, - PMUX_PINGRP_PBB4, - PMUX_PINGRP_PBB5, - PMUX_PINGRP_PBB6, - PMUX_PINGRP_PBB7, - PMUX_PINGRP_PCC2, - PMUX_PINGRP_JTAG_RTCK_PU7, - PMUX_PINGRP_PWR_I2C_SCL_PZ6, - PMUX_PINGRP_PWR_I2C_SDA_PZ7, - PMUX_PINGRP_KB_ROW0_PR0, - PMUX_PINGRP_KB_ROW1_PR1, - PMUX_PINGRP_KB_ROW2_PR2, - PMUX_PINGRP_KB_ROW3_PR3, - PMUX_PINGRP_KB_ROW4_PR4, - PMUX_PINGRP_KB_ROW5_PR5, - PMUX_PINGRP_KB_ROW6_PR6, - PMUX_PINGRP_KB_ROW7_PR7, - PMUX_PINGRP_KB_ROW8_PS0, - PMUX_PINGRP_KB_ROW9_PS1, - PMUX_PINGRP_KB_ROW10_PS2, - PMUX_PINGRP_KB_ROW11_PS3, - PMUX_PINGRP_KB_ROW12_PS4, - PMUX_PINGRP_KB_ROW13_PS5, - PMUX_PINGRP_KB_ROW14_PS6, - PMUX_PINGRP_KB_ROW15_PS7, - PMUX_PINGRP_KB_COL0_PQ0, - PMUX_PINGRP_KB_COL1_PQ1, - PMUX_PINGRP_KB_COL2_PQ2, - PMUX_PINGRP_KB_COL3_PQ3, - PMUX_PINGRP_KB_COL4_PQ4, - PMUX_PINGRP_KB_COL5_PQ5, - PMUX_PINGRP_KB_COL6_PQ6, - PMUX_PINGRP_KB_COL7_PQ7, - PMUX_PINGRP_CLK_32K_OUT_PA0, - PMUX_PINGRP_SYS_CLK_REQ_PZ5, - PMUX_PINGRP_CORE_PWR_REQ, - PMUX_PINGRP_CPU_PWR_REQ, - PMUX_PINGRP_PWR_INT_N, - PMUX_PINGRP_CLK_32K_IN, - PMUX_PINGRP_OWR, - PMUX_PINGRP_DAP1_FS_PN0, - PMUX_PINGRP_DAP1_DIN_PN1, - PMUX_PINGRP_DAP1_DOUT_PN2, - PMUX_PINGRP_DAP1_SCLK_PN3, - PMUX_PINGRP_CLK1_REQ_PEE2, - PMUX_PINGRP_CLK1_OUT_PW4, - PMUX_PINGRP_SPDIF_IN_PK6, - PMUX_PINGRP_SPDIF_OUT_PK5, - PMUX_PINGRP_DAP2_FS_PA2, - PMUX_PINGRP_DAP2_DIN_PA4, - PMUX_PINGRP_DAP2_DOUT_PA5, - PMUX_PINGRP_DAP2_SCLK_PA3, - PMUX_PINGRP_SPI2_MOSI_PX0, - PMUX_PINGRP_SPI2_MISO_PX1, - PMUX_PINGRP_SPI2_CS0_N_PX3, - PMUX_PINGRP_SPI2_SCK_PX2, - PMUX_PINGRP_SPI1_MOSI_PX4, - PMUX_PINGRP_SPI1_SCK_PX5, - PMUX_PINGRP_SPI1_CS0_N_PX6, - PMUX_PINGRP_SPI1_MISO_PX7, - PMUX_PINGRP_SPI2_CS1_N_PW2, - PMUX_PINGRP_SPI2_CS2_N_PW3, - PMUX_PINGRP_SDMMC3_CLK_PA6, - PMUX_PINGRP_SDMMC3_CMD_PA7, - PMUX_PINGRP_SDMMC3_DAT0_PB7, - PMUX_PINGRP_SDMMC3_DAT1_PB6, - PMUX_PINGRP_SDMMC3_DAT2_PB5, - PMUX_PINGRP_SDMMC3_DAT3_PB4, - PMUX_PINGRP_SDMMC3_DAT4_PD1, - PMUX_PINGRP_SDMMC3_DAT5_PD0, - PMUX_PINGRP_SDMMC3_DAT6_PD3, - PMUX_PINGRP_SDMMC3_DAT7_PD4, - PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0, - PMUX_PINGRP_PEX_L0_RST_N_PDD1, - PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, - PMUX_PINGRP_PEX_WAKE_N_PDD3, - PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4, - PMUX_PINGRP_PEX_L1_RST_N_PDD5, - PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, - PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7, - PMUX_PINGRP_PEX_L2_RST_N_PCC6, - PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7, - PMUX_PINGRP_HDMI_CEC_PEE3, - PMUX_PINGRP_COUNT, -}; - -enum pmux_drvgrp { - PMUX_DRVGRP_AO1, - PMUX_DRVGRP_AO2, - PMUX_DRVGRP_AT1, - PMUX_DRVGRP_AT2, - PMUX_DRVGRP_AT3, - PMUX_DRVGRP_AT4, - PMUX_DRVGRP_AT5, - PMUX_DRVGRP_CDEV1, - PMUX_DRVGRP_CDEV2, - PMUX_DRVGRP_CSUS, - PMUX_DRVGRP_DAP1, - PMUX_DRVGRP_DAP2, - PMUX_DRVGRP_DAP3, - PMUX_DRVGRP_DAP4, - PMUX_DRVGRP_DBG, - PMUX_DRVGRP_LCD1, - PMUX_DRVGRP_LCD2, - PMUX_DRVGRP_SDIO2, - PMUX_DRVGRP_SDIO3, - PMUX_DRVGRP_SPI, - PMUX_DRVGRP_UAA, - PMUX_DRVGRP_UAB, - PMUX_DRVGRP_UART2, - PMUX_DRVGRP_UART3, - PMUX_DRVGRP_VI1, - PMUX_DRVGRP_SDIO1 = (0x84 / 4), - PMUX_DRVGRP_CRT = (0x90 / 4), - PMUX_DRVGRP_DDC, - PMUX_DRVGRP_GMA, - PMUX_DRVGRP_GMB, - PMUX_DRVGRP_GMC, - PMUX_DRVGRP_GMD, - PMUX_DRVGRP_GME, - PMUX_DRVGRP_GMF, - PMUX_DRVGRP_GMG, - PMUX_DRVGRP_GMH, - PMUX_DRVGRP_OWR, - PMUX_DRVGRP_UDA, - PMUX_DRVGRP_GPV, - PMUX_DRVGRP_DEV3, - PMUX_DRVGRP_CEC = (0xd0 / 4), - PMUX_DRVGRP_COUNT, -}; - -enum pmux_func { - PMUX_FUNC_DEFAULT, - PMUX_FUNC_BLINK, - PMUX_FUNC_CEC, - PMUX_FUNC_CLK_12M_OUT, - PMUX_FUNC_CLK_32K_IN, - PMUX_FUNC_CORE_PWR_REQ, - PMUX_FUNC_CPU_PWR_REQ, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP, - PMUX_FUNC_DDR, - PMUX_FUNC_DEV3, - PMUX_FUNC_DISPLAYA, - PMUX_FUNC_DISPLAYB, - PMUX_FUNC_DTV, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HDCP, - PMUX_FUNC_HDMI, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_INVALID, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_NAND, - PMUX_FUNC_NAND_ALT, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_PWR_INT_N, - PMUX_FUNC_RTCK, - PMUX_FUNC_SATA, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYSCLK, - PMUX_FUNC_TEST, - PMUX_FUNC_TRACE, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VGP1, - PMUX_FUNC_VGP2, - PMUX_FUNC_VGP3, - PMUX_FUNC_VGP4, - PMUX_FUNC_VGP5, - PMUX_FUNC_VGP6, - PMUX_FUNC_VI, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT2, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 -#define TEGRA_PMX_SOC_HAS_DRVGRPS -#define TEGRA_PMX_GRPS_HAVE_LPMD -#define TEGRA_PMX_GRPS_HAVE_SCHMT -#define TEGRA_PMX_GRPS_HAVE_HSM -#define TEGRA_PMX_PINS_HAVE_E_INPUT -#define TEGRA_PMX_PINS_HAVE_LOCK -#define TEGRA_PMX_PINS_HAVE_OD -#define TEGRA_PMX_PINS_HAVE_IO_RESET -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA30_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/powergate.h b/arch/arm/include/asm/arch-tegra30/powergate.h deleted file mode 100644 index c70e44b..0000000 --- a/arch/arm/include/asm/arch-tegra30/powergate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _TEGRA30_POWERGATE_H_ -#define _TEGRA30_POWERGATE_H_ - -#include <asm/arch-tegra/powergate.h> - -#endif /* _TEGRA30_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h deleted file mode 100644 index 1de7d2f..0000000 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA30_H_ -#define _TEGRA30_H_ - -#define NV_PA_MC_BASE 0x7000F000 -#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ - -#include <asm/arch-tegra/tegra.h> - -#define TEGRA_USB1_BASE 0x7D000000 - -#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ - -#define MAX_NUM_CPU 4 - -#endif /* TEGRA30_H */ diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h deleted file mode 100644 index 72184fd..0000000 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_IPG_CLK, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, - MXC_DSPI_CLK, -}; - -void enable_ocotp_clk(unsigned char enable); -unsigned int mxc_get_clock(enum mxc_clock clk); -u32 get_lpuart_clk(void); -#ifdef CONFIG_SYS_I2C_MXC -int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); -#endif - -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h deleted file mode 100644 index 0c9ed52..0000000 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ /dev/null @@ -1,275 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ -#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> - -/* Clock Controller Module (CCM) */ -struct ccm_reg { - u32 ccr; - u32 csr; - u32 ccsr; - u32 cacrr; - u32 cscmr1; - u32 cscdr1; - u32 cscdr2; - u32 cscdr3; - u32 cscmr2; - u32 cscdr4; - u32 ctor; - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; - u32 cgpr; - u32 ccgr0; - u32 ccgr1; - u32 ccgr2; - u32 ccgr3; - u32 ccgr4; - u32 ccgr5; - u32 ccgr6; - u32 ccgr7; - u32 ccgr8; - u32 ccgr9; - u32 ccgr10; - u32 ccgr11; - u32 cmeor0; - u32 cmeor1; - u32 cmeor2; - u32 cmeor3; - u32 cmeor4; - u32 cmeor5; - u32 cppdsr; - u32 ccowr; - u32 ccpgr0; - u32 ccpgr1; - u32 ccpgr2; - u32 ccpgr3; -}; - -/* Analog components control digital interface (ANADIG) */ -struct anadig_reg { - u32 reserved_0x000[4]; - u32 pll3_ctrl; - u32 reserved_0x014[3]; - u32 pll7_ctrl; - u32 reserved_0x024[3]; - u32 pll2_ctrl; - u32 reserved_0x034[3]; - u32 pll2_ss; - u32 reserved_0x044[3]; - u32 pll2_num; - u32 reserved_0x054[3]; - u32 pll2_denom; - u32 reserved_0x064[3]; - u32 pll4_ctrl; - u32 reserved_0x074[3]; - u32 pll4_num; - u32 reserved_0x084[3]; - u32 pll4_denom; - u32 reserved_0x094[3]; - u32 pll6_ctrl; - u32 reserved_0x0A4[3]; - u32 pll6_num; - u32 reserved_0x0B4[3]; - u32 pll6_denom; - u32 reserved_0x0C4[7]; - u32 pll5_ctrl; - u32 reserved_0x0E4[3]; - u32 pll3_pfd; - u32 reserved_0x0F4[3]; - u32 pll2_pfd; - u32 reserved_0x104[3]; - u32 reg_1p1; - u32 reserved_0x114[3]; - u32 reg_3p0; - u32 reserved_0x124[3]; - u32 reg_2p5; - u32 reserved_0x134[7]; - u32 ana_misc0; - u32 reserved_0x154[3]; - u32 ana_misc1; - u32 reserved_0x164[63]; - u32 anadig_digprog; - u32 reserved_0x264[3]; - u32 pll1_ctrl; - u32 reserved_0x274[3]; - u32 pll1_ss; - u32 reserved_0x284[3]; - u32 pll1_num; - u32 reserved_0x294[3]; - u32 pll1_denom; - u32 reserved_0x2A4[3]; - u32 pll1_pdf; - u32 reserved_0x2B4[3]; - u32 pll_lock; -}; -#endif - -#define CCM_CCR_FIRC_EN (1 << 16) -#define CCM_CCR_OSCNT_MASK 0xff -#define CCM_CCR_OSCNT(v) ((v) & 0xff) - -#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 -#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) -#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) - -#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 -#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) -#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) - -#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) -#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) -#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) -#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) -#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) -#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) -#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) -#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) - -#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) -#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) - -#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 -#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 -#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) - -#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 -#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) -#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) -#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 -#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) -#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) -#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 -#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 -#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) - -#define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29) -#define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28) - -#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 -#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) -#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) -#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 -#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) -#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) -#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 -#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) -#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) - -#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) - -#define CCM_CSCDR2_NFC_EN (1 << 9) -#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) -#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) -#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 -#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) -#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) - -#define CCM_CSCDR2_ESDHC1_EN (1 << 29) -#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 -#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) -#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) - -#define CCM_CSCDR3_DCU1_EN (1 << 23) -#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20) -#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20) -#define CCM_CSCDR3_DCU0_EN (1 << 19) -#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16) -#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16) - -#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 -#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) -#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) -#define CCM_CSCDR3_QSPI0_EN (1 << 4) -#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) -#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) -#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) - -#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 -#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) -#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) - -#define CCM_REG_CTRL_MASK 0xffffffff -#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) -#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) -#define CCM_CCGR0_UART2_CTRL_MASK (0x3 << 18) -#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) -#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) -#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) -#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) -#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26) -#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) -#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) -#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) -#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) -#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) -#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) -#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) -#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) -#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 -#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) -#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16) -#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) -#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) -#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) -#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) -#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14) -#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) -#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) -#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) -#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) -#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) -#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) -#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 -#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) -#define CCM_CCGR10_NFC_CTRL_MASK 0x3 -#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12) -#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14) - -#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL5_CTRL_DIV_SELECT 1 -#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL2_CTRL_DIV_SELECT 1 -#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL1_CTRL_DIV_SELECT 1 - -#define FASE_CLK_FREQ 24000000 -#define SLOW_CLK_FREQ 32000 -#define PLL1_PFD1_FREQ 500000000 -#define PLL1_PFD2_FREQ 452000000 -#define PLL1_PFD3_FREQ 396000000 -#define PLL1_PFD4_FREQ 528000000 -#define PLL1_MAIN_FREQ 528000000 -#define PLL2_PFD1_FREQ 500000000 -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD3_FREQ 339000000 -#define PLL2_PFD4_FREQ 413000000 -#define PLL2_MAIN_FREQ 528000000 -#define PLL3_MAIN_FREQ 480000000 -#define PLL3_PFD3_FREQ 298000000 -#define PLL5_MAIN_FREQ 500000000 - -#define ENET_EXTERNAL_CLK 50000000 -#define AUDIO_EXTERNAL_CLK 24576000 - -#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h deleted file mode 100644 index 03e3cec..0000000 --- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 - * Toradex, Inc. - * - * Authors: Stefan Agner - * Sanchayan Maity - */ - -#ifndef __ASM_ARCH_VF610_DDRMC_H -#define __ASM_ARCH_VF610_DDRMC_H - -#include <asm/arch/iomux-vf610.h> - -struct ddr3_jedec_timings { - u8 tinit; - u32 trst_pwron; - u32 cke_inactive; - u8 wrlat; - u8 caslat_lin; - u8 trc; - u8 trrd; - u8 tccd; - u8 tbst_int_interval; - u8 tfaw; - u8 trp; - u8 twtr; - u8 tras_min; - u8 tmrd; - u8 trtp; - u32 tras_max; - u8 tmod; - u8 tckesr; - u8 tcke; - u8 trcd_int; - u8 tras_lockout; - u8 tdal; - u8 bstlen; - u16 tdll; - u8 trp_ab; - u16 tref; - u8 trfc; - u16 tref_int; - u8 tpdex; - u8 txpdll; - u8 txsnr; - u16 txsr; - u8 cksrx; - u8 cksre; - u8 freq_chg_en; - u16 zqcl; - u16 zqinit; - u8 zqcs; - u8 ref_per_zq; - u8 zqcs_rotate; - u8 aprebit; - u8 cmd_age_cnt; - u8 age_cnt; - u8 q_fullness; - u8 odt_rd_mapcs0; - u8 odt_wr_mapcs0; - u8 wlmrd; - u8 wldqsen; -}; - -struct ddrmc_cr_setting { - u32 setting; - int cr_rnum; /* CR register ; -1 for last entry */ -}; - -struct ddrmc_phy_setting { - u32 setting; - int phy_rnum; /* PHY register ; -1 for last entry */ -}; - -void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); -void ddrmc_phy_init(void); -void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, - struct ddrmc_cr_setting *board_cr_settings, - struct ddrmc_phy_setting *board_phy_settings, - int col_diff, int row_diff); - -#endif diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h deleted file mode 100644 index 9bfdf16..0000000 --- a/arch/arm/include/asm/arch-vf610/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 - * Bhuvanchandra DV, Toradex, Inc. - */ - -#ifndef __ASM_ARCH_VF610_GPIO_H -#define __ASM_ARCH_VF610_GPIO_H - -#define VYBRID_GPIO_COUNT 32 -#define VF610_GPIO_DIRECTION_IN 0x0 -#define VF610_GPIO_DIRECTION_OUT 0x1 - -/* GPIO registers */ -struct vybrid_gpio_regs { - u32 gpio_pdor; - u32 gpio_psor; - u32 gpio_pcor; - u32 gpio_ptor; - u32 gpio_pdir; -}; - -struct vybrid_gpio_platdata { - unsigned int chip; - u32 base; - const char *port_name; -}; -#endif /* __ASM_ARCH_VF610_GPIO_H */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h deleted file mode 100644 index ae0a187..0000000 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ /dev/null @@ -1,479 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX_REGS_H__ -#define __ASM_ARCH_IMX_REGS_H__ - -#define ARCH_MXC - -#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ -#define IRAM_SIZE 0x00080000 /* 512 KB */ - -#define AIPS0_BASE_ADDR 0x40000000 -#define AIPS1_BASE_ADDR 0x40080000 - -/* AIPS 0 */ -#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) -#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800) -#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) -#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) -#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) -#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000) -#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000) -#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) -#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) -#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000) -#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) -#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000) -#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000) -#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) -#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000) -#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000) -#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000) -#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000) -#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000) -#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000) -#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000) -#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000) -#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000) -#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000) -#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000) -#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000) -#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000) -#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000) -#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000) -#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000) -#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000) -#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000) -#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) -#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) -#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) -#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) -#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) -#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) -#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) -#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) -#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) -#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000) -#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000) -#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) -#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000) -#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) -#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000) -#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) -#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) -#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) -#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800) -#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00) -#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) -#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000) -#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) -#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) -#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) -#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) -#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) -#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) -#define I2C2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00067000) -#define I2C3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E6000) -#define I2C4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E7000) -#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) -#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) -#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) -#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) -#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) -#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) -#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) -#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) -#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) -#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) -#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100) - -/* AIPS 1 */ -#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) -#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) -#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) -#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) -#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000) -#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) -#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) -#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000) -#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000) - -#define QSPI0_AMBA_BASE 0x20000000 - -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - -#define FEC_QUIRK_ENET_MAC -#define I2C_QUIRK_REG - -/* MSCM interrupt rounter */ -#define MSCM_IRSPRC_CP0_EN 1 -#define MSCM_IRSPRC_NUM 112 - -/* DDRMC */ -#define DDRMC_PHY_DQ_TIMING 0x00002613 -#define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x00210000 -#define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00002000 -#define DDRMC_PHY_OFF 0x00000000 -#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 - -#define DDRMC_PHY50_DDR3_MODE (1 << 12) -#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) - -#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8) -#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8) -#define DDRMC_CR00_START 1 -#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff) -#define DDRMC_CR10_TRST_PWRON(v) (v) -#define DDRMC_CR11_CKE_INACTIVE(v) (v) -#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8) -#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f) -#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24) -#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16) -#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8) -#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7) -#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24) -#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16) -#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8) -#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff) -#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24) -#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16) -#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8) -#define DDRMC_CR17_TMOD(v) ((v) & 0xff) -#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8) -#define DDRMC_CR18_TCKE(v) ((v) & 0x7) -#define DDRMC_CR20_AP_EN (1 << 24) -#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) -#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8) -#define DDRMC_CR21_CCMAP_EN 1 -#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) -#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) -#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) -#define DDRMC_CR25_TREF_EN (1 << 16) -#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) -#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) -#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff) -#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff) -#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff) -#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16) -#define DDRMC_CR31_TXSR(v) ((v) & 0xffff) -#define DDRMC_CR33_EN_QK_SREF (1 << 16) -#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) -#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) -#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) -#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) -#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) -#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1 -#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16) -#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff) -#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16) -#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff) -#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) -#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) -#define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) -#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) -#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) -#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) -#define DDRMC_CR74_BANKSPLT_EN (1 << 24) -#define DDRMC_CR74_ADDR_CMP_EN (1 << 16) -#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8) -#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff) -#define DDRMC_CR75_RW_PG_EN (1 << 24) -#define DDRMC_CR75_RW_EN (1 << 16) -#define DDRMC_CR75_PRI_EN (1 << 8) -#define DDRMC_CR75_PLEN 1 -#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24) -#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16) -#define DDRMC_CR76_W2R_SPLT_EN (1 << 8) -#define DDRMC_CR76_CS_EN 1 -#define DDRMC_CR77_CS_MAP (1 << 24) -#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) -#define DDRMC_CR77_SWAP_EN 1 -#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) -#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) -#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8) -#define DDRMC_CR82_INT_MASK (1 << 28) -#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24) -#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16) -#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) -#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) -#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) -#define DDRMC_CR93_SW_LVL_MODE_OFF (8) -#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF) -#define DDRMC_CR93_SWLVL_LOAD BIT(16) -#define DDRMC_CR93_SWLVL_START BIT(24) -#define DDRMC_CR94_SWLVL_EXIT BIT(0) -#define DDRMC_CR94_SWLVL_OP_DONE BIT(8) -#define DDRMC_CR94_SWLVL_RESP_0_OFF (24) -#define DDRMC_CR95_SWLVL_RESP_1_OFF (0) -#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) -#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) -#define DDRMC_CR97_WRLVL_EN (1 << 24) -#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) -#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) -#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF (24) -#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF) -#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) -#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) -#define DDRMC_CR105_RDLVL_DL_0_OFF (8) -#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF) -#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) -#define DDRMC_CR110_RDLVL_DL_1_OFF (0) -#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) -#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) -#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) -#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) -#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) -#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) -#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) -#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16) -#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24) -#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16) -#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8) -#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf) -#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24) -#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16) -#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) -#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) -#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) -#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) -#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) -#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) -#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) -#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) -#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) -#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) -#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8) -#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) -#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) -#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) -#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) -#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) -#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) -#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) -#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) -#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) -#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) -#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) -#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) -#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) -#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) -#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) -#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) -#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) -#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) -#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) -#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) -#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) -#define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) -#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) -#define DDRMC_CR158_TWR(v) ((v) & 0x3f) -#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) -#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) -#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) - -/* System Reset Controller (SRC) */ -#define SRC_SRSR_SW_RST (0x1 << 18) -#define SRC_SRSR_RESETB (0x1 << 7) -#define SRC_SRSR_JTAG_RST (0x1 << 5) -#define SRC_SRSR_WDOG_M4 (0x1 << 4) -#define SRC_SRSR_WDOG_A5 (0x1 << 3) -#define SRC_SRSR_POR_RST (0x1 << 0) -#define SRC_SBMR1_BOOTCFG1_SDMMC BIT(6) -#define SRC_SBMR1_BOOTCFG1_MMC BIT(4) -#define SRC_SBMR2_BMOD_MASK (0x3 << 24) -#define SRC_SBMR2_BMOD_SHIFT 24 -#define SRC_SBMR2_BMOD_FUSES 0x0 -#define SRC_SBMR2_BMOD_SERIAL 0x1 -#define SRC_SBMR2_BMOD_RCON 0x2 - -/* Slow Clock Source Controller Module (SCSC) */ -#define SCSC_SOSC_CTR_SOSC_EN 0x1 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr1; - u32 srsr; - u32 secr; - u32 gpsr; - u32 sicr; - u32 simr; - u32 sbmr2; - u32 gpr0; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 hab0; - u32 hab1; - u32 hab2; - u32 hab3; - u32 hab4; - u32 hab5; - u32 misc0; - u32 misc1; - u32 misc2; - u32 misc3; -}; - -/* Periodic Interrupt Timer (PIT) */ -struct pit_reg { - u32 mcr; - u32 recv0[55]; - u32 ltmr64h; - u32 ltmr64l; - u32 recv1[6]; - u32 ldval0; - u32 cval0; - u32 tctrl0; - u32 tflg0; - u32 ldval1; - u32 cval1; - u32 tctrl1; - u32 tflg1; - u32 ldval2; - u32 cval2; - u32 tctrl2; - u32 tflg2; - u32 ldval3; - u32 cval3; - u32 tctrl3; - u32 tflg3; - u32 ldval4; - u32 cval4; - u32 tctrl4; - u32 tflg4; - u32 ldval5; - u32 cval5; - u32 tctrl5; - u32 tflg5; - u32 ldval6; - u32 cval6; - u32 tctrl6; - u32 tflg6; - u32 ldval7; - u32 cval7; - u32 tctrl7; - u32 tflg7; -}; - -/* Watchdog Timer (WDOG) */ -struct wdog_regs { - u16 wcr; - u16 wsr; - u16 wrsr; - u16 wicr; - u16 wmcr; -}; - -/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */ -struct ddrmr_regs { - u32 cr[162]; - u32 rsvd[94]; - u32 phy[53]; -}; - -/* On-Chip One Time Programmable Controller (OCOTP) */ -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[7]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd4[3]; - u32 crc_value; - u32 rsvd5[3]; - u32 version; - u32 rsvd6[0xdb]; - - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[16]; -}; - -struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 uid_low; - u32 rsvd1[3]; - u32 uid_high; - u32 rsvd2[0x17]; -}; - -struct fuse_bank4_regs { - u32 sjc_resp0; - u32 rsvd0[3]; - u32 sjc_resp1; - u32 rsvd1[3]; - u32 mac_addr0; - u32 rsvd2[3]; - u32 mac_addr1; - u32 rsvd3[3]; - u32 mac_addr2; - u32 rsvd4[3]; - u32 mac_addr3; - u32 rsvd5[3]; - u32 gp1; - u32 rsvd6[3]; - u32 gp2; - u32 rsvd7[3]; -}; - -/* MSCM Interrupt Router */ -struct mscm_ir { - u32 ircp0ir; - u32 ircp1ir; - u32 rsvd1[6]; - u32 ircpgir; - u32 rsvd2[23]; - u16 irsprc[112]; - u16 rsvd3[848]; -}; - -/* SCSC */ -struct scsc_reg { - u32 sirc_ctr; - u32 sosc_ctr; -}; - -/* MSCM */ -struct mscm { - u32 cpxtype; - u32 cpxnum; - u32 cpxmaster; - u32 cpxcount; - u32 cpxcfg0; - u32 cpxcfg1; - u32 cpxcfg2; - u32 cpxcfg3; -}; - -#endif /* __ASSEMBLER__*/ - -#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h deleted file mode 100644 index 8ba03e5..0000000 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ /dev/null @@ -1,255 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#ifndef __IOMUX_VF610_H__ -#define __IOMUX_VF610_H__ - -#include <asm/mach-imx/iomux-v3.h> - -/* Pad control groupings */ -#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm -#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \ - PAD_CTL_INPUT_DIFFERENTIAL) -#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_NFC_CN_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE) -#define VF610_NFC_RB_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE) - -#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) - -#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ - PAD_CTL_IBE_ENABLE) - -#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) -#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) -#define VF610_DCU_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE) - -enum { - VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL), - VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_PTA22__I2C2_SCL = IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL), - VF610_PAD_PTA23__I2C2_SDA = IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL), - VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD0__UART2_TX = IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL), - VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD1__UART2_RX = IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL), - VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD2__GPIO_81 = IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD3__GPIO_82 = IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), - - VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE2__DCU0_PCLK = IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE4__DCU0_DE = IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE5__DCU0_R0 = IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE6__DCU0_R1 = IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE7__DCU0_R2 = IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE8__DCU0_R3 = IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE9__DCU0_R4 = IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE10__DCU0_R5 = IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE11__DCU0_R6 = IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE12__DCU0_R7 = IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE13__DCU0_G0 = IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE14__DCU0_G1 = IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE15__DCU0_G2 = IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE16__DCU0_G3 = IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE17__DCU0_G4 = IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE18__DCU0_G5 = IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE19__DCU0_G6 = IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE20__DCU0_G7 = IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE21__DCU0_B0 = IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE22__DCU0_B1 = IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE23__DCU0_B2 = IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE24__DCU0_B3 = IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE25__DCU0_B4 = IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE26__DCU0_B5 = IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE27__DCU0_B6 = IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE28__DCU0_B7 = IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - - VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), -}; - -#endif /* __IOMUX_VF610_H__ */ |