rm arch/arm/include/asm/arch-*

12 files changed, 0 insertions, 3596 deletions

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
deleted file mode 100644
index dded6e0..0000000
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- *
- * Peng Fan <peng.fan at nxp.com>
- */
-
-#include <linux/bitops.h>
-
-#ifdef CONFIG_IMX8MQ
-#include <asm/arch/clock_imx8mq.h>
-#elif defined(CONFIG_IMX8MM)
-#include <asm/arch/clock_imx8mm.h>
-#else
-#error "Error no clock.h"
-#endif
-
-#define MHZ(X)	((X) * 1000000UL)
-
-/* Mainly for compatible to imx common code. */
-enum mxc_clock {
-	MXC_ARM_CLK = 0,
-	MXC_IPG_CLK,
-	MXC_CSPI_CLK,
-	MXC_ESDHC_CLK,
-	MXC_ESDHC2_CLK,
-	MXC_ESDHC3_CLK,
-	MXC_I2C_CLK,
-	MXC_UART_CLK,
-	MXC_QSPI_CLK,
-};
-
-enum clk_slice_type {
-	CORE_CLOCK_SLICE,
-	BUS_CLOCK_SLICE,
-	IP_CLOCK_SLICE,
-	AHB_CLOCK_SLICE,
-	IPG_CLOCK_SLICE,
-	CORE_SEL_CLOCK_SLICE,
-	DRAM_SEL_CLOCK_SLICE,
-};
-
-enum root_pre_div {
-	CLK_ROOT_PRE_DIV1 = 0,
-	CLK_ROOT_PRE_DIV2,
-	CLK_ROOT_PRE_DIV3,
-	CLK_ROOT_PRE_DIV4,
-	CLK_ROOT_PRE_DIV5,
-	CLK_ROOT_PRE_DIV6,
-	CLK_ROOT_PRE_DIV7,
-	CLK_ROOT_PRE_DIV8,
-};
-
-enum root_post_div {
-	CLK_ROOT_POST_DIV1 = 0,
-	CLK_ROOT_POST_DIV2,
-	CLK_ROOT_POST_DIV3,
-	CLK_ROOT_POST_DIV4,
-	CLK_ROOT_POST_DIV5,
-	CLK_ROOT_POST_DIV6,
-	CLK_ROOT_POST_DIV7,
-	CLK_ROOT_POST_DIV8,
-	CLK_ROOT_POST_DIV9,
-	CLK_ROOT_POST_DIV10,
-	CLK_ROOT_POST_DIV11,
-	CLK_ROOT_POST_DIV12,
-	CLK_ROOT_POST_DIV13,
-	CLK_ROOT_POST_DIV14,
-	CLK_ROOT_POST_DIV15,
-	CLK_ROOT_POST_DIV16,
-	CLK_ROOT_POST_DIV17,
-	CLK_ROOT_POST_DIV18,
-	CLK_ROOT_POST_DIV19,
-	CLK_ROOT_POST_DIV20,
-	CLK_ROOT_POST_DIV21,
-	CLK_ROOT_POST_DIV22,
-	CLK_ROOT_POST_DIV23,
-	CLK_ROOT_POST_DIV24,
-	CLK_ROOT_POST_DIV25,
-	CLK_ROOT_POST_DIV26,
-	CLK_ROOT_POST_DIV27,
-	CLK_ROOT_POST_DIV28,
-	CLK_ROOT_POST_DIV29,
-	CLK_ROOT_POST_DIV30,
-	CLK_ROOT_POST_DIV31,
-	CLK_ROOT_POST_DIV32,
-	CLK_ROOT_POST_DIV33,
-	CLK_ROOT_POST_DIV34,
-	CLK_ROOT_POST_DIV35,
-	CLK_ROOT_POST_DIV36,
-	CLK_ROOT_POST_DIV37,
-	CLK_ROOT_POST_DIV38,
-	CLK_ROOT_POST_DIV39,
-	CLK_ROOT_POST_DIV40,
-	CLK_ROOT_POST_DIV41,
-	CLK_ROOT_POST_DIV42,
-	CLK_ROOT_POST_DIV43,
-	CLK_ROOT_POST_DIV44,
-	CLK_ROOT_POST_DIV45,
-	CLK_ROOT_POST_DIV46,
-	CLK_ROOT_POST_DIV47,
-	CLK_ROOT_POST_DIV48,
-	CLK_ROOT_POST_DIV49,
-	CLK_ROOT_POST_DIV50,
-	CLK_ROOT_POST_DIV51,
-	CLK_ROOT_POST_DIV52,
-	CLK_ROOT_POST_DIV53,
-	CLK_ROOT_POST_DIV54,
-	CLK_ROOT_POST_DIV55,
-	CLK_ROOT_POST_DIV56,
-	CLK_ROOT_POST_DIV57,
-	CLK_ROOT_POST_DIV58,
-	CLK_ROOT_POST_DIV59,
-	CLK_ROOT_POST_DIV60,
-	CLK_ROOT_POST_DIV61,
-	CLK_ROOT_POST_DIV62,
-	CLK_ROOT_POST_DIV63,
-	CLK_ROOT_POST_DIV64,
-};
-
-struct clk_root_map {
-	enum clk_root_index entry;
-	enum clk_slice_type slice_type;
-	u32 slice_index;
-	u8 src_mux[8];
-};
-
-struct ccm_ccgr {
-	u32 ccgr;
-	u32 ccgr_set;
-	u32 ccgr_clr;
-	u32 ccgr_tog;
-};
-
-struct ccm_root {
-	u32 target_root;
-	u32 target_root_set;
-	u32 target_root_clr;
-	u32 target_root_tog;
-	u32 misc;
-	u32 misc_set;
-	u32 misc_clr;
-	u32 misc_tog;
-	u32 nm_post;
-	u32 nm_post_root_set;
-	u32 nm_post_root_clr;
-	u32 nm_post_root_tog;
-	u32 nm_pre;
-	u32 nm_pre_root_set;
-	u32 nm_pre_root_clr;
-	u32 nm_pre_root_tog;
-	u32 db_post;
-	u32 db_post_root_set;
-	u32 db_post_root_clr;
-	u32 db_post_root_tog;
-	u32 db_pre;
-	u32 db_pre_root_set;
-	u32 db_pre_root_clr;
-	u32 db_pre_root_tog;
-	u32 reserved[4];
-	u32 access_ctrl;
-	u32 access_ctrl_root_set;
-	u32 access_ctrl_root_clr;
-	u32 access_ctrl_root_tog;
-};
-
-struct ccm_reg {
-	u32 reserved_0[4096];
-	struct ccm_ccgr ccgr_array[192];
-	u32 reserved_1[3328];
-	struct ccm_root core_root[5];
-	u32 reserved_2[352];
-	struct ccm_root bus_root[12];
-	u32 reserved_3[128];
-	struct ccm_root ahb_ipg_root[4];
-	u32 reserved_4[384];
-	struct ccm_root dram_sel;
-	struct ccm_root core_sel;
-	u32 reserved_5[448];
-	struct ccm_root ip_root[78];
-};
-
-enum enet_freq {
-	ENET_25MHZ = 0,
-	ENET_50MHZ,
-	ENET_125MHZ,
-};
-
-#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k)			\
-	{								\
-		.clk		=	(_rate),			\
-		.alt_root_sel	=	(_m),				\
-		.alt_pre_div	=	(_p),				\
-		.apb_root_sel	=	(_s),				\
-		.apb_pre_div	=	(_k),				\
-	}
-
-struct dram_bypass_clk_setting {
-	ulong clk;
-	int alt_root_sel;
-	enum root_pre_div alt_pre_div;
-	int apb_root_sel;
-	enum root_pre_div apb_pre_div;
-};
-
-#define CCGR_CLK_ON_MASK	0x03
-#define CLK_SRC_ON_MASK		0x03
-
-#define CLK_ROOT_ON		BIT(28)
-#define CLK_ROOT_OFF		(0 << 28)
-#define CLK_ROOT_ENABLE_MASK	BIT(28)
-#define CLK_ROOT_ENABLE_SHIFT	28
-#define CLK_ROOT_SOURCE_SEL(n)	(((n) & 0x7) << 24)
-
-/* For SEL, only use 1 bit */
-#define CLK_ROOT_SRC_MUX_MASK	0x07000000
-#define CLK_ROOT_SRC_MUX_SHIFT	24
-#define CLK_ROOT_SRC_0		0x00000000
-#define CLK_ROOT_SRC_1		0x01000000
-#define CLK_ROOT_SRC_2		0x02000000
-#define CLK_ROOT_SRC_3		0x03000000
-#define CLK_ROOT_SRC_4		0x04000000
-#define CLK_ROOT_SRC_5		0x05000000
-#define CLK_ROOT_SRC_6		0x06000000
-#define CLK_ROOT_SRC_7		0x07000000
-
-#define CLK_ROOT_PRE_DIV_MASK	(0x00070000)
-#define CLK_ROOT_PRE_DIV_SHIFT	16
-#define CLK_ROOT_PRE_DIV(n)	(((n) << 16) & 0x00070000)
-
-#define CLK_ROOT_AUDO_SLOW_EN	0x1000
-
-#define CLK_ROOT_AUDO_DIV_MASK	0x700
-#define CLK_ROOT_AUDO_DIV_SHIFT	0x8
-#define CLK_ROOT_AUDO_DIV(n)	(((n) << 8) & 0x700)
-
-/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
-#define CLK_ROOT_POST_DIV_MASK		0x3f
-#define CLK_ROOT_CORE_POST_DIV_MASK	0x7
-#define CLK_ROOT_IPG_POST_DIV_MASK	0x3
-#define CLK_ROOT_POST_DIV_SHIFT		0
-#define CLK_ROOT_POST_DIV(n)		((n) & 0x3f)
-#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
-#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
-#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
-#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x07000000
-#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M			0x01000000
-#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
-#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK	0x01000000
-
-void dram_pll_init(ulong pll_val);
-void dram_enable_bypass(ulong clk_val);
-void dram_disable_bypass(void);
-u32 imx_get_fecclk(void);
-u32 imx_get_uartclk(void);
-int clock_init(void);
-void init_clk_usdhc(u32 index);
-void init_uart_clk(u32 index);
-void init_wdog_clk(void);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-int clock_enable(enum clk_ccgr_index index, bool enable);
-int clock_root_enabled(enum clk_root_index clock_id);
-int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
-		   enum root_post_div post_div, enum clk_root_src clock_src);
-int clock_set_target_val(enum clk_root_index clock_id, u32 val);
-int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
-int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
-int clock_get_postdiv(enum clk_root_index clock_id,
-		      enum root_post_div *post_div);
-int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
-void mxs_set_lcdclk(u32 base_addr, u32 freq);
-int set_clk_qspi(void);
-void enable_ocotp_clk(unsigned char enable);
-int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
-int set_clk_enet(enum enet_freq type);
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
deleted file mode 100644
index 305514a..0000000
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018-2019 NXP
- *
- * Peng Fan <peng.fan@nxp.com>
- */
-
-#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
-#define _ASM_ARCH_IMX8MM_CLOCK_H
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)			\
-	{							\
-		.rate	=	(_rate),			\
-		.mdiv	=	(_m),				\
-		.pdiv	=	(_p),				\
-		.sdiv	=	(_s),				\
-		.kdiv	=	(_k),				\
-	}
-
-#define LOCK_STATUS	BIT(31)
-#define LOCK_SEL_MASK	BIT(29)
-#define CLKE_MASK	BIT(11)
-#define RST_MASK	BIT(9)
-#define BYPASS_MASK	BIT(4)
-#define	MDIV_SHIFT	12
-#define	MDIV_MASK	GENMASK(21, 12)
-#define PDIV_SHIFT	4
-#define PDIV_MASK	GENMASK(9, 4)
-#define SDIV_SHIFT	0
-#define SDIV_MASK	GENMASK(2, 0)
-#define KDIV_SHIFT	0
-#define KDIV_MASK	GENMASK(15, 0)
-
-struct imx_int_pll_rate_table {
-	u32 rate;
-	int mdiv;
-	int pdiv;
-	int sdiv;
-	int kdiv;
-};
-
-enum pll_clocks {
-	ANATOP_ARM_PLL,
-	ANATOP_VPU_PLL,
-	ANATOP_GPU_PLL,
-	ANATOP_SYSTEM_PLL1,
-	ANATOP_SYSTEM_PLL2,
-	ANATOP_SYSTEM_PLL3,
-	ANATOP_AUDIO_PLL1,
-	ANATOP_AUDIO_PLL2,
-	ANATOP_VIDEO_PLL,
-	ANATOP_DRAM_PLL,
-};
-
-enum clk_root_index {
-	ARM_A53_CLK_ROOT		= 0,
-	ARM_M4_CLK_ROOT			= 1,
-	VPU_A53_CLK_ROOT		= 2,
-	GPU3D_CLK_ROOT			= 3,
-	GPU2D_CLK_ROOT			= 4,
-	MAIN_AXI_CLK_ROOT		= 16,
-	ENET_AXI_CLK_ROOT		= 17,
-	NAND_USDHC_BUS_CLK_ROOT		= 18,
-	VPU_BUS_CLK_ROOT		= 19,
-	DISPLAY_AXI_CLK_ROOT		= 20,
-	DISPLAY_APB_CLK_ROOT		= 21,
-	DISPLAY_RTRM_CLK_ROOT		= 22,
-	USB_BUS_CLK_ROOT		= 23,
-	GPU_AXI_CLK_ROOT		= 24,
-	GPU_AHB_CLK_ROOT		= 25,
-	NOC_CLK_ROOT			= 26,
-	NOC_APB_CLK_ROOT		= 27,
-	AHB_CLK_ROOT			= 32,
-	IPG_CLK_ROOT			= 33,
-	AUDIO_AHB_CLK_ROOT		= 34,
-	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
-	DRAM_SEL_CFG			= 48,
-	CORE_SEL_CFG			= 49,
-	DRAM_ALT_CLK_ROOT		= 64,
-	DRAM_APB_CLK_ROOT		= 65,
-	VPU_G1_CLK_ROOT			= 66,
-	VPU_G2_CLK_ROOT			= 67,
-	DISPLAY_DTRC_CLK_ROOT		= 68,
-	DISPLAY_DC8000_CLK_ROOT		= 69,
-	PCIE_CTRL_CLK_ROOT		= 70,
-	PCIE_PHY_CLK_ROOT		= 71,
-	PCIE_AUX_CLK_ROOT		= 72,
-	DC_PIXEL_CLK_ROOT		= 73,
-	LCDIF_PIXEL_CLK_ROOT		= 74,
-	SAI1_CLK_ROOT			= 75,
-	SAI2_CLK_ROOT			= 76,
-	SAI3_CLK_ROOT			= 77,
-	SAI4_CLK_ROOT			= 78,
-	SAI5_CLK_ROOT			= 79,
-	SAI6_CLK_ROOT			= 80,
-	SPDIF1_CLK_ROOT			= 81,
-	SPDIF2_CLK_ROOT			= 82,
-	ENET_REF_CLK_ROOT		= 83,
-	ENET_TIMER_CLK_ROOT		= 84,
-	ENET_PHY_REF_CLK_ROOT		= 85,
-	NAND_CLK_ROOT			= 86,
-	QSPI_CLK_ROOT			= 87,
-	USDHC1_CLK_ROOT			= 88,
-	USDHC2_CLK_ROOT			= 89,
-	I2C1_CLK_ROOT			= 90,
-	I2C2_CLK_ROOT			= 91,
-	I2C3_CLK_ROOT			= 92,
-	I2C4_CLK_ROOT			= 93,
-	UART1_CLK_ROOT			= 94,
-	UART2_CLK_ROOT			= 95,
-	UART3_CLK_ROOT			= 96,
-	UART4_CLK_ROOT			= 97,
-	USB_CORE_REF_CLK_ROOT		= 98,
-	USB_PHY_REF_CLK_ROOT		= 99,
-	GIC_CLK_ROOT			= 100,
-	ECSPI1_CLK_ROOT			= 101,
-	ECSPI2_CLK_ROOT			= 102,
-	PWM1_CLK_ROOT			= 103,
-	PWM2_CLK_ROOT			= 104,
-	PWM3_CLK_ROOT			= 105,
-	PWM4_CLK_ROOT			= 106,
-	GPT1_CLK_ROOT			= 107,
-	GPT2_CLK_ROOT			= 108,
-	GPT3_CLK_ROOT			= 109,
-	GPT4_CLK_ROOT			= 110,
-	GPT5_CLK_ROOT			= 111,
-	GPT6_CLK_ROOT			= 112,
-	TRACE_CLK_ROOT			= 113,
-	WDOG_CLK_ROOT			= 114,
-	WRCLK_CLK_ROOT			= 115,
-	IPP_DO_CLKO1			= 116,
-	IPP_DO_CLKO2			= 117,
-	MIPI_DSI_CORE_CLK_ROOT		= 118,
-	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
-	MIPI_DSI_DBI_CLK_ROOT		= 120,
-	USDHC3_CLK_ROOT			= 121,
-	MIPI_CSI1_CORE_CLK_ROOT		= 122,
-	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
-	MIPI_CSI1_ESC_CLK_ROOT		= 124,
-	MIPI_CSI2_CORE_CLK_ROOT		= 125,
-	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
-	MIPI_CSI2_ESC_CLK_ROOT		= 127,
-	PCIE2_CTRL_CLK_ROOT		= 128,
-	PCIE2_PHY_CLK_ROOT		= 129,
-	PCIE2_AUX_CLK_ROOT		= 130,
-	ECSPI3_CLK_ROOT			= 131,
-	PDM_CLK_ROOT			= 132,
-	VPU_H1_CLK_ROOT			= 133,
-	CLK_ROOT_MAX,
-};
-
-enum clk_root_src {
-	OSC_24M_CLK,
-	ARM_PLL_CLK,
-	DRAM_PLL1_CLK,
-	VIDEO_PLL2_CLK,
-	VPU_PLL_CLK,
-	GPU_PLL_CLK,
-	SYSTEM_PLL1_800M_CLK,
-	SYSTEM_PLL1_400M_CLK,
-	SYSTEM_PLL1_266M_CLK,
-	SYSTEM_PLL1_200M_CLK,
-	SYSTEM_PLL1_160M_CLK,
-	SYSTEM_PLL1_133M_CLK,
-	SYSTEM_PLL1_100M_CLK,
-	SYSTEM_PLL1_80M_CLK,
-	SYSTEM_PLL1_40M_CLK,
-	SYSTEM_PLL2_1000M_CLK,
-	SYSTEM_PLL2_500M_CLK,
-	SYSTEM_PLL2_333M_CLK,
-	SYSTEM_PLL2_250M_CLK,
-	SYSTEM_PLL2_200M_CLK,
-	SYSTEM_PLL2_166M_CLK,
-	SYSTEM_PLL2_125M_CLK,
-	SYSTEM_PLL2_100M_CLK,
-	SYSTEM_PLL2_50M_CLK,
-	SYSTEM_PLL3_CLK,
-	AUDIO_PLL1_CLK,
-	AUDIO_PLL2_CLK,
-	VIDEO_PLL_CLK,
-	OSC_32K_CLK,
-	EXT_CLK_1,
-	EXT_CLK_2,
-	EXT_CLK_3,
-	EXT_CLK_4,
-	OSC_HDMI_CLK
-};
-
-enum clk_ccgr_index {
-	CCGR_DVFS = 0,
-	CCGR_ANAMIX = 1,
-	CCGR_CPU = 2,
-	CCGR_CSU = 3,
-	CCGR_DEBUG = 4,
-	CCGR_DDR1 = 5,
-	CCGR_ECSPI1 = 7,
-	CCGR_ECSPI2 = 8,
-	CCGR_ECSPI3 = 9,
-	CCGR_ENET1 = 10,
-	CCGR_GPIO1 = 11,
-	CCGR_GPIO2 = 12,
-	CCGR_GPIO3 = 13,
-	CCGR_GPIO4 = 14,
-	CCGR_GPIO5 = 15,
-	CCGR_GPT1 = 16,
-	CCGR_GPT2 = 17,
-	CCGR_GPT3 = 18,
-	CCGR_GPT4 = 19,
-	CCGR_GPT5 = 20,
-	CCGR_GPT6 = 21,
-	CCGR_HS = 22,
-	CCGR_I2C1 = 23,
-	CCGR_I2C2 = 24,
-	CCGR_I2C3 = 25,
-	CCGR_I2C4 = 26,
-	CCGR_IOMUX = 27,
-	CCGR_IOMUX1 = 28,
-	CCGR_IOMUX2 = 29,
-	CCGR_IOMUX3 = 30,
-	CCGR_IOMUX4 = 31,
-	CCGR_SNVSMIX_IPG_CLK = 32,
-	CCGR_MU = 33,
-	CCGR_OCOTP = 34,
-	CCGR_OCRAM = 35,
-	CCGR_OCRAM_S = 36,
-	CCGR_PCIE = 37,
-	CCGR_PERFMON1 = 38,
-	CCGR_PERFMON2 = 39,
-	CCGR_PWM1 = 40,
-	CCGR_PWM2 = 41,
-	CCGR_PWM3 = 42,
-	CCGR_PWM4 = 43,
-	CCGR_QOS = 44,
-	CCGR_QOS_DISPMIX = 45,
-	CCGR_QOS_ETHENET = 46,
-	CCGR_QSPI = 47,
-	CCGR_RAWNAND = 48,
-	CCGR_RDC = 49,
-	CCGR_ROM = 50,
-	CCGR_SAI1 = 51,
-	CCGR_SAI2 = 52,
-	CCGR_SAI3 = 53,
-	CCGR_SAI4 = 54,
-	CCGR_SAI5 = 55,
-	CCGR_SAI6 = 56,
-	CCGR_SCTR = 57,
-	CCGR_SDMA1 = 58,
-	CCGR_SDMA2 = 59,
-	CCGR_SEC_DEBUG = 60,
-	CCGR_SEMA1 = 61,
-	CCGR_SEMA2 = 62,
-	CCGR_SIM_DISPLAY = 63,
-	CCGR_SIM_ENET = 64,
-	CCGR_SIM_M = 65,
-	CCGR_SIM_MAIN = 66,
-	CCGR_SIM_S = 67,
-	CCGR_SIM_WAKEUP = 68,
-	CCGR_SIM_HSIO = 69,
-	CCGR_SIM_VPU = 70,
-	CCGR_SNVS = 71,
-	CCGR_TRACE = 72,
-	CCGR_UART1 = 73,
-	CCGR_UART2 = 74,
-	CCGR_UART3 = 75,
-	CCGR_UART4 = 76,
-	CCGR_USB_MSCALE_PL301 = 77,
-	CCGR_GPU3D = 79,
-	CCGR_USDHC1 = 81,
-	CCGR_USDHC2 = 82,
-	CCGR_WDOG1 = 83,
-	CCGR_WDOG2 = 84,
-	CCGR_WDOG3 = 85,
-	CCGR_VPUG1 = 86,
-	CCGR_GPU_BUS = 87,
-	CCGR_VPUH1 = 89,
-	CCGR_VPUG2 = 90,
-	CCGR_PDM = 91,
-	CCGR_GIC = 92,
-	CCGR_DISPMIX = 93,
-	CCGR_USDHC3 = 94,
-	CCGR_SDMA3 = 95,
-	CCGR_XTAL = 96,
-	CCGR_PLL = 97,
-	CCGR_TEMP_SENSOR = 98,
-	CCGR_VPUMIX_BUS = 99,
-	CCGR_GPU2D = 102,
-	CCGR_MAX
-};
-
-enum clk_src_index {
-	CLK_SRC_CKIL_SYNC_REQ = 0,
-	CLK_SRC_ARM_PLL_EN = 1,
-	CLK_SRC_GPU_PLL_EN = 2,
-	CLK_SRC_VPU_PLL_EN = 3,
-	CLK_SRC_DRAM_PLL_EN = 4,
-	CLK_SRC_SYSTEM_PLL1_EN = 5,
-	CLK_SRC_SYSTEM_PLL2_EN = 6,
-	CLK_SRC_SYSTEM_PLL3_EN = 7,
-	CLK_SRC_AUDIO_PLL1_EN = 8,
-	CLK_SRC_AUDIO_PLL2_EN = 9,
-	CLK_SRC_VIDEO_PLL1_EN = 10,
-	CLK_SRC_RESERVED = 11,
-	CLK_SRC_ARM_PLL = 12,
-	CLK_SRC_GPU_PLL = 13,
-	CLK_SRC_VPU_PLL = 14,
-	CLK_SRC_DRAM_PLL = 15,
-	CLK_SRC_SYSTEM_PLL1_800M = 16,
-	CLK_SRC_SYSTEM_PLL1_400M = 17,
-	CLK_SRC_SYSTEM_PLL1_266M = 18,
-	CLK_SRC_SYSTEM_PLL1_200M = 19,
-	CLK_SRC_SYSTEM_PLL1_160M = 20,
-	CLK_SRC_SYSTEM_PLL1_133M = 21,
-	CLK_SRC_SYSTEM_PLL1_100M = 22,
-	CLK_SRC_SYSTEM_PLL1_80M = 23,
-	CLK_SRC_SYSTEM_PLL1_40M = 24,
-	CLK_SRC_SYSTEM_PLL2_1000M = 25,
-	CLK_SRC_SYSTEM_PLL2_500M = 26,
-	CLK_SRC_SYSTEM_PLL2_333M = 27,
-	CLK_SRC_SYSTEM_PLL2_250M = 28,
-	CLK_SRC_SYSTEM_PLL2_200M = 29,
-	CLK_SRC_SYSTEM_PLL2_166M = 30,
-	CLK_SRC_SYSTEM_PLL2_125M = 31,
-	CLK_SRC_SYSTEM_PLL2_100M = 32,
-	CLK_SRC_SYSTEM_PLL2_50M = 33,
-	CLK_SRC_SYSTEM_PLL3 = 34,
-	CLK_SRC_AUDIO_PLL1 = 35,
-	CLK_SRC_AUDIO_PLL2 = 36,
-	CLK_SRC_VIDEO_PLL1 = 37,
-};
-
-#define INTPLL_LOCK_MASK			BIT(31)
-#define INTPLL_LOCK_SEL_MASK			BIT(29)
-#define INTPLL_EXT_BYPASS_MASK			BIT(28)
-#define INTPLL_DIV20_CLKE_MASK			BIT(27)
-#define INTPLL_DIV20_CLKE_OVERRIDE_MASK		BIT(26)
-#define INTPLL_DIV10_CLKE_MASK			BIT(25)
-#define INTPLL_DIV10_CLKE_OVERRIDE_MASK		BIT(24)
-#define INTPLL_DIV8_CLKE_MASK			BIT(23)
-#define INTPLL_DIV8_CLKE_OVERRIDE_MASK		BIT(22)
-#define INTPLL_DIV6_CLKE_MASK			BIT(21)
-#define INTPLL_DIV6_CLKE_OVERRIDE_MASK		BIT(20)
-#define INTPLL_DIV5_CLKE_MASK			BIT(19)
-#define INTPLL_DIV5_CLKE_OVERRIDE_MASK		BIT(18)
-#define INTPLL_DIV4_CLKE_MASK			BIT(17)
-#define INTPLL_DIV4_CLKE_OVERRIDE_MASK		BIT(16)
-#define INTPLL_DIV3_CLKE_MASK			BIT(15)
-#define INTPLL_DIV3_CLKE_OVERRIDE_MASK		BIT(14)
-#define INTPLL_DIV2_CLKE_MASK			BIT(13)
-#define INTPLL_DIV2_CLKE_OVERRIDE_MASK		BIT(12)
-#define INTPLL_CLKE_MASK			BIT(11)
-#define INTPLL_CLKE_OVERRIDE_MASK		BIT(10)
-#define INTPLL_RST_MASK				BIT(9)
-#define INTPLL_RST_OVERRIDE_MASK		BIT(8)
-#define INTPLL_BYPASS_MASK			BIT(4)
-#define INTPLL_PAD_CLK_SEL_MASK			GENMASK(3, 2)
-#define INTPLL_REF_CLK_SEL_MASK			GENMASK(1, 0)
-
-#define INTPLL_MAIN_DIV_MASK		GENMASK(21, 12)
-#define INTPLL_MAIN_DIV_VAL(n)		((n << 12) & GENMASK(21, 12))
-#define INTPLL_MAIN_DIV_SHIFT		12
-#define INTPLL_PRE_DIV_MASK		GENMASK(9, 4)
-#define INTPLL_PRE_DIV_VAL(n)		((n << 4) & GENMASK(9, 4))
-#define INTPLL_PRE_DIV_SHIFT		4
-#define INTPLL_POST_DIV_MASK		GENMASK(2, 0)
-#define INTPLL_POST_DIV_VAL(n)		((n << 0) & GENMASK(2, 0))
-#define INTPLL_POST_DIV_SHIFT		0
-
-#define INTPLL_LOCK_CON_DLY_MASK	GENMASK(5, 4)
-#define INTPLL_LOCK_CON_DLY_SHIFT	4
-#define INTPLL_LOCK_CON_OUT_MASK	GENMASK(3, 2)
-#define INTPLL_LOCK_CON_OUT_SHIFT	2
-#define INTPLL_LOCK_CON_IN_MASK		GENMASK(1, 0)
-#define INTPLL_LOCK_CON_IN_SHIFT	0
-
-#define INTPLL_LRD_EN_MASK		BIT(21)
-#define INTPLL_FOUT_MASK		BIT(20)
-#define INTPLL_AFC_SEL_MASK		BIT(19)
-#define INTPLL_PBIAS_CTRL_MASK		BIT(18)
-#define INTPLL_PBIAS_CTRL_EN_MASK	BIT(17)
-#define INTPLL_AFCINIT_SEL_MASK		BIT(16)
-#define INTPLL_FSEL_MASK		BIT(14)
-#define INTPLL_FEED_EN_MASK		BIT(13)
-#define INTPLL_EXTAFC_MASK		GENMASK(7, 3)
-#define INTPLL_AFC_EN_MASK		BIT(2)
-#define INTPLL_ICP_MASK			GENMASK(1, 0)
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
deleted file mode 100644
index 9fa9eb2..0000000
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- *
- * Peng Fan <peng.fan@nxp.com>
- */
-
-#ifndef _ASM_ARCH_IMX8M_CLOCK_H
-#define _ASM_ARCH_IMX8M_CLOCK_H
-
-enum pll_clocks {
-	ANATOP_ARM_PLL,
-	ANATOP_GPU_PLL,
-	ANATOP_SYSTEM_PLL1,
-	ANATOP_SYSTEM_PLL2,
-	ANATOP_SYSTEM_PLL3,
-	ANATOP_AUDIO_PLL1,
-	ANATOP_AUDIO_PLL2,
-	ANATOP_VIDEO_PLL1,
-	ANATOP_VIDEO_PLL2,
-	ANATOP_DRAM_PLL,
-};
-
-enum clk_root_index {
-	ARM_A53_CLK_ROOT		= 0,
-	ARM_M4_CLK_ROOT			= 1,
-	VPU_A53_CLK_ROOT		= 2,
-	GPU_CORE_CLK_ROOT		= 3,
-	GPU_SHADER_CLK_ROOT		= 4,
-	MAIN_AXI_CLK_ROOT		= 16,
-	ENET_AXI_CLK_ROOT		= 17,
-	NAND_USDHC_BUS_CLK_ROOT		= 18,
-	VPU_BUS_CLK_ROOT		= 19,
-	DISPLAY_AXI_CLK_ROOT		= 20,
-	DISPLAY_APB_CLK_ROOT		= 21,
-	DISPLAY_RTRM_CLK_ROOT		= 22,
-	USB_BUS_CLK_ROOT		= 23,
-	GPU_AXI_CLK_ROOT		= 24,
-	GPU_AHB_CLK_ROOT		= 25,
-	NOC_CLK_ROOT			= 26,
-	NOC_APB_CLK_ROOT		= 27,
-	AHB_CLK_ROOT			= 32,
-	IPG_CLK_ROOT			= 33,
-	AUDIO_AHB_CLK_ROOT		= 34,
-	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
-	DRAM_SEL_CFG			= 48,
-	CORE_SEL_CFG			= 49,
-	DRAM_ALT_CLK_ROOT		= 64,
-	DRAM_APB_CLK_ROOT		= 65,
-	VPU_G1_CLK_ROOT			= 66,
-	VPU_G2_CLK_ROOT			= 67,
-	DISPLAY_DTRC_CLK_ROOT		= 68,
-	DISPLAY_DC8000_CLK_ROOT		= 69,
-	PCIE1_CTRL_CLK_ROOT		= 70,
-	PCIE1_PHY_CLK_ROOT		= 71,
-	PCIE1_AUX_CLK_ROOT		= 72,
-	DC_PIXEL_CLK_ROOT		= 73,
-	LCDIF_PIXEL_CLK_ROOT		= 74,
-	SAI1_CLK_ROOT			= 75,
-	SAI2_CLK_ROOT			= 76,
-	SAI3_CLK_ROOT			= 77,
-	SAI4_CLK_ROOT			= 78,
-	SAI5_CLK_ROOT			= 79,
-	SAI6_CLK_ROOT			= 80,
-	SPDIF1_CLK_ROOT			= 81,
-	SPDIF2_CLK_ROOT			= 82,
-	ENET_REF_CLK_ROOT		= 83,
-	ENET_TIMER_CLK_ROOT		= 84,
-	ENET_PHY_REF_CLK_ROOT		= 85,
-	NAND_CLK_ROOT			= 86,
-	QSPI_CLK_ROOT			= 87,
-	USDHC1_CLK_ROOT			= 88,
-	USDHC2_CLK_ROOT			= 89,
-	I2C1_CLK_ROOT			= 90,
-	I2C2_CLK_ROOT			= 91,
-	I2C3_CLK_ROOT			= 92,
-	I2C4_CLK_ROOT			= 93,
-	UART1_CLK_ROOT			= 94,
-	UART2_CLK_ROOT			= 95,
-	UART3_CLK_ROOT			= 96,
-	UART4_CLK_ROOT			= 97,
-	USB_CORE_REF_CLK_ROOT		= 98,
-	USB_PHY_REF_CLK_ROOT		= 99,
-	GIC_CLK_ROOT			= 100,
-	ECSPI1_CLK_ROOT			= 101,
-	ECSPI2_CLK_ROOT			= 102,
-	PWM1_CLK_ROOT			= 103,
-	PWM2_CLK_ROOT			= 104,
-	PWM3_CLK_ROOT			= 105,
-	PWM4_CLK_ROOT			= 106,
-	GPT1_CLK_ROOT			= 107,
-	GPT2_CLK_ROOT			= 108,
-	GPT3_CLK_ROOT			= 109,
-	GPT4_CLK_ROOT			= 110,
-	GPT5_CLK_ROOT			= 111,
-	GPT6_CLK_ROOT			= 112,
-	TRACE_CLK_ROOT			= 113,
-	WDOG_CLK_ROOT			= 114,
-	WRCLK_CLK_ROOT			= 115,
-	IPP_DO_CLKO1			= 116,
-	IPP_DO_CLKO2			= 117,
-	MIPI_DSI_CORE_CLK_ROOT		= 118,
-	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
-	MIPI_DSI_DBI_CLK_ROOT		= 120,
-	OLD_MIPI_DSI_ESC_CLK_ROOT	= 121,
-	MIPI_CSI1_CORE_CLK_ROOT		= 122,
-	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
-	MIPI_CSI1_ESC_CLK_ROOT		= 124,
-	MIPI_CSI2_CORE_CLK_ROOT		= 125,
-	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
-	MIPI_CSI2_ESC_CLK_ROOT		= 127,
-	PCIE2_CTRL_CLK_ROOT		= 128,
-	PCIE2_PHY_CLK_ROOT		= 129,
-	PCIE2_AUX_CLK_ROOT		= 130,
-	ECSPI3_CLK_ROOT			= 131,
-	OLD_MIPI_DSI_ESC_RX_ROOT	= 132,
-	DISPLAY_HDMI_CLK_ROOT		= 133,
-	CLK_ROOT_MAX,
-};
-
-enum clk_root_src {
-	OSC_25M_CLK,
-	ARM_PLL_CLK,
-	DRAM_PLL1_CLK,
-	VIDEO_PLL2_CLK,
-	VPU_PLL_CLK,
-	GPU_PLL_CLK,
-	SYSTEM_PLL1_800M_CLK,
-	SYSTEM_PLL1_400M_CLK,
-	SYSTEM_PLL1_266M_CLK,
-	SYSTEM_PLL1_200M_CLK,
-	SYSTEM_PLL1_160M_CLK,
-	SYSTEM_PLL1_133M_CLK,
-	SYSTEM_PLL1_100M_CLK,
-	SYSTEM_PLL1_80M_CLK,
-	SYSTEM_PLL1_40M_CLK,
-	SYSTEM_PLL2_1000M_CLK,
-	SYSTEM_PLL2_500M_CLK,
-	SYSTEM_PLL2_333M_CLK,
-	SYSTEM_PLL2_250M_CLK,
-	SYSTEM_PLL2_200M_CLK,
-	SYSTEM_PLL2_166M_CLK,
-	SYSTEM_PLL2_125M_CLK,
-	SYSTEM_PLL2_100M_CLK,
-	SYSTEM_PLL2_50M_CLK,
-	SYSTEM_PLL3_CLK,
-	AUDIO_PLL1_CLK,
-	AUDIO_PLL2_CLK,
-	VIDEO_PLL_CLK,
-	OSC_32K_CLK,
-	EXT_CLK_1,
-	EXT_CLK_2,
-	EXT_CLK_3,
-	EXT_CLK_4,
-	OSC_27M_CLK,
-};
-
-/* CCGR index */
-enum clk_ccgr_index {
-	CCGR_DVFS = 0,
-	CCGR_ANAMIX = 1,
-	CCGR_CPU = 2,
-	CCGR_CSU = 4,
-	CCGR_DRAM1 = 5,
-	CCGR_DRAM2_OBSOLETE = 6,
-	CCGR_ECSPI1 = 7,
-	CCGR_ECSPI2 = 8,
-	CCGR_ECSPI3 = 9,
-	CCGR_ENET1 = 10,
-	CCGR_GPIO1 = 11,
-	CCGR_GPIO2 = 12,
-	CCGR_GPIO3 = 13,
-	CCGR_GPIO4 = 14,
-	CCGR_GPIO5 = 15,
-	CCGR_GPT1 = 16,
-	CCGR_GPT2 = 17,
-	CCGR_GPT3 = 18,
-	CCGR_GPT4 = 19,
-	CCGR_GPT5 = 20,
-	CCGR_GPT6 = 21,
-	CCGR_HS = 22,
-	CCGR_I2C1 = 23,
-	CCGR_I2C2 = 24,
-	CCGR_I2C3 = 25,
-	CCGR_I2C4 = 26,
-	CCGR_IOMUX = 27,
-	CCGR_IOMUX1 = 28,
-	CCGR_IOMUX2 = 29,
-	CCGR_IOMUX3 = 30,
-	CCGR_IOMUX4 = 31,
-	CCGR_M4 = 32,
-	CCGR_MU = 33,
-	CCGR_OCOTP = 34,
-	CCGR_OCRAM = 35,
-	CCGR_OCRAM_S = 36,
-	CCGR_PCIE = 37,
-	CCGR_PERFMON1 = 38,
-	CCGR_PERFMON2 = 39,
-	CCGR_PWM1 = 40,
-	CCGR_PWM2 = 41,
-	CCGR_PWM3 = 42,
-	CCGR_PWM4 = 43,
-	CCGR_QOS = 44,
-	CCGR_DISMIX = 45,
-	CCGR_MEGAMIX = 46,
-	CCGR_QSPI = 47,
-	CCGR_RAWNAND = 48,
-	CCGR_RDC = 49,
-	CCGR_ROM = 50,
-	CCGR_SAI1 = 51,
-	CCGR_SAI2 = 52,
-	CCGR_SAI3 = 53,
-	CCGR_SAI4 = 54,
-	CCGR_SAI5 = 55,
-	CCGR_SAI6 = 56,
-	CCGR_SCTR = 57,
-	CCGR_SDMA1 = 58,
-	CCGR_SDMA2 = 59,
-	CCGR_SEC_DEBUG = 60,
-	CCGR_SEMA1 = 61,
-	CCGR_SEMA2 = 62,
-	CCGR_SIM_DISPLAY = 63,
-	CCGR_SIM_ENET = 64,
-	CCGR_SIM_M = 65,
-	CCGR_SIM_MAIN = 66,
-	CCGR_SIM_S = 67,
-	CCGR_SIM_WAKEUP = 68,
-	CCGR_SIM_USB = 69,
-	CCGR_SIM_VPU = 70,
-	CCGR_SNVS = 71,
-	CCGR_TRACE = 72,
-	CCGR_UART1 = 73,
-	CCGR_UART2 = 74,
-	CCGR_UART3 = 75,
-	CCGR_UART4 = 76,
-	CCGR_USB_CTRL1 = 77,
-	CCGR_USB_CTRL2 = 78,
-	CCGR_USB_PHY1 = 79,
-	CCGR_USB_PHY2 = 80,
-	CCGR_USDHC1 = 81,
-	CCGR_USDHC2 = 82,
-	CCGR_WDOG1 = 83,
-	CCGR_WDOG2 = 84,
-	CCGR_WDOG3 = 85,
-	CCGR_VA53 = 86,
-	CCGR_GPU = 87,
-	CCGR_HEVC = 88,
-	CCGR_AVC = 89,
-	CCGR_VP9 = 90,
-	CCGR_HEVC_INTER = 91,
-	CCGR_GIC = 92,
-	CCGR_DISPLAY = 93,
-	CCGR_HDMI = 94,
-	CCGR_HDMI_PHY = 95,
-	CCGR_XTAL = 96,
-	CCGR_PLL = 97,
-	CCGR_TSENSOR = 98,
-	CCGR_VPU_DEC = 99,
-	CCGR_PCIE2 = 100,
-	CCGR_MIPI_CSI1 = 101,
-	CCGR_MIPI_CSI2 = 102,
-	CCGR_MAX,
-};
-
-/* src index */
-enum clk_src_index {
-	CLK_SRC_CKIL_SYNC_REQ = 0,
-	CLK_SRC_ARM_PLL_EN = 1,
-	CLK_SRC_GPU_PLL_EN = 2,
-	CLK_SRC_VPU_PLL_EN = 3,
-	CLK_SRC_DRAM_PLL_EN = 4,
-	CLK_SRC_SYSTEM_PLL1_EN = 5,
-	CLK_SRC_SYSTEM_PLL2_EN = 6,
-	CLK_SRC_SYSTEM_PLL3_EN = 7,
-	CLK_SRC_AUDIO_PLL1_EN = 8,
-	CLK_SRC_AUDIO_PLL2_EN = 9,
-	CLK_SRC_VIDEO_PLL1_EN = 10,
-	CLK_SRC_VIDEO_PLL2_EN = 11,
-	CLK_SRC_ARM_PLL = 12,
-	CLK_SRC_GPU_PLL = 13,
-	CLK_SRC_VPU_PLL = 14,
-	CLK_SRC_DRAM_PLL = 15,
-	CLK_SRC_SYSTEM_PLL1_800M = 16,
-	CLK_SRC_SYSTEM_PLL1_400M = 17,
-	CLK_SRC_SYSTEM_PLL1_266M = 18,
-	CLK_SRC_SYSTEM_PLL1_200M = 19,
-	CLK_SRC_SYSTEM_PLL1_160M = 20,
-	CLK_SRC_SYSTEM_PLL1_133M = 21,
-	CLK_SRC_SYSTEM_PLL1_100M = 22,
-	CLK_SRC_SYSTEM_PLL1_80M = 23,
-	CLK_SRC_SYSTEM_PLL1_40M = 24,
-	CLK_SRC_SYSTEM_PLL2_1000M = 25,
-	CLK_SRC_SYSTEM_PLL2_500M = 26,
-	CLK_SRC_SYSTEM_PLL2_333M = 27,
-	CLK_SRC_SYSTEM_PLL2_250M = 28,
-	CLK_SRC_SYSTEM_PLL2_200M = 29,
-	CLK_SRC_SYSTEM_PLL2_166M = 30,
-	CLK_SRC_SYSTEM_PLL2_125M = 31,
-	CLK_SRC_SYSTEM_PLL2_100M = 32,
-	CLK_SRC_SYSTEM_PLL2_50M = 33,
-	CLK_SRC_SYSTEM_PLL3 = 34,
-	CLK_SRC_AUDIO_PLL1 = 35,
-	CLK_SRC_AUDIO_PLL2 = 36,
-	CLK_SRC_VIDEO_PLL1 = 37,
-	CLK_SRC_VIDEO_PLL2 = 38,
-	CLK_SRC_OSC_25M = 39,
-	CLK_SRC_OSC_27M = 40,
-};
-
-/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
-#define FRAC_PLL_LOCK_MASK		BIT(31)
-#define FRAC_PLL_CLKE_MASK		BIT(21)
-#define FRAC_PLL_PD_MASK		BIT(19)
-#define FRAC_PLL_REFCLK_SEL_MASK	BIT(16)
-#define FRAC_PLL_LOCK_SEL_MASK		BIT(15)
-#define FRAC_PLL_BYPASS_MASK		BIT(14)
-#define FRAC_PLL_COUNTCLK_SEL_MASK	BIT(13)
-#define FRAC_PLL_NEWDIV_VAL_MASK	BIT(12)
-#define FRAC_PLL_NEWDIV_ACK_MASK	BIT(11)
-#define FRAC_PLL_REFCLK_DIV_VAL(n)	(((n) << 5) & (0x3f << 5))
-#define FRAC_PLL_REFCLK_DIV_VAL_MASK	(0x3f << 5)
-#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT	5
-#define FRAC_PLL_OUTPUT_DIV_VAL_MASK	0x1f
-#define FRAC_PLL_OUTPUT_DIV_VAL(n)	((n) & 0x1f)
-
-#define FRAC_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
-#define FRAC_PLL_REFCLK_SEL_OSC_27M	BIT(16)
-#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define FRAC_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
-
-#define FRAC_PLL_FRAC_DIV_CTL_MASK	(0x1ffffff << 7)
-#define FRAC_PLL_FRAC_DIV_CTL_SHIFT	7
-#define FRAC_PLL_INT_DIV_CTL_MASK	0x7f
-#define FRAC_PLL_INT_DIV_CTL_VAL(n)	((n) & 0x7f)
-
-/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
-#define SSCG_PLL_LOCK_MASK		BIT(31)
-#define SSCG_PLL_CLKE_MASK		BIT(25)
-#define SSCG_PLL_DIV2_CLKE_MASK		BIT(23)
-#define SSCG_PLL_DIV3_CLKE_MASK		BIT(21)
-#define SSCG_PLL_DIV4_CLKE_MASK		BIT(19)
-#define SSCG_PLL_DIV5_CLKE_MASK		BIT(17)
-#define SSCG_PLL_DIV6_CLKE_MASK		BIT(15)
-#define SSCG_PLL_DIV8_CLKE_MASK		BIT(13)
-#define SSCG_PLL_DIV10_CLKE_MASK	BIT(11)
-#define SSCG_PLL_DIV20_CLKE_MASK	BIT(9)
-#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK	BIT(9)
-#define SSCG_PLL_DRAM_PLL_CLKE_MASK	BIT(9)
-#define SSCG_PLL_PLL3_CLKE_MASK		BIT(9)
-#define SSCG_PLL_PD_MASK		BIT(7)
-#define SSCG_PLL_BYPASS1_MASK		BIT(5)
-#define SSCG_PLL_BYPASS2_MASK		BIT(4)
-#define SSCG_PLL_LOCK_SEL_MASK		BIT(3)
-#define SSCG_PLL_COUNTCLK_SEL_MASK	BIT(2)
-#define SSCG_PLL_REFCLK_SEL_MASK	0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M	BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
-
-#define SSCG_PLL_SSDS_MASK		BIT(8)
-#define SSCG_PLL_SSMD_MASK		(0x7 << 5)
-#define SSCG_PLL_SSMF_MASK		(0xf << 1)
-#define SSCG_PLL_SSE_MASK		0x1
-
-#define SSCG_PLL_REF_DIVR1_MASK		(0x7 << 25)
-#define SSCG_PLL_REF_DIVR1_SHIFT	25
-#define SSCG_PLL_REF_DIVR1_VAL(n)	(((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
-#define SSCG_PLL_REF_DIVR2_MASK		(0x3f << 19)
-#define SSCG_PLL_REF_DIVR2_SHIFT	19
-#define SSCG_PLL_REF_DIVR2_VAL(n)	(((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F1_MASK	(0x3f << 13)
-#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT	13
-#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n)	(((n) << 13) & \
-					 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F2_MASK	(0x3f << 7)
-#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT	7
-#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n)	(((n) << 7) & \
-					 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
-#define SSCG_PLL_OUTPUT_DIV_VAL_MASK	(0x3f << 1)
-#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT	1
-#define SSCG_PLL_OUTPUT_DIV_VAL(n)	(((n) << 1) & \
-					 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
-#define SSCG_PLL_FILTER_RANGE_MASK	0x1
-
-#define HW_DIGPROG_MAJOR_UPPER_MASK	(0xff << 16)
-#define HW_DIGPROG_MAJOR_LOWER_MASK	(0xff << 8)
-#define HW_DIGPROG_MINOR_MASK		0xff
-
-#define HW_OSC_27M_CLKE_MASK		BIT(4)
-#define HW_OSC_25M_CLKE_MASK		BIT(2)
-#define HW_OSC_32K_SEL_MASK		0x1
-#define HW_OSC_32K_SEL_RTC		0x1
-#define HW_OSC_32K_SEL_25M_DIV800	0x0
-
-#define HW_FRAC_ARM_PLL_DIV_MASK	(0x7 << 20)
-#define HW_FRAC_ARM_PLL_DIV_SHIFT	20
-#define HW_FRAC_VPU_PLL_DIV_MASK	(0x7 << 16)
-#define HW_FRAC_VPU_PLL_DIV_SHIFT	16
-#define HW_FRAC_GPU_PLL_DIV_MASK	(0x7 << 12)
-#define HW_FRAC_GPU_PLL_DIV_SHIFT	12
-#define HW_FRAC_VIDEO_PLL1_DIV_MASK	(0x7 << 10)
-#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT	10
-#define HW_FRAC_AUDIO_PLL2_DIV_MASK	(0x7 << 4)
-#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT	4
-#define HW_FRAC_AUDIO_PLL1_DIV_MASK	0x7
-#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT	0
-
-#define HW_SSCG_VIDEO_PLL2_DIV_MASK	(0x7 << 16)
-#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT	16
-#define HW_SSCG_DRAM_PLL_DIV_MASK	(0x7 << 14)
-#define HW_SSCG_DRAM_PLL_DIV_SHIFT	14
-#define HW_SSCG_SYSTEM_PLL3_DIV_MASK	(0x7 << 8)
-#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT	8
-#define HW_SSCG_SYSTEM_PLL2_DIV_MASK	(0x7 << 4)
-#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT	4
-#define HW_SSCG_SYSTEM_PLL1_DIV_MASK	0x7
-#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT	0
-
-enum frac_pll_out_val {
-	FRAC_PLL_OUT_1000M,
-	FRAC_PLL_OUT_1600M,
-};
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h
deleted file mode 100644
index c42e668..0000000
--- a/arch/arm/include/asm/arch-imx8m/crm_regs.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- */
-
-#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
-#define _ASM_ARCH_IMX8M_CRM_REGS_H
-/* Dummy header, some imx-common code needs this file */
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
deleted file mode 100644
index 53d4625..0000000
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ /dev/null
@@ -1,740 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- */
-
-#ifndef __ASM_ARCH_IMX8M_DDR_H
-#define __ASM_ARCH_IMX8M_DDR_H
-
-#include <asm/io.h>
-#include <asm/types.h>
-#include <asm/arch/ddr.h>
-
-#define DDRC_DDR_SS_GPR0		0x3d000000
-#define DDRC_IPS_BASE_ADDR_0		0x3f400000
-#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(0x3c000000 + (X * 0x2000000))
-#define DDRPHY_MEM(X)			(0x3c000000 + (X * 0x2000000) + 0x50000)
-
-struct ddrc_freq {
-	u32 res0[8];
-	u32 derateen;
-	u32 derateint;
-	u32 res1[10];
-	u32 rfshctl0;
-	u32 res2[4];
-	u32 rfshtmg;
-	u32 rfshtmg1;
-	u32 res3[28];
-	u32 init3;
-	u32 init4;
-	u32 res;
-	u32 init6;
-	u32 init7;
-	u32 res4[4];
-	u32 dramtmg0;
-	u32 dramtmg1;
-	u32 dramtmg2;
-	u32 dramtmg3;
-	u32 dramtmg4;
-	u32 dramtmg5;
-	u32 dramtmg6;
-	u32 dramtmg7;
-	u32 dramtmg8;
-	u32 dramtmg9;
-	u32 dramtmg10;
-	u32 dramtmg11;
-	u32 dramtmg12;
-	u32 dramtmg13;
-	u32 dramtmg14;
-	u32 dramtmg15;
-	u32 dramtmg16;
-	u32 dramtmg17;
-	u32 res5[10];
-	u32 mramtmg0;
-	u32 mramtmg1;
-	u32 mramtmg4;
-	u32 mramtmg9;
-	u32 zqctl0;
-	u32 res6[3];
-	u32 dfitmg0;
-	u32 dfitmg1;
-	u32 res7[7];
-	u32 dfitmg2;
-	u32 dfitmg3;
-	u32 res8[33];
-	u32 odtcfg;
-};
-
-struct imx8m_ddrc_regs {
-	u32 mstr;
-	u32 stat;
-	u32 mstr1;
-	u32 res1;
-	u32 mrctrl0;
-	u32 mrctrl1;
-	u32 mrstat;
-	u32 mrctrl2;
-	u32 derateen;
-	u32 derateint;
-	u32 mstr2;
-	u32 res2;
-	u32 pwrctl;
-	u32 pwrtmg;
-	u32 hwlpctl;
-	u32 hwffcctl;
-	u32 hwffcstat;
-	u32 res3[3];
-	u32 rfshctl0;
-	u32 rfshctl1;
-	u32 rfshctl2;
-	u32 rfshctl4;
-	u32 rfshctl3;
-	u32 rfshtmg;
-	u32 rfshtmg1;
-	u32 res4;
-	u32 ecccfg0;
-	u32 ecccfg1;
-	u32 eccstat;
-	u32 eccclr;
-	u32 eccerrcnt;
-	u32 ecccaddr0;
-	u32 ecccaddr1;
-	u32 ecccsyn0;
-	u32 ecccsyn1;
-	u32 ecccsyn2;
-	u32 eccbitmask0;
-	u32 eccbitmask1;
-	u32 eccbitmask2;
-	u32 eccuaddr0;
-	u32 eccuaddr1;
-	u32 eccusyn0;
-	u32 eccusyn1;
-	u32 eccusyn2;
-	u32 eccpoisonaddr0;
-	u32 eccpoisonaddr1;
-	u32 crcparctl0;
-	u32 crcparctl1;
-	u32 crcparctl2;
-	u32 crcparstat;
-	u32 init0;
-	u32 init1;
-	u32 init2;
-	u32 init3;
-	u32 init4;
-	u32 init5;
-	u32 init6;
-	u32 init7;
-	u32 dimmctl;
-	u32 rankctl;
-	u32 res5;
-	u32 chctl;
-	u32 dramtmg0;
-	u32 dramtmg1;
-	u32 dramtmg2;
-	u32 dramtmg3;
-	u32 dramtmg4;
-	u32 dramtmg5;
-	u32 dramtmg6;
-	u32 dramtmg7;
-	u32 dramtmg8;
-	u32 dramtmg9;
-	u32 dramtmg10;
-	u32 dramtmg11;
-	u32 dramtmg12;
-	u32 dramtmg13;
-	u32 dramtmg14;
-	u32 dramtmg15;
-	u32 dramtmg16;
-	u32 dramtmg17;
-	u32 res6[10];
-	u32 mramtmg0;
-	u32 mramtmg1;
-	u32 mramtmg4;
-	u32 mramtmg9;
-	u32 zqctl0;
-	u32 zqctl1;
-	u32 zqctl2;
-	u32 zqstat;
-	u32 dfitmg0;
-	u32 dfitmg1;
-	u32 dfilpcfg0;
-	u32 dfilpcfg1;
-	u32 dfiupd0;
-	u32 dfiupd1;
-	u32 dfiupd2;
-	u32 res7;
-	u32 dfimisc;
-	u32 dfitmg2;
-	u32 dfitmg3;
-	u32 dfistat;
-	u32 dbictl;
-	u32 dfiphymstr;
-	u32 res8[14];
-	u32 addrmap0;
-	u32 addrmap1;
-	u32 addrmap2;
-	u32 addrmap3;
-	u32 addrmap4;
-	u32 addrmap5;
-	u32 addrmap6;
-	u32 addrmap7;
-	u32 addrmap8;
-	u32 addrmap9;
-	u32 addrmap10;
-	u32 addrmap11;
-	u32 res9[4];
-	u32 odtcfg;
-	u32 odtmap;
-	u32 res10[2];
-	u32 sched;
-	u32 sched1;
-	u32 sched2;
-	u32 perfhpr1;
-	u32 res11;
-	u32 perflpr1;
-	u32 res12;
-	u32 perfwr1;
-	u32 res13[4];
-	u32 dqmap0;
-	u32 dqmap1;
-	u32 dqmap2;
-	u32 dqmap3;
-	u32 dqmap4;
-	u32 dqmap5;
-	u32 res14[26];
-	u32 dbg0;
-	u32 dbg1;
-	u32 dbgcam;
-	u32 dbgcmd;
-	u32 dbgstat;
-	u32 res15[3];
-	u32 swctl;
-	u32 swstat;
-	u32 res16[2];
-	u32 ocparcfg0;
-	u32 ocparcfg1;
-	u32 ocparcfg2;
-	u32 ocparcfg3;
-	u32 ocparstat0;
-	u32 ocparstat1;
-	u32 ocparwlog0;
-	u32 ocparwlog1;
-	u32 ocparwlog2;
-	u32 ocparawlog0;
-	u32 ocparawlog1;
-	u32 ocparrlog0;
-	u32 ocparrlog1;
-	u32 ocpararlog0;
-	u32 ocpararlog1;
-	u32 poisoncfg;
-	u32 poisonstat;
-	u32 adveccindex;
-	union  {
-		u32 adveccstat;
-		u32 eccapstat;
-	};
-	u32 eccpoisonpat0;
-	u32 eccpoisonpat1;
-	u32 eccpoisonpat2;
-	u32 res17[6];
-	u32 caparpoisonctl;
-	u32 caparpoisonstat;
-	u32 res18[2];
-	u32 dynbsmstat;
-	u32 res19[18];
-	u32 pstat;
-	u32 pccfg;
-	struct {
-		u32 pcfgr;
-		u32 pcfgw;
-		u32 pcfgc;
-		struct {
-			u32 pcfgidmaskch0;
-			u32 pcfidvaluech0;
-		} pcfgid[16];
-		u32 pctrl;
-		u32 pcfgqos0;
-		u32 pcfgqos1;
-		u32 pcfgwqos0;
-		u32 pcfgwqos1;
-		u32 res[4];
-	} pcfg[16];
-	struct {
-		u32 sarbase;
-		u32 sarsize;
-	} sar[4];
-	u32 sbrctl;
-	u32 sbrstat;
-	u32 sbrwdata0;
-	u32 sbrwdata1;
-	u32 pdch;
-	u32 res20[755];
-	/* umctl2_regs_dch1 */
-	u32 ch1_stat;
-	u32 res21[2];
-	u32 ch1_mrctrl0;
-	u32 ch1_mrctrl1;
-	u32 ch1_mrstat;
-	u32 ch1_mrctrl2;
-	u32 res22[4];
-	u32 ch1_pwrctl;
-	u32 ch1_pwrtmg;
-	u32 ch1_hwlpctl;
-	u32 res23[15];
-	u32 ch1_eccstat;
-	u32 ch1_eccclr;
-	u32 ch1_eccerrcnt;
-	u32 ch1_ecccaddr0;
-	u32 ch1_ecccaddr1;
-	u32 ch1_ecccsyn0;
-	u32 ch1_ecccsyn1;
-	u32 ch1_ecccsyn2;
-	u32 ch1_eccbitmask0;
-	u32 ch1_eccbitmask1;
-	u32 ch1_eccbitmask2;
-	u32 ch1_eccuaddr0;
-	u32 ch1_eccuaddr1;
-	u32 ch1_eccusyn0;
-	u32 ch1_eccusyn1;
-	u32 ch1_eccusyn2;
-	u32 res24[2];
-	u32 ch1_crcparctl0;
-	u32 res25[2];
-	u32 ch1_crcparstat;
-	u32 res26[46];
-	u32 ch1_zqctl2;
-	u32 ch1_zqstat;
-	u32 res27[11];
-	u32 ch1_dfistat;
-	u32 res28[33];
-	u32 ch1_odtmap;
-	u32 res29[47];
-	u32 ch1_dbg1;
-	u32 ch1_dbgcam;
-	u32 ch1_dbgcmd;
-	u32 ch1_dbgstat;
-	u32 res30[123];
-	/* umctl2_regs_freq1 */
-	struct ddrc_freq freq1;
-	u32 res31[109];
-	/* umctl2_regs_addrmap_alt */
-	u32 addrmap0_alt;
-	u32 addrmap1_alt;
-	u32 addrmap2_alt;
-	u32 addrmap3_alt;
-	u32 addrmap4_alt;
-	u32 addrmap5_alt;
-	u32 addrmap6_alt;
-	u32 addrmap7_alt;
-	u32 addrmap8_alt;
-	u32 addrmap9_alt;
-	u32 addrmap10_alt;
-	u32 addrmap11_alt;
-	u32 res32[758];
-	/* umctl2_regs_freq2 */
-	struct ddrc_freq freq2;
-	u32 res33[879];
-	/* umctl2_regs_freq3 */
-	struct ddrc_freq freq3;
-};
-
-struct imx8m_ddrphy_regs {
-	u32 reg[0xf0000];
-};
-
-/* PHY State */
-enum pstate {
-	PS0,
-	PS1,
-	PS2,
-	PS3,
-};
-
-enum msg_response {
-	TRAIN_SUCCESS = 0x7,
-	TRAIN_STREAM_START = 0x8,
-	TRAIN_FAIL = 0xff,
-};
-
-#define DDRC_MSTR(X)             (DDRC_IPS_BASE_ADDR(X) + 0x00)
-#define DDRC_STAT(X)             (DDRC_IPS_BASE_ADDR(X) + 0x04)
-#define DDRC_MSTR1(X)            (DDRC_IPS_BASE_ADDR(X) + 0x08)
-#define DDRC_MRCTRL0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x10)
-#define DDRC_MRCTRL1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x14)
-#define DDRC_MRSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18)
-#define DDRC_MRCTRL2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1c)
-#define DDRC_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20)
-#define DDRC_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x24)
-#define DDRC_MSTR2(X)            (DDRC_IPS_BASE_ADDR(X) + 0x28)
-#define DDRC_PWRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30)
-#define DDRC_PWRTMG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x34)
-#define DDRC_HWLPCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0x38)
-#define DDRC_HWFFCCTL(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3c)
-#define DDRC_HWFFCSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x40)
-#define DDRC_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x50)
-#define DDRC_RFSHCTL1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x54)
-#define DDRC_RFSHCTL2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x58)
-#define DDRC_RFSHCTL3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x60)
-#define DDRC_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x64)
-#define DDRC_ECCCFG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x70)
-#define DDRC_ECCCFG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x74)
-#define DDRC_ECCSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x78)
-#define DDRC_ECCCLR(X)           (DDRC_IPS_BASE_ADDR(X) + 0x7c)
-#define DDRC_ECCERRCNT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x80)
-#define DDRC_ECCCADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x84)
-#define DDRC_ECCCADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x88)
-#define DDRC_ECCCSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x8c)
-#define DDRC_ECCCSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x90)
-#define DDRC_ECCCSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x94)
-#define DDRC_ECCBITMASK0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x98)
-#define DDRC_ECCBITMASK1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x9c)
-#define DDRC_ECCBITMASK2(X)      (DDRC_IPS_BASE_ADDR(X) + 0xa0)
-#define DDRC_ECCUADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa4)
-#define DDRC_ECCUADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa8)
-#define DDRC_ECCUSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xac)
-#define DDRC_ECCUSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb0)
-#define DDRC_ECCUSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb4)
-#define DDRC_ECCPOISONADDR0(X)   (DDRC_IPS_BASE_ADDR(X) + 0xb8)
-#define DDRC_ECCPOISONADDR1(X)   (DDRC_IPS_BASE_ADDR(X) + 0xbc)
-#define DDRC_CRCPARCTL0(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc0)
-#define DDRC_CRCPARCTL1(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc4)
-#define DDRC_CRCPARCTL2(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc8)
-#define DDRC_CRCPARSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0xcc)
-#define DDRC_INIT0(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd0)
-#define DDRC_INIT1(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd4)
-#define DDRC_INIT2(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd8)
-#define DDRC_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0xdc)
-#define DDRC_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe0)
-#define DDRC_INIT5(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe4)
-#define DDRC_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe8)
-#define DDRC_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0xec)
-#define DDRC_DIMMCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf0)
-#define DDRC_RANKCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf4)
-#define DDRC_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x100)
-#define DDRC_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x104)
-#define DDRC_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x108)
-#define DDRC_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x10c)
-#define DDRC_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x110)
-#define DDRC_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x114)
-#define DDRC_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x118)
-#define DDRC_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x11c)
-#define DDRC_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x120)
-#define DDRC_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x124)
-#define DDRC_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x128)
-#define DDRC_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x12c)
-#define DDRC_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x130)
-#define DDRC_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x134)
-#define DDRC_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x138)
-#define DDRC_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x13C)
-#define DDRC_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x140)
-#define DDRC_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x144)
-#define DDRC_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x180)
-#define DDRC_ZQCTL1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x184)
-#define DDRC_ZQCTL2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x188)
-#define DDRC_ZQSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18c)
-#define DDRC_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x190)
-#define DDRC_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x194)
-#define DDRC_DFILPCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x198)
-#define DDRC_DFILPCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x19c)
-#define DDRC_DFIUPD0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
-#define DDRC_DFIUPD1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
-#define DDRC_DFIUPD2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
-#define DDRC_DFIMISC(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
-#define DDRC_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
-#define DDRC_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
-#define DDRC_DFISTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
-#define DDRC_DBICTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
-#define DDRC_DFIPHYMSTR(X)       (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
-#define DDRC_TRAINCTL0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
-#define DDRC_TRAINCTL1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
-#define DDRC_TRAINCTL2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
-#define DDRC_TRAINSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
-#define DDRC_ADDRMAP0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x200)
-#define DDRC_ADDRMAP1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x204)
-#define DDRC_ADDRMAP2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x208)
-#define DDRC_ADDRMAP3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20c)
-#define DDRC_ADDRMAP4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210)
-#define DDRC_ADDRMAP5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x214)
-#define DDRC_ADDRMAP6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x218)
-#define DDRC_ADDRMAP7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21c)
-#define DDRC_ADDRMAP8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x220)
-#define DDRC_ADDRMAP9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x224)
-#define DDRC_ADDRMAP10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x228)
-#define DDRC_ADDRMAP11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x22c)
-#define DDRC_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x240)
-#define DDRC_ODTMAP(X)           (DDRC_IPS_BASE_ADDR(X) + 0x244)
-#define DDRC_SCHED(X)            (DDRC_IPS_BASE_ADDR(X) + 0x250)
-#define DDRC_SCHED1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x254)
-#define DDRC_PERFHPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x25c)
-#define DDRC_PERFLPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x264)
-#define DDRC_PERFWR1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x26c)
-#define DDRC_PERFVPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x274)
-#define DDRC_PERFVPW1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x278)
-#define DDRC_DQMAP0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x280)
-#define DDRC_DQMAP1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x284)
-#define DDRC_DQMAP2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x288)
-#define DDRC_DQMAP3(X)           (DDRC_IPS_BASE_ADDR(X) + 0x28c)
-#define DDRC_DQMAP4(X)           (DDRC_IPS_BASE_ADDR(X) + 0x290)
-#define DDRC_DQMAP5(X)           (DDRC_IPS_BASE_ADDR(X) + 0x294)
-#define DDRC_DBG0(X)             (DDRC_IPS_BASE_ADDR(X) + 0x300)
-#define DDRC_DBG1(X)             (DDRC_IPS_BASE_ADDR(X) + 0x304)
-#define DDRC_DBGCAM(X)           (DDRC_IPS_BASE_ADDR(X) + 0x308)
-#define DDRC_DBGCMD(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30c)
-#define DDRC_DBGSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x310)
-#define DDRC_SWCTL(X)            (DDRC_IPS_BASE_ADDR(X) + 0x320)
-#define DDRC_SWSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x324)
-#define DDRC_OCPARCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x330)
-#define DDRC_OCPARCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x334)
-#define DDRC_OCPARCFG2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x338)
-#define DDRC_OCPARCFG3(X)        (DDRC_IPS_BASE_ADDR(X) + 0x33c)
-#define DDRC_OCPARSTAT0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x340)
-#define DDRC_OCPARSTAT1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x344)
-#define DDRC_OCPARWLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x348)
-#define DDRC_OCPARWLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x34c)
-#define DDRC_OCPARWLOG2(X)       (DDRC_IPS_BASE_ADDR(X) + 0x350)
-#define DDRC_OCPARAWLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x354)
-#define DDRC_OCPARAWLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x358)
-#define DDRC_OCPARRLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x35c)
-#define DDRC_OCPARRLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x360)
-#define DDRC_OCPARARLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x364)
-#define DDRC_OCPARARLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x368)
-#define DDRC_POISONCFG(X)        (DDRC_IPS_BASE_ADDR(X) + 0x36C)
-#define DDRC_POISONSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0x370)
-
-#define DDRC_PSTAT(X)            (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
-#define DDRC_PCCFG(X)            (DDRC_IPS_BASE_ADDR(X) + 0x400)
-#define DDRC_PCFGR_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x404)
-#define DDRC_PCFGR_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
-#define DDRC_PCFGR_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
-#define DDRC_PCFGR_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
-#define DDRC_PCFGW_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x408)
-#define DDRC_PCFGW_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
-#define DDRC_PCFGW_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
-#define DDRC_PCFGW_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
-#define DDRC_PCFGC_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x40c)
-#define DDRC_PCFGIDMASKCH(X)     (DDRC_IPS_BASE_ADDR(X) + 0x410)
-#define DDRC_PCFGIDVALUECH(X)    (DDRC_IPS_BASE_ADDR(X) + 0x414)
-#define DDRC_PCTRL_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490)
-#define DDRC_PCTRL_1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
-#define DDRC_PCTRL_2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
-#define DDRC_PCTRL_3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
-#define DDRC_PCFGQOS0_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x494)
-#define DDRC_PCFGQOS1_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x498)
-#define DDRC_PCFGWQOS0_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x49c)
-#define DDRC_PCFGWQOS1_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
-#define DDRC_SARBASE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf04)
-#define DDRC_SARSIZE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf08)
-#define DDRC_SBRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0xf24)
-#define DDRC_SBRSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf28)
-#define DDRC_SBRWDATA0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
-#define DDRC_SBRWDATA1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf30)
-#define DDRC_PDCH(X)             (DDRC_IPS_BASE_ADDR(X) + 0xf34)
-
-#define DDRC_FREQ1_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2020)
-#define DDRC_FREQ1_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2024)
-#define DDRC_FREQ1_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2050)
-#define DDRC_FREQ1_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2064)
-#define DDRC_FREQ1_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
-#define DDRC_FREQ1_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
-#define DDRC_FREQ1_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
-#define DDRC_FREQ1_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
-#define DDRC_FREQ1_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2100)
-#define DDRC_FREQ1_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2104)
-#define DDRC_FREQ1_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2108)
-#define DDRC_FREQ1_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210c)
-#define DDRC_FREQ1_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2110)
-#define DDRC_FREQ1_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2114)
-#define DDRC_FREQ1_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2118)
-#define DDRC_FREQ1_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x211c)
-#define DDRC_FREQ1_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2120)
-#define DDRC_FREQ1_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2124)
-#define DDRC_FREQ1_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2128)
-#define DDRC_FREQ1_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x212c)
-#define DDRC_FREQ1_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2130)
-#define DDRC_FREQ1_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2134)
-#define DDRC_FREQ1_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2138)
-#define DDRC_FREQ1_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x213C)
-#define DDRC_FREQ1_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2140)
-#define DDRC_FREQ1_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2144)
-#define DDRC_FREQ1_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2180)
-#define DDRC_FREQ1_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2190)
-#define DDRC_FREQ1_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2194)
-#define DDRC_FREQ1_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
-#define DDRC_FREQ1_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
-#define DDRC_FREQ1_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2240)
-
-#define DDRC_FREQ2_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3020)
-#define DDRC_FREQ2_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3024)
-#define DDRC_FREQ2_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3050)
-#define DDRC_FREQ2_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3064)
-#define DDRC_FREQ2_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
-#define DDRC_FREQ2_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
-#define DDRC_FREQ2_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
-#define DDRC_FREQ2_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
-#define DDRC_FREQ2_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3100)
-#define DDRC_FREQ2_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3104)
-#define DDRC_FREQ2_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3108)
-#define DDRC_FREQ2_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x310c)
-#define DDRC_FREQ2_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3110)
-#define DDRC_FREQ2_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3114)
-#define DDRC_FREQ2_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3118)
-#define DDRC_FREQ2_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x311c)
-#define DDRC_FREQ2_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3120)
-#define DDRC_FREQ2_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3124)
-#define DDRC_FREQ2_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3128)
-#define DDRC_FREQ2_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x312c)
-#define DDRC_FREQ2_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3130)
-#define DDRC_FREQ2_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3134)
-#define DDRC_FREQ2_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3138)
-#define DDRC_FREQ2_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x313C)
-#define DDRC_FREQ2_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3140)
-#define DDRC_FREQ2_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3144)
-#define DDRC_FREQ2_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3180)
-#define DDRC_FREQ2_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3190)
-#define DDRC_FREQ2_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3194)
-#define DDRC_FREQ2_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
-#define DDRC_FREQ2_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
-#define DDRC_FREQ2_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3240)
-
-#define DDRC_FREQ3_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4020)
-#define DDRC_FREQ3_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4024)
-#define DDRC_FREQ3_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4050)
-#define DDRC_FREQ3_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4064)
-#define DDRC_FREQ3_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
-#define DDRC_FREQ3_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
-#define DDRC_FREQ3_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
-#define DDRC_FREQ3_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
-#define DDRC_FREQ3_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4100)
-#define DDRC_FREQ3_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4104)
-#define DDRC_FREQ3_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4108)
-#define DDRC_FREQ3_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x410c)
-#define DDRC_FREQ3_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4110)
-#define DDRC_FREQ3_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4114)
-#define DDRC_FREQ3_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4118)
-#define DDRC_FREQ3_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x411c)
-#define DDRC_FREQ3_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4120)
-#define DDRC_FREQ3_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4124)
-#define DDRC_FREQ3_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4128)
-#define DDRC_FREQ3_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x412c)
-#define DDRC_FREQ3_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4130)
-#define DDRC_FREQ3_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4134)
-#define DDRC_FREQ3_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4138)
-#define DDRC_FREQ3_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x413C)
-#define DDRC_FREQ3_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4140)
-
-#define DDRC_FREQ3_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4180)
-#define DDRC_FREQ3_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4190)
-#define DDRC_FREQ3_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4194)
-#define DDRC_FREQ3_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
-#define DDRC_FREQ3_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
-#define DDRC_FREQ3_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4240)
-#define DDRC_DFITMG0_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2190)
-#define DDRC_DFITMG1_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2194)
-#define DDRC_DFITMG2_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
-#define DDRC_DFITMG3_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
-#define DDRC_ODTCFG_SHADOW(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2240)
-
-#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
-
-#define DRC_PERF_MON_BASE_ADDR(X)            (0x3d800000 + ((X) * 0x2000000))
-#define DRC_PERF_MON_CNT0_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
-#define DRC_PERF_MON_CNT1_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
-#define DRC_PERF_MON_CNT2_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
-#define DRC_PERF_MON_CNT3_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
-#define DRC_PERF_MON_CNT0_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
-#define DRC_PERF_MON_CNT1_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
-#define DRC_PERF_MON_CNT2_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
-#define DRC_PERF_MON_CNT3_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
-#define DRC_PERF_MON_MRR0_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
-#define DRC_PERF_MON_MRR1_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
-#define DRC_PERF_MON_MRR2_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
-#define DRC_PERF_MON_MRR3_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
-#define DRC_PERF_MON_MRR4_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
-#define DRC_PERF_MON_MRR5_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
-#define DRC_PERF_MON_MRR6_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
-#define DRC_PERF_MON_MRR7_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
-#define DRC_PERF_MON_MRR8_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
-#define DRC_PERF_MON_MRR9_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
-#define DRC_PERF_MON_MRR10_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
-#define DRC_PERF_MON_MRR11_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
-#define DRC_PERF_MON_MRR12_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
-#define DRC_PERF_MON_MRR13_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
-#define DRC_PERF_MON_MRR14_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
-#define DRC_PERF_MON_MRR15_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
-
-/* user data type */
-enum fw_type {
-	FW_1D_IMAGE,
-	FW_2D_IMAGE,
-};
-
-struct dram_cfg_param {
-	unsigned int reg;
-	unsigned int val;
-};
-
-struct dram_fsp_msg {
-	unsigned int drate;
-	enum fw_type fw_type;
-	struct dram_cfg_param *fsp_cfg;
-	unsigned int fsp_cfg_num;
-};
-
-struct dram_timing_info {
-	/* umctl2 config */
-	struct dram_cfg_param *ddrc_cfg;
-	unsigned int ddrc_cfg_num;
-	/* ddrphy config */
-	struct dram_cfg_param *ddrphy_cfg;
-	unsigned int ddrphy_cfg_num;
-	/* ddr fsp train info */
-	struct dram_fsp_msg *fsp_msg;
-	unsigned int fsp_msg_num;
-	/* ddr phy trained CSR */
-	struct dram_cfg_param *ddrphy_trained_csr;
-	unsigned int ddrphy_trained_csr_num;
-	/* ddr phy PIE */
-	struct dram_cfg_param *ddrphy_pie;
-	unsigned int ddrphy_pie_num;
-	/* initialized drate table */
-	unsigned int fsp_table[4];
-};
-
-extern struct dram_timing_info dram_timing;
-
-void ddr_load_train_firmware(enum fw_type type);
-void ddr_init(struct dram_timing_info *timing_info);
-void ddr_cfg_phy(struct dram_timing_info *timing_info);
-void load_lpddr4_phy_pie(void);
-void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
-void dram_config_save(struct dram_timing_info *info, unsigned long base);
-
-/* utils function for ddr phy training */
-void wait_ddrphy_training_complete(void);
-void ddrphy_init_set_dfi_clk(unsigned int drate);
-void ddrphy_init_read_msg_block(enum fw_type type);
-
-static inline void reg32_write(unsigned long addr, u32 val)
-{
-	writel(val, addr);
-}
-
-static inline u32 reg32_read(unsigned long addr)
-{
-	return readl(addr);
-}
-
-static inline void reg32setbit(unsigned long addr, u32 bit)
-{
-	setbits_le32(addr, (1 << bit));
-}
-
-#define dwc_ddrphy_apb_wr(addr, data) \
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
-#define dwc_ddrphy_apb_rd(addr) \
-	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
-
-extern struct dram_cfg_param ddrphy_trained_csr[];
-extern uint32_t ddrphy_trained_csr_num;
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h
deleted file mode 100644
index 2d9fbcb..0000000
--- a/arch/arm/include/asm/arch-imx8m/gpio.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- */
-
-#ifndef __ASM_ARCH_IMX8M_GPIO_H
-#define __ASM_ARCH_IMX8M_GPIO_H
-
-#include <asm/mach-imx/gpio.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
deleted file mode 100644
index 62640d9..0000000
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- */
-
-#ifndef __ASM_ARCH_IMX8M_REGS_H__
-#define __ASM_ARCH_IMX8M_REGS_H__
-
-#define ARCH_MXC
-
-#include <asm/mach-imx/regs-lcdif.h>
-
-#define ROM_VERSION_A0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
-#define ROM_VERSION_B0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
-
-#define M4_BOOTROM_BASE_ADDR   0x007E0000
-
-#define GPIO1_BASE_ADDR		0X30200000
-#define GPIO2_BASE_ADDR		0x30210000
-#define GPIO3_BASE_ADDR		0x30220000
-#define GPIO4_BASE_ADDR		0x30230000
-#define GPIO5_BASE_ADDR		0x30240000
-#define WDOG1_BASE_ADDR		0x30280000
-#define WDOG2_BASE_ADDR		0x30290000
-#define WDOG3_BASE_ADDR		0x302A0000
-#define IOMUXC_BASE_ADDR	0x30330000
-#define IOMUXC_GPR_BASE_ADDR	0x30340000
-#define OCOTP_BASE_ADDR		0x30350000
-#define ANATOP_BASE_ADDR	0x30360000
-#define CCM_BASE_ADDR		0x30380000
-#define SRC_BASE_ADDR		0x30390000
-#define GPC_BASE_ADDR		0x303A0000
-
-#define SYSCNT_RD_BASE_ADDR	0x306A0000
-#define SYSCNT_CMP_BASE_ADDR	0x306B0000
-#define SYSCNT_CTRL_BASE_ADDR	0x306C0000
-
-#define UART1_BASE_ADDR		0x30860000
-#define UART3_BASE_ADDR		0x30880000
-#define UART2_BASE_ADDR		0x30890000
-#define I2C1_BASE_ADDR		0x30A20000
-#define I2C2_BASE_ADDR		0x30A30000
-#define I2C3_BASE_ADDR		0x30A40000
-#define I2C4_BASE_ADDR		0x30A50000
-#define UART4_BASE_ADDR		0x30A60000
-#define USDHC1_BASE_ADDR	0x30B40000
-#define USDHC2_BASE_ADDR	0x30B50000
-#ifdef CONFIG_IMX8MM
-#define USDHC3_BASE_ADDR	0x30B60000
-#endif
-
-#define TZASC_BASE_ADDR		0x32F80000
-
-#define MXS_LCDIF_BASE		IS_ENABLED(CONFIG_IMX8MQ) ? \
-					0x30320000 : 0x32e00000
-
-#define SRC_IPS_BASE_ADDR	0x30390000
-#define SRC_DDRC_RCR_ADDR	0x30391000
-#define SRC_DDRC2_RCR_ADDR	0x30391004
-
-#define DDRC_DDR_SS_GPR0	0x3d000000
-#define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
-#define DDR_CSD1_BASE_ADDR	0x40000000
-
-#if !defined(__ASSEMBLY__)
-#include <asm/types.h>
-#include <linux/bitops.h>
-#include <stdbool.h>
-
-#define GPR_TZASC_EN		BIT(0)
-#define GPR_TZASC_EN_LOCK	BIT(16)
-
-#define SRC_SCR_M4_ENABLE_OFFSET	3
-#define SRC_SCR_M4_ENABLE_MASK		BIT(3)
-#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET	0
-#define SRC_SCR_M4C_NON_SCLR_RST_MASK	BIT(0)
-#define SRC_DDR1_ENABLE_MASK		0x8F000000UL
-#define SRC_DDR2_ENABLE_MASK		0x8F000000UL
-#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK	BIT(3)
-#define SRC_DDR1_RCR_PHY_RESET_MASK	BIT(2)
-#define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
-#define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
-
-struct iomuxc_gpr_base_regs {
-	u32 gpr[47];
-};
-
-struct ocotp_regs {
-	u32	ctrl;
-	u32	ctrl_set;
-	u32     ctrl_clr;
-	u32	ctrl_tog;
-	u32	timing;
-	u32     rsvd0[3];
-	u32     data;
-	u32     rsvd1[3];
-	u32     read_ctrl;
-	u32     rsvd2[3];
-	u32	read_fuse_data;
-	u32     rsvd3[3];
-	u32	sw_sticky;
-	u32     rsvd4[3];
-	u32     scs;
-	u32     scs_set;
-	u32     scs_clr;
-	u32     scs_tog;
-	u32     crc_addr;
-	u32     rsvd5[3];
-	u32     crc_value;
-	u32     rsvd6[3];
-	u32     version;
-	u32     rsvd7[0xdb];
-
-	/* fuse banks */
-	struct fuse_bank {
-		u32	fuse_regs[0x10];
-	} bank[0];
-};
-
-struct fuse_bank0_regs {
-	u32 lock;
-	u32 rsvd0[3];
-	u32 uid_low;
-	u32 rsvd1[3];
-	u32 uid_high;
-	u32 rsvd2[7];
-};
-
-struct fuse_bank1_regs {
-	u32 tester3;
-	u32 rsvd0[3];
-	u32 tester4;
-	u32 rsvd1[3];
-	u32 tester5;
-	u32 rsvd2[3];
-	u32 cfg0;
-	u32 rsvd3[3];
-};
-
-#ifdef CONFIG_IMX8MQ
-struct anamix_pll {
-	u32 audio_pll1_cfg0;
-	u32 audio_pll1_cfg1;
-	u32 audio_pll2_cfg0;
-	u32 audio_pll2_cfg1;
-	u32 video_pll_cfg0;
-	u32 video_pll_cfg1;
-	u32 gpu_pll_cfg0;
-	u32 gpu_pll_cfg1;
-	u32 vpu_pll_cfg0;
-	u32 vpu_pll_cfg1;
-	u32 arm_pll_cfg0;
-	u32 arm_pll_cfg1;
-	u32 sys_pll1_cfg0;
-	u32 sys_pll1_cfg1;
-	u32 sys_pll1_cfg2;
-	u32 sys_pll2_cfg0;
-	u32 sys_pll2_cfg1;
-	u32 sys_pll2_cfg2;
-	u32 sys_pll3_cfg0;
-	u32 sys_pll3_cfg1;
-	u32 sys_pll3_cfg2;
-	u32 video_pll2_cfg0;
-	u32 video_pll2_cfg1;
-	u32 video_pll2_cfg2;
-	u32 dram_pll_cfg0;
-	u32 dram_pll_cfg1;
-	u32 dram_pll_cfg2;
-	u32 digprog;
-	u32 osc_misc_cfg;
-	u32 pllout_monitor_cfg;
-	u32 frac_pllout_div_cfg;
-	u32 sscg_pllout_div_cfg;
-};
-#else
-struct anamix_pll {
-	u32 audio_pll1_gnrl_ctl;
-	u32 audio_pll1_fdiv_ctl0;
-	u32 audio_pll1_fdiv_ctl1;
-	u32 audio_pll1_sscg_ctl;
-	u32 audio_pll1_mnit_ctl;
-	u32 audio_pll2_gnrl_ctl;
-	u32 audio_pll2_fdiv_ctl0;
-	u32 audio_pll2_fdiv_ctl1;
-	u32 audio_pll2_sscg_ctl;
-	u32 audio_pll2_mnit_ctl;
-	u32 video_pll1_gnrl_ctl;
-	u32 video_pll1_fdiv_ctl0;
-	u32 video_pll1_fdiv_ctl1;
-	u32 video_pll1_sscg_ctl;
-	u32 video_pll1_mnit_ctl;
-	u32 reserved[5];
-	u32 dram_pll_gnrl_ctl;
-	u32 dram_pll_fdiv_ctl0;
-	u32 dram_pll_fdiv_ctl1;
-	u32 dram_pll_sscg_ctl;
-	u32 dram_pll_mnit_ctl;
-	u32 gpu_pll_gnrl_ctl;
-	u32 gpu_pll_div_ctl;
-	u32 gpu_pll_locked_ctl1;
-	u32 gpu_pll_mnit_ctl;
-	u32 vpu_pll_gnrl_ctl;
-	u32 vpu_pll_div_ctl;
-	u32 vpu_pll_locked_ctl1;
-	u32 vpu_pll_mnit_ctl;
-	u32 arm_pll_gnrl_ctl;
-	u32 arm_pll_div_ctl;
-	u32 arm_pll_locked_ctl1;
-	u32 arm_pll_mnit_ctl;
-	u32 sys_pll1_gnrl_ctl;
-	u32 sys_pll1_div_ctl;
-	u32 sys_pll1_locked_ctl1;
-	u32 reserved2[24];
-	u32 sys_pll1_mnit_ctl;
-	u32 sys_pll2_gnrl_ctl;
-	u32 sys_pll2_div_ctl;
-	u32 sys_pll2_locked_ctl1;
-	u32 sys_pll2_mnit_ctl;
-	u32 sys_pll3_gnrl_ctl;
-	u32 sys_pll3_div_ctl;
-	u32 sys_pll3_locked_ctl1;
-	u32 sys_pll3_mnit_ctl;
-	u32 anamix_misc_ctl;
-	u32 anamix_clk_mnit_ctl;
-	u32 reserved3[437];
-	u32 digprog;
-};
-#endif
-
-struct fuse_bank9_regs {
-	u32 mac_addr0;
-	u32 rsvd0[3];
-	u32 mac_addr1;
-	u32 rsvd1[11];
-};
-
-/* System Reset Controller (SRC) */
-struct src {
-	u32 scr;
-	u32 a53rcr;
-	u32 a53rcr1;
-	u32 m4rcr;
-	u32 reserved1[4];
-	u32 usbophy1_rcr;
-	u32 usbophy2_rcr;
-	u32 mipiphy_rcr;
-	u32 pciephy_rcr;
-	u32 hdmi_rcr;
-	u32 disp_rcr;
-	u32 reserved2[2];
-	u32 gpu_rcr;
-	u32 vpu_rcr;
-	u32 pcie2_rcr;
-	u32 mipiphy1_rcr;
-	u32 mipiphy2_rcr;
-	u32 reserved3;
-	u32 sbmr1;
-	u32 srsr;
-	u32 reserved4[2];
-	u32 sisr;
-	u32 simr;
-	u32 sbmr2;
-	u32 gpr1;
-	u32 gpr2;
-	u32 gpr3;
-	u32 gpr4;
-	u32 gpr5;
-	u32 gpr6;
-	u32 gpr7;
-	u32 gpr8;
-	u32 gpr9;
-	u32 gpr10;
-	u32 reserved5[985];
-	u32 ddr1_rcr;
-	u32 ddr2_rcr;
-};
-
-#define WDOG_WDT_MASK	BIT(3)
-#define WDOG_WDZST_MASK	BIT(0)
-struct wdog_regs {
-	u16	wcr;	/* Control */
-	u16	wsr;	/* Service */
-	u16	wrsr;	/* Reset Status */
-	u16	wicr;	/* Interrupt Control */
-	u16	wmcr;	/* Miscellaneous Control */
-};
-
-struct bootrom_sw_info {
-	u8 reserved_1;
-	u8 boot_dev_instance;
-	u8 boot_dev_type;
-	u8 reserved_2;
-	u32 core_freq;
-	u32 axi_freq;
-	u32 ddr_freq;
-	u32 tick_freq;
-	u32 reserved_3[3];
-};
-
-#define ROM_SW_INFO_ADDR_B0	(IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
-				 0x000009e8)
-#define ROM_SW_INFO_ADDR_A0	0x000009e8
-
-#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
-		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
-		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
deleted file mode 100644
index 210e96e..0000000
--- a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
+++ /dev/null
@@ -1,691 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018-2019 NXP
- */
-
-#ifndef __ASM_ARCH_IMX8MM_PINS_H__
-#define __ASM_ARCH_IMX8MM_PINS_H__
-
-#include <asm/mach-imx/iomux-v3.h>
-
-enum {
-	IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0                               =  IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT               =  IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K                     =  IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1                            =  IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1                               =  IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO01_PWM1_OUT                                =  IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M                     =  IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2                            =  IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2                               =  IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B                            =  IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY                          =  IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3                               =  IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT                          =  IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0                        =  IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4                               =  IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT                          =  IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1                        =  IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5                               =  IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI                     =  IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY                          =  IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
-	IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT                            =  IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6                               =  IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO06_ENET1_MDC                               =  IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B                             =  IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3                            =  IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7                               =  IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO                              =  IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
-	IMX8MM_PAD_GPIO1_IO07_USDHC1_WP                               =  IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4                            =  IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8                               =  IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN                    =  IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B                          =  IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO08_CCM_WAIT                                =  IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9                               =  IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT                   =  IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B                          =  IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0                        =  IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO09_CCM_STOP                                =  IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10                              =  IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID                             =  IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11                              =  IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID                             =  IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT                          =  IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY                          =  IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
-	IMX8MM_PAD_GPIO1_IO11_CCM_OUT0                                =  IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12                              =  IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR                            =  IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1                        =  IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO12_CCM_OUT1                                =  IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13                              =  IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC                             =  IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO13_PWM2_OUT                                =  IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO13_CCM_OUT2                                =  IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14                              =  IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR                            =  IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B                             =  IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0),
-	IMX8MM_PAD_GPIO1_IO14_PWM3_OUT                                =  IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1                               =  IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15                              =  IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC                             =  IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO15_USDHC3_WP                               =  IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0),
-	IMX8MM_PAD_GPIO1_IO15_PWM4_OUT                                =  IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2                               =  IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_MDC_ENET1_MDC                                 =  IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_MDC_GPIO1_IO16                                =  IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_MDIO_ENET1_MDIO                               =  IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
-	IMX8MM_PAD_ENET_MDIO_GPIO1_IO17                               =  IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3                           =  IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD3_GPIO1_IO18                                =  IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2                           =  IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK                              =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT                     =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD2_GPIO1_IO19                                =  IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1                           =  IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD1_GPIO1_IO20                                =  IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0                           =  IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TD0_GPIO1_IO21                                =  IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL                     =  IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22                             =  IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC                           =  IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TXC_ENET1_TX_ER                               =  IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_TXC_GPIO1_IO23                                =  IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL                     =  IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24                             =  IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC                           =  IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RXC_ENET1_RX_ER                               =  IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RXC_GPIO1_IO25                                =  IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0                           =  IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD0_GPIO1_IO26                                =  IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1                           =  IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD1_GPIO1_IO27                                =  IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2                           =  IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD2_GPIO1_IO28                                =  IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3                           =  IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ENET_RD3_GPIO1_IO29                                =  IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_CLK_USDHC1_CLK                                 =  IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_CLK_GPIO2_IO0                                  =  IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_CMD_USDHC1_CMD                                 =  IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_CMD_GPIO2_IO1                                  =  IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0                             =  IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA0_GPIO2_IO2                                =  IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1                             =  IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA1_GPIO2_IO3                                =  IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2                             =  IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA2_GPIO2_IO4                                =  IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3                             =  IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA3_GPIO2_IO5                                =  IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4                             =  IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA4_GPIO2_IO6                                =  IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5                             =  IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA5_GPIO2_IO7                                =  IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6                             =  IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA6_GPIO2_IO8                                =  IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7                             =  IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_DATA7_GPIO2_IO9                                =  IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B                         =  IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10                             =  IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE                           =  IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD1_STROBE_GPIO2_IO11                              =  IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B                               =  IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CD_B_GPIO2_IO12                                =  IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_CLK_USDHC2_CLK                                 =  IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CLK_GPIO2_IO13                                 =  IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0                               =  IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_CMD_USDHC2_CMD                                 =  IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CMD_GPIO2_IO14                                 =  IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1                               =  IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0                             =  IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA0_GPIO2_IO15                               =  IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2                             =  IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1                             =  IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA1_GPIO2_IO16                               =  IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA1_CCM_WAIT                                 =  IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2                             =  IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA2_GPIO2_IO17                               =  IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA2_CCM_STOP                                 =  IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3                             =  IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA3_GPIO2_IO18                               =  IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET                          =  IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B                         =  IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19                             =  IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET                       =  IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SD2_WP_USDHC2_WP                                   =  IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SD2_WP_GPIO2_IO20                                  =  IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE                               =  IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK                               =  IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_ALE_GPIO3_IO0                                 =  IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B                           =  IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B                            =  IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1                               =  IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B                           =  IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B                            =  IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE                           =  IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2                               =  IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B                           =  IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B                            =  IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5                            =  IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3                               =  IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B                           =  IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B                            =  IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6                            =  IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4                               =  IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE                               =  IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK                               =  IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7                              =  IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_CLE_GPIO3_IO5                                 =  IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00                         =  IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0                           =  IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA00_GPIO3_IO6                              =  IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01                         =  IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1                           =  IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA01_GPIO3_IO7                              =  IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02                         =  IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2                           =  IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B                            =  IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0),
-	IMX8MM_PAD_NAND_DATA02_GPIO3_IO8                              =  IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03                         =  IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3                           =  IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA03_USDHC3_WP                              =  IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0),
-	IMX8MM_PAD_NAND_DATA03_GPIO3_IO9                              =  IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04                         =  IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA04_GPIO3_IO10                             =  IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05                         =  IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA05_GPIO3_IO11                             =  IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06                         =  IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA06_GPIO3_IO12                             =  IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07                         =  IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DATA07_GPIO3_IO13                             =  IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_DQS_RAWNAND_DQS                               =  IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DQS_QSPI_A_DQS                                =  IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_DQS_GPIO3_IO14                                =  IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B                             =  IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS                               =  IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4                             =  IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_RE_B_GPIO3_IO15                               =  IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B                       =  IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B                        =  IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_READY_B_GPIO3_IO16                            =  IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B                             =  IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK                               =  IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WE_B_GPIO3_IO17                               =  IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B                             =  IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD                               =  IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_NAND_WP_B_GPIO3_IO18                               =  IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
-	IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19                               =  IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
-	IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1                             =  IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXC_PDM_CLK                                   =  IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXC_GPIO3_IO20                                =  IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
-	IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
-	IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21                               =  IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3                            =  IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
-	IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22                               =  IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
-	IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK                             =  IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
-	IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23                               =  IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5                            =  IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
-	IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
-	IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24                               =  IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
-	IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
-	IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25                               =  IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK                           =  IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
-	IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
-	IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK                   =  IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0                                =  IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
-	IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL                    =  IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXC_GPIO4_IO1                                 =  IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
-	IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0),
-	IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0                      =  IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2                                =  IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0                            =  IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
-	IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0),
-	IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1                      =  IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3                                =  IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1                            =  IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
-	IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0),
-	IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2                      =  IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4                                =  IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2                            =  IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0),
-	IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0),
-	IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3                      =  IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5                                =  IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3                            =  IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4                            =  IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4                      =  IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6                                =  IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4                            =  IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5                            =  IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
-	IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5                      =  IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7                                =  IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5                            =  IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6                            =  IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6                      =  IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8                                =  IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6                            =  IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7                            =  IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK                                =  IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
-	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7                      =  IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9                                =  IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7                            =  IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
-	IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
-	IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO                      =  IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10                               =  IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
-	IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
-	IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI                       =  IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXC_GPIO4_IO11                                =  IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8                      =  IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12                               =  IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8                            =  IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9                      =  IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13                               =  IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9                            =  IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10                     =  IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14                               =  IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10                           =  IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11                     =  IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15                               =  IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11                           =  IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4                            =  IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
-	IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
-	IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12                     =  IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16                               =  IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12                           =  IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5                            =  IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
-	IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13                     =  IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17                               =  IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13                           =  IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6                            =  IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
-	IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
-	IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14                     =  IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18                               =  IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14                           =  IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7                            =  IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK                                =  IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
-	IMX8MM_PAD_SAI1_TXD7_PDM_CLK                                  =  IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15                     =  IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19                               =  IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15                           =  IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
-	IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
-	IMX8MM_PAD_SAI1_MCLK_PDM_CLK                                  =  IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20                               =  IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
-	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_UART1_TX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXFS_UART1_RX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
-	IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21                               =  IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
-	IMX8MM_PAD_SAI2_RXC_UART1_RX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
-	IMX8MM_PAD_SAI2_RXC_UART1_TX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXC_GPIO4_IO22                                =  IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
-	IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23                               =  IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC                             =  IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
-	IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24                               =  IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK                              =  IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2                             =  IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXC_GPIO4_IO25                                =  IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0                            =  IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3                            =  IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26                               =  IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
-	IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27                               =  IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1                            =  IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
-	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1                            =  IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28                               =  IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXC_GPT1_CLK                                  =  IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
-	IMX8MM_PAD_SAI3_RXC_UART2_CTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXC_UART2_RTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
-	IMX8MM_PAD_SAI3_RXC_GPIO4_IO29                                =  IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1                             =  IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
-	IMX8MM_PAD_SAI3_RXD_UART2_RTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
-	IMX8MM_PAD_SAI3_RXD_UART2_CTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_RXD_GPIO4_IO30                                =  IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC                             =  IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2                            =  IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
-	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_UART2_RX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
-	IMX8MM_PAD_SAI3_TXFS_UART2_TX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31                               =  IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK                              =  IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2                             =  IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2                             =  IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
-	IMX8MM_PAD_SAI3_TXC_UART2_TX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXC_UART2_RX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
-	IMX8MM_PAD_SAI3_TXC_GPIO5_IO0                                 =  IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0                             =  IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3                             =  IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3                             =  IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
-	IMX8MM_PAD_SAI3_TXD_GPIO5_IO1                                 =  IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_MCLK_PWM4_OUT                                 =  IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
-	IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2                                =  IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT                                =  IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_TX_PWM3_OUT                                  =  IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_TX_GPIO5_IO3                                 =  IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SPDIF_RX_SPDIF1_IN                                 =  IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_RX_PWM2_OUT                                  =  IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_RX_GPIO5_IO4                                 =  IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                       =  IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT                             =  IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5                            =  IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK                            =  IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SCLK_UART3_RX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
-	IMX8MM_PAD_ECSPI1_SCLK_UART3_TX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6                              =  IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI                            =  IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MOSI_UART3_TX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MOSI_UART3_RX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
-	IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7                              =  IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO                            =  IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
-	IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8                              =  IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0                              =  IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
-	IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9                               =  IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK                            =  IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SCLK_UART4_RX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
-	IMX8MM_PAD_ECSPI2_SCLK_UART4_TX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10                             =  IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI                            =  IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MOSI_UART4_TX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MOSI_UART4_RX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
-	IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11                             =  IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO                            =  IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
-	IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12                             =  IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0                              =  IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
-	IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13                              =  IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C1_SCL_I2C1_SCL                                  =  IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C1_SCL_ENET1_MDC                                 =  IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C1_SCL_GPIO5_IO14                                =  IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C1_SDA_I2C1_SDA                                  =  IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C1_SDA_ENET1_MDIO                                =  IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
-	IMX8MM_PAD_I2C1_SDA_GPIO5_IO15                                =  IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C2_SCL_I2C2_SCL                                  =  IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN                      =  IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B                               =  IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0),
-	IMX8MM_PAD_I2C2_SCL_GPIO5_IO16                                =  IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C2_SDA_I2C2_SDA                                  =  IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT                     =  IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C2_SDA_USDHC3_WP                                 =  IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0),
-	IMX8MM_PAD_I2C2_SDA_GPIO5_IO17                                =  IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C3_SCL_I2C3_SCL                                  =  IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SCL_PWM4_OUT                                  =  IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SCL_GPT2_CLK                                  =  IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SCL_GPIO5_IO18                                =  IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C3_SDA_I2C3_SDA                                  =  IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SDA_PWM3_OUT                                  =  IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SDA_GPT3_CLK                                  =  IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C3_SDA_GPIO5_IO19                                =  IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C4_SCL_I2C4_SCL                                  =  IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SCL_PWM2_OUT                                  =  IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B                            =  IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
-	IMX8MM_PAD_I2C4_SCL_GPIO5_IO20                                =  IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_I2C4_SDA_I2C4_SDA                                  =  IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SDA_PWM1_OUT                                  =  IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_I2C4_SDA_GPIO5_IO21                                =  IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART1_RXD_UART1_RX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
-	IMX8MM_PAD_UART1_RXD_UART1_TX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK                              =  IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_RXD_GPIO5_IO22                               =  IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART1_TXD_UART1_TX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_TXD_UART1_RX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
-	IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI                              =  IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART1_TXD_GPIO5_IO23                               =  IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART2_RXD_UART2_RX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
-	IMX8MM_PAD_UART2_RXD_UART2_TX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_RXD_ECSPI3_MISO                              =  IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_RXD_GPIO5_IO24                               =  IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART2_TXD_UART2_TX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_TXD_UART2_RX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
-	IMX8MM_PAD_UART2_TXD_ECSPI3_SS0                               =  IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART2_TXD_GPIO5_IO25                               =  IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART3_RXD_UART3_RX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
-	IMX8MM_PAD_UART3_RXD_UART3_TX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_RXD_UART1_CTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_RXD_UART1_RTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
-	IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B                           =  IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_RXD_GPIO5_IO26                               =  IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART3_TXD_UART3_TX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_TXD_UART3_RX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
-	IMX8MM_PAD_UART3_TXD_UART1_RTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
-	IMX8MM_PAD_UART3_TXD_UART1_CTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT                           =  IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
-	IMX8MM_PAD_UART3_TXD_GPIO5_IO27                               =  IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART4_RXD_UART4_RX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
-	IMX8MM_PAD_UART4_RXD_UART4_TX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_RXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_RXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
-	IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B                           =  IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
-	IMX8MM_PAD_UART4_RXD_GPIO5_IO28                               =  IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
-
-	IMX8MM_PAD_UART4_TXD_UART4_TX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_TXD_UART4_RX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
-	IMX8MM_PAD_UART4_TXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
-	IMX8MM_PAD_UART4_TXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
-	IMX8MM_PAD_UART4_TXD_GPIO5_IO29                               =  IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
-};
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
deleted file mode 100644
index c71913f..0000000
--- a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
+++ /dev/null
@@ -1,622 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 NXP
- */
-
-#ifndef __ASM_ARCH_IMX8MQ_PINS_H__
-#define __ASM_ARCH_IMX8MQ_PINS_H__
-
-#include <asm/mach-imx/iomux-v3.h>
-
-enum {
-		IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0                    = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT    = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K          = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1                 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL                    = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1                    = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT                     = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M          = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2                 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE                  = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2                    = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B                 = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY               = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B                    = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3                    = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT               = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0             = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK              = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE                    = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4                    = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT               = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1             = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V           = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5                    = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI         = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY               = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT                 = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6                    = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO06__ENET_MDC                     = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B                  = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3                 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7                    = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO                    = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP                    = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4                 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8                    = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN          = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B               = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT                     = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9                    = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT         = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0             = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO09__CCM_STOP                     = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10                   = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID                  = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11                   = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID                  = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY               = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
-
-		IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12                   = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR                 = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1             = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0           = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13                   = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC                  = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT                     = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1           = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14                   = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR                 = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT                     = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1                    = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2           = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15                   = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC                  = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT                     = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2                    = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
-		IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB              = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_MDC__ENET_MDC                       = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_MDC__GPIO1_IO16                     = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_MDIO__ENET_MDIO                     = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
-		IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17                    = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3                 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TD3__GPIO1_IO18                     = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2                 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK                    = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TD2__GPIO1_IO19                     = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1                 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TD1__GPIO1_IO20                     = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0                 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TD0__GPIO1_IO21                     = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL           = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22                  = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC                 = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TXC__ENET_TX_ER                     = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_TXC__GPIO1_IO23                     = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL           = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24                  = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC                 = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_RXC__ENET_RX_ER                     = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_RXC__GPIO1_IO25                     = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0                 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_RD0__GPIO1_IO26                     = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1                 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_RD1__GPIO1_IO27                     = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2                 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_RD2__GPIO1_IO28                     = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3                 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ENET_RD3__GPIO1_IO29                     = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_CLK__USDHC1_CLK                      = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_CLK__GPIO2_IO0                       = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_CMD__USDHC1_CMD                      = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_CMD__GPIO2_IO1                       = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0                  = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2                     = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1                  = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3                     = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2                  = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4                     = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3                  = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5                     = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4                  = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6                     = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5                  = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7                     = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6                  = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8                     = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7                  = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9                     = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B              = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10                  = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE                = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11                   = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B                    = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12                     = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_CLK__USDHC2_CLK                      = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_CLK__GPIO2_IO13                      = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_CMD__USDHC2_CMD                      = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_CMD__GPIO2_IO14                      = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0                  = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15                    = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1                  = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16                    = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_DATA1__CCM_WAIT                      = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2                  = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17                    = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_DATA2__CCM_STOP                      = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3                  = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18                    = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET               = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B              = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19                  = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET            = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SD2_WP__USDHC2_WP                        = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SD2_WP__GPIO2_IO20                       = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE                    = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK                    = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_ALE__GPIO3_IO0                      = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B                = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B                 = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1                    = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B                = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B                 = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2                    = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B                = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B                 = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3                    = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B                = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B                 = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4                    = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE                    = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK                    = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_CLE__GPIO3_IO5                      = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00              = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0                = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6                   = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01              = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1                = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7                   = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02              = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2                = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8                   = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03              = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3                = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9                   = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04              = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0                = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10                  = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05              = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1                = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11                  = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06              = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2                = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12                  = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07              = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3                = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13                  = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS                    = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS                     = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_DQS__GPIO3_IO14                     = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B                  = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS                    = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15                    = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B            = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16                 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B                  = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17                    = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B                  = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18                    = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
-		IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0                 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19                    = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
-		IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1                  = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20                     = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2                 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21                    = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3                 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22                    = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4                 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
-		IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK                  = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23                    = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5                 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC                  = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
-		IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0                 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24                    = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
-		IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
-		IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25                    = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK                = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
-		IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
-		IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK        = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0                     = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
-		IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL         = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1                      = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
-		IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0           = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2                     = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0                 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
-		IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1           = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3                     = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1                 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
-		IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2           = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4                     = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2                 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
-		IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3           = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5                     = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3                 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4                 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4           = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6                     = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4                 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5                 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC                  = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
-		IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5           = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7                     = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5                 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6                 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6           = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8                     = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6                 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7                 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK                     = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC                  = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
-		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4                 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7           = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9                     = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7                 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
-		IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
-		IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO           = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10                    = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
-		IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
-		IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI            = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11                     = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8           = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12                    = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8                 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9           = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13                    = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9                 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10          = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14                    = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10                = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11          = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15                    = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11                = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4                 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
-		IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
-		IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12          = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16                    = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12                = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5                 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
-		IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13          = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17                    = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13                = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6                 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
-		IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
-		IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14          = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18                    = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14                = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7                 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK                     = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
-		IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15          = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19                    = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15                = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
-		IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
-		IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20                    = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
-		IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21                    = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
-		IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22                     = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23                    = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC                  = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1                 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24                    = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK                   = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2                  = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25                     = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0                 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3                 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26                    = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
-		IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27                    = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1                 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
-		IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28                    = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2                  = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
-		IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29                     = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1                  = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
-		IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30                     = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC                  = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK                      = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1                 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
-		IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31                    = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK                   = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2                  = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2                  = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
-		IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0                      = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0                  = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3                  = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3                  = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
-		IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1                      = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT                      = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
-		IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2                     = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT                     = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SPDIF_TX__PWM3_OUT                       = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3                      = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN                      = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SPDIF_RX__PWM2_OUT                       = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4                      = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK            = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT                  = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5                 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK                 = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX                    = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
-		IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6                   = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI                 = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX                    = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
-		IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7                   = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO                 = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B                 = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
-		IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8                   = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0                   = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B                  = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
-		IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9                    = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK                 = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX                    = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
-		IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10                  = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI                 = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX                    = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
-		IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11                  = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO                 = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B                 = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
-		IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12                  = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0                   = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B                  = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
-		IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13                   = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C1_SCL__I2C1_SCL                       = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C1_SCL__ENET_MDC                       = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14                     = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C1_SDA__I2C1_SDA                       = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C1_SDA__ENET_MDIO                      = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
-		IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15                     = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C2_SCL__I2C2_SCL                       = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN            = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16                     = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C2_SDA__I2C2_SDA                       = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT           = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17                     = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C3_SCL__I2C3_SCL                       = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C3_SCL__PWM4_OUT                       = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C3_SCL__GPT2_CLK                       = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18                     = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C3_SDA__I2C3_SDA                       = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C3_SDA__PWM3_OUT                       = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C3_SDA__GPT3_CLK                       = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19                     = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C4_SCL__I2C4_SCL                       = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C4_SCL__PWM2_OUT                       = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B                 = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
-		IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20                     = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_I2C4_SDA__I2C4_SDA                       = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C4_SDA__PWM1_OUT                       = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B                 = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
-		IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21                     = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART1_RXD__UART1_RX                      = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
-		IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK                   = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART1_RXD__GPIO5_IO22                    = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART1_TXD__UART1_TX                      = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI                   = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART1_TXD__GPIO5_IO23                    = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART2_RXD__UART2_RX                      = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
-		IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO                   = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART2_RXD__GPIO5_IO24                    = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART2_TXD__UART2_TX                      = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0                    = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART2_TXD__GPIO5_IO25                    = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART3_RXD__UART3_RX                      = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
-		IMX8MQ_PAD_UART3_RXD__UART1_CTS_B                   = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
-		IMX8MQ_PAD_UART3_RXD__GPIO5_IO26                    = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART3_TXD__UART3_TX                      = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART3_TXD__UART1_RTS_B                   = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
-		IMX8MQ_PAD_UART3_TXD__GPIO5_IO27                    = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART4_RXD__UART4_RX                      = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
-		IMX8MQ_PAD_UART4_RXD__UART2_CTS_B                   = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
-		IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B                = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
-		IMX8MQ_PAD_UART4_RXD__GPIO5_IO28                    = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
-
-		IMX8MQ_PAD_UART4_TXD__UART4_TX                      = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
-		IMX8MQ_PAD_UART4_TXD__UART2_RTS_B                   = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
-		IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B                = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
-		IMX8MQ_PAD_UART4_TXD__GPIO5_IO29                    = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
-};
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h
deleted file mode 100644
index caf5baf..0000000
--- a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2018 NXP
- */
-
-#ifndef __LPDDR4_DEFINE_H_
-#define __LPDDR4_DEFINE_H_
-
-#define LPDDR4_DVFS_DBI
-#define DDR_ONE_RANK
-/* #define LPDDR4_DBI_ON */
-#define DFI_BUG_WR
-#define M845S_4GBx2
-#define PRETRAIN
-
-/* DRAM MR setting */
-#ifdef LPDDR4_DBI_ON
-#define LPDDR4_MR3			0xf1
-#define LPDDR4_PHY_DMIPinPresent	0x1
-#else
-#define LPDDR4_MR3			0x31
-#define LPDDR4_PHY_DMIPinPresent	0x0
-#endif
-
-#ifdef DDR_ONE_RANK
-#define LPDDR4_CS			0x1
-#else
-#define LPDDR4_CS			0x3
-#endif
-
-/* PHY training feature */
-#define LPDDR4_HDT_CTL_2D		0xC8
-#define LPDDR4_HDT_CTL_3200_1D		0xC8
-#define LPDDR4_HDT_CTL_400_1D		0xC8
-#define LPDDR4_HDT_CTL_100_1D		0xC8
-
-/* 400/100 training seq */
-#define LPDDR4_TRAIN_SEQ_P2		0x121f
-#define LPDDR4_TRAIN_SEQ_P1		0x121f
-#define LPDDR4_TRAIN_SEQ_P0		0x121f
-#define LPDDR4_TRAIN_SEQ_100		0x121f
-#define LPDDR4_TRAIN_SEQ_400		0x121f
-
-/* 2D share & weight */
-#define LPDDR4_2D_WEIGHT		0x1f7f
-#define LPDDR4_2D_SHARE			1
-#define LPDDR4_CATRAIN_3200_1d		0
-#define LPDDR4_CATRAIN_400		0
-#define LPDDR4_CATRAIN_100		0
-#define LPDDR4_CATRAIN_3200_2d		0
-
-/* MRS parameter */
-/* for LPDDR4 Rtt */
-#define LPDDR4_RTT40			6
-#define LPDDR4_RTT48			5
-#define LPDDR4_RTT60			4
-#define LPDDR4_RTT80			3
-#define LPDDR4_RTT120			2
-#define LPDDR4_RTT240			1
-#define LPDDR4_RTT_DIS			0
-
-/* for LPDDR4 Ron */
-#define LPDDR4_RON34			7
-#define LPDDR4_RON40			6
-#define LPDDR4_RON48			5
-#define LPDDR4_RON60			4
-#define LPDDR4_RON80			3
-
-#define LPDDR4_PHY_ADDR_RON60		0x1
-#define LPDDR4_PHY_ADDR_RON40		0x3
-#define LPDDR4_PHY_ADDR_RON30		0x7
-#define LPDDR4_PHY_ADDR_RON24		0xf
-#define LPDDR4_PHY_ADDR_RON20		0x1f
-
-/* for read channel */
-#define LPDDR4_RON			LPDDR4_RON40
-#define LPDDR4_PHY_RTT			30
-#define LPDDR4_PHY_VREF_VALUE		17
-
-/* for write channel */
-#define LPDDR4_PHY_RON			30
-#define LPDDR4_PHY_ADDR_RON		LPDDR4_PHY_ADDR_RON40
-#define LPDDR4_RTT_DQ			LPDDR4_RTT40
-#define LPDDR4_RTT_CA			LPDDR4_RTT40
-#define LPDDR4_RTT_CA_BANK0		LPDDR4_RTT40
-#define LPDDR4_RTT_CA_BANK1		LPDDR4_RTT40
-#define LPDDR4_VREF_VALUE_CA		((1 << 6) | (0xd))
-#define LPDDR4_VREF_VALUE_DQ_RANK0	((1 << 6) | (0xd))
-#define LPDDR4_VREF_VALUE_DQ_RANK1	((1 << 6) | (0xd))
-#define LPDDR4_MR22_RANK0		((0 << 5) | (1 << 4) | (0 << 3) | \
-					(LPDDR4_RTT40))
-#define LPDDR4_MR22_RANK1		((1 << 5) | (1 << 4) | (1 << 3) | \
-					(LPDDR4_RTT40))
-
-#define LPDDR4_MR3_PU_CAL		1
-
-#endif /* __LPDDR4_DEFINE_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h
deleted file mode 100644
index 0f94945..0000000
--- a/arch/arm/include/asm/arch-imx8m/power-domain.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2017 NXP
- */
-
-#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
-#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
-
-struct imx8m_power_domain_platdata {
-	int resource_id;
-	int has_pd;
-	struct power_domain pd;
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
deleted file mode 100644
index d328542..0000000
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 NXP
- */
-
-#ifndef __ARCH_IMX8M_SYS_PROTO_H
-#define __ARCH_NMX8M_SYS_PROTO_H
-
-#include <asm/mach-imx/sys_proto.h>
-
-void set_wdog_reset(struct wdog_regs *wdog);
-void enable_tzc380(void);
-void restore_boot_params(void);
-extern unsigned long rom_pointer[];
-enum boot_device get_boot_device(void);
-bool is_usb_boot(void);
-#endif