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author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:21:52 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:48:38 +0800 |
commit | ae51f41d14f548d494ac41e0d21137c5a4c3f59c (patch) | |
tree | 6ddb9d1aaa7bd5bad5bbf8497edc2e08ff208d79 /arch/arm/include/asm/arch-lpc32xx/wdt.h | |
download | uext4-ae51f41d14f548d494ac41e0d21137c5a4c3f59c.tar.xz |
import the U-Boot code and make it compile
Diffstat (limited to 'arch/arm/include/asm/arch-lpc32xx/wdt.h')
-rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/wdt.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h new file mode 100644 index 0000000..dd0fc16 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/wdt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> + */ + +#ifndef _LPC32XX_WDT_H +#define _LPC32XX_WDT_H + +#include <asm/types.h> + +/* Watchdog Timer Registers */ +struct wdt_regs { + u32 isr; /* Interrupt Status Register */ + u32 ctrl; /* Control Register */ + u32 counter; /* Counter Value Register */ + u32 mctrl; /* Match Control Register */ + u32 match0; /* Match 0 Register */ + u32 emr; /* External Match Control Register */ + u32 pulse; /* Reset Pulse Length Register */ + u32 res; /* Reset Source Register */ +}; + +/* Watchdog Timer Control Register bits */ +#define WDTIM_CTRL_PAUSE_EN (1 << 2) +#define WDTIM_CTRL_RESET_COUNT (1 << 1) +#define WDTIM_CTRL_COUNT_ENAB (1 << 0) + +/* Watchdog Timer Match Control Register bits */ +#define WDTIM_MCTRL_RESFRC2 (1 << 6) +#define WDTIM_MCTRL_RESFRC1 (1 << 5) +#define WDTIM_MCTRL_M_RES2 (1 << 4) +#define WDTIM_MCTRL_M_RES1 (1 << 3) +#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) +#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) +#define WDTIM_MCTRL_MR0_INT (1 << 0) + +#endif /* _LPC32XX_WDT_H */ |