diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:43:26 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 15:43:26 +0800 |
| commit | a899a6c0ed9a3066557fb170850f977b6bd7366f (patch) | |
| tree | 78f7b1166fc1bd0265bcb61990130479528b09c4 /arch/arm/include/asm/arch-mx7ulp | |
| parent | 1a691f101632955a994a0198fc5498b108e97fbc (diff) | |
| download | uext4-a899a6c0ed9a3066557fb170850f977b6bd7366f.tar.xz | |
rm arch/arm/include/asm/arch-*
Diffstat (limited to 'arch/arm/include/asm/arch-mx7ulp')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/clock.h | 42 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/gpio.h | 21 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1141 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/iomux.h | 94 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h | 909 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S | 93 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/pcc.h | 372 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 21 |
8 files changed, 0 insertions, 2693 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h deleted file mode 100644 index eb02a20..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _ASM_ARCH_CLOCK_H -#define _ASM_ARCH_CLOCK_H - -#include <common.h> -#include <asm/arch/pcc.h> -#include <asm/arch/scg.h> - -/* Mainly for compatible to imx common code. */ -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_AXI_CLK, - MXC_DDR_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_I2C_CLK, -}; - -u32 mxc_get_clock(enum mxc_clock clk); -u32 get_lpuart_clk(void); -#ifdef CONFIG_SYS_I2C_IMX_LPI2C -int enable_i2c_clk(unsigned char enable, unsigned i2c_num); -u32 imx_get_i2cclk(unsigned i2c_num); -#endif -#ifdef CONFIG_MXC_OCOTP -void enable_ocotp_clk(unsigned char enable); -#endif -#ifdef CONFIG_USB_EHCI_HCD -void enable_usboh3_clk(unsigned char enable); -#endif -void init_clk_usdhc(u32 index); -void clock_init(void); -void hab_caam_clock_enable(unsigned char enable); -#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/gpio.h b/arch/arm/include/asm/arch-mx7ulp/gpio.h deleted file mode 100644 index 7c62560..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_MX7ULP_GPIO_H -#define __ASM_ARCH_MX7ULP_GPIO_H - -struct gpio_regs { - u32 gpio_pdor; - u32 gpio_psor; - u32 gpio_pcor; - u32 gpio_ptor; - u32 gpio_pdir; - u32 gpio_pddr; - u32 gpio_gacr; -}; - -#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31)) - -#endif /* __ASM_ARCH_MX7ULP_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h deleted file mode 100644 index 3c82e99..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ /dev/null @@ -1,1141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _MX7ULP_REGS_H_ -#define _MX7ULP_REGS_H_ - -#include <linux/sizes.h> - -#define ARCH_MXC - -#define ROM_SW_INFO_ADDR 0x000001E8 - -#define CAAM_SEC_SRAM_BASE (0x26000000) -#define CAAM_SEC_SRAM_SIZE (SZ_32K) -#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) - -#define OCRAM_0_BASE (0x2F000000) -#define OCRAM_0_SIZE (SZ_128K) -#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) - -#define OCRAM_1_BASE (0x2F020000) -#define OCRAM_1_SIZE (SZ_128K) -#define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) - -#define TCML_BASE (0x1FFD0000) -#define TCMU_BASE (0x20000000) - -#define AIPS3_BASE (0x40800000UL) -#define AIPS3_SLOT_SIZE (SZ_64K) -#define AIPS2_BASE (0x40000000UL) -#define AIPS2_SLOT_SIZE (SZ_64K) -#define AIPS1_BASE (0x41080000UL) -#define AIPS1_SLOT_SIZE (SZ_4K) -#define AIPS0_BASE (0x41000000UL) -#define AIPS0_SLOT_SIZE (SZ_4K) -#define IOMUXC0_AIPS0_SLOT (61) -#define WDG0_AIPS0_SLOT (37) -#define WDG1_AIPS2_SLOT (61) -#define WDG2_AIPS2_SLOT (67) -#define WDG0_PCC0_SLOT (37) -#define IOMUXC1_AIPS3_SLOT (44) -#define CMC0_AIPS1_SLOT (36) -#define CMC1_AIPS2_SLOT (65) -#define SCG0_AIPS0_SLOT (39) -#define PCC0_AIPS0_SLOT (38) -#define PCC1_AIPS1_SLOT (50) -#define PCC2_AIPS2_SLOT (63) -#define PCC3_AIPS3_SLOT (51) -#define SCG1_AIPS2_SLOT (62) -#define SIM0_AIPS1_SLOT (35) -#define SIM1_AIPS1_SLOT (48) -#define USBOTG0_AIPS2_SLOT (51) -#define USBOTG1_AIPS2_SLOT (52) -#define USBPHY_AIPS2_SLOT (53) -#define USDHC0_AIPS2_SLOT (55) -#define USDHC1_AIPS2_SLOT (56) -#define RGPIO2P0_AIPS0_SLOT (15) -#define RGPIO2P1_AIPS2_SLOT (15) -#define SNVS_AIPS2_SLOT (35) -#define IOMUXC0_AIPS0_SLOT (61) -#define OCOTP_CTRL_AIPS1_SLOT (38) -#define OCOTP_CTRL_PCC1_SLOT (38) -#define SIM1_PCC1_SLOT (48) -#define MMDC0_AIPS3_SLOT (43) -#define IOMUXC_DDR_AIPS3_SLOT (45) - -#define LPI2C0_AIPS0_SLOT (51) -#define LPI2C1_AIPS0_SLOT (52) -#define LPI2C2_AIPS0_SLOT (53) -#define LPI2C3_AIPS0_SLOT (54) -#define LPI2C4_AIPS2_SLOT (43) -#define LPI2C5_AIPS2_SLOT (44) -#define LPI2C6_AIPS3_SLOT (36) -#define LPI2C7_AIPS3_SLOT (37) - -#define LPUART0_PCC0_SLOT (58) -#define LPUART1_PCC0_SLOT (59) -#define LPUART2_PCC1_SLOT (43) -#define LPUART3_PCC1_SLOT (44) -#define LPUART0_AIPS0_SLOT (58) -#define LPUART1_AIPS0_SLOT (59) -#define LPUART2_AIPS1_SLOT (43) -#define LPUART3_AIPS1_SLOT (44) -#define LPUART4_AIPS2_SLOT (45) -#define LPUART5_AIPS2_SLOT (46) -#define LPUART6_AIPS3_SLOT (38) -#define LPUART7_AIPS3_SLOT (39) - -#define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) -#define CORE_B_ROM_BASE (0x00000000) - -#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE -#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE -#define IRAM_BASE_ADDR OCRAM_0_BASE -#define IRAM_SIZE (SZ_128K + SZ_128K) - -#define IOMUXC_PCR_MUX_ALT0 (0<<8) -#define IOMUXC_PCR_MUX_ALT1 (1<<8) -#define IOMUXC_PCR_MUX_ALT2 (2<<8) -#define IOMUXC_PCR_MUX_ALT3 (3<<8) -#define IOMUXC_PCR_MUX_ALT4 (4<<8) -#define IOMUXC_PCR_MUX_ALT5 (5<<8) -#define IOMUXC_PCR_MUX_ALT6 (6<<8) -#define IOMUXC_PCR_MUX_ALT7 (7<<8) -#define IOMUXC_PCR_MUX_ALT8 (8<<8) -#define IOMUXC_PCR_MUX_ALT9 (9<<8) -#define IOMUXC_PCR_MUX_ALT10 (10<<8) -#define IOMUXC_PCR_MUX_ALT11 (11<<8) -#define IOMUXC_PCR_MUX_ALT12 (12<<8) -#define IOMUXC_PCR_MUX_ALT13 (13<<8) -#define IOMUXC_PCR_MUX_ALT14 (14<<8) -#define IOMUXC_PCR_MUX_ALT15 (15<<8) - -#define IOMUXC_PSMI_IMUX_ALT0 (0x0) -#define IOMUXC_PSMI_IMUX_ALT1 (0x1) -#define IOMUXC_PSMI_IMUX_ALT2 (0x2) -#define IOMUXC_PSMI_IMUX_ALT3 (0x3) -#define IOMUXC_PSMI_IMUX_ALT4 (0x4) -#define IOMUXC_PSMI_IMUX_ALT5 (0x5) -#define IOMUXC_PSMI_IMUX_ALT6 (0x6) -#define IOMUXC_PSMI_IMUX_ALT7 (0x7) - - -#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) -#define SIM_SOPT1_PMIC_STBY_REQ (1<<2) -#define SIM_SOPT1_A7_SW_RESET (1<<0) - -#define IOMUXC_PCR_MUX_ALT_SHIFT (8) -#define IOMUXC_PCR_MUX_ALT_MASK (0xF00) -#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) - -#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) -#define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) -#define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) -#define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) -#define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) -#define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) -#define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) -#define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) -#define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) -#define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) -#define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) -#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) -#define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ -#define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) -#define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) -#define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) -#define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) -#define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) -#define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) - -#define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) -#define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) -#define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) -#define USB_PHY0_BASE_ADDR USBPHY_RBASE -#define USB_BASE_ADDR USBOTG0_RBASE - -#define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) -#define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) -#define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) -#define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) -#define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) -#define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) -#define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) -#define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) - -#define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) -#define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) -#define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) -#define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) -#define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) -#define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) -#define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) -#define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) - -#define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) -#define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) - -#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) -#define SNVS_LP_LPCR (SNVS_BASE + 0x38) - -#define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) -#define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) - -#define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) -#define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) -#define CMC0_SRS (CMC0_RBASE + 0x20) -#define CMC0_SSRS (CMC0_RBASE + 0x28) -#define CMC1_SRS (CMC1_RBASE + 0x20) -#define CMC1_SSRS (CMC1_RBASE + 0x28) - -#define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) -#define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) -#define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) -#define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) -#define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) -#define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) -#define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) - -#define SCG_CSR (SCG0_RBASE + 0x010) -#define SCG_RCCR (SCG0_RBASE + 0x014) -#define SCG_VCCR (SCG0_RBASE + 0x018) -#define SCG_HCCR (SCG0_RBASE + 0x01c) - -#define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) -#define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) -#define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) -#define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) -#define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) -#define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) -#define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) -#define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) - -#define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) -#define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) - -#define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) -#define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) - -#define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) - -#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) -#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) - -#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) -#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) -#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) -#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) - - -#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) -#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) -#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) -#define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) -#define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) -#define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) -#define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) -#define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) -#define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) -#define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) -#define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) -#define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) -#define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) -#define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) -#define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) -#define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) -#define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) -#define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) -#define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) -#define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) -#define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) -#define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) -#define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) -#define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) -#define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) -#define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) -#define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) -#define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) -#define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) -#define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) -#define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) -#define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) - -/* Remap the rgpio2p registers addr to driver's addr */ -#define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE -#define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) -#define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) -#define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) -#define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) -#define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) - -/* MMDC registers addresses */ -#define MMDC_MDCTL_OFFSET (0x000) -#define MMDC_MDPDC_OFFSET (0x004) -#define MMDC_MDOTC_OFFSET (0x008) -#define MMDC_MDCFG0_OFFSET (0x00C) -#define MMDC_MDCFG1_OFFSET (0x010) -#define MMDC_MDCFG2_OFFSET (0x014) -#define MMDC_MDMISC_OFFSET (0x018) -#define MMDC_MDSCR_OFFSET (0x01C) -#define MMDC_MDREF_OFFSET (0x020) -#define MMDC_MDRWD_OFFSET (0x02C) -#define MMDC_MDOR_OFFSET (0x030) -#define MMDC_MDMRR_OFFSET (0x034) -#define MMDC_MDCFG3LP_OFFSET (0x038) -#define MMDC_MDMR4_OFFSET (0x03C) -#define MMDC_MDASP_OFFSET (0x040) - -#define MMDC_MAARCR_OFFSET (0x400) -#define MMDC_MAPSR_OFFSET (0x404) -#define MMDC_MAEXIDR0_OFFSET (0x408) -#define MMDC_MAEXIDR1_OFFSET (0x40C) -#define MMDC_MADPCR0_OFFSET (0x410) -#define MMDC_MADPCR1_OFFSET (0x414) -#define MMDC_MADPSR0_OFFSET (0x418) -#define MMDC_MADPSR1_OFFSET (0x41C) -#define MMDC_MADPSR2_OFFSET (0x420) -#define MMDC_MADPSR3_OFFSET (0x424) -#define MMDC_MADPSR4_OFFSET (0x428) -#define MMDC_MADPSR5_OFFSET (0x42C) -#define MMDC_MASBS0_OFFSET (0x430) -#define MMDC_MASBS1_OFFSET (0x434) -#define MMDC_MAGENP_OFFSET (0x440) - -#define MMDC_MPZQHWCTRL_OFFSET (0x800) -#define MMDC_MPZQSWCTRL_OFFSET (0x804) -#define MMDC_MPWLGCR_OFFSET (0x808) -#define MMDC_MPWLDECTRL0_OFFSET (0x80C) -#define MMDC_MPWLDECTRL1_OFFSET (0x810) -#define MMDC_MPWLDLST_OFFSET (0x814) -#define MMDC_MPODTCTRL_OFFSET (0x818) -#define MMDC_MPREDQBY0DL_OFFSET (0x81C) -#define MMDC_MPREDQBY1DL_OFFSET (0x820) -#define MMDC_MPREDQBY2DL_OFFSET (0x824) -#define MMDC_MPREDQBY3DL_OFFSET (0x828) -#define MMDC_MPWRDQBY0DL_OFFSET (0x82C) -#define MMDC_MPWRDQBY1DL_OFFSET (0x830) -#define MMDC_MPWRDQBY2DL_OFFSET (0x834) -#define MMDC_MPWRDQBY3DL_OFFSET (0x838) -#define MMDC_MPDGCTRL0_OFFSET (0x83C) -#define MMDC_MPDGCTRL1_OFFSET (0x840) -#define MMDC_MPDGDLST_OFFSET (0x844) -#define MMDC_MPRDDLCTL_OFFSET (0x848) -#define MMDC_MPRDDLST_OFFSET (0x84C) -#define MMDC_MPWRDLCTL_OFFSET (0x850) -#define MMDC_MPWRDLST_OFFSET (0x854) -#define MMDC_MPSDCTRL_OFFSET (0x858) -#define MMDC_MPZQLP2CTL_OFFSET (0x85C) -#define MMDC_MPRDDLHWCTL_OFFSET (0x860) -#define MMDC_MPWRDLHWCTL_OFFSET (0x864) -#define MMDC_MPRDDLHWST0_OFFSET (0x868) -#define MMDC_MPRDDLHWST1_OFFSET (0x86C) -#define MMDC_MPWRDLHWST0_OFFSET (0x870) -#define MMDC_MPWRDLHWST1_OFFSET (0x874) -#define MMDC_MPWLHWERR_OFFSET (0x878) -#define MMDC_MPDGHWST0_OFFSET (0x87C) -#define MMDC_MPDGHWST1_OFFSET (0x880) -#define MMDC_MPDGHWST2_OFFSET (0x884) -#define MMDC_MPDGHWST3_OFFSET (0x888) -#define MMDC_MPPDCMPR1_OFFSET (0x88C) -#define MMDC_MPPDCMPR2_OFFSET (0x890) -#define MMDC_MPSWDAR_OFFSET (0x894) -#define MMDC_MPSWDRDR0_OFFSET (0x898) -#define MMDC_MPSWDRDR1_OFFSET (0x89C) -#define MMDC_MPSWDRDR2_OFFSET (0x8A0) -#define MMDC_MPSWDRDR3_OFFSET (0x8A4) -#define MMDC_MPSWDRDR4_OFFSET (0x8A8) -#define MMDC_MPSWDRDR5_OFFSET (0x8AC) -#define MMDC_MPSWDRDR6_OFFSET (0x8B0) -#define MMDC_MPSWDRDR7_OFFSET (0x8B4) -#define MMDC_MPMUR_OFFSET (0x8B8) -#define MMDC_MPWRCADL_OFFSET (0x8BC) -#define MMDC_MPDCCR_OFFSET (0x8C0) -#define MMDC_MPBC_OFFSET (0x8C4) -#define MMDC_MPSWDRAR_OFFSET (0x8C8) - -/* First MMDC invalid IPS address */ -#define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) -#define MMDC_REGS_BASE MMDC0_RBASE - -#define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) -#define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) -#define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) -#define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) -#define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) -#define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) -#define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) -#define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) -#define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) -#define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) -#define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) -#define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) -#define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) -#define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) -#define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) - -#define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) -#define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) -#define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) -#define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) -#define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) -#define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) -#define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) -#define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) -#define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) -#define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) -#define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) -#define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) -#define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) -#define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) -#define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) - -#define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) -#define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) -#define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) -#define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) -#define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) -#define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) -#define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) -#define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) -#define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) -#define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) -#define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) -#define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) -#define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) -#define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) -#define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) -#define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) -#define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) -#define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) -#define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) -#define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) -#define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) -#define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) -#define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) -#define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) -#define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) -#define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) -#define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) -#define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) -#define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) -#define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) -#define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) -#define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) -#define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) -#define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) -#define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) -#define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) -#define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) -#define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) -#define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) -#define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) -#define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) -#define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) -#define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) -#define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) -#define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) -#define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) -#define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) -#define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) -#define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) -#define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) -#define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) - -/* MMDC registers bit defines */ -#define MMDC_MDCTL_SDE_0 (31) -#define MMDC_MDCTL_SDE_1 (30) -#define MMDC_MDCTL_ROW (24) -#define MMDC_MDCTL_COL (20) -#define MMDC_MDCTL_BL (19) -#define MMDC_MDCTL_DSIZ (16) - -/* MDMISC */ -#define MMDC_MDMISC_CS0_RDY (31) -#define MMDC_MDMISC_CS1_RDY (30) -#define MMDC_MDMISC_CK1_DEL (22) -#define MMDC_MDMISC_CK1_GATING (21) -#define MMDC_MDMISC_CALIB_PER_CS (20) -#define MMDC_MDMISC_ADDR_MIRROR (19) -#define MMDC_MDMISC_LHD (18) -#define MMDC_MDMISC_WALAT (16) -#define MMDC_MDMISC_BI (12) -#define MMDC_MDMISC_LPDDR2_S (11) -#define MMDC_MDMISC_MIF3_MODE (9) -#define MMDC_MDMISC_RALAT (6) -#define MMDC_MDMISC_DDR_4_BANK (5) -#define MMDC_MDMISC_DDR_TYPE (3) -#define MMDC_MDMISC_RST (1) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_WL_HW_ERR (8) - -/* MDSCR */ -#define MMDC_MDSCR_CMD_ADDR_MSB (24) -#define MMDC_MDSCR_MR_OP (24) -#define MMDC_MDSCR_CMD_ADDR_LSB (16) -#define MMDC_MDSCR_MR_ADDR (16) -#define MMDC_MDSCR_CON_REQ (15) -#define MMDC_MDSCR_CON_ACK (14) -#define MMDC_MDSCR_MRR_READ_DATA_VALID (10) -#define MMDC_MDSCR_WL_EN (9) -#define MMDC_MDSCR_CMD (4) -#define MMDC_MDSCR_CMD_CS (3) -#define MMDC_MDSCR_CMD_BA (0) - -/* MPZQHWCTRL */ -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) -#define MMDC_MPZQHWCTRL_ZQ_MODE (0) - -/* MPZQSWCTRL */ -#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) -#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) -#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) -#define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) -#define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) - -/* MPDGCTRL0 */ -#define MMDC_MPDGCTRL0_RST_RD_FIFO (31) -#define MMDC_MPDGCTRL0_DG_CMP_CYC (30) -#define MMDC_MPDGCTRL0_DG_DIS (29) -#define MMDC_MPDGCTRL0_HW_DG_EN (28) -#define MMDC_MPDGCTRL0_HW_DG_ERR (12) - -/* MPRDDLHWCTL */ -#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) - -/* MPWRDLHWCTL */ -#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) - -/* MPSWDAR */ -#define MMDC_MPSWDAR_TEST_DUMMY_EN (6) -#define MMDC_MPSWDAR_SW_DUM_CMP3 (5) -#define MMDC_MPSWDAR_SW_DUM_CMP2 (4) -#define MMDC_MPSWDAR_SW_DUM_CMP1 (3) -#define MMDC_MPSWDAR_SW_DUM_CMP0 (2) -#define MMDC_MPSWDAR_SW_DUMMY_RD (1) -#define MMDC_MPSWDAR_SW_DUMMY_WR (0) - -/* MADPCR0 */ -#define MMDC_MADPCR0_SBS (9) -#define MMDC_MADPCR0_SBS_EN (8) - -/* MASBS1 */ -#define MMDC_MASBS1_SBS_VLD (0) -#define MMDC_MASBS1_SBS_TYPE (1) - -/* MDREF */ -#define MMDC_MDREF_REF_CNT (16) -#define MMDC_MDREF_REF_SEL (14) -#define MMDC_MDREF_REFR (11) -#define MMDC_MDREF_START_REF (0) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_HW_WL_EN (0) - -/* MPBC */ -#define MMDC_MPBC_BIST_DM_LP_EN (0) -#define MMDC_MPBC_BIST_CA0_LP_EN (1) -#define MMDC_MPBC_BIST_DQ0_LP_EN (3) -#define MMDC_MPBC_BIST_DQ1_LP_EN (4) -#define MMDC_MPBC_BIST_DQ2_LP_EN (5) -#define MMDC_MPBC_BIST_DQ3_LP_EN (6) - -/* MPMUR */ -#define MMDC_MPMUR_FRC_MSR (11) - -/* MPODTCTRL */ -#define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) -#define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) -#define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) -#define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) - -/* MAPSR */ -#define MMDC_MAPSR_DVACK (25) -#define MMDC_MAPSR_LPACK (24) -#define MMDC_MAPSR_DVFS (21) -#define MMDC_MAPSR_LPMD (20) - -/* MAARCR */ -#define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) - -/* MPZQLP2CTL */ -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) - -/* MDCFG3LP */ -#define MMDC_MDCFG3LP_tRC_LP (16) -#define MMDC_MDCFG3LP_tRCD_LP (8) -#define MMDC_MDCFG3LP_tRPpb_LP (4) -#define MMDC_MDCFG3LP_tRPab_LP (0) - -/* MDOR */ -#define MMDC_MDOR_tXPR (16) -#define MMDC_MDOR_SDE_to_RST (8) -#define MMDC_MDOR_RST_to_CKE (0) - -/* MDCFG0 */ -#define MMDC_MDCFG0_tRFC (24) -#define MMDC_MDCFG0_tXS (16) -#define MMDC_MDCFG0_tXP (13) -#define MMDC_MDCFG0_tXPDLL (9) -#define MMDC_MDCFG0_tFAW (4) -#define MMDC_MDCFG0_tCL (0) - -/* MDCFG1 */ -#define MMDC_MDCFG1_tRCD (29) -#define MMDC_MDCFG1_tRP (26) -#define MMDC_MDCFG1_tRC (21) -#define MMDC_MDCFG1_tRAS (16) -#define MMDC_MDCFG1_tRPA (15) -#define MMDC_MDCFG1_tWR (9) -#define MMDC_MDCFG1_tMRD (5) -#define MMDC_MDCFG1_tCWL (0) - -/* MDCFG2 */ -#define MMDC_MDCFG2_tDLLK (16) -#define MMDC_MDCFG2_tRTP (6) -#define MMDC_MDCFG2_tWTR (3) -#define MMDC_MDCFG2_tRRD (0) - -/* MDRWD */ -#define MMDC_MDRWD_tDAI (16) -#define MMDC_MDRWD_RTW_SAME (12) -#define MMDC_MDRWD_WTR_DIFF (9) -#define MMDC_MDRWD_WTW_DIFF (6) -#define MMDC_MDRWD_RTW_DIFF (3) -#define MMDC_MDRWD_RTR_DIFF (0) - -/* MDPDC */ -#define MMDC_MDPDC_PRCT_1 (28) -#define MMDC_MDPDC_PRCT_0 (24) -#define MMDC_MDPDC_tCKE (16) -#define MMDC_MDPDC_PWDT_1 (12) -#define MMDC_MDPDC_PWDT_0 (8) -#define MMDC_MDPDC_SLOW_PD (7) -#define MMDC_MDPDC_BOTH_CS_PD (6) -#define MMDC_MDPDC_tCKSRX (3) -#define MMDC_MDPDC_tCKSRE (0) - -/* MDASP */ -#define MMDC_MDASP_CS0_END (0) - -/* MAEXIDR0 */ -#define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) -#define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) - -/* MAEXIDR1 */ -#define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) -#define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) - -/* MPWRDLCTL */ -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) - -/* MPRDDLCTL */ -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) - -/* MPWRDQBY0DL */ -#define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) -#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) -#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) -#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) -#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) -#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) -#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) -#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) -#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) - -/* MPWRDQBY1DL */ -#define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) -#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) -#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) -#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) -#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) -#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) -#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) -#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) -#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) - -/* MPWRDQBY2DL */ -#define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) -#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) -#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) -#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) -#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) -#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) -#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) -#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) -#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) - -/* MPWRDQBY3DL */ -#define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) -#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) -#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) -#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) -#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) -#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) -#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) -#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) -#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) - -/* Fields masks */ -#define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) -#define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) -#define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) -#define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) -#define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) -#define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) - -/* MDMISC */ -#define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) -#define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) -#define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) -#define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) -#define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) -#define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) -#define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) -#define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) -#define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) -#define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) -#define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) -#define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) -#define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) -#define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) -#define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) - -/* MDSCR */ -#define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) -#define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) -#define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) -#define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) -#define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) -#define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) -#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) -#define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) -#define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) -#define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) -#define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) - -/* MPZQHWCTRL */ -#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) -#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) - -/* MPZQSWCTRL */ -#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) -#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) -#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) -#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) - -/* MPDGCTRL0 */ -#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) -#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) -#define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) -#define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) -#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) - -/* MPRDDLHWCTL */ -#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) -#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) - -/* MPWRDLHWCTL */ -#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) -#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) - -/* MPSWDAR */ -#define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) -#define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) -#define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) -#define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) -#define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) -#define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) -#define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) - -/* MADPCR0 */ -#define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) -#define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) - -/* MASBS1 */ -#define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) -#define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) - -/* MDREF */ -#define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) -#define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) -#define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) -#define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) - -/* MPWLGCR */ -#define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) - -/* MPBC */ -#define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) -#define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) -#define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) -#define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) -#define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) -#define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) -#define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) - -/* MPMUR */ -#define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) - -/* MPODTCTRL */ -#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) -#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) -#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) -#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) - -/* MAPSR */ -#define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) -#define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) -#define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) -#define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) - -/* MAARCR */ -#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) - -/* MPZQLP2CTL */ -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) -#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) - -/* MDCFG3LP */ -#define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) -#define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) -#define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) -#define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) - -/* MDOR */ -#define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) -#define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) -#define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) - -/* MDCFG0 */ -#define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) -#define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) -#define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) -#define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) -#define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) -#define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) - -/* MDCFG1 */ -#define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) -#define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) -#define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) -#define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) -#define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) -#define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) -#define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) -#define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) - -/* MDCFG2 */ -#define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) -#define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) -#define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) -#define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) - -/* MDRWD */ -#define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) -#define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) -#define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) -#define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) -#define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) -#define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) - -/* MDPDC */ -#define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) -#define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) -#define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) -#define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) -#define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) -#define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) -#define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) -#define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) -#define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) - -/* MDASP */ -#define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) - -/* MAEXIDR0 */ -#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) -#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) - -/* MAEXIDR1 */ -#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) -#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) - -/* MPWRDLCTL */ -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) -#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) - -/* MPRDDLCTL */ -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) -#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) - -/* MPWRDQBY0DL */ -#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) -#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) - -/* MPWRDQBY1DL */ -#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) -#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) - -/* MPWRDQBY2DL */ -#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) -#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) - -/* MPWRDQBY3DL */ -#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) -#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) - -#define SNVS_LPCR_DPEN (0x20) -#define SNVS_LPCR_SRTC_ENV (0x1) - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) - -#include <asm/types.h> - -struct fuse_word { - u32 fuse; - u32 rsvd[3]; -}; - -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 pdn; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[3]; - u32 sw_sticky; - u32 rsvd4[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 out_status; - u32 out_status_set; - u32 out_status_clr; - u32 out_status_tog; - u32 startword; - u32 rsvd5[3]; - u32 version; - u32 rsvd6[19]; - struct fuse_word mem_repair[8]; - u32 rsvd7[0xa8]; - - /* fuse banks */ - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[0]; -}; - -struct fuse_bank1_regs { - u32 lock0; - u32 rsvd0[3]; - u32 lock1; - u32 rsvd1[3]; - u32 lock2; - u32 rsvd2[3]; - u32 cfg0; - u32 rsvd3[3]; - u32 cfg1; - u32 rsvd4[3]; - u32 cfg2; - u32 rsvd5[3]; - u32 cfg3; - u32 rsvd6[3]; - u32 cfg4; - u32 rsvd7[3]; -}; - -struct fuse_bank2_regs { - struct fuse_word boot[8]; -}; - -struct fuse_bank3_regs { - u32 mem0; - u32 rsvd0[3]; - u32 mem1; - u32 rsvd1[3]; - u32 mem2; - u32 rsvd2[3]; - u32 mem3; - u32 rsvd3[3]; - u32 ana0; - u32 rsvd4[3]; - u32 ana1; - u32 rsvd5[3]; - u32 ana2; - u32 rsvd6[3]; - u32 ana3; - u32 rsvd7[3]; -}; - -struct fuse_bank7_regs { - u32 sjc_resp0; - u32 rsvd0[3]; - u32 sjc_resp1; - u32 rsvd1[3]; - u32 gp0; - u32 rsvd2[3]; - u32 gp1; - u32 rsvd3[3]; - u32 gp2; - u32 rsvd4[3]; - u32 gp3; - u32 rsvd5[3]; - u32 gp4; - u32 rsvd6[3]; - u32 gp5; - u32 rsvd7[3]; -}; - -struct usbphy_regs { - u32 usbphy_pwd; /* 0x000 */ - u32 usbphy_pwd_set; /* 0x004 */ - u32 usbphy_pwd_clr; /* 0x008 */ - u32 usbphy_pwd_tog; /* 0x00c */ - u32 usbphy_tx; /* 0x010 */ - u32 usbphy_tx_set; /* 0x014 */ - u32 usbphy_tx_clr; /* 0x018 */ - u32 usbphy_tx_tog; /* 0x01c */ - u32 usbphy_rx; /* 0x020 */ - u32 usbphy_rx_set; /* 0x024 */ - u32 usbphy_rx_clr; /* 0x028 */ - u32 usbphy_rx_tog; /* 0x02c */ - u32 usbphy_ctrl; /* 0x030 */ - u32 usbphy_ctrl_set; /* 0x034 */ - u32 usbphy_ctrl_clr; /* 0x038 */ - u32 usbphy_ctrl_tog; /* 0x03c */ - u32 usbphy_status; /* 0x040 */ - u32 reserved0[3]; - u32 usbphy_debug0; /* 0x050 */ - u32 usbphy_debug0_set; /* 0x054 */ - u32 usbphy_debug0_clr; /* 0x058 */ - u32 usbphy_debug0_tog; /* 0x05c */ - u32 reserved1[4]; - u32 usbphy_debug1; /* 0x070 */ - u32 usbphy_debug1_set; /* 0x074 */ - u32 usbphy_debug1_clr; /* 0x078 */ - u32 usbphy_debug1_tog; /* 0x07c */ - u32 usbphy_version; /* 0x080 */ - u32 reserved2[7]; - u32 usb1_pll_480_ctrl; /* 0x0a0 */ - u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ - u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ - u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ - u32 reserved3[4]; - u32 usb1_vbus_detect; /* 0xc0 */ - u32 usb1_vbus_detect_set; /* 0xc4 */ - u32 usb1_vbus_detect_clr; /* 0xc8 */ - u32 usb1_vbus_detect_tog; /* 0xcc */ - u32 usb1_vbus_det_stat; /* 0xd0 */ - u32 reserved4[3]; - u32 usb1_chrg_detect; /* 0xe0 */ - u32 usb1_chrg_detect_set; /* 0xe4 */ - u32 usb1_chrg_detect_clr; /* 0xe8 */ - u32 usb1_chrg_detect_tog; /* 0xec */ - u32 usb1_chrg_det_stat; /* 0xf0 */ - u32 reserved5[3]; - u32 usbphy_anactrl; /* 0x100 */ - u32 usbphy_anactrl_set; /* 0x104 */ - u32 usbphy_anactrl_clr; /* 0x108 */ - u32 usbphy_anactrl_tog; /* 0x10c */ - u32 usb1_loopback; /* 0x110 */ - u32 usb1_loopback_set; /* 0x114 */ - u32 usb1_loopback_clr; /* 0x118 */ - u32 usb1_loopback_tog; /* 0x11c */ - u32 usb1_loopback_hsfscnt; /* 0x120 */ - u32 usb1_loopback_hsfscnt_set; /* 0x124 */ - u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ - u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ - u32 usphy_trim_override_en; /* 0x130 */ - u32 usphy_trim_override_en_set; /* 0x134 */ - u32 usphy_trim_override_en_clr; /* 0x138 */ - u32 usphy_trim_override_en_tog; /* 0x13c */ - u32 usb1_pfda_ctrl1; /* 0x140 */ - u32 usb1_pfda_ctrl1_set; /* 0x144 */ - u32 usb1_pfda_ctrl1_clr; /* 0x148 */ - u32 usb1_pfda_ctrl1_tog; /* 0x14c */ -}; - -struct bootrom_sw_info { - u8 reserved_1; - u8 boot_dev_instance; - u8 boot_dev_type; - u8 reserved_2; - u32 core_freq; - u32 axi_freq; - u32 ddr_freq; - u32 rom_tick_freq; - u32 reserved_3[3]; -}; - -#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) -#define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) - -#endif - -#endif /* _MX7ULP_REGS_H_*/ diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h deleted file mode 100644 index f067c02..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/iomux.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Based on Linux i.MX iomux-v3.h file: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __MACH_IOMUX_H__ -#define __MACH_IOMUX_H__ - -/* - * build IOMUX_PAD structure - * - * This iomux scheme is based around pads, which are the physical balls - * on the processor. - * - * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls - * things like driving strength and pullup/pulldown. - * - Each pad can have but not necessarily does have an output routing register - * (IOMUXC_SW_MUX_CTL_PAD_x). - * - Each pad can have but not necessarily does have an input routing register - * (IOMUXC_x_SELECT_INPUT) - * - * The three register sets do not have a fixed offset to each other, - * hence we order this table by pad control registers (which all pads - * have) and put the optional i/o routing registers into additional - * fields. - * - * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * - * IOMUX/PAD Bit field definitions - * - * MUX_CTRL_OFS: 0..15 (16) - * SEL_INPUT_OFS: 16..31 (16) - * MUX_MODE: 32..37 (6) - * SEL_INP: 38..41 (4) - * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) - * reserved: 61-63 (3) -*/ - -typedef u64 iomux_cfg_t; - -#define MUX_CTRL_OFS_SHIFT 0 -#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) -#define MUX_SEL_INPUT_OFS_SHIFT 16 -#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ - MUX_SEL_INPUT_OFS_SHIFT) - -#define MUX_MODE_SHIFT 32 -#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) -#define MUX_SEL_INPUT_SHIFT 38 -#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) -#define MUX_PAD_CTRL_SHIFT 42 -#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) - -#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) - -#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ - sel_input, pad_ctrl) \ - (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ - ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ - ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ - ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ - ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) - -#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ - MUX_PAD_CTRL(pad)) - - -#define IOMUX_CONFIG_MPORTS 0x20 -#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ - MUX_MODE_SHIFT) - -/* Bit definition below needs to be fixed acccording to ulp rm */ - -#define NO_PAD_CTRL (1 << 18) -#define PAD_CTL_OBE_ENABLE (1 << 17) -#define PAD_CTL_IBE_ENABLE (1 << 16) -#define PAD_CTL_DSE (1 << 6) -#define PAD_CTL_ODE (1 << 5) -#define PAD_CTL_SRE_FAST (0 << 2) -#define PAD_CTL_SRE_SLOW (1 << 2) -#define PAD_CTL_PUE (1 << 1) -#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) -#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) - - -void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); -void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, - unsigned count); -#endif /* __MACH_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h deleted file mode 100644 index 139b766..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h +++ /dev/null @@ -1,909 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX7ULP_PINS_H__ -#define __ASM_ARCH_IMX7ULP_PINS_H__ - -#include <asm/arch/iomux.h> - -enum { - MX7ULP_PAD_PTA0__CMP0_IN1_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA0__PTA0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA0__LPSPI0_PCS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0), - MX7ULP_PAD_PTA0__LPUART0_CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), - MX7ULP_PAD_PTA0__LPI2C0_SCL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0), - MX7ULP_PAD_PTA0__TPM0_CLKIN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0), - MX7ULP_PAD_PTA0__I2S0_RX_BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0), - MX7ULP_PAD_PTA0__LLWU0_P0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__CMP0_IN2_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__PTA1 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__LPSPI0_PCS2 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0), - MX7ULP_PAD_PTA1__LPUART0_RTS_b = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA1__LPI2C0_SDA = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0), - MX7ULP_PAD_PTA1__TPM0_CH0 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0), - MX7ULP_PAD_PTA1__I2S0_RX_FS = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0), - MX7ULP_PAD_PTA2__CMP1_IN2_3V = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA2__PTA2 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA2__LPSPI0_PCS3 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x1, 0), - MX7ULP_PAD_PTA2__LPUART0_TX = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x1, 0), - MX7ULP_PAD_PTA2__LPI2C0_HREQ = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x1, 0), - MX7ULP_PAD_PTA2__TPM0_CH1 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x1, 0), - MX7ULP_PAD_PTA2__I2S0_RXD0 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x1, 0), - MX7ULP_PAD_PTA3__CMP1_IN4_3V = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA3__PTA3 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA3__LPSPI0_PCS0 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x1, 0), - MX7ULP_PAD_PTA3__LPUART0_RX = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x1, 0), - MX7ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x1, 0), - MX7ULP_PAD_PTA3__I2S0_RXD1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x1, 0), - MX7ULP_PAD_PTA3__CMP0_OUT = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA3__LLWU0_P1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA4__ADC1_CH3A = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA4__PTA4 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA4__LPSPI0_SIN = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0), - MX7ULP_PAD_PTA4__LPUART1_CTS_b = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), - MX7ULP_PAD_PTA4__LPI2C1_SCL = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0), - MX7ULP_PAD_PTA4__TPM0_CH3 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0), - MX7ULP_PAD_PTA4__I2S0_MCLK = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0), - MX7ULP_PAD_PTA5__ADC1_CH3B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA5__PTA5 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA5__LPSPI0_SOUT = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0), - MX7ULP_PAD_PTA5__LPUART1_RTS_b = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA5__LPI2C1_SDA = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0), - MX7ULP_PAD_PTA5__TPM0_CH4 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0), - MX7ULP_PAD_PTA5__I2S0_TX_BCLK = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0), - MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA6__PTA6 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA6__LPSPI0_SCK = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0), - MX7ULP_PAD_PTA6__LPUART1_TX = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0), - MX7ULP_PAD_PTA6__LPI2C1_HREQ = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0), - MX7ULP_PAD_PTA6__TPM0_CH5 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0), - MX7ULP_PAD_PTA6__I2S0_TX_FS = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0), - MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA7__PTA7 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA7__LPUART1_RX = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0), - MX7ULP_PAD_PTA7__TPM1_CH1 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0), - MX7ULP_PAD_PTA7__I2S0_TXD0 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__PTA8 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__LPSPI1_PCS1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0), - MX7ULP_PAD_PTA8__LPUART2_CTS_b = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), - MX7ULP_PAD_PTA8__LPI2C2_SCL = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0), - MX7ULP_PAD_PTA8__TPM1_CLKIN = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0), - MX7ULP_PAD_PTA8__I2S0_TXD1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__PTA9 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__LPSPI1_PCS2 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0), - MX7ULP_PAD_PTA9__LPUART2_RTS_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__LPI2C2_SDA = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0), - MX7ULP_PAD_PTA9__TPM1_CH0 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0), - MX7ULP_PAD_PTA9__NMI0_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__PTA10 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__LPSPI1_PCS3 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0), - MX7ULP_PAD_PTA10__LPUART2_TX = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0), - MX7ULP_PAD_PTA10__LPI2C2_HREQ = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0), - MX7ULP_PAD_PTA10__TPM2_CLKIN = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0), - MX7ULP_PAD_PTA10__I2S0_RX_BCLK = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0), - MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA11__PTA11 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA11__LPUART2_RX = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0), - MX7ULP_PAD_PTA11__TPM2_CH0 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0), - MX7ULP_PAD_PTA11__I2S0_RX_FS = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0), - MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA12__PTA12 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA12__LPSPI1_SIN = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0), - MX7ULP_PAD_PTA12__LPUART3_CTS_b = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), - MX7ULP_PAD_PTA12__LPI2C3_SCL = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0), - MX7ULP_PAD_PTA12__TPM2_CH1 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0), - MX7ULP_PAD_PTA12__I2S0_RXD0 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0), - MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__PTA13 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__LPSPI1_SOUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0), - MX7ULP_PAD_PTA13__LPUART3_RTS_b = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__LPI2C3_SDA = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0), - MX7ULP_PAD_PTA13__TPM3_CLKIN = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0), - MX7ULP_PAD_PTA13__I2S0_RXD1 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0), - MX7ULP_PAD_PTA13__CMP0_OUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA13__LLWU0_P2 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__PTA14 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__LPSPI1_SCK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0), - MX7ULP_PAD_PTA14__LPUART3_TX = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0), - MX7ULP_PAD_PTA14__LPI2C3_HREQ = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x2, 0), - MX7ULP_PAD_PTA14__TPM3_CH0 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0), - MX7ULP_PAD_PTA14__I2S0_MCLK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0), - MX7ULP_PAD_PTA14__LLWU0_P3 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__PTA15 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__LPSPI1_PCS0 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0), - MX7ULP_PAD_PTA15__LPUART3_RX = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0), - MX7ULP_PAD_PTA15__TPM3_CH1 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x1, 0), - MX7ULP_PAD_PTA15__I2S0_TX_BCLK = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x2, 0), - MX7ULP_PAD_PTA16__CMP1_IN5_3V = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA16__PTA16 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA16__FXIO0_D0 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA16__LPSPI0_SOUT = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0), - MX7ULP_PAD_PTA16__LPUART0_CTS_b = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), - MX7ULP_PAD_PTA16__LPI2C0_SCL = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0), - MX7ULP_PAD_PTA16__TPM3_CH2 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0), - MX7ULP_PAD_PTA16__I2S0_TX_FS = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0), - MX7ULP_PAD_PTA17__CMP1_IN6_3V = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__PTA17 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__FXIO0_D1 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__LPSPI0_SCK = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0), - MX7ULP_PAD_PTA17__LPUART0_RTS_b = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA17__LPI2C0_SDA = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0), - MX7ULP_PAD_PTA17__TPM3_CH3 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0), - MX7ULP_PAD_PTA17__I2S0_TXD0 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__CMP1_IN1_3V = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__PTA18 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__FXIO0_D2 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__LPSPI0_PCS0 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x2, 0), - MX7ULP_PAD_PTA18__LPUART0_TX = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x2, 0), - MX7ULP_PAD_PTA18__LPI2C0_HREQ = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x2, 0), - MX7ULP_PAD_PTA18__TPM3_CH4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x1, 0), - MX7ULP_PAD_PTA18__I2S0_TXD1 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA18__LLWU0_P4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__CMP1_IN3_3V = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__PTA19 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__FXIO0_D3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__LPUART0_RX = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x2, 0), - MX7ULP_PAD_PTA19__TPM3_CH5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x1, 0), - MX7ULP_PAD_PTA19__I2S1_RX_BCLK = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0), - MX7ULP_PAD_PTA19__LPTMR0_ALT3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA19__LLWU0_P5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__PTA20 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__FXIO0_D4 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__LPSPI0_SIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0), - MX7ULP_PAD_PTA20__LPUART1_CTS_b = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), - MX7ULP_PAD_PTA20__LPI2C1_SCL = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0), - MX7ULP_PAD_PTA20__TPM0_CLKIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0), - MX7ULP_PAD_PTA20__I2S1_RX_FS = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0), - MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__PTA21 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__FXIO0_D5 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__LPSPI0_PCS1 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0), - MX7ULP_PAD_PTA21__LPUART1_RTS_b = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA21__LPI2C1_SDA = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0), - MX7ULP_PAD_PTA21__TPM0_CH0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0), - MX7ULP_PAD_PTA21__I2S1_RXD0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0), - MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__PTA22 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__FXIO0_D6 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__LPSPI0_PCS2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0), - MX7ULP_PAD_PTA22__LPUART1_TX = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x2, 0), - MX7ULP_PAD_PTA22__LPI2C1_HREQ = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x2, 0), - MX7ULP_PAD_PTA22__TPM0_CH1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0), - MX7ULP_PAD_PTA22__I2S1_RXD1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0), - MX7ULP_PAD_PTA22__LPTMR0_ALT2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__EWM_OUT_b = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__PTA23 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__FXIO0_D7 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__LPSPI0_PCS3 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0), - MX7ULP_PAD_PTA23__LPUART1_RX = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x2, 0), - MX7ULP_PAD_PTA23__TPM0_CH2 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0), - MX7ULP_PAD_PTA23__I2S1_MCLK = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0), - MX7ULP_PAD_PTA23__LLWU0_P6 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__PTA24 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__FXIO0_D8 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__LPSPI1_PCS1 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0), - MX7ULP_PAD_PTA24__LPUART2_CTS_b = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), - MX7ULP_PAD_PTA24__LPI2C2_SCL = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0), - MX7ULP_PAD_PTA24__TPM0_CH3 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0), - MX7ULP_PAD_PTA24__I2S1_TX_BCLK = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0), - MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__PTA25 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__FXIO0_D9 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__LPSPI1_PCS2 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0), - MX7ULP_PAD_PTA25__LPUART2_RTS_b = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA25__LPI2C2_SDA = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0), - MX7ULP_PAD_PTA25__TPM0_CH4 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0), - MX7ULP_PAD_PTA25__I2S1_TX_FS = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0), - MX7ULP_PAD_PTA26__PTA26 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA26__FXIO0_D10 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA26__LPSPI1_PCS3 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x2, 0), - MX7ULP_PAD_PTA26__LPUART2_TX = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x2, 0), - MX7ULP_PAD_PTA26__LPI2C2_HREQ = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x2, 0), - MX7ULP_PAD_PTA26__TPM0_CH5 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x2, 0), - MX7ULP_PAD_PTA26__I2S1_RXD2 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x1, 0), - MX7ULP_PAD_PTA27__PTA27 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA27__JTAG_TDO = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA27__FXIO0_D11 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA27__LPUART2_RX = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x2, 0), - MX7ULP_PAD_PTA27__TPM1_CH1 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x2, 0), - MX7ULP_PAD_PTA27__I2S1_RXD3 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x1, 0), - MX7ULP_PAD_PTA28__PTA28 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA28__JTAG_TDI = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA28__FXIO0_D12 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA28__LPSPI1_SIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0), - MX7ULP_PAD_PTA28__LPUART3_CTS_b = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), - MX7ULP_PAD_PTA28__LPI2C3_SCL = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0), - MX7ULP_PAD_PTA28__TPM1_CLKIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0), - MX7ULP_PAD_PTA28__I2S1_TXD2 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__PTA29 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__FXIO0_D13 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__LPSPI1_SOUT = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0), - MX7ULP_PAD_PTA29__LPUART3_RTS_b = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA29__LPI2C3_SDA = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0), - MX7ULP_PAD_PTA29__TPM1_CH0 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0), - MX7ULP_PAD_PTA29__I2S1_TXD3 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__ADC0_CH1A = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__PTA30 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__FXIO0_D14 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__LPSPI1_SCK = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x1, 0), - MX7ULP_PAD_PTA30__LPUART3_TX = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x1, 0), - MX7ULP_PAD_PTA30__LPI2C3_HREQ = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0), - MX7ULP_PAD_PTA30__TPM2_CLKIN = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0), - MX7ULP_PAD_PTA30__I2S1_TXD0 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__JTAG_TRST_b = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__ADC0_CH1B = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__PTA31 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__FXIO0_D15 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__LPSPI1_PCS0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x2, 0), - MX7ULP_PAD_PTA31__LPUART3_RX = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x2, 0), - MX7ULP_PAD_PTA31__TPM2_CH0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x2, 0), - MX7ULP_PAD_PTA31__I2S1_TXD1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__LPTMR0_ALT1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA31__EWM_IN = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x1, 0), - MX7ULP_PAD_PTA31__LLWU0_P7 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__ADC0_CH0A = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__PTB0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__FXIO0_D16 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__LPSPI0_SIN = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x3, 0), - MX7ULP_PAD_PTB0__LPUART0_TX = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x3, 0), - MX7ULP_PAD_PTB0__TPM2_CH1 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0), - MX7ULP_PAD_PTB0__CLKOUT0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__CMP1_OUT = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__EWM_OUT_b = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__ADC0_CH0B = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__PTB1 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__FXIO0_D17 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__LPSPI0_SOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x3, 0), - MX7ULP_PAD_PTB1__LPUART0_RX = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x3, 0), - MX7ULP_PAD_PTB1__TPM3_CLKIN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x3, 0), - MX7ULP_PAD_PTB1__I2S1_TX_BCLK = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x2, 0), - MX7ULP_PAD_PTB1__RTC_CLKOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB1__EWM_IN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0), - MX7ULP_PAD_PTB1__LLWU0_P8 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__PTB2 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__FXIO0_D18 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__LPSPI0_SCK = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0), - MX7ULP_PAD_PTB2__LPUART1_TX = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x3, 0), - MX7ULP_PAD_PTB2__TPM3_CH0 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0), - MX7ULP_PAD_PTB2__I2S1_TX_FS = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0), - MX7ULP_PAD_PTB2__TRACE_CLKOUT = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__PTB3 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__FXIO0_D19 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__LPSPI0_PCS0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0), - MX7ULP_PAD_PTB3__LPUART1_RX = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x3, 0), - MX7ULP_PAD_PTB3__TPM3_CH1 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x2, 0), - MX7ULP_PAD_PTB3__I2S1_TXD0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__TRACE_D0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__LPTMR1_ALT2 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__LLWU0_P9 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__PTB4 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__FXIO0_D20 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__LPSPI0_PCS1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x3, 0), - MX7ULP_PAD_PTB4__LPUART2_TX = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x3, 0), - MX7ULP_PAD_PTB4__LPI2C0_HREQ = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x3, 0), - MX7ULP_PAD_PTB4__TPM3_CH2 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x2, 0), - MX7ULP_PAD_PTB4__I2S1_TXD1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__QSPIA_DATA7 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB4__TRACE_D1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__PTB5 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__FXIO0_D21 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__LPSPI0_PCS2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0), - MX7ULP_PAD_PTB5__LPUART2_RX = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x3, 0), - MX7ULP_PAD_PTB5__LPI2C1_HREQ = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x3, 0), - MX7ULP_PAD_PTB5__TPM3_CH3 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x2, 0), - MX7ULP_PAD_PTB5__I2S1_TXD2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__QSPIA_DATA6 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB5__TRACE_D2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__ADC1_CH1A = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__PTB6 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__FXIO0_D22 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__LPSPI0_PCS3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x3, 0), - MX7ULP_PAD_PTB6__LPUART3_TX = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x3, 0), - MX7ULP_PAD_PTB6__LPI2C0_SCL = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x3, 0), - MX7ULP_PAD_PTB6__TPM3_CH4 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x2, 0), - MX7ULP_PAD_PTB6__I2S1_TXD3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__QSPIA_DATA5 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__TRACE_D3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__LPTMR1_ALT3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB6__LLWU0_P10 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__ADC1_CH1B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__PTB7 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__FXIO0_D23 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__LPSPI1_SIN = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x3, 0), - MX7ULP_PAD_PTB7__LPUART3_RX = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x3, 0), - MX7ULP_PAD_PTB7__LPI2C0_SDA = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x3, 0), - MX7ULP_PAD_PTB7__TPM3_CH5 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x2, 0), - MX7ULP_PAD_PTB7__I2S1_MCLK = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x2, 0), - MX7ULP_PAD_PTB7__QSPIA_SS1_B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__CMP1_OUT = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB7__LLWU0_P11 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__PTB8 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__FXIO0_D24 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__LPSPI1_SOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x3, 0), - MX7ULP_PAD_PTB8__LPI2C1_SCL = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x3, 0), - MX7ULP_PAD_PTB8__TPM0_CLKIN = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x3, 0), - MX7ULP_PAD_PTB8__I2S1_RX_BCLK = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x2, 0), - MX7ULP_PAD_PTB8__QSPIA_SS0_B = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB8__RTC_CLKOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__PTB9 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__FXIO0_D25 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__LPSPI1_SCK = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x3, 0), - MX7ULP_PAD_PTB9__LPI2C1_SDA = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x3, 0), - MX7ULP_PAD_PTB9__TPM0_CH0 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x3, 0), - MX7ULP_PAD_PTB9__I2S1_RX_FS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x2, 0), - MX7ULP_PAD_PTB9__QSPIA_DQS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB9__LLWU0_P12 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__CMP0_IN1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__PTB10 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__FXIO0_D26 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB10__LPSPI1_PCS0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x3, 0), - MX7ULP_PAD_PTB10__LPI2C2_SCL = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x3, 0), - MX7ULP_PAD_PTB10__TPM0_CH1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x3, 0), - MX7ULP_PAD_PTB10__I2S1_RXD0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x2, 0), - MX7ULP_PAD_PTB10__TRACE_D4 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__CMP0_IN3 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__PTB11 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__FXIO0_D27 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB11__LPSPI1_PCS1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x3, 0), - MX7ULP_PAD_PTB11__LPI2C2_SDA = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x3, 0), - MX7ULP_PAD_PTB11__TPM1_CLKIN = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x3, 0), - MX7ULP_PAD_PTB11__I2S1_RXD1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x2, 0), - MX7ULP_PAD_PTB11__TRACE_D5 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__PTB12 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__FXIO0_D28 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB12__LPSPI1_PCS2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0), - MX7ULP_PAD_PTB12__LPI2C3_SCL = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0), - MX7ULP_PAD_PTB12__TPM1_CH0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0), - MX7ULP_PAD_PTB12__I2S1_RXD2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0), - MX7ULP_PAD_PTB12__TRACE_D6 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__PTB13 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__FXIO0_D29 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__LPSPI1_PCS3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0), - MX7ULP_PAD_PTB13__LPI2C3_SDA = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0), - MX7ULP_PAD_PTB13__TPM1_CH1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0), - MX7ULP_PAD_PTB13__I2S1_RXD3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0), - MX7ULP_PAD_PTB13__QSPIA_DATA4 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB13__TRACE_D7 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__ADC1_CH2A = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__PTB14 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__FXIO0_D30 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__LPI2C2_HREQ = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0), - MX7ULP_PAD_PTB14__TPM2_CLKIN = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0), - MX7ULP_PAD_PTB14__QSPIA_SS1_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__QSPIA_SCLK_b = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__LLWU0_P13 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__ADC1_CH2B = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__PTB15 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__FXIO0_D31 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB15__LPI2C3_HREQ = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0), - MX7ULP_PAD_PTB15__TPM2_CH0 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0), - MX7ULP_PAD_PTB15__QSPIA_SCLK = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__PTB16 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__TPM2_CH1 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0), - MX7ULP_PAD_PTB16__QSPIA_DATA3 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__LLWU0_P14 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__PTB17 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__TPM3_CLKIN = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0), - MX7ULP_PAD_PTB17__QSPIA_DATA2 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__PTB18 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__TPM3_CH0 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0), - MX7ULP_PAD_PTB18__QSPIA_DATA1 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__PTB19 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__TPM3_CH1 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0), - MX7ULP_PAD_PTB19__QSPIA_DATA0 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__LLWU0_P15 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__PTC0 = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__LPUART4_CTS_b = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), - MX7ULP_PAD_PTC0__LPI2C4_SCL = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0), - MX7ULP_PAD_PTC0__TPM4_CLKIN = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0), - MX7ULP_PAD_PTC0__FB_AD0 = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__TRACE_D15 = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__DEBUG_MUX0 = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__PTC1 = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__LPUART4_RTS_b = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__LPI2C4_SDA = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0), - MX7ULP_PAD_PTC1__TPM4_CH0 = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0), - MX7ULP_PAD_PTC1__FB_AD1 = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__TRACE_D14 = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__DEBUG_MUX1 = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__PTC2 = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__LPUART4_TX = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0), - MX7ULP_PAD_PTC2__LPI2C4_HREQ = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0), - MX7ULP_PAD_PTC2__TPM4_CH1 = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0), - MX7ULP_PAD_PTC2__FB_AD2 = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__TRACE_D13 = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__DEBUG_MUX2 = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__PTC3 = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__LPUART4_RX = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0), - MX7ULP_PAD_PTC3__TPM4_CH2 = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0), - MX7ULP_PAD_PTC3__FB_AD3 = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__TRACE_D12 = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__DEBUG_MUX3 = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__PTC4 = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__FXIO1_D0 = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0), - MX7ULP_PAD_PTC4__LPSPI2_PCS1 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0), - MX7ULP_PAD_PTC4__LPUART5_CTS_b = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), - MX7ULP_PAD_PTC4__LPI2C5_SCL = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0), - MX7ULP_PAD_PTC4__TPM4_CH3 = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0), - MX7ULP_PAD_PTC4__FB_AD4 = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__TRACE_D11 = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__DEBUG_MUX4 = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__PTC5 = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__FXIO1_D1 = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0), - MX7ULP_PAD_PTC5__LPSPI2_PCS2 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0), - MX7ULP_PAD_PTC5__LPUART5_RTS_b = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__LPI2C5_SDA = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0), - MX7ULP_PAD_PTC5__TPM4_CH4 = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0), - MX7ULP_PAD_PTC5__FB_AD5 = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__TRACE_D10 = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__DEBUG_MUX5 = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__PTC6 = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__FXIO1_D2 = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0), - MX7ULP_PAD_PTC6__LPSPI2_PCS3 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0), - MX7ULP_PAD_PTC6__LPUART5_TX = IOMUX_PAD(0x0018, 0x0018, 0x4, 0x0258, 0x1, 0), - MX7ULP_PAD_PTC6__LPI2C5_HREQ = IOMUX_PAD(0x0018, 0x0018, 0x5, 0x02B8, 0x1, 0), - MX7ULP_PAD_PTC6__TPM4_CH5 = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0), - MX7ULP_PAD_PTC6__FB_AD6 = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__TRACE_D9 = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__DEBUG_MUX6 = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__PTC7 = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__FXIO1_D3 = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0), - MX7ULP_PAD_PTC7__LPUART5_RX = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0), - MX7ULP_PAD_PTC7__TPM5_CH1 = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0), - MX7ULP_PAD_PTC7__FB_AD7 = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__TRACE_D8 = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__DEBUG_MUX7 = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__PTC8 = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__FXIO1_D4 = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0), - MX7ULP_PAD_PTC8__LPSPI2_SIN = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0), - MX7ULP_PAD_PTC8__LPUART6_CTS_b = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), - MX7ULP_PAD_PTC8__LPI2C6_SCL = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0), - MX7ULP_PAD_PTC8__TPM5_CLKIN = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0), - MX7ULP_PAD_PTC8__FB_AD8 = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__TRACE_D7 = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__DEBUG_MUX8 = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__PTC9 = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__FXIO1_D5 = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0), - MX7ULP_PAD_PTC9__LPSPI2_SOUT = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0), - MX7ULP_PAD_PTC9__LPUART6_RTS_b = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__LPI2C6_SDA = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0), - MX7ULP_PAD_PTC9__TPM5_CH0 = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0), - MX7ULP_PAD_PTC9__FB_AD9 = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__TRACE_D6 = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__DEBUG_MUX9 = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__FXIO1_D6 = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0), - MX7ULP_PAD_PTC10__LPSPI2_SCK = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0), - MX7ULP_PAD_PTC10__LPUART6_TX = IOMUX_PAD(0x0028, 0x0028, 0x4, 0x0264, 0x1, 0), - MX7ULP_PAD_PTC10__LPI2C6_HREQ = IOMUX_PAD(0x0028, 0x0028, 0x5, 0x02F8, 0x1, 0), - MX7ULP_PAD_PTC10__TPM7_CH3 = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0), - MX7ULP_PAD_PTC10__FB_AD10 = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__TRACE_D5 = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__DEBUG_MUX10 = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__PTC11 = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__FXIO1_D7 = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0), - MX7ULP_PAD_PTC11__LPSPI2_PCS0 = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0), - MX7ULP_PAD_PTC11__LPUART6_RX = IOMUX_PAD(0x002C, 0x002C, 0x4, 0x0260, 0x1, 0), - MX7ULP_PAD_PTC11__TPM7_CH4 = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0), - MX7ULP_PAD_PTC11__FB_AD11 = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__TRACE_D4 = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__DEBUG_MUX11 = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__PTC12 = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__FXIO1_D8 = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0), - MX7ULP_PAD_PTC12__LPSPI3_PCS1 = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0), - MX7ULP_PAD_PTC12__LPUART7_CTS_b = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), - MX7ULP_PAD_PTC12__LPI2C7_SCL = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0), - MX7ULP_PAD_PTC12__TPM7_CH5 = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0), - MX7ULP_PAD_PTC12__FB_AD12 = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__TRACE_D3 = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__DEBUG_MUX12 = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__PTC13 = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__FXIO1_D9 = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0), - MX7ULP_PAD_PTC13__LPSPI3_PCS2 = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0), - MX7ULP_PAD_PTC13__LPUART7_RTS_b = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__LPI2C7_SDA = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0), - MX7ULP_PAD_PTC13__TPM7_CLKIN = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0), - MX7ULP_PAD_PTC13__FB_AD13 = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__TRACE_D2 = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__DEBUG_MUX13 = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC14__PTC14 = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC14__FXIO1_D10 = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0), - MX7ULP_PAD_PTC14__LPSPI3_PCS3 = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0), - MX7ULP_PAD_PTC14__LPUART7_TX = IOMUX_PAD(0x0038, 0x0038, 0x4, 0x0270, 0x1, 0), - MX7ULP_PAD_PTC14__LPI2C7_HREQ = IOMUX_PAD(0x0038, 0x0038, 0x5, 0x0304, 0x1, 0), - MX7ULP_PAD_PTC14__TPM7_CH0 = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0), - MX7ULP_PAD_PTC14__FB_AD14 = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC14__TRACE_D1 = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC14__DEBUG_MUX14 = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC15__PTC15 = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC15__FXIO1_D11 = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0), - MX7ULP_PAD_PTC15__LPUART7_RX = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0), - MX7ULP_PAD_PTC15__TPM7_CH1 = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0), - MX7ULP_PAD_PTC15__FB_AD15 = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC15__TRACE_D0 = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC15__DEBUG_MUX15 = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC16__PTC16 = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC16__FXIO1_D12 = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0), - MX7ULP_PAD_PTC16__LPSPI3_SIN = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0), - MX7ULP_PAD_PTC16__TPM7_CH2 = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0), - MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC16__TRACE_CLKOUT = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC16__USB1_ULPI_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0), - MX7ULP_PAD_PTC17__PTC17 = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC17__FXIO1_D13 = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0), - MX7ULP_PAD_PTC17__LPSPI3_SOUT = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0), - MX7ULP_PAD_PTC17__TPM6_CLKIN = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0), - MX7ULP_PAD_PTC17__FB_CS0_b = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC17__DEBUG_MUX16 = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC18__PTC18 = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC18__FXIO1_D14 = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0), - MX7ULP_PAD_PTC18__LPSPI3_SCK = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0), - MX7ULP_PAD_PTC18__TPM6_CH0 = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0), - MX7ULP_PAD_PTC18__FB_OE_b = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC18__DEBUG_MUX17 = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC19__PTC19 = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC19__FXIO1_D15 = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0), - MX7ULP_PAD_PTC19__LPSPI3_PCS0 = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0), - MX7ULP_PAD_PTC19__TPM6_CH1 = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0), - MX7ULP_PAD_PTC19__FB_A16 = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC19__USB1_ULPI_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD0__PTD0 = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD0__DEBUG_MUX18 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD1__PTD1 = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD1__SDHC0_CMD = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD1__DEBUG_MUX19 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD2__PTD2 = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD2__SDHC0_CLK = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD2__DEBUG_MUX20 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD3__PTD3 = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD3__SDHC0_D7 = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD3__DEBUG_MUX21 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD4__PTD4 = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD4__SDHC0_D6 = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD4__DEBUG_MUX22 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD5__PTD5 = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD5__SDHC0_D5 = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD5__DEBUG_MUX23 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD6__PTD6 = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD6__SDHC0_D4 = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD6__DEBUG_MUX24 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD7__PTD7 = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD7__SDHC0_D3 = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD7__DEBUG_MUX25 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD8__PTD8 = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD8__TPM4_CLKIN = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0), - MX7ULP_PAD_PTD8__SDHC0_D2 = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD8__DEBUG_MUX26 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD9__PTD9 = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD9__TPM4_CH0 = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0), - MX7ULP_PAD_PTD9__SDHC0_D1 = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD9__DEBUG_MUX27 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD10__PTD10 = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD10__TPM4_CH1 = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0), - MX7ULP_PAD_PTD10__SDHC0_D0 = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD10__DEBUG_MUX28 = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD11__PTD11 = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD11__TPM4_CH2 = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0), - MX7ULP_PAD_PTD11__SDHC0_DQS = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD11__DEBUG_MUX29 = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE0__PTE0 = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE0__FXIO1_D31 = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE0__LPSPI2_PCS1 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0), - MX7ULP_PAD_PTE0__LPUART4_CTS_b = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0), - MX7ULP_PAD_PTE0__LPI2C4_SCL = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0), - MX7ULP_PAD_PTE0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE0__FB_A25 = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE0__DEBUG_MUX30 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__PTE1 = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__FXIO1_D30 = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__LPSPI2_PCS2 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0), - MX7ULP_PAD_PTE1__LPUART4_RTS_b = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__LPI2C4_SDA = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0), - MX7ULP_PAD_PTE1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__FB_A26 = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__DEBUG_MUX31 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE2__PTE2 = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE2__FXIO1_D29 = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE2__LPSPI2_PCS3 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0), - MX7ULP_PAD_PTE2__LPUART4_TX = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0), - MX7ULP_PAD_PTE2__LPI2C4_HREQ = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0), - MX7ULP_PAD_PTE2__SDHC1_CLK = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE2__DEBUG_MUX32 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE3__PTE3 = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE3__FXIO1_D28 = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE3__LPUART4_RX = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0), - MX7ULP_PAD_PTE3__TPM5_CH1 = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0), - MX7ULP_PAD_PTE3__SDHC1_CMD = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE3__DEBUG_MUX33 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE4__PTE4 = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE4__FXIO1_D27 = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE4__LPSPI2_SIN = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0), - MX7ULP_PAD_PTE4__LPUART5_CTS_b = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0), - MX7ULP_PAD_PTE4__LPI2C5_SCL = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0), - MX7ULP_PAD_PTE4__TPM5_CLKIN = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0), - MX7ULP_PAD_PTE4__SDHC1_D3 = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE5__PTE5 = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE5__FXIO1_D26 = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE5__LPSPI2_SOUT = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0), - MX7ULP_PAD_PTE5__LPUART5_RTS_b = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE5__LPI2C5_SDA = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0), - MX7ULP_PAD_PTE5__TPM5_CH0 = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0), - MX7ULP_PAD_PTE5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE6__PTE6 = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE6__FXIO1_D25 = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE6__LPSPI2_SCK = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0), - MX7ULP_PAD_PTE6__LPUART5_TX = IOMUX_PAD(0x0118, 0x0118, 0x4, 0x0258, 0x2, 0), - MX7ULP_PAD_PTE6__LPI2C5_HREQ = IOMUX_PAD(0x0118, 0x0118, 0x5, 0x02B8, 0x2, 0), - MX7ULP_PAD_PTE6__TPM7_CH3 = IOMUX_PAD(0x0118, 0x0118, 0x6, 0x02E8, 0x2, 0), - MX7ULP_PAD_PTE6__SDHC1_D4 = IOMUX_PAD(0x0118, 0x0118, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE6__FB_A17 = IOMUX_PAD(0x0118, 0x0118, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE6__USB0_OC = IOMUX_PAD(0x0118, 0x0118, 0xb, 0x0330, 0x1, 0), - MX7ULP_PAD_PTE7__PTE7 = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE7__FXIO1_D24 = IOMUX_PAD(0x011C, 0x011C, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE7__LPSPI2_PCS0 = IOMUX_PAD(0x011C, 0x011C, 0x3, 0x029C, 0x2, 0), - MX7ULP_PAD_PTE7__LPUART5_RX = IOMUX_PAD(0x011C, 0x011C, 0x4, 0x0254, 0x2, 0), - MX7ULP_PAD_PTE7__TPM7_CH4 = IOMUX_PAD(0x011C, 0x011C, 0x6, 0x02EC, 0x2, 0), - MX7ULP_PAD_PTE7__SDHC1_D5 = IOMUX_PAD(0x011C, 0x011C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE7__FB_A18 = IOMUX_PAD(0x011C, 0x011C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE7__TRACE_D7 = IOMUX_PAD(0x011C, 0x011C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE7__USB0_PWR = IOMUX_PAD(0x011C, 0x011C, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE7__VIU_FID = IOMUX_PAD(0x011C, 0x011C, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__PTE8 = IOMUX_PAD(0x0120, 0x0120, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__TRACE_D6 = IOMUX_PAD(0x0120, 0x0120, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__VIU_D16 = IOMUX_PAD(0x0120, 0x0120, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__FXIO1_D23 = IOMUX_PAD(0x0120, 0x0120, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__LPSPI3_PCS1 = IOMUX_PAD(0x0120, 0x0120, 0x3, 0x0314, 0x2, 0), - MX7ULP_PAD_PTE8__LPUART6_CTS_b = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0), - MX7ULP_PAD_PTE8__LPI2C6_SCL = IOMUX_PAD(0x0120, 0x0120, 0x5, 0x02FC, 0x2, 0), - MX7ULP_PAD_PTE8__TPM7_CH5 = IOMUX_PAD(0x0120, 0x0120, 0x6, 0x02F0, 0x2, 0), - MX7ULP_PAD_PTE8__SDHC1_WP = IOMUX_PAD(0x0120, 0x0120, 0x7, 0x0200, 0x1, 0), - MX7ULP_PAD_PTE8__SDHC1_D6 = IOMUX_PAD(0x0120, 0x0120, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__FB_CS3_b_FB_BE7_0_BLS31_24_b = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__PTE9 = IOMUX_PAD(0x0124, 0x0124, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__TRACE_D5 = IOMUX_PAD(0x0124, 0x0124, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__VIU_D17 = IOMUX_PAD(0x0124, 0x0124, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__FXIO1_D22 = IOMUX_PAD(0x0124, 0x0124, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__LPSPI3_PCS2 = IOMUX_PAD(0x0124, 0x0124, 0x3, 0x0318, 0x2, 0), - MX7ULP_PAD_PTE9__LPUART6_RTS_b = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__LPI2C6_SDA = IOMUX_PAD(0x0124, 0x0124, 0x5, 0x0300, 0x2, 0), - MX7ULP_PAD_PTE9__TPM7_CLKIN = IOMUX_PAD(0x0124, 0x0124, 0x6, 0x02F4, 0x2, 0), - MX7ULP_PAD_PTE9__SDHC1_CD = IOMUX_PAD(0x0124, 0x0124, 0x7, 0x032C, 0x1, 0), - MX7ULP_PAD_PTE9__SDHC1_D7 = IOMUX_PAD(0x0124, 0x0124, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__FB_TBST_b_FB_CS2_b_FB_BE15_8_BLS23_16_b = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE10__PTE10 = IOMUX_PAD(0x0128, 0x0128, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE10__TRACE_D4 = IOMUX_PAD(0x0128, 0x0128, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE10__VIU_D18 = IOMUX_PAD(0x0128, 0x0128, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE10__FXIO1_D21 = IOMUX_PAD(0x0128, 0x0128, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE10__LPSPI3_PCS3 = IOMUX_PAD(0x0128, 0x0128, 0x3, 0x031C, 0x2, 0), - MX7ULP_PAD_PTE10__LPUART6_TX = IOMUX_PAD(0x0128, 0x0128, 0x4, 0x0264, 0x2, 0), - MX7ULP_PAD_PTE10__LPI2C6_HREQ = IOMUX_PAD(0x0128, 0x0128, 0x5, 0x02F8, 0x2, 0), - MX7ULP_PAD_PTE10__TPM7_CH0 = IOMUX_PAD(0x0128, 0x0128, 0x6, 0x02DC, 0x2, 0), - MX7ULP_PAD_PTE10__SDHC1_VS = IOMUX_PAD(0x0128, 0x0128, 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE10__SDHC1_DQS = IOMUX_PAD(0x0128, 0x0128, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE10__FB_A19 = IOMUX_PAD(0x0128, 0x0128, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE11__PTE11 = IOMUX_PAD(0x012C, 0x012C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE11__TRACE_D3 = IOMUX_PAD(0x012C, 0x012C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE11__VIU_D19 = IOMUX_PAD(0x012C, 0x012C, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE11__FXIO1_D20 = IOMUX_PAD(0x012C, 0x012C, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE11__LPUART6_RX = IOMUX_PAD(0x012C, 0x012C, 0x4, 0x0260, 0x2, 0), - MX7ULP_PAD_PTE11__TPM7_CH1 = IOMUX_PAD(0x012C, 0x012C, 0x6, 0x02E0, 0x2, 0), - MX7ULP_PAD_PTE11__SDHC1_RESET_b = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE11__FB_A20 = IOMUX_PAD(0x012C, 0x012C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE12__PTE12 = IOMUX_PAD(0x0130, 0x0130, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE12__FXIO1_D19 = IOMUX_PAD(0x0130, 0x0130, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE12__LPSPI3_SIN = IOMUX_PAD(0x0130, 0x0130, 0x3, 0x0324, 0x2, 0), - MX7ULP_PAD_PTE12__LPUART7_CTS_b = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0), - MX7ULP_PAD_PTE12__LPI2C7_SCL = IOMUX_PAD(0x0130, 0x0130, 0x5, 0x0308, 0x2, 0), - MX7ULP_PAD_PTE12__TPM7_CH2 = IOMUX_PAD(0x0130, 0x0130, 0x6, 0x02E4, 0x2, 0), - MX7ULP_PAD_PTE12__SDHC1_WP = IOMUX_PAD(0x0130, 0x0130, 0x8, 0x0200, 0x2, 0), - MX7ULP_PAD_PTE12__FB_A21 = IOMUX_PAD(0x0130, 0x0130, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE12__TRACE_D2 = IOMUX_PAD(0x0130, 0x0130, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE12__USB1_ULPI_OC2 = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0), - MX7ULP_PAD_PTE12__VIU_D20 = IOMUX_PAD(0x0130, 0x0130, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__PTE13 = IOMUX_PAD(0x0134, 0x0134, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__FXIO1_D18 = IOMUX_PAD(0x0134, 0x0134, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__LPSPI3_SOUT = IOMUX_PAD(0x0134, 0x0134, 0x3, 0x0328, 0x2, 0), - MX7ULP_PAD_PTE13__LPUART7_RTS_b = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__LPI2C7_SDA = IOMUX_PAD(0x0134, 0x0134, 0x5, 0x030C, 0x2, 0), - MX7ULP_PAD_PTE13__TPM6_CLKIN = IOMUX_PAD(0x0134, 0x0134, 0x6, 0x02D8, 0x2, 0), - MX7ULP_PAD_PTE13__SDHC1_CD = IOMUX_PAD(0x0134, 0x0134, 0x8, 0x032C, 0x2, 0), - MX7ULP_PAD_PTE13__FB_A22 = IOMUX_PAD(0x0134, 0x0134, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__TRACE_D1 = IOMUX_PAD(0x0134, 0x0134, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__USB1_ULPI_PWR2 = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__VIU_D21 = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE14__PTE14 = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE14__FXIO1_D17 = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE14__LPSPI3_SCK = IOMUX_PAD(0x0138, 0x0138, 0x3, 0x0320, 0x2, 0), - MX7ULP_PAD_PTE14__LPUART7_TX = IOMUX_PAD(0x0138, 0x0138, 0x4, 0x0270, 0x2, 0), - MX7ULP_PAD_PTE14__LPI2C7_HREQ = IOMUX_PAD(0x0138, 0x0138, 0x5, 0x0304, 0x2, 0), - MX7ULP_PAD_PTE14__TPM6_CH0 = IOMUX_PAD(0x0138, 0x0138, 0x6, 0x02D0, 0x2, 0), - MX7ULP_PAD_PTE14__SDHC1_VS = IOMUX_PAD(0x0138, 0x0138, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE14__FB_A23 = IOMUX_PAD(0x0138, 0x0138, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE14__TRACE_D0 = IOMUX_PAD(0x0138, 0x0138, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE14__USB0_OC = IOMUX_PAD(0x0138, 0x0138, 0xb, 0x0330, 0x2, 0), - MX7ULP_PAD_PTE14__VIU_D22 = IOMUX_PAD(0x0138, 0x0138, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE15__PTE15 = IOMUX_PAD(0x013C, 0x013C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE15__FXIO1_D16 = IOMUX_PAD(0x013C, 0x013C, 0x2, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE15__LPSPI3_PCS0 = IOMUX_PAD(0x013C, 0x013C, 0x3, 0x0310, 0x2, 0), - MX7ULP_PAD_PTE15__LPUART7_RX = IOMUX_PAD(0x013C, 0x013C, 0x4, 0x026C, 0x2, 0), - MX7ULP_PAD_PTE15__TPM6_CH1 = IOMUX_PAD(0x013C, 0x013C, 0x6, 0x02D4, 0x2, 0), - MX7ULP_PAD_PTE15__FB_A24 = IOMUX_PAD(0x013C, 0x013C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE15__TRACE_CLKOUT = IOMUX_PAD(0x013C, 0x013C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE15__USB0_PWR = IOMUX_PAD(0x013C, 0x013C, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE15__VIU_D23 = IOMUX_PAD(0x013C, 0x013C, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF0__PTF0 = IOMUX_PAD(0x0180, 0x0180, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF0__LPUART4_CTS_b = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0), - MX7ULP_PAD_PTF0__LPI2C4_SCL = IOMUX_PAD(0x0180, 0x0180, 0x5, 0x0278, 0x3, 0), - MX7ULP_PAD_PTF0__TPM4_CLKIN = IOMUX_PAD(0x0180, 0x0180, 0x6, 0x0298, 0x3, 0), - MX7ULP_PAD_PTF0__FB_RW_b = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF1__PTF1 = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF1__LPUART4_RTS_b = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF1__LPI2C4_SDA = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0), - MX7ULP_PAD_PTF1__TPM4_CH0 = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0), - MX7ULP_PAD_PTF1__CLKOUT = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF1__VIU_HSYNC = IOMUX_PAD(0x0184, 0x0184, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF2__PTF2 = IOMUX_PAD(0x0188, 0x0188, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF2__LPUART4_TX = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0), - MX7ULP_PAD_PTF2__LPI2C4_HREQ = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0), - MX7ULP_PAD_PTF2__TPM4_CH1 = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0), - MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF2__VIU_VSYNC = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF3__PTF3 = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF3__LPUART4_RX = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0), - MX7ULP_PAD_PTF3__TPM4_CH2 = IOMUX_PAD(0x018C, 0x018C, 0x6, 0x0288, 0x3, 0), - MX7ULP_PAD_PTF3__FB_AD16 = IOMUX_PAD(0x018C, 0x018C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF3__VIU_PCLK = IOMUX_PAD(0x018C, 0x018C, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF4__PTF4 = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF4__FXIO1_D0 = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0), - MX7ULP_PAD_PTF4__LPSPI2_PCS1 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0), - MX7ULP_PAD_PTF4__LPUART5_CTS_b = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0), - MX7ULP_PAD_PTF4__LPI2C5_SCL = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0), - MX7ULP_PAD_PTF4__TPM4_CH3 = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0), - MX7ULP_PAD_PTF4__FB_AD17 = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF4__VIU_D0 = IOMUX_PAD(0x0190, 0x0190, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF5__PTF5 = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF5__FXIO1_D1 = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0), - MX7ULP_PAD_PTF5__LPSPI2_PCS2 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0), - MX7ULP_PAD_PTF5__LPUART5_RTS_b = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF5__LPI2C5_SDA = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0), - MX7ULP_PAD_PTF5__TPM4_CH4 = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0), - MX7ULP_PAD_PTF5__FB_AD18 = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF5__VIU_D1 = IOMUX_PAD(0x0194, 0x0194, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF6__PTF6 = IOMUX_PAD(0x0198, 0x0198, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF6__FXIO1_D2 = IOMUX_PAD(0x0198, 0x0198, 0x2, 0x020C, 0x2, 0), - MX7ULP_PAD_PTF6__LPSPI2_PCS3 = IOMUX_PAD(0x0198, 0x0198, 0x3, 0x02A8, 0x3, 0), - MX7ULP_PAD_PTF6__LPUART5_TX = IOMUX_PAD(0x0198, 0x0198, 0x4, 0x0258, 0x3, 0), - MX7ULP_PAD_PTF6__LPI2C5_HREQ = IOMUX_PAD(0x0198, 0x0198, 0x5, 0x02B8, 0x3, 0), - MX7ULP_PAD_PTF6__TPM4_CH5 = IOMUX_PAD(0x0198, 0x0198, 0x6, 0x0294, 0x2, 0), - MX7ULP_PAD_PTF6__FB_AD19 = IOMUX_PAD(0x0198, 0x0198, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF6__VIU_D2 = IOMUX_PAD(0x0198, 0x0198, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x019C, 0x019C, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF7__FXIO1_D3 = IOMUX_PAD(0x019C, 0x019C, 0x2, 0x0210, 0x2, 0), - MX7ULP_PAD_PTF7__LPUART5_RX = IOMUX_PAD(0x019C, 0x019C, 0x4, 0x0254, 0x3, 0), - MX7ULP_PAD_PTF7__TPM5_CH1 = IOMUX_PAD(0x019C, 0x019C, 0x6, 0x02C8, 0x3, 0), - MX7ULP_PAD_PTF7__FB_AD20 = IOMUX_PAD(0x019C, 0x019C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF7__VIU_D3 = IOMUX_PAD(0x019C, 0x019C, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__PTF8 = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__FXIO1_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0), - MX7ULP_PAD_PTF8__LPSPI2_SIN = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0), - MX7ULP_PAD_PTF8__LPUART6_CTS_b = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), - MX7ULP_PAD_PTF8__LPI2C6_SCL = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0), - MX7ULP_PAD_PTF8__TPM5_CLKIN = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0), - MX7ULP_PAD_PTF8__FB_AD21 = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__USB1_ULPI_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__VIU_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__PTF9 = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__FXIO1_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0), - MX7ULP_PAD_PTF9__LPSPI2_SOUT = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0), - MX7ULP_PAD_PTF9__LPUART6_RTS_b = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__LPI2C6_SDA = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0), - MX7ULP_PAD_PTF9__TPM5_CH0 = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0), - MX7ULP_PAD_PTF9__FB_AD22 = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__USB1_ULPI_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__VIU_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__PTF10 = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__FXIO1_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0), - MX7ULP_PAD_PTF10__LPSPI2_SCK = IOMUX_PAD(0x01A8, 0x01A8, 0x3, 0x02AC, 0x3, 0), - MX7ULP_PAD_PTF10__LPUART6_TX = IOMUX_PAD(0x01A8, 0x01A8, 0x4, 0x0264, 0x3, 0), - MX7ULP_PAD_PTF10__LPI2C6_HREQ = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0), - MX7ULP_PAD_PTF10__TPM7_CH3 = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0), - MX7ULP_PAD_PTF10__FB_AD23 = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__USB1_ULPI_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__VIU_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__PTF11 = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__FXIO1_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0), - MX7ULP_PAD_PTF11__LPSPI2_PCS0 = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0), - MX7ULP_PAD_PTF11__LPUART6_RX = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0), - MX7ULP_PAD_PTF11__TPM7_CH4 = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0), - MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__USB1_ULPI_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__VIU_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__PTF12 = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__FXIO1_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0), - MX7ULP_PAD_PTF12__LPSPI3_PCS1 = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0), - MX7ULP_PAD_PTF12__LPUART7_CTS_b = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), - MX7ULP_PAD_PTF12__LPI2C7_SCL = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0), - MX7ULP_PAD_PTF12__TPM7_CH5 = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0), - MX7ULP_PAD_PTF12__FB_AD24 = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__USB1_ULPI_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__VIU_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__PTF13 = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__FXIO1_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0), - MX7ULP_PAD_PTF13__LPSPI3_PCS2 = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0), - MX7ULP_PAD_PTF13__LPUART7_RTS_b = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__LPI2C7_SDA = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0), - MX7ULP_PAD_PTF13__TPM7_CLKIN = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0), - MX7ULP_PAD_PTF13__FB_AD25 = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__USB1_ULPI_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__VIU_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__PTF14 = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__FXIO1_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0), - MX7ULP_PAD_PTF14__LPSPI3_PCS3 = IOMUX_PAD(0x01B8, 0x01B8, 0x3, 0x031C, 0x3, 0), - MX7ULP_PAD_PTF14__LPUART7_TX = IOMUX_PAD(0x01B8, 0x01B8, 0x4, 0x0270, 0x3, 0), - MX7ULP_PAD_PTF14__LPI2C7_HREQ = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0), - MX7ULP_PAD_PTF14__TPM7_CH0 = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0), - MX7ULP_PAD_PTF14__FB_AD26 = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__USB1_ULPI_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__VIU_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__PTF15 = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__FXIO1_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0), - MX7ULP_PAD_PTF15__LPUART7_RX = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0), - MX7ULP_PAD_PTF15__TPM7_CH1 = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0), - MX7ULP_PAD_PTF15__FB_AD27 = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__USB1_ULPI_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__VIU_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__PTF16 = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__USB1_ULPI_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__VIU_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__FXIO1_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0), - MX7ULP_PAD_PTF16__LPSPI3_SIN = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0), - MX7ULP_PAD_PTF16__TPM7_CH2 = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0), - MX7ULP_PAD_PTF16__FB_AD28 = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__PTF17 = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__USB1_ULPI_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__VIU_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__FXIO1_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0), - MX7ULP_PAD_PTF17__LPSPI3_SOUT = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0), - MX7ULP_PAD_PTF17__TPM6_CLKIN = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0), - MX7ULP_PAD_PTF17__FB_AD29 = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__PTF18 = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__USB1_ULPI_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__VIU_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__FXIO1_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0), - MX7ULP_PAD_PTF18__LPSPI3_SCK = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0), - MX7ULP_PAD_PTF18__TPM6_CH0 = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0), - MX7ULP_PAD_PTF18__FB_AD30 = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__PTF19 = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__USB1_ULPI_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__VIU_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__FXIO1_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0), - MX7ULP_PAD_PTF19__LPSPI3_PCS0 = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0), - MX7ULP_PAD_PTF19__TPM6_CH1 = IOMUX_PAD(0x01CC, 0x01CC, 0x6, 0x02D4, 0x3, 0), - MX7ULP_PAD_PTF19__FB_AD31 = IOMUX_PAD(0x01CC, 0x01CC, 0x9, 0x0000, 0x0, 0), -}; -#endif /* __ASM_ARCH_IMX7ULP_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S deleted file mode 100644 index bcc804b..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#include <config.h> - -#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180 -#define ROM_VERSION_OFFSET 0x80 -#define ROM_API_HWCNFG_SETUP_OFFSET 0x08 - -plugin_start: - - push {r0-r4, lr} - - imx7ulp_ddr_setting - imx7ulp_clock_gating - imx7ulp_qos_setting - -normal_boot: - -/* - * The following is to fill in those arguments for this ROM function - * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) - * This function is used to copy data from the storage media into DDR. - * start - Initial (possibly partial) image load address on entry. - * Final image load address on exit. - * bytes - Initial (possibly partial) image size on entry. - * Final image size on exit. - * boot_data - Initial @ref ivt Boot Data load address. - */ - adr r0, boot_data2 - adr r1, image_len2 - adr r2, boot_data2 - -/* - * check the _pu_irom_api_table for the address - */ -before_calling_rom___pu_irom_hwcnfg_setup: - ldr r3, =ROM_VERSION_OFFSET - ldr r4, [r3] - ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY - ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] - blx r4 -after_calling_rom___pu_irom_hwcnfg_setup: - -/* - * To return to ROM from plugin, we need to fill in these argument. - * Here is what need to do: - * Need to construct the parameters for this function before return to ROM: - * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) - */ - pop {r0-r4, lr} - push {r5} - ldr r5, boot_data2 - str r5, [r0] - ldr r5, image_len2 - str r5, [r1] - ldr r5, second_ivt_offset - str r5, [r2] - mov r0, #1 - pop {r5} - - /* return back to ROM code */ - bx lr - -/* make the following data right in the end of the output*/ -.ltorg - -#define FLASH_OFFSET 0x400 - -/* - * second_ivt_offset is the offset from the "second_ivt_header" to - * "image_copy_start", which involves FLASH_OFFSET, plus the first - * ivt_header, the plugin code size itself recorded by "ivt2_header" - */ - -second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET) - -/* - * The following is the second IVT header plus the second boot data - */ -ivt2_header: .long 0x0 -app2_code_jump_v: .long 0x0 -reserv3: .long 0x0 -dcd2_ptr: .long 0x0 -boot_data2_ptr: .long 0x0 -self_ptr2: .long 0x0 -app_code_csf2: .long 0x0 -reserv4: .long 0x0 -boot_data2: .long 0x0 -image_len2: .long 0x0 -plugin2: .long 0x0 diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h deleted file mode 100644 index dee3cfc..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ /dev/null @@ -1,372 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _ASM_ARCH_PCC_H -#define _ASM_ARCH_PCC_H - -#include <common.h> -#include <asm/arch/scg.h> - -/* PCC2 */ - -enum pcc2_entry { - /* On-Platform (32 entries) */ - RSVD0_PCC2_SLOT = 0, - RSVD1_PCC2_SLOT = 1, - CA7_GIC_PCC2_SLOT = 2, - RSVD3_PCC2_SLOT = 3, - RSVD4_PCC2_SLOT = 4, - RSVD5_PCC2_SLOT = 5, - RSVD6_PCC2_SLOT = 6, - RSVD7_PCC2_SLOT = 7, - DMA1_PCC2_SLOT = 8, - RSVD9_PCC2_SLOT = 9, - RSVD10_PCC2_SLOT = 10, - RSVD11_PCC2_SLOT = 11, - RSVD12_PCC2_SLOT = 12, - RSVD13_PCC2_SLOT = 13, - RSVD14_PCC2_SLOT = 14, - RGPIO1_PCC2_SLOT = 15, - FLEXBUS0_PCC2_SLOT = 16, - RSVD17_PCC2_SLOT = 17, - RSVD18_PCC2_SLOT = 18, - RSVD19_PCC2_SLOT = 19, - RSVD20_PCC2_SLOT = 20, - RSVD21_PCC2_SLOT = 21, - RSVD22_PCC2_SLOT = 22, - RSVD23_PCC2_SLOT = 23, - RSVD24_PCC2_SLOT = 24, - RSVD25_PCC2_SLOT = 25, - RSVD26_PCC2_SLOT = 26, - SEMA42_1_PCC2_SLOT = 27, - RSVD28_PCC2_SLOT = 28, - RSVD29_PCC2_SLOT = 29, - RSVD30_PCC2_SLOT = 30, - RSVD31_PCC2_SLOT = 31, - - /* Off-Platform (96 entries) */ - RSVD32_PCC2_SLOT = 32, - DMA1_CH_MUX0_PCC2_SLOT = 33, - MU_B_PCC2_SLOT = 34, - SNVS_PCC2_SLOT = 35, - CAAM_PCC2_SLOT = 36, - LPTPM4_PCC2_SLOT = 37, - LPTPM5_PCC2_SLOT = 38, - LPIT1_PCC2_SLOT = 39, - RSVD40_PCC2_SLOT = 40, - LPSPI2_PCC2_SLOT = 41, - LPSPI3_PCC2_SLOT = 42, - LPI2C4_PCC2_SLOT = 43, - LPI2C5_PCC2_SLOT = 44, - LPUART4_PCC2_SLOT = 45, - LPUART5_PCC2_SLOT = 46, - RSVD47_PCC2_SLOT = 47, - RSVD48_PCC2_SLOT = 48, - FLEXIO1_PCC2_SLOT = 49, - RSVD50_PCC2_SLOT = 50, - USBOTG0_PCC2_SLOT = 51, - USBOTG1_PCC2_SLOT = 52, - USBPHY_PCC2_SLOT = 53, - USB_PL301_PCC2_SLOT = 54, - USDHC0_PCC2_SLOT = 55, - USDHC1_PCC2_SLOT = 56, - RSVD57_PCC2_SLOT = 57, - TRGMUX1_PCC2_SLOT = 58, - RSVD59_PCC2_SLOT = 59, - RSVD60_PCC2_SLOT = 60, - WDG1_PCC2_SLOT = 61, - SCG1_PCC2_SLOT = 62, - PCC2_PCC2_SLOT = 63, - PMC1_PCC2_SLOT = 64, - SMC1_PCC2_SLOT = 65, - RCM1_PCC2_SLOT = 66, - WDG2_PCC2_SLOT = 67, - RSVD68_PCC2_SLOT = 68, - TEST_SPACE1_PCC2_SLOT = 69, - TEST_SPACE2_PCC2_SLOT = 70, - TEST_SPACE3_PCC2_SLOT = 71, - RSVD72_PCC2_SLOT = 72, - RSVD73_PCC2_SLOT = 73, - RSVD74_PCC2_SLOT = 74, - RSVD75_PCC2_SLOT = 75, - RSVD76_PCC2_SLOT = 76, - RSVD77_PCC2_SLOT = 77, - RSVD78_PCC2_SLOT = 78, - RSVD79_PCC2_SLOT = 79, - RSVD80_PCC2_SLOT = 80, - RSVD81_PCC2_SLOT = 81, - RSVD82_PCC2_SLOT = 82, - RSVD83_PCC2_SLOT = 83, - RSVD84_PCC2_SLOT = 84, - RSVD85_PCC2_SLOT = 85, - RSVD86_PCC2_SLOT = 86, - RSVD87_PCC2_SLOT = 87, - RSVD88_PCC2_SLOT = 88, - RSVD89_PCC2_SLOT = 89, - RSVD90_PCC2_SLOT = 90, - RSVD91_PCC2_SLOT = 91, - RSVD92_PCC2_SLOT = 92, - RSVD93_PCC2_SLOT = 93, - RSVD94_PCC2_SLOT = 94, - RSVD95_PCC2_SLOT = 95, - RSVD96_PCC2_SLOT = 96, - RSVD97_PCC2_SLOT = 97, - RSVD98_PCC2_SLOT = 98, - RSVD99_PCC2_SLOT = 99, - RSVD100_PCC2_SLOT = 100, - RSVD101_PCC2_SLOT = 101, - RSVD102_PCC2_SLOT = 102, - RSVD103_PCC2_SLOT = 103, - RSVD104_PCC2_SLOT = 104, - RSVD105_PCC2_SLOT = 105, - RSVD106_PCC2_SLOT = 106, - RSVD107_PCC2_SLOT = 107, - RSVD108_PCC2_SLOT = 108, - RSVD109_PCC2_SLOT = 109, - RSVD110_PCC2_SLOT = 110, - RSVD111_PCC2_SLOT = 111, - RSVD112_PCC2_SLOT = 112, - RSVD113_PCC2_SLOT = 113, - RSVD114_PCC2_SLOT = 114, - RSVD115_PCC2_SLOT = 115, - RSVD116_PCC2_SLOT = 116, - RSVD117_PCC2_SLOT = 117, - RSVD118_PCC2_SLOT = 118, - RSVD119_PCC2_SLOT = 119, - RSVD120_PCC2_SLOT = 120, - RSVD121_PCC2_SLOT = 121, - RSVD122_PCC2_SLOT = 122, - RSVD123_PCC2_SLOT = 123, - RSVD124_PCC2_SLOT = 124, - RSVD125_PCC2_SLOT = 125, - RSVD126_PCC2_SLOT = 126, - RSVD127_PCC2_SLOT = 127, -}; - -enum pcc3_entry { - /* On-Platform (32 entries) */ - RSVD0_PCC3_SLOT = 0, - RSVD1_PCC3_SLOT = 1, - RSVD2_PCC3_SLOT = 2, - RSVD3_PCC3_SLOT = 3, - RSVD4_PCC3_SLOT = 4, - RSVD5_PCC3_SLOT = 5, - RSVD6_PCC3_SLOT = 6, - RSVD7_PCC3_SLOT = 7, - RSVD8_PCC3_SLOT = 8, - RSVD9_PCC3_SLOT = 9, - RSVD10_PCC3_SLOT = 10, - RSVD11_PCC3_SLOT = 11, - RSVD12_PCC3_SLOT = 12, - RSVD13_PCC3_SLOT = 13, - RSVD14_PCC3_SLOT = 14, - RSVD15_PCC3_SLOT = 15, - ROMCP1_PCC3_SLOT = 16, - RSVD17_PCC3_SLOT = 17, - RSVD18_PCC3_SLOT = 18, - RSVD19_PCC3_SLOT = 19, - RSVD20_PCC3_SLOT = 20, - RSVD21_PCC3_SLOT = 21, - RSVD22_PCC3_SLOT = 22, - RSVD23_PCC3_SLOT = 23, - RSVD24_PCC3_SLOT = 24, - RSVD25_PCC3_SLOT = 25, - RSVD26_PCC3_SLOT = 26, - RSVD27_PCC3_SLOT = 27, - RSVD28_PCC3_SLOT = 28, - RSVD29_PCC3_SLOT = 29, - RSVD30_PCC3_SLOT = 30, - RSVD31_PCC3_SLOT = 31, - - /* Off-Platform (96 entries) */ - RSVD32_PCC3_SLOT = 32, - LPTPM6_PCC3_SLOT = 33, - LPTPM7_PCC3_SLOT = 34, - RSVD35_PCC3_SLOT = 35, - LPI2C6_PCC3_SLOT = 36, - LPI2C7_PCC3_SLOT = 37, - LPUART6_PCC3_SLOT = 38, - LPUART7_PCC3_SLOT = 39, - VIU0_PCC3_SLOT = 40, - DSI0_PCC3_SLOT = 41, - LCDIF0_PCC3_SLOT = 42, - MMDC0_PCC3_SLOT = 43, - IOMUXC1_PCC3_SLOT = 44, - IOMUXC_DDR_PCC3_SLOT = 45, - PORTC_PCC3_SLOT = 46, - PORTD_PCC3_SLOT = 47, - PORTE_PCC3_SLOT = 48, - PORTF_PCC3_SLOT = 49, - RSVD50_PCC3_SLOT = 50, - PCC3_PCC3_SLOT = 51, - RSVD52_PCC3_SLOT = 52, - WKPU_PCC3_SLOT = 53, - RSVD54_PCC3_SLOT = 54, - RSVD55_PCC3_SLOT = 55, - RSVD56_PCC3_SLOT = 56, - RSVD57_PCC3_SLOT = 57, - RSVD58_PCC3_SLOT = 58, - RSVD59_PCC3_SLOT = 59, - RSVD60_PCC3_SLOT = 60, - RSVD61_PCC3_SLOT = 61, - RSVD62_PCC3_SLOT = 62, - RSVD63_PCC3_SLOT = 63, - RSVD64_PCC3_SLOT = 64, - RSVD65_PCC3_SLOT = 65, - RSVD66_PCC3_SLOT = 66, - RSVD67_PCC3_SLOT = 67, - RSVD68_PCC3_SLOT = 68, - RSVD69_PCC3_SLOT = 69, - RSVD70_PCC3_SLOT = 70, - RSVD71_PCC3_SLOT = 71, - RSVD72_PCC3_SLOT = 72, - RSVD73_PCC3_SLOT = 73, - RSVD74_PCC3_SLOT = 74, - RSVD75_PCC3_SLOT = 75, - RSVD76_PCC3_SLOT = 76, - RSVD77_PCC3_SLOT = 77, - RSVD78_PCC3_SLOT = 78, - RSVD79_PCC3_SLOT = 79, - RSVD80_PCC3_SLOT = 80, - GPU3D_PCC3_SLOT = 81, - GPU2D_PCC3_SLOT = 82, - RSVD83_PCC3_SLOT = 83, - RSVD84_PCC3_SLOT = 84, - RSVD85_PCC3_SLOT = 85, - RSVD86_PCC3_SLOT = 86, - RSVD87_PCC3_SLOT = 87, - RSVD88_PCC3_SLOT = 88, - RSVD89_PCC3_SLOT = 89, - RSVD90_PCC3_SLOT = 90, - RSVD91_PCC3_SLOT = 91, - RSVD92_PCC3_SLOT = 92, - RSVD93_PCC3_SLOT = 93, - RSVD94_PCC3_SLOT = 94, - RSVD95_PCC3_SLOT = 95, - RSVD96_PCC3_SLOT = 96, - RSVD97_PCC3_SLOT = 97, - RSVD98_PCC3_SLOT = 98, - RSVD99_PCC3_SLOT = 99, - RSVD100_PCC3_SLOT = 100, - RSVD101_PCC3_SLOT = 101, - RSVD102_PCC3_SLOT = 102, - RSVD103_PCC3_SLOT = 103, - RSVD104_PCC3_SLOT = 104, - RSVD105_PCC3_SLOT = 105, - RSVD106_PCC3_SLOT = 106, - RSVD107_PCC3_SLOT = 107, - RSVD108_PCC3_SLOT = 108, - RSVD109_PCC3_SLOT = 109, - RSVD110_PCC3_SLOT = 110, - RSVD111_PCC3_SLOT = 111, - RSVD112_PCC3_SLOT = 112, - RSVD113_PCC3_SLOT = 113, - RSVD114_PCC3_SLOT = 114, - RSVD115_PCC3_SLOT = 115, - RSVD116_PCC3_SLOT = 116, - RSVD117_PCC3_SLOT = 117, - RSVD118_PCC3_SLOT = 118, - RSVD119_PCC3_SLOT = 119, - RSVD120_PCC3_SLOT = 120, - RSVD121_PCC3_SLOT = 121, - RSVD122_PCC3_SLOT = 122, - RSVD123_PCC3_SLOT = 123, - RSVD124_PCC3_SLOT = 124, - RSVD125_PCC3_SLOT = 125, - RSVD126_PCC3_SLOT = 126, - RSVD127_PCC3_SLOT = 127, -}; - - -/* PCC registers */ -#define PCC_PR_OFFSET 31 -#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) -#define PCC_CGC_OFFSET 30 -#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET) -#define PCC_INUSE_OFFSET 29 -#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) -#define PCC_PCS_OFFSET 24 -#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) -#define PCC_FRAC_OFFSET 3 -#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) -#define PCC_PCD_OFFSET 0 -#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) - - -enum pcc_clksrc_type { - CLKSRC_PER_PLAT = 0, - CLKSRC_PER_BUS = 1, - CLKSRC_NO_PCS = 2, -}; - -enum pcc_div_type { - PCC_HAS_DIV, - PCC_NO_DIV, -}; - -/* All peripheral clocks on A7 PCCs */ -enum pcc_clk { - /*PCC2 clocks*/ - PER_CLK_DMA1 = 0, - PER_CLK_RGPIO2P1, - PER_CLK_FLEXBUS, - PER_CLK_SEMA42_1, - PER_CLK_DMA_MUX1, - PER_CLK_SNVS, - PER_CLK_CAAM, - PER_CLK_LPTPM4, - PER_CLK_LPTPM5, - PER_CLK_LPIT1, - PER_CLK_LPSPI2, - PER_CLK_LPSPI3, - PER_CLK_LPI2C4, - PER_CLK_LPI2C5, - PER_CLK_LPUART4, - PER_CLK_LPUART5, - PER_CLK_FLEXIO1, - PER_CLK_USB0, - PER_CLK_USB1, - PER_CLK_USB_PHY, - PER_CLK_USB_PL301, - PER_CLK_USDHC0, - PER_CLK_USDHC1, - PER_CLK_WDG1, - PER_CLK_WDG2, - - /*PCC3 clocks*/ - PER_CLK_LPTPM6, - PER_CLK_LPTPM7, - PER_CLK_LPI2C6, - PER_CLK_LPI2C7, - PER_CLK_LPUART6, - PER_CLK_LPUART7, - PER_CLK_VIU, - PER_CLK_DSI, - PER_CLK_LCDIF, - PER_CLK_MMDC, - PER_CLK_PCTLC, - PER_CLK_PCTLD, - PER_CLK_PCTLE, - PER_CLK_PCTLF, - PER_CLK_GPU3D, - PER_CLK_GPU2D, -}; - - -/* This structure keeps info for each pcc slot */ -struct pcc_entry { - u32 pcc_base; - u32 pcc_slot; - enum pcc_clksrc_type clksrc; - enum pcc_div_type div; -}; - -int pcc_clock_enable(enum pcc_clk clk, bool enable); -int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src); -int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div); -bool pcc_clock_is_enable(enum pcc_clk clk); -int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src); -u32 pcc_clock_get_rate(enum pcc_clk clk); -#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h deleted file mode 100644 index 0e4c8ad..0000000 --- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef _SYS_PROTO_MX7ULP_H_ -#define _SYS_PROTO_MX7ULP_H_ - -#include <asm/mach-imx/sys_proto.h> - -#define BT0CFG_LPBOOT_MASK 0x1 -#define BT0CFG_DUALBOOT_MASK 0x2 - -enum bt_mode { - LOW_POWER_BOOT, /* LP_BT = 1 */ - DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ - SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ -}; - -enum boot_device get_boot_device(void); -#endif |