import the U-Boot code and make it compile

49 files changed, 9384 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h
new file mode 100644
index 0000000..0c375e5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33').  This
+ * magic constant will be written into the final image by the rkimage
+ * tool, but we need to reserve space for it here.
+ *
+ * To make life easier for everyone, we build the SPL binary with
+ * space for this 4-byte header already included in the binary.
+ */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * We need to add 4 bytes of space for the 'RK33' at the
+	 * beginning of the executable.	 However, as we want to keep
+	 * this generic and make it applicable to builds that are like
+	 * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
+	 * TPL, but extra space needed in the SPL), we simply insert
+	 * a branch-to-next-instruction-word with the expectation that
+	 * the first one may be overwritten, if this is the first stage
+	 * contained in the final image created with mkimage)...
+	 */
+	b 1f	 /* if overwritten, entry-address is at the next word */
+1:
+#endif
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+	adr     r3, entry_counter
+	ldr	r0, [r3]
+	cmp	r0, #1           /* check if entry_counter == 1 */
+	beq	reset            /* regular bootup */
+	add     r0, #1
+	str	r0, [r3]         /* increment the entry_counter in memory */
+	mov     r0, #0           /* return 0 to the BROM to signal 'OK' */
+	bx	lr               /* return control to the BROM */
+entry_counter:
+	.word   0
+#endif
+
+#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64))
+	/* U-Boot proper of armv7 do not need this */
+	b reset
+#endif
+
+#if !defined(CONFIG_ARM64)
+	/*
+	 * For armv7, the addr '_start' will used as vector start address
+	 * and write to VBAR register, which needs to aligned to 0x20.
+	 */
+	.align(5), 0x0
+_start:
+	ARM_VECTORS
+#endif
+
+#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \
+	(CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
+	.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM	/* space for the ATF data */
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h
new file mode 100644
index 0000000..6b2a610
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/boot_mode.h
@@ -0,0 +1,25 @@
+#ifndef __REBOOT_MODE_H
+#define __REBOOT_MODE_H
+
+/* high 24 bits is tag, low 8 bits is type */
+#define REBOOT_FLAG		0x5242C300
+/* normal boot */
+#define BOOT_NORMAL		(REBOOT_FLAG + 0)
+/* enter loader rockusb mode */
+#define BOOT_LOADER		(REBOOT_FLAG + 1)
+/* enter recovery */
+#define BOOT_RECOVERY		(REBOOT_FLAG + 3)
+/* enter fastboot mode */
+#define BOOT_FASTBOOT		(REBOOT_FLAG + 9)
+/* enter charging mode */
+#define BOOT_CHARGING		(REBOOT_FLAG + 11)
+/* enter usb mass storage mode */
+#define BOOT_UMS		(REBOOT_FLAG + 12)
+/* enter bootrom download mode */
+#define BOOT_BROM_DOWNLOAD	0xEF08A53C
+
+#ifndef __ASSEMBLY__
+int setup_boot_mode(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
new file mode 100644
index 0000000..0da78f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef _ASM_ARCH_BOOTROM_H
+#define _ASM_ARCH_BOOTROM_H
+
+/*
+ * Saved Stack pointer address.
+ * Access might be needed in some special cases.
+ */
+extern u32 SAVE_SP_ADDR;
+
+/**
+ * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a
+ *                     result code
+ *
+ * Transfer control back to the Rockchip BROM, restoring necessary
+ * register context and passing a command/result code to the BROM
+ * to instruct its next actions (e.g. continue boot sequence, enter
+ * download mode, ...).
+ *
+ * This function does not return.
+ *
+ * @brom_cmd: indicates how the bootrom should continue the boot
+ *            sequence (e.g. load the next stage)
+ */
+enum rockchip_bootrom_cmd {
+	/*
+	 * These can not start at 0, as 0 has a special meaning
+	 * for setjmp().
+	 */
+
+	BROM_BOOT_NEXTSTAGE = 1,  /* continue boot-sequence */
+	BROM_BOOT_ENTER_DNL,      /* have BROM enter download-mode */
+};
+
+void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd);
+
+/**
+ * Boot-device identifiers as used by the BROM
+ */
+enum {
+	BROM_BOOTSOURCE_NAND = 1,
+	BROM_BOOTSOURCE_EMMC = 2,
+	BROM_BOOTSOURCE_SPINOR = 3,
+	BROM_BOOTSOURCE_SPINAND = 4,
+	BROM_BOOTSOURCE_SD = 5,
+	BROM_BOOTSOURCE_USB = 10,
+	BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
+};
+
+extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
+
+/**
+ * Locations of the boot-device identifier in SRAM
+ */
+#define BROM_BOOTSOURCE_ID_ADDR   (CONFIG_IRAM_BASE + 0x10)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
new file mode 100644
index 0000000..0eb19ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+/* define pll mode */
+#define RKCLK_PLL_MODE_SLOW		0
+#define RKCLK_PLL_MODE_NORMAL		1
+
+enum {
+	ROCKCHIP_SYSCON_NOC,
+	ROCKCHIP_SYSCON_GRF,
+	ROCKCHIP_SYSCON_SGRF,
+	ROCKCHIP_SYSCON_PMU,
+	ROCKCHIP_SYSCON_PMUGRF,
+	ROCKCHIP_SYSCON_PMUSGRF,
+	ROCKCHIP_SYSCON_CIC,
+	ROCKCHIP_SYSCON_MSCH,
+};
+
+/* Standard Rockchip clock numbers */
+enum rk_clk_id {
+	CLK_OSC,
+	CLK_ARM,
+	CLK_DDR,
+	CLK_CODEC,
+	CLK_GENERAL,
+	CLK_NEW,
+
+	CLK_COUNT,
+};
+
+static inline int rk_pll_id(enum rk_clk_id clk_id)
+{
+	return clk_id - 1;
+}
+
+struct sysreset_reg {
+	unsigned int glb_srst_fst_value;
+	unsigned int glb_srst_snd_value;
+};
+
+struct softreset_reg {
+        void __iomem *base;
+        unsigned int sf_reset_offset;
+        unsigned int sf_reset_num;
+};
+
+/**
+ * clk_get_divisor() - Calculate the required clock divisior
+ *
+ * Given an input rate and a required output_rate, calculate the Rockchip
+ * divisor needed to achieve this.
+ *
+ * @input_rate:		Input clock rate in Hz
+ * @output_rate:	Output clock rate in Hz
+ * @return divisor register value to use
+ */
+static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
+{
+	uint clk_div;
+
+	clk_div = input_rate / output_rate;
+	clk_div = (clk_div + 1) & 0xfffe;
+
+	return clk_div;
+}
+
+/**
+ * rockchip_get_cru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_cru(void);
+
+/**
+ * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_pmucru(void);
+
+struct rk3288_cru;
+struct rk3288_grf;
+
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+
+int rockchip_get_clk(struct udevice **devp);
+
+/*
+ * rockchip_reset_bind() - Bind soft reset device as child of clock device
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * @return 0 success, or error value
+ */
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
new file mode 100644
index 0000000..4722522
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_CRU_RK3036_H
+#define _ASM_ARCH_CRU_RK3036_H
+
+#include <common.h>
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(600 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+
+#define CORE_PERI_HZ	150000000
+#define CORE_ACLK_HZ	300000000
+
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3036_clk_priv {
+	struct rk3036_cru *cru;
+	ulong rate;
+};
+
+struct rk3036_cru {
+	struct rk3036_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+	} pll[4];
+	unsigned int cru_mode_con;
+	unsigned int cru_clksel_con[35];
+	unsigned int cru_clkgate_con[11];
+	unsigned int reserved;
+	unsigned int cru_glb_srst_fst_value;
+	unsigned int cru_glb_srst_snd_value;
+	unsigned int reserved1[2];
+	unsigned int cru_softrst_con[9];
+	unsigned int cru_misc_con;
+	unsigned int reserved2[2];
+	unsigned int cru_glb_cnt_th;
+	unsigned int cru_sdmmc_con[2];
+	unsigned int cru_sdio_con[2];
+	unsigned int cru_emmc_con[2];
+	unsigned int reserved3;
+	unsigned int cru_rst_st;
+	unsigned int reserved4[0x23];
+	unsigned int cru_pll_mask_con;
+};
+check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLLCON0*/
+	PLL_POSTDIV1_SHIFT	= 12,
+	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
+	PLL_FBDIV_SHIFT		= 0,
+	PLL_FBDIV_MASK		= 0xfff,
+
+	/* PLLCON1 */
+	PLL_RST_SHIFT		= 14,
+	PLL_DSMPD_SHIFT		= 12,
+	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
+	PLL_LOCK_STATUS_SHIFT	= 10,
+	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
+	PLL_POSTDIV2_SHIFT	= 6,
+	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
+	PLL_REFDIV_SHIFT	= 0,
+	PLL_REFDIV_MASK		= 0x3f,
+
+	/* CRU_MODE */
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORM,
+	GPLL_MODE_DEEP,
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORM,
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORM,
+
+	/* CRU_CLK_SEL0_CON */
+	BUS_ACLK_PLL_SEL_SHIFT	= 14,
+	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
+	BUS_ACLK_PLL_SEL_APLL	= 0,
+	BUS_ACLK_PLL_SEL_DPLL,
+	BUS_ACLK_PLL_SEL_GPLL,
+	BUS_ACLK_DIV_SHIFT	= 8,
+	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
+	CORE_CLK_PLL_SEL_SHIFT	= 7,
+	CORE_CLK_PLL_SEL_MASK	= 1 << CORE_CLK_PLL_SEL_SHIFT,
+	CORE_CLK_PLL_SEL_APLL	= 0,
+	CORE_CLK_PLL_SEL_GPLL,
+	CORE_DIV_CON_SHIFT	= 0,
+	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL1_CON */
+	BUS_PCLK_DIV_SHIFT	= 12,
+	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
+	BUS_HCLK_DIV_SHIFT	= 8,
+	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
+	CORE_ACLK_DIV_SHIFT	= 4,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+	CORE_PERI_DIV_SHIFT	= 0,
+	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
+
+	/* CRU_CLKSEL10_CON */
+	PERI_PLL_SEL_SHIFT	= 14,
+	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
+	PERI_PLL_APLL		= 0,
+	PERI_PLL_DPLL,
+	PERI_PLL_GPLL,
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL11_CON */
+	SDIO_DIV_SHIFT		= 8,
+	SDIO_DIV_MASK		= 0x7f << SDIO_DIV_SHIFT,
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x7f << MMC0_DIV_SHIFT,
+
+	/* CRU_CLKSEL12_CON */
+	EMMC_PLL_SHIFT		= 12,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_SEL_APLL		= 0,
+	EMMC_SEL_DPLL,
+	EMMC_SEL_GPLL,
+	EMMC_SEL_24M,
+	SDIO_PLL_SHIFT		= 10,
+	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
+	SDIO_SEL_APLL		= 0,
+	SDIO_SEL_DPLL,
+	SDIO_SEL_GPLL,
+	SDIO_SEL_24M,
+	MMC0_PLL_SHIFT		= 8,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_SEL_APLL		= 0,
+	MMC0_SEL_DPLL,
+	MMC0_SEL_GPLL,
+	MMC0_SEL_24M,
+	EMMC_DIV_SHIFT		= 0,
+	EMMC_DIV_MASK		= 0x7f << EMMC_DIV_SHIFT,
+
+	/* CRU_SOFTRST5_CON */
+	DDRCTRL_PSRST_SHIFT	= 11,
+	DDRCTRL_SRST_SHIFT	= 10,
+	DDRPHY_PSRST_SHIFT	= 9,
+	DDRPHY_SRST_SHIFT	= 8,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
new file mode 100644
index 0000000..b856560
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3128_H
+#define _ASM_ARCH_CRU_RK3128_H
+
+#include <common.h>
+
+#define MHz		1000000
+#define OSC_HZ		(24 * MHz)
+
+#define APLL_HZ		(600 * MHz)
+#define GPLL_HZ		(594 * MHz)
+
+#define CORE_PERI_HZ	150000000
+#define CORE_ACLK_HZ	300000000
+
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3128_clk_priv {
+	struct rk3128_cru *cru;
+};
+
+struct rk3128_cru {
+	struct rk3128_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+	} pll[4];
+	unsigned int cru_mode_con;
+	unsigned int cru_clksel_con[35];
+	unsigned int cru_clkgate_con[11];
+	unsigned int reserved;
+	unsigned int cru_glb_srst_fst_value;
+	unsigned int cru_glb_srst_snd_value;
+	unsigned int reserved1[2];
+	unsigned int cru_softrst_con[9];
+	unsigned int cru_misc_con;
+	unsigned int reserved2[2];
+	unsigned int cru_glb_cnt_th;
+	unsigned int reserved3[3];
+	unsigned int cru_glb_rst_st;
+	unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
+	unsigned int cru_sdmmc_con[2];
+	unsigned int cru_sdio_con[2];
+	unsigned int reserved5[2];
+	unsigned int cru_emmc_con[2];
+	unsigned int reserved6[4];
+	unsigned int cru_pll_prg_en;
+};
+check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLLCON0*/
+	PLL_POSTDIV1_SHIFT	= 12,
+	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
+	PLL_FBDIV_SHIFT		= 0,
+	PLL_FBDIV_MASK		= 0xfff,
+
+	/* PLLCON1 */
+	PLL_RST_SHIFT		= 14,
+	PLL_PD_SHIFT		= 13,
+	PLL_PD_MASK		= 1 << PLL_PD_SHIFT,
+	PLL_DSMPD_SHIFT		= 12,
+	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
+	PLL_LOCK_STATUS_SHIFT	= 10,
+	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
+	PLL_POSTDIV2_SHIFT	= 6,
+	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
+	PLL_REFDIV_SHIFT	= 0,
+	PLL_REFDIV_MASK		= 0x3f,
+
+	/* CRU_MODE */
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORM,
+	GPLL_MODE_DEEP,
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 1 << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORM,
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORM,
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORM,
+
+	/* CRU_CLK_SEL0_CON */
+	BUS_ACLK_PLL_SEL_SHIFT	= 14,
+	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
+	BUS_ACLK_PLL_SEL_CPLL	= 0,
+	BUS_ACLK_PLL_SEL_GPLL,
+	BUS_ACLK_PLL_SEL_GPLL_DIV2,
+	BUS_ACLK_PLL_SEL_GPLL_DIV3,
+	BUS_ACLK_DIV_SHIFT	= 8,
+	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
+	CORE_CLK_PLL_SEL_SHIFT	= 7,
+	CORE_CLK_PLL_SEL_MASK	= 1 << CORE_CLK_PLL_SEL_SHIFT,
+	CORE_CLK_PLL_SEL_APLL	= 0,
+	CORE_CLK_PLL_SEL_GPLL_DIV2,
+	CORE_DIV_CON_SHIFT	= 0,
+	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL1_CON */
+	BUS_PCLK_DIV_SHIFT	= 12,
+	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
+	BUS_HCLK_DIV_SHIFT	= 8,
+	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
+	CORE_ACLK_DIV_SHIFT	= 4,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+	CORE_PERI_DIV_SHIFT	= 0,
+	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
+
+	/* CRU_CLK_SEL2_CON */
+	NANDC_PLL_SEL_SHIFT	= 14,
+	NANDC_PLL_SEL_MASK	= 3 << NANDC_PLL_SEL_SHIFT,
+	NANDC_PLL_SEL_CPLL	= 0,
+	NANDC_PLL_SEL_GPLL,
+	NANDC_CLK_DIV_SHIFT	= 8,
+	NANDC_CLK_DIV_MASK	= 0x1f << NANDC_CLK_DIV_SHIFT,
+	PVTM_CLK_DIV_SHIFT	= 0,
+	PVTM_CLK_DIV_MASK	= 0x3f << PVTM_CLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL10_CON */
+	PERI_PLL_SEL_SHIFT	= 14,
+	PERI_PLL_SEL_MASK	= 1 << PERI_PLL_SEL_SHIFT,
+	PERI_PLL_APLL		= 0,
+	PERI_PLL_DPLL,
+	PERI_PLL_GPLL,
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL11_CON */
+	MMC0_PLL_SHIFT		= 6,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_SEL_APLL		= 0,
+	MMC0_SEL_GPLL,
+	MMC0_SEL_GPLL_DIV2,
+	MMC0_SEL_24M,
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
+
+	/* CRU_CLKSEL12_CON */
+	EMMC_PLL_SHIFT		= 14,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_SEL_APLL		= 0,
+	EMMC_SEL_GPLL,
+	EMMC_SEL_GPLL_DIV2,
+	EMMC_SEL_24M,
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
+
+	/* CLKSEL_CON24 */
+	SARADC_DIV_CON_SHIFT	= 8,
+	SARADC_DIV_CON_MASK	= GENMASK(15, 8),
+	SARADC_DIV_CON_WIDTH	= 8,
+
+	/* CRU_CLKSEL27_CON*/
+	DCLK_VOP_SEL_SHIFT         = 0,
+	DCLK_VOP_SEL_MASK          = 1 << DCLK_VOP_SEL_SHIFT,
+	DCLK_VOP_PLL_SEL_CPLL           = 0,
+	DCLK_VOP_DIV_CON_SHIFT          = 8,
+	DCLK_VOP_DIV_CON_MASK           = 0xff << DCLK_VOP_DIV_CON_SHIFT,
+
+	/* CRU_CLKSEL31_CON */
+	VIO0_PLL_SHIFT		= 5,
+	VIO0_PLL_MASK		= 7 << VIO0_PLL_SHIFT,
+	VI00_SEL_CPLL		= 0,
+	VIO0_SEL_GPLL,
+	VIO0_DIV_SHIFT		= 0,
+	VIO0_DIV_MASK		= 0x1f << VIO0_DIV_SHIFT,
+	VIO1_PLL_SHIFT		= 13,
+	VIO1_PLL_MASK		= 7 << VIO1_PLL_SHIFT,
+	VI01_SEL_CPLL		= 0,
+	VIO1_SEL_GPLL,
+	VIO1_DIV_SHIFT		= 8,
+	VIO1_DIV_MASK		= 0x1f << VIO1_DIV_SHIFT,
+
+	/* CRU_SOFTRST5_CON */
+	DDRCTRL_PSRST_SHIFT	= 11,
+	DDRCTRL_SRST_SHIFT	= 10,
+	DDRPHY_PSRST_SHIFT	= 9,
+	DDRPHY_SRST_SHIFT	= 8,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
new file mode 100644
index 0000000..eec4815
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
+ */
+#ifndef _ASM_ARCH_CRU_RK3188_H
+#define _ASM_ARCH_CRU_RK3188_H
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(1608 * 1000000)
+#define APLL_SAFE_HZ	(600 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+#define CPLL_HZ		(384 * 1000000)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ	297000000
+#define CPU_HCLK_HZ	148500000
+#define CPU_PCLK_HZ	74250000
+#define CPU_H2P_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3188_clk_priv {
+	struct rk3188_grf *grf;
+	struct rk3188_cru *cru;
+	ulong rate;
+	bool has_bwadj;
+};
+
+struct rk3188_cru {
+	struct rk3188_pll {
+		u32 con0;
+		u32 con1;
+		u32 con2;
+		u32 con3;
+	} pll[4];
+	u32 cru_mode_con;
+	u32 cru_clksel_con[35];
+	u32 cru_clkgate_con[10];
+	u32 reserved1[2];
+	u32 cru_glb_srst_fst_value;
+	u32 cru_glb_srst_snd_value;
+	u32 reserved2[2];
+	u32 cru_softrst_con[9];
+	u32 cru_misc_con;
+	u32 reserved3[2];
+	u32 cru_glb_cnt_th;
+};
+check_member(rk3188_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+	/* a9_core_div: core = core_src / (a9_core_div + 1) */
+	A9_CORE_DIV_SHIFT	= 9,
+	A9_CORE_DIV_MASK	= 0x1f,
+	CORE_PLL_SHIFT		= 8,
+	CORE_PLL_MASK		= 1,
+	CORE_PLL_SELECT_APLL	= 0,
+	CORE_PLL_SELECT_GPLL,
+
+	/* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
+	CORE_PERI_DIV_SHIFT	= 6,
+	CORE_PERI_DIV_MASK	= 3,
+
+	/* aclk_cpu pll selection */
+	CPU_ACLK_PLL_SHIFT	= 5,
+	CPU_ACLK_PLL_MASK	= 1,
+	CPU_ACLK_PLL_SELECT_APLL	= 0,
+	CPU_ACLK_PLL_SELECT_GPLL,
+
+	/* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
+	A9_CPU_DIV_SHIFT	= 0,
+	A9_CPU_DIV_MASK		= 0x1f,
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+	/* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
+	AHB2APB_DIV_SHIFT	= 14,
+	AHB2APB_DIV_MASK	= 3,
+
+	/* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
+	CPU_PCLK_DIV_SHIFT	= 12,
+	CPU_PCLK_DIV_MASK	= 3,
+
+	/* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
+	CPU_HCLK_DIV_SHIFT	= 8,
+	CPU_HCLK_DIV_MASK	= 3,
+
+	/* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
+	CORE_ACLK_DIV_SHIFT	= 3,
+	CORE_ACLK_DIV_MASK	= 7,
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+	PERI_SEL_PLL_MASK	= 1,
+	PERI_SEL_PLL_SHIFT	= 15,
+	PERI_SEL_CPLL		= 0,
+	PERI_SEL_GPLL,
+
+	/* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3,
+
+	/* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3,
+
+	/* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f,
+};
+/* CRU_CLKSEL11_CON */
+enum {
+	HSICPHY_DIV_SHIFT	= 8,
+	HSICPHY_DIV_MASK	= 0x3f,
+
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+	UART_PLL_SHIFT		= 15,
+	UART_PLL_MASK		= 1,
+	UART_PLL_SELECT_GENERAL	= 0,
+	UART_PLL_SELECT_CODEC,
+
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f,
+
+	SDIO_DIV_SHIFT		= 0,
+	SDIO_DIV_MASK		= 0x3f,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+	SPI1_DIV_SHIFT		= 8,
+	SPI1_DIV_MASK		= 0x7f,
+
+	SPI0_DIV_SHIFT		= 0,
+	SPI0_DIV_MASK		= 0x7f,
+};
+
+/* CRU_MODE_CON */
+enum {
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORMAL,
+	GPLL_MODE_DEEP,
+
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 3,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORMAL,
+	CPLL_MODE_DEEP,
+
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 3,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORMAL,
+	DPLL_MODE_DEEP,
+
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 3,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORMAL,
+	APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+	CLKR_SHIFT		= 8,
+	CLKR_MASK		= 0x3f,
+
+	CLKOD_SHIFT		= 0,
+	CLKOD_MASK		= 0x3f,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+	CLKF_SHIFT		= 0,
+	CLKF_MASK		= 0x1fff,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
new file mode 100644
index 0000000..c87c830
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK322X_H
+#define _ASM_ARCH_CRU_RK322X_H
+
+#include <common.h>
+
+#define MHz		1000000
+#define OSC_HZ		(24 * MHz)
+
+#define APLL_HZ		(600 * MHz)
+#define GPLL_HZ		(594 * MHz)
+
+#define CORE_PERI_HZ	150000000
+#define CORE_ACLK_HZ	300000000
+
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk322x_clk_priv {
+	struct rk322x_cru *cru;
+	ulong rate;
+};
+
+struct rk322x_cru {
+	struct rk322x_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+	} pll[4];
+	unsigned int reserved0[4];
+	unsigned int cru_mode_con;
+	unsigned int cru_clksel_con[35];
+	unsigned int cru_clkgate_con[16];
+	unsigned int cru_softrst_con[9];
+	unsigned int cru_misc_con;
+	unsigned int reserved1[2];
+	unsigned int cru_glb_cnt_th;
+	unsigned int reserved2[3];
+	unsigned int cru_glb_rst_st;
+	unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
+	unsigned int cru_sdmmc_con[2];
+	unsigned int cru_sdio_con[2];
+	unsigned int reserved4[2];
+	unsigned int cru_emmc_con[2];
+	unsigned int reserved5[4];
+	unsigned int cru_glb_srst_fst_value;
+	unsigned int cru_glb_srst_snd_value;
+	unsigned int cru_pll_mask_con;
+};
+check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLLCON0*/
+	PLL_BP_SHIFT		= 15,
+	PLL_POSTDIV1_SHIFT	= 12,
+	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
+	PLL_FBDIV_SHIFT		= 0,
+	PLL_FBDIV_MASK		= 0xfff,
+
+	/* PLLCON1 */
+	PLL_RST_SHIFT		= 14,
+	PLL_PD_SHIFT		= 13,
+	PLL_PD_MASK		= 1 << PLL_PD_SHIFT,
+	PLL_DSMPD_SHIFT		= 12,
+	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
+	PLL_LOCK_STATUS_SHIFT	= 10,
+	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
+	PLL_POSTDIV2_SHIFT	= 6,
+	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
+	PLL_REFDIV_SHIFT	= 0,
+	PLL_REFDIV_MASK		= 0x3f,
+
+	/* CRU_MODE */
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 1 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORM,
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 1 << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORM,
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORM,
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORM,
+
+	/* CRU_CLK_SEL0_CON */
+	BUS_ACLK_PLL_SEL_SHIFT	= 13,
+	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
+	BUS_ACLK_PLL_SEL_APLL	= 0,
+	BUS_ACLK_PLL_SEL_GPLL,
+	BUS_ACLK_PLL_SEL_HDMIPLL,
+	BUS_ACLK_DIV_SHIFT	= 8,
+	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
+	CORE_CLK_PLL_SEL_SHIFT	= 6,
+	CORE_CLK_PLL_SEL_MASK	= 3 << CORE_CLK_PLL_SEL_SHIFT,
+	CORE_CLK_PLL_SEL_APLL	= 0,
+	CORE_CLK_PLL_SEL_GPLL,
+	CORE_CLK_PLL_SEL_DPLL,
+	CORE_DIV_CON_SHIFT	= 0,
+	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL1_CON */
+	BUS_PCLK_DIV_SHIFT	= 12,
+	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
+	BUS_HCLK_DIV_SHIFT	= 8,
+	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
+	CORE_ACLK_DIV_SHIFT	= 4,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+	CORE_PERI_DIV_SHIFT	= 0,
+	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
+
+	/* CRU_CLKSEL5_CON */
+	GMAC_OUT_PLL_SHIFT	= 15,
+	GMAC_OUT_PLL_MASK	= 1 << GMAC_OUT_PLL_SHIFT,
+	GMAC_OUT_DIV_SHIFT	= 8,
+	GMAC_OUT_DIV_MASK	= 0x1f << GMAC_OUT_DIV_SHIFT,
+	MAC_PLL_SEL_SHIFT	= 7,
+	MAC_PLL_SEL_MASK	= 1 << MAC_PLL_SEL_SHIFT,
+	RMII_EXTCLK_SLE_SHIFT	= 5,
+	RMII_EXTCLK_SEL_MASK	= 1 << RMII_EXTCLK_SLE_SHIFT,
+	RMII_EXTCLK_SEL_INT		= 0,
+	RMII_EXTCLK_SEL_EXT,
+	CLK_MAC_DIV_SHIFT	= 0,
+	CLK_MAC_DIV_MASK	= 0x1f << CLK_MAC_DIV_SHIFT,
+
+	/* CRU_CLKSEL10_CON */
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 7 << PERI_PCLK_DIV_SHIFT,
+	PERI_PLL_SEL_SHIFT	= 10,
+	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
+	PERI_PLL_CPLL		= 0,
+	PERI_PLL_GPLL,
+	PERI_PLL_HDMIPLL,
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL11_CON */
+	EMMC_PLL_SHIFT		= 12,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_SEL_CPLL		= 0,
+	EMMC_SEL_GPLL,
+	EMMC_SEL_24M,
+	SDIO_PLL_SHIFT		= 10,
+	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
+	SDIO_SEL_CPLL		= 0,
+	SDIO_SEL_GPLL,
+	SDIO_SEL_24M,
+	MMC0_PLL_SHIFT		= 8,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_SEL_CPLL		= 0,
+	MMC0_SEL_GPLL,
+	MMC0_SEL_24M,
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0xff << MMC0_DIV_SHIFT,
+
+	/* CRU_CLKSEL12_CON */
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0xff << EMMC_DIV_SHIFT,
+	SDIO_DIV_SHIFT		= 0,
+	SDIO_DIV_MASK		= 0xff << SDIO_DIV_SHIFT,
+
+	/* CRU_CLKSEL26_CON */
+	DDR_CLK_PLL_SEL_SHIFT	= 8,
+	DDR_CLK_PLL_SEL_MASK	= 3 << DDR_CLK_PLL_SEL_SHIFT,
+	DDR_CLK_SEL_DPLL	= 0,
+	DDR_CLK_SEL_GPLL,
+	DDR_CLK_SEL_APLL,
+	DDR_DIV_SEL_SHIFT	= 0,
+	DDR_DIV_SEL_MASK	= 3 << DDR_DIV_SEL_SHIFT,
+
+	/* CRU_CLKSEL27_CON */
+	VOP_DCLK_DIV_SHIFT	= 8,
+	VOP_DCLK_DIV_MASK	= 0xff << VOP_DCLK_DIV_SHIFT,
+	VOP_PLL_SEL_SHIFT	= 1,
+	VOP_PLL_SEL_MASK	= 1 << VOP_PLL_SEL_SHIFT,
+
+	/* CRU_CLKSEL29_CON */
+	GMAC_CLK_SRC_SHIFT	= 12,
+	GMAC_CLK_SRC_MASK	= 1 << GMAC_CLK_SRC_SHIFT,
+
+	/* CRU_SOFTRST5_CON */
+	DDRCTRL_PSRST_SHIFT	= 11,
+	DDRCTRL_SRST_SHIFT	= 10,
+	DDRPHY_PSRST_SHIFT	= 9,
+	DDRPHY_SRST_SHIFT	= 8,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
new file mode 100644
index 0000000..e891f20
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ * Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ */
+#ifndef _ASM_ARCH_CRU_RK3288_H
+#define _ASM_ARCH_CRU_RK3288_H
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(1800 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+#define CPLL_HZ		(384 * 1000000)
+#define NPLL_HZ		(384 * 1000000)
+
+/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
+#define PD_BUS_ACLK_HZ	297000000
+#define PD_BUS_HCLK_HZ	148500000
+#define PD_BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3288_clk_priv {
+	struct rk3288_grf *grf;
+	struct rk3288_cru *cru;
+	ulong rate;
+};
+
+struct rk3288_cru {
+	struct rk3288_pll {
+		u32 con0;
+		u32 con1;
+		u32 con2;
+		u32 con3;
+	} pll[5];
+	u32 cru_mode_con;
+	u32 reserved0[3];
+	u32 cru_clksel_con[43];
+	u32 reserved1[21];
+	u32 cru_clkgate_con[19];
+	u32 reserved2;
+	u32 cru_glb_srst_fst_value;
+	u32 cru_glb_srst_snd_value;
+	u32 cru_softrst_con[12];
+	u32 cru_misc_con;
+	u32 cru_glb_cnt_th;
+	u32 cru_glb_rst_con;
+	u32 reserved3;
+	u32 cru_glb_rst_st;
+	u32 reserved4;
+	u32 cru_sdmmc_con[2];
+	u32 cru_sdio0_con[2];
+	u32 cru_sdio1_con[2];
+	u32 cru_emmc_con[2];
+};
+check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
+
+/* CRU_CLKSEL11_CON */
+enum {
+	HSICPHY_DIV_SHIFT	= 8,
+	HSICPHY_DIV_MASK	= 0x3f << HSICPHY_DIV_SHIFT,
+
+	MMC0_PLL_SHIFT		= 6,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_PLL_SELECT_CODEC	= 0,
+	MMC0_PLL_SELECT_GENERAL,
+	MMC0_PLL_SELECT_24MHZ,
+
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL8_CON */
+enum {
+	I2S0_FRAC_DENOM_SHIFT	= 0,
+	I2S0_FRAC_DENOM_MASK	= 0xffff << I2S0_FRAC_DENOM_SHIFT,
+	I2S0_FRAC_NUMER_SHIFT	= 16,
+	I2S0_FRAC_NUMER_MASK	= 0xffffu << I2S0_FRAC_NUMER_SHIFT,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+	EMMC_PLL_SHIFT		= 0xe,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_PLL_SELECT_CODEC	= 0,
+	EMMC_PLL_SELECT_GENERAL,
+	EMMC_PLL_SELECT_24MHZ,
+
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
+
+	SDIO0_PLL_SHIFT		= 6,
+	SDIO0_PLL_MASK		= 3 << SDIO0_PLL_SHIFT,
+	SDIO0_PLL_SELECT_CODEC	= 0,
+	SDIO0_PLL_SELECT_GENERAL,
+	SDIO0_PLL_SELECT_24MHZ,
+
+	SDIO0_DIV_SHIFT		= 0,
+	SDIO0_DIV_MASK		= 0x3f << SDIO0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL21_CON */
+enum {
+	MAC_DIV_CON_SHIFT	= 0xf,
+	MAC_DIV_CON_MASK	= 0x1f << MAC_DIV_CON_SHIFT,
+
+	RMII_EXTCLK_SHIFT	= 4,
+	RMII_EXTCLK_MASK	= 1 << RMII_EXTCLK_SHIFT,
+	RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+	RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+	EMAC_PLL_SHIFT		= 0,
+	EMAC_PLL_MASK		= 0x3 << EMAC_PLL_SHIFT,
+	EMAC_PLL_SELECT_NEW	= 0x0,
+	EMAC_PLL_SELECT_CODEC	= 0x1,
+	EMAC_PLL_SELECT_GENERAL	= 0x2,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+	SPI1_PLL_SHIFT		= 0xf,
+	SPI1_PLL_MASK		= 1 << SPI1_PLL_SHIFT,
+	SPI1_PLL_SELECT_CODEC	= 0,
+	SPI1_PLL_SELECT_GENERAL,
+
+	SPI1_DIV_SHIFT		= 8,
+	SPI1_DIV_MASK		= 0x7f << SPI1_DIV_SHIFT,
+
+	SPI0_PLL_SHIFT		= 7,
+	SPI0_PLL_MASK		= 1 << SPI0_PLL_SHIFT,
+	SPI0_PLL_SELECT_CODEC	= 0,
+	SPI0_PLL_SELECT_GENERAL,
+
+	SPI0_DIV_SHIFT		= 0,
+	SPI0_DIV_MASK		= 0x7f << SPI0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL37_CON */
+enum {
+	PCLK_CORE_DBG_DIV_SHIFT	= 9,
+	PCLK_CORE_DBG_DIV_MASK	= 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
+
+	ATCLK_CORE_DIV_CON_SHIFT = 4,
+	ATCLK_CORE_DIV_CON_MASK	= 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
+
+	CLK_L2RAM_DIV_SHIFT	= 0,
+	CLK_L2RAM_DIV_MASK	= 7 << CLK_L2RAM_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL39_CON */
+enum {
+	ACLK_HEVC_PLL_SHIFT	= 0xe,
+	ACLK_HEVC_PLL_MASK	= 3 << ACLK_HEVC_PLL_SHIFT,
+	ACLK_HEVC_PLL_SELECT_CODEC = 0,
+	ACLK_HEVC_PLL_SELECT_GENERAL,
+	ACLK_HEVC_PLL_SELECT_NEW,
+
+	ACLK_HEVC_DIV_SHIFT	= 8,
+	ACLK_HEVC_DIV_MASK	= 0x1f << ACLK_HEVC_DIV_SHIFT,
+
+	SPI2_PLL_SHIFT		= 7,
+	SPI2_PLL_MASK		= 1 << SPI2_PLL_SHIFT,
+	SPI2_PLL_SELECT_CODEC	= 0,
+	SPI2_PLL_SELECT_GENERAL,
+
+	SPI2_DIV_SHIFT		= 0,
+	SPI2_DIV_MASK		= 0x7f << SPI2_DIV_SHIFT,
+};
+
+/* CRU_MODE_CON */
+enum {
+	CRU_MODE_MASK		= 3,
+
+	NPLL_MODE_SHIFT		= 0xe,
+	NPLL_MODE_MASK		= CRU_MODE_MASK << NPLL_MODE_SHIFT,
+	NPLL_MODE_SLOW		= 0,
+	NPLL_MODE_NORMAL,
+	NPLL_MODE_DEEP,
+
+	GPLL_MODE_SHIFT		= 0xc,
+	GPLL_MODE_MASK		= CRU_MODE_MASK << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORMAL,
+	GPLL_MODE_DEEP,
+
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= CRU_MODE_MASK << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORMAL,
+	CPLL_MODE_DEEP,
+
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= CRU_MODE_MASK << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORMAL,
+	DPLL_MODE_DEEP,
+
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= CRU_MODE_MASK << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORMAL,
+	APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+	CLKR_SHIFT		= 8,
+	CLKR_MASK		= 0x3f << CLKR_SHIFT,
+
+	CLKOD_SHIFT		= 0,
+	CLKOD_MASK		= 0xf << CLKOD_SHIFT,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+	LOCK_SHIFT		= 0x1f,
+	LOCK_MASK		= 1 << LOCK_SHIFT,
+	LOCK_UNLOCK		= 0,
+	LOCK_LOCK,
+
+	CLKF_SHIFT		= 0,
+	CLKF_MASK		= 0x1fff << CLKF_SHIFT,
+};
+
+/* CRU_GLB_RST_ST */
+enum {
+	GLB_POR_RST,
+	FST_GLB_RST_ST		= BIT(0),
+	SND_GLB_RST_ST		= BIT(1),
+	FST_GLB_TSADC_RST_ST	= BIT(2),
+	SND_GLB_TSADC_RST_ST	= BIT(3),
+	FST_GLB_WDT_RST_ST	= BIT(4),
+	SND_GLB_WDT_RST_ST	= BIT(5),
+	GLB_RST_ST_MASK		= GENMASK(5, 0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
new file mode 100644
index 0000000..15b9788
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3328_H_
+#define __ASM_ARCH_CRU_RK3328_H_
+
+#include <common.h>
+
+struct rk3328_clk_priv {
+	struct rk3328_cru *cru;
+	ulong rate;
+};
+
+struct rk3328_cru {
+	u32 apll_con[5];
+	u32 reserved1[3];
+	u32 dpll_con[5];
+	u32 reserved2[3];
+	u32 cpll_con[5];
+	u32 reserved3[3];
+	u32 gpll_con[5];
+	u32 reserved4[3];
+	u32 mode_con;
+	u32 misc;
+	u32 reserved5[2];
+	u32 glb_cnt_th;
+	u32 glb_rst_st;
+	u32 glb_srst_snd_value;
+	u32 glb_srst_fst_value;
+	u32 npll_con[5];
+	u32 reserved6[(0x100 - 0xb4) / 4];
+	u32 clksel_con[53];
+	u32 reserved7[(0x200 - 0x1d4) / 4];
+	u32 clkgate_con[29];
+	u32 reserved8[3];
+	u32 ssgtbl[32];
+	u32 softrst_con[12];
+	u32 reserved9[(0x380 - 0x330) / 4];
+	u32 sdmmc_con[2];
+	u32 sdio_con[2];
+	u32 emmc_con[2];
+	u32 sdmmc_ext_con[2];
+};
+check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24 * MHz)
+#define APLL_HZ		(600 * MHz)
+#define GPLL_HZ		(576 * MHz)
+#define CPLL_HZ		(594 * MHz)
+
+#define CLK_CORE_HZ	(600 * MHz)
+#define ACLKM_CORE_HZ	(300 * MHz)
+#define PCLK_DBG_HZ	(300 * MHz)
+
+#define PERIHP_ACLK_HZ	(144000 * KHz)
+#define PERIHP_HCLK_HZ	(72000 * KHz)
+#define PERIHP_PCLK_HZ	(72000 * KHz)
+
+#define PWM_CLOCK_HZ    (74 * MHz)
+
+enum apll_frequencies {
+	APLL_816_MHZ,
+	APLL_600_MHZ,
+};
+
+#endif	/* __ASM_ARCH_CRU_RK3328_H_ */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
new file mode 100644
index 0000000..1fe1f01
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ */
+#ifndef _ASM_ARCH_CRU_RK3368_H
+#define _ASM_ARCH_CRU_RK3368_H
+
+#include <common.h>
+
+
+/* RK3368 clock numbers */
+enum rk3368_pll_id {
+	APLLB,
+	APLLL,
+	DPLL,
+	CPLL,
+	GPLL,
+	NPLL,
+	PLL_COUNT,
+};
+
+struct rk3368_cru {
+	struct rk3368_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+	} pll[6];
+	unsigned int reserved[0x28];
+	unsigned int clksel_con[56];
+	unsigned int reserved1[8];
+	unsigned int clkgate_con[25];
+	unsigned int reserved2[7];
+	unsigned int glb_srst_fst_val;
+	unsigned int glb_srst_snd_val;
+	unsigned int reserved3[0x1e];
+	unsigned int softrst_con[15];
+	unsigned int reserved4[0x11];
+	unsigned int misc_con;
+	unsigned int glb_cnt_th;
+	unsigned int glb_rst_con;
+	unsigned int glb_rst_st;
+	unsigned int reserved5[0x1c];
+	unsigned int sdmmc_con[2];
+	unsigned int sdio0_con[2];
+	unsigned int sdio1_con[2];
+	unsigned int emmc_con[2];
+};
+check_member(rk3368_cru, emmc_con[1], 0x41c);
+
+struct rk3368_clk_priv {
+	struct rk3368_cru *cru;
+};
+
+enum {
+	/* PLL CON0 */
+	PLL_NR_SHIFT			= 8,
+	PLL_NR_MASK			= GENMASK(13, 8),
+	PLL_OD_SHIFT			= 0,
+	PLL_OD_MASK			= GENMASK(3, 0),
+
+	/* PLL CON1 */
+	PLL_LOCK_STA			= BIT(31),
+	PLL_NF_SHIFT			= 0,
+	PLL_NF_MASK			= GENMASK(12, 0),
+
+	/* PLL CON2 */
+	PLL_BWADJ_SHIFT			= 0,
+	PLL_BWADJ_MASK			= GENMASK(11, 0),
+
+	/* PLL CON3 */
+	PLL_MODE_SHIFT			= 8,
+	PLL_MODE_MASK			= GENMASK(9, 8),
+	PLL_MODE_SLOW			= 0,
+	PLL_MODE_NORMAL			= 1,
+	PLL_MODE_DEEP_SLOW		= 3,
+	PLL_RESET_SHIFT			= 5,
+	PLL_RESET			= 1,
+	PLL_RESET_MASK			= GENMASK(5, 5),
+
+	/* CLKSEL12_CON */
+	MCU_STCLK_DIV_SHIFT		= 8,
+	MCU_STCLK_DIV_MASK		= GENMASK(10, 8),
+	MCU_PLL_SEL_SHIFT		= 7,
+	MCU_PLL_SEL_MASK		= BIT(7),
+	MCU_PLL_SEL_CPLL		= 0,
+	MCU_PLL_SEL_GPLL		= 1,
+	MCU_CLK_DIV_SHIFT		= 0,
+	MCU_CLK_DIV_MASK		= GENMASK(4, 0),
+
+	/* CLKSEL_CON25 */
+	CLK_SARADC_DIV_CON_SHIFT	= 8,
+	CLK_SARADC_DIV_CON_MASK		= GENMASK(15, 8),
+	CLK_SARADC_DIV_CON_WIDTH	= 8,
+
+	/* CLKSEL43_CON */
+	GMAC_DIV_CON_SHIFT		= 0x0,
+	GMAC_DIV_CON_MASK		= GENMASK(4, 0),
+	GMAC_PLL_SHIFT			= 6,
+	GMAC_PLL_MASK			= GENMASK(7, 6),
+	GMAC_PLL_SELECT_NEW		= (0x0 << GMAC_PLL_SHIFT),
+	GMAC_PLL_SELECT_CODEC		= (0x1 << GMAC_PLL_SHIFT),
+	GMAC_PLL_SELECT_GENERAL		= (0x2 << GMAC_PLL_SHIFT),
+	GMAC_MUX_SEL_EXTCLK             = BIT(8),
+
+	/* CLKSEL51_CON */
+	MMC_PLL_SEL_SHIFT		= 8,
+	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
+	MMC_PLL_SEL_CPLL		= (0 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_GPLL                = (1 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_USBPHY_480M         = (2 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_24M                 = (3 << MMC_PLL_SEL_SHIFT),
+	MMC_CLK_DIV_SHIFT		= 0,
+	MMC_CLK_DIV_MASK		= GENMASK(6, 0),
+
+	/* SOFTRST1_CON */
+	MCU_PO_SRST_MASK		= BIT(13),
+	MCU_SYS_SRST_MASK		= BIT(12),
+	DMA1_SRST_REQ                   = BIT(2),
+
+	/* SOFTRST4_CON */
+	DMA2_SRST_REQ                   = BIT(0),
+
+	/* GLB_RST_CON */
+	PMU_GLB_SRST_CTRL_SHIFT		= 2,
+	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
+	PMU_RST_BY_FST_GLB_SRST 	= 0,
+	PMU_RST_BY_SND_GLB_SRST 	= 1,
+	PMU_RST_DISABLE			= 2,
+	WDT_GLB_SRST_CTRL_SHIFT		= 1,
+	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
+	WDT_TRIGGER_SND_GLB_SRST 	= 0,
+	WDT_TRIGGER_FST_GLB_SRST 	= 1,
+	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
+	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
+	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
+	TSADC_TRIGGER_FST_GLB_SRST 	= 1,
+
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
new file mode 100644
index 0000000..15eeb9c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3399_H_
+#define __ASM_ARCH_CRU_RK3399_H_
+
+#include <common.h>
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3399_clk_priv {
+	struct rk3399_cru *cru;
+};
+
+struct rk3399_pmuclk_priv {
+	struct rk3399_pmucru *pmucru;
+};
+
+struct rk3399_pmucru {
+	u32 ppll_con[6];
+	u32 reserved[0x1a];
+	u32 pmucru_clksel[6];
+	u32 pmucru_clkfrac_con[2];
+	u32 reserved2[0x18];
+	u32 pmucru_clkgate_con[3];
+	u32 reserved3;
+	u32 pmucru_softrst_con[2];
+	u32 reserved4[2];
+	u32 pmucru_rstnhold_con[2];
+	u32 reserved5[2];
+	u32 pmucru_gatedis_con[2];
+};
+check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
+
+struct rk3399_cru {
+	u32 apll_l_con[6];
+	u32 reserved[2];
+	u32 apll_b_con[6];
+	u32 reserved1[2];
+	u32 dpll_con[6];
+	u32 reserved2[2];
+	u32 cpll_con[6];
+	u32 reserved3[2];
+	u32 gpll_con[6];
+	u32 reserved4[2];
+	u32 npll_con[6];
+	u32 reserved5[2];
+	u32 vpll_con[6];
+	u32 reserved6[0x0a];
+	u32 clksel_con[108];
+	u32 reserved7[0x14];
+	u32 clkgate_con[35];
+	u32 reserved8[0x1d];
+	u32 softrst_con[21];
+	u32 reserved9[0x2b];
+	u32 glb_srst_fst_value;
+	u32 glb_srst_snd_value;
+	u32 glb_cnt_th;
+	u32 misc_con;
+	u32 glb_rst_con;
+	u32 glb_rst_st;
+	u32 reserved10[0x1a];
+	u32 sdmmc_con[2];
+	u32 sdio0_con[2];
+	u32 sdio1_con[2];
+};
+check_member(rk3399_cru, sdio1_con[1], 0x594);
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24*MHz)
+#define LPLL_HZ		(600*MHz)
+#define BPLL_HZ		(600*MHz)
+#define GPLL_HZ		(594*MHz)
+#define CPLL_HZ		(384*MHz)
+#define PPLL_HZ		(676*MHz)
+
+#define PMU_PCLK_HZ	(48*MHz)
+
+#define ACLKM_CORE_L_HZ	(300*MHz)
+#define ATCLK_CORE_L_HZ	(300*MHz)
+#define PCLK_DBG_L_HZ	(100*MHz)
+
+#define ACLKM_CORE_B_HZ	(300*MHz)
+#define ATCLK_CORE_B_HZ	(300*MHz)
+#define PCLK_DBG_B_HZ	(100*MHz)
+
+#define PERIHP_ACLK_HZ	(148500*KHz)
+#define PERIHP_HCLK_HZ	(148500*KHz)
+#define PERIHP_PCLK_HZ	(37125*KHz)
+
+#define PERILP0_ACLK_HZ	(99000*KHz)
+#define PERILP0_HCLK_HZ	(99000*KHz)
+#define PERILP0_PCLK_HZ	(49500*KHz)
+
+#define PERILP1_HCLK_HZ	(99000*KHz)
+#define PERILP1_PCLK_HZ	(49500*KHz)
+
+#define PWM_CLOCK_HZ    PMU_PCLK_HZ
+
+enum apll_l_frequencies {
+	APLL_L_1600_MHZ,
+	APLL_L_600_MHZ,
+};
+
+enum apll_b_frequencies {
+	APLL_B_600_MHZ,
+};
+
+void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+			    enum apll_l_frequencies apll_l_freq);
+void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+			    enum apll_b_frequencies apll_b_freq);
+
+#endif	/* __ASM_ARCH_CRU_RK3399_H_ */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
new file mode 100644
index 0000000..7697e96
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ */
+#ifndef _ASM_ARCH_CRU_RV1108_H
+#define _ASM_ARCH_CRU_RV1108_H
+
+#include <common.h>
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(600 * 1000000)
+#define GPLL_HZ		(1188 * 1000000)
+#define ACLK_PERI_HZ	(148500000)
+#define HCLK_PERI_HZ	(148500000)
+#define PCLK_PERI_HZ	(74250000)
+#define ACLK_BUS_HZ	(148500000)
+
+struct rv1108_clk_priv {
+	struct rv1108_cru *cru;
+	ulong rate;
+};
+
+struct rv1108_cru {
+	struct rv1108_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+		unsigned int con4;
+		unsigned int con5;
+		unsigned int reserved[2];
+	} pll[3];
+	unsigned int clksel_con[46];
+	unsigned int reserved1[2];
+	unsigned int clkgate_con[20];
+	unsigned int reserved2[4];
+	unsigned int softrst_con[13];
+	unsigned int reserved3[3];
+	unsigned int glb_srst_fst_val;
+	unsigned int glb_srst_snd_val;
+	unsigned int glb_cnt_th;
+	unsigned int misc_con;
+	unsigned int glb_rst_con;
+	unsigned int glb_rst_st;
+	unsigned int sdmmc_con[2];
+	unsigned int sdio_con[2];
+	unsigned int emmc_con[2];
+};
+check_member(rv1108_cru, emmc_con[1], 0x01ec);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLL CON0 */
+	FBDIV_MASK		= 0xfff,
+	FBDIV_SHIFT		= 0,
+
+	/* PLL CON1 */
+	POSTDIV2_SHIFT          = 12,
+	POSTDIV2_MASK		= 7 << POSTDIV2_SHIFT,
+	POSTDIV1_SHIFT          = 8,
+	POSTDIV1_MASK		= 7 << POSTDIV1_SHIFT,
+	REFDIV_MASK		= 0x3f,
+	REFDIV_SHIFT		= 0,
+
+	/* PLL CON2 */
+	LOCK_STA_SHIFT          = 31,
+	LOCK_STA_MASK		= 1 << LOCK_STA_SHIFT,
+	FRACDIV_MASK		= 0xffffff,
+	FRACDIV_SHIFT		= 0,
+
+	/* PLL CON3 */
+	WORK_MODE_SHIFT         = 8,
+	WORK_MODE_MASK		= 1 << WORK_MODE_SHIFT,
+	WORK_MODE_SLOW		= 0,
+	WORK_MODE_NORMAL	= 1,
+	DSMPD_SHIFT             = 3,
+	DSMPD_MASK		= 1 << DSMPD_SHIFT,
+	INTEGER_MODE			= 1,
+	GLOBAL_POWER_DOWN_SHIFT		= 0,
+	GLOBAL_POWER_DOWN_MASK		= 1 << GLOBAL_POWER_DOWN_SHIFT,
+	GLOBAL_POWER_DOWN		= 1,
+	GLOBAL_POWER_UP			= 0,
+
+	/* CLKSEL0_CON */
+	CORE_PLL_SEL_SHIFT	= 8,
+	CORE_PLL_SEL_MASK	= 3 << CORE_PLL_SEL_SHIFT,
+	CORE_PLL_SEL_APLL	= 0,
+	CORE_PLL_SEL_GPLL	= 1,
+	CORE_PLL_SEL_DPLL	= 2,
+	CORE_CLK_DIV_SHIFT	= 0,
+	CORE_CLK_DIV_MASK	= 0x1f << CORE_CLK_DIV_SHIFT,
+
+	/* CLKSEL_CON1 */
+	PCLK_DBG_DIV_CON_SHIFT		= 4,
+	PCLK_DBG_DIV_CON_MASK		= 0xf << PCLK_DBG_DIV_CON_SHIFT,
+	ACLK_CORE_DIV_CON_SHIFT		= 0,
+	ACLK_CORE_DIV_CON_MASK		= 7 << ACLK_CORE_DIV_CON_SHIFT,
+
+	/* CLKSEL_CON2 */
+	ACLK_BUS_PLL_SEL_SHIFT		= 8,
+	ACLK_BUS_PLL_SEL_MASK		= 3 << ACLK_BUS_PLL_SEL_SHIFT,
+	ACLK_BUS_PLL_SEL_GPLL		= 0,
+	ACLK_BUS_PLL_SEL_APLL		= 1,
+	ACLK_BUS_PLL_SEL_DPLL		= 2,
+	ACLK_BUS_DIV_CON_SHIFT		= 0,
+	ACLK_BUS_DIV_CON_MASK		= 0x1f << ACLK_BUS_DIV_CON_SHIFT,
+	ACLK_BUS_DIV_CON_WIDTH		= 5,
+
+	/* CLKSEL_CON3 */
+	PCLK_BUS_DIV_CON_SHIFT		= 8,
+	PCLK_BUS_DIV_CON_MASK		= 0x1f << PCLK_BUS_DIV_CON_SHIFT,
+	HCLK_BUS_DIV_CON_SHIFT		= 0,
+	HCLK_BUS_DIV_CON_MASK		= 0x1f,
+
+	/* CLKSEL_CON4 */
+	CLK_DDR_PLL_SEL_SHIFT		= 8,
+	CLK_DDR_PLL_SEL_MASK		= 0x3 << CLK_DDR_PLL_SEL_SHIFT,
+	CLK_DDR_DIV_CON_SHIFT		= 0,
+	CLK_DDR_DIV_CON_MASK		= 0x3 << CLK_DDR_DIV_CON_SHIFT,
+
+	/* CLKSEL_CON19 */
+	CLK_I2C1_PLL_SEL_SHIFT		= 15,
+	CLK_I2C1_PLL_SEL_MASK		= 1 << CLK_I2C1_PLL_SEL_SHIFT,
+	CLK_I2C1_PLL_SEL_DPLL		= 0,
+	CLK_I2C1_PLL_SEL_GPLL		= 1,
+	CLK_I2C1_DIV_CON_SHIFT		= 8,
+	CLK_I2C1_DIV_CON_MASK		= 0x7f << CLK_I2C1_DIV_CON_SHIFT,
+	CLK_I2C0_PLL_SEL_SHIFT		= 7,
+	CLK_I2C0_PLL_SEL_MASK		= 1 << CLK_I2C0_PLL_SEL_SHIFT,
+	CLK_I2C0_DIV_CON_SHIFT		= 0,
+	CLK_I2C0_DIV_CON_MASK		= 0x7f,
+	I2C_DIV_CON_WIDTH		= 7,
+
+	/* CLKSEL_CON20 */
+	CLK_I2C3_PLL_SEL_SHIFT		= 15,
+	CLK_I2C3_PLL_SEL_MASK		= 1 << CLK_I2C3_PLL_SEL_SHIFT,
+	CLK_I2C3_PLL_SEL_DPLL		= 0,
+	CLK_I2C3_PLL_SEL_GPLL		= 1,
+	CLK_I2C3_DIV_CON_SHIFT		= 8,
+	CLK_I2C3_DIV_CON_MASK		= 0x7f << CLK_I2C3_DIV_CON_SHIFT,
+	CLK_I2C2_PLL_SEL_SHIFT		= 7,
+	CLK_I2C2_PLL_SEL_MASK		= 1 << CLK_I2C2_PLL_SEL_SHIFT,
+	CLK_I2C2_DIV_CON_SHIFT		= 0,
+	CLK_I2C2_DIV_CON_MASK		= 0x7f,
+
+	/* CLKSEL_CON22 */
+	CLK_SARADC_DIV_CON_SHIFT= 0,
+	CLK_SARADC_DIV_CON_MASK	= GENMASK(9, 0),
+	CLK_SARADC_DIV_CON_WIDTH= 10,
+
+	/* CLKSEL_CON23 */
+	ACLK_PERI_PLL_SEL_SHIFT		= 15,
+	ACLK_PERI_PLL_SEL_MASK		= 1 << ACLK_PERI_PLL_SEL_SHIFT,
+	ACLK_PERI_PLL_SEL_GPLL		= 0,
+	ACLK_PERI_PLL_SEL_DPLL		= 1,
+	PCLK_PERI_DIV_CON_SHIFT		= 10,
+	PCLK_PERI_DIV_CON_MASK		= 0x1f << PCLK_PERI_DIV_CON_SHIFT,
+	HCLK_PERI_DIV_CON_SHIFT		= 5,
+	HCLK_PERI_DIV_CON_MASK		= 0x1f << HCLK_PERI_DIV_CON_SHIFT,
+	ACLK_PERI_DIV_CON_SHIFT		= 0,
+	ACLK_PERI_DIV_CON_MASK		= 0x1f,
+	PERI_DIV_CON_WIDTH		= 5,
+
+	/* CLKSEL24_CON */
+	MAC_PLL_SEL_SHIFT	= 12,
+	MAC_PLL_SEL_MASK	= 1 << MAC_PLL_SEL_SHIFT,
+	MAC_PLL_SEL_APLL	= 0,
+	MAC_PLL_SEL_GPLL	= 1,
+	RMII_EXTCLK_SEL_SHIFT   = 8,
+	RMII_EXTCLK_SEL_MASK	= 1 << RMII_EXTCLK_SEL_SHIFT,
+	MAC_CLK_DIV_MASK	= 0x1f,
+	MAC_CLK_DIV_SHIFT	= 0,
+
+	/* CLKSEL25_CON */
+	EMMC_PLL_SEL_SHIFT	= 12,
+	EMMC_PLL_SEL_MASK	= 3 << EMMC_PLL_SEL_SHIFT,
+	EMMC_PLL_SEL_DPLL	= 0,
+	EMMC_PLL_SEL_GPLL,
+	EMMC_PLL_SEL_OSC,
+
+	/* CLKSEL26_CON */
+	EMMC_CLK_DIV_SHIFT	= 8,
+	EMMC_CLK_DIV_MASK	= 0xff << EMMC_CLK_DIV_SHIFT,
+
+	/* CLKSEL27_CON */
+	SFC_PLL_SEL_SHIFT	= 7,
+	SFC_PLL_SEL_MASK	= 1 << SFC_PLL_SEL_SHIFT,
+	SFC_PLL_SEL_DPLL	= 0,
+	SFC_PLL_SEL_GPLL	= 1,
+	SFC_CLK_DIV_SHIFT	= 0,
+	SFC_CLK_DIV_MASK	= 0x3f << SFC_CLK_DIV_SHIFT,
+
+	/* CLKSEL28_CON */
+	ACLK_VIO1_PLL_SEL_SHIFT		= 14,
+	ACLK_VIO1_PLL_SEL_MASK		= 3 << ACLK_VIO1_PLL_SEL_SHIFT,
+	VIO_PLL_SEL_DPLL		= 0,
+	VIO_PLL_SEL_GPLL		= 1,
+	ACLK_VIO1_CLK_DIV_SHIFT		= 8,
+	ACLK_VIO1_CLK_DIV_MASK		= 0x1f << ACLK_VIO1_CLK_DIV_SHIFT,
+	CLK_VIO_DIV_CON_WIDTH		= 5,
+	ACLK_VIO0_PLL_SEL_SHIFT		= 6,
+	ACLK_VIO0_PLL_SEL_MASK		= 3 << ACLK_VIO0_PLL_SEL_SHIFT,
+	ACLK_VIO0_CLK_DIV_SHIFT		= 0,
+	ACLK_VIO0_CLK_DIV_MASK		= 0x1f << ACLK_VIO0_CLK_DIV_SHIFT,
+
+	/* CLKSEL29_CON */
+	PCLK_VIO_CLK_DIV_SHIFT		= 8,
+	PCLK_VIO_CLK_DIV_MASK		= 0x1f << PCLK_VIO_CLK_DIV_SHIFT,
+	HCLK_VIO_CLK_DIV_SHIFT		= 0,
+	HCLK_VIO_CLK_DIV_MASK		= 0x1f << HCLK_VIO_CLK_DIV_SHIFT,
+
+	/* CLKSEL32_CON */
+	DCLK_VOP_SEL_SHIFT		= 7,
+	DCLK_VOP_SEL_MASK		= 1 << DCLK_VOP_SEL_SHIFT,
+	DCLK_VOP_SEL_HDMI		= 0,
+	DCLK_VOP_SEL_PLL		= 1,
+	DCLK_VOP_PLL_SEL_SHIFT		= 6,
+	DCLK_VOP_PLL_SEL_MASK		= 1 << DCLK_VOP_PLL_SEL_SHIFT,
+	DCLK_VOP_PLL_SEL_GPLL		= 0,
+	DCLK_VOP_PLL_SEL_DPLL		= 1,
+	DCLK_VOP_CLK_DIV_SHIFT		= 0,
+	DCLK_VOP_CLK_DIV_MASK		= 0x3f << DCLK_VOP_CLK_DIV_SHIFT,
+	DCLK_VOP_DIV_CON_WIDTH		= 6,
+
+	/* SOFTRST1_CON*/
+	DDRPHY_SRSTN_CLKDIV_REQ_SHIFT	= 0,
+	DDRPHY_SRSTN_CLKDIV_REQ		= 1,
+	DDRPHY_SRSTN_CLKDIV_DIS		= 0,
+	DDRPHY_SRSTN_CLKDIV_REQ_MASK	= 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT,
+	DDRPHY_SRSTN_REQ_SHIFT		= 1,
+	DDRPHY_SRSTN_REQ		= 1,
+	DDRPHY_SRSTN_DIS		= 0,
+	DDRPHY_SRSTN_REQ_MASK		= 1 << DDRPHY_SRSTN_REQ_SHIFT,
+	DDRPHY_PSRSTN_REQ_SHIFT		= 2,
+	DDRPHY_PSRSTN_REQ		= 1,
+	DDRPHY_PSRSTN_DIS		= 0,
+	DDRPHY_PSRSTN_REQ_MASK		= 1 << DDRPHY_PSRSTN_REQ_SHIFT,
+
+	/* SOFTRST2_CON*/
+	DDRUPCTL_PSRSTN_REQ_SHIFT	= 0,
+	DDRUPCTL_PSRSTN_REQ		= 1,
+	DDRUPCTL_PSRSTN_DIS		= 0,
+	DDRUPCTL_PSRSTN_REQ_MASK	= 1 << DDRUPCTL_PSRSTN_REQ_SHIFT,
+	DDRUPCTL_NSRSTN_REQ_SHIFT	= 1,
+	DDRUPCTL_NSRSTN_REQ		= 1,
+	DDRUPCTL_NSRSTN_DIS		= 0,
+	DDRUPCTL_NSRSTN_REQ_MASK	= 1 << DDRUPCTL_NSRSTN_REQ_SHIFT,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
new file mode 100644
index 0000000..db83d0e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_DDR_RK3188_H
+#define _ASM_ARCH_DDR_RK3188_H
+
+#include <asm/arch-rockchip/ddr_rk3288.h>
+
+/*
+ * RK3188 Memory scheduler register map.
+ */
+struct rk3188_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+};
+check_member(rk3188_msch, readlatency, 0x0014);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
new file mode 100644
index 0000000..979d547
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -0,0 +1,443 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_DDR_RK3288_H
+#define _ASM_ARCH_DDR_RK3288_H
+
+struct rk3288_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 tstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 reserved5[14];
+	u32 ecccfg;
+	u32 ecctst;
+	u32 eccclr;
+	u32 ecclog;
+	u32 reserved6[28];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3288_ddr_pctl, iptr, 0x03fc);
+
+struct rk3288_ddr_publ_datx {
+	u32 dxgcr;
+	u32 dxgsr[2];
+	u32 dxdllcr;
+	u32 dxdqtr;
+	u32 dxdqstr;
+	u32 reserved[10];
+};
+
+struct rk3288_ddr_publ {
+	u32 ridr;
+	u32 pir;
+	u32 pgcr;
+	u32 pgsr;
+	u32 dllgcr;
+	u32 acdllcr;
+	u32 ptr[3];
+	u32 aciocr;
+	u32 dxccr;
+	u32 dsgcr;
+	u32 dcr;
+	u32 dtpr[3];
+	u32 mr[4];
+	u32 odtcr;
+	u32 dtar;
+	u32 dtdr[2];
+	u32 reserved1[24];
+	u32 dcuar;
+	u32 dcudr;
+	u32 dcurr;
+	u32 dculr;
+	u32 dcugcr;
+	u32 dcutpr;
+	u32 dcusr[2];
+	u32 reserved2[8];
+	u32 bist[17];
+	u32 reserved3[15];
+	u32 zq0cr[2];
+	u32 zq0sr[2];
+	u32 zq1cr[2];
+	u32 zq1sr[2];
+	u32 zq2cr[2];
+	u32 zq2sr[2];
+	u32 zq3cr[2];
+	u32 zq3sr[2];
+	struct rk3288_ddr_publ_datx datx8[4];
+};
+check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294);
+
+struct rk3288_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 reserved1[8];
+	u32 activate;
+	u32 devtodev;
+};
+check_member(rk3288_msch, devtodev, 0x003c);
+
+/* PCT_DFISTCFG0 */
+#define DFI_INIT_START			(1 << 0)
+
+/* PCT_DFISTCFG1 */
+#define DFI_DRAM_CLK_SR_EN		(1 << 0)
+#define DFI_DRAM_CLK_DPD_EN		(1 << 1)
+
+/* PCT_DFISTCFG2 */
+#define DFI_PARITY_INTR_EN		(1 << 0)
+#define DFI_PARITY_EN			(1 << 1)
+
+/* PCT_DFILPCFG0 */
+#define TLP_RESP_TIME_SHIFT		16
+#define LP_SR_EN			(1 << 8)
+#define LP_PD_EN			(1 << 0)
+
+/* PCT_DFITCTRLDELAY */
+#define TCTRL_DELAY_TIME_SHIFT		0
+
+/* PCT_DFITPHYWRDATA */
+#define TPHY_WRDATA_TIME_SHIFT		0
+
+/* PCT_DFITPHYRDLAT */
+#define TPHY_RDLAT_TIME_SHIFT		0
+
+/* PCT_DFITDRAMCLKDIS */
+#define TDRAM_CLK_DIS_TIME_SHIFT	0
+
+/* PCT_DFITDRAMCLKEN */
+#define TDRAM_CLK_EN_TIME_SHIFT		0
+
+/* PCTL_DFIODTCFG */
+#define RANK0_ODT_WRITE_SEL		(1 << 3)
+#define RANK1_ODT_WRITE_SEL		(1 << 11)
+
+/* PCTL_DFIODTCFG1 */
+#define ODT_LEN_BL8_W_SHIFT		16
+
+/* PUBL_ACDLLCR */
+#define ACDLLCR_DLLDIS			(1 << 31)
+#define ACDLLCR_DLLSRST			(1 << 30)
+
+/* PUBL_DXDLLCR */
+#define DXDLLCR_DLLDIS			(1 << 31)
+#define DXDLLCR_DLLSRST			(1 << 30)
+
+/* PUBL_DLLGCR */
+#define DLLGCR_SBIAS			(1 << 30)
+
+/* PUBL_DXGCR */
+#define DQSRTT				(1 << 9)
+#define DQRTT				(1 << 10)
+
+/* PIR */
+#define PIR_INIT			(1 << 0)
+#define PIR_DLLSRST			(1 << 1)
+#define PIR_DLLLOCK			(1 << 2)
+#define PIR_ZCAL			(1 << 3)
+#define PIR_ITMSRST			(1 << 4)
+#define PIR_DRAMRST			(1 << 5)
+#define PIR_DRAMINIT			(1 << 6)
+#define PIR_QSTRN			(1 << 7)
+#define PIR_RVTRN			(1 << 8)
+#define PIR_ICPC			(1 << 16)
+#define PIR_DLLBYP			(1 << 17)
+#define PIR_CTLDINIT			(1 << 18)
+#define PIR_CLRSR			(1 << 28)
+#define PIR_LOCKBYP			(1 << 29)
+#define PIR_ZCALBYP			(1 << 30)
+#define PIR_INITBYP			(1u << 31)
+
+/* PGCR */
+#define PGCR_DFTLMT_SHIFT		3
+#define PGCR_DFTCMP_SHIFT		2
+#define PGCR_DQSCFG_SHIFT		1
+#define PGCR_ITMDMD_SHIFT		0
+
+/* PGSR */
+#define PGSR_IDONE			(1 << 0)
+#define PGSR_DLDONE			(1 << 1)
+#define PGSR_ZCDONE			(1 << 2)
+#define PGSR_DIDONE			(1 << 3)
+#define PGSR_DTDONE			(1 << 4)
+#define PGSR_DTERR			(1 << 5)
+#define PGSR_DTIERR			(1 << 6)
+#define PGSR_DFTERR			(1 << 7)
+#define PGSR_RVERR			(1 << 8)
+#define PGSR_RVEIRR			(1 << 9)
+
+/* PTR0 */
+#define PRT_ITMSRST_SHIFT		18
+#define PRT_DLLLOCK_SHIFT		6
+#define PRT_DLLSRST_SHIFT		0
+
+/* PTR1 */
+#define PRT_DINIT0_SHIFT		0
+#define PRT_DINIT1_SHIFT		19
+
+/* PTR2 */
+#define PRT_DINIT2_SHIFT		0
+#define PRT_DINIT3_SHIFT		17
+
+/* DCR */
+#define DDRMD_LPDDR			0
+#define DDRMD_DDR			1
+#define DDRMD_DDR2			2
+#define DDRMD_DDR3			3
+#define DDRMD_LPDDR2_LPDDR3		4
+#define DDRMD_MASK			7
+#define DDRMD_SHIFT			0
+#define PDQ_MASK			7
+#define PDQ_SHIFT			4
+
+/* DXCCR */
+#define DQSNRES_MASK			0xf
+#define DQSNRES_SHIFT			8
+#define DQSRES_MASK			0xf
+#define DQSRES_SHIFT			4
+
+/* DTPR */
+#define TDQSCKMAX_SHIFT			27
+#define TDQSCKMAX_MASK			7
+#define TDQSCK_SHIFT			24
+#define TDQSCK_MASK			7
+
+/* DSGCR */
+#define DQSGX_SHIFT			5
+#define DQSGX_MASK			7
+#define DQSGE_SHIFT			8
+#define DQSGE_MASK			7
+
+/* SCTL */
+#define INIT_STATE			0
+#define CFG_STATE			1
+#define GO_STATE			2
+#define SLEEP_STATE			3
+#define WAKEUP_STATE			4
+
+/* STAT */
+#define LP_TRIG_SHIFT			4
+#define LP_TRIG_MASK			7
+#define PCTL_STAT_MSK			7
+#define INIT_MEM			0
+#define CONFIG				1
+#define CONFIG_REQ			2
+#define ACCESS				3
+#define ACCESS_REQ			4
+#define LOW_POWER			5
+#define LOW_POWER_ENTRY_REQ		6
+#define LOW_POWER_EXIT_REQ		7
+
+/* ZQCR*/
+#define PD_OUTPUT_SHIFT			0
+#define PU_OUTPUT_SHIFT			5
+#define PD_ONDIE_SHIFT			10
+#define PU_ONDIE_SHIFT			15
+#define ZDEN_SHIFT			28
+
+/* DDLGCR */
+#define SBIAS_BYPASS			(1 << 23)
+
+/* MCFG */
+#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT	24
+#define PD_IDLE_SHIFT			8
+#define MDDR_EN				(2 << 22)
+#define LPDDR2_EN			(3 << 22)
+#define DDR2_EN				(0 << 5)
+#define DDR3_EN				(1 << 5)
+#define LPDDR2_S2			(0 << 6)
+#define LPDDR2_S4			(1 << 6)
+#define MDDR_LPDDR2_BL_2		(0 << 20)
+#define MDDR_LPDDR2_BL_4		(1 << 20)
+#define MDDR_LPDDR2_BL_8		(2 << 20)
+#define MDDR_LPDDR2_BL_16		(3 << 20)
+#define DDR2_DDR3_BL_4			0
+#define DDR2_DDR3_BL_8			1
+#define TFAW_SHIFT			18
+#define PD_EXIT_SLOW			(0 << 17)
+#define PD_EXIT_FAST			(1 << 17)
+#define PD_TYPE_SHIFT			16
+#define BURSTLENGTH_SHIFT		20
+
+/* POWCTL */
+#define POWER_UP_START			(1 << 0)
+
+/* POWSTAT */
+#define POWER_UP_DONE			(1 << 0)
+
+/* MCMD */
+enum {
+	DESELECT_CMD			= 0,
+	PREA_CMD,
+	REF_CMD,
+	MRS_CMD,
+	ZQCS_CMD,
+	ZQCL_CMD,
+	RSTL_CMD,
+	MRR_CMD				= 8,
+	DPDE_CMD,
+};
+
+#define LPDDR2_MA_SHIFT			4
+#define LPDDR2_MA_MASK			0xff
+#define LPDDR2_OP_SHIFT			12
+#define LPDDR2_OP_MASK			0xff
+
+#define START_CMD			(1u << 31)
+
+/*
+ * DDRCONF
+ * [5:4] row(13+n)
+ * [1:0] col(9+n), assume bw=2
+ */
+#define DDRCONF_ROW_SHIFT		4
+#define DDRCONF_COL_SHIFT		0
+
+/* DEVTODEV */
+#define BUSWRTORD_SHIFT			4
+#define BUSRDTOWR_SHIFT			2
+#define BUSRDTORD_SHIFT			0
+
+/* mr1 for ddr3 */
+#define DDR3_DLL_DISABLE		1
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
new file mode 100644
index 0000000..82234cf
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef __ASM_ARCH_DDR_RK3368_H__
+#define __ASM_ARCH_DDR_RK3368_H__
+
+/*
+ * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
+ * in a few details. Most notably, it has an additional field to track
+ * tREFI in controller cycles (i.e. trefi_mem_ddr3).
+ */
+struct rk3368_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 trefi_mem_ddr3;
+	u32 reserved5[45];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3368_ddr_pctl, iptr, 0x03fc);
+
+struct rk3368_ddrphy {
+	u32 reg[0x100];
+};
+check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
+
+struct rk3368_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 reserved1[8];
+	u32 activate;
+	u32 devtodev;
+};
+check_member(rk3368_msch, devtodev, 0x003c);
+
+/* GRF_SOC_CON0 */
+enum {
+	NOC_RSP_ERR_STALL = BIT(9),
+	MOBILE_DDR_SEL = BIT(4),
+	DDR0_16BIT_EN = BIT(3),
+	MSCH0_MAINDDR3_DDR3 = BIT(2),
+	MSCH0_MAINPARTIALPOP = BIT(1),
+	UPCTL_C_ACTIVE = BIT(0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
new file mode 100644
index 0000000..105a335
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
@@ -0,0 +1,635 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_EDP_H
+#define _ASM_ARCH_EDP_H
+
+struct rk3288_edp {
+	u8	res0[0x10];
+	u32	dp_tx_version;
+	u8	res1[0x4];
+	u32	func_en_1;
+	u32	func_en_2;
+	u32	video_ctl_1;
+	u32	video_ctl_2;
+	u32	video_ctl_3;
+	u32	video_ctl_4;
+	u8	res2[0xc];
+	u32	video_ctl_8;
+	u8	res3[0x4];
+	u32	video_ctl_10;
+	u32	total_line_l;
+	u32	total_line_h;
+	u32	active_line_l;
+	u32	active_line_h;
+	u32	v_f_porch;
+	u32	vsync;
+	u32	v_b_porch;
+	u32	total_pixel_l;
+	u32	total_pixel_h;
+	u32	active_pixel_l;
+	u32	active_pixel_h;
+	u32	h_f_porch_l;
+	u32	h_f_porch_h;
+	u32	hsync_l;
+	u32	hysnc_h;
+	u32	h_b_porch_l;
+	u32	h_b_porch_h;
+	u32	vid_status;
+	u32	total_line_sta_l;
+	u32	total_line_sta_h;
+	u32	active_line_sta_l;
+	u32	active_line_sta_h;
+	u32	v_f_porch_sta;
+	u32	vsync_sta;
+	u32	v_b_porch_sta;
+	u32	total_pixel_sta_l;
+	u32	total_pixel_sta_h;
+	u32	active_pixel_sta_l;
+	u32	active_pixel_sta_h;
+	u32	h_f_porch_sta_l;
+	u32	h_f_porch_sta_h;
+	u32	hsync_sta_l;
+	u32	hsync_sta_h;
+	u32	h_b_porch_sta_l;
+	u32	h_b_porch__sta_h;
+	u8      res4[0x28];
+	u32	pll_reg_1;
+	u8	res5[4];
+	u32	ssc_reg;
+	u8	res6[0xc];
+	u32	tx_common;
+	u32	tx_common2;
+	u8	res7[0x4];
+	u32	dp_aux;
+	u32	dp_bias;
+	u32	dp_test;
+	u32	dp_pd;
+	u32	dp_reserv1;
+	u32	dp_reserv2;
+	u8	res8[0x224];
+	u32	lane_map;
+	u8	res9[0x14];
+	u32	analog_ctl_2;
+	u8	res10[0x48];
+	u32	int_state;
+	u32	common_int_sta_1;
+	u32	common_int_sta_2;
+	u32	common_int_sta_3;
+	u32	common_int_sta_4;
+	u32	spdif_biphase_int_sta;
+	u8	res11[0x4];
+	u32	dp_int_sta;
+	u32	common_int_mask_1;
+	u32	common_int_mask_2;
+	u32	common_int_mask_3;
+	u32	common_int_mask_4;
+	u8	res12[0x08];
+	u32	int_sta_mask;
+	u32	int_ctl;
+	u8	res13[0x200];
+	u32	sys_ctl_1;
+	u32	sys_ctl_2;
+	u32	sys_ctl_3;
+	u32	sys_ctl_4;
+	u32	dp_vid_ctl;
+	u8	res14[0x4];
+	u32	dp_aud_ctl;
+	u8	res15[0x24];
+	u32	pkt_send_ctl;
+	u8	res16[0x4];
+	u32	dp_hdcp_ctl;
+	u8	res17[0x34];
+	u32	link_bw_set;
+	u32	lane_count_set;
+	u32	dp_training_ptn_set;
+	u32	ln_link_trn_ctl[4];
+	u8	res18[0x4];
+	u32	dp_hw_link_training;
+	u8	res19[0x1c];
+	u32	dp_debug_ctl;
+	u32	hpd_deglitch_l;
+	u32	hpd_deglitch_h;
+	u8	res20[0x14];
+	u32	dp_link_debug_ctl;
+	u8	res21[0x1c];
+	u32	m_vid_0;
+	u32	m_vid_1;
+	u32	m_vid_2;
+	u32	n_vid_0;
+	u32	n_vid_1;
+	u32	n_vid_2;
+	u32	m_vid_mon;
+	u8	res22[0x14];
+	u32	dp_video_fifo_thrd;
+	u8	res23[0x8];
+	u32	dp_audio_margin;
+	u8	res24[0x20];
+	u32	dp_m_cal_ctl;
+	u32	m_vid_gen_filter_th;
+	u8	res25[0x10];
+	u32	m_aud_gen_filter_th;
+	u8	res26[0x4];
+	u32	aux_ch_sta;
+	u32	aux_err_num;
+	u32	aux_ch_defer_dtl;
+	u32	aux_rx_comm;
+	u32	buf_data_ctl;
+	u32	aux_ch_ctl_1;
+	u32	aux_addr_7_0;
+	u32	aux_addr_15_8;
+	u32	aux_addr_19_16;
+	u32	aux_ch_ctl_2;
+	u8	res27[0x18];
+	u32	buf_data[16];
+	u32	soc_general_ctl;
+	u8	res29[0x1e0];
+	u32	pll_reg_2;
+	u32	pll_reg_3;
+	u32	pll_reg_4;
+	u8	res30[0x10];
+	u32	pll_reg_5;
+};
+check_member(rk3288_edp, pll_reg_5, 0xa00);
+
+/* func_en_1 */
+#define VID_CAP_FUNC_EN_N			(0x1 << 6)
+#define VID_FIFO_FUNC_EN_N			(0x1 << 5)
+#define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
+#define AUD_FUNC_EN_N				(0x1 << 3)
+#define HDCP_FUNC_EN_N				(0x1 << 2)
+#define SW_FUNC_EN_N				(0x1 << 0)
+
+/* func_en_2 */
+#define SSC_FUNC_EN_N				(0x1 << 7)
+#define AUX_FUNC_EN_N				(0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
+
+/* video_ctl_1 */
+#define VIDEO_EN				(0x1 << 7)
+#define VIDEO_MUTE				(0x1 << 6)
+
+/* video_ctl_2 */
+#define IN_D_RANGE_MASK				(0x1 << 7)
+#define IN_D_RANGE_SHIFT			(7)
+#define IN_D_RANGE_CEA				(0x1 << 7)
+#define IN_D_RANGE_VESA				(0x0 << 7)
+#define IN_BPC_MASK				(0x7 << 4)
+#define IN_BPC_SHIFT				(4)
+#define IN_BPC_12_BITS				(0x3 << 4)
+#define IN_BPC_10_BITS				(0x2 << 4)
+#define IN_BPC_8_BITS				(0x1 << 4)
+#define IN_BPC_6_BITS				(0x0 << 4)
+#define IN_COLOR_F_MASK				(0x3 << 0)
+#define IN_COLOR_F_SHIFT			(0)
+#define IN_COLOR_F_YCBCR444			(0x2 << 0)
+#define IN_COLOR_F_YCBCR422			(0x1 << 0)
+#define IN_COLOR_F_RGB				(0x0 << 0)
+
+/* video_ctl_3 */
+#define IN_YC_COEFFI_MASK			(0x1 << 7)
+#define IN_YC_COEFFI_SHIFT			(7)
+#define IN_YC_COEFFI_ITU709			(0x1 << 7)
+#define IN_YC_COEFFI_ITU601			(0x0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK		(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT		(4)
+#define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
+
+/* video_ctl_4 */
+#define BIST_EN					(0x1 << 3)
+#define BIST_WH_64				(0x1 << 2)
+#define BIST_WH_32				(0x0 << 2)
+#define BIST_TYPE_COLR_BAR			(0x0 << 0)
+#define BIST_TYPE_GRAY_BAR			(0x1 << 0)
+#define BIST_TYPE_MOBILE_BAR			(0x2 << 0)
+
+/* video_ctl_8 */
+#define VID_HRES_TH(x)				(((x) & 0xf) << 4)
+#define VID_VRES_TH(x)				(((x) & 0xf) << 0)
+
+/* video_ctl_10 */
+#define F_SEL					(0x1 << 4)
+#define INTERACE_SCAN_CFG			(0x1 << 2)
+#define INTERACD_SCAN_CFG_OFFSET		2
+#define VSYNC_POLARITY_CFG			(0x1 << 1)
+#define VSYNC_POLARITY_CFG_OFFSET		1
+#define HSYNC_POLARITY_CFG			(0x1 << 0)
+#define HSYNC_POLARITY_CFG_OFFSET		0
+
+/* dp_pd */
+#define PD_INC_BG				(0x1 << 7)
+#define PD_EXP_BG				(0x1 << 6)
+#define PD_AUX					(0x1 << 5)
+#define PD_PLL					(0x1 << 4)
+#define PD_CH3					(0x1 << 3)
+#define PD_CH2					(0x1 << 2)
+#define PD_CH1					(0x1 << 1)
+#define PD_CH0					(0x1 << 0)
+
+/* pll_reg_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
+/* line_map */
+#define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
+#define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
+#define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
+#define LANE3_MAP_LOGIC_LANE_3			(0x3 << 6)
+#define LANE2_MAP_LOGIC_LANE_0			(0x0 << 4)
+#define LANE2_MAP_LOGIC_LANE_1			(0x1 << 4)
+#define LANE2_MAP_LOGIC_LANE_2			(0x2 << 4)
+#define LANE2_MAP_LOGIC_LANE_3			(0x3 << 4)
+#define LANE1_MAP_LOGIC_LANE_0			(0x0 << 2)
+#define LANE1_MAP_LOGIC_LANE_1			(0x1 << 2)
+#define LANE1_MAP_LOGIC_LANE_2			(0x2 << 2)
+#define LANE1_MAP_LOGIC_LANE_3			(0x3 << 2)
+#define LANE0_MAP_LOGIC_LANE_0			(0x0 << 0)
+#define LANE0_MAP_LOGIC_LANE_1			(0x1 << 0)
+#define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
+#define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
+
+/* analog_ctl_2 */
+#define SEL_24M					(0x1 << 3)
+
+/* common_int_sta_1 */
+#define VSYNC_DET				(0x1 << 7)
+#define PLL_LOCK_CHG				(0x1 << 6)
+#define SPDIF_ERR				(0x1 << 5)
+#define SPDIF_UNSTBL				(0x1 << 4)
+#define VID_FORMAT_CHG				(0x1 << 3)
+#define AUD_CLK_CHG				(0x1 << 2)
+#define VID_CLK_CHG				(0x1 << 1)
+#define SW_INT					(0x1 << 0)
+
+/* common_int_sta_2 */
+#define ENC_EN_CHG				(0x1 << 6)
+#define HW_BKSV_RDY				(0x1 << 3)
+#define HW_SHA_DONE				(0x1 << 2)
+#define HW_AUTH_STATE_CHG			(0x1 << 1)
+#define HW_AUTH_DONE				(0x1 << 0)
+
+/* common_int_sta_3 */
+#define AFIFO_UNDER				(0x1 << 7)
+#define AFIFO_OVER				(0x1 << 6)
+#define R0_CHK_FLAG				(0x1 << 5)
+
+/* common_int_sta_4 */
+#define PSR_ACTIVE				(0x1 << 7)
+#define PSR_INACTIVE				(0x1 << 6)
+#define SPDIF_BI_PHASE_ERR			(0x1 << 5)
+#define HOTPLUG_CHG				(0x1 << 2)
+#define HPD_LOST				(0x1 << 1)
+#define PLUG					(0x1 << 0)
+
+/* dp_int_sta */
+#define INT_HPD					(0x1 << 6)
+#define HW_LT_DONE				(0x1 << 5)
+#define SINK_LOST				(0x1 << 3)
+#define LINK_LOST				(0x1 << 2)
+#define RPLY_RECEIV				(0x1 << 1)
+#define AUX_ERR					(0x1 << 0)
+
+/* int_ctl */
+#define SOFT_INT_CTRL				(0x1 << 2)
+#define INT_POL					(0x1 << 0)
+
+/* sys_ctl_1 */
+#define DET_STA					(0x1 << 2)
+#define FORCE_DET				(0x1 << 1)
+#define DET_CTRL				(0x1 << 0)
+
+/* sys_ctl_2 */
+#define CHA_CRI(x)				(((x) & 0xf) << 4)
+#define CHA_STA					(0x1 << 2)
+#define FORCE_CHA				(0x1 << 1)
+#define CHA_CTRL				(0x1 << 0)
+
+/* sys_ctl_3 */
+#define HPD_STATUS				(0x1 << 6)
+#define F_HPD					(0x1 << 5)
+#define HPD_CTRL				(0x1 << 4)
+#define HDCP_RDY				(0x1 << 3)
+#define STRM_VALID				(0x1 << 2)
+#define F_VALID					(0x1 << 1)
+#define VALID_CTRL				(0x1 << 0)
+
+/* sys_ctl_4 */
+#define FIX_M_AUD				(0x1 << 4)
+#define ENHANCED				(0x1 << 3)
+#define FIX_M_VID				(0x1 << 2)
+#define M_VID_UPDATE_CTRL			(0x3 << 0)
+
+/* pll_reg_2 */
+#define LDO_OUTPUT_V_SEL_145			(2 << 6)
+#define KVCO_DEFALUT				(1 << 4)
+#define CHG_PUMP_CUR_SEL_5US			(1 << 2)
+#define V2L_CUR_SEL_1MA				(1 << 0)
+
+/* pll_reg_3 */
+#define LOCK_DET_CNT_SEL_256			(2 << 5)
+#define LOOP_FILTER_RESET			(0 << 4)
+#define PALL_SSC_RESET				(0 << 3)
+#define LOCK_DET_BYPASS				(0 << 2)
+#define PLL_LOCK_DET_MODE			(0 << 1)
+#define PLL_LOCK_DET_FORCE			(0 << 0)
+
+/* pll_reg_5 */
+#define REGULATOR_V_SEL_950MV			(2 << 4)
+#define STANDBY_CUR_SEL				(0 << 3)
+#define CHG_PUMP_INOUT_CTRL_1200MV		(1 << 1)
+#define CHG_PUMP_INPUT_CTRL_OP			(0 << 0)
+
+/* ssc_reg */
+#define SSC_OFFSET				(0 << 6)
+#define SSC_MODE				(1 << 4)
+#define SSC_DEPTH				(9 << 0)
+
+/* tx_common */
+#define TX_SWING_PRE_EMP_MODE			(1 << 7)
+#define PRE_DRIVER_PW_CTRL1			(0 << 5)
+#define LP_MODE_CLK_REGULATOR			(0 << 4)
+#define RESISTOR_MSB_CTRL			(0 << 3)
+#define RESISTOR_CTRL				(7 << 0)
+
+/* dp_aux */
+#define DP_AUX_COMMON_MODE			(0 << 4)
+#define DP_AUX_EN				(0 << 3)
+#define AUX_TERM_50OHM				(3 << 0)
+
+/* dp_bias */
+#define DP_BG_OUT_SEL				(4 << 4)
+#define DP_DB_CUR_CTRL				(0 << 3)
+#define DP_BG_SEL				(1 << 2)
+#define DP_RESISTOR_TUNE_BG			(2 << 0)
+
+/* dp_reserv2 */
+#define CH1_CH3_SWING_EMP_CTRL			(5 << 4)
+#define CH0_CH2_SWING_EMP_CTRL			(5 << 0)
+
+/* dp_training_ptn_set */
+#define SCRAMBLING_DISABLE			(0x1 << 5)
+#define SCRAMBLING_ENABLE			(0x0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK		(0x7 << 2)
+#define LINK_QUAL_PATTERN_SET_HBR2		(0x5 << 2)
+#define LINK_QUAL_PATTERN_SET_80BIT		(0x4 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
+#define SW_TRAINING_PATTERN_SET_DISABLE		(0x0 << 0)
+
+/* dp_hw_link_training_ctl */
+#define HW_LT_ERR_CODE_MASK			0x70
+#define HW_LT_ERR_CODE_SHIFT			4
+#define HW_LT_EN				(0x1 << 0)
+
+/* dp_debug_ctl */
+#define PLL_LOCK				(0x1 << 4)
+#define F_PLL_LOCK				(0x1 << 3)
+#define PLL_LOCK_CTRL				(0x1 << 2)
+#define POLL_EN					(0x1 << 1)
+#define PN_INV					(0x1 << 0)
+
+/* aux_ch_sta */
+#define AUX_BUSY				(0x1 << 4)
+#define AUX_STATUS_MASK				(0xf << 0)
+
+/* aux_ch_defer_ctl */
+#define DEFER_CTRL_EN				(0x1 << 7)
+#define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
+
+/* aux_rx_comm */
+#define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
+#define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
+
+/* buffer_data_ctl */
+#define BUF_CLR					(0x1 << 7)
+#define BUF_HAVE_DATA				(0x1 << 4)
+#define BUF_DATA_COUNT(x)			(((x) & 0xf) << 0)
+
+/* aux_ch_ctl_1 */
+#define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
+#define AUX_TX_COMM_MASK			(0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION		(0x0 << 3)
+#define AUX_TX_COMM_MOT				(0x1 << 2)
+#define AUX_TX_COMM_WRITE			(0x0 << 0)
+#define AUX_TX_COMM_READ			(0x1 << 0)
+
+/* aux_ch_ctl_2 */
+#define PD_AUX_IDLE				(0x1 << 3)
+#define ADDR_ONLY				(0x1 << 1)
+#define AUX_EN					(0x1 << 0)
+
+/* tx_sw_reset */
+#define RST_DP_TX				(0x1 << 0)
+
+/* analog_ctl_1 */
+#define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
+
+/* analog_ctl_3 */
+#define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
+#define VCO_BIT_600_MICRO			(0x5 << 0)
+
+/* pll_filter_ctl_1 */
+#define PD_RING_OSC				(0x1 << 6)
+#define AUX_TERMINAL_CTRL_37_5_OHM		(0x0 << 4)
+#define AUX_TERMINAL_CTRL_45_OHM		(0x1 << 4)
+#define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
+#define AUX_TERMINAL_CTRL_65_OHM		(0x3 << 4)
+#define TX_CUR1_2X				(0x1 << 2)
+#define TX_CUR_16_MA				(0x3 << 0)
+
+/* Definition for DPCD Register */
+#define DPCD_DPCD_REV				(0x0000)
+#define DPCD_MAX_LINK_RATE			(0x0001)
+#define DPCD_MAX_LANE_COUNT			(0x0002)
+#define DP_MAX_LANE_COUNT_MASK			0x1f
+#define DP_TPS3_SUPPORTED			(1 << 6)
+#define DP_ENHANCED_FRAME_CAP			(1 << 7)
+
+#define DPCD_LINK_BW_SET			(0x0100)
+#define DPCD_LANE_COUNT_SET			(0x0101)
+
+#define DPCD_TRAINING_PATTERN_SET		(0x0102)
+#define DP_TRAINING_PATTERN_DISABLE		0
+#define DP_TRAINING_PATTERN_1			1
+#define DP_TRAINING_PATTERN_2			2
+#define DP_TRAINING_PATTERN_3			3
+#define DP_TRAINING_PATTERN_MASK		0x3
+
+#define DPCD_TRAINING_LANE0_SET			(0x0103)
+#define DP_TRAIN_VOLTAGE_SWING_MASK		0x3
+#define DP_TRAIN_VOLTAGE_SWING_SHIFT		0
+#define DP_TRAIN_MAX_SWING_REACHED		(1 << 2)
+#define DP_TRAIN_VOLTAGE_SWING_400		(0 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_600		(1 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_800		(2 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_1200		(3 << 0)
+
+#define DP_TRAIN_PRE_EMPHASIS_MASK		(3 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_0			(0 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_3_5		(1 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_6			(2 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_9_5		(3 << 3)
+
+#define DP_TRAIN_PRE_EMPHASIS_SHIFT		3
+#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED	(1 << 5)
+
+#define DPCD_LANE0_1_STATUS			(0x0202)
+#define DPCD_LANE2_3_STATUS			(0x0203)
+#define DP_LANE_CR_DONE				(1 << 0)
+#define DP_LANE_CHANNEL_EQ_DONE			(1 << 1)
+#define DP_LANE_SYMBOL_LOCKED			(1 << 2)
+#define DP_CHANNEL_EQ_BITS			(DP_LANE_CR_DONE |\
+						DP_LANE_CHANNEL_EQ_DONE |\
+						DP_LANE_SYMBOL_LOCKED)
+
+#define DPCD_LANE_ALIGN_STATUS_UPDATED		(0x0204)
+#define DP_INTERLANE_ALIGN_DONE			(1 << 0)
+#define DP_DOWNSTREAM_PORT_STATUS_CHANGED	(1 << 6)
+#define DP_LINK_STATUS_UPDATED			(1 << 7)
+
+#define DPCD_ADJUST_REQUEST_LANE0_1		(0x0206)
+#define DPCD_ADJUST_REQUEST_LANE2_3		(0x0207)
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK	0x03
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT	0
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK	0x0c
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT	2
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK	0x30
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT	4
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK	0xc0
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT	6
+
+#define DPCD_TEST_REQUEST			(0x0218)
+#define DPCD_TEST_RESPONSE			(0x0260)
+#define DPCD_TEST_EDID_CHECKSUM			(0x0261)
+#define DPCD_LINK_POWER_STATE			(0x0600)
+#define DP_SET_POWER_D0				0x1
+#define DP_SET_POWER_D3				0x2
+#define DP_SET_POWER_MASK			0x3
+
+#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
+#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
+#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
+
+#define STREAM_ON_TIMEOUT 100
+#define PLL_LOCK_TIMEOUT 10
+#define DP_INIT_TRIES 10
+
+#define EDID_ADDR				0x50
+#define EDID_LENGTH				0x80
+#define EDID_HEADER				0x00
+#define EDID_EXTENSION_FLAG			0x7e
+
+
+enum dpcd_request {
+	DPCD_READ,
+	DPCD_WRITE,
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	CS_RGB,
+	CS_YCBCR422,
+	CS_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_CNT1 = 1,
+	LANE_CNT2 = 2,
+	LANE_CNT4 = 4
+};
+
+enum link_training_state {
+	LT_START,
+	LT_CLK_RECOVERY,
+	LT_EQ_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+struct link_train {
+	unsigned char revision;
+	u8 link_rate;
+	u8 lane_count;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
new file mode 100644
index 0000000..9772321
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ *
+ * Eddie Cai <eddie.cai.linux@gmail.com>
+ */
+
+#ifndef _F_ROCKUSB_H_
+#define _F_ROCKUSB_H_
+#include <blk.h>
+
+#define ROCKUSB_VERSION		"0.1"
+
+#define ROCKUSB_INTERFACE_CLASS	0xff
+#define ROCKUSB_INTERFACE_SUB_CLASS	0x06
+#define ROCKUSB_INTERFACE_PROTOCOL	0x05
+
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0  0x0200
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1  0x0040
+#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE      0x0040
+
+#define EP_BUFFER_SIZE			4096
+/*
+ * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size
+ * (64 or 512 or 1024), else we break on certain controllers like DWC3
+ * that expect bulk OUT requests to be divisible by maxpacket size.
+ */
+
+#define RKUSB_BUF_SIZE		EP_BUFFER_SIZE * 2
+#define RKBLOCK_BUF_SIZE		4096
+
+#define RKUSB_STATUS_IDLE			0
+#define RKUSB_STATUS_CMD			1
+#define RKUSB_STATUS_RXDATA			2
+#define RKUSB_STATUS_TXDATA			3
+#define RKUSB_STATUS_CSW			4
+#define RKUSB_STATUS_RXDATA_PREPARE		5
+#define RKUSB_STATUS_TXDATA_PREPARE		6
+
+enum rkusb_command {
+K_FW_TEST_UNIT_READY	= 0x00,
+K_FW_READ_FLASH_ID = 0x01,
+K_FW_SET_DEVICE_ID = 0x02,
+K_FW_TEST_BAD_BLOCK = 0x03,
+K_FW_READ_10 = 0x04,
+K_FW_WRITE_10 = 0x05,
+K_FW_ERASE_10 = 0x06,
+K_FW_WRITE_SPARE = 0x07,
+K_FW_READ_SPARE = 0x08,
+
+K_FW_ERASE_10_FORCE = 0x0b,
+K_FW_GET_VERSION = 0x0c,
+
+K_FW_LBA_READ_10 = 0x14,
+K_FW_LBA_WRITE_10 = 0x15,
+K_FW_ERASE_SYS_DISK = 0x16,
+K_FW_SDRAM_READ_10 = 0x17,
+K_FW_SDRAM_WRITE_10 = 0x18,
+K_FW_SDRAM_EXECUTE = 0x19,
+K_FW_READ_FLASH_INFO = 0x1A,
+K_FW_GET_CHIP_VER = 0x1B,
+K_FW_LOW_FORMAT = 0x1C,
+K_FW_SET_RESET_FLAG = 0x1E,
+K_FW_SPI_READ_10 = 0x21,
+K_FW_SPI_WRITE_10 = 0x22,
+K_FW_LBA_ERASE_10 = 0x25,
+
+K_FW_SESSION = 0X30,
+K_FW_RESET = 0xff,
+};
+
+#define CBW_DIRECTION_OUT		0x00
+#define CBW_DIRECTION_IN		0x80
+
+struct cmd_dispatch_info {
+	enum rkusb_command cmd;
+	/* call back function to handle rockusb command */
+	void (*cb)(struct usb_ep *ep, struct usb_request *req);
+};
+
+/* Bulk-only data structures */
+
+/* Command Block Wrapper */
+struct fsg_bulk_cb_wrap {
+	__le32  signature;              /* Contains 'USBC' */
+	u32     tag;                    /* Unique per command id */
+	__le32  data_transfer_length;   /* Size of the data */
+	u8      flags;                  /* Direction in bit 7 */
+	u8      lun;                    /* lun (normally 0) */
+	u8      length;                 /* Of the CDB, <= MAX_COMMAND_SIZE */
+	u8      CDB[16];                /* Command Data Block */
+};
+
+#define USB_BULK_CB_WRAP_LEN    31
+#define USB_BULK_CB_SIG         0x43425355      /* Spells out USBC */
+#define USB_BULK_IN_FLAG        0x80
+
+/* Command status Wrapper */
+struct bulk_cs_wrap {
+	__le32  signature;              /* Should = 'USBS' */
+	u32     tag;                    /* Same as original command */
+	__le32  residue;                /* Amount not transferred */
+	u8      status;                 /* See below */
+};
+
+#define USB_BULK_CS_WRAP_LEN    13
+#define USB_BULK_CS_SIG         0x53425355      /* Spells out 'USBS' */
+#define USB_STATUS_PASS         0
+#define USB_STATUS_FAIL         1
+#define USB_STATUS_PHASE_ERROR  2
+
+#define CSW_GOOD                0x00
+#define CSW_FAIL                0x01
+
+struct f_rockusb {
+	struct usb_function usb_function;
+	struct usb_ep *in_ep, *out_ep;
+	struct usb_request *in_req, *out_req;
+	char *dev_type;
+	unsigned int dev_index;
+	unsigned int tag;
+	unsigned int lba;
+	unsigned int dl_size;
+	unsigned int dl_bytes;
+	unsigned int ul_size;
+	unsigned int ul_bytes;
+	struct blk_desc *desc;
+	int reboot_flag;
+	void *buf;
+	void *buf_head;
+};
+
+/* init rockusb device, tell rockusb which device you want to read/write*/
+void rockusb_dev_init(char *dev_type, int dev_index);
+#endif /* _F_ROCKUSB_H_ */
+
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
new file mode 100644
index 0000000..1aaec5f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+struct rockchip_gpio_regs {
+	u32 swport_dr;
+	u32 swport_ddr;
+	u32 reserved0[(0x30 - 0x08) / 4];
+	u32 inten;
+	u32 intmask;
+	u32 inttype_level;
+	u32 int_polarity;
+	u32 int_status;
+	u32 int_rawstatus;
+	u32 debounce;
+	u32 porta_eoi;
+	u32 ext_port;
+	u32 reserved1[(0x60 - 0x54) / 4];
+	u32 ls_sync;
+};
+check_member(rockchip_gpio_regs, ls_sync, 0x60);
+
+enum gpio_pu_pd {
+	GPIO_PULL_NORMAL = 0,
+	GPIO_PULL_UP,
+	GPIO_PULL_DOWN,
+	GPIO_PULL_REPEAT,
+};
+
+/* These defines are only used by spl_gpio.h */
+enum {
+	/* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */
+	GPIO_BANK_SHIFT		= 3,
+	GPIO_BANK_MASK		= 3 << GPIO_BANK_SHIFT,
+
+	GPIO_OFFSET_MASK	= 0x1f,
+};
+
+#define GPIO(bank, offset)	((bank) << GPIO_BANK_SHIFT | (offset))
+
+enum gpio_bank_t {
+	BANK_A = 0,
+	BANK_B,
+	BANK_C,
+	BANK_D,
+};
+
+enum gpio_dir_t {
+	GPIO_INPUT = 0,
+	GPIO_OUTPUT,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
new file mode 100644
index 0000000..5f12ebf
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_GRF_RK3036_H
+#define _ASM_ARCH_GRF_RK3036_H
+
+#include <common.h>
+
+struct rk3036_grf {
+	unsigned int reserved[0x2a];
+	unsigned int gpio0a_iomux;
+	unsigned int gpio0b_iomux;
+	unsigned int gpio0c_iomux;
+	unsigned int gpio0d_iomux;
+
+	unsigned int gpio1a_iomux;
+	unsigned int gpio1b_iomux;
+	unsigned int gpio1c_iomux;
+	unsigned int gpio1d_iomux;
+
+	unsigned int gpio2a_iomux;
+	unsigned int gpio2b_iomux;
+	unsigned int gpio2c_iomux;
+	unsigned int gpio2d_iomux;
+
+	unsigned int reserved2[0x0a];
+	unsigned int gpiods;
+	unsigned int reserved3[0x05];
+	unsigned int gpio0l_pull;
+	unsigned int gpio0h_pull;
+	unsigned int gpio1l_pull;
+	unsigned int gpio1h_pull;
+	unsigned int gpio2l_pull;
+	unsigned int gpio2h_pull;
+	unsigned int reserved4[4];
+	unsigned int soc_con0;
+	unsigned int soc_con1;
+	unsigned int soc_con2;
+	unsigned int soc_status0;
+	unsigned int reserved5;
+	unsigned int soc_con3;
+	unsigned int reserved6;
+	unsigned int dmac_con0;
+	unsigned int dmac_con1;
+	unsigned int dmac_con2;
+	unsigned int reserved7[5];
+	unsigned int uoc0_con5;
+	unsigned int reserved8[4];
+	unsigned int uoc1_con4;
+	unsigned int uoc1_con5;
+	unsigned int reserved9;
+	unsigned int ddrc_stat;
+	unsigned int uoc_con6;
+	unsigned int soc_status1;
+	unsigned int cpu_con0;
+	unsigned int cpu_con1;
+	unsigned int cpu_con2;
+	unsigned int cpu_con3;
+	unsigned int reserved10;
+	unsigned int reserved11;
+	unsigned int cpu_status0;
+	unsigned int cpu_status1;
+	unsigned int os_reg[8];
+	unsigned int reserved12[6];
+	unsigned int dll_con[4];
+	unsigned int dll_status[4];
+	unsigned int dfi_wrnum;
+	unsigned int dfi_rdnum;
+	unsigned int dfi_actnum;
+	unsigned int dfi_timerval;
+	unsigned int nfi_fifo[4];
+	unsigned int reserved13[0x10];
+	unsigned int usbphy0_con[8];
+	unsigned int usbphy1_con[8];
+	unsigned int reserved14[0x10];
+	unsigned int chip_tag;
+	unsigned int sdmmc_det_cnt;
+};
+check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
new file mode 100644
index 0000000..519b36a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
@@ -0,0 +1,550 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_GRF_RK3128_H
+#define _ASM_ARCH_GRF_RK3128_H
+
+#include <common.h>
+
+struct rk3128_grf {
+	unsigned int reserved[0x2a];
+	unsigned int gpio0a_iomux;
+	unsigned int gpio0b_iomux;
+	unsigned int gpio0c_iomux;
+	unsigned int gpio0d_iomux;
+	unsigned int gpio1a_iomux;
+	unsigned int gpio1b_iomux;
+	unsigned int gpio1c_iomux;
+	unsigned int gpio1d_iomux;
+	unsigned int gpio2a_iomux;
+	unsigned int gpio2b_iomux;
+	unsigned int gpio2c_iomux;
+	unsigned int gpio2d_iomux;
+	unsigned int gpio3a_iomux;
+	unsigned int gpio3b_iomux;
+	unsigned int gpio3c_iomux;
+	unsigned int gpio3d_iomux;
+	unsigned int gpio2c_iomux2;
+	unsigned int grf_cif_iomux;
+	unsigned int grf_cif_iomux1;
+	unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
+	unsigned int gpio0l_pull;
+	unsigned int gpio0h_pull;
+	unsigned int gpio1l_pull;
+	unsigned int gpio1h_pull;
+	unsigned int gpio2l_pull;
+	unsigned int gpio2h_pull;
+	unsigned int gpio3l_pull;
+	unsigned int gpio3h_pull;
+	unsigned int reserved2;
+	unsigned int soc_con0;
+	unsigned int soc_con1;
+	unsigned int soc_con2;
+	unsigned int soc_status0;
+	unsigned int reserved3[6];
+	unsigned int mac_con0;
+	unsigned int mac_con1;
+	unsigned int reserved4[4];
+	unsigned int uoc0_con0;
+	unsigned int reserved5;
+	unsigned int uoc1_con1;
+	unsigned int uoc1_con2;
+	unsigned int uoc1_con3;
+	unsigned int uoc1_con4;
+	unsigned int uoc1_con5;
+	unsigned int reserved6;
+	unsigned int ddrc_stat;
+	unsigned int reserved9;
+	unsigned int soc_status1;
+	unsigned int cpu_con0;
+	unsigned int cpu_con1;
+	unsigned int cpu_con2;
+	unsigned int cpu_con3;
+	unsigned int reserved10;
+	unsigned int reserved11;
+	unsigned int cpu_status0;
+	unsigned int cpu_status1;
+	unsigned int os_reg[8];
+	unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
+	unsigned int usbphy0_con[8];
+	unsigned int usbphy1_con[8];
+	unsigned int uoc_status0;
+	unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
+	unsigned int chip_tag;
+	unsigned int sdmmc_det_cnt;
+};
+check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
+
+struct rk3128_pmu {
+	unsigned int wakeup_cfg;
+	unsigned int pwrdn_con;
+	unsigned int pwrdn_st;
+	unsigned int idle_req;
+	unsigned int idle_st;
+	unsigned int pwrmode_con;
+	unsigned int pwr_state;
+	unsigned int osc_cnt;
+	unsigned int core_pwrdwn_cnt;
+	unsigned int core_pwrup_cnt;
+	unsigned int sft_con;
+	unsigned int ddr_sref_st;
+	unsigned int int_con;
+	unsigned int int_st;
+	unsigned int sys_reg[4];
+};
+check_member(rk3128_pmu, int_st, 0x34);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+	GPIO0A7_SHIFT		= 14,
+	GPIO0A7_MASK		= 3 << GPIO0A7_SHIFT,
+	GPIO0A7_GPIO		= 0,
+	GPIO0A7_I2C3_SDA,
+
+	GPIO0A6_SHIFT		= 12,
+	GPIO0A6_MASK		= 3 << GPIO0A6_SHIFT,
+	GPIO0A6_GPIO		= 0,
+	GPIO0A6_I2C3_SCL,
+
+	GPIO0A3_SHIFT		= 6,
+	GPIO0A3_MASK		= 3 << GPIO0A3_SHIFT,
+	GPIO0A3_GPIO		= 0,
+	GPIO0A3_I2C1_SDA,
+
+	GPIO0A2_SHIFT		= 4,
+	GPIO0A2_MASK		= 1 << GPIO0A2_SHIFT,
+	GPIO0A2_GPIO		= 0,
+	GPIO0A2_I2C1_SCL,
+
+	GPIO0A1_SHIFT		= 2,
+	GPIO0A1_MASK		= 1 << GPIO0A1_SHIFT,
+	GPIO0A1_GPIO		= 0,
+	GPIO0A1_I2C0_SDA,
+
+	GPIO0A0_SHIFT		= 0,
+	GPIO0A0_MASK		= 1 << GPIO0A0_SHIFT,
+	GPIO0A0_GPIO		= 0,
+	GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+	GPIO0B6_SHIFT		= 12,
+	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
+	GPIO0B6_GPIO		= 0,
+	GPIO0B6_I2S_SDI,
+	GPIO0B6_SPI_CSN0,
+
+	GPIO0B5_SHIFT		= 10,
+	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
+	GPIO0B5_GPIO		= 0,
+	GPIO0B5_I2S_SDO,
+	GPIO0B5_SPI_RXD,
+
+	GPIO0B4_SHIFT		= 8,
+	GPIO0B4_MASK		= 1 << GPIO0B4_SHIFT,
+	GPIO0B4_GPIO		= 0,
+	GPIO0B4_I2S_LRCKTX,
+
+	GPIO0B3_SHIFT		= 6,
+	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
+	GPIO0B3_GPIO		= 0,
+	GPIO0B3_I2S_LRCKRX,
+	GPIO0B3_SPI_TXD,
+
+	GPIO0B1_SHIFT		= 2,
+	GPIO0B1_MASK		= 3,
+	GPIO0B1_GPIO		= 0,
+	GPIO0B1_I2S_SCLK,
+	GPIO0B1_SPI_CLK,
+
+	GPIO0B0_SHIFT		= 0,
+	GPIO0B0_MASK		= 3,
+	GPIO0B0_GPIO		= 0,
+	GPIO0B0_I2S1_MCLK,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+	GPIO0D4_SHIFT		= 8,
+	GPIO0D4_MASK		= 1 << GPIO0D4_SHIFT,
+	GPIO0D4_GPIO		= 0,
+	GPIO0D4_PWM2,
+
+	GPIO0D3_SHIFT		= 6,
+	GPIO0D3_MASK		= 1 << GPIO0D3_SHIFT,
+	GPIO0D3_GPIO		= 0,
+	GPIO0D3_PWM1,
+
+	GPIO0D2_SHIFT		= 4,
+	GPIO0D2_MASK		= 1 << GPIO0D2_SHIFT,
+	GPIO0D2_GPIO		= 0,
+	GPIO0D2_PWM0,
+
+	GPIO0D1_SHIFT		= 2,
+	GPIO0D1_MASK		= 1 << GPIO0D1_SHIFT,
+	GPIO0D1_GPIO		= 0,
+	GPIO0D1_UART2_CTSN,
+
+	GPIO0D0_SHIFT		= 0,
+	GPIO0D0_MASK		= 3 << GPIO0D0_SHIFT,
+	GPIO0D0_GPIO		= 0,
+	GPIO0D0_UART2_RTSN,
+	GPIO0D0_PMIC_SLEEP,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+	GPIO1A5_SHIFT		= 10,
+	GPIO1A5_MASK		= 3 << GPIO1A5_SHIFT,
+	GPIO1A5_GPIO		= 0,
+	GPIO1A5_I2S_SDI,
+	GPIO1A5_SDMMC_DATA3,
+
+	GPIO1A4_SHIFT		= 8,
+	GPIO1A4_MASK		= 3 << GPIO1A4_SHIFT,
+	GPIO1A4_GPIO		= 0,
+	GPIO1A4_I2S_SD0,
+	GPIO1A4_SDMMC_DATA2,
+
+	GPIO1A3_SHIFT		= 6,
+	GPIO1A3_MASK		= 1 << GPIO1A3_SHIFT,
+	GPIO1A3_GPIO		= 0,
+	GPIO1A3_I2S_LRCKTX,
+
+	GPIO1A2_SHIFT		= 4,
+	GPIO1A2_MASK		= 3 << GPIO1A2_SHIFT,
+	GPIO1A2_GPIO		= 0,
+	GPIO1A2_I2S_LRCKRX,
+	GPIO1A2_SDMMC_DATA1,
+
+	GPIO1A1_SHIFT		= 2,
+	GPIO1A1_MASK		= 3 << GPIO1A1_SHIFT,
+	GPIO1A1_GPIO		= 0,
+	GPIO1A1_I2S_SCLK,
+	GPIO1A1_SDMMC_DATA0,
+	GPIO1A1_PMIC_SLEEP,
+
+	GPIO1A0_SHIFT		= 0,
+	GPIO1A0_MASK		= 3,
+	GPIO1A0_GPIO		= 0,
+	GPIO1A0_I2S_MCLK,
+	GPIO1A0_SDMMC_CLKOUT,
+	GPIO1A0_XIN32K,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+	GPIO1B7_SHIFT		= 14,
+	GPIO1B7_MASK		= 1 << GPIO1B7_SHIFT,
+	GPIO1B7_GPIO		= 0,
+	GPIO1B7_MMC0_CMD,
+
+	GPIO1B6_SHIFT		= 12,
+	GPIO1B6_MASK		= 1 << GPIO1B6_SHIFT,
+	GPIO1B6_GPIO		= 0,
+	GPIO1B6_MMC_PWREN,
+
+	GPIO1B2_SHIFT		= 4,
+	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
+	GPIO1B2_GPIO		= 0,
+	GPIO1B2_SPI_RXD,
+	GPIO1B2_UART1_SIN,
+
+	GPIO1B1_SHIFT		= 2,
+	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
+	GPIO1B1_GPIO		= 0,
+	GPIO1B1_SPI_TXD,
+	GPIO1B1_UART1_SOUT,
+
+	GPIO1B0_SHIFT		= 0,
+	GPIO1B0_MASK		= 3 << GPIO1B0_SHIFT,
+	GPIO1B0_GPIO		= 0,
+	GPIO1B0_SPI_CLK,
+	GPIO1B0_UART1_CTSN
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+	GPIO1C6_SHIFT		= 12,
+	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
+	GPIO1C6_GPIO		= 0,
+	GPIO1C6_NAND_CS2,
+	GPIO1C6_EMMC_CMD,
+
+	GPIO1C5_SHIFT		= 10,
+	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
+	GPIO1C5_GPIO		= 0,
+	GPIO1C5_MMC0_D3,
+	GPIO1C5_JTAG_TMS,
+
+	GPIO1C4_SHIFT		= 8,
+	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
+	GPIO1C4_GPIO		= 0,
+	GPIO1C4_MMC0_D2,
+	GPIO1C4_JTAG_TCK,
+
+	GPIO1C3_SHIFT		= 6,
+	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
+	GPIO1C3_GPIO		= 0,
+	GPIO1C3_MMC0_D1,
+	GPIO1C3_UART2_RX,
+
+	GPIO1C2_SHIFT		= 4,
+	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT,
+	GPIO1C2_GPIO		= 0,
+	GPIO1C2_MMC0_D0,
+	GPIO1C2_UART2_TX,
+
+	GPIO1C1_SHIFT		= 2,
+	GPIO1C1_MASK		= 1 << GPIO1C1_SHIFT,
+	GPIO1C1_GPIO		= 0,
+	GPIO1C1_MMC0_DETN,
+
+	GPIO1C0_SHIFT		= 0,
+	GPIO1C0_MASK		= 1 << GPIO1C0_SHIFT,
+	GPIO1C0_GPIO		= 0,
+	GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+	GPIO1D7_SHIFT		= 14,
+	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
+	GPIO1D7_GPIO		= 0,
+	GPIO1D7_NAND_D7,
+	GPIO1D7_EMMC_D7,
+	GPIO1D7_SPI_CSN1,
+
+	GPIO1D6_SHIFT		= 12,
+	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
+	GPIO1D6_GPIO		= 0,
+	GPIO1D6_NAND_D6,
+	GPIO1D6_EMMC_D6,
+	GPIO1D6_SPI_CSN0,
+
+	GPIO1D5_SHIFT		= 10,
+	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
+	GPIO1D5_GPIO		= 0,
+	GPIO1D5_NAND_D5,
+	GPIO1D5_EMMC_D5,
+	GPIO1D5_SPI_TXD1,
+
+	GPIO1D4_SHIFT		= 8,
+	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
+	GPIO1D4_GPIO		= 0,
+	GPIO1D4_NAND_D4,
+	GPIO1D4_EMMC_D4,
+	GPIO1D4_SPI_RXD1,
+
+	GPIO1D3_SHIFT		= 6,
+	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
+	GPIO1D3_GPIO		= 0,
+	GPIO1D3_NAND_D3,
+	GPIO1D3_EMMC_D3,
+	GPIO1D3_SFC_SIO3,
+
+	GPIO1D2_SHIFT		= 4,
+	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
+	GPIO1D2_GPIO		= 0,
+	GPIO1D2_NAND_D2,
+	GPIO1D2_EMMC_D2,
+	GPIO1D2_SFC_SIO2,
+
+	GPIO1D1_SHIFT		= 2,
+	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
+	GPIO1D1_GPIO		= 0,
+	GPIO1D1_NAND_D1,
+	GPIO1D1_EMMC_D1,
+	GPIO1D1_SFC_SIO1,
+
+	GPIO1D0_SHIFT		= 0,
+	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
+	GPIO1D0_GPIO		= 0,
+	GPIO1D0_NAND_D0,
+	GPIO1D0_EMMC_D0,
+	GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+	GPIO2A7_SHIFT		= 14,
+	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
+	GPIO2A7_GPIO		= 0,
+	GPIO2A7_NAND_DQS,
+	GPIO2A7_EMMC_CLKOUT,
+
+	GPIO2A6_SHIFT		= 12,
+	GPIO2A6_MASK		= 1 << GPIO2A6_SHIFT,
+	GPIO2A6_GPIO		= 0,
+	GPIO2A6_NAND_CS0,
+
+	GPIO2A5_SHIFT		= 10,
+	GPIO2A5_MASK		= 3 << GPIO2A5_SHIFT,
+	GPIO2A5_GPIO		= 0,
+	GPIO2A5_NAND_WP,
+	GPIO2A5_EMMC_PWREN,
+
+	GPIO2A4_SHIFT		= 8,
+	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
+	GPIO2A4_GPIO		= 0,
+	GPIO2A4_NAND_RDY,
+	GPIO2A4_EMMC_CMD,
+	GPIO2A3_SFC_CLK,
+
+	GPIO2A3_SHIFT		= 6,
+	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
+	GPIO2A3_GPIO		= 0,
+	GPIO2A3_NAND_RDN,
+	GPIO2A4_SFC_CSN1,
+
+	GPIO2A2_SHIFT		= 4,
+	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
+	GPIO2A2_GPIO		= 0,
+	GPIO2A2_NAND_WRN,
+	GPIO2A4_SFC_CSN0,
+
+	GPIO2A1_SHIFT		= 2,
+	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
+	GPIO2A1_GPIO		= 0,
+	GPIO2A1_NAND_CLE,
+	GPIO2A1_EMMC_CLKOUT,
+
+	GPIO2A0_SHIFT		= 0,
+	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
+	GPIO2A0_GPIO		= 0,
+	GPIO2A0_NAND_ALE,
+	GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+	GPIO2B7_SHIFT		= 14,
+	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
+	GPIO2B7_GPIO		= 0,
+	GPIO2B7_LCDC0_D13,
+	GPIO2B7_EBC_SDCE5,
+	GPIO2B7_GMAC_RXER,
+
+	GPIO2B6_SHIFT		= 12,
+	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
+	GPIO2B6_GPIO		= 0,
+	GPIO2B6_LCDC0_D12,
+	GPIO2B6_EBC_SDCE4,
+	GPIO2B6_GMAC_CLK,
+
+	GPIO2B5_SHIFT		= 10,
+	GPIO2B5_MASK		= 3 << GPIO2B5_SHIFT,
+	GPIO2B5_GPIO		= 0,
+	GPIO2B5_LCDC0_D11,
+	GPIO2B5_EBC_SDCE3,
+	GPIO2B5_GMAC_TXEN,
+
+	GPIO2B4_SHIFT		= 8,
+	GPIO2B4_MASK		= 3 << GPIO2B4_SHIFT,
+	GPIO2B4_GPIO		= 0,
+	GPIO2B4_LCDC0_D10,
+	GPIO2B4_EBC_SDCE2,
+	GPIO2B4_GMAC_MDIO,
+
+	GPIO2B3_SHIFT		= 6,
+	GPIO2B3_MASK		= 3 << GPIO2B3_SHIFT,
+	GPIO2B3_GPIO		= 0,
+	GPIO2B3_LCDC0_DEN,
+	GPIO2B3_EBC_GDCLK,
+	GPIO2B3_GMAC_RXCLK,
+
+	GPIO2B2_SHIFT		= 4,
+	GPIO2B2_MASK		= 3 << GPIO2B2_SHIFT,
+	GPIO2B2_GPIO		= 0,
+	GPIO2B2_LCDC0_VSYNC,
+	GPIO2B2_EBC_SDOE,
+	GPIO2B2_GMAC_CRS,
+
+	GPIO2B1_SHIFT		= 2,
+	GPIO2B1_MASK		= 3 << GPIO2B1_SHIFT,
+	GPIO2B1_GPIO		= 0,
+	GPIO2B1_LCDC0_HSYNC,
+	GPIO2B1_EBC_SDLE,
+	GPIO2B1_GMAC_TXCLK,
+
+	GPIO2B0_SHIFT		= 0,
+	GPIO2B0_MASK		= 3 << GPIO2B0_SHIFT,
+	GPIO2B0_GPIO		= 0,
+	GPIO2B0_LCDC0_DCLK,
+	GPIO2B0_EBC_SDCLK,
+	GPIO2B0_GMAC_RXDV,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+	GPIO2C3_SHIFT		= 6,
+	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
+	GPIO2C3_GPIO		= 0,
+	GPIO2C3_LCDC0_D17,
+	GPIO2C3_EBC_GDPWR0,
+	GPIO2C3_GMAC_TXD0,
+
+	GPIO2C2_SHIFT		= 4,
+	GPIO2C2_MASK		= 3 << GPIO2C2_SHIFT,
+	GPIO2C2_GPIO		= 0,
+	GPIO2C2_LCDC0_D16,
+	GPIO2C2_EBC_GDSP,
+	GPIO2C2_GMAC_TXD1,
+
+	GPIO2C1_SHIFT		= 2,
+	GPIO2C1_MASK		= 3 << GPIO2C1_SHIFT,
+	GPIO2C1_GPIO		= 0,
+	GPIO2C1_LCDC0_D15,
+	GPIO2C1_EBC_GDOE,
+	GPIO2C1_GMAC_RXD0,
+
+	GPIO2C0_SHIFT		= 0,
+	GPIO2C0_MASK		= 3 << GPIO2C0_SHIFT,
+	GPIO2C0_GPIO		= 0,
+	GPIO2C0_LCDC0_D14,
+	GPIO2C0_EBC_VCOM,
+	GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2D6_SHIFT		= 12,
+	GPIO2D6_MASK		= 3 << GPIO2D6_SHIFT,
+	GPIO2D6_GPIO		= 0,
+	GPIO2D6_LCDC0_D22,
+	GPIO2D6_GMAC_COL	= 4,
+
+	GPIO2D1_SHIFT		= 2,
+	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
+	GPIO2D1_GPIO		= 0,
+	GPIO2D1_GMAC_MDC	= 3,
+};
+
+/* GRF_GPIO2C_IOMUX2 */
+enum {
+	GPIO2C7_SHIFT		= 12,
+	GPIO2C7_MASK		= 7 << GPIO2C7_SHIFT,
+	GPIO2C7_GPIO		= 0,
+	GPIO2C7_GMAC_TXD3	= 4,
+
+	GPIO2C6_SHIFT		= 12,
+	GPIO2C6_MASK		= 7 << GPIO2C6_SHIFT,
+	GPIO2C6_GPIO		= 0,
+	GPIO2C6_GMAC_TXD2	= 4,
+
+	GPIO2C5_SHIFT		= 4,
+	GPIO2C5_MASK		= 7 << GPIO2C5_SHIFT,
+	GPIO2C5_GPIO		= 0,
+	GPIO2C5_I2C2_SCL	= 3,
+	GPIO2C5_GMAC_RXD2,
+
+	GPIO2C4_SHIFT		= 0,
+	GPIO2C4_MASK		= 7 << GPIO2C4_SHIFT,
+	GPIO2C4_GPIO		= 0,
+	GPIO2C4_I2C2_SDA	= 3,
+	GPIO2C4_GMAC_RXD2,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
new file mode 100644
index 0000000..d051976
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3188_H
+#define _ASM_ARCH_GRF_RK3188_H
+
+struct rk3188_grf_gpio_lh {
+	u32 l;
+	u32 h;
+};
+
+struct rk3188_grf {
+	struct rk3188_grf_gpio_lh gpio_dir[4];
+	struct rk3188_grf_gpio_lh gpio_do[4];
+	struct rk3188_grf_gpio_lh gpio_en[4];
+
+	u32 reserved[2];
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_status0;
+
+	u32 busdmac_con[3];
+	u32 peridmac_con[4];
+
+	u32 cpu_con[6];
+	u32 reserved0[2];
+
+	u32 ddrc_con0;
+	u32 ddrc_stat;
+
+	u32 io_con[5];
+	u32 soc_status1;
+
+	u32 uoc0_con[4];
+	u32 uoc1_con[4];
+	u32 uoc2_con[2];
+	u32 reserved1;
+	u32 uoc3_con[2];
+	u32 hsic_stat;
+	u32 os_reg[8];
+
+	u32 gpio0_p[3];
+	u32 gpio1_p[3][4];
+
+	u32 flash_data_p;
+	u32 flash_cmd_p;
+};
+check_member(rk3188_grf, flash_cmd_p, 0x01a4);
+
+/* GRF_SOC_CON0 */
+enum {
+	HSADC_CLK_DIR_SHIFT	= 15,
+	HSADC_CLK_DIR_MASK	= 1,
+
+	HSADC_SEL_SHIFT		= 14,
+	HSADC_SEL_MASK		= 1,
+
+	NOC_REMAP_SHIFT		= 12,
+	NOC_REMAP_MASK		= 1,
+
+	EMMC_FLASH_SEL_SHIFT	= 11,
+	EMMC_FLASH_SEL_MASK	= 1,
+
+	TZPC_REVISION_SHIFT	= 7,
+	TZPC_REVISION_MASK	= 0xf,
+
+	L2CACHE_ACC_SHIFT	= 5,
+	L2CACHE_ACC_MASK	= 3,
+
+	L2RD_WAIT_SHIFT		= 3,
+	L2RD_WAIT_MASK		= 3,
+
+	IMEMRD_WAIT_SHIFT	= 1,
+	IMEMRD_WAIT_MASK	= 3,
+};
+
+/* GRF_SOC_CON1 */
+enum {
+	RKI2C4_SEL_SHIFT	= 15,
+	RKI2C4_SEL_MASK		= 1,
+
+	RKI2C3_SEL_SHIFT	= 14,
+	RKI2C3_SEL_MASK		= 1,
+
+	RKI2C2_SEL_SHIFT	= 13,
+	RKI2C2_SEL_MASK		= 1,
+
+	RKI2C1_SEL_SHIFT	= 12,
+	RKI2C1_SEL_MASK		= 1,
+
+	RKI2C0_SEL_SHIFT	= 11,
+	RKI2C0_SEL_MASK		= 1,
+
+	VCODEC_SEL_SHIFT	= 10,
+	VCODEC_SEL_MASK		= 1,
+
+	PERI_EMEM_PAUSE_SHIFT	= 9,
+	PERI_EMEM_PAUSE_MASK	= 1,
+
+	PERI_USB_PAUSE_SHIFT	= 8,
+	PERI_USB_PAUSE_MASK	= 1,
+
+	SMC_MUX_MODE_0_SHIFT	= 6,
+	SMC_MUX_MODE_0_MASK	= 1,
+
+	SMC_SRAM_MW_0_SHIFT	= 4,
+	SMC_SRAM_MW_0_MASK	= 3,
+
+	SMC_REMAP_0_SHIFT	= 3,
+	SMC_REMAP_0_MASK	= 1,
+
+	SMC_A_GT_M0_SYNC_SHIFT	= 2,
+	SMC_A_GT_M0_SYNC_MASK	= 1,
+
+	EMAC_SPEED_SHIFT	= 1,
+	EMAC_SPEEC_MASK		= 1,
+
+	EMAC_MODE_SHIFT		= 0,
+	EMAC_MODE_MASK		= 1,
+};
+
+/* GRF_SOC_CON2 */
+enum {
+	SDIO_CLK_OUT_SR_SHIFT	= 15,
+	SDIO_CLK_OUT_SR_MASK	= 1,
+
+	MEM_EMA_L2C_SHIFT	= 11,
+	MEM_EMA_L2C_MASK	= 7,
+
+	MEM_EMA_A9_SHIFT	= 8,
+	MEM_EMA_A9_MASK		= 7,
+
+	MSCH4_MAINDDR3_SHIFT	= 7,
+	MSCH4_MAINDDR3_MASK	= 1,
+	MSCH4_MAINDDR3_DDR3	= 1,
+
+	EMAC_NEWRCV_EN_SHIFT	= 6,
+	EMAC_NEWRCV_EN_MASK	= 1,
+
+	SW_ADDR15_EN_SHIFT	= 5,
+	SW_ADDR15_EN_MASK	= 1,
+
+	SW_ADDR16_EN_SHIFT	= 4,
+	SW_ADDR16_EN_MASK	= 1,
+
+	SW_ADDR17_EN_SHIFT	= 3,
+	SW_ADDR17_EN_MASK	= 1,
+
+	BANK2_TO_RANK_EN_SHIFT	= 2,
+	BANK2_TO_RANK_EN_MASK	= 1,
+
+	RANK_TO_ROW15_EN_SHIFT	= 1,
+	RANK_TO_ROW15_EN_MASK	= 1,
+
+	UPCTL_C_ACTIVE_IN_SHIFT = 0,
+	UPCTL_C_ACTIVE_IN_MASK	= 1,
+	UPCTL_C_ACTIVE_IN_MAY	= 0,
+	UPCTL_C_ACTIVE_IN_WILL,
+};
+
+/* GRF_DDRC_CON0 */
+enum {
+	DDR_16BIT_EN_SHIFT	= 15,
+	DDR_16BIT_EN_MASK	= 1,
+
+	DTO_LB_SHIFT		= 11,
+	DTO_LB_MASK		= 3,
+
+	DTO_TE_SHIFT		= 9,
+	DTO_TE_MASK		= 3,
+
+	DTO_PDR_SHIFT		= 7,
+	DTO_PDR_MASK		= 3,
+
+	DTO_PDD_SHIFT		= 5,
+	DTO_PDD_MASK		= 3,
+
+	DTO_IOM_SHIFT		= 3,
+	DTO_IOM_MASK		= 3,
+
+	DTO_OE_SHIFT		= 1,
+	DTO_OE_MASK		= 3,
+
+	ATO_AE_SHIFT		= 0,
+	ATO_AE_MASK		= 1,
+};
+
+/* GRF_UOC_CON0 */
+enum {
+	SIDDQ_SHIFT		= 13,
+	SIDDQ_MASK		= 1 << SIDDQ_SHIFT,
+
+	BYPASSSEL_SHIFT		= 9,
+	BYPASSSEL_MASK		= 1 << BYPASSSEL_SHIFT,
+
+	BYPASSDMEN_SHIFT	= 8,
+	BYPASSDMEN_MASK		= 1 << BYPASSDMEN_SHIFT,
+
+	UOC_DISABLE_SHIFT	= 4,
+	UOC_DISABLE_MASK	= 1 << UOC_DISABLE_SHIFT,
+
+	COMMON_ON_N_SHIFT	= 0,
+	COMMON_ON_N_MASK	= 1 << COMMON_ON_N_SHIFT,
+};
+
+/* GRF_UOC_CON2 */
+enum {
+	SOFT_CON_SEL_SHIFT	= 2,
+	SOFT_CON_SEL_MASK	= 1 << SOFT_CON_SEL_SHIFT,
+};
+
+/* GRF_UOC0_CON3 */
+enum {
+	TERMSEL_FULLSPEED_SHIFT	= 5,
+	TERMSEL_FULLSPEED_MASK	= 1 << TERMSEL_FULLSPEED_SHIFT,
+
+	XCVRSELECT_SHIFT	= 3,
+	XCVRSELECT_FSTRANSC	= 1,
+	XCVRSELECT_MASK		= 3 << XCVRSELECT_SHIFT,
+
+	OPMODE_SHIFT		= 1,
+	OPMODE_NODRIVING	= 1,
+	OPMODE_MASK		= 3 << OPMODE_SHIFT,
+
+	SUSPENDN_SHIFT		= 0,
+	SUSPENDN_MASK		= 1 << SUSPENDN_SHIFT,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
new file mode 100644
index 0000000..a99d137
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_GRF_RK322X_H
+#define _ASM_ARCH_GRF_RK322X_H
+
+#include <common.h>
+
+struct rk322x_grf {
+	unsigned int gpio0a_iomux;
+	unsigned int gpio0b_iomux;
+	unsigned int gpio0c_iomux;
+	unsigned int gpio0d_iomux;
+
+	unsigned int gpio1a_iomux;
+	unsigned int gpio1b_iomux;
+	unsigned int gpio1c_iomux;
+	unsigned int gpio1d_iomux;
+
+	unsigned int gpio2a_iomux;
+	unsigned int gpio2b_iomux;
+	unsigned int gpio2c_iomux;
+	unsigned int gpio2d_iomux;
+
+	unsigned int gpio3a_iomux;
+	unsigned int gpio3b_iomux;
+	unsigned int gpio3c_iomux;
+	unsigned int gpio3d_iomux;
+
+	unsigned int reserved1[4];
+	unsigned int con_iomux;
+	unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
+	unsigned int gpio0_p[4];
+	unsigned int gpio1_p[4];
+	unsigned int gpio2_p[4];
+	unsigned int gpio3_p[4];
+	unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
+	unsigned int gpio0_e[4];
+	unsigned int gpio1_e[4];
+	unsigned int gpio2_e[4];
+	unsigned int gpio3_e[4];
+	unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
+	unsigned int soc_con[7];
+	unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
+	unsigned int soc_status[3];
+	unsigned int chip_id;
+	unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
+	unsigned int cpu_con[4];
+	unsigned int reserved7[4];
+	unsigned int cpu_status[2];
+	unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
+	unsigned int os_reg[8];
+	unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
+	unsigned int ddrc_stat;
+	unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
+	unsigned int sig_detect_con[2];
+	unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
+	unsigned int sig_detect_status[2];
+	unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
+	unsigned int sig_detect_clr[2];
+	unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
+	unsigned int emmc_det;
+	unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
+	unsigned int host0_con[3];
+	unsigned int reserved15;
+	unsigned int host1_con[3];
+	unsigned int reserved16;
+	unsigned int host2_con[3];
+	unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
+	unsigned int usbphy0_con[27];
+	unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
+	unsigned int usbphy1_con[27];
+	unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
+	unsigned int otg_con0;
+	unsigned int uoc_status0;
+	unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
+	unsigned int mac_con[2];
+	unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
+	unsigned int macphy_con[4];
+	unsigned int macphy_status;
+};
+check_member(rk322x_grf, ddrc_stat, 0x604);
+
+struct rk322x_sgrf {
+	unsigned int soc_con[11];
+	unsigned int busdmac_con[4];
+};
+
+/* GRF_MACPHY_CON0 */
+enum {
+	MACPHY_CFG_ENABLE_SHIFT = 0,
+	MACPHY_CFG_ENABLE_MASK  = 1 << MACPHY_CFG_ENABLE_SHIFT,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
new file mode 100644
index 0000000..894d3a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -0,0 +1,1155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3288_H
+#define _ASM_ARCH_GRF_RK3288_H
+
+struct rk3288_grf_gpio_lh {
+	u32 l;
+	u32 h;
+};
+
+struct rk3288_grf {
+	u32 reserved[3];
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+
+	u32 gpio2c_iomux;
+	u32 reserved2;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+
+	u32 gpio3c_iomux;
+	u32 gpio3dl_iomux;
+	u32 gpio3dh_iomux;
+	u32 gpio4al_iomux;
+
+	u32 gpio4ah_iomux;
+	u32 gpio4bl_iomux;
+	u32 reserved3;
+	u32 gpio4c_iomux;
+
+	u32 gpio4d_iomux;
+	u32 reserved4;
+	u32 gpio5b_iomux;
+	u32 gpio5c_iomux;
+
+	u32 reserved5;
+	u32 gpio6a_iomux;
+	u32 gpio6b_iomux;
+	u32 gpio6c_iomux;
+	u32 reserved6;
+	u32 gpio7a_iomux;
+	u32 gpio7b_iomux;
+	u32 gpio7cl_iomux;
+	u32 gpio7ch_iomux;
+	u32 reserved7;
+	u32 gpio8a_iomux;
+	u32 gpio8b_iomux;
+	u32 reserved8[30];
+	struct rk3288_grf_gpio_lh gpio_sr[8];
+	u32 gpio1_p[8][4];
+	u32 gpio1_e[8][4];
+	u32 gpio_smt;
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_status[22];
+	u32 reserved9[2];
+	u32 peridmac_con[4];
+	u32 ddrc0_con0;
+	u32 ddrc1_con0;
+	u32 cpu_con[5];
+	u32 reserved10[3];
+	u32 cpu_status0;
+	u32 reserved11;
+	u32 uoc0_con[5];
+	u32 uoc1_con[5];
+	u32 uoc2_con[4];
+	u32 uoc3_con[2];
+	u32 uoc4_con[2];
+	u32 pvtm_con[3];
+	u32 pvtm_status[3];
+	u32 io_vsel;
+	u32 saradc_testbit;
+	u32 tsadc_testbit_l;
+	u32 tsadc_testbit_h;
+	u32 os_reg[4];
+	u32 reserved12;
+	u32 soc_con15;
+	u32 soc_con16;
+};
+
+struct rk3288_sgrf {
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 reserved1[(0x20-0x18)/4];
+	u32 busdmac_con[2];
+	u32 reserved2[(0x40-0x28)/4];
+	u32 cpu_con[3];
+	u32 reserved3[(0x50-0x4c)/4];
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 soc_con16;
+	u32 soc_con17;
+	u32 soc_con18;
+	u32 soc_con19;
+	u32 soc_con20;
+	u32 soc_con21;
+	u32 reserved4[(0x100-0x90)/4];
+	u32 soc_status[2];
+	u32 reserved5[(0x120-0x108)/4];
+	u32 fast_boot_addr;
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+	GPIO1D3_SHIFT		= 6,
+	GPIO1D3_MASK		= 1,
+	GPIO1D3_GPIO		= 0,
+	GPIO1D3_LCDC0_DCLK,
+
+	GPIO1D2_SHIFT		= 4,
+	GPIO1D2_MASK		= 1,
+	GPIO1D2_GPIO		= 0,
+	GPIO1D2_LCDC0_DEN,
+
+	GPIO1D1_SHIFT		= 2,
+	GPIO1D1_MASK		= 1,
+	GPIO1D1_GPIO		= 0,
+	GPIO1D1_LCDC0_VSYNC,
+
+	GPIO1D0_SHIFT		= 0,
+	GPIO1D0_MASK		= 1,
+	GPIO1D0_GPIO		= 0,
+	GPIO1D0_LCDC0_HSYNC,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+	GPIO2C1_SHIFT		= 2,
+	GPIO2C1_MASK		= 1,
+	GPIO2C1_GPIO		= 0,
+	GPIO2C1_I2C3CAM_SDA,
+
+	GPIO2C0_SHIFT		= 0,
+	GPIO2C0_MASK		= 1,
+	GPIO2C0_GPIO		= 0,
+	GPIO2C0_I2C3CAM_SCL,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+	GPIO3A7_SHIFT		= 14,
+	GPIO3A7_MASK		= 3,
+	GPIO3A7_GPIO		= 0,
+	GPIO3A7_FLASH0_DATA7,
+	GPIO3A7_EMMC_DATA7,
+
+	GPIO3A6_SHIFT		= 12,
+	GPIO3A6_MASK		= 3,
+	GPIO3A6_GPIO		= 0,
+	GPIO3A6_FLASH0_DATA6,
+	GPIO3A6_EMMC_DATA6,
+
+	GPIO3A5_SHIFT		= 10,
+	GPIO3A5_MASK		= 3,
+	GPIO3A5_GPIO		= 0,
+	GPIO3A5_FLASH0_DATA5,
+	GPIO3A5_EMMC_DATA5,
+
+	GPIO3A4_SHIFT		= 8,
+	GPIO3A4_MASK		= 3,
+	GPIO3A4_GPIO		= 0,
+	GPIO3A4_FLASH0_DATA4,
+	GPIO3A4_EMMC_DATA4,
+
+	GPIO3A3_SHIFT		= 6,
+	GPIO3A3_MASK		= 3,
+	GPIO3A3_GPIO		= 0,
+	GPIO3A3_FLASH0_DATA3,
+	GPIO3A3_EMMC_DATA3,
+
+	GPIO3A2_SHIFT		= 4,
+	GPIO3A2_MASK		= 3,
+	GPIO3A2_GPIO		= 0,
+	GPIO3A2_FLASH0_DATA2,
+	GPIO3A2_EMMC_DATA2,
+
+	GPIO3A1_SHIFT		= 2,
+	GPIO3A1_MASK		= 3,
+	GPIO3A1_GPIO		= 0,
+	GPIO3A1_FLASH0_DATA1,
+	GPIO3A1_EMMC_DATA1,
+
+	GPIO3A0_SHIFT		= 0,
+	GPIO3A0_MASK		= 3,
+	GPIO3A0_GPIO		= 0,
+	GPIO3A0_FLASH0_DATA0,
+	GPIO3A0_EMMC_DATA0,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+	GPIO3B7_SHIFT		= 14,
+	GPIO3B7_MASK		= 1,
+	GPIO3B7_GPIO		= 0,
+	GPIO3B7_FLASH0_CSN1,
+
+	GPIO3B6_SHIFT		= 12,
+	GPIO3B6_MASK		= 1,
+	GPIO3B6_GPIO		= 0,
+	GPIO3B6_FLASH0_CSN0,
+
+	GPIO3B5_SHIFT		= 10,
+	GPIO3B5_MASK		= 1,
+	GPIO3B5_GPIO		= 0,
+	GPIO3B5_FLASH0_WRN,
+
+	GPIO3B4_SHIFT		= 8,
+	GPIO3B4_MASK		= 1,
+	GPIO3B4_GPIO		= 0,
+	GPIO3B4_FLASH0_CLE,
+
+	GPIO3B3_SHIFT		= 6,
+	GPIO3B3_MASK		= 1,
+	GPIO3B3_GPIO		= 0,
+	GPIO3B3_FLASH0_ALE,
+
+	GPIO3B2_SHIFT		= 4,
+	GPIO3B2_MASK		= 1,
+	GPIO3B2_GPIO		= 0,
+	GPIO3B2_FLASH0_RDN,
+
+	GPIO3B1_SHIFT		= 2,
+	GPIO3B1_MASK		= 3,
+	GPIO3B1_GPIO		= 0,
+	GPIO3B1_FLASH0_WP,
+	GPIO3B1_EMMC_PWREN,
+
+	GPIO3B0_SHIFT		= 0,
+	GPIO3B0_MASK		= 1,
+	GPIO3B0_GPIO		= 0,
+	GPIO3B0_FLASH0_RDY,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+	GPIO3C2_SHIFT		= 4,
+	GPIO3C2_MASK		= 3,
+	GPIO3C2_GPIO		= 0,
+	GPIO3C2_FLASH0_DQS,
+	GPIO3C2_EMMC_CLKOUT,
+
+	GPIO3C1_SHIFT		= 2,
+	GPIO3C1_MASK		= 3,
+	GPIO3C1_GPIO		= 0,
+	GPIO3C1_FLASH0_CSN3,
+	GPIO3C1_EMMC_RSTNOUT,
+
+	GPIO3C0_SHIFT		= 0,
+	GPIO3C0_MASK		= 3,
+	GPIO3C0_GPIO		= 0,
+	GPIO3C0_FLASH0_CSN2,
+	GPIO3C0_EMMC_CMD,
+};
+
+/* GRF_GPIO3DL_IOMUX */
+enum {
+	GPIO3D3_SHIFT		= 12,
+	GPIO3D3_MASK		= 7,
+	GPIO3D3_GPIO		= 0,
+	GPIO3D3_FLASH1_DATA3,
+	GPIO3D3_HOST_DOUT3,
+	GPIO3D3_MAC_RXD3,
+	GPIO3D3_SDIO1_DATA3,
+
+	GPIO3D2_SHIFT		= 8,
+	GPIO3D2_MASK		= 7,
+	GPIO3D2_GPIO		= 0,
+	GPIO3D2_FLASH1_DATA2,
+	GPIO3D2_HOST_DOUT2,
+	GPIO3D2_MAC_RXD2,
+	GPIO3D2_SDIO1_DATA2,
+
+	GPIO3D1_SHIFT		= 4,
+	GPIO3D1_MASK		= 7,
+	GPIO3D1_GPIO		= 0,
+	GPIO3DL1_FLASH1_DATA1,
+	GPIO3D1_HOST_DOUT1,
+	GPIO3D1_MAC_TXD3,
+	GPIO3D1_SDIO1_DATA1,
+
+	GPIO3D0_SHIFT		= 0,
+	GPIO3D0_MASK		= 7,
+	GPIO3D0_GPIO		= 0,
+	GPIO3D0_FLASH1_DATA0,
+	GPIO3D0_HOST_DOUT0,
+	GPIO3D0_MAC_TXD2,
+	GPIO3D0_SDIO1_DATA0,
+};
+
+/* GRF_GPIO3HL_IOMUX */
+enum {
+	GPIO3D7_SHIFT		= 12,
+	GPIO3D7_MASK		= 7,
+	GPIO3D7_GPIO		= 0,
+	GPIO3D7_FLASH1_DATA7,
+	GPIO3D7_HOST_DOUT7,
+	GPIO3D7_MAC_RXD1,
+	GPIO3D7_SDIO1_INTN,
+
+	GPIO3D6_SHIFT		= 8,
+	GPIO3D6_MASK		= 7,
+	GPIO3D6_GPIO		= 0,
+	GPIO3D6_FLASH1_DATA6,
+	GPIO3D6_HOST_DOUT6,
+	GPIO3D6_MAC_RXD0,
+	GPIO3D6_SDIO1_BKPWR,
+
+	GPIO3D5_SHIFT		= 4,
+	GPIO3D5_MASK		= 7,
+	GPIO3D5_GPIO		= 0,
+	GPIO3D5_FLASH1_DATA5,
+	GPIO3D5_HOST_DOUT5,
+	GPIO3D5_MAC_TXD1,
+	GPIO3D5_SDIO1_WRPRT,
+
+	GPIO3D4_SHIFT		= 0,
+	GPIO3D4_MASK		= 7,
+	GPIO3D4_GPIO		= 0,
+	GPIO3D4_FLASH1_DATA4,
+	GPIO3D4_HOST_DOUT4,
+	GPIO3D4_MAC_TXD0,
+	GPIO3D4_SDIO1_DETECTN,
+};
+
+/* GRF_GPIO4AL_IOMUX */
+enum {
+	GPIO4A3_SHIFT		= 12,
+	GPIO4A3_MASK		= 7,
+	GPIO4A3_GPIO		= 0,
+	GPIO4A3_FLASH1_ALE,
+	GPIO4A3_HOST_DOUT9,
+	GPIO4A3_MAC_CLK,
+	GPIO4A3_FLASH0_CSN6,
+
+	GPIO4A2_SHIFT		= 8,
+	GPIO4A2_MASK		= 7,
+	GPIO4A2_GPIO		= 0,
+	GPIO4A2_FLASH1_RDN,
+	GPIO4A2_HOST_DOUT8,
+	GPIO4A2_MAC_RXER,
+	GPIO4A2_FLASH0_CSN5,
+
+	GPIO4A1_SHIFT		= 4,
+	GPIO4A1_MASK		= 7,
+	GPIO4A1_GPIO		= 0,
+	GPIO4A1_FLASH1_WP,
+	GPIO4A1_HOST_CKOUTN,
+	GPIO4A1_MAC_TXDV,
+	GPIO4A1_FLASH0_CSN4,
+
+	GPIO4A0_SHIFT		= 0,
+	GPIO4A0_MASK		= 3,
+	GPIO4A0_GPIO		= 0,
+	GPIO4A0_FLASH1_RDY,
+	GPIO4A0_HOST_CKOUTP,
+	GPIO4A0_MAC_MDC,
+};
+
+/* GRF_GPIO4AH_IOMUX */
+enum {
+	GPIO4A7_SHIFT		= 12,
+	GPIO4A7_MASK		= 7,
+	GPIO4A7_GPIO		= 0,
+	GPIO4A7_FLASH1_CSN1,
+	GPIO4A7_HOST_DOUT13,
+	GPIO4A7_MAC_CSR,
+	GPIO4A7_SDIO1_CLKOUT,
+
+	GPIO4A6_SHIFT		= 8,
+	GPIO4A6_MASK		= 7,
+	GPIO4A6_GPIO		= 0,
+	GPIO4A6_FLASH1_CSN0,
+	GPIO4A6_HOST_DOUT12,
+	GPIO4A6_MAC_RXCLK,
+	GPIO4A6_SDIO1_CMD,
+
+	GPIO4A5_SHIFT		= 4,
+	GPIO4A5_MASK		= 3,
+	GPIO4A5_GPIO		= 0,
+	GPIO4A5_FLASH1_WRN,
+	GPIO4A5_HOST_DOUT11,
+	GPIO4A5_MAC_MDIO,
+
+	GPIO4A4_SHIFT		= 0,
+	GPIO4A4_MASK		= 7,
+	GPIO4A4_GPIO		= 0,
+	GPIO4A4_FLASH1_CLE,
+	GPIO4A4_HOST_DOUT10,
+	GPIO4A4_MAC_TXEN,
+	GPIO4A4_FLASH0_CSN7,
+};
+
+/* GRF_GPIO4BL_IOMUX */
+enum {
+	GPIO4B1_SHIFT		= 4,
+	GPIO4B1_MASK		= 7,
+	GPIO4B1_GPIO		= 0,
+	GPIO4B1_FLASH1_CSN2,
+	GPIO4B1_HOST_DOUT15,
+	GPIO4B1_MAC_TXCLK,
+	GPIO4B1_SDIO1_PWREN,
+
+	GPIO4B0_SHIFT		= 0,
+	GPIO4B0_MASK		= 7,
+	GPIO4B0_GPIO		= 0,
+	GPIO4B0_FLASH1_DQS,
+	GPIO4B0_HOST_DOUT14,
+	GPIO4B0_MAC_COL,
+	GPIO4B0_FLASH1_CSN3,
+};
+
+/* GRF_GPIO4C_IOMUX */
+enum {
+	GPIO4C7_SHIFT		= 14,
+	GPIO4C7_MASK		= 1,
+	GPIO4C7_GPIO		= 0,
+	GPIO4C7_SDIO0_DATA3,
+
+	GPIO4C6_SHIFT		= 12,
+	GPIO4C6_MASK		= 1,
+	GPIO4C6_GPIO		= 0,
+	GPIO4C6_SDIO0_DATA2,
+
+	GPIO4C5_SHIFT		= 10,
+	GPIO4C5_MASK		= 1,
+	GPIO4C5_GPIO		= 0,
+	GPIO4C5_SDIO0_DATA1,
+
+	GPIO4C4_SHIFT		= 8,
+	GPIO4C4_MASK		= 1,
+	GPIO4C4_GPIO		= 0,
+	GPIO4C4_SDIO0_DATA0,
+
+	GPIO4C3_SHIFT		= 6,
+	GPIO4C3_MASK		= 1,
+	GPIO4C3_GPIO		= 0,
+	GPIO4C3_UART0BT_RTSN,
+
+	GPIO4C2_SHIFT		= 4,
+	GPIO4C2_MASK		= 1,
+	GPIO4C2_GPIO		= 0,
+	GPIO4C2_UART0BT_CTSN,
+
+	GPIO4C1_SHIFT		= 2,
+	GPIO4C1_MASK		= 1,
+	GPIO4C1_GPIO		= 0,
+	GPIO4C1_UART0BT_SOUT,
+
+	GPIO4C0_SHIFT		= 0,
+	GPIO4C0_MASK		= 1,
+	GPIO4C0_GPIO		= 0,
+	GPIO4C0_UART0BT_SIN,
+};
+
+/* GRF_GPIO5B_IOMUX */
+enum {
+	GPIO5B7_SHIFT		= 14,
+	GPIO5B7_MASK		= 3,
+	GPIO5B7_GPIO		= 0,
+	GPIO5B7_SPI0_RXD,
+	GPIO5B7_TS0_DATA7,
+	GPIO5B7_UART4EXP_SIN,
+
+	GPIO5B6_SHIFT		= 12,
+	GPIO5B6_MASK		= 3,
+	GPIO5B6_GPIO		= 0,
+	GPIO5B6_SPI0_TXD,
+	GPIO5B6_TS0_DATA6,
+	GPIO5B6_UART4EXP_SOUT,
+
+	GPIO5B5_SHIFT		= 10,
+	GPIO5B5_MASK		= 3,
+	GPIO5B5_GPIO		= 0,
+	GPIO5B5_SPI0_CSN0,
+	GPIO5B5_TS0_DATA5,
+	GPIO5B5_UART4EXP_RTSN,
+
+	GPIO5B4_SHIFT		= 8,
+	GPIO5B4_MASK		= 3,
+	GPIO5B4_GPIO		= 0,
+	GPIO5B4_SPI0_CLK,
+	GPIO5B4_TS0_DATA4,
+	GPIO5B4_UART4EXP_CTSN,
+
+	GPIO5B3_SHIFT		= 6,
+	GPIO5B3_MASK		= 3,
+	GPIO5B3_GPIO		= 0,
+	GPIO5B3_UART1BB_RTSN,
+	GPIO5B3_TS0_DATA3,
+
+	GPIO5B2_SHIFT		= 4,
+	GPIO5B2_MASK		= 3,
+	GPIO5B2_GPIO		= 0,
+	GPIO5B2_UART1BB_CTSN,
+	GPIO5B2_TS0_DATA2,
+
+	GPIO5B1_SHIFT		= 2,
+	GPIO5B1_MASK		= 3,
+	GPIO5B1_GPIO		= 0,
+	GPIO5B1_UART1BB_SOUT,
+	GPIO5B1_TS0_DATA1,
+
+	GPIO5B0_SHIFT		= 0,
+	GPIO5B0_MASK		= 3,
+	GPIO5B0_GPIO		= 0,
+	GPIO5B0_UART1BB_SIN,
+	GPIO5B0_TS0_DATA0,
+};
+
+/* GRF_GPIO5C_IOMUX */
+enum {
+	GPIO5C3_SHIFT		= 6,
+	GPIO5C3_MASK		= 1,
+	GPIO5C3_GPIO		= 0,
+	GPIO5C3_TS0_ERR,
+
+	GPIO5C2_SHIFT		= 4,
+	GPIO5C2_MASK		= 1,
+	GPIO5C2_GPIO		= 0,
+	GPIO5C2_TS0_CLK,
+
+	GPIO5C1_SHIFT		= 2,
+	GPIO5C1_MASK		= 1,
+	GPIO5C1_GPIO		= 0,
+	GPIO5C1_TS0_VALID,
+
+	GPIO5C0_SHIFT		= 0,
+	GPIO5C0_MASK		= 3,
+	GPIO5C0_GPIO		= 0,
+	GPIO5C0_SPI0_CSN1,
+	GPIO5C0_TS0_SYNC,
+};
+
+/* GRF_GPIO6A_IOMUX */
+enum {
+	GPIO6A7_SHIFT		= 0xe,
+	GPIO6A7_MASK		= 1,
+	GPIO6A7_GPIO		= 0,
+	GPIO6A7_I2S_SDO3,
+
+	GPIO6A6_SHIFT		= 0xc,
+	GPIO6A6_MASK		= 1,
+	GPIO6A6_GPIO		= 0,
+	GPIO6A6_I2S_SDO2,
+
+	GPIO6A5_SHIFT		= 0xa,
+	GPIO6A5_MASK		= 1,
+	GPIO6A5_GPIO		= 0,
+	GPIO6A5_I2S_SDO1,
+
+	GPIO6A4_SHIFT		= 8,
+	GPIO6A4_MASK		= 1,
+	GPIO6A4_GPIO		= 0,
+	GPIO6A4_I2S_SDO0,
+
+	GPIO6A3_SHIFT		= 6,
+	GPIO6A3_MASK		= 1,
+	GPIO6A3_GPIO		= 0,
+	GPIO6A3_I2S_SDI,
+
+	GPIO6A2_SHIFT		= 4,
+	GPIO6A2_MASK		= 1,
+	GPIO6A2_GPIO		= 0,
+	GPIO6A2_I2S_LRCKTX,
+
+	GPIO6A1_SHIFT		= 2,
+	GPIO6A1_MASK		= 1,
+	GPIO6A1_GPIO		= 0,
+	GPIO6A1_I2S_LRCKRX,
+
+	GPIO6A0_SHIFT		= 0,
+	GPIO6A0_MASK		= 1,
+	GPIO6A0_GPIO		= 0,
+	GPIO6A0_I2S_SCLK,
+};
+
+/* GRF_GPIO6B_IOMUX */
+enum {
+	GPIO6B3_SHIFT		= 6,
+	GPIO6B3_MASK		= 1,
+	GPIO6B3_GPIO		= 0,
+	GPIO6B3_SPDIF_TX,
+
+	GPIO6B2_SHIFT		= 4,
+	GPIO6B2_MASK		= 1,
+	GPIO6B2_GPIO		= 0,
+	GPIO6B2_I2C1AUDIO_SCL,
+
+	GPIO6B1_SHIFT		= 2,
+	GPIO6B1_MASK		= 1,
+	GPIO6B1_GPIO		= 0,
+	GPIO6B1_I2C1AUDIO_SDA,
+
+	GPIO6B0_SHIFT		= 0,
+	GPIO6B0_MASK		= 1,
+	GPIO6B0_GPIO		= 0,
+	GPIO6B0_I2S_CLK,
+};
+
+/* GRF_GPIO6C_IOMUX */
+enum {
+	GPIO6C6_SHIFT		= 12,
+	GPIO6C6_MASK		= 1,
+	GPIO6C6_GPIO		= 0,
+	GPIO6C6_SDMMC0_DECTN,
+
+	GPIO6C5_SHIFT		= 10,
+	GPIO6C5_MASK		= 1,
+	GPIO6C5_GPIO		= 0,
+	GPIO6C5_SDMMC0_CMD,
+
+	GPIO6C4_SHIFT		= 8,
+	GPIO6C4_MASK		= 3,
+	GPIO6C4_GPIO		= 0,
+	GPIO6C4_SDMMC0_CLKOUT,
+	GPIO6C4_JTAG_TDO,
+
+	GPIO6C3_SHIFT		= 6,
+	GPIO6C3_MASK		= 3,
+	GPIO6C3_GPIO		= 0,
+	GPIO6C3_SDMMC0_DATA3,
+	GPIO6C3_JTAG_TCK,
+
+	GPIO6C2_SHIFT		= 4,
+	GPIO6C2_MASK		= 3,
+	GPIO6C2_GPIO		= 0,
+	GPIO6C2_SDMMC0_DATA2,
+	GPIO6C2_JTAG_TDI,
+
+	GPIO6C1_SHIFT		= 2,
+	GPIO6C1_MASK		= 3,
+	GPIO6C1_GPIO		= 0,
+	GPIO6C1_SDMMC0_DATA1,
+	GPIO6C1_JTAG_TRSTN,
+
+	GPIO6C0_SHIFT		= 0,
+	GPIO6C0_MASK		= 3,
+	GPIO6C0_GPIO		= 0,
+	GPIO6C0_SDMMC0_DATA0,
+	GPIO6C0_JTAG_TMS,
+};
+
+/* GRF_GPIO7A_IOMUX */
+enum {
+	GPIO7A7_SHIFT		= 14,
+	GPIO7A7_MASK		= 3,
+	GPIO7A7_GPIO		= 0,
+	GPIO7A7_UART3GPS_SIN,
+	GPIO7A7_GPS_MAG,
+	GPIO7A7_HSADCT1_DATA0,
+
+	GPIO7A1_SHIFT		= 2,
+	GPIO7A1_MASK		= 1,
+	GPIO7A1_GPIO		= 0,
+	GPIO7A1_PWM_1,
+
+	GPIO7A0_SHIFT		= 0,
+	GPIO7A0_MASK		= 3,
+	GPIO7A0_GPIO		= 0,
+	GPIO7A0_PWM_0,
+	GPIO7A0_VOP0_PWM,
+	GPIO7A0_VOP1_PWM,
+};
+
+/* GRF_GPIO7B_IOMUX */
+enum {
+	GPIO7B7_SHIFT		= 14,
+	GPIO7B7_MASK		= 3,
+	GPIO7B7_GPIO		= 0,
+	GPIO7B7_ISP_SHUTTERTRIG,
+	GPIO7B7_SPI1_TXD,
+
+	GPIO7B6_SHIFT		= 12,
+	GPIO7B6_MASK		= 3,
+	GPIO7B6_GPIO		= 0,
+	GPIO7B6_ISP_PRELIGHTTRIG,
+	GPIO7B6_SPI1_RXD,
+
+	GPIO7B5_SHIFT		= 10,
+	GPIO7B5_MASK		= 3,
+	GPIO7B5_GPIO		= 0,
+	GPIO7B5_ISP_FLASHTRIGOUT,
+	GPIO7B5_SPI1_CSN0,
+
+	GPIO7B4_SHIFT		= 8,
+	GPIO7B4_MASK		= 3,
+	GPIO7B4_GPIO		= 0,
+	GPIO7B4_ISP_SHUTTEREN,
+	GPIO7B4_SPI1_CLK,
+
+	GPIO7B3_SHIFT		= 6,
+	GPIO7B3_MASK		= 3,
+	GPIO7B3_GPIO		= 0,
+	GPIO7B3_USB_DRVVBUS1,
+	GPIO7B3_EDP_HOTPLUG,
+
+	GPIO7B2_SHIFT		= 4,
+	GPIO7B2_MASK		= 3,
+	GPIO7B2_GPIO		= 0,
+	GPIO7B2_UART3GPS_RTSN,
+	GPIO7B2_USB_DRVVBUS0,
+
+	GPIO7B1_SHIFT		= 2,
+	GPIO7B1_MASK		= 3,
+	GPIO7B1_GPIO		= 0,
+	GPIO7B1_UART3GPS_CTSN,
+	GPIO7B1_GPS_RFCLK,
+	GPIO7B1_GPST1_CLK,
+
+	GPIO7B0_SHIFT		= 0,
+	GPIO7B0_MASK		= 3,
+	GPIO7B0_GPIO		= 0,
+	GPIO7B0_UART3GPS_SOUT,
+	GPIO7B0_GPS_SIG,
+	GPIO7B0_HSADCT1_DATA1,
+};
+
+/* GRF_GPIO7CL_IOMUX */
+enum {
+	GPIO7C3_SHIFT		= 12,
+	GPIO7C3_MASK		= 3,
+	GPIO7C3_GPIO		= 0,
+	GPIO7C3_I2C5HDMI_SDA,
+	GPIO7C3_EDPHDMII2C_SDA,
+
+	GPIO7C2_SHIFT		= 8,
+	GPIO7C2_MASK		= 1,
+	GPIO7C2_GPIO		= 0,
+	GPIO7C2_I2C4TP_SCL,
+
+	GPIO7C1_SHIFT		= 4,
+	GPIO7C1_MASK		= 1,
+	GPIO7C1_GPIO		= 0,
+	GPIO7C1_I2C4TP_SDA,
+
+	GPIO7C0_SHIFT		= 0,
+	GPIO7C0_MASK		= 3,
+	GPIO7C0_GPIO		= 0,
+	GPIO7C0_ISP_FLASHTRIGIN,
+	GPIO7C0_EDPHDMI_CECINOUTT1,
+};
+
+/* GRF_GPIO7CH_IOMUX */
+enum {
+	GPIO7C7_SHIFT		= 12,
+	GPIO7C7_MASK		= 7,
+	GPIO7C7_GPIO		= 0,
+	GPIO7C7_UART2DBG_SOUT,
+	GPIO7C7_UART2DBG_SIROUT,
+	GPIO7C7_PWM_3,
+	GPIO7C7_EDPHDMI_CECINOUT,
+
+	GPIO7C6_SHIFT		= 8,
+	GPIO7C6_MASK		= 3,
+	GPIO7C6_GPIO		= 0,
+	GPIO7C6_UART2DBG_SIN,
+	GPIO7C6_UART2DBG_SIRIN,
+	GPIO7C6_PWM_2,
+
+	GPIO7C4_SHIFT		= 0,
+	GPIO7C4_MASK		= 3,
+	GPIO7C4_GPIO		= 0,
+	GPIO7C4_I2C5HDMI_SCL,
+	GPIO7C4_EDPHDMII2C_SCL,
+};
+
+/* GRF_GPIO8A_IOMUX */
+enum {
+	GPIO8A7_SHIFT		= 14,
+	GPIO8A7_MASK		= 3,
+	GPIO8A7_GPIO		= 0,
+	GPIO8A7_SPI2_CSN0,
+	GPIO8A7_SC_DETECT,
+	GPIO8A7_RESERVE,
+
+	GPIO8A6_SHIFT		= 12,
+	GPIO8A6_MASK		= 3,
+	GPIO8A6_GPIO		= 0,
+	GPIO8A6_SPI2_CLK,
+	GPIO8A6_SC_IO,
+	GPIO8A6_RESERVE,
+
+	GPIO8A5_SHIFT		= 10,
+	GPIO8A5_MASK		= 3,
+	GPIO8A5_GPIO		= 0,
+	GPIO8A5_I2C2SENSOR_SCL,
+	GPIO8A5_SC_CLK,
+
+	GPIO8A4_SHIFT		= 8,
+	GPIO8A4_MASK		= 3,
+	GPIO8A4_GPIO		= 0,
+	GPIO8A4_I2C2SENSOR_SDA,
+	GPIO8A4_SC_RST,
+
+	GPIO8A3_SHIFT		= 6,
+	GPIO8A3_MASK		= 3,
+	GPIO8A3_GPIO		= 0,
+	GPIO8A3_SPI2_CSN1,
+	GPIO8A3_SC_IOT1,
+
+	GPIO8A2_SHIFT		= 4,
+	GPIO8A2_MASK		= 1,
+	GPIO8A2_GPIO		= 0,
+	GPIO8A2_SC_DETECTT1,
+
+	GPIO8A1_SHIFT		= 2,
+	GPIO8A1_MASK		= 3,
+	GPIO8A1_GPIO		= 0,
+	GPIO8A1_PS2_DATA,
+	GPIO8A1_SC_VCC33V,
+
+	GPIO8A0_SHIFT		= 0,
+	GPIO8A0_MASK		= 3,
+	GPIO8A0_GPIO		= 0,
+	GPIO8A0_PS2_CLK,
+	GPIO8A0_SC_VCC18V,
+};
+
+/* GRF_GPIO8B_IOMUX */
+enum {
+	GPIO8B1_SHIFT		= 2,
+	GPIO8B1_MASK		= 3,
+	GPIO8B1_GPIO		= 0,
+	GPIO8B1_SPI2_TXD,
+	GPIO8B1_SC_CLK,
+
+	GPIO8B0_SHIFT		= 0,
+	GPIO8B0_MASK		= 3,
+	GPIO8B0_GPIO		= 0,
+	GPIO8B0_SPI2_RXD,
+	GPIO8B0_SC_RST,
+};
+
+/* GRF_SOC_CON0 */
+enum {
+	PAUSE_MMC_PERI_SHIFT	= 0xf,
+	PAUSE_MMC_PERI_MASK	= 1,
+
+	PAUSE_EMEM_PERI_SHIFT	= 0xe,
+	PAUSE_EMEM_PERI_MASK	= 1,
+
+	PAUSE_USB_PERI_SHIFT	= 0xd,
+	PAUSE_USB_PERI_MASK	= 1,
+
+	GRF_FORCE_JTAG_SHIFT	= 0xc,
+	GRF_FORCE_JTAG_MASK	= 1,
+
+	GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
+	GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
+
+	GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
+	GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
+
+	DDR1_16BIT_EN_SHIFT	= 9,
+	DDR1_16BIT_EN_MASK	= 1,
+
+	DDR0_16BIT_EN_SHIFT	= 8,
+	DDR0_16BIT_EN_MASK	= 1,
+
+	VCODEC_SHIFT		= 7,
+	VCODEC_MASK		= 1,
+	VCODEC_SELECT_VEPU_ACLK	= 0,
+	VCODEC_SELECT_VDPU_ACLK,
+
+	UPCTL1_C_ACTIVE_IN_SHIFT = 6,
+	UPCTL1_C_ACTIVE_IN_MASK	= 1,
+	UPCTL1_C_ACTIVE_IN_MAY	= 0,
+	UPCTL1_C_ACTIVE_IN_WILL,
+
+	UPCTL0_C_ACTIVE_IN_SHIFT = 5,
+	UPCTL0_C_ACTIVE_IN_MASK	= 1,
+	UPCTL0_C_ACTIVE_IN_MAY	= 0,
+	UPCTL0_C_ACTIVE_IN_WILL,
+
+	MSCH1_MAINDDR3_SHIFT	= 4,
+	MSCH1_MAINDDR3_MASK	= 1,
+	MSCH1_MAINDDR3_DDR3	= 1,
+
+	MSCH0_MAINDDR3_SHIFT	= 3,
+	MSCH0_MAINDDR3_MASK	= 1,
+	MSCH0_MAINDDR3_DDR3	= 1,
+
+	MSCH1_MAINPARTIALPOP_SHIFT = 2,
+	MSCH1_MAINPARTIALPOP_MASK = 1,
+
+	MSCH0_MAINPARTIALPOP_SHIFT = 1,
+	MSCH0_MAINPARTIALPOP_MASK = 1,
+};
+
+/* GRF_SOC_CON1 */
+enum {
+	RK3288_RMII_MODE_SHIFT = 14,
+	RK3288_RMII_MODE_MASK  = (1 << RK3288_RMII_MODE_SHIFT),
+	RK3288_RMII_MODE       = (1 << RK3288_RMII_MODE_SHIFT),
+
+	RK3288_GMAC_CLK_SEL_SHIFT = 12,
+	RK3288_GMAC_CLK_SEL_MASK  = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_125M  = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_25M   = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_2_5M  = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
+
+	RK3288_RMII_CLK_SEL_SHIFT = 11,
+	RK3288_RMII_CLK_SEL_MASK  = (1 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_2_5M  = (0 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_25M   = (1 << RK3288_RMII_CLK_SEL_SHIFT),
+
+	GMAC_SPEED_SHIFT	= 0xa,
+	GMAC_SPEED_MASK		= 1,
+	GMAC_SPEED_10M		= 0,
+	GMAC_SPEED_100M,
+
+	GMAC_FLOWCTRL_SHIFT	= 0x9,
+	GMAC_FLOWCTRL_MASK	= 1,
+
+	RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
+	RK3288_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+
+	HOST_REMAP_SHIFT	= 0x5,
+	HOST_REMAP_MASK		= 1
+};
+
+/* GRF_SOC_CON2 */
+enum {
+	UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
+	UPCTL1_LPDDR3_ODT_EN_MASK = 1,
+	UPCTL1_LPDDR3_ODT_EN_ODT = 1,
+
+	UPCTL1_BST_DIABLE_SHIFT	= 0xc,
+	UPCTL1_BST_DIABLE_MASK	= 1,
+	UPCTL1_BST_DIABLE_DISABLE = 1,
+
+	LPDDR3_EN1_SHIFT	= 0xb,
+	LPDDR3_EN1_MASK		= 1,
+	LPDDR3_EN1_LPDDR3	= 1,
+
+	UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
+	UPCTL0_LPDDR3_ODT_EN_MASK = 1,
+	UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
+
+	UPCTL0_BST_DIABLE_SHIFT	= 9,
+	UPCTL0_BST_DIABLE_MASK	= 1,
+	UPCTL0_BST_DIABLE_DISABLE = 1,
+
+	LPDDR3_EN0_SHIFT	= 8,
+	LPDDR3_EN0_MASK		= 1,
+	LPDDR3_EN0_LPDDR3	= 1,
+
+	GRF_POC_FLASH0_CTRL_SHIFT = 7,
+	GRF_POC_FLASH0_CTRL_MASK = 1,
+	GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
+	GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
+
+	SIMCARD_MUX_SHIFT	= 6,
+	SIMCARD_MUX_MASK	= 1,
+	SIMCARD_MUX_USE_A	= 1,
+	SIMCARD_MUX_USE_B	= 0,
+
+	GRF_SPDIF_2CH_EN_SHIFT	= 1,
+	GRF_SPDIF_2CH_EN_MASK	= 1,
+	GRF_SPDIF_2CH_EN_8CH	= 0,
+	GRF_SPDIF_2CH_EN_2CH,
+
+	PWM_SHIFT		= 0,
+	PWM_MASK		= 1,
+	PWM_RK			= 1,
+	PWM_PWM			= 0,
+};
+
+/* GRF_SOC_CON3 */
+enum {
+	RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
+	RK3288_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
+	RK3288_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+	RK3288_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+	RK3288_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
+};
+
+/* GRF_SOC_CON6 */
+enum GRF_SOC_CON6 {
+	RK3288_HDMI_EDP_SEL_SHIFT = 0xf,
+	RK3288_HDMI_EDP_SEL_MASK =
+		1 << RK3288_HDMI_EDP_SEL_SHIFT,
+	RK3288_HDMI_EDP_SEL_EDP = 0,
+	RK3288_HDMI_EDP_SEL_HDMI,
+
+	RK3288_DSI0_DPICOLORM_SHIFT = 0x8,
+	RK3288_DSI0_DPICOLORM_MASK =
+		1 << RK3288_DSI0_DPICOLORM_SHIFT,
+
+	RK3288_DSI0_DPISHUTDN_SHIFT = 0x7,
+	RK3288_DSI0_DPISHUTDN_MASK =
+		1 << RK3288_DSI0_DPISHUTDN_SHIFT,
+
+	RK3288_DSI0_LCDC_SEL_SHIFT = 0x6,
+	RK3288_DSI0_LCDC_SEL_MASK =
+		1 << RK3288_DSI0_LCDC_SEL_SHIFT,
+	RK3288_DSI0_LCDC_SEL_BIG = 0,
+	RK3288_DSI0_LCDC_SEL_LIT = 1,
+
+	RK3288_EDP_LCDC_SEL_SHIFT = 0x5,
+	RK3288_EDP_LCDC_SEL_MASK =
+		1 << RK3288_EDP_LCDC_SEL_SHIFT,
+	RK3288_EDP_LCDC_SEL_BIG = 0,
+	RK3288_EDP_LCDC_SEL_LIT = 1,
+
+	RK3288_HDMI_LCDC_SEL_SHIFT = 0x4,
+	RK3288_HDMI_LCDC_SEL_MASK =
+		1 << RK3288_HDMI_LCDC_SEL_SHIFT,
+	RK3288_HDMI_LCDC_SEL_BIG = 0,
+	RK3288_HDMI_LCDC_SEL_LIT = 1,
+
+	RK3288_LVDS_LCDC_SEL_SHIFT = 0x3,
+	RK3288_LVDS_LCDC_SEL_MASK =
+		1 << RK3288_LVDS_LCDC_SEL_SHIFT,
+	RK3288_LVDS_LCDC_SEL_BIG = 0,
+	RK3288_LVDS_LCDC_SEL_LIT = 1,
+};
+
+/* RK3288_SOC_CON8 */
+enum GRF_SOC_CON8 {
+	RK3288_DPHY_TX0_RXMODE_SHIFT = 4,
+	RK3288_DPHY_TX0_RXMODE_MASK =
+	   0xf << RK3288_DPHY_TX0_RXMODE_SHIFT,
+	RK3288_DPHY_TX0_RXMODE_EN = 0xf,
+	RK3288_DPHY_TX0_RXMODE_DIS = 0,
+
+	RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8,
+	RK3288_DPHY_TX0_TXSTOPMODE_MASK =
+	   0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT,
+	RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf,
+	RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0,
+
+	RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0,
+	RK3288_DPHY_TX0_TURNREQUEST_MASK =
+	   0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT,
+	RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf,
+	RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
+};
+
+/* GRF_IO_VSEL */
+enum {
+	GPIO1830_V18SEL_SHIFT		= 9,
+	GPIO1830_V18SEL_MASK		= 1,
+	GPIO1830_V18SEL_3_3V		= 0,
+	GPIO1830_V18SEL_1_8V,
+
+	GPIO30_V18SEL_SHIFT	= 8,
+	GPIO30_V18SEL_MASK	= 1,
+	GPIO30_V18SEL_3_3V	= 0,
+	GPIO30_V18SEL_1_8V,
+
+	SDCARD_V18SEL_SHIFT	= 7,
+	SDCARD_V18SEL_MASK	= 1,
+	SDCARD_V18SEL_3_3V	= 0,
+	SDCARD_V18SEL_1_8V,
+
+	AUDIO_V18SEL_SHIFT	= 6,
+	AUDIO_V18SEL_MASK	= 1,
+	AUDIO_V18SEL_3_3V	= 0,
+	AUDIO_V18SEL_1_8V,
+
+	BB_V18SEL_SHIFT		= 5,
+	BB_V18SEL_MASK		= 1,
+	BB_V18SEL_3_3V		= 0,
+	BB_V18SEL_1_8V,
+
+	WIFI_V18SEL_SHIFT	= 4,
+	WIFI_V18SEL_MASK	= 1,
+	WIFI_V18SEL_3_3V	= 0,
+	WIFI_V18SEL_1_8V,
+
+	FLASH1_V18SEL_SHIFT	= 3,
+	FLASH1_V18SEL_MASK	= 1,
+	FLASH1_V18SEL_3_3V	= 0,
+	FLASH1_V18SEL_1_8V,
+
+	FLASH0_V18SEL_SHIFT	= 2,
+	FLASH0_V18SEL_MASK	= 1,
+	FLASH0_V18SEL_3_3V	= 0,
+	FLASH0_V18SEL_1_8V,
+
+	DVP_V18SEL_SHIFT	= 1,
+	DVP_V18SEL_MASK		= 1,
+	DVP_V18SEL_3_3V		= 0,
+	DVP_V18SEL_1_8V,
+
+	LCDC_V18SEL_SHIFT	= 0,
+	LCDC_V18SEL_MASK	= 1,
+	LCDC_V18SEL_3_3V	= 0,
+	LCDC_V18SEL_1_8V,
+};
+
+/* GPIO Bias settings */
+enum GPIO_BIAS {
+	GPIO_BIAS_2MA = 0,
+	GPIO_BIAS_4MA,
+	GPIO_BIAS_8MA,
+	GPIO_BIAS_12MA,
+};
+
+#define GPIO_BIAS_MASK	0x3
+#define GPIO_BIAS_SHIFT(x)  ((x) * 2)
+
+#define GPIO_PULL_MASK	0x3
+#define GPIO_PULL_SHIFT(x)  ((x) * 2)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
new file mode 100644
index 0000000..d8a4680
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
+#define __SOC_ROCKCHIP_RK3328_GRF_H__
+
+struct rk3328_grf_regs {
+	u32 gpio0a_iomux;
+	u32 gpio0b_iomux;
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2bl_iomux;
+	u32 gpio2bh_iomux;
+	u32 gpio2cl_iomux;
+	u32 gpio2ch_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3al_iomux;
+	u32 gpio3ah_iomux;
+	u32 gpio3bl_iomux;
+	u32 gpio3bh_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 com_iomux;
+	u32 reserved1[(0x100 - 0x54) / 4];
+
+	u32 gpio0a_p;
+	u32 gpio0b_p;
+	u32 gpio0c_p;
+	u32 gpio0d_p;
+	u32 gpio1a_p;
+	u32 gpio1b_p;
+	u32 gpio1c_p;
+	u32 gpio1d_p;
+	u32 gpio2a_p;
+	u32 gpio2b_p;
+	u32 gpio2c_p;
+	u32 gpio2d_p;
+	u32 gpio3a_p;
+	u32 gpio3b_p;
+	u32 gpio3c_p;
+	u32 gpio3d_p;
+	u32 reserved2[(0x200 - 0x140) / 4];
+	u32 gpio0a_e;
+	u32 gpio0b_e;
+	u32 gpio0c_e;
+	u32 gpio0d_e;
+	u32 gpio1a_e;
+	u32 gpio1b_e;
+	u32 gpio1c_e;
+	u32 gpio1d_e;
+	u32 gpio2a_e;
+	u32 gpio2b_e;
+	u32 gpio2c_e;
+	u32 gpio2d_e;
+	u32 gpio3a_e;
+	u32 gpio3b_e;
+	u32 gpio3c_e;
+	u32 gpio3d_e;
+	u32 reserved3[(0x300 - 0x240) / 4];
+	u32 gpio0l_sr;
+	u32 gpio0h_sr;
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved4[(0x380 - 0x320) / 4];
+	u32 gpio0l_smt;
+	u32 gpio0h_smt;
+	u32 gpio1l_smt;
+	u32 gpio1h_smt;
+	u32 gpio2l_smt;
+	u32 gpio2h_smt;
+	u32 gpio3l_smt;
+	u32 gpio3h_smt;
+	u32 reserved5[(0x400 - 0x3a0) / 4];
+	u32 soc_con[11];
+	u32 reserved6[(0x480 - 0x42c) / 4];
+	u32 soc_status[5];
+	u32 reserved7[(0x4c0 - 0x494) / 4];
+	u32 otg3_con[2];
+	u32 reserved8[(0x500 - 0x4c8) / 4];
+	u32 cpu_con[2];
+	u32 reserved9[(0x520 - 0x508) / 4];
+	u32 cpu_status[2];
+	u32 reserved10[(0x5c8 - 0x528) / 4];
+	u32 os_reg[8];
+	u32 reserved11[(0x680 - 0x5e8) / 4];
+	u32 sig_detect_con;
+	u32 reserved12[3];
+	u32 sig_detect_status;
+	u32 reserved13[3];
+	u32 sig_detect_status_clr;
+	u32 reserved14[3];
+
+	u32 sdmmc_det_counter;
+	u32 reserved15[(0x700 - 0x6b4) / 4];
+	u32 host0_con[3];
+	u32 reserved16[(0x880 - 0x70c) / 4];
+	u32 otg_con0;
+	u32 reserved17[3];
+	u32 host0_status;
+	u32 reserved18[(0x900 - 0x894) / 4];
+	u32 mac_con[3];
+	u32 reserved19[(0xb00 - 0x90c) / 4];
+	u32 macphy_con[4];
+	u32 macphy_status;
+};
+check_member(rk3328_grf_regs, macphy_status, 0xb10);
+
+struct rk3328_sgrf_regs {
+	u32 soc_con[6];
+	u32 reserved0[(0x100 - 0x18) / 4];
+	u32 dmac_con[6];
+	u32 reserved1[(0x180 - 0x118) / 4];
+	u32 fast_boot_addr;
+	u32 reserved2[(0x200 - 0x184) / 4];
+	u32 chip_fuse_con;
+	u32 reserved3[(0x280 - 0x204) / 4];
+	u32 hdcp_key_reg[8];
+	u32 hdcp_key_access_mask;
+};
+check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
+
+#endif	/* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
new file mode 100644
index 0000000..b70b08f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+#ifndef _ASM_ARCH_GRF_RK3368_H
+#define _ASM_ARCH_GRF_RK3368_H
+
+#include <common.h>
+
+struct rk3368_grf {
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 reserved[0x34];
+	u32 gpio1a_pull;
+	u32 gpio1b_pull;
+	u32 gpio1c_pull;
+	u32 gpio1d_pull;
+	u32 gpio2a_pull;
+	u32 gpio2b_pull;
+	u32 gpio2c_pull;
+	u32 gpio2d_pull;
+	u32 gpio3a_pull;
+	u32 gpio3b_pull;
+	u32 gpio3c_pull;
+	u32 gpio3d_pull;
+	u32 reserved1[0x34];
+	u32 gpio1a_drv;
+	u32 gpio1b_drv;
+	u32 gpio1c_drv;
+	u32 gpio1d_drv;
+	u32 gpio2a_drv;
+	u32 gpio2b_drv;
+	u32 gpio2c_drv;
+	u32 gpio2d_drv;
+	u32 gpio3a_drv;
+	u32 gpio3b_drv;
+	u32 gpio3c_drv;
+	u32 gpio3d_drv;
+	u32 reserved2[0x34];
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved3[0x1a];
+	u32 gpio_smt;
+	u32 reserved4[0x1f];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 soc_con16;
+	u32 soc_con17;
+	u32 reserved5[0x6e];
+	u32 ddrc0_con0;
+};
+check_member(rk3368_grf, soc_con17, 0x444);
+check_member(rk3368_grf, ddrc0_con0, 0x600);
+
+struct rk3368_pmu_grf {
+	u32 gpio0a_iomux;
+	u32 gpio0b_iomux;
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+	u32 gpio0a_pull;
+	u32 gpio0b_pull;
+	u32 gpio0c_pull;
+	u32 gpio0d_pull;
+	u32 gpio0a_drv;
+	u32 gpio0b_drv;
+	u32 gpio0c_drv;
+	u32 gpio0d_drv;
+	u32 gpio0l_sr;
+	u32 gpio0h_sr;
+	u32 reserved[0x72];
+	u32 os_reg[4];
+};
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+check_member(rk3368_pmu_grf, os_reg[0], 0x200);
+
+/*GRF_SOC_CON11/12/13*/
+enum {
+	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
+	MCU_SRAM_BASE_BIT27_BIT12_MASK	= GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON12*/
+enum {
+	MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT  = 0,
+	MCU_EXSRAM_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON13*/
+enum {
+	MCU_EXPERI_BASE_BIT27_BIT12_SHIFT  = 0,
+	MCU_EXPERI_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON14*/
+enum {
+	MCU_EXPERI_BASE_BIT31_BIT28_SHIFT	= 12,
+	MCU_EXPERI_BASE_BIT31_BIT28_MASK	= GENMASK(15, 12),
+	MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT	= 8,
+	MCU_EXSRAM_BASE_BIT31_BIT28_MASK	= GENMASK(11, 8),
+	MCU_SRAM_BASE_BIT31_BIT28_SHIFT		= 4,
+	MCU_SRAM_BASE_BIT31_BIT28_MASK		= GENMASK(7, 4),
+	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
+	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
new file mode 100644
index 0000000..dd89cd2
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -0,0 +1,672 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
+#define __SOC_ROCKCHIP_RK3399_GRF_H__
+
+struct rk3399_grf_regs {
+	u32 reserved[0x800];
+	u32 usb3_perf_con0;
+	u32 usb3_perf_con1;
+	u32 usb3_perf_con2;
+	u32 usb3_perf_rd_max_latency_num;
+	u32 usb3_perf_rd_latency_samp_num;
+	u32 usb3_perf_rd_latency_acc_num;
+	u32 usb3_perf_rd_axi_total_byte;
+	u32 usb3_perf_wr_axi_total_byte;
+	u32 usb3_perf_working_cnt;
+	u32 reserved1[0x103];
+	u32 usb3otg0_con0;
+	u32 usb3otg0_con1;
+	u32 reserved2[2];
+	u32 usb3otg1_con0;
+	u32 usb3otg1_con1;
+	u32 reserved3[2];
+	u32 usb3otg0_status_lat0;
+	u32 usb3otg0_status_lat1;
+	u32 usb3otg0_status_cb;
+	u32 reserved4;
+	u32 usb3otg1_status_lat0;
+	u32 usb3otg1_status_lat1;
+	u32 usb3ogt1_status_cb;
+	u32 reserved5[0x6e5];
+	u32 pcie_perf_con0;
+	u32 pcie_perf_con1;
+	u32 pcie_perf_con2;
+	u32 pcie_perf_rd_max_latency_num;
+	u32 pcie_perf_rd_latency_samp_num;
+	u32 pcie_perf_rd_laterncy_acc_num;
+	u32 pcie_perf_rd_axi_total_byte;
+	u32 pcie_perf_wr_axi_total_byte;
+	u32 pcie_perf_working_cnt;
+	u32 reserved6[0x37];
+	u32 usb20_host0_con0;
+	u32 usb20_host0_con1;
+	u32 reserved7[2];
+	u32 usb20_host1_con0;
+	u32 usb20_host1_con1;
+	u32 reserved8[2];
+	u32 hsic_con0;
+	u32 hsic_con1;
+	u32 reserved9[6];
+	u32 grf_usbhost0_status;
+	u32 grf_usbhost1_Status;
+	u32 grf_hsic_status;
+	u32 reserved10[0xc9];
+	u32 hsicphy_con0;
+	u32 reserved11[3];
+	u32 usbphy0_ctrl[26];
+	u32 reserved12[6];
+	u32 usbphy1[26];
+	u32 reserved13[0x72f];
+	u32 soc_con9;
+	u32 reserved14[0x0a];
+	u32 soc_con20;
+	u32 soc_con21;
+	u32 soc_con22;
+	u32 soc_con23;
+	u32 soc_con24;
+	u32 soc_con25;
+	u32 soc_con26;
+	u32 reserved15[0xf65];
+	u32 cpu_con[4];
+	u32 reserved16[0x1c];
+	u32 cpu_status[6];
+	u32 reserved17[0x1a];
+	u32 a53_perf_con[4];
+	u32 a53_perf_rd_mon_st;
+	u32 a53_perf_rd_mon_end;
+	u32 a53_perf_wr_mon_st;
+	u32 a53_perf_wr_mon_end;
+	u32 a53_perf_rd_max_latency_num;
+	u32 a53_perf_rd_latency_samp_num;
+	u32 a53_perf_rd_laterncy_acc_num;
+	u32 a53_perf_rd_axi_total_byte;
+	u32 a53_perf_wr_axi_total_byte;
+	u32 a53_perf_working_cnt;
+	u32 a53_perf_int_status;
+	u32 reserved18[0x31];
+	u32 a72_perf_con[4];
+	u32 a72_perf_rd_mon_st;
+	u32 a72_perf_rd_mon_end;
+	u32 a72_perf_wr_mon_st;
+	u32 a72_perf_wr_mon_end;
+	u32 a72_perf_rd_max_latency_num;
+	u32 a72_perf_rd_latency_samp_num;
+	u32 a72_perf_rd_laterncy_acc_num;
+	u32 a72_perf_rd_axi_total_byte;
+	u32 a72_perf_wr_axi_total_byte;
+	u32 a72_perf_working_cnt;
+	u32 a72_perf_int_status;
+	u32 reserved19[0x7f6];
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 reserved20[0x779];
+	u32 gpio2a_iomux;
+	union {
+		u32 iomux_spi2;
+		u32 gpio2b_iomux;
+	};
+	union {
+		u32 gpio2c_iomux;
+		u32 iomux_spi5;
+	};
+	u32 gpio2d_iomux;
+	union {
+		u32 gpio3a_iomux;
+		u32 iomux_spi0;
+	};
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	union {
+		u32 iomux_i2s0;
+		u32 gpio3d_iomux;
+	};
+	union {
+		u32 iomux_i2sclk;
+		u32 gpio4a_iomux;
+	};
+	union {
+		u32 iomux_sdmmc;
+		u32 iomux_uart2a;
+		u32 gpio4b_iomux;
+	};
+	union {
+		u32 iomux_pwm_0;
+		u32 iomux_pwm_1;
+		u32 iomux_uart2b;
+		u32 iomux_uart2c;
+		u32 iomux_edp_hotplug;
+		u32 gpio4c_iomux;
+	};
+	u32 gpio4d_iomux;
+	u32 reserved21[4];
+	u32 gpio2_p[4];
+	u32 gpio3_p[4];
+	u32 gpio4_p[4];
+	u32 reserved22[4];
+	u32 gpio2_sr[3][4];
+	u32 reserved23[4];
+	u32 gpio2_smt[3][4];
+	u32 reserved24[(0xe100 - 0xe0ec)/4 - 1];
+	u32 gpio2_e[4];
+	u32 gpio3_e[7];
+	u32 gpio4_e[5];
+	u32 reserved24a[(0xe200 - 0xe13c)/4 - 1];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5_pcie;
+	u32 reserved25;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9_pcie;
+	u32 reserved26[0x1e];
+	u32 soc_status[6];
+	u32 reserved27[0x32];
+	u32 ddrc0_con0;
+	u32 ddrc0_con1;
+	u32 ddrc1_con0;
+	u32 ddrc1_con1;
+	u32 reserved28[0xac];
+	u32 io_vsel;
+	u32 saradc_testbit;
+	u32 tsadc_testbit_l;
+	u32 tsadc_testbit_h;
+	u32 reserved29[0x6c];
+	u32 chip_id_addr;
+	u32 reserved30[0x1f];
+	u32 fast_boot_addr;
+	u32 reserved31[0x1df];
+	u32 emmccore_con[12];
+	u32 reserved32[4];
+	u32 emmccore_status[4];
+	u32 reserved33[0x1cc];
+	u32 emmcphy_con[7];
+	u32 reserved34;
+	u32 emmcphy_status;
+};
+check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
+
+struct rk3399_pmugrf_regs {
+	union {
+		u32 iomux_pwm_3a;
+		u32 gpio0a_iomux;
+	};
+	u32 gpio0b_iomux;
+	u32 reserved0[2];
+	union {
+		u32 spi1_rxd;
+		u32 tsadc_int;
+		u32 gpio1a_iomux;
+	};
+	union {
+		u32 spi1_csclktx;
+		u32 iomux_pwm_3b;
+		u32 iomux_i2c0_sda;
+		u32 gpio1b_iomux;
+	};
+	union {
+		u32 iomux_pwm_2;
+		u32 iomux_i2c0_scl;
+		u32 gpio1c_iomux;
+	};
+	u32 gpio1d_iomux;
+	u32 reserved1[8];
+	u32 gpio0_p[2];
+	u32 reserved2[2];
+	u32 gpio1_p[4];
+	u32 reserved3[8];
+	u32 gpio0a_e;
+	u32 reserved4;
+	u32 gpio0b_e;
+	u32 reserved5[5];
+	u32 gpio1a_e;
+	u32 reserved6;
+	u32 gpio1b_e;
+	u32 reserved7;
+	u32 gpio1c_e;
+	u32 reserved8;
+	u32 gpio1d_e;
+	u32 reserved9[0x11];
+	u32 gpio0l_sr;
+	u32 reserved10;
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 reserved11[4];
+	u32 gpio0a_smt;
+	u32 gpio0b_smt;
+	u32 reserved12[2];
+	u32 gpio1a_smt;
+	u32 gpio1b_smt;
+	u32 gpio1c_smt;
+	u32 gpio1d_smt;
+	u32 reserved13[8];
+	u32 gpio0l_he;
+	u32 reserved14;
+	u32 gpio1l_he;
+	u32 gpio1h_he;
+	u32 reserved15[4];
+	u32 soc_con0;
+	u32 reserved16[9];
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 reserved17[0x24];
+	u32 pmupvtm_con0;
+	u32 pmupvtm_con1;
+	u32 pmupvtm_status0;
+	u32 pmupvtm_status1;
+	u32 grf_osc_e;
+	u32 reserved18[0x2b];
+	u32 os_reg0;
+	u32 os_reg1;
+	u32 os_reg2;
+	u32 os_reg3;
+};
+check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
+
+struct rk3399_pmusgrf_regs {
+	u32 ddr_rgn_con[35];
+	u32 reserved[0x1fe5];
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 reserved1[3];
+	u32 soc_con19;
+	u32 soc_con20;
+	u32 soc_con21;
+	u32 soc_con22;
+	u32 reserved2[0x29];
+	u32 perilp_con[9];
+	u32 reserved4[7];
+	u32 perilp_status;
+	u32 reserved5[0xfaf];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 reserved6[0x3e];
+	u32 pmu_con[9];
+	u32 reserved7[0x17];
+	u32 fast_boot_addr;
+	u32 reserved8[0x1f];
+	u32 efuse_prg_mask;
+	u32 efuse_read_mask;
+	u32 reserved9[0x0e];
+	u32 pmu_slv_con0;
+	u32 pmu_slv_con1;
+	u32 reserved10[0x771];
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 reserved11[8];
+	u32 soc_con16;
+	u32 soc_con17;
+	u32 soc_con18;
+	u32 reserved12[0xdd];
+	u32 slv_secure_con0;
+	u32 slv_secure_con1;
+	u32 reserved13;
+	u32 slv_secure_con2;
+	u32 slv_secure_con3;
+	u32 slv_secure_con4;
+};
+check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
+
+enum {
+	/* GRF_GPIO2A_IOMUX */
+	GRF_GPIO2A0_SEL_SHIFT   = 0,
+	GRF_GPIO2A0_SEL_MASK    = 3 << GRF_GPIO2A0_SEL_SHIFT,
+	GRF_I2C2_SDA            = 2,
+	GRF_GPIO2A1_SEL_SHIFT   = 2,
+	GRF_GPIO2A1_SEL_MASK    = 3 << GRF_GPIO2A1_SEL_SHIFT,
+	GRF_I2C2_SCL            = 2,
+	GRF_GPIO2A7_SEL_SHIFT   = 14,
+	GRF_GPIO2A7_SEL_MASK    = 3 << GRF_GPIO2A7_SEL_SHIFT,
+	GRF_I2C7_SDA            = 2,
+
+	/* GRF_GPIO2B_IOMUX */
+	GRF_GPIO2B0_SEL_SHIFT   = 0,
+	GRF_GPIO2B0_SEL_MASK    = 3 << GRF_GPIO2B0_SEL_SHIFT,
+	GRF_I2C7_SCL            = 2,
+	GRF_GPIO2B1_SEL_SHIFT	= 2,
+	GRF_GPIO2B1_SEL_MASK	= 3 << GRF_GPIO2B1_SEL_SHIFT,
+	GRF_SPI2TPM_RXD		= 1,
+	GRF_I2C6_SDA            = 2,
+	GRF_GPIO2B2_SEL_SHIFT	= 4,
+	GRF_GPIO2B2_SEL_MASK	= 3 << GRF_GPIO2B2_SEL_SHIFT,
+	GRF_SPI2TPM_TXD		= 1,
+	GRF_I2C6_SCL            = 2,
+	GRF_GPIO2B3_SEL_SHIFT	= 6,
+	GRF_GPIO2B3_SEL_MASK	= 3 << GRF_GPIO2B3_SEL_SHIFT,
+	GRF_SPI2TPM_CLK		= 1,
+	GRF_GPIO2B4_SEL_SHIFT	= 8,
+	GRF_GPIO2B4_SEL_MASK	= 3 << GRF_GPIO2B4_SEL_SHIFT,
+	GRF_SPI2TPM_CSN0	= 1,
+
+	/* GRF_GPIO2C_IOMUX */
+	GRF_GPIO2C0_SEL_SHIFT   = 0,
+	GRF_GPIO2C0_SEL_MASK    = 3 << GRF_GPIO2C0_SEL_SHIFT,
+	GRF_UART0BT_SIN         = 1,
+	GRF_GPIO2C1_SEL_SHIFT   = 2,
+	GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
+	GRF_UART0BT_SOUT        = 1,
+	GRF_GPIO2C4_SEL_SHIFT   = 8,
+	GRF_GPIO2C4_SEL_MASK    = 3 << GRF_GPIO2C4_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_RXD     = 2,
+	GRF_GPIO2C5_SEL_SHIFT   = 10,
+	GRF_GPIO2C5_SEL_MASK    = 3 << GRF_GPIO2C5_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_TXD     = 2,
+	GRF_GPIO2C6_SEL_SHIFT   = 12,
+	GRF_GPIO2C6_SEL_MASK    = 3 << GRF_GPIO2C6_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CLK     = 2,
+	GRF_GPIO2C7_SEL_SHIFT   = 14,
+	GRF_GPIO2C7_SEL_MASK    = 3 << GRF_GPIO2C7_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CSN0    = 2,
+
+	/* GRF_GPIO3A_IOMUX */
+	GRF_GPIO3A0_SEL_SHIFT   = 0,
+	GRF_GPIO3A0_SEL_MASK    = 3 << GRF_GPIO3A0_SEL_SHIFT,
+	GRF_MAC_TXD2            = 1,
+	GRF_GPIO3A1_SEL_SHIFT   = 2,
+	GRF_GPIO3A1_SEL_MASK    = 3 << GRF_GPIO3A1_SEL_SHIFT,
+	GRF_MAC_TXD3            = 1,
+	GRF_GPIO3A2_SEL_SHIFT   = 4,
+	GRF_GPIO3A2_SEL_MASK    = 3 << GRF_GPIO3A2_SEL_SHIFT,
+	GRF_MAC_RXD2            = 1,
+	GRF_GPIO3A3_SEL_SHIFT   = 6,
+	GRF_GPIO3A3_SEL_MASK    = 3 << GRF_GPIO3A3_SEL_SHIFT,
+	GRF_MAC_RXD3            = 1,
+	GRF_GPIO3A4_SEL_SHIFT	= 8,
+	GRF_GPIO3A4_SEL_MASK	= 3 << GRF_GPIO3A4_SEL_SHIFT,
+	GRF_MAC_TXD0            = 1,
+	GRF_SPI0NORCODEC_RXD	= 2,
+	GRF_GPIO3A5_SEL_SHIFT	= 10,
+	GRF_GPIO3A5_SEL_MASK	= 3 << GRF_GPIO3A5_SEL_SHIFT,
+	GRF_MAC_TXD1            = 1,
+	GRF_SPI0NORCODEC_TXD	= 2,
+	GRF_GPIO3A6_SEL_SHIFT	= 12,
+	GRF_GPIO3A6_SEL_MASK	= 3 << GRF_GPIO3A6_SEL_SHIFT,
+	GRF_MAC_RXD0            = 1,
+	GRF_SPI0NORCODEC_CLK	= 2,
+	GRF_GPIO3A7_SEL_SHIFT	= 14,
+	GRF_GPIO3A7_SEL_MASK	= 3 << GRF_GPIO3A7_SEL_SHIFT,
+	GRF_MAC_RXD1            = 1,
+	GRF_SPI0NORCODEC_CSN0	= 2,
+
+	/* GRF_GPIO3B_IOMUX */
+	GRF_GPIO3B0_SEL_SHIFT	= 0,
+	GRF_GPIO3B0_SEL_MASK	= 3 << GRF_GPIO3B0_SEL_SHIFT,
+	GRF_MAC_MDC             = 1,
+	GRF_SPI0NORCODEC_CSN1	= 2,
+	GRF_GPIO3B1_SEL_SHIFT	= 2,
+	GRF_GPIO3B1_SEL_MASK	= 3 << GRF_GPIO3B1_SEL_SHIFT,
+	GRF_MAC_RXDV            = 1,
+	GRF_GPIO3B3_SEL_SHIFT	= 6,
+	GRF_GPIO3B3_SEL_MASK	= 3 << GRF_GPIO3B3_SEL_SHIFT,
+	GRF_MAC_CLK             = 1,
+	GRF_GPIO3B4_SEL_SHIFT	= 8,
+	GRF_GPIO3B4_SEL_MASK	= 3 << GRF_GPIO3B4_SEL_SHIFT,
+	GRF_MAC_TXEN            = 1,
+	GRF_GPIO3B5_SEL_SHIFT	= 10,
+	GRF_GPIO3B5_SEL_MASK	= 3 << GRF_GPIO3B5_SEL_SHIFT,
+	GRF_MAC_MDIO            = 1,
+	GRF_GPIO3B6_SEL_SHIFT   = 12,
+	GRF_GPIO3B6_SEL_MASK    = 3 << GRF_GPIO3B6_SEL_SHIFT,
+	GRF_MAC_RXCLK           = 1,
+	GRF_UART3_SIN           = 2,
+	GRF_GPIO3B7_SEL_SHIFT   = 14,
+	GRF_GPIO3B7_SEL_MASK    = 3 << GRF_GPIO3B7_SEL_SHIFT,
+	GRF_UART3_SOUT          = 2,
+
+	/* GRF_GPIO3C_IOMUX */
+	GRF_GPIO3C1_SEL_SHIFT	= 2,
+	GRF_GPIO3C1_SEL_MASK	= 3 << GRF_GPIO3C1_SEL_SHIFT,
+	GRF_MAC_TXCLK           = 1,
+
+	/* GRF_GPIO4A_IOMUX */
+	GRF_GPIO4A1_SEL_SHIFT   = 2,
+	GRF_GPIO4A1_SEL_MASK    = 3 << GRF_GPIO4A1_SEL_SHIFT,
+	GRF_I2C1_SDA            = 1,
+	GRF_GPIO4A2_SEL_SHIFT   = 4,
+	GRF_GPIO4A2_SEL_MASK    = 3 << GRF_GPIO4A2_SEL_SHIFT,
+	GRF_I2C1_SCL            = 1,
+
+	/* GRF_GPIO4B_IOMUX */
+	GRF_GPIO4B0_SEL_SHIFT	= 0,
+	GRF_GPIO4B0_SEL_MASK	= 3 << GRF_GPIO4B0_SEL_SHIFT,
+	GRF_SDMMC_DATA0		= 1,
+	GRF_UART2DBGA_SIN	= 2,
+	GRF_GPIO4B1_SEL_SHIFT	= 2,
+	GRF_GPIO4B1_SEL_MASK	= 3 << GRF_GPIO4B1_SEL_SHIFT,
+	GRF_SDMMC_DATA1		= 1,
+	GRF_UART2DBGA_SOUT	= 2,
+	GRF_GPIO4B2_SEL_SHIFT	= 4,
+	GRF_GPIO4B2_SEL_MASK	= 3 << GRF_GPIO4B2_SEL_SHIFT,
+	GRF_SDMMC_DATA2		= 1,
+	GRF_GPIO4B3_SEL_SHIFT	= 6,
+	GRF_GPIO4B3_SEL_MASK	= 3 << GRF_GPIO4B3_SEL_SHIFT,
+	GRF_SDMMC_DATA3		= 1,
+	GRF_GPIO4B4_SEL_SHIFT	= 8,
+	GRF_GPIO4B4_SEL_MASK    = 3 << GRF_GPIO4B4_SEL_SHIFT,
+	GRF_SDMMC_CLKOUT        = 1,
+	GRF_GPIO4B5_SEL_SHIFT   = 10,
+	GRF_GPIO4B5_SEL_MASK    = 3 << GRF_GPIO4B5_SEL_SHIFT,
+	GRF_SDMMC_CMD           = 1,
+
+	/*  GRF_GPIO4C_IOMUX */
+	GRF_GPIO4C0_SEL_SHIFT   = 0,
+	GRF_GPIO4C0_SEL_MASK    = 3 << GRF_GPIO4C0_SEL_SHIFT,
+	GRF_UART2DGBB_SIN       = 2,
+	GRF_HDMII2C_SCL         = 3,
+	GRF_GPIO4C1_SEL_SHIFT   = 2,
+	GRF_GPIO4C1_SEL_MASK    = 3 << GRF_GPIO4C1_SEL_SHIFT,
+	GRF_UART2DGBB_SOUT      = 2,
+	GRF_HDMII2C_SDA         = 3,
+	GRF_GPIO4C2_SEL_SHIFT   = 4,
+	GRF_GPIO4C2_SEL_MASK    = 3 << GRF_GPIO4C2_SEL_SHIFT,
+	GRF_PWM_0               = 1,
+	GRF_GPIO4C3_SEL_SHIFT   = 6,
+	GRF_GPIO4C3_SEL_MASK    = 3 << GRF_GPIO4C3_SEL_SHIFT,
+	GRF_UART2DGBC_SIN       = 1,
+	GRF_GPIO4C4_SEL_SHIFT   = 8,
+	GRF_GPIO4C4_SEL_MASK    = 3 << GRF_GPIO4C4_SEL_SHIFT,
+	GRF_UART2DBGC_SOUT      = 1,
+	GRF_GPIO4C6_SEL_SHIFT   = 12,
+	GRF_GPIO4C6_SEL_MASK    = 3 << GRF_GPIO4C6_SEL_SHIFT,
+	GRF_PWM_1               = 1,
+
+	/* GRF_GPIO3A_E01 */
+	GRF_GPIO3A0_E_SHIFT = 0,
+	GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT,
+	GRF_GPIO3A1_E_SHIFT = 3,
+	GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT,
+	GRF_GPIO3A2_E_SHIFT = 6,
+	GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT,
+	GRF_GPIO3A3_E_SHIFT = 9,
+	GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT,
+	GRF_GPIO3A4_E_SHIFT = 12,
+	GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT,
+	GRF_GPIO3A5_E0_SHIFT = 15,
+	GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT,
+
+	/*  GRF_GPIO3A_E2 */
+	GRF_GPIO3A5_E12_SHIFT = 0,
+	GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
+	GRF_GPIO3A6_E_SHIFT = 2,
+	GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT,
+	GRF_GPIO3A7_E_SHIFT = 5,
+	GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT,
+
+	/* GRF_GPIO3B_E01 */
+	GRF_GPIO3B0_E_SHIFT = 0,
+	GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT,
+	GRF_GPIO3B1_E_SHIFT = 3,
+	GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT,
+	GRF_GPIO3B2_E_SHIFT = 6,
+	GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT,
+	GRF_GPIO3B3_E_SHIFT = 9,
+	GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT,
+	GRF_GPIO3B4_E_SHIFT = 12,
+	GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT,
+	GRF_GPIO3B5_E0_SHIFT = 15,
+	GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT,
+
+	/*  GRF_GPIO3A_E2 */
+	GRF_GPIO3B5_E12_SHIFT = 0,
+	GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
+	GRF_GPIO3B6_E_SHIFT = 2,
+	GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT,
+	GRF_GPIO3B7_E_SHIFT = 5,
+	GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT,
+
+	/* GRF_GPIO3C_E01 */
+	GRF_GPIO3C0_E_SHIFT = 0,
+	GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT,
+	GRF_GPIO3C1_E_SHIFT = 3,
+	GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT,
+	GRF_GPIO3C2_E_SHIFT = 6,
+	GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT,
+	GRF_GPIO3C3_E_SHIFT = 9,
+	GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT,
+	GRF_GPIO3C4_E_SHIFT = 12,
+	GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT,
+	GRF_GPIO3C5_E0_SHIFT = 15,
+	GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT,
+
+	/*  GRF_GPIO3C_E2 */
+	GRF_GPIO3C5_E12_SHIFT = 0,
+	GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
+	GRF_GPIO3C6_E_SHIFT = 2,
+	GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT,
+	GRF_GPIO3C7_E_SHIFT = 5,
+	GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
+
+	/* GRF_SOC_CON7 */
+	GRF_UART_DBG_SEL_SHIFT  = 10,
+	GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
+	GRF_UART_DBG_SEL_C      = 2,
+
+	/* GRF_SOC_CON20 */
+	GRF_DSI0_VOP_SEL_SHIFT  = 0,
+	GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+	GRF_DSI0_VOP_SEL_B      = 0,
+	GRF_DSI0_VOP_SEL_L      = 1,
+	GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6,
+	GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6,
+	GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6,
+
+	/* GRF_SOC_CON22 */
+	GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+	GRF_DPHY_TX0_RXMODE_MASK  = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+	GRF_DPHY_TX0_RXMODE_EN    = 0xb,
+	GRF_DPHY_TX0_RXMODE_DIS   = 0,
+
+	GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+	GRF_DPHY_TX0_TXSTOPMODE_MASK  = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+	GRF_DPHY_TX0_TXSTOPMODE_EN    = 0xc,
+	GRF_DPHY_TX0_TXSTOPMODE_DIS   = 0,
+
+	GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+	GRF_DPHY_TX0_TURNREQUEST_MASK  =
+		0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+	GRF_DPHY_TX0_TURNREQUEST_EN    = 0x1,
+	GRF_DPHY_TX0_TURNREQUEST_DIS   = 0,
+
+	/*  PMUGRF_GPIO0A_IOMUX */
+	PMUGRF_GPIO0A6_SEL_SHIFT        = 12,
+	PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
+	PMUGRF_PWM_3A           = 1,
+
+	/*  PMUGRF_GPIO1A_IOMUX */
+	PMUGRF_GPIO1A7_SEL_SHIFT        = 14,
+	PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
+	PMUGRF_SPI1EC_RXD       = 2,
+
+	/*  PMUGRF_GPIO1B_IOMUX */
+	PMUGRF_GPIO1B0_SEL_SHIFT        = 0,
+	PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
+	PMUGRF_SPI1EC_TXD       = 2,
+	PMUGRF_GPIO1B1_SEL_SHIFT        = 2,
+	PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
+	PMUGRF_SPI1EC_CLK       = 2,
+	PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
+	PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
+	PMUGRF_SPI1EC_CSN0      = 2,
+	PMUGRF_GPIO1B3_SEL_SHIFT	= 6,
+	PMUGRF_GPIO1B3_SEL_MASK	= 3 << PMUGRF_GPIO1B3_SEL_SHIFT,
+	PMUGRF_I2C4_SDA         = 1,
+	PMUGRF_GPIO1B4_SEL_SHIFT        = 8,
+	PMUGRF_GPIO1B4_SEL_MASK	= 3 << PMUGRF_GPIO1B4_SEL_SHIFT,
+	PMUGRF_I2C4_SCL	        = 1,
+	PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
+	PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
+	PMUGRF_PWM_3B           = 1,
+	PMUGRF_GPIO1B7_SEL_SHIFT        = 14,
+	PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
+	PMUGRF_I2C0PMU_SDA      = 2,
+
+	/*  PMUGRF_GPIO1C_IOMUX */
+	PMUGRF_GPIO1C0_SEL_SHIFT        = 0,
+	PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
+	PMUGRF_I2C0PMU_SCL      = 2,
+	PMUGRF_GPIO1C3_SEL_SHIFT        = 6,
+	PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
+	PMUGRF_PWM_2            = 1,
+	PMUGRF_GPIO1C4_SEL_SHIFT = 8,
+	PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT,
+	PMUGRF_I2C8PMU_SDA = 1,
+	PMUGRF_GPIO1C5_SEL_SHIFT = 10,
+	PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT,
+	PMUGRF_I2C8PMU_SCL = 1,
+};
+
+/* GRF_SOC_CON5 */
+enum {
+	RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
+	RK3399_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+
+	RK3399_GMAC_CLK_SEL_SHIFT = 4,
+	RK3399_GMAC_CLK_SEL_MASK  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_125M  = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_25M	  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_2_5M  = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
+};
+
+/* GRF_SOC_CON6 */
+enum {
+	RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
+	RK3399_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_TXCLK_DLY_ENA_GMAC_SHIFT	= 7,
+	RK3399_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+	RK3399_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+	RK3399_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
+};
+
+#endif	/* __SOC_ROCKCHIP_RK3399_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
new file mode 100644
index 0000000..9f42fbd
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_GRF_RV1108_H
+#define _ASM_ARCH_GRF_RV1108_H
+
+#include <common.h>
+
+struct rv1108_grf {
+	u32 reserved[4];
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 reserved1[52];
+	u32 gpio1a_pull;
+	u32 gpio1b_pull;
+	u32 gpio1c_pull;
+	u32 gpio1d_pull;
+	u32 gpio2a_pull;
+	u32 gpio2b_pull;
+	u32 gpio2c_pull;
+	u32 gpio2d_pull;
+	u32 gpio3a_pull;
+	u32 gpio3b_pull;
+	u32 gpio3c_pull;
+	u32 gpio3d_pull;
+	u32 reserved2[52];
+	u32 gpio1a_drv;
+	u32 gpio1b_drv;
+	u32 gpio1c_drv;
+	u32 gpio1d_drv;
+	u32 gpio2a_drv;
+	u32 gpio2b_drv;
+	u32 gpio2c_drv;
+	u32 gpio2d_drv;
+	u32 gpio3a_drv;
+	u32 gpio3b_drv;
+	u32 gpio3c_drv;
+	u32 gpio3d_drv;
+	u32 reserved3[50];
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved4[26];
+	u32 gpio1l_smt;
+	u32 gpio1h_smt;
+	u32 gpio2l_smt;
+	u32 gpio2h_smt;
+	u32 gpio3l_smt;
+	u32 gpio3h_smt;
+	u32 reserved5[24];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 reserved6[20];
+	u32 soc_status0;
+	u32 soc_status1;
+	u32 reserved7[30];
+	u32 cpu_con0;
+	u32 cpu_con1;
+	u32 reserved8[30];
+	u32 os_reg0;
+	u32 os_reg1;
+	u32 os_reg2;
+	u32 os_reg3;
+	u32 reserved9[29];
+	u32 ddr_status;
+	u32 reserved10[30];
+	u32 sig_det_con;
+	u32 reserved11[3];
+	u32 sig_det_status;
+	u32 reserved12[3];
+	u32 sig_det_clr;
+	u32 reserved13[23];
+	u32 host_con0;
+	u32 host_con1;
+	u32 reserved14[2];
+	u32 dma_con0;
+	u32 dma_con1;
+	u32 reserved15[59];
+	u32 uoc_status;
+	u32 reserved16[2];
+	u32 host_status;
+	u32 reserved17[59];
+	u32 gmac_con0;
+	u32 reserved18[191];
+	u32 chip_id;
+};
+
+check_member(rv1108_grf, chip_id, 0x0c00);
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h
new file mode 100644
index 0000000..62e8bed
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/hardware.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define RK_CLRSETBITS(clr, set)		((((clr) | (set)) << 16) | (set))
+#define RK_SETBITS(set)			RK_CLRSETBITS(0, set)
+#define RK_CLRBITS(clr)			RK_CLRSETBITS(clr, 0)
+
+#define rk_clrsetreg(addr, clr, set)	\
+				writel(((clr) | (set)) << 16 | (set), addr)
+#define rk_clrreg(addr, clr)		writel((clr) << 16, addr)
+#define rk_setreg(addr, set)		writel((set) << 16 | (set), addr)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/i2c.h b/arch/arm/include/asm/arch-rockchip/i2c.h
new file mode 100644
index 0000000..b0e1936
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/i2c.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ */
+
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
+
+struct i2c_regs {
+	u32 con;
+	u32 clkdiv;
+	u32 mrxaddr;
+	u32 mrxraddr;
+	u32 mtxcnt;
+	u32 mrxcnt;
+	u32 ien;
+	u32 ipd;
+	u32 fcnt;
+	u32 reserved0[0x37];
+	u32 txdata[8];
+	u32 reserved1[0x38];
+	u32 rxdata[8];
+};
+
+/* Control register */
+#define I2C_CON_EN		(1 << 0)
+#define I2C_CON_MOD(mod)	((mod) << 1)
+#define I2C_MODE_TX		0x00
+#define I2C_MODE_TRX		0x01
+#define I2C_MODE_RX		0x02
+#define I2C_MODE_RRX		0x03
+#define I2C_CON_MASK		(3 << 1)
+
+#define I2C_CON_START		(1 << 3)
+#define I2C_CON_STOP		(1 << 4)
+#define I2C_CON_LASTACK		(1 << 5)
+#define I2C_CON_ACTACK		(1 << 6)
+
+/* Clock dividor register */
+#define I2C_CLKDIV_VAL(divl, divh) \
+	(((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
+
+/* the slave address accessed  for master rx mode */
+#define I2C_MRXADDR_SET(vld, addr)	(((vld) << 24) | (addr))
+
+/* the slave register address accessed  for master rx mode */
+#define I2C_MRXRADDR_SET(vld, raddr)	(((vld) << 24) | (raddr))
+
+/* interrupt enable register */
+#define I2C_BTFIEN		(1 << 0)
+#define I2C_BRFIEN		(1 << 1)
+#define I2C_MBTFIEN		(1 << 2)
+#define I2C_MBRFIEN		(1 << 3)
+#define I2C_STARTIEN		(1 << 4)
+#define I2C_STOPIEN		(1 << 5)
+#define I2C_NAKRCVIEN		(1 << 6)
+
+/* interrupt pending register */
+#define I2C_BTFIPD              (1 << 0)
+#define I2C_BRFIPD              (1 << 1)
+#define I2C_MBTFIPD             (1 << 2)
+#define I2C_MBRFIPD             (1 << 3)
+#define I2C_STARTIPD            (1 << 4)
+#define I2C_STOPIPD             (1 << 5)
+#define I2C_NAKRCVIPD           (1 << 6)
+#define I2C_IPD_ALL_CLEAN       0x7f
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
new file mode 100644
index 0000000..0f00df6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_LVDS_RK3288_H
+#define _ASM_ARCH_LVDS_RK3288_H
+
+#define RK3288_LVDS_CH0_REG0			0x00
+#define RK3288_LVDS_CH0_REG0_LVDS_EN		BIT(7)
+#define RK3288_LVDS_CH0_REG0_TTL_EN		BIT(6)
+#define RK3288_LVDS_CH0_REG0_LANECK_EN		BIT(5)
+#define RK3288_LVDS_CH0_REG0_LANE4_EN		BIT(4)
+#define RK3288_LVDS_CH0_REG0_LANE3_EN		BIT(3)
+#define RK3288_LVDS_CH0_REG0_LANE2_EN		BIT(2)
+#define RK3288_LVDS_CH0_REG0_LANE1_EN		BIT(1)
+#define RK3288_LVDS_CH0_REG0_LANE0_EN		BIT(0)
+
+#define RK3288_LVDS_CH0_REG1			0x04
+#define RK3288_LVDS_CH0_REG1_LANECK_BIAS	BIT(5)
+#define RK3288_LVDS_CH0_REG1_LANE4_BIAS		BIT(4)
+#define RK3288_LVDS_CH0_REG1_LANE3_BIAS		BIT(3)
+#define RK3288_LVDS_CH0_REG1_LANE2_BIAS		BIT(2)
+#define RK3288_LVDS_CH0_REG1_LANE1_BIAS		BIT(1)
+#define RK3288_LVDS_CH0_REG1_LANE0_BIAS		BIT(0)
+
+#define RK3288_LVDS_CH0_REG2			0x08
+#define RK3288_LVDS_CH0_REG2_RESERVE_ON		BIT(7)
+#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE	BIT(6)
+#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE	BIT(5)
+#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE	BIT(4)
+#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE	BIT(3)
+#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE	BIT(2)
+#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE	BIT(1)
+#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8		BIT(0)
+
+#define RK3288_LVDS_CH0_REG3			0x0c
+#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK	0xff
+
+#define RK3288_LVDS_CH0_REG4			0x10
+#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE	BIT(5)
+#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE	BIT(4)
+#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE	BIT(3)
+#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE	BIT(2)
+#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE	BIT(1)
+#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE	BIT(0)
+
+#define RK3288_LVDS_CH0_REG5			0x14
+#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA	BIT(5)
+#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA	BIT(4)
+#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA	BIT(3)
+#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA	BIT(2)
+#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA	BIT(1)
+#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA	BIT(0)
+
+#define RK3288_LVDS_CFG_REGC			0x30
+#define RK3288_LVDS_CFG_REGC_PLL_ENABLE		0x00
+#define RK3288_LVDS_CFG_REGC_PLL_DISABLE	0xff
+
+#define RK3288_LVDS_CH0_REGD			0x34
+#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK	0x1f
+
+#define RK3288_LVDS_CH0_REG20			0x80
+#define RK3288_LVDS_CH0_REG20_MSB		0x45
+#define RK3288_LVDS_CH0_REG20_LSB		0x44
+
+#define RK3288_LVDS_CFG_REG21			0x84
+#define RK3288_LVDS_CFG_REG21_TX_ENABLE		0x92
+#define RK3288_LVDS_CFG_REG21_TX_DISABLE	0x00
+
+/* fbdiv value is split over 2 registers, with bit8 in reg2 */
+#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
+		(_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
+#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
+		(_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
+#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
+		(_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
+
+#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT	BIT(3)
+
+#define LVDS_FMT_MASK			(7 << 16)
+#define LVDS_MSB			(1 << 3)
+#define LVDS_DUAL			(1 << 4)
+#define LVDS_FMT_1			(1 << 5)
+#define LVDS_TTL_EN			(1 << 6)
+#define LVDS_START_PHASE_RST_1		(1 << 7)
+#define LVDS_DCLK_INV			(1 << 8)
+#define LVDS_CH0_EN			(1 << 11)
+#define LVDS_CH1_EN			(1 << 12)
+#define LVDS_PWRDN			(1 << 15)
+
+#define LVDS_24BIT		(0 << 1)
+#define LVDS_18BIT		(1 << 1)
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h
new file mode 100644
index 0000000..b6b03c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/misc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ *      Rohan Garg <rohan.garg@collabora.com>
+ */
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+			      const u32 cpuid_length,
+			      u8 *cpuid);
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
+int rockchip_setup_macaddr(void);
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
new file mode 100644
index 0000000..2191b7d
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * The peripherals supported by the hardware. This is used to specify clocks
+ * and pinctrl settings. Some SoCs will not support all of these, but it
+ * provides a common reference for common drivers to use.
+ */
+enum periph_id {
+	PERIPH_ID_PWM0,
+	PERIPH_ID_PWM1,
+	PERIPH_ID_PWM2,
+	PERIPH_ID_PWM3,
+	PERIPH_ID_PWM4,
+	PERIPH_ID_I2C0,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_I2C4,
+	PERIPH_ID_I2C5,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_I2C7,
+	PERIPH_ID_I2C8,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SPI2,
+	PERIPH_ID_SPI3,
+	PERIPH_ID_SPI4,
+	PERIPH_ID_SPI5,
+	PERIPH_ID_UART0,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+	PERIPH_ID_UART3,
+	PERIPH_ID_UART4,
+	PERIPH_ID_LCDC0,
+	PERIPH_ID_LCDC1,
+	PERIPH_ID_SDMMC0,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_GMAC,
+	PERIPH_ID_SFC,
+	PERIPH_ID_I2S,
+
+	PERIPH_ID_COUNT,
+
+	/* Some aliases */
+	PERIPH_ID_EMMC = PERIPH_ID_SDMMC0,
+	PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1,
+	PERIPH_ID_UART_BT = PERIPH_ID_UART0,
+	PERIPH_ID_UART_BB = PERIPH_ID_UART1,
+	PERIPH_ID_UART_DBG = PERIPH_ID_UART2,
+	PERIPH_ID_UART_GPS = PERIPH_ID_UART3,
+	PERIPH_ID_UART_EXP = PERIPH_ID_UART4,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
new file mode 100644
index 0000000..f7b9a06
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _ASM_ARCH_PMU_RK3188_H
+#define _ASM_ARCH_PMU_RK3188_H
+
+struct rk3188_pmu {
+	u32 wakeup_cfg[2];
+	u32 pwrdn_con;
+	u32 pwrdn_st;
+
+	u32 int_con;
+	u32 int_st;
+	u32 misc_con;
+
+	u32 osc_cnt;
+	u32 pll_cnt;
+	u32 pmu_cnt;
+	u32 ddrio_pwron_cnt;
+	u32 wakeup_rst_clr_cnt;
+	u32 scu_pwrdwn_cnt;
+	u32 scu_pwrup_cnt;
+	u32 misc_con1;
+	u32 gpio0_con;
+
+	u32 sys_reg[4];
+	u32 reserved0[4];
+	u32 stop_int_dly;
+	u32 gpio0_p[2];
+};
+check_member(rk3188_pmu, gpio0_p[1], 0x0068);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
new file mode 100644
index 0000000..8553d2e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_PMU_RK3288_H
+#define _ASM_ARCH_PMU_RK3288_H
+
+struct rk3288_pmu {
+	u32 wakeup_cfg[2];
+	u32 pwrdn_con;
+	u32 pwrdn_st;
+
+	u32 idle_req;
+	u32 idle_st;
+	u32 pwrmode_con;
+	u32 pwr_state;
+
+	u32 osc_cnt;
+	u32 pll_cnt;
+	u32 stabl_cnt;
+	u32 ddr0io_pwron_cnt;
+
+	u32 ddr1io_pwron_cnt;
+	u32 core_pwrdn_cnt;
+	u32 core_pwrup_cnt;
+	u32 gpu_pwrdn_cnt;
+
+	u32 gpu_pwrup_cnt;
+	u32 wakeup_rst_clr_cnt;
+	u32 sft_con;
+	u32 ddr_sref_st;
+
+	u32 int_con;
+	u32 int_st;
+	u32 boot_addr_sel;
+	u32 grf_con;
+
+	u32 gpio_sr;
+	u32 gpio0pull[3];
+
+	u32 gpio0drv[3];
+	u32 gpio_op;
+
+	u32 gpio0_sel18;	/* 0x80 */
+	u32 gpio0_iomux[4];	/* a, b, c, d */
+	u32 sys_reg[4];
+};
+check_member(rk3288_pmu, sys_reg[3], 0x00a0);
+
+enum {
+	PMU_GPIO0_A	= 0,
+	PMU_GPIO0_B,
+	PMU_GPIO0_C,
+	PMU_GPIO0_D,
+};
+
+/* PMU_GPIO0_B_IOMUX */
+enum {
+	GPIO0_B7_SHIFT		= 14,
+	GPIO0_B7_MASK		= 1,
+	GPIO0_B7_GPIOB7		= 0,
+	GPIO0_B7_I2C0PMU_SDA,
+
+	GPIO0_B5_SHIFT		= 10,
+	GPIO0_B5_MASK		= 1,
+	GPIO0_B5_GPIOB5		= 0,
+	GPIO0_B5_CLK_27M,
+
+	GPIO0_B2_SHIFT		= 4,
+	GPIO0_B2_MASK		= 1,
+	GPIO0_B2_GPIOB2		= 0,
+	GPIO0_B2_TSADC_INT,
+};
+
+/* PMU_GPIO0_C_IOMUX */
+enum {
+	GPIO0_C1_SHIFT		= 2,
+	GPIO0_C1_MASK		= 3,
+	GPIO0_C1_GPIOC1		= 0,
+	GPIO0_C1_TEST_CLKOUT,
+	GPIO0_C1_CLKT1_27M,
+
+	GPIO0_C0_SHIFT		= 0,
+	GPIO0_C0_MASK		= 1,
+	GPIO0_C0_GPIOC0		= 0,
+	GPIO0_C0_I2C0PMU_SCL,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
new file mode 100644
index 0000000..f1096dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
+#define __SOC_ROCKCHIP_RK3399_PMU_H__
+
+struct rk3399_pmu_regs {
+	u32 pmu_wakeup_cfg[5];
+	u32 pmu_pwrdn_con;
+	u32 pmu_pwrdn_st;
+	u32 pmu_pll_con;
+	u32 pmu_pwrmode_con;
+	u32 pmu_sft_con;
+	u32 pmu_int_con;
+	u32 pmu_int_st;
+	u32 pmu_gpio0_pos_int_con;
+	u32 pmu_gpio0_net_int_con;
+	u32 pmu_gpio1_pos_int_con;
+	u32 pmu_gpio1_net_int_con;
+	u32 pmu_gpio0_pos_int_st;
+	u32 pmu_gpio0_net_int_st;
+	u32 pmu_gpio1_pos_int_st;
+	u32 pmu_gpio1_net_int_st;
+	u32 pmu_pwrdn_inten;
+	u32 pmu_pwrdn_status;
+	u32 pmu_wakeup_status;
+	u32 pmu_bus_clr;
+	u32 pmu_bus_idle_req;
+	u32 pmu_bus_idle_st;
+	u32 pmu_bus_idle_ack;
+	u32 pmu_cci500_con;
+	u32 pmu_adb400_con;
+	u32 pmu_adb400_st;
+	u32 pmu_power_st;
+	u32 pmu_core_pwr_st;
+	u32 pmu_osc_cnt;
+	u32 pmu_plllock_cnt;
+	u32 pmu_pllrst_cnt;
+	u32 pmu_stable_cnt;
+	u32 pmu_ddrio_pwron_cnt;
+	u32 pmu_wakeup_rst_clr_cnt;
+	u32 pmu_ddr_sref_st;
+	u32 pmu_scu_l_pwrdn_cnt;
+	u32 pmu_scu_l_pwrup_cnt;
+	u32 pmu_scu_b_pwrdn_cnt;
+	u32 pmu_scu_b_pwrup_cnt;
+	u32 pmu_gpu_pwrdn_cnt;
+	u32 pmu_gpu_pwrup_cnt;
+	u32 pmu_center_pwrdn_cnt;
+	u32 pmu_center_pwrup_cnt;
+	u32 pmu_timeout_cnt;
+	u32 pmu_cpu0apm_con;
+	u32 pmu_cpu1apm_con;
+	u32 pmu_cpu2apm_con;
+	u32 pmu_cpu3apm_con;
+	u32 pmu_cpu0bpm_con;
+	u32 pmu_cpu1bpm_con;
+	u32 pmu_noc_auto_ena;
+	u32 pmu_pwrdn_con1;
+	u32 reserved0[0x4];
+	u32 pmu_sys_reg_reg0;
+	u32 pmu_sys_reg_reg1;
+	u32 pmu_sys_reg_reg2;
+	u32 pmu_sys_reg_reg3;
+};
+
+check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
+
+#endif	/* __SOC_ROCKCHIP_RK3399_PMU_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h
new file mode 100644
index 0000000..b5178db
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pwm.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Google, Inc
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ */
+
+#ifndef _ASM_ARCH_PWM_H
+#define _ASM_ARCH_PWM_H
+
+struct rk3288_pwm {
+	u32 cnt;
+	u32 period_hpr;
+	u32 duty_lpr;
+	u32 ctrl;
+};
+check_member(rk3288_pwm, ctrl, 0xc);
+
+#define RK_PWM_DISABLE                  (0 << 0)
+#define RK_PWM_ENABLE                   (1 << 0)
+
+#define PWM_ONE_SHOT                    (0 << 1)
+#define PWM_CONTINUOUS                  (1 << 1)
+#define RK_PWM_CAPTURE                  (1 << 2)
+
+#define PWM_DUTY_POSTIVE                (1 << 3)
+#define PWM_DUTY_NEGATIVE               (0 << 3)
+#define PWM_DUTY_MASK			(1 << 3)
+
+#define PWM_INACTIVE_POSTIVE            (1 << 4)
+#define PWM_INACTIVE_NEGATIVE           (0 << 4)
+#define PWM_INACTIVE_MASK		(1 << 4)
+
+#define PWM_OUTPUT_LEFT                 (0 << 5)
+#define PWM_OUTPUT_CENTER               (1 << 5)
+
+#define PWM_LP_ENABLE                   (1 << 8)
+#define PWM_LP_DISABLE                  (0 << 8)
+
+#define PWM_SEL_SCALE_CLK		(1 << 9)
+#define PWM_SEL_SRC_CLK			(0 << 9)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
new file mode 100644
index 0000000..c24b090
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Rockchip Inc.
+ */
+#ifndef _ASM_ARCH_QOS_RK3288_H
+#define _ASM_ARCH_QOS_RK3288_H
+
+#define PRIORITY_HIGH_SHIFT	2
+#define PRIORITY_LOW_SHIFT	0
+
+#define CPU_AXI_QOS_PRIORITY    0x08
+
+#define VIO0_VOP_QOS            0xffad0400
+#define VIO1_VOP_QOS            0xffad0000
+#define VIO1_ISP_R_QOS          0xffad0900
+#define VIO1_ISP_W0_QOS         0xffad0100
+#define VIO1_ISP_W1_QOS         0xffad0180
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
new file mode 100644
index 0000000..c13957a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ * author: Eric Gao <eric.gao@rock-chips.com>
+ */
+
+#ifndef ROCKCHIP_MIPI_DSI_H
+#define ROCKCHIP_MIPI_DSI_H
+
+/*
+ * All these mipi controller register declaration provide reg address offset,
+ * bits width, bit offset for a specified register bits. With these message, we
+ * can set or clear every bits individually for a 32bit widthregister. We use
+ * DSI_HOST_BITS macro definition to combinat these message using the following
+ * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
+ * For example:
+ *    #define SHUTDOWNZ           DSI_HOST_BITS(0x004, 1, 0)
+ * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr
+ * offset is 0x004.The conbinat result  = (0x004 << 16) | (1 << 8) | 0
+ */
+#define ADDR_SHIFT 16
+#define BITS_SHIFT 8
+#define OFFSET_SHIFT 0
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
+((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT))
+
+/* DWC_DSI_VERSION_0x3133302A */
+#define VERSION				DSI_HOST_BITS(0x000, 32, 0)
+#define SHUTDOWNZ			DSI_HOST_BITS(0x004, 1, 0)
+#define TO_CLK_DIVISION		DSI_HOST_BITS(0x008, 8, 8)
+#define TX_ESC_CLK_DIVISION	DSI_HOST_BITS(0x008, 8, 0)
+#define DPI_VCID			DSI_HOST_BITS(0x00c, 2, 0)
+#define EN18_LOOSELY		DSI_HOST_BITS(0x010, 1, 8)
+#define DPI_COLOR_CODING	DSI_HOST_BITS(0x010, 4, 0)
+#define COLORM_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 4)
+#define SHUTD_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 3)
+#define HSYNC_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 2)
+#define VSYNC_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 1)
+#define DATAEN_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 0)
+#define OUTVACT_LPCMD_TIME	DSI_HOST_BITS(0x018, 8, 16)
+#define INVACT_LPCMD_TIME	DSI_HOST_BITS(0x018, 8, 0)
+#define CRC_RX_EN			DSI_HOST_BITS(0x02c, 1, 4)
+#define ECC_RX_EN			DSI_HOST_BITS(0x02c, 1, 3)
+#define BTA_EN				DSI_HOST_BITS(0x02c, 1, 2)
+#define EOTP_RX_EN			DSI_HOST_BITS(0x02c, 1, 1)
+#define EOTP_TX_EN			DSI_HOST_BITS(0x02c, 1, 0)
+#define GEN_VID_RX			DSI_HOST_BITS(0x030, 2, 0)
+#define CMD_VIDEO_MODE		DSI_HOST_BITS(0x034, 1, 0)
+#define VPG_ORIENTATION		DSI_HOST_BITS(0x038, 1, 24)
+#define VPG_MODE			DSI_HOST_BITS(0x038, 1, 20)
+#define VPG_EN				DSI_HOST_BITS(0x038, 1, 16)
+#define LP_CMD_EN			DSI_HOST_BITS(0x038, 1, 15)
+#define FRAME_BTA_ACK_EN	DSI_HOST_BITS(0x038, 1, 14)
+#define LP_HFP_EN			DSI_HOST_BITS(0x038, 1, 13)
+#define LP_HBP_EN			DSI_HOST_BITS(0x038, 1, 12)
+#define LP_VACT_EN			DSI_HOST_BITS(0x038, 1, 11)
+#define LP_VFP_EN			DSI_HOST_BITS(0x038, 1, 10)
+#define LP_VBP_EN			DSI_HOST_BITS(0x038, 1, 9)
+#define LP_VSA_EN			DSI_HOST_BITS(0x038, 1, 8)
+#define VID_MODE_TYPE		DSI_HOST_BITS(0x038, 2, 0)
+#define VID_PKT_SIZE		DSI_HOST_BITS(0x03c, 14, 0)
+#define NUM_CHUNKS			DSI_HOST_BITS(0x040, 13, 0)
+#define NULL_PKT_SIZE		DSI_HOST_BITS(0x044, 13, 0)
+#define VID_HSA_TIME		DSI_HOST_BITS(0x048, 12, 0)
+#define VID_HBP_TIME		DSI_HOST_BITS(0x04c, 12, 0)
+#define VID_HLINE_TIME		DSI_HOST_BITS(0x050, 15, 0)
+#define VID_VSA_LINES		DSI_HOST_BITS(0x054, 10, 0)
+#define VID_VBP_LINES		DSI_HOST_BITS(0x058, 10, 0)
+#define VID_VFP_LINES		DSI_HOST_BITS(0x05c, 10, 0)
+#define VID_ACTIVE_LINES	DSI_HOST_BITS(0x060, 14, 0)
+#define EDPI_CMD_SIZE		DSI_HOST_BITS(0x064, 16, 0)
+#define MAX_RD_PKT_SIZE		DSI_HOST_BITS(0x068, 1, 24)
+#define DCS_LW_TX			DSI_HOST_BITS(0x068, 1, 19)
+#define DCS_SR_0P_TX		DSI_HOST_BITS(0x068, 1, 18)
+#define DCS_SW_1P_TX		DSI_HOST_BITS(0x068, 1, 17)
+#define DCS_SW_0P_TX		DSI_HOST_BITS(0x068, 1, 16)
+#define GEN_LW_TX			DSI_HOST_BITS(0x068, 1, 14)
+#define GEN_SR_2P_TX		DSI_HOST_BITS(0x068, 1, 13)
+#define GEN_SR_1P_TX		DSI_HOST_BITS(0x068, 1, 12)
+#define GEN_SR_0P_TX		DSI_HOST_BITS(0x068, 1, 11)
+#define GEN_SW_2P_TX		DSI_HOST_BITS(0x068, 1, 10)
+#define GEN_SW_1P_TX		DSI_HOST_BITS(0x068, 1, 9)
+#define GEN_SW_0P_TX		DSI_HOST_BITS(0x068, 1, 8)
+#define ACK_RQST_EN			DSI_HOST_BITS(0x068, 1, 1)
+#define TEAR_FX_EN			DSI_HOST_BITS(0x068, 1, 0)
+#define GEN_WC_MSBYTE		DSI_HOST_BITS(0x06c, 14, 16)
+#define GEN_WC_LSBYTE		DSI_HOST_BITS(0x06c, 8, 8)
+#define GEN_VC				DSI_HOST_BITS(0x06c, 2, 6)
+#define GEN_DT				DSI_HOST_BITS(0x06c, 6, 0)
+#define GEN_PLD_DATA		DSI_HOST_BITS(0x070, 32, 0)
+#define GEN_RD_CMD_BUSY		DSI_HOST_BITS(0x074, 1, 6)
+#define GEN_PLD_R_FULL		DSI_HOST_BITS(0x074, 1, 5)
+#define GEN_PLD_R_EMPTY		DSI_HOST_BITS(0x074, 1, 4)
+#define GEN_PLD_W_FULL		DSI_HOST_BITS(0x074, 1, 3)
+#define GEN_PLD_W_EMPTY		DSI_HOST_BITS(0x074, 1, 2)
+#define GEN_CMD_FULL		DSI_HOST_BITS(0x074, 1, 1)
+#define GEN_CMD_EMPTY		DSI_HOST_BITS(0x074, 1, 0)
+#define HSTX_TO_CNT			DSI_HOST_BITS(0x078, 16, 16)
+#define LPRX_TO_CNT			DSI_HOST_BITS(0x078, 16, 0)
+#define HS_RD_TO_CNT		DSI_HOST_BITS(0x07c, 16, 0)
+#define LP_RD_TO_CNT		DSI_HOST_BITS(0x080, 16, 0)
+#define PRESP_TO_MODE		DSI_HOST_BITS(0x084, 1, 24)
+#define HS_WR_TO_CNT		DSI_HOST_BITS(0x084, 16, 0)
+#define LP_WR_TO_CNT		DSI_HOST_BITS(0x088, 16, 0)
+#define BTA_TO_CNT			DSI_HOST_BITS(0x08c, 16, 0)
+#define AUTO_CLKLANE_CTRL	DSI_HOST_BITS(0x094, 1, 1)
+#define PHY_TXREQUESTCLKHS	DSI_HOST_BITS(0x094, 1, 0)
+#define PHY_HS2LP_TIME_CLK_LANE	DSI_HOST_BITS(0x098, 10, 16)
+#define PHY_HS2HS_TIME_CLK_LANE	DSI_HOST_BITS(0x098, 10, 0)
+#define PHY_HS2LP_TIME		DSI_HOST_BITS(0x09c, 8, 24)
+#define PHY_LP2HS_TIME		DSI_HOST_BITS(0x09c, 8, 16)
+#define MAX_RD_TIME			DSI_HOST_BITS(0x09c, 15, 0)
+#define PHY_FORCEPLL		DSI_HOST_BITS(0x0a0, 1, 3)
+#define PHY_ENABLECLK		DSI_HOST_BITS(0x0a0, 1, 2)
+#define PHY_RSTZ			DSI_HOST_BITS(0x0a0, 1, 1)
+#define PHY_SHUTDOWNZ		DSI_HOST_BITS(0x0a0, 1, 0)
+#define PHY_STOP_WAIT_TIME	DSI_HOST_BITS(0x0a4, 8, 8)
+#define N_LANES				DSI_HOST_BITS(0x0a4, 2, 0)
+#define PHY_TXEXITULPSLAN	DSI_HOST_BITS(0x0a8, 1, 3)
+#define PHY_TXREQULPSLAN	DSI_HOST_BITS(0x0a8, 1, 2)
+#define PHY_TXEXITULPSCLK	DSI_HOST_BITS(0x0a8, 1, 1)
+#define PHY_TXREQULPSCLK	DSI_HOST_BITS(0x0a8, 1, 0)
+#define PHY_TX_TRIGGERS		DSI_HOST_BITS(0x0ac, 4, 0)
+#define PHYSTOPSTATECLKLANE	DSI_HOST_BITS(0x0b0, 1, 2)
+#define PHYLOCK				DSI_HOST_BITS(0x0b0, 1, 0)
+#define PHY_TESTCLK			DSI_HOST_BITS(0x0b4, 1, 1)
+#define PHY_TESTCLR			DSI_HOST_BITS(0x0b4, 1, 0)
+#define PHY_TESTEN			DSI_HOST_BITS(0x0b8, 1, 16)
+#define PHY_TESTDOUT		DSI_HOST_BITS(0x0b8, 8, 8)
+#define PHY_TESTDIN			DSI_HOST_BITS(0x0b8, 8, 0)
+#define PHY_TEST_CTRL1		DSI_HOST_BITS(0x0b8, 17, 0)
+#define PHY_TEST_CTRL0		DSI_HOST_BITS(0x0b4, 2, 0)
+#define INT_ST0				DSI_HOST_BITS(0x0bc, 21, 0)
+#define INT_ST1				DSI_HOST_BITS(0x0c0, 18, 0)
+#define INT_MKS0			DSI_HOST_BITS(0x0c4, 21, 0)
+#define INT_MKS1			DSI_HOST_BITS(0x0c8, 18, 0)
+#define INT_FORCE0			DSI_HOST_BITS(0x0d8, 21, 0)
+#define INT_FORCE1			DSI_HOST_BITS(0x0dc, 18, 0)
+
+#define CODE_HS_RX_CLOCK	0x34
+#define CODE_HS_RX_LANE0	0x44
+#define CODE_HS_RX_LANE1	0x54
+#define CODE_HS_RX_LANE2	0x84
+#define CODE_HS_RX_LANE3	0x94
+
+#define CODE_PLL_VCORANGE_VCOCAP	0x10
+#define CODE_PLL_CPCTRL	0x11
+#define CODE_PLL_LPF_CP 0x12
+#define CODE_PLL_INPUT_DIV_RAT	0x17
+#define CODE_PLL_LOOP_DIV_RAT	0x18
+#define CODE_PLL_INPUT_LOOP_DIV_RAT	0x19
+#define CODE_BANDGAP_BIAS_CTRL	0x20
+#define CODE_TERMINATION_CTRL	0x21
+#define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22
+
+#define CODE_HSTXDATALANEREQUSETSTATETIME	0x70
+#define CODE_HSTXDATALANEPREPARESTATETIME	0x71
+#define CODE_HSTXDATALANEHSZEROSTATETIME	0x72
+
+/* Transmission mode between vop and MIPI controller */
+enum vid_mode_type_t {
+	NON_BURST_SYNC_PLUSE = 0,
+	NON_BURST_SYNC_EVENT,
+	BURST_MODE,
+};
+
+enum cmd_video_mode {
+	VIDEO_MODE = 0,
+	CMD_MODE,
+};
+
+/* Indicate MIPI DSI color mode */
+enum dpi_color_coding {
+	DPI_16BIT_CFG_1 = 0,
+	DPI_16BIT_CFG_2,
+	DPI_16BIT_CFG_3,
+	DPI_18BIT_CFG_1,
+	DPI_18BIT_CFG_2,
+	DPI_24BIT,
+	DPI_20BIT_YCBCR_422_LP,
+	DPI_24BIT_YCBCR_422,
+	DPI_16BIT_YCBCR_422,
+	DPI_30BIT,
+	DPI_36BIT,
+	DPI_12BIT_YCBCR_420,
+};
+
+/* Indicate which VOP the MIPI DSI use, bit or little one */
+enum  vop_id {
+	VOP_B = 0,
+	VOP_L,
+};
+
+#endif /* end of ROCKCHIP_MIPI_DSI_H */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
new file mode 100644
index 0000000..9220763
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_RK3288_SDRAM_H__
+#define _ASM_ARCH_RK3288_SDRAM_H__
+
+struct rk3288_sdram_channel {
+	/*
+	 * bit width in address, eg:
+	 * 8 banks using 3 bit to address,
+	 * 2 cs using 1 bit to address.
+	 */
+	u8 rank;
+	u8 col;
+	u8 bk;
+	u8 bw;
+	u8 dbw;
+	u8 row_3_4;
+	u8 cs0_row;
+	u8 cs1_row;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/*
+	 * For of-platdata, which would otherwise convert this into two
+	 * byte-swapped integers. With a size of 9 bytes, this struct will
+	 * appear in of-platdata as a byte array.
+	 *
+	 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
+	 */
+	u8 dummy;
+#endif
+};
+
+struct rk3288_sdram_pctl_timing {
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+};
+check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
+
+struct rk3288_sdram_phy_timing {
+	u32 dtpr0;
+	u32 dtpr1;
+	u32 dtpr2;
+	u32 mr[4];
+};
+
+struct rk3288_base_params {
+	u32 noc_timing;
+	u32 noc_activate;
+	u32 ddrconfig;
+	u32 ddr_freq;
+	u32 dramtype;
+	/*
+	 * DDR Stride is address mapping for DRAM space
+	 * Stride	Ch 0 range	Ch1 range	Total
+	 * 0x00		0-256MB		256MB-512MB	512MB
+	 * 0x05		0-1GB		0-1GB		1GB
+	 * 0x09		0-2GB		0-2GB		2GB
+	 * 0x0d		0-4GB		0-4GB		4GB
+	 * 0x17		N/A		0-4GB		4GB
+	 * 0x1a		0-4GB		4GB-8GB		8GB
+	 */
+	u32 stride;
+	u32 odt;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
new file mode 100644
index 0000000..8027b53
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _ASM_ARCH_SDRAM_COMMON_H
+#define _ASM_ARCH_SDRAM_COMMON_H
+
+enum {
+	DDR4 = 0,
+	DDR3 = 0x3,
+	LPDDR2 = 0x5,
+	LPDDR3 = 0x6,
+	LPDDR4 = 0x7,
+	UNUSED = 0xFF
+};
+
+struct sdram_cap_info {
+	unsigned int rank;
+	/* dram column number, 0 means this channel is invalid */
+	unsigned int col;
+	/* dram bank number, 3:8bank, 2:4bank */
+	unsigned int bk;
+	/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int bw;
+	/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int dbw;
+	/*
+	 * row_3_4 = 1: 6Gb or 12Gb die
+	 * row_3_4 = 0: normal die, power of 2
+	 */
+	unsigned int row_3_4;
+	unsigned int cs0_row;
+	unsigned int cs1_row;
+	unsigned int ddrconfig;
+};
+
+struct sdram_base_params {
+	unsigned int ddr_freq;
+	unsigned int dramtype;
+	unsigned int num_channels;
+	unsigned int stride;
+	unsigned int odt;
+};
+
+/*
+ * sys_reg bitfield struct
+ * [31]		row_3_4_ch1
+ * [30]		row_3_4_ch0
+ * [29:28]	chinfo
+ * [27]		rank_ch1
+ * [26:25]	col_ch1
+ * [24]		bk_ch1
+ * [23:22]	cs0_row_ch1
+ * [21:20]	cs1_row_ch1
+ * [19:18]	bw_ch1
+ * [17:16]	dbw_ch1;
+ * [15:13]	ddrtype
+ * [12]		channelnum
+ * [11]		rank_ch0
+ * [10:9]	col_ch0
+ * [8]		bk_ch0
+ * [7:6]	cs0_row_ch0
+ * [5:4]	cs1_row_ch0
+ * [3:2]	bw_ch0
+ * [1:0]	dbw_ch0
+*/
+#define SYS_REG_DDRTYPE_SHIFT		13
+#define DDR_SYS_REG_VERSION		2
+#define SYS_REG_DDRTYPE_MASK		7
+#define SYS_REG_NUM_CH_SHIFT		12
+#define SYS_REG_NUM_CH_MASK		1
+#define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
+#define SYS_REG_ROW_3_4_MASK		1
+#define SYS_REG_ENC_ROW_3_4(n, ch)	((n) << (30 + (ch)))
+#define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch)		(1 << SYS_REG_CHINFO_SHIFT(ch))
+#define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
+#define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
+					SYS_REG_NUM_CH_SHIFT)
+#define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
+#define SYS_REG_RANK_MASK		1
+#define SYS_REG_ENC_RANK(n, ch)		(((n) - SYS_REG_RANK_MASK) << \
+					 SYS_REG_RANK_SHIFT(ch))
+#define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
+#define SYS_REG_COL_MASK		3
+#define SYS_REG_ENC_COL(n, ch)		(((n) - 9) << SYS_REG_COL_SHIFT(ch))
+#define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
+#define SYS_REG_BK_MASK			1
+#define SYS_REG_ENC_BK(n, ch)		(((n) == 3 ? 0 : 1) << \
+					SYS_REG_BK_SHIFT(ch))
+#define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
+#define SYS_REG_CS0_ROW_MASK		3
+#define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
+#define SYS_REG_CS1_ROW_MASK		3
+#define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
+#define SYS_REG_BW_MASK			3
+#define SYS_REG_ENC_BW(n, ch)		((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
+#define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
+#define SYS_REG_DBW_MASK		3
+#define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+
+#define SYS_REG_ENC_VERSION(n)		((n) << 28)
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (5 + 2 * (ch)); \
+		} while (0)
+
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+			(os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+			(os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (4 + 2 * (ch)); \
+		} while (0)
+
+#define SYS_REG_CS1_COL_SHIFT(ch)	(0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch)      (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
+/* Get sdram size decode from reg */
+size_t rockchip_sdram_size(phys_addr_t reg);
+
+/* Called by U-Boot board_init_r for Rockchip SoCs */
+int dram_init(void);
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+				 struct sdram_base_params *base)
+{
+}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+			  struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h
new file mode 100644
index 0000000..5de3220
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h
@@ -0,0 +1,340 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_SDRAM_RK3036_H
+#define _ASM_ARCH_SDRAM_RK3036_H
+
+#include <common.h>
+
+struct rk3036_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 reserved5[47];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3036_ddr_pctl, iptr, 0x03fc);
+
+struct rk3036_ddr_phy {
+	u32 ddrphy_reg1;
+	u32 ddrphy_reg3;
+	u32 ddrphy_reg2;
+	u32 reserve[11];
+	u32 ddrphy_reg4a;
+	u32 ddrphy_reg4b;
+	u32 reserve1[5];
+	u32 ddrphy_reg16;
+	u32 reserve2;
+	u32 ddrphy_reg18;
+	u32 ddrphy_reg19;
+	u32 reserve3;
+	u32 ddrphy_reg21;
+	u32 reserve4;
+	u32 ddrphy_reg22;
+	u32 reserve5[3];
+	u32 ddrphy_reg25;
+	u32 ddrphy_reg26;
+	u32 ddrphy_reg27;
+	u32 ddrphy_reg28;
+	u32 reserve6[17];
+	u32 ddrphy_reg6;
+	u32 ddrphy_reg7;
+	u32 reserve7;
+	u32 ddrphy_reg8;
+	u32 ddrphy_reg0e4;
+	u32 reserve8[11];
+	u32 ddrphy_reg9;
+	u32 ddrphy_reg10;
+	u32 reserve9;
+	u32 ddrphy_reg11;
+	u32 ddrphy_reg124;
+	u32 reserve10[38];
+	u32 ddrphy_reg29;
+	u32 reserve11[40];
+	u32 ddrphy_reg264;
+	u32 reserve12[18];
+	u32 ddrphy_reg2a;
+	u32 reserve13[4];
+	u32 ddrphy_reg30;
+	u32 ddrphy_reg31;
+	u32 ddrphy_reg32;
+	u32 ddrphy_reg33;
+	u32 ddrphy_reg34;
+	u32 ddrphy_reg35;
+	u32 ddrphy_reg36;
+	u32 ddrphy_reg37;
+	u32 ddrphy_reg38;
+	u32 ddrphy_reg39;
+	u32 ddrphy_reg40;
+	u32 ddrphy_reg41;
+	u32 ddrphy_reg42;
+	u32 ddrphy_reg43;
+	u32 ddrphy_reg44;
+	u32 ddrphy_reg45;
+	u32 ddrphy_reg46;
+	u32 ddrphy_reg47;
+	u32 ddrphy_reg48;
+	u32 ddrphy_reg49;
+	u32 ddrphy_reg50;
+	u32 ddrphy_reg51;
+	u32 ddrphy_reg52;
+	u32 ddrphy_reg53;
+	u32 reserve14;
+	u32 ddrphy_reg54;
+	u32 ddrphy_reg55;
+	u32 ddrphy_reg56;
+	u32 ddrphy_reg57;
+	u32 ddrphy_reg58;
+	u32 ddrphy_reg59;
+	u32 ddrphy_reg5a;
+	u32 ddrphy_reg5b;
+	u32 ddrphy_reg5c;
+	u32 ddrphy_reg5d;
+	u32 ddrphy_reg5e;
+	u32 reserve15[28];
+	u32 ddrphy_reg5f;
+	u32 reserve16[6];
+	u32 ddrphy_reg60;
+	u32 ddrphy_reg61;
+	u32 ddrphy_reg62;
+};
+check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8);
+
+struct rk3036_pctl_timing {
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+};
+
+struct rk3036_phy_timing {
+	u32 mr[4];
+	u32 bl;
+	u32 cl_al;
+};
+
+typedef union {
+	u32 noc_timing;
+	struct {
+		u32 acttoact:6;
+		u32 rdtomiss:6;
+		u32 wrtomiss:6;
+		u32 burstlen:3;
+		u32 rdtowr:5;
+		u32 wrtord:5;
+		u32 bwratio:1;
+	};
+} rk3036_noc_timing;
+
+struct rk3036_ddr_timing {
+	u32 freq;
+	struct rk3036_pctl_timing pctl_timing;
+	struct rk3036_phy_timing phy_timing;
+	rk3036_noc_timing noc_timing;
+};
+
+struct rk3036_service_sys {
+	u32 id_coreid;
+	u32 id_revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+};
+
+struct rk3036_ddr_config {
+	/*
+	 * 000: lpddr
+	 * 001: ddr
+	 * 010: ddr2
+	 * 011: ddr3
+	 * 100: lpddr2-s2
+	 * 101: lpddr2-s4
+	 * 110: lpddr3
+	 */
+	u32 ddr_type;
+	u32 rank;
+	u32 cs0_row;
+	u32 cs1_row;
+
+	/* 2: 4bank, 3: 8bank */
+	u32 bank;
+	u32 col;
+
+	/* bw(0: 8bit, 1: 16bit, 2: 32bit) */
+	u32 bw;
+};
+
+/* rk3036 sdram initial */
+void sdram_init(void);
+
+/* get ddr die config, implement in specific board */
+void get_ddr_config(struct rk3036_ddr_config *config);
+
+/* get ddr size on board */
+size_t sdram_size(void);
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
new file mode 100644
index 0000000..336c5d7
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
@@ -0,0 +1,573 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_SDRAM_RK322X_H
+#define _ASM_ARCH_SDRAM_RK322X_H
+
+#include <common.h>
+
+struct rk322x_sdram_channel {
+	/*
+	 * bit width in address, eg:
+	 * 8 banks using 3 bit to address,
+	 * 2 cs using 1 bit to address.
+	 */
+	u8 rank;
+	u8 col;
+	u8 bk;
+	u8 bw;
+	u8 dbw;
+	u8 row_3_4;
+	u8 cs0_row;
+	u8 cs1_row;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/*
+	 * For of-platdata, which would otherwise convert this into two
+	 * byte-swapped integers. With a size of 9 bytes, this struct will
+	 * appear in of-platdata as a byte array.
+	 *
+	 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
+	 */
+	u8 dummy;
+#endif
+};
+
+struct rk322x_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[(0x40 - 0x10) / 4];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[(0x60 - 0x54) / 4];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[(0x7c - 0x6c) / 4];
+
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[(0xc0 - 0xb4) / 4];
+
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 tref_mem_ddr3;
+	u32 reserved5[(0x180 - 0x14c) / 4];
+	u32 ecccfg;
+	u32 ecctst;
+	u32 eccclr;
+	u32 ecclog;
+	u32 reserved6[(0x200 - 0x190) / 4];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	/* dfi control registers */
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	/* dfi write data registers */
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[(0x260 - 0x258) / 4];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[(0x270 - 0x268) / 4];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[(0x2ac - 0x29c) / 4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[(0x2f0 - 0x2e4) / 4];
+
+	u32 dfilpcfg0;
+	u32 reserved13[(0x300 - 0x2f4) / 4];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[(0x3f8 - 0x340) / 4];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk322x_ddr_pctl, iptr, 0x03fc);
+
+struct rk322x_ddr_phy {
+	u32 ddrphy_reg[0x100];
+};
+
+struct rk322x_pctl_timing {
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 trefi_mem_ddr3;
+};
+
+struct rk322x_phy_timing {
+	u32 mr[4];
+	u32 mr11;
+	u32 bl;
+	u32 cl_al;
+};
+
+struct rk322x_msch_timings {
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 activate;
+	u32 devtodev;
+};
+
+struct rk322x_service_sys {
+	u32 id_coreid;
+	u32 id_revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 activate;
+	u32 devtodev;
+};
+
+struct rk322x_base_params {
+	struct rk322x_msch_timings noc_timing;
+	u32 ddrconfig;
+	u32 ddr_freq;
+	u32 dramtype;
+	/*
+	 * unused for rk322x
+	 */
+	u32 stride;
+	u32 odt;
+};
+
+/* PCT_DFISTCFG0 */
+#define DFI_INIT_START			BIT(0)
+#define DFI_DATA_BYTE_DISABLE_EN	BIT(2)
+
+/* PCT_DFISTCFG1 */
+#define DFI_DRAM_CLK_SR_EN		BIT(0)
+#define DFI_DRAM_CLK_DPD_EN		BIT(1)
+
+/* PCT_DFISTCFG2 */
+#define DFI_PARITY_INTR_EN		BIT(0)
+#define DFI_PARITY_EN			BIT(1)
+
+/* PCT_DFILPCFG0 */
+#define TLP_RESP_TIME_SHIFT		16
+#define LP_SR_EN			BIT(8)
+#define LP_PD_EN			BIT(0)
+
+/* PCT_DFITCTRLDELAY */
+#define TCTRL_DELAY_TIME_SHIFT		0
+
+/* PCT_DFITPHYWRDATA */
+#define TPHY_WRDATA_TIME_SHIFT		0
+
+/* PCT_DFITPHYRDLAT */
+#define TPHY_RDLAT_TIME_SHIFT		0
+
+/* PCT_DFITDRAMCLKDIS */
+#define TDRAM_CLK_DIS_TIME_SHIFT	0
+
+/* PCT_DFITDRAMCLKEN */
+#define TDRAM_CLK_EN_TIME_SHIFT		0
+
+/* PCTL_DFIODTCFG */
+#define RANK0_ODT_WRITE_SEL		BIT(3)
+#define RANK1_ODT_WRITE_SEL		BIT(11)
+
+/* PCTL_DFIODTCFG1 */
+#define ODT_LEN_BL8_W_SHIFT		16
+
+/* PUBL_ACDLLCR */
+#define ACDLLCR_DLLDIS			BIT(31)
+#define ACDLLCR_DLLSRST			BIT(30)
+
+/* PUBL_DXDLLCR */
+#define DXDLLCR_DLLDIS			BIT(31)
+#define DXDLLCR_DLLSRST			BIT(30)
+
+/* PUBL_DLLGCR */
+#define DLLGCR_SBIAS			BIT(30)
+
+/* PUBL_DXGCR */
+#define DQSRTT				BIT(9)
+#define DQRTT				BIT(10)
+
+/* PIR */
+#define PIR_INIT			BIT(0)
+#define PIR_DLLSRST			BIT(1)
+#define PIR_DLLLOCK			BIT(2)
+#define PIR_ZCAL			BIT(3)
+#define PIR_ITMSRST			BIT(4)
+#define PIR_DRAMRST			BIT(5)
+#define PIR_DRAMINIT			BIT(6)
+#define PIR_QSTRN			BIT(7)
+#define PIR_RVTRN			BIT(8)
+#define PIR_ICPC			BIT(16)
+#define PIR_DLLBYP			BIT(17)
+#define PIR_CTLDINIT			BIT(18)
+#define PIR_CLRSR			BIT(28)
+#define PIR_LOCKBYP			BIT(29)
+#define PIR_ZCALBYP			BIT(30)
+#define PIR_INITBYP			BIT(31)
+
+/* PGCR */
+#define PGCR_DFTLMT_SHIFT		3
+#define PGCR_DFTCMP_SHIFT		2
+#define PGCR_DQSCFG_SHIFT		1
+#define PGCR_ITMDMD_SHIFT		0
+
+/* PGSR */
+#define PGSR_IDONE			BIT(0)
+#define PGSR_DLDONE			BIT(1)
+#define PGSR_ZCDONE			BIT(2)
+#define PGSR_DIDONE			BIT(3)
+#define PGSR_DTDONE			BIT(4)
+#define PGSR_DTERR			BIT(5)
+#define PGSR_DTIERR			BIT(6)
+#define PGSR_DFTERR			BIT(7)
+#define PGSR_RVERR			BIT(8)
+#define PGSR_RVEIRR			BIT(9)
+
+/* PTR0 */
+#define PRT_ITMSRST_SHIFT		18
+#define PRT_DLLLOCK_SHIFT		6
+#define PRT_DLLSRST_SHIFT		0
+
+/* PTR1 */
+#define PRT_DINIT0_SHIFT		0
+#define PRT_DINIT1_SHIFT		19
+
+/* PTR2 */
+#define PRT_DINIT2_SHIFT		0
+#define PRT_DINIT3_SHIFT		17
+
+/* DCR */
+#define DDRMD_LPDDR			0
+#define DDRMD_DDR			1
+#define DDRMD_DDR2			2
+#define DDRMD_DDR3			3
+#define DDRMD_LPDDR2_LPDDR3		4
+#define DDRMD_MASK			7
+#define DDRMD_SHIFT			0
+#define PDQ_MASK			7
+#define PDQ_SHIFT			4
+
+/* DXCCR */
+#define DQSNRES_MASK			0xf
+#define DQSNRES_SHIFT			8
+#define DQSRES_MASK			0xf
+#define DQSRES_SHIFT			4
+
+/* DTPR */
+#define TDQSCKMAX_SHIFT			27
+#define TDQSCKMAX_MASK			7
+#define TDQSCK_SHIFT			24
+#define TDQSCK_MASK			7
+
+/* DSGCR */
+#define DQSGX_SHIFT			5
+#define DQSGX_MASK			7
+#define DQSGE_SHIFT			8
+#define DQSGE_MASK			7
+
+/* SCTL */
+#define INIT_STATE			0
+#define CFG_STATE			1
+#define GO_STATE			2
+#define SLEEP_STATE			3
+#define WAKEUP_STATE			4
+
+/* STAT */
+#define LP_TRIG_SHIFT			4
+#define LP_TRIG_MASK			7
+#define PCTL_STAT_MASK			7
+#define INIT_MEM			0
+#define CONFIG				1
+#define CONFIG_REQ			2
+#define ACCESS				3
+#define ACCESS_REQ			4
+#define LOW_POWER			5
+#define LOW_POWER_ENTRY_REQ		6
+#define LOW_POWER_EXIT_REQ		7
+
+/* ZQCR*/
+#define PD_OUTPUT_SHIFT			0
+#define PU_OUTPUT_SHIFT			5
+#define PD_ONDIE_SHIFT			10
+#define PU_ONDIE_SHIFT			15
+#define ZDEN_SHIFT			28
+
+/* DDLGCR */
+#define SBIAS_BYPASS			BIT(23)
+
+/* MCFG */
+#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT	24
+#define PD_IDLE_SHIFT			8
+#define MDDR_EN				(2 << 22)
+#define LPDDR2_EN			(3 << 22)
+#define LPDDR3_EN			(1 << 22)
+#define DDR2_EN				(0 << 5)
+#define DDR3_EN				(1 << 5)
+#define LPDDR2_S2			(0 << 6)
+#define LPDDR2_S4			(1 << 6)
+#define MDDR_LPDDR2_BL_2		(0 << 20)
+#define MDDR_LPDDR2_BL_4		(1 << 20)
+#define MDDR_LPDDR2_BL_8		(2 << 20)
+#define MDDR_LPDDR2_BL_16		(3 << 20)
+#define DDR2_DDR3_BL_4			0
+#define DDR2_DDR3_BL_8			1
+#define TFAW_SHIFT			18
+#define PD_EXIT_SLOW			(0 << 17)
+#define PD_EXIT_FAST			(1 << 17)
+#define PD_TYPE_SHIFT			16
+#define BURSTLENGTH_SHIFT		20
+
+/* POWCTL */
+#define POWER_UP_START			BIT(0)
+
+/* POWSTAT */
+#define POWER_UP_DONE			BIT(0)
+
+/* MCMD */
+enum {
+	DESELECT_CMD			= 0,
+	PREA_CMD,
+	REF_CMD,
+	MRS_CMD,
+	ZQCS_CMD,
+	ZQCL_CMD,
+	RSTL_CMD,
+	MRR_CMD				= 8,
+	DPDE_CMD,
+};
+
+#define BANK_ADDR_MASK			7
+#define BANK_ADDR_SHIFT			17
+#define CMD_ADDR_MASK			0x1fff
+#define CMD_ADDR_SHIFT			4
+
+#define LPDDR23_MA_SHIFT		4
+#define LPDDR23_MA_MASK			0xff
+#define LPDDR23_OP_SHIFT		12
+#define LPDDR23_OP_MASK			0xff
+
+#define START_CMD			(1u << 31)
+
+/* DDRPHY REG */
+enum {
+	/* DDRPHY_REG0 */
+	SOFT_RESET_MASK				= 3,
+	SOFT_DERESET_ANALOG			= 1 << 2,
+	SOFT_DERESET_DIGITAL			= 1 << 3,
+	SOFT_RESET_SHIFT			= 2,
+
+	/* DDRPHY REG1 */
+	PHY_DDR3				= 0,
+	PHY_DDR2				= 1,
+	PHY_LPDDR3				= 2,
+	PHY_LPDDR2				= 3,
+
+	PHT_BL_8				= 1 << 2,
+	PHY_BL_4				= 0 << 2,
+
+	/* DDRPHY_REG2 */
+	MEMORY_SELECT_DDR3			= 0 << 0,
+	MEMORY_SELECT_LPDDR3			= 2 << 0,
+	MEMORY_SELECT_LPDDR2			= 3 << 0,
+	DQS_SQU_CAL_SEL_CS0_CS1			= 0 << 4,
+	DQS_SQU_CAL_SEL_CS1			= 1 << 4,
+	DQS_SQU_CAL_SEL_CS0			= 2 << 4,
+	DQS_SQU_CAL_NORMAL_MODE			= 0 << 1,
+	DQS_SQU_CAL_BYPASS_MODE			= 1 << 1,
+	DQS_SQU_CAL_START			= 1 << 0,
+	DQS_SQU_NO_CAL				= 0 << 0,
+};
+
+/* CK pull up/down driver strength control */
+enum {
+	PHY_RON_RTT_DISABLE = 0,
+	PHY_RON_RTT_451OHM = 1,
+	PHY_RON_RTT_225OHM,
+	PHY_RON_RTT_150OHM,
+	PHY_RON_RTT_112OHM,
+	PHY_RON_RTT_90OHM,
+	PHY_RON_RTT_75OHM,
+	PHY_RON_RTT_64OHM = 7,
+
+	PHY_RON_RTT_56OHM = 16,
+	PHY_RON_RTT_50OHM,
+	PHY_RON_RTT_45OHM,
+	PHY_RON_RTT_41OHM,
+	PHY_RON_RTT_37OHM,
+	PHY_RON_RTT_34OHM,
+	PHY_RON_RTT_33OHM,
+	PHY_RON_RTT_30OHM = 23,
+
+	PHY_RON_RTT_28OHM = 24,
+	PHY_RON_RTT_26OHM,
+	PHY_RON_RTT_25OHM,
+	PHY_RON_RTT_23OHM,
+	PHY_RON_RTT_22OHM,
+	PHY_RON_RTT_21OHM,
+	PHY_RON_RTT_20OHM,
+	PHY_RON_RTT_19OHM = 31,
+};
+
+/* DQS squelch DLL delay */
+enum {
+	DQS_DLL_NO_DELAY	= 0,
+	DQS_DLL_22P5_DELAY,
+	DQS_DLL_45_DELAY,
+	DQS_DLL_67P5_DELAY,
+	DQS_DLL_90_DELAY,
+	DQS_DLL_112P5_DELAY,
+	DQS_DLL_135_DELAY,
+	DQS_DLL_157P5_DELAY,
+};
+
+/* GRF_SOC_CON0 */
+#define GRF_DDR_16BIT_EN		(((0x1 << 0) << 16) | (0x1 << 0))
+#define GRF_DDR_32BIT_EN		(((0x1 << 0) << 16) | (0x0 << 0))
+#define GRF_MSCH_NOC_16BIT_EN		(((0x1 << 7) << 16) | (0x1 << 7))
+#define GRF_MSCH_NOC_32BIT_EN		(((0x1 << 7) << 16) | (0x0 << 7))
+
+#define GRF_DDRPHY_BUFFEREN_CORE_EN	(((0x1 << 8) << 16) | (0x0 << 8))
+#define GRF_DDRPHY_BUFFEREN_CORE_DIS	(((0x1 << 8) << 16) | (0x1 << 8))
+
+#define GRF_DDR3_EN			(((0x1 << 6) << 16) | (0x1 << 6))
+#define GRF_LPDDR2_3_EN			(((0x1 << 6) << 16) | (0x0 << 6))
+
+#define PHY_DRV_ODT_SET(n)		(((n) << 4) | (n))
+#define DDR3_DLL_RESET			(1 << 8)
+
+#endif /* _ASM_ARCH_SDRAM_RK322X_H */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
new file mode 100644
index 0000000..11411ea
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3328_H
+#define _ASM_ARCH_SDRAM_RK3328_H
+
+#define SR_IDLE		93
+#define PD_IDLE		13
+#define SDRAM_ADDR	0x00000000
+#define PATTERN		(0x5aa5f00f)
+
+/* ddr pctl registers define */
+#define DDR_PCTL2_MSTR			0x0
+#define DDR_PCTL2_STAT			0x4
+#define DDR_PCTL2_MSTR1			0x8
+#define DDR_PCTL2_MRCTRL0		0x10
+#define DDR_PCTL2_MRCTRL1		0x14
+#define DDR_PCTL2_MRSTAT		0x18
+#define DDR_PCTL2_MRCTRL2		0x1c
+#define DDR_PCTL2_DERATEEN		0x20
+#define DDR_PCTL2_DERATEINT		0x24
+#define DDR_PCTL2_PWRCTL		0x30
+#define DDR_PCTL2_PWRTMG		0x34
+#define DDR_PCTL2_HWLPCTL		0x38
+#define DDR_PCTL2_RFSHCTL0		0x50
+#define DDR_PCTL2_RFSHCTL1		0x54
+#define DDR_PCTL2_RFSHCTL2		0x58
+#define DDR_PCTL2_RFSHCTL4		0x5c
+#define DDR_PCTL2_RFSHCTL3		0x60
+#define DDR_PCTL2_RFSHTMG		0x64
+#define DDR_PCTL2_RFSHTMG1		0x68
+#define DDR_PCTL2_RFSHCTL5		0x6c
+#define DDR_PCTL2_INIT0			0xd0
+#define DDR_PCTL2_INIT1			0xd4
+#define DDR_PCTL2_INIT2			0xd8
+#define DDR_PCTL2_INIT3			0xdc
+#define DDR_PCTL2_INIT4			0xe0
+#define DDR_PCTL2_INIT5			0xe4
+#define DDR_PCTL2_INIT6			0xe8
+#define DDR_PCTL2_INIT7			0xec
+#define DDR_PCTL2_DIMMCTL		0xf0
+#define DDR_PCTL2_RANKCTL		0xf4
+#define DDR_PCTL2_CHCTL			0xfc
+#define DDR_PCTL2_DRAMTMG0		0x100
+#define DDR_PCTL2_DRAMTMG1		0x104
+#define DDR_PCTL2_DRAMTMG2		0x108
+#define DDR_PCTL2_DRAMTMG3		0x10c
+#define DDR_PCTL2_DRAMTMG4		0x110
+#define DDR_PCTL2_DRAMTMG5		0x114
+#define DDR_PCTL2_DRAMTMG6		0x118
+#define DDR_PCTL2_DRAMTMG7		0x11c
+#define DDR_PCTL2_DRAMTMG8		0x120
+#define DDR_PCTL2_DRAMTMG9		0x124
+#define DDR_PCTL2_DRAMTMG10		0x128
+#define DDR_PCTL2_DRAMTMG11		0x12c
+#define DDR_PCTL2_DRAMTMG12		0x130
+#define DDR_PCTL2_DRAMTMG13		0x134
+#define DDR_PCTL2_DRAMTMG14		0x138
+#define DDR_PCTL2_DRAMTMG15		0x13c
+#define DDR_PCTL2_DRAMTMG16		0x140
+#define DDR_PCTL2_ZQCTL0		0x180
+#define DDR_PCTL2_ZQCTL1		0x184
+#define DDR_PCTL2_ZQCTL2		0x188
+#define DDR_PCTL2_ZQSTAT		0x18c
+#define DDR_PCTL2_DFITMG0		0x190
+#define DDR_PCTL2_DFITMG1		0x194
+#define DDR_PCTL2_DFILPCFG0		0x198
+#define DDR_PCTL2_DFILPCFG1		0x19c
+#define DDR_PCTL2_DFIUPD0		0x1a0
+#define DDR_PCTL2_DFIUPD1		0x1a4
+#define DDR_PCTL2_DFIUPD2		0x1a8
+#define DDR_PCTL2_DFIMISC		0x1b0
+#define DDR_PCTL2_DFITMG2		0x1b4
+#define DDR_PCTL2_DFITMG3		0x1b8
+#define DDR_PCTL2_DFISTAT		0x1bc
+#define DDR_PCTL2_DBICTL		0x1c0
+#define DDR_PCTL2_ADDRMAP0		0x200
+#define DDR_PCTL2_ADDRMAP1		0x204
+#define DDR_PCTL2_ADDRMAP2		0x208
+#define DDR_PCTL2_ADDRMAP3		0x20c
+#define DDR_PCTL2_ADDRMAP4		0x210
+#define DDR_PCTL2_ADDRMAP5		0x214
+#define DDR_PCTL2_ADDRMAP6		0x218
+#define DDR_PCTL2_ADDRMAP7		0x21c
+#define DDR_PCTL2_ADDRMAP8		0x220
+#define DDR_PCTL2_ADDRMAP9		0x224
+#define DDR_PCTL2_ADDRMAP10		0x228
+#define DDR_PCTL2_ADDRMAP11		0x22c
+#define DDR_PCTL2_ODTCFG		0x240
+#define DDR_PCTL2_ODTMAP		0x244
+#define DDR_PCTL2_SCHED			0x250
+#define DDR_PCTL2_SCHED1		0x254
+#define DDR_PCTL2_PERFHPR1		0x25c
+#define DDR_PCTL2_PERFLPR1		0x264
+#define DDR_PCTL2_PERFWR1		0x26c
+#define DDR_PCTL2_DQMAP0		0x280
+#define DDR_PCTL2_DQMAP1		0x284
+#define DDR_PCTL2_DQMAP2		0x288
+#define DDR_PCTL2_DQMAP3		0x28c
+#define DDR_PCTL2_DQMAP4		0x290
+#define DDR_PCTL2_DQMAP5		0x294
+#define DDR_PCTL2_DBG0			0x300
+#define DDR_PCTL2_DBG1			0x304
+#define DDR_PCTL2_DBGCAM		0x308
+#define DDR_PCTL2_DBGCMD		0x30c
+#define DDR_PCTL2_DBGSTAT		0x310
+#define DDR_PCTL2_SWCTL			0x320
+#define DDR_PCTL2_SWSTAT		0x324
+#define DDR_PCTL2_POISONCFG		0x36c
+#define DDR_PCTL2_POISONSTAT		0x370
+#define DDR_PCTL2_ADVECCINDEX		0x374
+#define DDR_PCTL2_ADVECCSTAT		0x378
+#define DDR_PCTL2_PSTAT			0x3fc
+#define DDR_PCTL2_PCCFG			0x400
+#define DDR_PCTL2_PCFGR_n		0x404
+#define DDR_PCTL2_PCFGW_n		0x408
+#define DDR_PCTL2_PCTRL_n		0x490
+
+/* PCTL2_MRSTAT */
+#define MR_WR_BUSY			BIT(0)
+
+/* PHY_REG0 */
+#define DIGITAL_DERESET			BIT(3)
+#define ANALOG_DERESET			BIT(2)
+#define DIGITAL_RESET			(0 << 3)
+#define ANALOG_RESET			(0 << 2)
+
+/* PHY_REG1 */
+#define PHY_DDR2			(0)
+#define PHY_LPDDR2			(1)
+#define PHY_DDR3			(2)
+#define PHY_LPDDR3			(3)
+#define PHY_DDR4			(4)
+#define PHY_BL_4			(0 << 2)
+#define PHY_BL_8			BIT(2)
+
+/* PHY_REG2 */
+#define PHY_DTT_EN			BIT(0)
+#define PHY_DTT_DISB			(0 << 0)
+#define PHY_WRITE_LEVELING_EN		BIT(2)
+#define PHY_WRITE_LEVELING_DISB		(0 << 2)
+#define PHY_SELECT_CS0			(2)
+#define PHY_SELECT_CS1			(1)
+#define PHY_SELECT_CS0_1		(0)
+#define PHY_WRITE_LEVELING_SELECTCS(n)	(n << 6)
+#define PHY_DATA_TRAINING_SELECTCS(n)	(n << 4)
+
+#define PHY_DDR3_RON_RTT_DISABLE	(0)
+#define PHY_DDR3_RON_RTT_451ohm		(1)
+#define PHY_DDR3_RON_RTT_225ohm		(2)
+#define PHY_DDR3_RON_RTT_150ohm		(3)
+#define PHY_DDR3_RON_RTT_112ohm		(4)
+#define PHY_DDR3_RON_RTT_90ohm		(5)
+#define PHY_DDR3_RON_RTT_75ohm		(6)
+#define PHY_DDR3_RON_RTT_64ohm		(7)
+#define PHY_DDR3_RON_RTT_56ohm		(16)
+#define PHY_DDR3_RON_RTT_50ohm		(17)
+#define PHY_DDR3_RON_RTT_45ohm		(18)
+#define PHY_DDR3_RON_RTT_41ohm		(19)
+#define PHY_DDR3_RON_RTT_37ohm		(20)
+#define PHY_DDR3_RON_RTT_34ohm		(21)
+#define PHY_DDR3_RON_RTT_33ohm		(22)
+#define PHY_DDR3_RON_RTT_30ohm		(23)
+#define PHY_DDR3_RON_RTT_28ohm		(24)
+#define PHY_DDR3_RON_RTT_26ohm		(25)
+#define PHY_DDR3_RON_RTT_25ohm		(26)
+#define PHY_DDR3_RON_RTT_23ohm		(27)
+#define PHY_DDR3_RON_RTT_22ohm		(28)
+#define PHY_DDR3_RON_RTT_21ohm		(29)
+#define PHY_DDR3_RON_RTT_20ohm		(30)
+#define PHY_DDR3_RON_RTT_19ohm		(31)
+
+#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE	(0)
+#define PHY_DDR4_LPDDR3_RON_RTT_480ohm	(1)
+#define PHY_DDR4_LPDDR3_RON_RTT_240ohm	(2)
+#define PHY_DDR4_LPDDR3_RON_RTT_160ohm	(3)
+#define PHY_DDR4_LPDDR3_RON_RTT_120ohm	(4)
+#define PHY_DDR4_LPDDR3_RON_RTT_96ohm	(5)
+#define PHY_DDR4_LPDDR3_RON_RTT_80ohm	(6)
+#define PHY_DDR4_LPDDR3_RON_RTT_68ohm	(7)
+#define PHY_DDR4_LPDDR3_RON_RTT_60ohm	(16)
+#define PHY_DDR4_LPDDR3_RON_RTT_53ohm	(17)
+#define PHY_DDR4_LPDDR3_RON_RTT_48ohm	(18)
+#define PHY_DDR4_LPDDR3_RON_RTT_43ohm	(19)
+#define PHY_DDR4_LPDDR3_RON_RTT_40ohm	(20)
+#define PHY_DDR4_LPDDR3_RON_RTT_37ohm	(21)
+#define PHY_DDR4_LPDDR3_RON_RTT_34ohm	(22)
+#define PHY_DDR4_LPDDR3_RON_RTT_32ohm	(23)
+#define PHY_DDR4_LPDDR3_RON_RTT_30ohm	(24)
+#define PHY_DDR4_LPDDR3_RON_RTT_28ohm	(25)
+#define PHY_DDR4_LPDDR3_RON_RTT_26ohm	(26)
+#define PHY_DDR4_LPDDR3_RON_RTT_25ohm	(27)
+#define PHY_DDR4_LPDDR3_RON_RTT_24ohm	(28)
+#define PHY_DDR4_LPDDR3_RON_RTT_22ohm	(29)
+#define PHY_DDR4_LPDDR3_RON_RTT_21ohm	(30)
+#define PHY_DDR4_LPDDR3_RON_RTT_20ohm	(31)
+
+/* noc registers define */
+#define DDRCONF				0x8
+#define DDRTIMING			0xc
+#define DDRMODE				0x10
+#define READLATENCY			0x14
+#define AGING0				0x18
+#define AGING1				0x1c
+#define AGING2				0x20
+#define AGING3				0x24
+#define AGING4				0x28
+#define AGING5				0x2c
+#define ACTIVATE			0x38
+#define DEVTODEV			0x3c
+#define DDR4TIMING			0x40
+
+/* DDR GRF */
+#define DDR_GRF_CON(n)		(0 + (n) * 4)
+#define DDR_GRF_STATUS_BASE	(0X100)
+#define DDR_GRF_STATUS(n)	(DDR_GRF_STATUS_BASE + (n) * 4)
+
+/* CRU_SOFTRESET_CON5 */
+#define ddrphy_psrstn_req(n)    (((0x1 << 15) << 16) | (n << 15))
+#define ddrphy_srstn_req(n)     (((0x1 << 14) << 16) | (n << 14))
+#define ddrctrl_psrstn_req(n)	(((0x1 << 13) << 16) | (n << 13))
+#define ddrctrl_srstn_req(n)	(((0x1 << 12) << 16) | (n << 12))
+#define ddrmsch_srstn_req(n)	(((0x1 << 11) << 16) | (n << 11))
+#define msch_srstn_req(n)		(((0x1 << 9) << 16) | (n << 9))
+#define dfimon_srstn_req(n)		(((0x1 << 8) << 16) | (n << 8))
+#define grf_ddr_srstn_req(n)	(((0x1 << 7) << 16) | (n << 7))
+/* CRU_SOFTRESET_CON9 */
+#define ddrctrl_asrstn_req(n)		(((0x1 << 9) << 16) | (n << 9))
+
+/* CRU register */
+#define CRU_PLL_CON(pll_id, n)	((pll_id)  * 0x20 + (n) * 4)
+#define CRU_MODE				(0x80)
+#define CRU_GLB_CNT_TH			(0x90)
+#define CRU_CLKSEL_CON_BASE		0x100
+#define CRU_CLKSELS_CON(i)		(CRU_CLKSEL_CON_BASE + ((i) * 4))
+#define CRU_CLKGATE_CON_BASE		0x200
+#define CRU_CLKGATE_CON(i)		(CRU_CLKGATE_CON_BASE + ((i) * 4))
+#define CRU_CLKSFTRST_CON_BASE	0x300
+#define CRU_CLKSFTRST_CON(i)	(CRU_CLKSFTRST_CON_BASE + ((i) * 4))
+
+/* CRU_PLL_CON0 */
+#define PB(n)         ((0x1 << (15 + 16)) | ((n) << 15))
+#define POSTDIV1(n)   ((0x7 << (12 + 16)) | ((n) << 12))
+#define FBDIV(n)      ((0xFFF << 16) | (n))
+
+/* CRU_PLL_CON1 */
+#define RSTMODE(n)    ((0x1 << (15 + 16)) | ((n) << 15))
+#define RST(n)        ((0x1 << (14 + 16)) | ((n) << 14))
+#define PD(n)         ((0x1 << (13 + 16)) | ((n) << 13))
+#define DSMPD(n)      ((0x1 << (12 + 16)) | ((n) << 12))
+#define LOCK(n)       (((n) >> 10) & 0x1)
+#define POSTDIV2(n)   ((0x7 << (6 + 16)) | ((n) << 6))
+#define REFDIV(n)     ((0x3F << 16) | (n))
+
+union noc_ddrtiming {
+	u32 d32;
+	struct {
+		unsigned acttoact:6;
+		unsigned rdtomiss:6;
+		unsigned wrtomiss:6;
+		unsigned burstlen:3;
+		unsigned rdtowr:5;
+		unsigned wrtord:5;
+		unsigned bwratio:1;
+	} b;
+} NOC_TIMING_T;
+
+union noc_activate {
+	u32 d32;
+	struct {
+		unsigned rrd:4;
+		unsigned faw:6;
+		unsigned fawbank:1;
+		unsigned reserved1:21;
+	} b;
+};
+
+union noc_devtodev {
+	u32 d32;
+	struct {
+		unsigned busrdtord:2;
+		unsigned busrdtowr:2;
+		unsigned buswrtord:2;
+		unsigned reserved2:26;
+	} b;
+};
+
+union noc_ddr4timing {
+	u32 d32;
+	struct {
+		unsigned ccdl:3;
+		unsigned wrtordl:5;
+		unsigned rrdl:4;
+		unsigned reserved2:20;
+	} b;
+};
+
+union noc_ddrmode {
+	u32 d32;
+	struct {
+		unsigned autoprecharge:1;
+		unsigned bwratioextended:1;
+		unsigned reserved3:30;
+	} b;
+};
+
+u32 addrmap[21][9] = {
+	/* map0  map1  map2  map3  map4  map5  map6  map7  map8 */
+	{22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
+		0x06060606, 0x00000f0f, 0x3f3f},
+	{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x3f3f},
+	{23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
+		0x0f080808, 0x00000f0f, 0x3f3f},
+	{24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
+		0x08080808, 0x00000f0f, 0x3f3f},
+	{24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
+		0x0f090909, 0x00000f0f, 0x3f3f},
+	{6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x3f3f},
+	{7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x3f3f},
+	{8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909,
+		0x0f090909, 0x00000f0f, 0x3f3f},
+	{22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
+		0x06060606, 0x00000f0f, 0x3f3f},
+	{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
+		0x0f070707, 0x00000f0f, 0x3f3f},
+
+	{24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x0801},
+	{23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+		0x0f080808, 0x00000f0f, 0x0801},
+	{24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f07, 0x0700},
+	{23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x0700},
+	{24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f07, 0x3f01},
+	{23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x3f01},
+	{24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
+		0x06060606, 0x00000f06, 0x3f00},
+	{8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909,
+		0x0f090909, 0x00000f0f, 0x0801},
+	{7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x0700},
+	{7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x3f01},
+
+	{6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f07, 0x3f00}
+};
+
+struct rk3328_msch_timings {
+	union noc_ddrtiming ddrtiming;
+	union noc_ddrmode ddrmode;
+	u32 readlatency;
+	union noc_activate activate;
+	union noc_devtodev devtodev;
+	union noc_ddr4timing ddr4timing;
+	u32 agingx0;
+};
+
+struct rk3328_msch_regs {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 aging0;
+	u32 aging1;
+	u32 aging2;
+	u32 aging3;
+	u32 aging4;
+	u32 aging5;
+	u32 reserved[2];
+	u32 activate;
+	u32 devtodev;
+	u32 ddr4_timing;
+};
+
+struct rk3328_ddr_grf_regs {
+	u32 ddr_grf_con[4];
+	u32 reserved[(0x100 - 0x10) / 4];
+	u32 ddr_grf_status[11];
+};
+
+struct rk3328_ddr_pctl_regs {
+	u32 pctl[30][2];
+};
+
+struct rk3328_ddr_phy_regs {
+	u32 phy[5][2];
+};
+
+struct rk3328_ddr_skew {
+	u32 a0_a1_skew[15];
+	u32 cs0_dm0_skew[11];
+	u32 cs0_dm1_skew[11];
+	u32 cs0_dm2_skew[11];
+	u32 cs0_dm3_skew[11];
+	u32 cs1_dm0_skew[11];
+	u32 cs1_dm1_skew[11];
+	u32 cs1_dm2_skew[11];
+	u32 cs1_dm3_skew[11];
+};
+
+struct rk3328_sdram_channel {
+	unsigned int rank;
+	unsigned int col;
+	/* 3:8bank, 2:4bank */
+	unsigned int bk;
+	/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int bw;
+	/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int dbw;
+	unsigned int row_3_4;
+	unsigned int cs0_row;
+	unsigned int cs1_row;
+	unsigned int ddrconfig;
+	struct rk3328_msch_timings noc_timings;
+};
+
+struct rk3328_sdram_params {
+	struct rk3328_sdram_channel ch;
+	unsigned int ddr_freq;
+	unsigned int dramtype;
+	unsigned int odt;
+	struct rk3328_ddr_pctl_regs pctl_regs;
+	struct rk3328_ddr_phy_regs phy_regs;
+	struct rk3328_ddr_skew skew;
+};
+
+#define PHY_REG(base, n)		(base + 4 * (n))
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
new file mode 100644
index 0000000..dc65ae7
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3399_H
+#define _ASM_ARCH_SDRAM_RK3399_H
+
+struct rk3399_ddr_pctl_regs {
+	u32 denali_ctl[332];
+};
+
+struct rk3399_ddr_publ_regs {
+	u32 denali_phy[959];
+};
+
+struct rk3399_ddr_pi_regs {
+	u32 denali_pi[200];
+};
+
+union noc_ddrtimingc0 {
+	u32 d32;
+	struct {
+		unsigned burstpenalty : 4;
+		unsigned reserved0 : 4;
+		unsigned wrtomwr : 6;
+		unsigned reserved1 : 18;
+	} b;
+};
+
+union noc_ddrmode {
+	u32 d32;
+	struct {
+		unsigned autoprecharge : 1;
+		unsigned bypassfiltering : 1;
+		unsigned fawbank : 1;
+		unsigned burstsize : 2;
+		unsigned mwrsize : 2;
+		unsigned reserved2 : 1;
+		unsigned forceorder : 8;
+		unsigned forceorderstate : 8;
+		unsigned reserved3 : 8;
+	} b;
+};
+
+struct rk3399_msch_regs {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrsize;
+	u32 ddrtiminga0;
+	u32 ddrtimingb0;
+	u32 ddrtimingc0;
+	u32 devtodev0;
+	u32 reserved0[(0x110 - 0x20) / 4];
+	u32 ddrmode;
+	u32 reserved1[(0x1000 - 0x114) / 4];
+	u32 agingx0;
+};
+
+struct rk3399_msch_timings {
+	u32 ddrtiminga0;
+	u32 ddrtimingb0;
+	union noc_ddrtimingc0 ddrtimingc0;
+	u32 devtodev0;
+	union noc_ddrmode ddrmode;
+	u32 agingx0;
+};
+
+struct rk3399_ddr_cic_regs {
+	u32 cic_ctrl0;
+	u32 cic_ctrl1;
+	u32 cic_idle_th;
+	u32 cic_cg_wait_th;
+	u32 cic_status0;
+	u32 cic_status1;
+	u32 cic_ctrl2;
+	u32 cic_ctrl3;
+	u32 cic_ctrl4;
+};
+
+/* DENALI_CTL_00 */
+#define START		1
+
+/* DENALI_CTL_68 */
+#define PWRUP_SREFRESH_EXIT	(1 << 16)
+
+/* DENALI_CTL_274 */
+#define MEM_RST_VALID	1
+
+struct rk3399_sdram_channel {
+	struct sdram_cap_info cap_info;
+	struct rk3399_msch_timings noc_timings;
+};
+
+struct rk3399_sdram_params {
+	struct rk3399_sdram_channel ch[2];
+	struct sdram_base_params base;
+	struct rk3399_ddr_pctl_regs pctl_regs;
+	struct rk3399_ddr_pi_regs pi_regs;
+	struct rk3399_ddr_publ_regs phy_regs;
+};
+
+#define PI_CA_TRAINING		(1 << 0)
+#define PI_WRITE_LEVELING	(1 << 1)
+#define PI_READ_GATE_TRAINING	(1 << 2)
+#define PI_READ_LEVELING	(1 << 3)
+#define PI_WDQ_LEVELING		(1 << 4)
+#define PI_FULL_TRAINING	0xff
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
new file mode 100644
index 0000000..de5a8f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co.,Ltd
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h
new file mode 100644
index 0000000..77b5422
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/timer.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_TIMER_H
+#define __ASM_ARCH_TIMER_H
+
+struct rk_timer {
+	u32 timer_load_count0;
+	u32 timer_load_count1;
+	u32 timer_curr_value0;
+	u32 timer_curr_value1;
+	u32 timer_ctrl_reg;
+	u32 timer_int_status;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/uart.h b/arch/arm/include/asm/arch-rockchip/uart.h
new file mode 100644
index 0000000..feede5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/uart.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_UART_H
+#define __ASM_ARCH_UART_H
+struct rk_uart {
+	unsigned int rbr; /* Receive buffer register. */
+	unsigned int ier; /* Interrupt enable register. */
+	unsigned int fcr; /* FIFO control register. */
+	unsigned int lcr; /* Line control register. */
+	unsigned int mcr; /* Modem control register. */
+	unsigned int lsr; /* Line status register. */
+	unsigned int msr; /* Modem status register. */
+	unsigned int scr;
+	unsigned int reserved1[(0x30 - 0x20) / 4];
+	unsigned int srbr[(0x70 - 0x30) / 4];
+	unsigned int far;
+	unsigned int tfr;
+	unsigned int rfw;
+	unsigned int usr;
+	unsigned int tfl;
+	unsigned int rfl;
+	unsigned int srr;
+	unsigned int srts;
+	unsigned int sbcr;
+	unsigned int sdmam;
+	unsigned int sfe;
+	unsigned int srt;
+	unsigned int stet;
+	unsigned int htx;
+	unsigned int dmasa;
+	unsigned int reserver2[(0xf4 - 0xac) / 4];
+	unsigned int cpr;
+	unsigned int ucv;
+	unsigned int ctr;
+};
+
+void rk_uart_init(void *base);
+void print_hex(unsigned int n);
+void print(char *s);
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
new file mode 100644
index 0000000..8398249
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_VOP_RK3288_H
+#define _ASM_ARCH_VOP_RK3288_H
+
+struct rk3288_vop {
+	u32 reg_cfg_done;
+	u32 version_info;
+	u32 sys_ctrl;
+	u32 sys_ctrl1;
+	u32 dsp_ctrl0;
+	u32 dsp_ctrl1;
+	u32 dsp_bg;
+	u32 mcu_ctrl;
+	u32 intr_ctrl0;
+	u32 intr_ctrl1;
+	u32 intr_reserved0;
+	u32 intr_reserved1;
+
+	u32 win0_ctrl0;
+	u32 win0_ctrl1;
+	u32 win0_color_key;
+	u32 win0_vir;
+	u32 win0_yrgb_mst;
+	u32 win0_cbr_mst;
+	u32 win0_act_info;
+	u32 win0_dsp_info;
+	u32 win0_dsp_st;
+	u32 win0_scl_factor_yrgb;
+	u32 win0_scl_factor_cbr;
+	u32 win0_scl_offset;
+	u32 win0_src_alpha_ctrl;
+	u32 win0_dst_alpha_ctrl;
+	u32 win0_fading_ctrl;
+	u32 win0_reserved0;
+
+	u32 win1_ctrl0;
+	u32 win1_ctrl1;
+	u32 win1_color_key;
+	u32 win1_vir;
+	u32 win1_yrgb_mst;
+	u32 win1_cbr_mst;
+	u32 win1_act_info;
+	u32 win1_dsp_info;
+	u32 win1_dsp_st;
+	u32 win1_scl_factor_yrgb;
+	u32 win1_scl_factor_cbr;
+	u32 win1_scl_offset;
+	u32 win1_src_alpha_ctrl;
+	u32 win1_dst_alpha_ctrl;
+	u32 win1_fading_ctrl;
+	u32 win1_reservd0;
+	u32 reserved2[48];
+	u32 post_dsp_hact_info;
+	u32 post_dsp_vact_info;
+	u32 post_scl_factor_yrgb;
+	u32 post_reserved;
+	u32 post_scl_ctrl;
+	u32 post_dsp_vact_info_f1;
+	u32 dsp_htotal_hs_end;
+	u32 dsp_hact_st_end;
+	u32 dsp_vtotal_vs_end;
+	u32 dsp_vact_st_end;
+	u32 dsp_vs_st_end_f1;
+	u32 dsp_vact_st_end_f1;
+};
+check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
+
+enum rockchip_fb_data_format_t {
+	ARGB8888 = 0,
+	RGB888 = 1,
+	RGB565 = 2,
+};
+
+enum {
+	LB_YUV_3840X5 = 0x0,
+	LB_YUV_2560X8 = 0x1,
+	LB_RGB_3840X2 = 0x2,
+	LB_RGB_2560X4 = 0x3,
+	LB_RGB_1920X5 = 0x4,
+	LB_RGB_1280X8 = 0x5
+};
+
+enum vop_modes {
+	VOP_MODE_EDP = 0,
+	VOP_MODE_HDMI,
+	VOP_MODE_LVDS,
+	VOP_MODE_MIPI,
+	VOP_MODE_NONE,
+	VOP_MODE_AUTO_DETECT,
+	VOP_MODE_UNKNOWN,
+};
+
+/* VOP_VERSION_INFO */
+#define M_FPGA_VERSION (0xffff << 16)
+#define M_RTL_VERSION  (0xffff)
+
+/* VOP_SYS_CTRL */
+#define M_AUTO_GATING_EN (1 << 23)
+#define M_STANDBY_EN     (1 << 22)
+#define M_DMA_STOP       (1 << 21)
+#define M_MMU_EN         (1 << 20)
+#define M_DAM_BURST_LENGTH (0x3 << 18)
+#define M_MIPI_OUT_EN	   (1 << 15)
+#define M_EDP_OUT_EN       (1 << 14)
+#define M_HDMI_OUT_EN      (1 << 13)
+#define M_RGB_OUT_EN       (1 << 12)
+#define M_ALL_OUT_EN		\
+		(M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN)
+#define M_EDPI_WMS_FS      (1 << 10)
+#define M_EDPI_WMS_MODE    (1 << 9)
+#define M_EDPI_HALT_EN     (1 << 8)
+#define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
+#define M_DOUB_CHANNEL_EN     (1 << 3)
+#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
+#define M_DIRECT_PATH_EN       (1)
+
+#define V_AUTO_GATING_EN(x) (((x) & 1) << 23)
+#define V_STANDBY_EN(x)     (((x) & 1) << 22)
+#define V_DMA_STOP(x)       (((x) & 1) << 21)
+#define V_MMU_EN(x)         (((x) & 1) << 20)
+#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18)
+#define V_MIPI_OUT_EN(x)      (((x) & 1) << 15)
+#define V_EDP_OUT_EN(x)       (((x) & 1) << 14)
+#define V_HDMI_OUT_EN(x)      (((x) & 1) << 13)
+#define V_RGB_OUT_EN(x)       (((x) & 1) << 12)
+#define V_EDPI_WMS_FS(x)      (((x) & 1) << 10)
+#define V_EDPI_WMS_MODE(x)    (((x) & 1) << 9)
+#define V_EDPI_HALT_EN(x)     (((x)&1)<<8)
+#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
+#define V_DOUB_CHANNEL_EN(x)     (((x) & 1) << 3)
+#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1)
+#define V_DIRECT_PATH_EN(x)       ((x) & 1)
+
+/* VOP_SYS_CTRL1 */
+#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
+#define M_AXI_MAX_OUTSTANDING_EN  (1 << 12)
+#define M_NOC_WIN_QOS             (3 << 10)
+#define M_NOC_QOS_EN              (1 << 9)
+#define M_NOC_HURRY_THRESHOLD     (0x3f << 3)
+#define M_NOC_HURRY_VALUE         (0x3 << 1)
+#define M_NOC_HURRY_EN            (1)
+
+#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13)
+#define V_AXI_MAX_OUTSTANDING_EN(x)  (((x) & 1) << 12)
+#define V_NOC_WIN_QOS(x)             (((x) & 3) << 10)
+#define V_NOC_QOS_EN(x)              (((x) & 1) << 9)
+#define V_NOC_HURRY_THRESHOLD(x)     (((x) & 0x3f) << 3)
+#define V_NOC_HURRY_VALUE(x)         (((x) & 3) << 1)
+#define V_NOC_HURRY_EN(x)            ((x) & 1)
+
+/* VOP_DSP_CTRL0 */
+#define M_DSP_Y_MIR_EN              (1 << 23)
+#define M_DSP_X_MIR_EN              (1 << 22)
+#define M_DSP_YUV_CLIP              (1 << 21)
+#define M_DSP_CCIR656_AVG           (1 << 20)
+#define M_DSP_BLACK_EN              (1 << 19)
+#define M_DSP_BLANK_EN              (1 << 18)
+#define M_DSP_OUT_ZERO              (1 << 17)
+#define M_DSP_DUMMY_SWAP            (1 << 16)
+#define M_DSP_DELTA_SWAP            (1 << 15)
+#define M_DSP_RG_SWAP               (1 << 14)
+#define M_DSP_RB_SWAP               (1 << 13)
+#define M_DSP_BG_SWAP               (1 << 12)
+#define M_DSP_FIELD_POL             (1 << 11)
+#define M_DSP_INTERLACE             (1 << 10)
+#define M_DSP_DDR_PHASE             (1 << 9)
+#define M_DSP_DCLK_DDR              (1 << 8)
+#define M_DSP_DCLK_POL              (1 << 7)
+#define M_DSP_DEN_POL               (1 << 6)
+#define M_DSP_VSYNC_POL             (1 << 5)
+#define M_DSP_HSYNC_POL             (1 << 4)
+#define M_DSP_OUT_MODE              (0xf)
+
+#define V_DSP_Y_MIR_EN(x)              (((x) & 1) << 23)
+#define V_DSP_X_MIR_EN(x)              (((x) & 1) << 22)
+#define V_DSP_YUV_CLIP(x)              (((x) & 1) << 21)
+#define V_DSP_CCIR656_AVG(x)           (((x) & 1) << 20)
+#define V_DSP_BLACK_EN(x)              (((x) & 1) << 19)
+#define V_DSP_BLANK_EN(x)              (((x) & 1) << 18)
+#define V_DSP_OUT_ZERO(x)              (((x) & 1) << 17)
+#define V_DSP_DUMMY_SWAP(x)            (((x) & 1) << 16)
+#define V_DSP_DELTA_SWAP(x)            (((x) & 1) << 15)
+#define V_DSP_RG_SWAP(x)               (((x) & 1) << 14)
+#define V_DSP_RB_SWAP(x)               (((x) & 1) << 13)
+#define V_DSP_BG_SWAP(x)               (((x) & 1) << 12)
+#define V_DSP_FIELD_POL(x)             (((x) & 1) << 11)
+#define V_DSP_INTERLACE(x)             (((x) & 1) << 10)
+#define V_DSP_DDR_PHASE(x)             (((x) & 1) << 9)
+#define V_DSP_DCLK_DDR(x)              (((x) & 1) << 8)
+#define V_DSP_DCLK_POL(x)              (((x) & 1) << 7)
+#define V_DSP_DEN_POL(x)               (((x) & 1) << 6)
+#define V_DSP_VSYNC_POL(x)             (((x) & 1) << 5)
+#define V_DSP_HSYNC_POL(x)             (((x) & 1) << 4)
+#define V_DSP_PIN_POL(x)               (((x) & 0xf) << 4)
+#define V_DSP_OUT_MODE(x)              ((x) & 0xf)
+
+/* VOP_DSP_CTRL1 */
+#define V_RK3399_DSP_MIPI_POL(x)       ((x) << 28)
+#define V_RK3399_DSP_EDP_POL(x)        ((x) << 24)
+#define V_RK3399_DSP_HDMI_POL(x)       ((x) << 20)
+#define V_RK3399_DSP_LVDS_POL(x)       ((x) << 16)
+
+#define M_RK3399_DSP_MIPI_POL          (V_RK3399_DSP_MIPI_POL(0xf))
+#define M_RK3399_DSP_EDP_POL           (V_RK3399_DSP_EDP_POL(0xf))
+#define M_RK3399_DSP_HDMI_POL          (V_RK3399_DSP_HDMI_POL(0xf))
+#define M_RK3399_DSP_LVDS_POL          (V_RK3399_DSP_LVDS_POL(0xf))
+
+#define M_DSP_LAYER3_SEL               (3 << 14)
+#define M_DSP_LAYER2_SEL               (3 << 12)
+#define M_DSP_LAYER1_SEL               (3 << 10)
+#define M_DSP_LAYER0_SEL               (3 << 8)
+#define M_DITHER_UP_EN                 (1 << 6)
+#define M_DITHER_DOWN_SEL              (1 << 4)
+#define M_DITHER_DOWN_MODE             (1 << 3)
+#define M_DITHER_DOWN_EN               (1 << 2)
+#define M_PRE_DITHER_DOWN_EN           (1 << 1)
+#define M_DSP_LUT_EN                   (1)
+
+#define V_DSP_LAYER3_SEL(x)                (((x) & 3) << 14)
+#define V_DSP_LAYER2_SEL(x)                (((x) & 3) << 12)
+#define V_DSP_LAYER1_SEL(x)                (((x) & 3) << 10)
+#define V_DSP_LAYER0_SEL(x)                (((x) & 3) << 8)
+#define V_DITHER_UP_EN(x)                  (((x) & 1) << 6)
+#define V_DITHER_DOWN_SEL(x)               (((x) & 1) << 4)
+#define V_DITHER_DOWN_MODE(x)              (((x) & 1) << 3)
+#define V_DITHER_DOWN_EN(x)                (((x) & 1) << 2)
+#define V_PRE_DITHER_DOWN_EN(x)            (((x) & 1) << 1)
+#define V_DSP_LUT_EN(x)                    ((x)&1)
+
+/* VOP_DSP_BG */
+#define M_DSP_BG_RED     (0x3f << 20)
+#define M_DSP_BG_GREEN   (0x3f << 10)
+#define M_DSP_BG_BLUE    (0x3f << 0)
+
+#define V_DSP_BG_RED(x)     (((x) & 0x3f) << 20)
+#define V_DSP_BG_GREEN(x)   (((x) & 0x3f) << 10)
+#define V_DSP_BG_BLUE(x)    (((x) & 0x3f) << 0)
+
+/* VOP_WIN0_CTRL0 */
+#define M_WIN0_YUV_CLIP     (1 << 20)
+#define M_WIN0_CBR_DEFLICK  (1 << 19)
+#define M_WIN0_YRGB_DEFLICK  (1 << 18)
+#define M_WIN0_PPAS_ZERO_EN  (1 << 16)
+#define M_WIN0_UV_SWAP       (1 << 15)
+#define M_WIN0_MID_SWAP      (1 << 14)
+#define M_WIN0_ALPHA_SWAP    (1 << 13)
+#define M_WIN0_RB_SWAP       (1 << 12)
+#define M_WIN0_CSC_MODE      (3 << 10)
+#define M_WIN0_NO_OUTSTANDING (1 << 9)
+#define M_WIN0_INTERLACE_READ  (1 << 8)
+#define M_WIN0_LB_MODE         (7 << 5)
+#define M_WIN0_FMT_10          (1 << 4)
+#define M_WIN0_DATA_FMT        (7 << 1)
+#define M_WIN0_EN              (1 << 0)
+
+#define V_WIN0_YUV_CLIP(x)       (((x) & 1) << 20)
+#define V_WIN0_CBR_DEFLICK(x)    (((x) & 1) << 19)
+#define V_WIN0_YRGB_DEFLICK(x)   (((x) & 1) << 18)
+#define V_WIN0_PPAS_ZERO_EN(x)   (((x) & 1) << 16)
+#define V_WIN0_UV_SWAP(x)        (((x) & 1) << 15)
+#define V_WIN0_MID_SWAP(x)       (((x) & 1) << 14)
+#define V_WIN0_ALPHA_SWAP(x)     (((x) & 1) << 13)
+#define V_WIN0_RB_SWAP(x)        (((x) & 1) << 12)
+#define V_WIN0_CSC_MODE(x)       (((x) & 3) << 10)
+#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9)
+#define V_WIN0_INTERLACE_READ(x)  (((x) & 1) << 8)
+#define V_WIN0_LB_MODE(x)         (((x) & 7) << 5)
+#define V_WIN0_FMT_10(x)          (((x) & 1) << 4)
+#define V_WIN0_DATA_FMT(x)        (((x) & 7) << 1)
+#define V_WIN0_EN(x)              ((x) & 1)
+
+/* VOP_WIN0_CTRL1 */
+#define M_WIN0_CBR_VSD_MODE        (1 << 31)
+#define M_WIN0_CBR_VSU_MODE        (1 << 30)
+#define M_WIN0_CBR_HSD_MODE        (3 << 28)
+#define M_WIN0_CBR_VER_SCL_MODE    (3 << 26)
+#define M_WIN0_CBR_HOR_SCL_MODE    (3 << 24)
+#define M_WIN0_YRGB_VSD_MODE       (1 << 23)
+#define M_WIN0_YRGB_VSU_MODE       (1 << 22)
+#define M_WIN0_YRGB_HSD_MODE       (3 << 20)
+#define M_WIN0_YRGB_VER_SCL_MODE   (3 << 18)
+#define M_WIN0_YRGB_HOR_SCL_MODE   (3 << 16)
+#define M_WIN0_LINE_LOAD_MODE      (1 << 15)
+#define M_WIN0_CBR_AXI_GATHER_NUM  (7 << 12)
+#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8)
+#define M_WIN0_VSD_CBR_GT2         (1 << 7)
+#define M_WIN0_VSD_CBR_GT4         (1 << 6)
+#define M_WIN0_VSD_YRGB_GT2        (1 << 5)
+#define M_WIN0_VSD_YRGB_GT4        (1 << 4)
+#define M_WIN0_BIC_COE_SEL         (3 << 2)
+#define M_WIN0_CBR_AXI_GATHER_EN   (1 << 1)
+#define M_WIN0_YRGB_AXI_GATHER_EN  (1)
+
+#define V_WIN0_CBR_VSD_MODE(x)        (((x) & 1) << 31)
+#define V_WIN0_CBR_VSU_MODE(x)        (((x) & 1) << 30)
+#define V_WIN0_CBR_HSD_MODE(x)        (((x) & 3) << 28)
+#define V_WIN0_CBR_VER_SCL_MODE(x)    (((x) & 3) << 26)
+#define V_WIN0_CBR_HOR_SCL_MODE(x)    (((x) & 3) << 24)
+#define V_WIN0_YRGB_VSD_MODE(x)       (((x) & 1) << 23)
+#define V_WIN0_YRGB_VSU_MODE(x)       (((x) & 1) << 22)
+#define V_WIN0_YRGB_HSD_MODE(x)       (((x) & 3) << 20)
+#define V_WIN0_YRGB_VER_SCL_MODE(x)   (((x) & 3) << 18)
+#define V_WIN0_YRGB_HOR_SCL_MODE(x)   (((x) & 3) << 16)
+#define V_WIN0_LINE_LOAD_MODE(x)      (((x) & 1) << 15)
+#define V_WIN0_CBR_AXI_GATHER_NUM(x)  (((x) & 7) << 12)
+#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8)
+#define V_WIN0_VSD_CBR_GT2(x)         (((x) & 1) << 7)
+#define V_WIN0_VSD_CBR_GT4(x)         (((x) & 1) << 6)
+#define V_WIN0_VSD_YRGB_GT2(x)        (((x) & 1) << 5)
+#define V_WIN0_VSD_YRGB_GT4(x)        (((x) & 1) << 4)
+#define V_WIN0_BIC_COE_SEL(x)         (((x) & 3) << 2)
+#define V_WIN0_CBR_AXI_GATHER_EN(x)   (((x) & 1) << 1)
+#define V_WIN0_YRGB_AXI_GATHER_EN(x)  ((x) & 1)
+
+/*VOP_WIN0_COLOR_KEY*/
+#define M_WIN0_KEY_EN                 (1 << 31)
+#define M_WIN0_KEY_COLOR              (0x3fffffff)
+
+#define V_WIN0_KEY_EN(x)              (((x) & 1) << 31)
+#define V_WIN0_KEY_COLOR(x)           ((x) & 0x3fffffff)
+
+/* VOP_WIN0_VIR */
+#define V_ARGB888_VIRWIDTH(x)	(((x) & 0x3fff) << 0)
+#define V_RGB888_VIRWIDTH(x)	(((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0)
+#define V_RGB565_VIRWIDTH(x)	(((x / 2) & 0x3fff) << 0)
+#define YUV_VIRWIDTH(x)		(((x / 4) & 0x3fff) << 0)
+
+/* VOP_WIN0_ACT_INFO */
+#define V_ACT_HEIGHT(x)         (((x) & 0x1fff) << 16)
+#define V_ACT_WIDTH(x)          ((x) & 0x1fff)
+
+/* VOP_WIN0_DSP_INFO */
+#define V_DSP_HEIGHT(x)         (((x) & 0xfff) << 16)
+#define V_DSP_WIDTH(x)          ((x) & 0xfff)
+
+/* VOP_WIN0_DSP_ST */
+#define V_DSP_YST(x)            (((x) & 0x1fff) << 16)
+#define V_DSP_XST(x)            ((x) & 0x1fff)
+
+/* VOP_WIN0_SCL_OFFSET */
+#define V_WIN0_VS_OFFSET_CBR(x)     (((x) & 0xff) << 24)
+#define V_WIN0_VS_OFFSET_YRGB(x)    (((x) & 0xff) << 16)
+#define V_WIN0_HS_OFFSET_CBR(x)     (((x) & 0xff) << 8)
+#define V_WIN0_HS_OFFSET_YRGB(x)    ((x) & 0xff)
+
+#define V_HSYNC(x)		(((x)&0x1fff)<<0)   /* hsync pulse width */
+#define V_HORPRD(x)		(((x)&0x1fff)<<16)   /* horizontal period */
+#define V_VSYNC(x)		(((x)&0x1fff)<<0)
+#define V_VERPRD(x)		(((x)&0x1fff)<<16)
+
+#define V_HEAP(x)		(((x)&0x1fff)<<0)/* horizontal active end */
+#define V_HASP(x)		(((x)&0x1fff)<<16)/* horizontal active start */
+#define V_VAEP(x)		(((x)&0x1fff)<<0)
+#define V_VASP(x)		(((x)&0x1fff)<<16)
+
+#endif