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author | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:21:52 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-10-30 14:48:38 +0800 |
commit | ae51f41d14f548d494ac41e0d21137c5a4c3f59c (patch) | |
tree | 6ddb9d1aaa7bd5bad5bbf8497edc2e08ff208d79 /arch/nios2/include/asm/cache.h | |
download | uext4-ae51f41d14f548d494ac41e0d21137c5a4c3f59c.tar.xz |
import the U-Boot code and make it compile
Diffstat (limited to 'arch/nios2/include/asm/cache.h')
-rw-r--r-- | arch/nios2/include/asm/cache.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h new file mode 100644 index 0000000..5784884 --- /dev/null +++ b/arch/nios2/include/asm/cache.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + */ + +#ifndef __ASM_NIOS2_CACHE_H_ +#define __ASM_NIOS2_CACHE_H_ + +/* + * Valid L1 data cache line sizes for the NIOS2 architecture are 4, + * 16, and 32 bytes. We default to the largest of these values for + * alignment of DMA buffers. + */ +#define ARCH_DMA_MINALIGN 32 + +#endif /* __ASM_NIOS2_CACHE_H_ */ |