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authorIru Cai <mytbk920423@gmail.com>2019-10-30 14:21:52 +0800
committerIru Cai <mytbk920423@gmail.com>2019-10-30 14:48:38 +0800
commitae51f41d14f548d494ac41e0d21137c5a4c3f59c (patch)
tree6ddb9d1aaa7bd5bad5bbf8497edc2e08ff208d79 /arch/powerpc
downloaduext4-ae51f41d14f548d494ac41e0d21137c5a4c3f59c.tar.xz
import the U-Boot code and make it compile
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/arch-mpc83xx/clock.h22
-rw-r--r--arch/powerpc/include/asm/arch-mpc83xx/gpio.h31
-rw-r--r--arch/powerpc/include/asm/arch-mpc83xx/soc.h74
-rw-r--r--arch/powerpc/include/asm/arch-mpc85xx/gpio.h26
-rw-r--r--arch/powerpc/include/asm/arch-ppc4xx/gpio.h6
-rw-r--r--arch/powerpc/include/asm/atomic.h93
-rw-r--r--arch/powerpc/include/asm/bitops.h370
-rw-r--r--arch/powerpc/include/asm/byteorder.h84
-rw-r--r--arch/powerpc/include/asm/cache.h144
-rw-r--r--arch/powerpc/include/asm/config.h79
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h434
-rw-r--r--arch/powerpc/include/asm/config_mpc86xx.h9
-rw-r--r--arch/powerpc/include/asm/cpm_85xx.h829
-rw-r--r--arch/powerpc/include/asm/cpm_8xx.h687
-rw-r--r--arch/powerpc/include/asm/e300.h91
-rw-r--r--arch/powerpc/include/asm/fsl_dma.h124
-rw-r--r--arch/powerpc/include/asm/fsl_fdt.h10
-rw-r--r--arch/powerpc/include/asm/fsl_i2c.h80
-rw-r--r--arch/powerpc/include/asm/fsl_law.h147
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h535
-rw-r--r--arch/powerpc/include/asm/fsl_liodn.h247
-rw-r--r--arch/powerpc/include/asm/fsl_mpc83xx_serdes.h26
-rw-r--r--arch/powerpc/include/asm/fsl_pamu.h168
-rw-r--r--arch/powerpc/include/asm/fsl_pci.h273
-rw-r--r--arch/powerpc/include/asm/fsl_portals.h47
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h141
-rw-r--r--arch/powerpc/include/asm/fsl_serdes.h125
-rw-r--r--arch/powerpc/include/asm/fsl_srio.h47
-rw-r--r--arch/powerpc/include/asm/global_data.h120
-rw-r--r--arch/powerpc/include/asm/gpio.h2
-rw-r--r--arch/powerpc/include/asm/immap_83xx.h996
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h3141
-rw-r--r--arch/powerpc/include/asm/immap_86xx.h1221
-rw-r--r--arch/powerpc/include/asm/immap_8xx.h468
-rw-r--r--arch/powerpc/include/asm/interrupt.h13
-rw-r--r--arch/powerpc/include/asm/io.h325
-rw-r--r--arch/powerpc/include/asm/iopin_8xx.h466
-rw-r--r--arch/powerpc/include/asm/linkage.h6
-rw-r--r--arch/powerpc/include/asm/mc146818rtc.h27
-rw-r--r--arch/powerpc/include/asm/mmu.h588
-rw-r--r--arch/powerpc/include/asm/mp.h22
-rw-r--r--arch/powerpc/include/asm/mpc8349_pci.h168
-rw-r--r--arch/powerpc/include/asm/mpc85xx_gpio.h114
-rw-r--r--arch/powerpc/include/asm/mpc8xxx_spi.h32
-rw-r--r--arch/powerpc/include/asm/pci_io.h43
-rw-r--r--arch/powerpc/include/asm/posix_types.h109
-rw-r--r--arch/powerpc/include/asm/ppc.h135
-rw-r--r--arch/powerpc/include/asm/processor.h1220
-rw-r--r--arch/powerpc/include/asm/ptrace.h105
-rw-r--r--arch/powerpc/include/asm/sections.h11
-rw-r--r--arch/powerpc/include/asm/sigcontext.h15
-rw-r--r--arch/powerpc/include/asm/signal.h154
-rw-r--r--arch/powerpc/include/asm/spl.h11
-rw-r--r--arch/powerpc/include/asm/string.h29
-rw-r--r--arch/powerpc/include/asm/types.h36
-rw-r--r--arch/powerpc/include/asm/u-boot.h23
-rw-r--r--arch/powerpc/include/asm/unaligned.h16
57 files changed, 14565 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/clock.h b/arch/powerpc/include/asm/arch-mpc83xx/clock.h
new file mode 100644
index 0000000..d57e93c
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc83xx/clock.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_POWERPC_CLOCK_H
+#define __ASM_POWERPC_CLOCK_H
+
+/* Make fsl_esdhc driver happy */
+enum mxc_clock {
+ MXC_ESDHC_CLK,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+uint mxc_get_clock(int clk)
+{
+ return gd->arch.sdhc_clk;
+}
+#endif /* __ASM_POWERPC_CLOCK_H */
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
new file mode 100644
index 0000000..385d651
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _MPC83XX_GPIO_H_
+#define _MPC83XX_GPIO_H_
+
+/*
+ * The MCP83xx's 1-2 GPIO controllers each with 32 bits.
+ */
+#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
+ defined(CONFIG_ARCH_MPC8315)
+#define MPC83XX_GPIO_CTRLRS 1
+#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+#define MPC83XX_GPIO_CTRLRS 2
+#else
+#define MPC83XX_GPIO_CTRLRS 0
+#endif
+
+#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
+
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ unsigned long size;
+ uint ngpios;
+};
+
+#ifndef DM_GPIO
+void mpc83xx_gpio_init_f(void);
+void mpc83xx_gpio_init_r(void);
+#endif /* DM_GPIO */
+
+#endif /* MPC83XX_GPIO_H_ */
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
new file mode 100644
index 0000000..39bf7d5
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef _MPC83XX_SOC_H_
+#define _MPC83XX_SOC_H_
+
+enum soc_type {
+ SOC_MPC8308,
+ SOC_MPC8309,
+ SOC_MPC8313,
+ SOC_MPC8315,
+ SOC_MPC832X,
+ SOC_MPC8349,
+ SOC_MPC8360,
+ SOC_MPC8379,
+};
+
+bool mpc83xx_has_sdhc(int type)
+{
+ return (type == SOC_MPC8308) ||
+ (type == SOC_MPC8309) ||
+ (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_tsec(int type)
+{
+ return (type == SOC_MPC8308) ||
+ (type == SOC_MPC8313) ||
+ (type == SOC_MPC8315) ||
+ (type == SOC_MPC8349) ||
+ (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_pcie1(int type)
+{
+ return (type == SOC_MPC8308) ||
+ (type == SOC_MPC8315) ||
+ (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_pcie2(int type)
+{
+ return (type == SOC_MPC8315) ||
+ (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_sata(int type)
+{
+ return (type == SOC_MPC8315) ||
+ (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_pci(int type)
+{
+ return type != SOC_MPC8308;
+}
+
+bool mpc83xx_has_second_i2c(int type)
+{
+ return (type != SOC_MPC8315) &&
+ (type != SOC_MPC832X);
+}
+
+bool mpc83xx_has_quicc_engine(int type)
+{
+ return (type == SOC_MPC8309) ||
+ (type == SOC_MPC832X) ||
+ (type == SOC_MPC8360);
+}
+
+#endif /* _MPC83XX_SOC_H_ */
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
new file mode 100644
index 0000000..c7086a8
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+#ifndef CONFIG_MPC85XX_GPIO
+#include <asm/mpc85xx_gpio.h>
+#endif
+
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ unsigned long size;
+ uint ngpios;
+};
+
+#endif
diff --git a/arch/powerpc/include/asm/arch-ppc4xx/gpio.h b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
new file mode 100644
index 0000000..e74a2e1
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Google, Inc
+ */
+
+/* This is empty for now as we don't support the generic GPIO interface */
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
new file mode 100644
index 0000000..87efcca
--- /dev/null
+++ b/arch/powerpc/include/asm/atomic.h
@@ -0,0 +1,93 @@
+/*
+ * PowerPC atomic operations
+ */
+
+#ifndef _ASM_PPC_ATOMIC_H_
+#define _ASM_PPC_ATOMIC_H_
+
+#ifdef CONFIG_SMP
+typedef struct { volatile int counter; } atomic_t;
+#else
+typedef struct { int counter; } atomic_t;
+#endif
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v,i) (((v)->counter) = (i))
+
+extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
+extern void atomic_set_mask(unsigned long mask, unsigned long *addr);
+
+static __inline__ int atomic_add_return(int a, atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__("\n\
+1: lwarx %0,0,%3\n\
+ add %0,%2,%0\n\
+ stwcx. %0,0,%3\n\
+ bne- 1b"
+ : "=&r" (t), "=m" (*v)
+ : "r" (a), "r" (v), "m" (*v)
+ : "cc");
+
+ return t;
+}
+
+static __inline__ int atomic_sub_return(int a, atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__("\n\
+1: lwarx %0,0,%3\n\
+ subf %0,%2,%0\n\
+ stwcx. %0,0,%3\n\
+ bne- 1b"
+ : "=&r" (t), "=m" (*v)
+ : "r" (a), "r" (v), "m" (*v)
+ : "cc");
+
+ return t;
+}
+
+static __inline__ int atomic_inc_return(atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__("\n\
+1: lwarx %0,0,%2\n\
+ addic %0,%0,1\n\
+ stwcx. %0,0,%2\n\
+ bne- 1b"
+ : "=&r" (t), "=m" (*v)
+ : "r" (v), "m" (*v)
+ : "cc");
+
+ return t;
+}
+
+static __inline__ int atomic_dec_return(atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__("\n\
+1: lwarx %0,0,%2\n\
+ addic %0,%0,-1\n\
+ stwcx. %0,0,%2\n\
+ bne 1b"
+ : "=&r" (t), "=m" (*v)
+ : "r" (v), "m" (*v)
+ : "cc");
+
+ return t;
+}
+
+#define atomic_add(a, v) ((void) atomic_add_return((a), (v)))
+#define atomic_sub(a, v) ((void) atomic_sub_return((a), (v)))
+#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
+#define atomic_inc(v) ((void) atomic_inc_return((v)))
+#define atomic_dec(v) ((void) atomic_dec_return((v)))
+#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
+
+#endif /* _ASM_PPC_ATOMIC_H_ */
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
new file mode 100644
index 0000000..96491b6
--- /dev/null
+++ b/arch/powerpc/include/asm/bitops.h
@@ -0,0 +1,370 @@
+/*
+ * bitops.h: Bit string operations on the ppc
+ */
+
+#ifndef _PPC_BITOPS_H
+#define _PPC_BITOPS_H
+
+#include <asm/byteorder.h>
+#include <asm-generic/bitops/__ffs.h>
+
+/*
+ * Arguably these bit operations don't imply any memory barrier or
+ * SMP ordering, but in fact a lot of drivers expect them to imply
+ * both, since they do on x86 cpus.
+ */
+#ifdef CONFIG_SMP
+#define SMP_WMB "eieio\n"
+#define SMP_MB "\nsync"
+#else
+#define SMP_WMB
+#define SMP_MB
+#endif /* CONFIG_SMP */
+
+#define __INLINE_BITOPS 1
+
+#if __INLINE_BITOPS
+/*
+ * These used to be if'd out here because using : "cc" as a constraint
+ * resulted in errors from egcs. Things may be OK with gcc-2.95.
+ */
+static __inline__ void set_bit(int nr, volatile void * addr)
+{
+ unsigned long old;
+ unsigned long mask = 1 << (nr & 0x1f);
+ unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+ __asm__ __volatile__(SMP_WMB "\
+1: lwarx %0,0,%3\n\
+ or %0,%0,%2\n\
+ stwcx. %0,0,%3\n\
+ bne 1b"
+ SMP_MB
+ : "=&r" (old), "=m" (*p)
+ : "r" (mask), "r" (p), "m" (*p)
+ : "cc" );
+}
+
+static __inline__ void clear_bit(int nr, volatile void *addr)
+{
+ unsigned long old;
+ unsigned long mask = 1 << (nr & 0x1f);
+ unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+ __asm__ __volatile__(SMP_WMB "\
+1: lwarx %0,0,%3\n\
+ andc %0,%0,%2\n\
+ stwcx. %0,0,%3\n\
+ bne 1b"
+ SMP_MB
+ : "=&r" (old), "=m" (*p)
+ : "r" (mask), "r" (p), "m" (*p)
+ : "cc");
+}
+
+static __inline__ void change_bit(int nr, volatile void *addr)
+{
+ unsigned long old;
+ unsigned long mask = 1 << (nr & 0x1f);
+ unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+ __asm__ __volatile__(SMP_WMB "\
+1: lwarx %0,0,%3\n\
+ xor %0,%0,%2\n\
+ stwcx. %0,0,%3\n\
+ bne 1b"
+ SMP_MB
+ : "=&r" (old), "=m" (*p)
+ : "r" (mask), "r" (p), "m" (*p)
+ : "cc");
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+ unsigned int old, t;
+ unsigned int mask = 1 << (nr & 0x1f);
+ volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+ __asm__ __volatile__(SMP_WMB "\
+1: lwarx %0,0,%4\n\
+ or %1,%0,%3\n\
+ stwcx. %1,0,%4\n\
+ bne 1b"
+ SMP_MB
+ : "=&r" (old), "=&r" (t), "=m" (*p)
+ : "r" (mask), "r" (p), "m" (*p)
+ : "cc");
+
+ return (old & mask) != 0;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+ unsigned int old, t;
+ unsigned int mask = 1 << (nr & 0x1f);
+ volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+ __asm__ __volatile__(SMP_WMB "\
+1: lwarx %0,0,%4\n\
+ andc %1,%0,%3\n\
+ stwcx. %1,0,%4\n\
+ bne 1b"
+ SMP_MB
+ : "=&r" (old), "=&r" (t), "=m" (*p)
+ : "r" (mask), "r" (p), "m" (*p)
+ : "cc");
+
+ return (old & mask) != 0;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+ unsigned int old, t;
+ unsigned int mask = 1 << (nr & 0x1f);
+ volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+ __asm__ __volatile__(SMP_WMB "\
+1: lwarx %0,0,%4\n\
+ xor %1,%0,%3\n\
+ stwcx. %1,0,%4\n\
+ bne 1b"
+ SMP_MB
+ : "=&r" (old), "=&r" (t), "=m" (*p)
+ : "r" (mask), "r" (p), "m" (*p)
+ : "cc");
+
+ return (old & mask) != 0;
+}
+#endif /* __INLINE_BITOPS */
+
+static __inline__ int test_bit(int nr, __const__ volatile void *addr)
+{
+ __const__ unsigned int *p = (__const__ unsigned int *) addr;
+
+ return ((p[nr >> 5] >> (nr & 0x1f)) & 1) != 0;
+}
+
+/* Return the bit position of the most significant 1 bit in a word */
+/* - the result is undefined when x == 0 */
+static __inline__ int __ilog2(unsigned int x)
+{
+ int lz;
+
+ asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+ return 31 - lz;
+}
+
+static __inline__ int ffz(unsigned int x)
+{
+ if ((x = ~x) == 0)
+ return 32;
+ return __ilog2(x & -x);
+}
+
+/*
+ * fls: find last (most-significant) bit set.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ *
+ * On powerpc, __ilog2(0) returns -1, but this is not safe in general
+ */
+static __inline__ int fls(unsigned int x)
+{
+ return __ilog2(x) + 1;
+}
+#define PLATFORM_FLS
+
+/**
+ * fls64 - find last set bit in a 64-bit word
+ * @x: the word to search
+ *
+ * This is defined in a similar way as the libc and compiler builtin
+ * ffsll, but returns the position of the most significant set bit.
+ *
+ * fls64(value) returns 0 if value is 0 or the position of the last
+ * set bit if value is nonzero. The last (most significant) bit is
+ * at position 64.
+ */
+#if BITS_PER_LONG == 32
+static inline int fls64(__u64 x)
+{
+ __u32 h = x >> 32;
+ if (h)
+ return fls(h) + 32;
+ return fls(x);
+}
+#elif BITS_PER_LONG == 64
+static inline int fls64(__u64 x)
+{
+ if (x == 0)
+ return 0;
+ return __ilog2(x) + 1;
+}
+#else
+#error BITS_PER_LONG not 32 or 64
+#endif
+
+#ifdef __KERNEL__
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int ffs(int x)
+{
+ return __ilog2(x & -x) + 1;
+}
+#define PLATFORM_FFS
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+/*
+ * This implementation of find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h.
+ */
+#define find_first_zero_bit(addr, size) \
+ find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long find_next_zero_bit(void * addr,
+ unsigned long size, unsigned long offset)
+{
+ unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
+ unsigned int result = offset & ~31UL;
+ unsigned int tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if (offset) {
+ tmp = *p++;
+ tmp |= ~0UL >> (32-offset);
+ if (size < 32)
+ goto found_first;
+ if (tmp != ~0U)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while (size >= 32) {
+ if ((tmp = *p++) != ~0U)
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+found_first:
+ tmp |= ~0UL << size;
+found_middle:
+ return result + ffz(tmp);
+}
+
+
+#define _EXT2_HAVE_ASM_BITOPS_
+
+#ifdef __KERNEL__
+/*
+ * test_and_{set,clear}_bit guarantee atomicity without
+ * disabling interrupts.
+ */
+#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 0x18, addr)
+#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr)
+
+#else
+static __inline__ int ext2_set_bit(int nr, void * addr)
+{
+ int mask;
+ unsigned char *ADDR = (unsigned char *) addr;
+ int oldbit;
+
+ ADDR += nr >> 3;
+ mask = 1 << (nr & 0x07);
+ oldbit = (*ADDR & mask) ? 1 : 0;
+ *ADDR |= mask;
+ return oldbit;
+}
+
+static __inline__ int ext2_clear_bit(int nr, void * addr)
+{
+ int mask;
+ unsigned char *ADDR = (unsigned char *) addr;
+ int oldbit;
+
+ ADDR += nr >> 3;
+ mask = 1 << (nr & 0x07);
+ oldbit = (*ADDR & mask) ? 1 : 0;
+ *ADDR = *ADDR & ~mask;
+ return oldbit;
+}
+#endif /* __KERNEL__ */
+
+static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
+{
+ __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
+
+ return (ADDR[nr >> 3] >> (nr & 7)) & 1;
+}
+
+/*
+ * This implementation of ext2_find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h and modified for a big-endian machine.
+ */
+
+#define ext2_find_first_zero_bit(addr, size) \
+ ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+ unsigned long size, unsigned long offset)
+{
+ unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+ unsigned int result = offset & ~31UL;
+ unsigned int tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if (offset) {
+ tmp = cpu_to_le32p(p++);
+ tmp |= ~0UL >> (32-offset);
+ if (size < 32)
+ goto found_first;
+ if (tmp != ~0U)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while (size >= 32) {
+ if ((tmp = cpu_to_le32p(p++)) != ~0U)
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if (!size)
+ return result;
+ tmp = cpu_to_le32p(p);
+found_first:
+ tmp |= ~0U << size;
+found_middle:
+ return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
+#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size)
+
+#endif /* _PPC_BITOPS_H */
diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h
new file mode 100644
index 0000000..f731d18
--- /dev/null
+++ b/arch/powerpc/include/asm/byteorder.h
@@ -0,0 +1,84 @@
+#ifndef _PPC_BYTEORDER_H
+#define _PPC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+ unsigned val;
+
+ __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+ return val;
+}
+
+static __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
+{
+ __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+static __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+ unsigned val;
+
+ __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+ return val;
+}
+
+static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+ __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+ inline asm correctly, and can cause file corruption. Until I hear that
+ it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+# define __arch_swab16(x) ld_le16(&x)
+# define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value)
+{
+ __u16 result;
+
+ __asm__("rlwimi %0,%1,8,16,23"
+ : "=r" (result)
+ : "r" (value), "0" (value >> 8));
+ return result;
+}
+
+static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value)
+{
+ __u32 result;
+
+ __asm__("rlwimi %0,%1,24,16,23\n\t"
+ "rlwimi %0,%1,8,8,15\n\t"
+ "rlwimi %0,%1,24,0,7"
+ : "=r" (result)
+ : "r" (value), "0" (value >> 24));
+ return result;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif /* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+
+#endif /* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _PPC_BYTEORDER_H */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
new file mode 100644
index 0000000..445a366
--- /dev/null
+++ b/arch/powerpc/include/asm/cache.h
@@ -0,0 +1,144 @@
+/*
+ * include/asm-ppc/cache.h
+ */
+#ifndef __ARCH_PPC_CACHE_H
+#define __ARCH_PPC_CACHE_H
+
+#include <asm/processor.h>
+
+/* bytes per L1 cache line */
+#if defined(CONFIG_MPC8xx)
+#define L1_CACHE_SHIFT 4
+#elif defined(CONFIG_PPC64BRIDGE)
+#define L1_CACHE_SHIFT 7
+#elif defined(CONFIG_E500MC)
+#define L1_CACHE_SHIFT 6
+#else
+#define L1_CACHE_SHIFT 5
+#endif
+
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+/*
+ * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
+ */
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
+#endif
+
+#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
+#define L1_CACHE_PAGES 8
+
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
+
+#ifdef MODULE
+#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
+#else
+#define __cacheline_aligned \
+ __attribute__((__aligned__(L1_CACHE_BYTES), \
+ __section__(".data.cacheline_aligned")))
+#endif
+
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+extern void flush_dcache_range(unsigned long start, unsigned long stop);
+extern void clean_dcache_range(unsigned long start, unsigned long stop);
+extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache(void);
+extern void invalidate_dcache(void);
+extern void invalidate_icache(void);
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
+extern void unlock_ram_in_cache(void);
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
+#endif /* __ASSEMBLY__ */
+
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+int l2cache_init(void);
+void enable_cpc(void);
+void disable_cpc_sram(void);
+#endif
+
+/* prep registers for L2 */
+#define CACHECRBA 0x80000823 /* Cache configuration register address */
+#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
+#define L2CACHE_512KB 0x00 /* 512KB */
+#define L2CACHE_256KB 0x01 /* 256KB */
+#define L2CACHE_1MB 0x02 /* 1MB */
+#define L2CACHE_NONE 0x03 /* NONE */
+#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
+
+#ifdef CONFIG_MPC8xx
+/* Cache control on the MPC8xx is provided through some additional
+ * special purpose registers.
+ */
+#define IC_CST 560 /* Instruction cache control/status */
+#define IC_ADR 561 /* Address needed for some commands */
+#define IC_DAT 562 /* Read-only data register */
+#define DC_CST 568 /* Data cache control/status */
+#define DC_ADR 569 /* Address needed for some commands */
+#define DC_DAT 570 /* Read-only data register */
+
+/* Commands. Only the first few are available to the instruction cache.
+*/
+#define IDC_ENABLE 0x02000000 /* Cache enable */
+#define IDC_DISABLE 0x04000000 /* Cache disable */
+#define IDC_LDLCK 0x06000000 /* Load and lock */
+#define IDC_UNLINE 0x08000000 /* Unlock line */
+#define IDC_UNALL 0x0a000000 /* Unlock all */
+#define IDC_INVALL 0x0c000000 /* Invalidate all */
+
+#define DC_FLINE 0x0e000000 /* Flush data cache line */
+#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
+#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
+#define DC_SLES 0x05000000 /* Set little endian swap mode */
+#define DC_CLES 0x07000000 /* Clear little endian swap mode */
+
+/* Status.
+*/
+#define IDC_ENABLED 0x80000000 /* Cache is enabled */
+#define IDC_CERR1 0x00200000 /* Cache error 1 */
+#define IDC_CERR2 0x00100000 /* Cache error 2 */
+#define IDC_CERR3 0x00080000 /* Cache error 3 */
+
+#define DC_DFWT 0x40000000 /* Data cache is forced write through */
+#define DC_LES 0x20000000 /* Caches are little endian mode */
+
+#if !defined(__ASSEMBLY__)
+static inline uint rd_ic_cst(void)
+{
+ return mfspr(IC_CST);
+}
+
+static inline void wr_ic_cst(uint val)
+{
+ mtspr(IC_CST, val);
+}
+
+static inline void wr_ic_adr(uint val)
+{
+ mtspr(IC_ADR, val);
+}
+
+static inline uint rd_dc_cst(void)
+{
+ return mfspr(DC_CST);
+}
+
+static inline void wr_dc_cst(uint val)
+{
+ mtspr(DC_CST, val);
+}
+
+static inline void wr_dc_adr(uint val)
+{
+ mtspr(DC_ADR, val);
+}
+#endif
+#endif /* CONFIG_MPC8xx */
+
+#endif
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
new file mode 100644
index 0000000..c9c9964
--- /dev/null
+++ b/arch/powerpc/include/asm/config.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#ifdef CONFIG_MPC85xx
+#include <asm/config_mpc85xx.h>
+#endif
+
+#ifdef CONFIG_MPC86xx
+#include <asm/config_mpc86xx.h>
+#endif
+
+#ifndef HWCONFIG_BUFFER_SIZE
+ #define HWCONFIG_BUFFER_SIZE 256
+#endif
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#ifndef CONFIG_MAX_MEM_MAPPED
+#if defined(CONFIG_E500) || \
+ defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_E300)
+#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
+#else
+#define CONFIG_MAX_MEM_MAPPED (256 << 20)
+#endif
+#endif
+
+/* Check if boards need to enable FSL DMA engine for SDRAM init */
+#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
+#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
+ ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
+ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
+#define CONFIG_FSL_DMA
+#endif
+#endif
+
+/*
+ * Provide a default boot page translation virtual address that lines up with
+ * Freescale's default e500 reset page.
+ */
+#if (defined(CONFIG_E500) && defined(CONFIG_MP))
+#ifndef CONFIG_BPTR_VIRT_ADDR
+#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
+#endif
+#endif
+
+/* Since so many PPC SOCs have a semi-common LBC, define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_MPC83xx)
+#if !defined(CONFIG_FSL_IFC)
+#define CONFIG_FSL_LBC
+#endif
+#endif
+
+/* The TSEC driver uses the PHYLIB infrastructure */
+#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
+#include <config_phylib_all_drivers.h>
+#endif /* TSEC_ENET */
+
+/* The FMAN driver uses the PHYLIB infrastructure */
+
+/* All PPC boards must swap IDE bytes */
+#define CONFIG_IDE_SWAP_IO
+
+#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
+/*
+ * TODO: Convert this to a clock driver exists that can give us the UART
+ * clock here.
+ */
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#endif
+
+#endif /* _ASM_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
new file mode 100644
index 0000000..946e74a
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_MPC85xx_CONFIG_H_
+#define _ASM_MPC85xx_CONFIG_H_
+
+/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
+
+/*
+ * This macro should be removed when we no longer care about backwards
+ * compatibility with older operating systems.
+ */
+#define CONFIG_PPC_SPINTABLE_COMPATIBLE
+
+#include <fsl_ddrc_version.h>
+
+/* IP endianness */
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+
+#if defined(CONFIG_ARCH_MPC8548)
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+
+#elif defined(CONFIG_ARCH_MPC8568)
+#define QE_MURAM_SIZE 0x10000UL
+#define MAX_QE_RISC 2
+#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+
+#elif defined(CONFIG_ARCH_MPC8569)
+#define QE_MURAM_SIZE 0x20000UL
+#define MAX_QE_RISC 4
+#define QE_NUM_OF_SNUM 46
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+
+#elif defined(CONFIG_ARCH_P1010)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_ESDHC_HC_BLK_ADDR
+
+/* P1011 is single core version of P1020 */
+#elif defined(CONFIG_ARCH_P1011)
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#elif defined(CONFIG_ARCH_P1020)
+#define CONFIG_TSECV2
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#elif defined(CONFIG_ARCH_P1021)
+#define CONFIG_TSECV2
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#elif defined(CONFIG_ARCH_P1022)
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#elif defined(CONFIG_ARCH_P1023)
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_QMAN_NUM_PORTALS 3
+#define CONFIG_SYS_BMAN_NUM_PORTALS 3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+
+/* P1024 is lower end variant of P1020 */
+#elif defined(CONFIG_ARCH_P1024)
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* P1025 is lower end variant of P1021 */
+#elif defined(CONFIG_ARCH_P1025)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_TSECV2
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+
+#elif defined(CONFIG_ARCH_P2020)
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+
+#elif defined(CONFIG_ARCH_P3041)
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+
+#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM2_DTSEC 4
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_NUM_FM2_10GEC 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+
+#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 32
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
+
+#elif defined(CONFIG_ARCH_P5040)
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_NUM_FM2_DTSEC 5
+#define CONFIG_SYS_NUM_FM2_10GEC 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+
+#elif defined(CONFIG_ARCH_BSC9131)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_ESDHC_HC_BLK_ADDR
+
+#elif defined(CONFIG_ARCH_BSC9132)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
+#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+#define CONFIG_ESDHC_HC_BLK_ADDR
+
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#ifdef CONFIG_ARCH_T4240
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_SYS_NUM_FM2_DTSEC 8
+#define CONFIG_SYS_NUM_FM2_10GEC 2
+#else
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_NUM_FM2_DTSEC 8
+#define CONFIG_SYS_NUM_FM2_10GEC 1
+#if defined(CONFIG_ARCH_T4160)
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#endif
+#endif
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_PME_CLK 0
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM1_CLK 3
+#define CONFIG_SYS_FM2_CLK 3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
+#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
+#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_MAPLE
+#define CONFIG_SYS_CPRI
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_CPRI_CLK 3
+#define CONFIG_SYS_ULB_CLK 4
+#define CONFIG_SYS_ETVPE_CLK 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+#ifdef CONFIG_ARCH_B4860
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_MAX_DSP_CPUS 12
+#define CONFIG_NUM_DSP_CPUS 6
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#else
+#define CONFIG_MAX_DSP_CPUS 2
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM1_10GEC 0
+#endif
+
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_PME_PLAT_CLK_DIV 2
+#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_FM_PLAT_CLK_DIV 1
+#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
+ per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
+#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_NUM_CC_PLL 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
+ per rcw field value */
+#define CONFIG_QBMAN_CLK_DIV 1
+#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#define CONFIG_SYS_FSL_QMAN_V3
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 4
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#endif
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_PME_PLAT_CLK_DIV 1
+#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
+ per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ISBC_VER 2
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+
+#elif defined(CONFIG_ARCH_C29X)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2_1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
+
+#endif
+
+#if !defined(CONFIG_ARCH_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#endif
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
new file mode 100644
index 0000000..f19ff7a
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_MPC86xx_CONFIG_H_
+#define _ASM_MPC86xx_CONFIG_H_
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
new file mode 100644
index 0000000..b46e20e
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -0,0 +1,829 @@
+/*
+ * MPC85xx Communication Processor Module
+ * Copyright (c) 2003,Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * MPC8260 Communication Processor Module.
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels found in the dual port RAM or parameter RAM.
+ * All CPM control and status is available through the MPC8260 internal
+ * memory map. See immap.h for details.
+ */
+#ifndef __CPM_85XX__
+#define __CPM_85XX__
+
+#include <asm/immap_85xx.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST ((uint)0x80000000)
+#define CPM_CR_PAGE ((uint)0x7c000000)
+#define CPM_CR_SBLOCK ((uint)0x03e00000)
+#define CPM_CR_FLG ((uint)0x00010000)
+#define CPM_CR_MCN ((uint)0x00003fc0)
+#define CPM_CR_OPCODE ((uint)0x0000000f)
+
+/* Device sub-block and page codes.
+*/
+#define CPM_CR_SCC1_SBLOCK (0x04)
+#define CPM_CR_SCC2_SBLOCK (0x05)
+#define CPM_CR_SCC3_SBLOCK (0x06)
+#define CPM_CR_SCC4_SBLOCK (0x07)
+#define CPM_CR_SMC1_SBLOCK (0x08)
+#define CPM_CR_SMC2_SBLOCK (0x09)
+#define CPM_CR_SPI_SBLOCK (0x0a)
+#define CPM_CR_I2C_SBLOCK (0x0b)
+#define CPM_CR_TIMER_SBLOCK (0x0f)
+#define CPM_CR_RAND_SBLOCK (0x0e)
+#define CPM_CR_FCC1_SBLOCK (0x10)
+#define CPM_CR_FCC2_SBLOCK (0x11)
+#define CPM_CR_FCC3_SBLOCK (0x12)
+#define CPM_CR_MCC1_SBLOCK (0x1c)
+
+#define CPM_CR_SCC1_PAGE (0x00)
+#define CPM_CR_SCC2_PAGE (0x01)
+#define CPM_CR_SCC3_PAGE (0x02)
+#define CPM_CR_SCC4_PAGE (0x03)
+#define CPM_CR_SPI_PAGE (0x09)
+#define CPM_CR_I2C_PAGE (0x0a)
+#define CPM_CR_TIMER_PAGE (0x0a)
+#define CPM_CR_RAND_PAGE (0x0a)
+#define CPM_CR_FCC1_PAGE (0x04)
+#define CPM_CR_FCC2_PAGE (0x05)
+#define CPM_CR_FCC3_PAGE (0x06)
+#define CPM_CR_MCC1_PAGE (0x07)
+#define CPM_CR_MCC2_PAGE (0x08)
+
+/* Some opcodes (there are more...later)
+*/
+#define CPM_CR_INIT_TRX ((ushort)0x0000)
+#define CPM_CR_INIT_RX ((ushort)0x0001)
+#define CPM_CR_INIT_TX ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE ((ushort)0x0003)
+#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_RESTART_TX ((ushort)0x0006)
+#define CPM_CR_SET_GADDR ((ushort)0x0008)
+
+#define mk_cr_cmd(PG, SBC, MCN, OP) \
+ ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+
+/* Dual Port RAM addresses. The first 16K is available for almost
+ * any CPM use, so we put the BDs there. The first 128 bytes are
+ * used for SMC1 and SMC2 parameter RAM, so we start allocating
+ * BDs above that. All of this must change when we start
+ * downloading RAM microcode.
+ */
+#define CPM_DATAONLY_BASE ((uint)128)
+#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
+#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
+#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
+#else /* MPC8540, MPC8560 */
+#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
+#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
+#endif
+
+/* The number of pages of host memory we allocate for CPM. This is
+ * done early in kernel initialization to get physically contiguous
+ * pages.
+ */
+#define NUM_CPM_HOST_PAGES 2
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+/*extern cpm8560_t *cpmp; Pointer to comm processor */
+uint m8560_cpm_dpalloc(uint size, uint align);
+uint m8560_cpm_hostalloc(uint size, uint align);
+void m8560_cpm_setbrg(uint brg, uint rate);
+void m8560_cpm_fastbrg(uint brg, uint rate, int div16);
+void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
+#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
+#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
+#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001) /* ?? */
+
+/* Function code bits, usually generic to devices.
+*/
+#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
+#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
+#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
+#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
+#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
+
+/* Parameter RAM offsets from the base.
+*/
+#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
+#define PROFF_SCC1 ((uint)0x8000)
+#define PROFF_SCC2 ((uint)0x8100)
+#define PROFF_SCC3 ((uint)0x8200)
+#define PROFF_SCC4 ((uint)0x8300)
+#define PROFF_FCC1 ((uint)0x8400)
+#define PROFF_FCC2 ((uint)0x8500)
+#define PROFF_FCC3 ((uint)0x8600)
+#define PROFF_MCC1 ((uint)0x8700)
+#define PROFF_MCC2 ((uint)0x8800)
+#define PROFF_SPI_BASE ((uint)0x89fc)
+#define PROFF_TIMERS ((uint)0x8ae0)
+#define PROFF_REVNUM ((uint)0x8af0)
+#define PROFF_RAND ((uint)0x8af8)
+#define PROFF_I2C_BASE ((uint)0x8afc)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST ((uint)0x00020000)
+#define CPM_BRG_EN ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
+#define CPM_BRG_ATB ((uint)0x00002000)
+#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
+#define CPM_BRG_DIV16 ((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP ((uint)0x00040000)
+#define SCC_GSMRH_GDE ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
+#define SCC_GSMRH_REVD ((uint)0x00002000)
+#define SCC_GSMRH_TRX ((uint)0x00001000)
+#define SCC_GSMRH_TTX ((uint)0x00000800)
+#define SCC_GSMRH_CDP ((uint)0x00000400)
+#define SCC_GSMRH_CTSP ((uint)0x00000200)
+#define SCC_GSMRH_CDS ((uint)0x00000100)
+#define SCC_GSMRH_CTSS ((uint)0x00000080)
+#define SCC_GSMRH_TFL ((uint)0x00000040)
+#define SCC_GSMRH_RFW ((uint)0x00000020)
+#define SCC_GSMRH_TXSY ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
+#define SCC_GSMRH_RTSM ((uint)0x00000002)
+#define SCC_GSMRH_RSYN ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
+#define SCC_GSMRL_TCI ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
+#define SCC_GSMRL_RINV ((uint)0x02000000)
+#define SCC_GSMRL_TINV ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
+#define SCC_GSMRL_TEND ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
+#define SCC_GSMRL_ENR ((uint)0x00000020)
+#define SCC_GSMRL_ENT ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
+
+#define SCC_TODR_TOD ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE ((unsigned char)0x10)
+#define SCCM_BSY ((unsigned char)0x04)
+#define SCCM_TX ((unsigned char)0x02)
+#define SCCM_RX ((unsigned char)0x01)
+
+typedef struct scc_param {
+ ushort scc_rbase; /* Rx Buffer descriptor base address */
+ ushort scc_tbase; /* Tx Buffer descriptor base address */
+ u_char scc_rfcr; /* Rx function code */
+ u_char scc_tfcr; /* Tx function code */
+ ushort scc_mrblr; /* Max receive buffer length */
+ uint scc_rstate; /* Internal */
+ uint scc_idp; /* Internal */
+ ushort scc_rbptr; /* Internal */
+ ushort scc_ibc; /* Internal */
+ uint scc_rxtmp; /* Internal */
+ uint scc_tstate; /* Internal */
+ uint scc_tdp; /* Internal */
+ ushort scc_tbptr; /* Internal */
+ ushort scc_tbc; /* Internal */
+ uint scc_txtmp; /* Internal */
+ uint scc_rcrc; /* Internal */
+ uint scc_tcrc; /* Internal */
+} sccp_t;
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+ sccp_t sen_genscc;
+ uint sen_cpres; /* Preset CRC */
+ uint sen_cmask; /* Constant mask for CRC */
+ uint sen_crcec; /* CRC Error counter */
+ uint sen_alec; /* alignment error counter */
+ uint sen_disfc; /* discard frame counter */
+ ushort sen_pads; /* Tx short frame pad character */
+ ushort sen_retlim; /* Retry limit threshold */
+ ushort sen_retcnt; /* Retry limit counter */
+ ushort sen_maxflr; /* maximum frame length register */
+ ushort sen_minflr; /* minimum frame length register */
+ ushort sen_maxd1; /* maximum DMA1 length */
+ ushort sen_maxd2; /* maximum DMA2 length */
+ ushort sen_maxd; /* Rx max DMA */
+ ushort sen_dmacnt; /* Rx DMA counter */
+ ushort sen_maxb; /* Max BD byte count */
+ ushort sen_gaddr1; /* Group address filter */
+ ushort sen_gaddr2;
+ ushort sen_gaddr3;
+ ushort sen_gaddr4;
+ uint sen_tbuf0data0; /* Save area 0 - current frame */
+ uint sen_tbuf0data1; /* Save area 1 - current frame */
+ uint sen_tbuf0rba; /* Internal */
+ uint sen_tbuf0crc; /* Internal */
+ ushort sen_tbuf0bcnt; /* Internal */
+ ushort sen_paddrh; /* physical address (MSB) */
+ ushort sen_paddrm;
+ ushort sen_paddrl; /* physical address (LSB) */
+ ushort sen_pper; /* persistence */
+ ushort sen_rfbdptr; /* Rx first BD pointer */
+ ushort sen_tfbdptr; /* Tx first BD pointer */
+ ushort sen_tlbdptr; /* Tx last BD pointer */
+ uint sen_tbuf1data0; /* Save area 0 - current frame */
+ uint sen_tbuf1data1; /* Save area 1 - current frame */
+ uint sen_tbuf1rba; /* Internal */
+ uint sen_tbuf1crc; /* Internal */
+ ushort sen_tbuf1bcnt; /* Internal */
+ ushort sen_txlen; /* Tx Frame length counter */
+ ushort sen_iaddr1; /* Individual address filter */
+ ushort sen_iaddr2;
+ ushort sen_iaddr3;
+ ushort sen_iaddr4;
+ ushort sen_boffcnt; /* Backoff counter */
+
+ /* NOTE: Some versions of the manual have the following items
+ * incorrectly documented. Below is the proper order.
+ */
+ ushort sen_taddrh; /* temp address (MSB) */
+ ushort sen_taddrm;
+ ushort sen_taddrl; /* temp address (LSB) */
+} scc_enet_t;
+
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
+#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
+#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
+#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
+#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
+#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
+#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
+#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
+#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
+#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
+#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
+#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
+#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
+#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
+#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
+#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
+#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
+#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
+#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+ sccp_t scc_genscc;
+ uint scc_res1; /* Reserved */
+ uint scc_res2; /* Reserved */
+ ushort scc_maxidl; /* Maximum idle chars */
+ ushort scc_idlc; /* temp idle counter */
+ ushort scc_brkcr; /* Break count register */
+ ushort scc_parec; /* receive parity error counter */
+ ushort scc_frmec; /* receive framing error counter */
+ ushort scc_nosec; /* receive noise counter */
+ ushort scc_brkec; /* receive break condition counter */
+ ushort scc_brkln; /* last received break length */
+ ushort scc_uaddr1; /* UART address character 1 */
+ ushort scc_uaddr2; /* UART address character 2 */
+ ushort scc_rtemp; /* Temp storage */
+ ushort scc_toseq; /* Transmit out of sequence char */
+ ushort scc_char1; /* control character 1 */
+ ushort scc_char2; /* control character 2 */
+ ushort scc_char3; /* control character 3 */
+ ushort scc_char4; /* control character 4 */
+ ushort scc_char5; /* control character 5 */
+ ushort scc_char6; /* control character 6 */
+ ushort scc_char7; /* control character 7 */
+ ushort scc_char8; /* control character 8 */
+ ushort scc_rccm; /* receive control character mask */
+ ushort scc_rccr; /* receive control character register */
+ ushort scc_rlbc; /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR ((ushort)0x1000)
+#define UART_SCCM_GLT ((ushort)0x0800)
+#define UART_SCCM_AB ((ushort)0x0200)
+#define UART_SCCM_IDL ((ushort)0x0100)
+#define UART_SCCM_GRA ((ushort)0x0080)
+#define UART_SCCM_BRKE ((ushort)0x0040)
+#define UART_SCCM_BRKS ((ushort)0x0020)
+#define UART_SCCM_CCR ((ushort)0x0008)
+#define UART_SCCM_BSY ((ushort)0x0004)
+#define UART_SCCM_TX ((ushort)0x0002)
+#define UART_SCCM_RX ((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC ((ushort)0x8000)
+#define SCU_PSMR_SL ((ushort)0x4000)
+#define SCU_PSMR_CL ((ushort)0x3000)
+#define SCU_PSMR_UM ((ushort)0x0c00)
+#define SCU_PSMR_FRZ ((ushort)0x0200)
+#define SCU_PSMR_RZS ((ushort)0x0100)
+#define SCU_PSMR_SYN ((ushort)0x0080)
+#define SCU_PSMR_DRT ((ushort)0x0040)
+#define SCU_PSMR_PEN ((ushort)0x0010)
+#define SCU_PSMR_RPM ((ushort)0x000c)
+#define SCU_PSMR_REVP ((ushort)0x0008)
+#define SCU_PSMR_TPM ((ushort)0x0003)
+#define SCU_PSMR_TEVP ((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+ sccp_t st_genscc;
+ uint st_cpres; /* Preset CRC */
+ uint st_cmask; /* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST ((ushort)0x0800)
+
+/* How about some FCCs.....
+*/
+#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
+#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
+#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
+#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
+#define FCC_GFMR_TCI ((uint)0x20000000)
+#define FCC_GFMR_TRX ((uint)0x10000000)
+#define FCC_GFMR_TTX ((uint)0x08000000)
+#define FCC_GFMR_TTX ((uint)0x08000000)
+#define FCC_GFMR_CDP ((uint)0x04000000)
+#define FCC_GFMR_CTSP ((uint)0x02000000)
+#define FCC_GFMR_CDS ((uint)0x01000000)
+#define FCC_GFMR_CTSS ((uint)0x00800000)
+#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
+#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
+#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
+#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
+#define FCC_GFMR_RTSM ((uint)0x00002000)
+#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
+#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
+#define FCC_GFMR_REVD ((uint)0x00000400)
+#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
+#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
+#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
+#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
+#define FCC_GFMR_ENR ((uint)0x00000020)
+#define FCC_GFMR_ENT ((uint)0x00000010)
+#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
+#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
+#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
+
+/* Generic FCC parameter ram.
+*/
+typedef struct fcc_param {
+ ushort fcc_riptr; /* Rx Internal temp pointer */
+ ushort fcc_tiptr; /* Tx Internal temp pointer */
+ ushort fcc_res1;
+ ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
+ uint fcc_rstate; /* Upper byte is Func code, must be set */
+ uint fcc_rbase; /* Receive BD base */
+ ushort fcc_rbdstat; /* RxBD status */
+ ushort fcc_rbdlen; /* RxBD down counter */
+ uint fcc_rdptr; /* RxBD internal data pointer */
+ uint fcc_tstate; /* Upper byte is Func code, must be set */
+ uint fcc_tbase; /* Transmit BD base */
+ ushort fcc_tbdstat; /* TxBD status */
+ ushort fcc_tbdlen; /* TxBD down counter */
+ uint fcc_tdptr; /* TxBD internal data pointer */
+ uint fcc_rbptr; /* Rx BD Internal buf pointer */
+ uint fcc_tbptr; /* Tx BD Internal buf pointer */
+ uint fcc_rcrc; /* Rx temp CRC */
+ uint fcc_res2;
+ uint fcc_tcrc; /* Tx temp CRC */
+} fccp_t;
+
+
+/* Ethernet controller through FCC.
+*/
+typedef struct fcc_enet {
+ fccp_t fen_genfcc;
+ uint fen_statbuf; /* Internal status buffer */
+ uint fen_camptr; /* CAM address */
+ uint fen_cmask; /* Constant mask for CRC */
+ uint fen_cpres; /* Preset CRC */
+ uint fen_crcec; /* CRC Error counter */
+ uint fen_alec; /* alignment error counter */
+ uint fen_disfc; /* discard frame counter */
+ ushort fen_retlim; /* Retry limit */
+ ushort fen_retcnt; /* Retry counter */
+ ushort fen_pper; /* Persistence */
+ ushort fen_boffcnt; /* backoff counter */
+ uint fen_gaddrh; /* Group address filter, high 32-bits */
+ uint fen_gaddrl; /* Group address filter, low 32-bits */
+ ushort fen_tfcstat; /* out of sequence TxBD */
+ ushort fen_tfclen;
+ uint fen_tfcptr;
+ ushort fen_mflr; /* Maximum frame length (1518) */
+ ushort fen_paddrh; /* MAC address */
+ ushort fen_paddrm;
+ ushort fen_paddrl;
+ ushort fen_ibdcount; /* Internal BD counter */
+ ushort fen_ibdstart; /* Internal BD start pointer */
+ ushort fen_ibdend; /* Internal BD end pointer */
+ ushort fen_txlen; /* Internal Tx frame length counter */
+ uint fen_ibdbase[8]; /* Internal use */
+ uint fen_iaddrh; /* Individual address filter */
+ uint fen_iaddrl;
+ ushort fen_minflr; /* Minimum frame length (64) */
+ ushort fen_taddrh; /* Filter transfer MAC address */
+ ushort fen_taddrm;
+ ushort fen_taddrl;
+ ushort fen_padptr; /* Pointer to pad byte buffer */
+ ushort fen_cftype; /* control frame type */
+ ushort fen_cfrange; /* control frame range */
+ ushort fen_maxb; /* maximum BD count */
+ ushort fen_maxd1; /* Max DMA1 length (1520) */
+ ushort fen_maxd2; /* Max DMA2 length (1520) */
+ ushort fen_maxd; /* internal max DMA count */
+ ushort fen_dmacnt; /* internal DMA counter */
+ uint fen_octc; /* Total octect counter */
+ uint fen_colc; /* Total collision counter */
+ uint fen_broc; /* Total broadcast packet counter */
+ uint fen_mulc; /* Total multicast packet count */
+ uint fen_uspc; /* Total packets < 64 bytes */
+ uint fen_frgc; /* Total packets < 64 bytes with errors */
+ uint fen_ospc; /* Total packets > 1518 */
+ uint fen_jbrc; /* Total packets > 1518 with errors */
+ uint fen_p64c; /* Total packets == 64 bytes */
+ uint fen_p65c; /* Total packets 64 < bytes <= 127 */
+ uint fen_p128c; /* Total packets 127 < bytes <= 255 */
+ uint fen_p256c; /* Total packets 256 < bytes <= 511 */
+ uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
+ uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
+ uint fen_cambuf; /* Internal CAM buffer poiner */
+ ushort fen_rfthr; /* Received frames threshold */
+ ushort fen_rfcnt; /* Received frames count */
+} fcc_enet_t;
+
+/* FCC Event/Mask register as used by Ethernet.
+*/
+#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
+#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
+#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
+#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
+#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
+#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
+#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
+#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
+
+/* FCC Mode Register (FPSMR) as used by Ethernet.
+*/
+#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
+#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
+#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
+#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
+#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
+#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
+#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
+#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
+#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
+#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
+#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
+#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
+#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+ ushort iic_rbase; /* Rx Buffer descriptor base address */
+ ushort iic_tbase; /* Tx Buffer descriptor base address */
+ u_char iic_rfcr; /* Rx function code */
+ u_char iic_tfcr; /* Tx function code */
+ ushort iic_mrblr; /* Max receive buffer length */
+ uint iic_rstate; /* Internal */
+ uint iic_rdp; /* Internal */
+ ushort iic_rbptr; /* Internal */
+ ushort iic_rbc; /* Internal */
+ uint iic_rxtmp; /* Internal */
+ uint iic_tstate; /* Internal */
+ uint iic_tdp; /* Internal */
+ ushort iic_tbptr; /* Internal */
+ ushort iic_tbc; /* Internal */
+ uint iic_txtmp; /* Internal */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+ ushort spi_rbase; /* Rx Buffer descriptor base address */
+ ushort spi_tbase; /* Tx Buffer descriptor base address */
+ u_char spi_rfcr; /* Rx function code */
+ u_char spi_tfcr; /* Tx function code */
+ ushort spi_mrblr; /* Max receive buffer length */
+ uint spi_rstate; /* Internal */
+ uint spi_rdp; /* Internal */
+ ushort spi_rbptr; /* Internal */
+ ushort spi_rbc; /* Internal */
+ uint spi_rxtmp; /* Internal */
+ uint spi_tstate; /* Internal */
+ uint spi_tdp; /* Internal */
+ ushort spi_tbptr; /* Internal */
+ ushort spi_tbc; /* Internal */
+ uint spi_txtmp; /* Internal */
+ uint spi_res; /* Tx temp. */
+ uint spi_res1[4]; /* SDMA temp. */
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
+#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
+#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
+#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
+#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
+#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
+#define SPMODE_EN ((ushort)0x0100) /* Enable */
+#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
+#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
+
+#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x) ((x) &0xF)
+
+#define SPI_EB ((u_char)0x10) /* big endian byte order */
+
+#define BD_IIC_START ((ushort)0x0400)
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register 15-12
+ */
+#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
+#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
+#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
+#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register 15-14
+ */
+#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
+#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
+#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
+#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
+#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
+#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
+#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
+#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
+#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
+
+#endif /* __CPM_85XX__ */
diff --git a/arch/powerpc/include/asm/cpm_8xx.h b/arch/powerpc/include/asm/cpm_8xx.h
new file mode 100644
index 0000000..85903d2
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm_8xx.h
@@ -0,0 +1,687 @@
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file contains structures and information for the communication
+ * processor channels. Some CPM control and status is available
+ * through the MPC8xx internal memory map. See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities. I (or someone else) will add definitions as they
+ * are needed. -- Dan
+ *
+ */
+#ifndef __CPM_8XX__
+#define __CPM_8XX__
+
+#include <asm/immap_8xx.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST ((ushort)0x8000)
+#define CPM_CR_OPCODE ((ushort)0x0f00)
+#define CPM_CR_CHAN ((ushort)0x00f0)
+#define CPM_CR_FLG ((ushort)0x0001)
+
+/* Some commands (there are more...later)
+*/
+#define CPM_CR_INIT_TRX ((ushort)0x0000)
+#define CPM_CR_INIT_RX ((ushort)0x0001)
+#define CPM_CR_INIT_TX ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE ((ushort)0x0003)
+#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_RESTART_TX ((ushort)0x0006)
+#define CPM_CR_SET_GADDR ((ushort)0x0008)
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1 ((ushort)0x0000)
+#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2 ((ushort)0x0004)
+#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
+#define CPM_CR_CH_SCC3 ((ushort)0x0008)
+#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4 ((ushort)0x000c)
+#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
+
+/*
+ * DPRAM defines and allocation functions
+ */
+#define CPM_SERIAL_BASE 0x1800
+#define CPM_I2C_BASE 0x1820
+#define CPM_SPI_BASE 0x1840
+#define CPM_FEC_BASE 0x1860
+#define CPM_SERIAL2_BASE 0x18e0
+#define CPM_SCC_BASE 0x1900
+#define CPM_POST_BASE 0x1980
+#define CPM_WLKBD_BASE 0x1a00
+
+#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern cpm8xx_t *cpmp; /* Pointer to comm processor */
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
+#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
+#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
+#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
+#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
+#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1 ((uint)0x0000)
+#define PROFF_IIC ((uint)0x0080)
+#define PROFF_REVNUM ((uint)0x00b0)
+#define PROFF_SCC2 ((uint)0x0100)
+#define PROFF_SPI ((uint)0x0180)
+#define PROFF_SCC3 ((uint)0x0200)
+#define PROFF_SMC1 ((uint)0x0280)
+#define PROFF_SCC4 ((uint)0x0300)
+#define PROFF_SMC2 ((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+ ushort smc_rbase; /* Rx Buffer descriptor base address */
+ ushort smc_tbase; /* Tx Buffer descriptor base address */
+ u_char smc_rfcr; /* Rx function code */
+ u_char smc_tfcr; /* Tx function code */
+ ushort smc_mrblr; /* Max receive buffer length */
+ uint smc_rstate; /* Internal */
+ uint smc_idp; /* Internal */
+ ushort smc_rbptr; /* Internal */
+ ushort smc_ibc; /* Internal */
+ uint smc_rxtmp; /* Internal */
+ uint smc_tstate; /* Internal */
+ uint smc_tdp; /* Internal */
+ ushort smc_tbptr; /* Internal */
+ ushort smc_tbc; /* Internal */
+ uint smc_txtmp; /* Internal */
+ ushort smc_maxidl; /* Maximum idle characters */
+ ushort smc_tmpidl; /* Temporary idle counter */
+ ushort smc_brklen; /* Last received break length */
+ ushort smc_brkec; /* rcv'd break condition counter */
+ ushort smc_brkcr; /* xmt break count register */
+ ushort smc_rmask; /* Temporary bit mask */
+ u_char res1[8];
+ ushort smc_rpbase; /* Relocation pointer */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define SMCMR_REN ((ushort)0x0001)
+#define SMCMR_TEN ((ushort)0x0002)
+#define SMCMR_DM ((ushort)0x000c)
+#define SMCMR_SM_GCI ((ushort)0x0000)
+#define SMCMR_SM_UART ((ushort)0x0020)
+#define SMCMR_SM_TRANS ((ushort)0x0030)
+#define SMCMR_SM_MASK ((ushort)0x0030)
+#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
+#define SMCMR_REVD SMCMR_PM_EVEN
+#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
+#define SMCMR_BS SMCMR_PEN
+#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
+#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
+#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer. It is half duplex, in that
+ * it can only receive or transmit. The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+ ushort scent_rbase;
+ ushort scent_tbase;
+ u_char scent_cfcr;
+ u_char scent_smask;
+ ushort scent_mrblr;
+ uint scent_rstate;
+ uint scent_r_ptr;
+ ushort scent_rbptr;
+ ushort scent_r_cnt;
+ uint scent_rtemp;
+ uint scent_tstate;
+ uint scent_t_ptr;
+ ushort scent_tbptr;
+ ushort scent_t_cnt;
+ uint scent_ttemp;
+ ushort scent_max_sl;
+ ushort scent_sl_cnt;
+ ushort scent_character1;
+ ushort scent_character2;
+ ushort scent_character3;
+ ushort scent_character4;
+ ushort scent_character5;
+ ushort scent_character6;
+ ushort scent_character7;
+ ushort scent_character8;
+ ushort scent_rccm;
+ ushort scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F ((u_char)0x08)
+#define SMC_CENT_PE ((u_char)0x04)
+#define SMC_CENT_S ((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
+#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
+#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
+#define SMCM_BSY ((unsigned char)0x04)
+#define SMCM_TX ((unsigned char)0x02)
+#define SMCM_RX ((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST ((uint)0x00020000)
+#define CPM_BRG_EN ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
+#define CPM_BRG_ATB ((uint)0x00002000)
+#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
+#define CPM_BRG_DIV16 ((uint)0x00000001)
+
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP ((uint)0x00040000)
+#define SCC_GSMRH_GDE ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
+#define SCC_GSMRH_REVD ((uint)0x00002000)
+#define SCC_GSMRH_TRX ((uint)0x00001000)
+#define SCC_GSMRH_TTX ((uint)0x00000800)
+#define SCC_GSMRH_CDP ((uint)0x00000400)
+#define SCC_GSMRH_CTSP ((uint)0x00000200)
+#define SCC_GSMRH_CDS ((uint)0x00000100)
+#define SCC_GSMRH_CTSS ((uint)0x00000080)
+#define SCC_GSMRH_TFL ((uint)0x00000040)
+#define SCC_GSMRH_RFW ((uint)0x00000020)
+#define SCC_GSMRH_TXSY ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
+#define SCC_GSMRH_RTSM ((uint)0x00000002)
+#define SCC_GSMRH_RSYN ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
+#define SCC_GSMRL_TCI ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
+#define SCC_GSMRL_RINV ((uint)0x02000000)
+#define SCC_GSMRL_TINV ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
+#define SCC_GSMRL_TEND ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
+#define SCC_GSMRL_ENR ((uint)0x00000020)
+#define SCC_GSMRL_ENT ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
+
+#define SCC_TODR_TOD ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE ((unsigned char)0x10)
+#define SCCM_BSY ((unsigned char)0x04)
+#define SCCM_TX ((unsigned char)0x02)
+#define SCCM_RX ((unsigned char)0x01)
+
+typedef struct scc_param {
+ ushort scc_rbase; /* Rx Buffer descriptor base address */
+ ushort scc_tbase; /* Tx Buffer descriptor base address */
+ u_char scc_rfcr; /* Rx function code */
+ u_char scc_tfcr; /* Tx function code */
+ ushort scc_mrblr; /* Max receive buffer length */
+ uint scc_rstate; /* Internal */
+ uint scc_idp; /* Internal */
+ ushort scc_rbptr; /* Internal */
+ ushort scc_ibc; /* Internal */
+ uint scc_rxtmp; /* Internal */
+ uint scc_tstate; /* Internal */
+ uint scc_tdp; /* Internal */
+ ushort scc_tbptr; /* Internal */
+ ushort scc_tbc; /* Internal */
+ uint scc_txtmp; /* Internal */
+ uint scc_rcrc; /* Internal */
+ uint scc_tcrc; /* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
+
+/* CPM Ethernet through SCCx.
+ */
+typedef struct scc_enet {
+ sccp_t sen_genscc;
+ uint sen_cpres; /* Preset CRC */
+ uint sen_cmask; /* Constant mask for CRC */
+ uint sen_crcec; /* CRC Error counter */
+ uint sen_alec; /* alignment error counter */
+ uint sen_disfc; /* discard frame counter */
+ ushort sen_pads; /* Tx short frame pad character */
+ ushort sen_retlim; /* Retry limit threshold */
+ ushort sen_retcnt; /* Retry limit counter */
+ ushort sen_maxflr; /* maximum frame length register */
+ ushort sen_minflr; /* minimum frame length register */
+ ushort sen_maxd1; /* maximum DMA1 length */
+ ushort sen_maxd2; /* maximum DMA2 length */
+ ushort sen_maxd; /* Rx max DMA */
+ ushort sen_dmacnt; /* Rx DMA counter */
+ ushort sen_maxb; /* Max BD byte count */
+ ushort sen_gaddr1; /* Group address filter */
+ ushort sen_gaddr2;
+ ushort sen_gaddr3;
+ ushort sen_gaddr4;
+ uint sen_tbuf0data0; /* Save area 0 - current frame */
+ uint sen_tbuf0data1; /* Save area 1 - current frame */
+ uint sen_tbuf0rba; /* Internal */
+ uint sen_tbuf0crc; /* Internal */
+ ushort sen_tbuf0bcnt; /* Internal */
+ ushort sen_paddrh; /* physical address (MSB) */
+ ushort sen_paddrm;
+ ushort sen_paddrl; /* physical address (LSB) */
+ ushort sen_pper; /* persistence */
+ ushort sen_rfbdptr; /* Rx first BD pointer */
+ ushort sen_tfbdptr; /* Tx first BD pointer */
+ ushort sen_tlbdptr; /* Tx last BD pointer */
+ uint sen_tbuf1data0; /* Save area 0 - current frame */
+ uint sen_tbuf1data1; /* Save area 1 - current frame */
+ uint sen_tbuf1rba; /* Internal */
+ uint sen_tbuf1crc; /* Internal */
+ ushort sen_tbuf1bcnt; /* Internal */
+ ushort sen_txlen; /* Tx Frame length counter */
+ ushort sen_iaddr1; /* Individual address filter */
+ ushort sen_iaddr2;
+ ushort sen_iaddr3;
+ ushort sen_iaddr4;
+ ushort sen_boffcnt; /* Backoff counter */
+
+ /* NOTE: Some versions of the manual have the following items
+ * incorrectly documented. Below is the proper order.
+ */
+ ushort sen_taddrh; /* temp address (MSB) */
+ ushort sen_taddrm;
+ ushort sen_taddrl; /* temp address (LSB) */
+} scc_enet_t;
+
+/*********************************************************************/
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
+#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
+#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
+#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
+#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
+#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
+#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
+#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
+#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
+#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
+#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
+#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
+#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
+#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
+#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
+#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
+#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
+#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+ sccp_t scc_genscc;
+ uint scc_res1; /* Reserved */
+ uint scc_res2; /* Reserved */
+ ushort scc_maxidl; /* Maximum idle chars */
+ ushort scc_idlc; /* temp idle counter */
+ ushort scc_brkcr; /* Break count register */
+ ushort scc_parec; /* receive parity error counter */
+ ushort scc_frmec; /* receive framing error counter */
+ ushort scc_nosec; /* receive noise counter */
+ ushort scc_brkec; /* receive break condition counter */
+ ushort scc_brkln; /* last received break length */
+ ushort scc_uaddr1; /* UART address character 1 */
+ ushort scc_uaddr2; /* UART address character 2 */
+ ushort scc_rtemp; /* Temp storage */
+ ushort scc_toseq; /* Transmit out of sequence char */
+ ushort scc_char1; /* control character 1 */
+ ushort scc_char2; /* control character 2 */
+ ushort scc_char3; /* control character 3 */
+ ushort scc_char4; /* control character 4 */
+ ushort scc_char5; /* control character 5 */
+ ushort scc_char6; /* control character 6 */
+ ushort scc_char7; /* control character 7 */
+ ushort scc_char8; /* control character 8 */
+ ushort scc_rccm; /* receive control character mask */
+ ushort scc_rccr; /* receive control character register */
+ ushort scc_rlbc; /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR ((ushort)0x1000)
+#define UART_SCCM_GLT ((ushort)0x0800)
+#define UART_SCCM_AB ((ushort)0x0200)
+#define UART_SCCM_IDL ((ushort)0x0100)
+#define UART_SCCM_GRA ((ushort)0x0080)
+#define UART_SCCM_BRKE ((ushort)0x0040)
+#define UART_SCCM_BRKS ((ushort)0x0020)
+#define UART_SCCM_CCR ((ushort)0x0008)
+#define UART_SCCM_BSY ((ushort)0x0004)
+#define UART_SCCM_TX ((ushort)0x0002)
+#define UART_SCCM_RX ((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC ((ushort)0x8000)
+#define SCU_PSMR_SL ((ushort)0x4000)
+#define SCU_PSMR_CL ((ushort)0x3000)
+#define SCU_PSMR_UM ((ushort)0x0c00)
+#define SCU_PSMR_FRZ ((ushort)0x0200)
+#define SCU_PSMR_RZS ((ushort)0x0100)
+#define SCU_PSMR_SYN ((ushort)0x0080)
+#define SCU_PSMR_DRT ((ushort)0x0040)
+#define SCU_PSMR_PEN ((ushort)0x0010)
+#define SCU_PSMR_RPM ((ushort)0x000c)
+#define SCU_PSMR_REVP ((ushort)0x0008)
+#define SCU_PSMR_TPM ((ushort)0x0003)
+#define SCU_PSMR_TEVP ((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+ sccp_t st_genscc;
+ uint st_cpres; /* Preset CRC */
+ uint st_cmask; /* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST ((ushort)0x0800)
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+ ushort iic_rbase; /* Rx Buffer descriptor base address */
+ ushort iic_tbase; /* Tx Buffer descriptor base address */
+ u_char iic_rfcr; /* Rx function code */
+ u_char iic_tfcr; /* Tx function code */
+ ushort iic_mrblr; /* Max receive buffer length */
+ uint iic_rstate; /* Internal */
+ uint iic_rdp; /* Internal */
+ ushort iic_rbptr; /* Internal */
+ ushort iic_rbc; /* Internal */
+ uint iic_rxtmp; /* Internal */
+ uint iic_tstate; /* Internal */
+ uint iic_tdp; /* Internal */
+ ushort iic_tbptr; /* Internal */
+ ushort iic_tbc; /* Internal */
+ uint iic_txtmp; /* Internal */
+ uint iic_res; /* reserved */
+ ushort iic_rpbase; /* Relocation pointer */
+ ushort iic_res2; /* reserved */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+ ushort spi_rbase; /* Rx Buffer descriptor base address */
+ ushort spi_tbase; /* Tx Buffer descriptor base address */
+ u_char spi_rfcr; /* Rx function code */
+ u_char spi_tfcr; /* Tx function code */
+ ushort spi_mrblr; /* Max receive buffer length */
+ uint spi_rstate; /* Internal */
+ uint spi_rdp; /* Internal */
+ ushort spi_rbptr; /* Internal */
+ ushort spi_rbc; /* Internal */
+ uint spi_rxtmp; /* Internal */
+ uint spi_tstate; /* Internal */
+ uint spi_tdp; /* Internal */
+ ushort spi_tbptr; /* Internal */
+ ushort spi_tbc; /* Internal */
+ uint spi_txtmp; /* Internal */
+ uint spi_res;
+ ushort spi_rpbase; /* Relocation pointer */
+ ushort spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
+#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
+#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
+#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
+#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
+#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
+#define SPMODE_EN ((ushort)0x0100) /* Enable */
+#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
+#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
+
+#define SPMODE_LEN(x) ((((x) - 1) & 0xF) << 4)
+#define SPMODE_PM(x) ((x) & 0xF)
+
+/* HDLC parameter RAM.
+*/
+
+typedef struct hdlc_pram_s {
+ /*
+ * SCC parameter RAM
+ */
+ ushort rbase; /* Rx Buffer descriptor base address */
+ ushort tbase; /* Tx Buffer descriptor base address */
+ uchar rfcr; /* Rx function code */
+ uchar tfcr; /* Tx function code */
+ ushort mrblr; /* Rx buffer length */
+ ulong rstate; /* Rx internal state */
+ ulong rptr; /* Rx internal data pointer */
+ ushort rbptr; /* rb BD Pointer */
+ ushort rcount; /* Rx internal byte count */
+ ulong rtemp; /* Rx temp */
+ ulong tstate; /* Tx internal state */
+ ulong tptr; /* Tx internal data pointer */
+ ushort tbptr; /* Tx BD pointer */
+ ushort tcount; /* Tx byte count */
+ ulong ttemp; /* Tx temp */
+ ulong rcrc; /* temp receive CRC */
+ ulong tcrc; /* temp transmit CRC */
+ /*
+ * HDLC specific parameter RAM
+ */
+ uchar res[4]; /* reserved */
+ ulong c_mask; /* CRC constant */
+ ulong c_pres; /* CRC preset */
+ ushort disfc; /* discarded frame counter */
+ ushort crcec; /* CRC error counter */
+ ushort abtsc; /* abort sequence counter */
+ ushort nmarc; /* nonmatching address rx cnt */
+ ushort retrc; /* frame retransmission cnt */
+ ushort mflr; /* maximum frame length reg */
+ ushort max_cnt; /* maximum length counter */
+ ushort rfthr; /* received frames threshold */
+ ushort rfcnt; /* received frames count */
+ ushort hmask; /* user defined frm addr mask */
+ ushort haddr1; /* user defined frm address 1 */
+ ushort haddr2; /* user defined frm address 2 */
+ ushort haddr3; /* user defined frm address 3 */
+ ushort haddr4; /* user defined frm address 4 */
+ ushort tmp; /* temp */
+ ushort tmp_mb; /* temp */
+} hdlc_pram_t;
+
+/* CPM interrupts. There are nearly 32 interrupts generated by CPM
+ * channels or devices. All of these are presented to the PPC core
+ * as a single interrupt. The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler. We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR 32
+#define CPMVEC_OFFSET 0x00010000
+#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
+#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
+#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
+#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
+#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
+#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
+#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
+#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
+#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
+#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
+#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
+#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
+#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
+#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
+
+void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+
+/* CPM interrupt configuration vector.
+*/
+#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
+#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
+#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
+#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
+#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
+#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
+#define CICR_IEN ((uint)0x00000080) /* Int. enable */
+#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
+#endif /* __CPM_8XX__ */
diff --git a/arch/powerpc/include/asm/e300.h b/arch/powerpc/include/asm/e300.h
new file mode 100644
index 0000000..bfef4df
--- /dev/null
+++ b/arch/powerpc/include/asm/e300.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ * Liberty Eran (liberty@freescale.com)
+ */
+
+#ifndef __E300_H__
+#define __E300_H__
+
+#define PVR_E300C1 0x80830000
+#define PVR_E300C2 0x80840000
+#define PVR_E300C3 0x80850000
+#define PVR_E300C4 0x80860000
+
+/*
+ * Hardware Implementation-Dependent Register 0 (HID0)
+ */
+
+/* #define HID0 1008 already defined in processor.h */
+#define HID0_MASK_MACHINE_CHECK 0x00000000
+#define HID0_ENABLE_MACHINE_CHECK 0x80000000
+
+#define HID0_DISABLE_CACHE_PARITY 0x00000000
+#define HID0_ENABLE_CACHE_PARITY 0x40000000
+
+#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
+
+#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY 0x10000000
+
+#define HID0_CORE_CLK_OUT 0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
+
+#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
+#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
+
+#define HID0_DISABLE_DOSE_MODE 0x00000000
+#define HID0_ENABLE_DOSE_MODE 0x00800000
+
+#define HID0_DISABLE_NAP_MODE 0x00000000
+#define HID0_ENABLE_NAP_MODE 0x00400000
+
+#define HID0_DISABLE_SLEEP_MODE 0x00000000
+#define HID0_ENABLE_SLEEP_MODE 0x00200000
+
+#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
+#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
+
+#define HID0_SOFT_RESET 0x00010000
+
+#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
+
+#define HID0_DISABLE_DATA_CACHE 0x00000000
+#define HID0_ENABLE_DATA_CACHE 0x00004000
+
+#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
+
+#define HID0_LOCK_DATA_CACHE 0x00001000
+
+#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
+
+#define HID0_INVALIDATE_DATA_CACHE 0x00000400
+
+#define HID0_DISABLE_M_BIT 0x00000000
+#define HID0_ENABLE_M_BIT 0x00000080
+
+#define HID0_FBIOB 0x00000010
+
+#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
+
+#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
+#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
+
+/*
+ * Hardware Implementation-Dependent Register 2 (HID2)
+ */
+#define HID2 1011
+
+#define HID2_LET 0x08000000
+#define HID2_HBE 0x00040000
+#define HID2_IWLCK_000 0x00000000 /* no ways locked */
+#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
+#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
+#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
+#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
+#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
+#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
+
+#endif /* __E300_H__ */
diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h
new file mode 100644
index 0000000..727f4a7
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_dma.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Freescale DMA Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_FSL_DMA_H_
+#define _ASM_FSL_DMA_H_
+
+#include <asm/types.h>
+
+#ifdef CONFIG_MPC83xx
+typedef struct fsl_dma {
+ uint mr; /* DMA mode register */
+#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
+#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
+#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
+#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
+#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
+#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
+#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
+#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */
+#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */
+#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */
+#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */
+ uint sr; /* DMA status register */
+#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */
+#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
+#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
+#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
+ uint cdar; /* DMA current descriptor address register */
+ char res0[4];
+ uint sar; /* DMA source address register */
+ char res1[4];
+ uint dar; /* DMA destination address register */
+ char res2[4];
+ uint bcr; /* DMA byte count register */
+ uint ndar; /* DMA next descriptor address register */
+ uint gsr; /* DMA general status register (DMA3 ONLY!) */
+ char res3[84];
+} fsl_dma_t;
+#else
+typedef struct fsl_dma {
+ uint mr; /* DMA mode register */
+#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
+#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
+#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
+#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */
+#define FSL_DMA_MR_CDSM 0x00000010
+#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */
+#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */
+#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */
+#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */
+#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */
+#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */
+#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
+#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
+#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */
+#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */
+#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */
+ uint sr; /* DMA status register */
+#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */
+#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
+#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
+#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */
+#define FSL_DMA_SR_PE 0x00000010 /* Programming error */
+#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */
+#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
+ char res0[4];
+ uint clndar; /* DMA current link descriptor address register */
+ uint satr; /* DMA source attributes register */
+#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */
+#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */
+#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */
+#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */
+#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */
+#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */
+#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */
+#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */
+#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */
+ uint sar; /* DMA source address register */
+ uint datr; /* DMA destination attributes register */
+#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */
+#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */
+#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */
+#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */
+#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */
+#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */
+#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */
+#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */
+#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */
+#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */
+ uint dar; /* DMA destination address register */
+ uint bcr; /* DMA byte count register */
+ char res1[4];
+ uint nlndar; /* DMA next link descriptor address register */
+ char res2[8];
+ uint clabdar; /* DMA current List - alternate base descriptor address Register */
+ char res3[4];
+ uint nlsdar; /* DMA next list descriptor address register */
+ uint ssr; /* DMA source stride register */
+ uint dsr; /* DMA destination stride register */
+ char res4[56];
+} fsl_dma_t;
+#endif /* !CONFIG_MPC83xx */
+
+#ifdef CONFIG_FSL_DMA
+void dma_init(void);
+int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
+#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
+void dma_meminit(uint val, uint size);
+#endif
+#endif
+
+#endif /* _ASM_DMA_H_ */
diff --git a/arch/powerpc/include/asm/fsl_fdt.h b/arch/powerpc/include/asm/fsl_fdt.h
new file mode 100644
index 0000000..57bddf2
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_fdt.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+#ifndef _FSL_FDT_H_
+#define _FSL_FDT_H_
+
+void fdt_del_diu(void *blob);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h
new file mode 100644
index 0000000..fbf32b9
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_i2c.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c_base {
+
+ u8 adr; /* I2C slave address */
+ u8 res0[3];
+#define I2C_ADR 0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES ~(I2C_ADR)
+
+ u8 fdr; /* I2C frequency divider register */
+ u8 res1[3];
+#define IC2_FDR 0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES ~(IC2_FDR)
+
+ u8 cr; /* I2C control redister */
+ u8 res2[3];
+#define I2C_CR_MEN 0x80
+#define I2C_CR_MIEN 0x40
+#define I2C_CR_MSTA 0x20
+#define I2C_CR_MTX 0x10
+#define I2C_CR_TXAK 0x08
+#define I2C_CR_RSTA 0x04
+#define I2C_CR_BIT6 0x02 /* required for workaround A004447 */
+#define I2C_CR_BCST 0x01
+
+ u8 sr; /* I2C status register */
+ u8 res3[3];
+#define I2C_SR_MCF 0x80
+#define I2C_SR_MAAS 0x40
+#define I2C_SR_MBB 0x20
+#define I2C_SR_MAL 0x10
+#define I2C_SR_BCSTM 0x08
+#define I2C_SR_SRW 0x04
+#define I2C_SR_MIF 0x02
+#define I2C_SR_RXAK 0x01
+
+ u8 dr; /* I2C data register */
+ u8 res4[3];
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+
+ u8 dfsrr; /* I2C digital filter sampling rate register */
+ u8 res5[3];
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+
+ /* Fill out the reserved block */
+ u8 res6[0xE8];
+} fsl_i2c_t;
+
+#ifdef CONFIG_DM_I2C
+struct fsl_i2c_dev {
+ struct fsl_i2c_base __iomem *base; /* register base */
+ u32 i2c_clk;
+ u32 index;
+ u8 slaveadd;
+ uint speed;
+};
+#endif
+
+#endif /* _ASM_I2C_H_ */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
new file mode 100644
index 0000000..888640d
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_LAW_H_
+#define _FSL_LAW_H_
+
+#include <asm/io.h>
+#include <linux/log2.h>
+
+#define LAW_EN 0x80000000
+
+#define SET_LAW_ENTRY(idx, a, sz, trgt) \
+ { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
+
+#define SET_LAW(a, sz, trgt) \
+ { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
+
+enum law_size {
+ LAW_SIZE_4K = 0xb,
+ LAW_SIZE_8K,
+ LAW_SIZE_16K,
+ LAW_SIZE_32K,
+ LAW_SIZE_64K,
+ LAW_SIZE_128K,
+ LAW_SIZE_256K,
+ LAW_SIZE_512K,
+ LAW_SIZE_1M,
+ LAW_SIZE_2M,
+ LAW_SIZE_4M,
+ LAW_SIZE_8M,
+ LAW_SIZE_16M,
+ LAW_SIZE_32M,
+ LAW_SIZE_64M,
+ LAW_SIZE_128M,
+ LAW_SIZE_256M,
+ LAW_SIZE_512M,
+ LAW_SIZE_1G,
+ LAW_SIZE_2G,
+ LAW_SIZE_4G,
+ LAW_SIZE_8G,
+ LAW_SIZE_16G,
+ LAW_SIZE_32G,
+};
+
+#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
+#define lawar_size(x) (1ULL << ((x & 0x3f) + 1))
+
+#ifdef CONFIG_FSL_CORENET
+enum law_trgt_if {
+ LAW_TRGT_IF_PCIE_1 = 0x00,
+ LAW_TRGT_IF_PCIE_2 = 0x01,
+ LAW_TRGT_IF_PCIE_3 = 0x02,
+ LAW_TRGT_IF_PCIE_4 = 0x03,
+ LAW_TRGT_IF_RIO_1 = 0x08,
+ LAW_TRGT_IF_RIO_2 = 0x09,
+
+ LAW_TRGT_IF_DDR_1 = 0x10,
+ LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
+ LAW_TRGT_IF_DDR_3 = 0x12,
+ LAW_TRGT_IF_DDR_4 = 0x13,
+ LAW_TRGT_IF_DDR_INTRLV = 0x14,
+ LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
+ LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
+ LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
+ LAW_TRGT_IF_BMAN = 0x18,
+ LAW_TRGT_IF_DCSR = 0x1d,
+ LAW_TRGT_IF_CCSR = 0x1e,
+ LAW_TRGT_IF_LBC = 0x1f,
+ LAW_TRGT_IF_QMAN = 0x3c,
+
+ LAW_TRGT_IF_MAPLE = 0x50,
+};
+#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
+#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
+#else
+enum law_trgt_if {
+ LAW_TRGT_IF_PCI = 0x00,
+ LAW_TRGT_IF_PCI_2 = 0x01,
+#ifndef CONFIG_ARCH_MPC8641
+ LAW_TRGT_IF_PCIE_1 = 0x02,
+#endif
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+ LAW_TRGT_IF_OCN_DSP = 0x03,
+#else
+#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
+ LAW_TRGT_IF_PCIE_3 = 0x03,
+#endif
+#endif
+ LAW_TRGT_IF_LBC = 0x04,
+ LAW_TRGT_IF_CCSR = 0x08,
+ LAW_TRGT_IF_DSP_CCSR = 0x09,
+ LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
+ LAW_TRGT_IF_DDR_INTRLV = 0x0b,
+ LAW_TRGT_IF_RIO = 0x0c,
+#if defined(CONFIG_ARCH_BSC9132)
+ LAW_TRGT_IF_CLASS_DSP = 0x0d,
+#else
+ LAW_TRGT_IF_RIO_2 = 0x0d,
+#endif
+ LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
+ LAW_TRGT_IF_DDR = 0x0f,
+ LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
+ /* place holder for 3-way and 4-way interleaving */
+ LAW_TRGT_IF_DDR_3,
+ LAW_TRGT_IF_DDR_4,
+ LAW_TRGT_IF_DDR_INTLV_34,
+ LAW_TRGT_IF_DDR_INTLV_123,
+ LAW_TRGT_IF_DDR_INTLV_1234,
+};
+#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
+#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
+#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
+#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
+#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
+
+#ifdef CONFIG_ARCH_MPC8641
+#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
+#endif
+
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
+#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
+#endif
+#endif /* CONFIG_FSL_CORENET */
+
+struct law_entry {
+ int index;
+ phys_addr_t addr;
+ enum law_size size;
+ enum law_trgt_if trgt_id;
+};
+
+extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
+extern struct law_entry find_law(phys_addr_t addr);
+extern void disable_law(u8 idx);
+extern void init_laws(void);
+extern void print_laws(void);
+
+/* define in board code */
+extern struct law_entry law_table[];
+extern int num_law_entries;
+#endif
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
new file mode 100644
index 0000000..bf352d9
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -0,0 +1,535 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_PPC_FSL_LBC_H
+#define __ASM_PPC_FSL_LBC_H
+
+#include <config.h>
+#include <common.h>
+
+#ifdef CONFIG_MPC85xx
+void lbc_sdram_init(void);
+#endif
+
+/* BR - Base Registers
+ */
+#define BR0 0x5000 /* Register offset to immr */
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_XBA 0x00006000
+#define BR_XBA_SHIFT 13
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_DECC_OFF 0x00000000
+#define BR_DECC_CHK 0x00000200
+#define BR_DECC_CHK_GEN 0x00000400
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
+#define BR_MS_FCM 0x00000020 /* FCM */
+#endif
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#elif defined(CONFIG_MPC85xx)
+#define BR_MS_SDRAM 0x00000000 /* SDRAM */
+#endif
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#if !defined(CONFIG_ARCH_MPC834X)
+#define BR_ATOM 0x0000000C
+#define BR_ATOM_SHIFT 2
+#endif
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+
+#define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT)
+
+#define UPMA 0
+#define UPMB 1
+#define UPMC 2
+
+#if defined(CONFIG_ARCH_MPC834X)
+#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
+#else
+#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
+#endif
+
+/* Convert an address into the right format for the BR registers */
+#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
+#define BR_PHYS_ADDR(x) \
+ ((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
+#endif
+
+/* OR - Option Registers
+ */
+#define OR0 0x5004 /* Register offset to immr */
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_GPCM_AM 0xFFFF8000
+#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_XAM 0x00006000
+#define OR_GPCM_XAM_SHIFT 13
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT 12
+#define OR_GPCM_CSNT 0x00000800
+#define OR_GPCM_CSNT_SHIFT 11
+#define OR_GPCM_ACS 0x00000600
+#define OR_GPCM_ACS_SHIFT 9
+#define OR_GPCM_ACS_DIV2 0x00000600
+#define OR_GPCM_ACS_DIV4 0x00000400
+#define OR_GPCM_XACS 0x00000100
+#define OR_GPCM_XACS_SHIFT 8
+#define OR_GPCM_SCY 0x000000F0
+#define OR_GPCM_SCY_SHIFT 4
+#define OR_GPCM_SCY_1 0x00000010
+#define OR_GPCM_SCY_2 0x00000020
+#define OR_GPCM_SCY_3 0x00000030
+#define OR_GPCM_SCY_4 0x00000040
+#define OR_GPCM_SCY_5 0x00000050
+#define OR_GPCM_SCY_6 0x00000060
+#define OR_GPCM_SCY_7 0x00000070
+#define OR_GPCM_SCY_8 0x00000080
+#define OR_GPCM_SCY_9 0x00000090
+#define OR_GPCM_SCY_10 0x000000a0
+#define OR_GPCM_SCY_11 0x000000b0
+#define OR_GPCM_SCY_12 0x000000c0
+#define OR_GPCM_SCY_13 0x000000d0
+#define OR_GPCM_SCY_14 0x000000e0
+#define OR_GPCM_SCY_15 0x000000f0
+#define OR_GPCM_SETA 0x00000008
+#define OR_GPCM_SETA_SHIFT 3
+#define OR_GPCM_TRLX 0x00000004
+#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_TRLX_CLEAR 0x00000000
+#define OR_GPCM_TRLX_SET 0x00000004
+#define OR_GPCM_EHTR 0x00000002
+#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EHTR_CLEAR 0x00000000
+#define OR_GPCM_EHTR_SET 0x00000002
+#if !defined(CONFIG_ARCH_MPC8308)
+#define OR_GPCM_EAD 0x00000001
+#define OR_GPCM_EAD_SHIFT 0
+#endif
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
+#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
+
+#define OR_FCM_AM 0xFFFF8000
+#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_XAM 0x00006000
+#define OR_FCM_XAM_SHIFT 13
+#define OR_FCM_BCTLD 0x00001000
+#define OR_FCM_BCTLD_SHIFT 12
+#define OR_FCM_PGS 0x00000400
+#define OR_FCM_PGS_SHIFT 10
+#define OR_FCM_CSCT 0x00000200
+#define OR_FCM_CSCT_SHIFT 9
+#define OR_FCM_CST 0x00000100
+#define OR_FCM_CST_SHIFT 8
+#define OR_FCM_CHT 0x00000080
+#define OR_FCM_CHT_SHIFT 7
+#define OR_FCM_SCY 0x00000070
+#define OR_FCM_SCY_SHIFT 4
+#define OR_FCM_SCY_1 0x00000010
+#define OR_FCM_SCY_2 0x00000020
+#define OR_FCM_SCY_3 0x00000030
+#define OR_FCM_SCY_4 0x00000040
+#define OR_FCM_SCY_5 0x00000050
+#define OR_FCM_SCY_6 0x00000060
+#define OR_FCM_SCY_7 0x00000070
+#define OR_FCM_RST 0x00000008
+#define OR_FCM_RST_SHIFT 3
+#define OR_FCM_TRLX 0x00000004
+#define OR_FCM_TRLX_SHIFT 2
+#define OR_FCM_EHTR 0x00000002
+#define OR_FCM_EHTR_SHIFT 1
+
+#define OR_UPM_AM 0xFFFF8000
+#define OR_UPM_AM_SHIFT 15
+#define OR_UPM_XAM 0x00006000
+#define OR_UPM_XAM_SHIFT 13
+#define OR_UPM_BCTLD 0x00001000
+#define OR_UPM_BCTLD_SHIFT 12
+#define OR_UPM_BI 0x00000100
+#define OR_UPM_BI_SHIFT 8
+#define OR_UPM_TRLX 0x00000004
+#define OR_UPM_TRLX_SHIFT 2
+#define OR_UPM_EHTR 0x00000002
+#define OR_UPM_EHTR_SHIFT 1
+#define OR_UPM_EAD 0x00000001
+#define OR_UPM_EAD_SHIFT 0
+
+#define OR_SDRAM_AM 0xFFFF8000
+#define OR_SDRAM_AM_SHIFT 15
+#define OR_SDRAM_XAM 0x00006000
+#define OR_SDRAM_XAM_SHIFT 13
+#define OR_SDRAM_COLS 0x00001C00
+#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_MIN_COLS 7
+#define OR_SDRAM_ROWS 0x000001C0
+#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_MIN_ROWS 9
+#define OR_SDRAM_PMSEL 0x00000020
+#define OR_SDRAM_PMSEL_SHIFT 5
+#define OR_SDRAM_EAD 0x00000001
+#define OR_SDRAM_EAD_SHIFT 0
+
+#define OR_AM_32KB 0xFFFF8000
+#define OR_AM_64KB 0xFFFF0000
+#define OR_AM_128KB 0xFFFE0000
+#define OR_AM_256KB 0xFFFC0000
+#define OR_AM_512KB 0xFFF80000
+#define OR_AM_1MB 0xFFF00000
+#define OR_AM_2MB 0xFFE00000
+#define OR_AM_4MB 0xFFC00000
+#define OR_AM_8MB 0xFF800000
+#define OR_AM_16MB 0xFF000000
+#define OR_AM_32MB 0xFE000000
+#define OR_AM_64MB 0xFC000000
+#define OR_AM_128MB 0xF8000000
+#define OR_AM_256MB 0xF0000000
+#define OR_AM_512MB 0xE0000000
+#define OR_AM_1GB 0xC0000000
+#define OR_AM_2GB 0x80000000
+#define OR_AM_4GB 0x00000000
+
+/* MxMR - UPM Machine A/B/C Mode Registers
+ */
+#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
+#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
+#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
+#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
+#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
+#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
+#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
+#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
+#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
+#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
+#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
+#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
+#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
+#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
+#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
+#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
+#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
+#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
+#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
+#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
+#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
+#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
+#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
+#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
+#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
+#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
+#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
+#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
+#define MxMR_UWPL 0x08000000 /* LUPWAIT Polarity Mask */
+#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
+#define MxMR_OP_WARR 0x10000000 /* Write to Array */
+#define MxMR_OP_RARR 0x20000000 /* Read from Array */
+#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
+#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
+#define MxMR_RFEN 0x40000000 /* Refresh Enable */
+#define MxMR_BSEL 0x80000000 /* Bus Select */
+
+#define LBLAWAR_EN 0x80000000
+#define LBLAWAR_4KB 0x0000000B
+#define LBLAWAR_8KB 0x0000000C
+#define LBLAWAR_16KB 0x0000000D
+#define LBLAWAR_32KB 0x0000000E
+#define LBLAWAR_64KB 0x0000000F
+#define LBLAWAR_128KB 0x00000010
+#define LBLAWAR_256KB 0x00000011
+#define LBLAWAR_512KB 0x00000012
+#define LBLAWAR_1MB 0x00000013
+#define LBLAWAR_2MB 0x00000014
+#define LBLAWAR_4MB 0x00000015
+#define LBLAWAR_8MB 0x00000016
+#define LBLAWAR_16MB 0x00000017
+#define LBLAWAR_32MB 0x00000018
+#define LBLAWAR_64MB 0x00000019
+#define LBLAWAR_128MB 0x0000001A
+#define LBLAWAR_256MB 0x0000001B
+#define LBLAWAR_512MB 0x0000001C
+#define LBLAWAR_1GB 0x0000001D
+#define LBLAWAR_2GB 0x0000001E
+
+/* LBCR - Local Bus Configuration Register
+ */
+#define LBCR_LDIS 0x80000000
+#define LBCR_LDIS_SHIFT 31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT 22
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT 17
+#define LBCR_EPAR 0x00010000
+#define LBCR_EPAR_SHIFT 16
+#define LBCR_BMT 0x0000FF00
+#define LBCR_BMT_SHIFT 8
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT 0
+
+/* LCRR - Clock Ratio Register
+ */
+#define LCRR_DBYP 0x80000000
+#define LCRR_DBYP_SHIFT 31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT 28
+#define LCRR_BUFCMDC_1 0x10000000
+#define LCRR_BUFCMDC_2 0x20000000
+#define LCRR_BUFCMDC_3 0x30000000
+#define LCRR_BUFCMDC_4 0x00000000
+#define LCRR_ECL 0x03000000
+#define LCRR_ECL_SHIFT 24
+#define LCRR_ECL_4 0x00000000
+#define LCRR_ECL_5 0x01000000
+#define LCRR_ECL_6 0x02000000
+#define LCRR_ECL_7 0x03000000
+#define LCRR_EADC 0x00030000
+#define LCRR_EADC_SHIFT 16
+#define LCRR_EADC_1 0x00010000
+#define LCRR_EADC_2 0x00020000
+#define LCRR_EADC_3 0x00030000
+#define LCRR_EADC_4 0x00000000
+/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
+ * should always be zero on older parts that have a four bit CLKDIV.
+ */
+#define LCRR_CLKDIV 0x0000001F
+#define LCRR_CLKDIV_SHIFT 0
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
+ defined(CONFIG_ARCH_MPC8560)
+#define LCRR_CLKDIV_2 0x00000002
+#define LCRR_CLKDIV_4 0x00000004
+#define LCRR_CLKDIV_8 0x00000008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8 0x00000002
+#define LCRR_CLKDIV_16 0x00000004
+#define LCRR_CLKDIV_32 0x00000008
+#else
+#define LCRR_CLKDIV_4 0x00000002
+#define LCRR_CLKDIV_8 0x00000004
+#define LCRR_CLKDIV_16 0x00000008
+#endif
+
+/* LTEDR - Transfer Error Check Disable Register
+ */
+#define LTEDR_BMD 0x80000000 /* Bus monitor disable */
+#define LTEDR_PARD 0x20000000 /* Parity error checking disabled */
+#define LTEDR_WPD 0x04000000 /* Write protect error checking diable */
+#define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */
+#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
+#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
+
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO 0x0000F000
+#define FMR_CWTO_SHIFT 12
+#define FMR_BOOT 0x00000800
+#define FMR_ECCM 0x00000100
+#define FMR_AL 0x00000030
+#define FMR_AL_SHIFT 4
+#define FMR_OP 0x00000003
+#define FMR_OP_SHIFT 0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0 0xF0000000
+#define FIR_OP0_SHIFT 28
+#define FIR_OP1 0x0F000000
+#define FIR_OP1_SHIFT 24
+#define FIR_OP2 0x00F00000
+#define FIR_OP2_SHIFT 20
+#define FIR_OP3 0x000F0000
+#define FIR_OP3_SHIFT 16
+#define FIR_OP4 0x0000F000
+#define FIR_OP4_SHIFT 12
+#define FIR_OP5 0x00000F00
+#define FIR_OP5_SHIFT 8
+#define FIR_OP6 0x000000F0
+#define FIR_OP6_SHIFT 4
+#define FIR_OP7 0x0000000F
+#define FIR_OP7_SHIFT 0
+#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
+#define FIR_OP_CA 0x1 /* Issue current column address */
+#define FIR_OP_PA 0x2 /* Issue current block+page address */
+#define FIR_OP_UA 0x3 /* Issue user defined address */
+#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0 0xFF000000
+#define FCR_CMD0_SHIFT 24
+#define FCR_CMD1 0x00FF0000
+#define FCR_CMD1_SHIFT 16
+#define FCR_CMD2 0x0000FF00
+#define FCR_CMD2_SHIFT 8
+#define FCR_CMD3 0x000000FF
+#define FCR_CMD3_SHIFT 0
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK 0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI 0x00007C00
+#define FPAR_SP_PI_SHIFT 10
+#define FPAR_SP_MS 0x00000200
+#define FPAR_SP_CI 0x000001FF
+#define FPAR_SP_CI_SHIFT 0
+#define FPAR_LP_PI 0x0003F000
+#define FPAR_LP_PI_SHIFT 12
+#define FPAR_LP_MS 0x00000800
+#define FPAR_LP_CI 0x000007FF
+#define FPAR_LP_CI_SHIFT 0
+
+/* LSDMR - SDRAM Machine Mode Register
+ */
+#define LSDMR_RFEN (1 << (31 - 1))
+#define LSDMR_BSMA1516 (3 << (31 - 10))
+#define LSDMR_BSMA1617 (4 << (31 - 10))
+#define LSDMR_RFCR5 (3 << (31 - 16))
+#define LSDMR_RFCR8 (5 << (31 - 16))
+#define LSDMR_RFCR16 (7 << (31 - 16))
+#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT6 (5 << (31 - 19))
+#define LSDMR_PRETOACT7 (7 << (31 - 19))
+#define LSDMR_ACTTORW3 (3 << (31 - 22))
+#define LSDMR_ACTTORW7 (7 << (31 - 22))
+#define LSDMR_ACTTORW6 (6 << (31 - 22))
+#define LSDMR_BL8 (1 << (31 - 23))
+#define LSDMR_WRC2 (2 << (31 - 27))
+#define LSDMR_WRC3 (3 << (31 - 27))
+#define LSDMR_WRC4 (0 << (31 - 27))
+#define LSDMR_BUFCMD (1 << (31 - 29))
+#define LSDMR_CL3 (3 << (31 - 31))
+
+#define LSDMR_OP_NORMAL (0 << (31 - 4))
+#define LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define LSDMR_OP_MRW (3 << (31 - 4))
+#define LSDMR_OP_PRECH (4 << (31 - 4))
+#define LSDMR_OP_PCHALL (5 << (31 - 4))
+#define LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define LSDMR_OP_RWINV (7 << (31 - 4))
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM 0x80000000
+#define LTESR_FCT 0x40000000
+#define LTESR_PAR 0x20000000
+#define LTESR_WP 0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS 0x00080000
+#define LTESR_CC 0x00000001
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+extern void print_lbc_regs(void);
+extern void init_early_memctl_regs(void);
+extern void upmconfig(uint upm, uint *table, uint size);
+
+#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
+#define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
+#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
+#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
+#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
+#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
+
+typedef struct lbc_bank {
+ u32 br;
+ u32 or;
+} lbc_bank_t;
+
+/* Local Bus Controller Registers */
+typedef struct fsl_lbc {
+ lbc_bank_t bank[8];
+ u8 res1[40];
+ u32 mar; /* LBC UPM Addr */
+ u8 res2[4];
+ u32 mamr; /* LBC UPMA Mode */
+ u32 mbmr; /* LBC UPMB Mode */
+ u32 mcmr; /* LBC UPMC Mode */
+ u8 res3[8];
+ u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
+ u32 mdr; /* LBC UPM Data */
+#ifdef CONFIG_FSL_ELBC
+ u8 res4[4];
+ u32 lsor;
+ u8 res5[12];
+ u32 lurt; /* LBC UPM Refresh Timer */
+ u8 res6[4];
+#else
+ u8 res4[8];
+ u32 lsdmr; /* LBC SDRAM Mode */
+ u8 res5[8];
+ u32 lurt; /* LBC UPM Refresh Timer */
+ u32 lsrt; /* LBC SDRAM Refresh Timer */
+#endif
+ u8 res7[8];
+ u32 ltesr; /* LBC Transfer Error Status */
+ u32 ltedr; /* LBC Transfer Error Disable */
+ u32 lteir; /* LBC Transfer Error IRQ */
+ u32 lteatr; /* LBC Transfer Error Attrs */
+ u32 ltear; /* LBC Transfer Error Addr */
+ u8 res8[12];
+ u32 lbcr; /* LBC Configuration */
+ u32 lcrr; /* LBC Clock Ratio */
+#ifdef CONFIG_NAND_FSL_ELBC
+ u8 res9[0x8];
+ u32 fmr; /* Flash Mode Register */
+ u32 fir; /* Flash Instruction Register */
+ u32 fcr; /* Flash Command Register */
+ u32 fbar; /* Flash Block Addr Register */
+ u32 fpar; /* Flash Page Addr Register */
+ u32 fbcr; /* Flash Byte Count Register */
+ u8 res10[0xF08];
+#else
+ u8 res9[0xF28];
+#endif
+} fsl_lbc_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
new file mode 100644
index 0000000..7ced50c
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_LIODN_H_
+#define _FSL_LIODN_H_
+
+#include <asm/types.h>
+#include <fsl_qbman.h>
+
+struct srio_liodn_id_table {
+ u32 id[2];
+ unsigned long reg_offset[2];
+ u8 num_ids;
+ u8 portid;
+};
+#define SET_SRIO_LIODN_1(port, idA) \
+ { .id = { idA }, .num_ids = 1, .portid = port, \
+ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
+ + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ }
+
+#define SET_SRIO_LIODN_2(port, idA, idB) \
+ { .id = { idA, idB }, .num_ids = 2, .portid = port, \
+ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
+ + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
+ + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ }
+
+#define SET_SRIO_LIODN_BASE(port, id_a) \
+ { .id = { id_a }, .num_ids = 1, .portid = port, \
+ .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+ + (port - 1) * 0x200 \
+ + CONFIG_SYS_FSL_SRIO_ADDR, \
+ }
+
+struct liodn_id_table {
+ const char * compat;
+ u32 id[2];
+ u8 num_ids;
+ phys_addr_t compat_offset;
+ unsigned long reg_offset;
+};
+
+struct fman_liodn_id_table {
+ /* Freescale FMan Device Tree binding was updated for FMan.
+ * We need to support both new and old compatibles in order not to
+ * break backward compatibility.
+ */
+ const char *compat[2];
+ u32 id[2];
+ u8 num_ids;
+ phys_addr_t compat_offset;
+ unsigned long reg_offset;
+};
+
+extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid);
+extern void set_liodns(void);
+extern void fdt_fixup_liodn(void *blob);
+
+#define SET_LIODN_BASE_1(idA) \
+ { .id = { idA }, .num_ids = 1, }
+
+#define SET_LIODN_BASE_2(idA, idB) \
+ { .id = { idA, idB }, .num_ids = 2 }
+
+#define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\
+ { .compat[0] = name1, \
+ .compat[1] = name2, \
+ .id = { idA }, .num_ids = 1, \
+ .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+ { .compat = name, \
+ .id = { idA }, .num_ids = 1, \
+ .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+ { .compat = name, \
+ .id = { idA, idB }, .num_ids = 2, \
+ .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
+ SET_LIODN_ENTRY_1(compat, liodn, \
+ offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+ compatoff)
+
+#define SET_USB_LIODN(usbNum, compat, liodn) \
+ SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
+ CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+
+#define SET_SATA_LIODN(sataNum, liodn) \
+ SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
+ CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+
+#define SET_PCI_LIODN(compat, pciNum, liodn) \
+ SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
+ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+ SET_LIODN_ENTRY_1(compat, liodn,\
+ offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
+/* reg nodes for DMA start @ 0x300 */
+#define SET_DMA_LIODN(dmaNum, compat, liodn) \
+ SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
+ CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+
+#define SET_SDHC_LIODN(sdhcNum, liodn) \
+ SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
+ CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+
+#define SET_QE_LIODN(liodn) \
+ SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
+ CONFIG_SYS_MPC85xx_QE_OFFSET)
+
+#define SET_TDM_LIODN(liodn) \
+ SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+ CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
+#define SET_QMAN_LIODN(liodn) \
+ SET_LIODN_ENTRY_1("fsl,qman", liodn, \
+ offsetof(struct ccsr_qman, liodnr) + \
+ CONFIG_SYS_FSL_QMAN_OFFSET, \
+ CONFIG_SYS_FSL_QMAN_OFFSET)
+
+#define SET_BMAN_LIODN(liodn) \
+ SET_LIODN_ENTRY_1("fsl,bman", liodn, \
+ offsetof(struct ccsr_bman, liodnr) + \
+ CONFIG_SYS_FSL_BMAN_OFFSET, \
+ CONFIG_SYS_FSL_BMAN_OFFSET)
+
+#define SET_PME_LIODN(liodn) \
+ SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
+ CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
+ CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+
+#define SET_PMAN_LIODN(num, liodn) \
+ SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
+ offsetof(struct ccsr_pman, ppa1) + \
+ CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+ CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+
+/* -1 from portID due to how immap has the registers */
+#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
+ CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
+ offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
+
+#ifdef CONFIG_SYS_FMAN_V3
+/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
+#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
+ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
+ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+
+/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
+ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
+ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
+ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+
+/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
+ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
+ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+#else
+/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
+#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
+ SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
+ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+
+/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
+ SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
+ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
+ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+#endif
+/*
+ * handle both old and new versioned SEC properties:
+ * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
+ */
+#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
+ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
+ SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
+ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
+
+/* This is a bit evil since we treat rtic param as both a string & hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+ SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+
+#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
+ offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, 0)
+
+#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
+ SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
+ liodnA, \
+ offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
+ CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+ offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
+ CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+
+#define SET_RMAN_LIODN(ibNum, liodn) \
+ SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
+ offsetof(struct ccsr_rman, mmitdr) + \
+ CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
+ CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
+
+extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
+extern struct liodn_id_table raide_liodn_tbl[];
+extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+#ifdef CONFIG_SYS_SRIO
+extern struct srio_liodn_id_table srio_liodn_tbl[];
+extern int srio_liodn_tbl_sz;
+#endif
+extern struct liodn_id_table rman_liodn_tbl[];
+extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
+extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
+extern int rman_liodn_tbl_sz;
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h
new file mode 100644
index 0000000..a02b599
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_MPC83XX_SERDES_H
+#define __FSL_MPC83XX_SERDES_H
+
+#ifndef CONFIG_MPC83XX_SERDES
+
+#include <config.h>
+
+#define FSL_SERDES_CLK_100 (0 << 28)
+#define FSL_SERDES_CLK_125 (1 << 28)
+#define FSL_SERDES_CLK_150 (3 << 28)
+#define FSL_SERDES_PROTO_SATA 0
+#define FSL_SERDES_PROTO_PEX 1
+#define FSL_SERDES_PROTO_PEX_X2 2
+#define FSL_SERDES_PROTO_SGMII 3
+#define FSL_SERDES_VDD_1V 1
+
+extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
+
+#endif /* !CONFIG_MPC83XX_SERDES */
+
+#endif /* __FSL_MPC83XX_SERDES_H */
diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h
new file mode 100644
index 0000000..07e822b
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_pamu.h
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __PAMU_H
+#define __PAMU_H
+
+#define CONFIG_NUM_PAMU 16
+#define NUM_PPAACT_ENTRIES 512
+#define NUM_SPAACT_ENTRIES 256
+
+/* PAMU_OFFSET to the next pamu space in ccsr */
+#define PAMU_OFFSET 0x1000
+
+#define PAMU_TABLE_ALIGNMENT 0x00001000
+
+#define PAMU_PAGE_SHIFT 12
+#define PAMU_PAGE_SIZE 4096U
+
+#define PAACE_M_COHERENCE_REQ 0x01
+
+#define PAACE_DA_HOST_CR 0x80
+#define PAACE_DA_HOST_CR_SHIFT 7
+
+#define PAACE_AF_PT 0x00000002
+#define PAACE_AF_PT_SHIFT 1
+
+#define PAACE_PT_PRIMARY 0x0
+#define PAACE_PT_SECONDARY 0x1
+
+#define PPAACE_AF_WBAL 0xfffff000
+#define PPAACE_AF_WBAL_SHIFT 12
+
+#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */
+
+#define PAACE_IA_CID 0x00FF0000
+#define PAACE_IA_CID_SHIFT 16
+#define PAACE_IA_WCE 0x000000F0
+#define PAACE_IA_WCE_SHIFT 4
+#define PAACE_IA_ATM 0x0000000C
+#define PAACE_IA_ATM_SHIFT 2
+#define PAACE_IA_OTM 0x00000003
+#define PAACE_IA_OTM_SHIFT 0
+
+#define PAACE_OTM_NO_XLATE 0x00
+#define PAACE_OTM_IMMEDIATE 0x01
+#define PAACE_OTM_INDEXED 0x02
+#define PAACE_OTM_RESERVED 0x03
+#define PAACE_ATM_NO_XLATE 0x00
+#define PAACE_ATM_WINDOW_XLATE 0x01
+#define PAACE_ATM_PAGE_XLATE 0x02
+#define PAACE_ATM_WIN_PG_XLATE \
+ (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
+#define PAACE_WIN_TWBAL 0xfffff000
+#define PAACE_WIN_TWBAL_SHIFT 12
+#define PAACE_WIN_SWSE 0x00000fc0
+#define PAACE_WIN_SWSE_SHIFT 6
+
+#define PAACE_AF_AP 0x00000018
+#define PAACE_AF_AP_SHIFT 3
+#define PAACE_AF_DD 0x00000004
+#define PAACE_AF_DD_SHIFT 2
+#define PAACE_AF_PT 0x00000002
+#define PAACE_AF_PT_SHIFT 1
+#define PAACE_AF_V 0x00000001
+#define PAACE_AF_V_SHIFT 0
+#define PPAACE_AF_WSE 0x00000fc0
+#define PPAACE_AF_WSE_SHIFT 6
+#define PPAACE_AF_MW 0x00000020
+#define PPAACE_AF_MW_SHIFT 5
+
+#define PAACE_AP_PERMS_DENIED 0x0
+#define PAACE_AP_PERMS_QUERY 0x1
+#define PAACE_AP_PERMS_UPDATE 0x2
+#define PAACE_AP_PERMS_ALL 0x3
+
+#define SPAACE_AF_LIODN 0xffff0000
+#define SPAACE_AF_LIODN_SHIFT 16
+#define PAACE_V_VALID 0x1
+
+#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \
+ (m##_SHIFT)) & (m)))
+#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT))
+
+#define DEFAULT_NUM_SUBWINDOWS 128
+#define PAMU_PCR_OFFSET 0xc10
+#define PAMU_PCR_PE 0x40000000
+
+struct pamu_addr_tbl {
+ phys_addr_t start_addr[10];
+ phys_addr_t end_addr[10];
+ phys_size_t size[10];
+};
+
+struct paace {
+ /* PAACE Offset 0x00 */
+ uint32_t wbah; /* only valid for Primary PAACE */
+ uint32_t addr_bitfields; /* See P/S PAACE_AF_* */
+
+ /* PAACE Offset 0x08 */
+ /* Interpretation of first 32 bits dependent on DD above */
+ union {
+ struct {
+ /* Destination ID, see PAACE_DID_* defines */
+ uint8_t did;
+ /* Partition ID */
+ uint8_t pid;
+ /* Snoop ID */
+ uint8_t snpid;
+ /* coherency_required : 1 reserved : 7 */
+ uint8_t coherency_required; /* See PAACE_DA_* */
+ } to_host;
+ struct {
+ /* Destination ID, see PAACE_DID_* defines */
+ uint8_t did;
+ uint8_t reserved1;
+ uint16_t reserved2;
+ } to_io;
+ } domain_attr;
+
+ /* Implementation attributes + window count + address & operation
+ * translation modes
+ */
+ uint32_t impl_attr; /* See PAACE_IA_* */
+
+ /* PAACE Offset 0x10 */
+ /* Translated window base address */
+ uint32_t twbah;
+ uint32_t win_bitfields; /* See PAACE_WIN_* */
+
+ /* PAACE Offset 0x18 */
+ /* first secondary paace entry */
+ uint32_t fspi; /* only valid for Primary PAACE */
+ union {
+ struct {
+ uint8_t ioea;
+ uint8_t moea;
+ uint8_t ioeb;
+ uint8_t moeb;
+ } immed_ot;
+ struct {
+ uint16_t reserved;
+ uint16_t omi;
+ } index_ot;
+ } op_encode;
+
+ /* PAACE Offset 0x20 */
+ uint32_t reserved1[2]; /* not currently implemented */
+
+ /* PAACE Offset 0x28 */
+ uint32_t reserved2[2]; /* not currently implemented */
+
+ /* PAACE Offset 0x30 */
+ uint32_t reserved3[2]; /* not currently implemented */
+
+ /* PAACE Offset 0x38 */
+ uint32_t reserved4[2]; /* not currently implemented */
+
+};
+
+int pamu_init(void);
+void pamu_enable(void);
+void pamu_disable(void);
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
new file mode 100644
index 0000000..5088348
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_PCI_H_
+#define __FSL_PCI_H_
+
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <pci.h>
+
+#define PEX_IP_BLK_REV_2_2 0x02080202
+#define PEX_IP_BLK_REV_2_3 0x02080203
+#define PEX_IP_BLK_REV_3_0 0x02080300
+
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR 0x44
+
+#define FSL_PCIE_CFG_RDY 0x4b0
+#define FSL_PCIE_V3_CFG_RDY 0x1
+#define FSL_PROG_IF_AGENT 0x1
+
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
+
+int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
+int fsl_is_pci_agent(struct pci_controller *hose);
+void fsl_pci_config_unlock(struct pci_controller *hose);
+void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
+
+/*
+ * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
+ */
+
+/*
+ * PCI Translation Registers
+ */
+typedef struct pci_outbound_window {
+ u32 potar; /* 0x00 - Address */
+ u32 potear; /* 0x04 - Address Extended */
+ u32 powbar; /* 0x08 - Window Base Address */
+ u32 res1;
+ u32 powar; /* 0x10 - Window Attributes */
+#define POWAR_EN 0x80000000
+#define POWAR_IO_READ 0x00080000
+#define POWAR_MEM_READ 0x00040000
+#define POWAR_IO_WRITE 0x00008000
+#define POWAR_MEM_WRITE 0x00004000
+ u32 res2[3];
+} pot_t;
+
+typedef struct pci_inbound_window {
+ u32 pitar; /* 0x00 - Address */
+ u32 res1;
+ u32 piwbar; /* 0x08 - Window Base Address */
+ u32 piwbear; /* 0x0c - Window Base Address Extended */
+ u32 piwar; /* 0x10 - Window Attributes */
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_LOCAL 0x00f00000
+#define PIWAR_READ_SNOOP 0x00050000
+#define PIWAR_WRITE_SNOOP 0x00005000
+ u32 res2[3];
+} pit_t;
+
+/* PCI/PCI Express Registers */
+typedef struct ccsr_pci {
+ u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
+ u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
+ u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
+ u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
+ u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
+ u32 config; /* 0x014 - PCIE CONFIG Register */
+ u32 int_status; /* 0x018 - PCIE interrupt status register */
+ char res2[4];
+ u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
+ u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
+ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
+ u32 pm_command; /* 0x02c - PCIE PM Command register */
+ char res3[2188]; /* (0x8bc - 0x30 = 2188) */
+ u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */
+ char res4[824]; /* (0xbf8 - 0x8c0 = 824) */
+ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
+ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
+
+ pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
+ u32 res5[24];
+ pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */
+ u32 res6[24];
+ pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
+
+#define PIT3 0
+#define PIT2 1
+#define PIT1 2
+
+#if 0
+ u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */
+ u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
+ char res5[8];
+ u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */
+ char res6[12];
+ u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */
+ u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
+ u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */
+ char res7[4];
+ u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */
+ char res8[12];
+ u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */
+ u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
+ u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */
+ char res9[4];
+ u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */
+ char res10[12];
+ u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */
+ u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
+ u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */
+ char res11[4];
+ u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */
+ char res12[12];
+ u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */
+ u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
+ u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */
+ char res13[4];
+ u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */
+ char res14[268];
+ u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */
+ char res15[4];
+ u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */
+ u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
+ u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
+ char res16[12];
+ u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */
+ char res17[4];
+ u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
+ u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
+ u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
+ char res18[12];
+ u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */
+ char res19[4];
+ u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */
+ char res20[4];
+ u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
+ char res21[12];
+#endif
+ u32 pedr; /* 0xe00 - PCI Error Detect Register */
+ u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */
+ u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */
+ u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */
+ u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */
+/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */
+ u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */
+ u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */
+ u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */
+ u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */
+/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */
+ char res22[4];
+ u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */
+ u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
+ u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
+ u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
+ char res23[200];
+ u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
+ char res24[16];
+ u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/
+ u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/
+ char res25[228];
+} ccsr_fsl_pci_t;
+#define PCIE_CONFIG_PC 0x00020000
+#define PCIE_CONFIG_OB_CK 0x00002000
+#define PCIE_CONFIG_SAC 0x00000010
+#define PCIE_CONFIG_SP 0x80000002
+#define PCIE_CONFIG_SCC 0x80000001
+
+struct fsl_pci_info {
+ unsigned long regs;
+ pci_addr_t mem_bus;
+ phys_size_t mem_phys;
+ pci_size_t mem_size;
+ pci_addr_t io_bus;
+ phys_size_t io_phys;
+ pci_size_t io_size;
+ enum law_trgt_if law;
+ int pci_num;
+};
+
+void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+ struct pci_controller *hose, int busno);
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+ struct fsl_pci_info *pci_info);
+int fsl_pcie_init_board(int busno);
+
+#define SET_STD_PCI_INFO(x, num) \
+{ \
+ x.regs = CONFIG_SYS_PCI##num##_ADDR; \
+ x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
+ x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
+ x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
+ x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
+ x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
+ x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCI_##num; \
+ x.pci_num = num; \
+}
+
+#define SET_STD_PCIE_INFO(x, num) \
+{ \
+ x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
+ x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
+ x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
+ x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
+ x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
+ x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
+ x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCIE_##num; \
+ x.pci_num = num; \
+}
+
+#define __FT_FSL_PCI_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
+ ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
+
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
+
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
+
+#if !defined(CONFIG_PCI)
+#define FT_FSL_PCI_SETUP
+#elif defined(CONFIG_FSL_CORENET)
+#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP; \
+ FT_FSL_PCIE4_SETUP;
+#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
+#elif defined(CONFIG_MPC85xx)
+#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
+#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
+#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
+#else
+#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
+#endif
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCI2_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP;
+#define FT_FSL_PCIE_SETUP \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP; \
+ FT_FSL_PCIE3_SETUP;
+#elif defined(CONFIG_MPC86xx)
+#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
+#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
+#define FT_FSL_PCI_SETUP \
+ FT_FSL_PCI1_SETUP; \
+ FT_FSL_PCIE1_SETUP; \
+ FT_FSL_PCIE2_SETUP;
+#else
+#error FT_FSL_PCI_SETUP not defined
+#endif
+
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
new file mode 100644
index 0000000..b1fd6bd
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_PORTALS_H_
+#define _FSL_PORTALS_H_
+
+/* entries must be in order and contiguous */
+enum fsl_dpaa_dev {
+ FSL_HW_PORTAL_SEC,
+#ifdef CONFIG_SYS_DPAA_FMAN
+ FSL_HW_PORTAL_FMAN1,
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ FSL_HW_PORTAL_FMAN2,
+#endif
+#endif
+ FSL_HW_PORTAL_PME,
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+ FSL_HW_PORTAL_RAID_ENGINE,
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ FSL_HW_PORTAL_RMAN,
+#endif
+#ifdef CONFIG_SYS_DPAA_DCE
+ FSL_HW_PORTAL_DCE,
+#endif
+
+};
+
+struct qportal_info {
+ u16 dliodn; /* DQRR LIODN */
+ u16 fliodn; /* frame data LIODN */
+ u16 liodn_offset;
+ u8 sdest;
+};
+
+#define SET_QP_INFO(dqrr, fdata, off, dest) \
+ { .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }
+
+extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
+ u32 *liodns, int liodn_offset);
+extern struct qportal_info qp_info[];
+extern void fdt_portal(void *blob, const char *compat, const char *container,
+ u64 addr, u32 size);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
new file mode 100644
index 0000000..64c1007
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SECURE_BOOT_H
+#define __FSL_SECURE_BOOT_H
+#include <asm/config_mpc85xx.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#if defined(CONFIG_FSL_CORENET)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
+#elif defined(CONFIG_TARGET_BSC9132QDS)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
+#elif defined(CONFIG_TARGET_C29XPCIE)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
+#else
+#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
+#endif
+#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
+
+#if defined(CONFIG_TARGET_B4860QDS) || \
+ defined(CONFIG_TARGET_B4420QDS) || \
+ defined(CONFIG_TARGET_T4160QDS) || \
+ defined(CONFIG_TARGET_T4240QDS) || \
+ defined(CONFIG_TARGET_T2080QDS) || \
+ defined(CONFIG_TARGET_T2080RDB) || \
+ defined(CONFIG_TARGET_T1040QDS) || \
+ defined(CONFIG_TARGET_T1040RDB) || \
+ defined(CONFIG_TARGET_T1040D4RDB) || \
+ defined(CONFIG_TARGET_T1042RDB) || \
+ defined(CONFIG_TARGET_T1042D4RDB) || \
+ defined(CONFIG_TARGET_T1042RDB_PI) || \
+ defined(CONFIG_ARCH_T1023) || \
+ defined(CONFIG_ARCH_T1024)
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_CPC_REINIT_F
+#endif
+#define CONFIG_KEY_REVOCATION
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#undef CONFIG_SYS_INIT_L3_ADDR
+#ifdef CONFIG_SYS_INIT_L3_VADDR
+#define CONFIG_SYS_INIT_L3_ADDR \
+ (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
+ 0xbff00000
+#else
+#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#endif
+#endif
+
+#if defined(CONFIG_TARGET_C29XPCIE)
+#define CONFIG_KEY_REVOCATION
+#endif
+
+#if defined(CONFIG_ARCH_P3041) || \
+ defined(CONFIG_ARCH_P4080) || \
+ defined(CONFIG_ARCH_P5020) || \
+ defined(CONFIG_ARCH_P5040) || \
+ defined(CONFIG_ARCH_P2041)
+ #define CONFIG_FSL_TRUST_ARCH_v1
+#endif
+
+#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
+/* The key used for verification of next level images
+ * is picked up from an Extension Table which has
+ * been verified by the ISBC (Internal Secure boot Code)
+ * in boot ROM of the SoC.
+ * The feature is only applicable in case of NOR boot and is
+ * not applicable in case of RAMBOOT (NAND, SD, SPI).
+ */
+#define CONFIG_FSL_ISBC_KEY_EXT
+#endif
+#endif /* #ifdef CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+#ifdef CONFIG_SPL_BUILD
+/*
+ * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
+ * due to space crunch on CPC and thus malloc will not work.
+ */
+#define CONFIG_SPL_PPAACT_ADDR 0x2e000000
+#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
+#define CONFIG_SPL_JR0_LIODN_S 454
+#define CONFIG_SPL_JR0_LIODN_NS 458
+/*
+ * Define the key hash for U-Boot here if public/private key pair used to
+ * sign U-boot are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_SPL_UBOOT_KEY_HASH \
+ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ * else leave it defined as NULL
+ */
+
+#define CONFIG_SPL_UBOOT_KEY_HASH NULL
+#endif /* ifdef CONFIG_SPL_BUILD */
+
+#define CONFIG_FSL_SEC_MON
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsl_setenv_chain_of_trust() must be called from
+ * board_late_init()
+ */
+
+/* If Boot Script is not on NOR and is required to be copied on RAM */
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
+#define CONFIG_BS_HDR_SIZE 0x00002000
+#define CONFIG_BS_ADDR_RAM 0x00012000
+#define CONFIG_BS_ADDR_DEVICE 0x00802000
+#define CONFIG_BS_SIZE 0x00001000
+
+#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
+#else
+
+/* The bootscript header address is different for B4860 because the NOR
+ * mapping is different on B4 due to reduced NOR size.
+ */
+#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
+#elif defined(CONFIG_FSL_CORENET)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
+#elif defined(CONFIG_TARGET_BSC9132QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
+#elif defined(CONFIG_TARGET_C29XPCIE)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
+#else
+#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
+#endif
+
+#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
+
+#include <config_fsl_chain_trust.h>
+#endif /* #ifndef CONFIG_SPL_BUILD */
+#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
+#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
new file mode 100644
index 0000000..ddde4f8
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+enum srds_prtcl {
+ /*
+ * Nobody will check whether the device 'NONE' has been configured,
+ * So use it to indicate if the serdes_prtcl_map has been initialized.
+ */
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ SRIO1,
+ SRIO2,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
+ SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3,
+ SGMII_FM2_DTSEC4,
+ SGMII_FM2_DTSEC5,
+ SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC10,
+ SGMII_TSEC1,
+ SGMII_TSEC2,
+ SGMII_TSEC3,
+ SGMII_TSEC4,
+ XAUI_FM1,
+ XAUI_FM2,
+ AURORA,
+ CPRI1,
+ CPRI2,
+ CPRI3,
+ CPRI4,
+ CPRI5,
+ CPRI6,
+ CPRI7,
+ CPRI8,
+ XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10,
+ XAUI_FM2_MAC9,
+ XAUI_FM2_MAC10,
+ HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10,
+ HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10,
+ QSGMII_FM1_A, /* A indicates MACs 1-4 */
+ QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
+ QSGMII_FM2_A,
+ QSGMII_FM2_B,
+ XFI_FM1_MAC1,
+ XFI_FM1_MAC2,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ XFI_FM2_MAC9,
+ XFI_FM2_MAC10,
+ INTERLAKEN,
+ QSGMII_SW1_A, /* Indicates ports on L2 Switch */
+ QSGMII_SW1_B,
+ SGMII_2500_FM1_DTSEC1,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC3,
+ SGMII_2500_FM1_DTSEC4,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC6,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SGMII_2500_FM2_DTSEC1,
+ SGMII_2500_FM2_DTSEC2,
+ SGMII_2500_FM2_DTSEC3,
+ SGMII_2500_FM2_DTSEC4,
+ SGMII_2500_FM2_DTSEC5,
+ SGMII_2500_FM2_DTSEC6,
+ SGMII_2500_FM2_DTSEC9,
+ SGMII_2500_FM2_DTSEC10,
+ SGMII_SW1_MAC1,
+ SGMII_SW1_MAC2,
+ SGMII_SW1_MAC3,
+ SGMII_SW1_MAC4,
+ SGMII_SW1_MAC5,
+ SGMII_SW1_MAC6,
+ SERDES_PRCTL_COUNT /* Keep this item the last one */
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
+ FSL_SRDS_3 = 2,
+ FSL_SRDS_4 = 3,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
+
+#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+#else
+int serdes_get_first_lane(enum srds_prtcl device);
+#endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+void serdes_reset_rx(enum srds_prtcl device);
+#endif
+#endif
+
+#endif /* __FSL_SERDES_H */
diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h
new file mode 100644
index 0000000..9429233
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_srio.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_SRIO_H_
+#define _FSL_SRIO_H_
+
+#include <linux/log2.h>
+
+enum atmu_size {
+ ATMU_SIZE_4K = 0xb,
+ ATMU_SIZE_8K,
+ ATMU_SIZE_16K,
+ ATMU_SIZE_32K,
+ ATMU_SIZE_64K,
+ ATMU_SIZE_128K,
+ ATMU_SIZE_256K,
+ ATMU_SIZE_512K,
+ ATMU_SIZE_1M,
+ ATMU_SIZE_2M,
+ ATMU_SIZE_4M,
+ ATMU_SIZE_8M,
+ ATMU_SIZE_16M,
+ ATMU_SIZE_32M,
+ ATMU_SIZE_64M,
+ ATMU_SIZE_128M,
+ ATMU_SIZE_256M,
+ ATMU_SIZE_512M,
+ ATMU_SIZE_1G,
+ ATMU_SIZE_2G,
+ ATMU_SIZE_4G,
+ ATMU_SIZE_8G,
+ ATMU_SIZE_16G,
+ ATMU_SIZE_32G,
+ ATMU_SIZE_64G,
+};
+
+#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1)
+#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1))
+
+extern void srio_init(void);
+#ifdef CONFIG_FSL_CORENET
+extern void srio_boot_master(int port);
+extern void srio_boot_master_release_slave(int port);
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
new file mode 100644
index 0000000..b6e4dd6
--- /dev/null
+++ b/arch/powerpc/include/asm/global_data.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include "config.h"
+#include "asm/types.h"
+
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+ u32 sdhc_clk;
+#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
+ u8 sdhc_adapter;
+#endif
+#endif
+#if defined(CONFIG_MPC8xx)
+ unsigned long brg_clk;
+#endif
+#if defined(CONFIG_CPM2)
+ /* There are many clocks on the MPC8260 - see page 9-5 */
+ unsigned long vco_out;
+ unsigned long cpm_clk;
+ unsigned long scc_clk;
+ unsigned long brg_clk;
+#endif
+ /* TODO: sjg@chromium.org: Should these be unslgned long? */
+#if defined(CONFIG_MPC83xx)
+#ifdef CONFIG_CLK_MPC83XX
+ u32 core_clk;
+#else
+ /* There are other clocks in the MPC83XX */
+ u32 csb_clk;
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ u32 tsec1_clk;
+ u32 tsec2_clk;
+ u32 usbdr_clk;
+# elif defined(CONFIG_ARCH_MPC8309)
+ u32 usbdr_clk;
+# endif
+# if defined(CONFIG_ARCH_MPC834X)
+ u32 usbmph_clk;
+# endif /* CONFIG_ARCH_MPC834X */
+# if defined(CONFIG_ARCH_MPC8315)
+ u32 tdm_clk;
+# endif
+ u32 core_clk;
+ u32 enc_clk;
+ u32 lbiu_clk;
+ u32 lclk_clk;
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
+ u32 pciexp1_clk;
+ u32 pciexp2_clk;
+# endif
+# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+ u32 sata_clk;
+# endif
+# if defined(CONFIG_ARCH_MPC8360)
+ u32 mem_sec_clk;
+# endif /* CONFIG_ARCH_MPC8360 */
+#endif
+#endif
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ u32 lbc_clk;
+ void *cpu;
+#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+ defined(CONFIG_MPC86xx)
+ u32 i2c1_clk;
+ u32 i2c2_clk;
+#endif
+#if defined(CONFIG_QE)
+ u32 qe_clk;
+ u32 brg_clk;
+ uint mp_alloc_base;
+ uint mp_alloc_top;
+#endif /* CONFIG_QE */
+#if defined(CONFIG_FSL_LAW)
+ u32 used_laws;
+#endif
+#if defined(CONFIG_E500)
+ u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
+#endif
+ unsigned long reset_status; /* reset status register at boot */
+#if defined(CONFIG_MPC83xx)
+ unsigned long arbiter_event_attributes;
+ unsigned long arbiter_event_address;
+#endif
+#if defined(CONFIG_CPM2)
+ unsigned int dp_alloc_base;
+ unsigned int dp_alloc_top;
+#endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+ unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long wdt_last; /* trace watch-dog triggering rate */
+#endif
+#if defined(CONFIG_LWMON5)
+ unsigned long kbd_status;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#if 1
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
+#else /* We could use plain global data, but the resulting code is bigger */
+#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
+#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
+ gd_t *gd
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
new file mode 100644
index 0000000..d49ad08
--- /dev/null
+++ b/arch/powerpc/include/asm/gpio.h
@@ -0,0 +1,2 @@
+#include <asm/arch/gpio.h>
+#include <asm-generic/gpio.h>
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
new file mode 100644
index 0000000..d02da64
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -0,0 +1,996 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc.
+ *
+ * MPC83xx Internal Memory Map
+ *
+ * Contributors:
+ * Dave Liu <daveliu@freescale.com>
+ * Tanya Jiang <tanya.jiang@freescale.com>
+ * Mandy Lavi <mandy.lavi@freescale.com>
+ * Eran Liberty <liberty@freescale.com>
+ */
+#ifndef __IMMAP_83xx__
+#define __IMMAP_83xx__
+
+#include <fsl_immap.h>
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+#include <asm/mpc8xxx_spi.h>
+#include <asm/fsl_lbc.h>
+#include <asm/fsl_dma.h>
+
+/*
+ * Local Access Window
+ */
+typedef struct law83xx {
+ u32 bar; /* LBIU local access window base address register */
+ u32 ar; /* LBIU local access window attribute register */
+} law83xx_t;
+
+/*
+ * System configuration registers
+ */
+typedef struct sysconf83xx {
+ u32 immrbar; /* Internal memory map base address register */
+ u8 res0[0x04];
+ u32 altcbar; /* Alternate configuration base address register */
+ u8 res1[0x14];
+ law83xx_t lblaw[4]; /* LBIU local access window */
+ u8 res2[0x20];
+ law83xx_t pcilaw[2]; /* PCI local access window */
+ u8 res3[0x10];
+ law83xx_t pcielaw[2]; /* PCI Express local access window */
+ u8 res4[0x10];
+ law83xx_t ddrlaw[2]; /* DDR local access window */
+ u8 res5[0x50];
+ u32 sgprl; /* System General Purpose Register Low */
+ u32 sgprh; /* System General Purpose Register High */
+ u32 spridr; /* System Part and Revision ID Register */
+ u8 res6[0x04];
+ u32 spcr; /* System Priority Configuration Register */
+ u32 sicrl; /* System I/O Configuration Register Low */
+ u32 sicrh; /* System I/O Configuration Register High */
+ u8 res7[0x04];
+ u32 sidcr0; /* System I/O Delay Configuration Register 0 */
+ u32 sidcr1; /* System I/O Delay Configuration Register 1 */
+ u32 ddrcdr; /* DDR Control Driver Register */
+ u32 ddrdsr; /* DDR Debug Status Register */
+ u32 obir; /* Output Buffer Impedance Register */
+ u8 res8[0xC];
+ u32 pecr1; /* PCI Express control register 1 */
+#if defined(CONFIG_ARCH_MPC830X)
+ u32 sdhccr; /* eSDHC Control Registers for MPC830x */
+#else
+ u32 pecr2; /* PCI Express control register 2 */
+#endif
+#if defined(CONFIG_ARCH_MPC8309)
+ u32 can_dbg_ctrl;
+ u32 res9a;
+ u32 gpr1;
+ u8 res9b[0xAC];
+#else
+ u8 res9[0xB8];
+#endif
+} sysconf83xx_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt83xx {
+ u8 res0[4];
+ u32 swcrr; /* System watchdog control register */
+ u32 swcnr; /* System watchdog count register */
+ u8 res1[2];
+ u16 swsrr; /* System watchdog service register */
+ u8 res2[0xF0];
+} wdt83xx_t;
+
+/*
+ * RTC/PIT Module Registers
+ */
+typedef struct rtclk83xx {
+ u32 cnr; /* control register */
+ u32 ldr; /* load register */
+ u32 psr; /* prescale register */
+ u32 ctr; /* counter value field register */
+ u32 evr; /* event register */
+ u32 alr; /* alarm register */
+ u8 res0[0xE8];
+} rtclk83xx_t;
+
+/*
+ * Global timer module
+ */
+typedef struct gtm83xx {
+ u8 cfr1; /* Timer1/2 Configuration */
+ u8 res0[3];
+ u8 cfr2; /* Timer3/4 Configuration */
+ u8 res1[11];
+ u16 mdr1; /* Timer1 Mode Register */
+ u16 mdr2; /* Timer2 Mode Register */
+ u16 rfr1; /* Timer1 Reference Register */
+ u16 rfr2; /* Timer2 Reference Register */
+ u16 cpr1; /* Timer1 Capture Register */
+ u16 cpr2; /* Timer2 Capture Register */
+ u16 cnr1; /* Timer1 Counter Register */
+ u16 cnr2; /* Timer2 Counter Register */
+ u16 mdr3; /* Timer3 Mode Register */
+ u16 mdr4; /* Timer4 Mode Register */
+ u16 rfr3; /* Timer3 Reference Register */
+ u16 rfr4; /* Timer4 Reference Register */
+ u16 cpr3; /* Timer3 Capture Register */
+ u16 cpr4; /* Timer4 Capture Register */
+ u16 cnr3; /* Timer3 Counter Register */
+ u16 cnr4; /* Timer4 Counter Register */
+ u16 evr1; /* Timer1 Event Register */
+ u16 evr2; /* Timer2 Event Register */
+ u16 evr3; /* Timer3 Event Register */
+ u16 evr4; /* Timer4 Event Register */
+ u16 psr1; /* Timer1 Prescaler Register */
+ u16 psr2; /* Timer2 Prescaler Register */
+ u16 psr3; /* Timer3 Prescaler Register */
+ u16 psr4; /* Timer4 Prescaler Register */
+ u8 res[0xC0];
+} gtm83xx_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic83xx {
+ u32 sicfr; /* System Global Interrupt Configuration Register */
+ u32 sivcr; /* System Global Interrupt Vector Register */
+ u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
+ u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
+ u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
+ u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
+ u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
+ u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
+ u32 simsr_h; /* System Internal Interrupt Mask Register - High */
+ u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
+ u32 sicnr; /* System Internal Interrupt Control Register */
+ u32 sepnr; /* System External Interrupt Pending Register */
+ u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
+ u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
+ u32 semsr; /* System External Interrupt Mask Register */
+ u32 secnr; /* System External Interrupt Control Register */
+ u32 sersr; /* System Error Status Register */
+ u32 sermr; /* System Error Mask Register */
+ u32 sercr; /* System Error Control Register */
+ u32 sepcr; /* System External Interrupt Polarity Control Register */
+ u32 sifcr_h; /* System Internal Interrupt Force Register - High */
+ u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
+ u32 sefcr; /* System External Interrupt Force Register */
+ u32 serfr; /* System Error Force Register */
+ u32 scvcr; /* System Critical Interrupt Vector Register */
+ u32 smvcr; /* System Management Interrupt Vector Register */
+ u8 res[0x98];
+} ipic83xx_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter83xx {
+ u32 acr; /* Arbiter Configuration Register */
+ u32 atr; /* Arbiter Timers Register */
+ u8 res[4];
+ u32 aer; /* Arbiter Event Register */
+ u32 aidr; /* Arbiter Interrupt Definition Register */
+ u32 amr; /* Arbiter Mask Register */
+ u32 aeatr; /* Arbiter Event Attributes Register */
+ u32 aeadr; /* Arbiter Event Address Register */
+ u32 aerr; /* Arbiter Event Response Register */
+ u8 res1[0xDC];
+} arbiter83xx_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset83xx {
+ u32 rcwl; /* Reset Configuration Word Low Register */
+ u32 rcwh; /* Reset Configuration Word High Register */
+ u8 res0[8];
+ u32 rsr; /* Reset Status Register */
+ u32 rmr; /* Reset Mode Register */
+ u32 rpr; /* Reset protection Register */
+ u32 rcr; /* Reset Control Register */
+ u32 rcer; /* Reset Control Enable Register */
+ u8 res1[0xDC];
+} reset83xx_t;
+
+/*
+ * Clock Module
+ */
+typedef struct clk83xx {
+ u32 spmr; /* system PLL mode Register */
+ u32 occr; /* output clock control Register */
+ u32 sccr; /* system clock control Register */
+ u8 res0[0xF4];
+} clk83xx_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc83xx {
+ u32 pmccr; /* PMC Configuration Register */
+ u32 pmcer; /* PMC Event Register */
+ u32 pmcmr; /* PMC Mask Register */
+ u32 pmccr1; /* PMC Configuration Register 1 */
+ u32 pmccr2; /* PMC Configuration Register 2 */
+ u8 res0[0xEC];
+} pmc83xx_t;
+
+/*
+ * General purpose I/O module
+ */
+typedef struct gpio83xx {
+ u32 dir; /* direction register */
+ u32 odr; /* open drain register */
+ u32 dat; /* data register */
+ u32 ier; /* interrupt event register */
+ u32 imr; /* interrupt mask register */
+ u32 icr; /* external interrupt control register */
+ u8 res0[0xE8];
+} gpio83xx_t;
+
+/*
+ * QE Ports Interrupts Registers
+ */
+typedef struct qepi83xx {
+ u8 res0[0xC];
+ u32 qepier; /* QE Ports Interrupt Event Register */
+ u32 qepimr; /* QE Ports Interrupt Mask Register */
+ u32 qepicr; /* QE Ports Interrupt Control Register */
+ u8 res1[0xE8];
+} qepi83xx_t;
+
+/*
+ * QE Parallel I/O Ports
+ */
+typedef struct gpio_n {
+ u32 podr; /* Open Drain Register */
+ u32 pdat; /* Data Register */
+ u32 dir1; /* direction register 1 */
+ u32 dir2; /* direction register 2 */
+ u32 ppar1; /* Pin Assignment Register 1 */
+ u32 ppar2; /* Pin Assignment Register 2 */
+} gpio_n_t;
+
+typedef struct qegpio83xx {
+ gpio_n_t ioport[0x7];
+ u8 res0[0x358];
+} qepio83xx_t;
+
+/*
+ * QE Secondary Bus Access Windows
+ */
+typedef struct qesba83xx {
+ u32 lbmcsar; /* Local bus memory controller start address */
+ u32 sdmcsar; /* Secondary DDR memory controller start address */
+ u8 res0[0x38];
+ u32 lbmcear; /* Local bus memory controller end address */
+ u32 sdmcear; /* Secondary DDR memory controller end address */
+ u8 res1[0x38];
+ u32 lbmcar; /* Local bus memory controller attributes */
+ u32 sdmcar; /* Secondary DDR memory controller attributes */
+ u8 res2[0x378];
+} qesba83xx_t;
+
+/*
+ * DDR Memory Controller Memory Map for DDR1
+ * The structure of DDR2, or DDR3 is defined in fsl_immap.h
+ */
+#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
+typedef struct ddr_cs_bnds {
+ u32 csbnds;
+ u8 res0[4];
+} ddr_cs_bnds_t;
+
+typedef struct ddr83xx {
+ ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
+ u8 res0[0x60];
+ u32 cs_config[4]; /* Chip Select x Configuration */
+ u8 res1[0x70];
+ u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ u32 sdram_cfg; /* SDRAM Control Configuration */
+ u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
+ u32 sdram_mode; /* SDRAM Mode Configuration */
+ u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
+ u32 sdram_md_cntl; /* SDRAM Mode Control */
+ u32 sdram_interval; /* SDRAM Interval Configuration */
+ u32 ddr_data_init; /* SDRAM Data Initialization */
+ u8 res2[4];
+ u32 sdram_clk_cntl; /* SDRAM Clock Control */
+ u8 res3[0x14];
+ u32 ddr_init_addr; /* DDR training initialization address */
+ u32 ddr_init_ext_addr; /* DDR training initialization extended address */
+ u8 res4[0xAA8];
+ u32 ddr_ip_rev1; /* DDR IP block revision 1 */
+ u32 ddr_ip_rev2; /* DDR IP block revision 2 */
+ u8 res5[0x200];
+ u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
+ u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
+ u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
+ u8 res6[0x14];
+ u32 capture_data_hi; /* Memory Data Path Read Capture High */
+ u32 capture_data_lo; /* Memory Data Path Read Capture Low */
+ u32 capture_ecc; /* Memory Data Path Read Capture ECC */
+ u8 res7[0x14];
+ u32 err_detect; /* Memory Error Detect */
+ u32 err_disable; /* Memory Error Disable */
+ u32 err_int_en; /* Memory Error Interrupt Enable */
+ u32 capture_attributes; /* Memory Error Attributes Capture */
+ u32 capture_address; /* Memory Error Address Capture */
+ u32 capture_ext_address;/* Memory Error Extended Address Capture */
+ u32 err_sbe; /* Memory Single-Bit ECC Error Management */
+ u8 res8[0xA4];
+ u32 debug_reg;
+ u8 res9[0xFC];
+} ddr83xx_t;
+#endif
+
+/*
+ * DUART
+ */
+typedef struct duart83xx {
+ u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
+ u8 uier_udmb; /* combined register for UIER and UDMB */
+ u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
+ u8 ulcr; /* line control register */
+ u8 umcr; /* MODEM control register */
+ u8 ulsr; /* line status register */
+ u8 umsr; /* MODEM status register */
+ u8 uscr; /* scratch register */
+ u8 res0[8];
+ u8 udsr; /* DMA status register */
+ u8 res1[3];
+ u8 res2[0xEC];
+} duart83xx_t;
+
+/*
+ * DMA/Messaging Unit
+ */
+typedef struct dma83xx {
+ u32 res0[0xC]; /* 0x0-0x29 reseverd */
+ u32 omisr; /* 0x30 Outbound message interrupt status register */
+ u32 omimr; /* 0x34 Outbound message interrupt mask register */
+ u32 res1[0x6]; /* 0x38-0x49 reserved */
+ u32 imr0; /* 0x50 Inbound message register 0 */
+ u32 imr1; /* 0x54 Inbound message register 1 */
+ u32 omr0; /* 0x58 Outbound message register 0 */
+ u32 omr1; /* 0x5C Outbound message register 1 */
+ u32 odr; /* 0x60 Outbound doorbell register */
+ u32 res2; /* 0x64-0x67 reserved */
+ u32 idr; /* 0x68 Inbound doorbell register */
+ u32 res3[0x5]; /* 0x6C-0x79 reserved */
+ u32 imisr; /* 0x80 Inbound message interrupt status register */
+ u32 imimr; /* 0x84 Inbound message interrupt mask register */
+ u32 res4[0x1E]; /* 0x88-0x99 reserved */
+ struct fsl_dma dma[4];
+} dma83xx_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf83xx {
+ u32 config_address;
+ u32 config_data;
+ u32 int_ack;
+ u8 res[116];
+} pciconf83xx_t;
+
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+ u32 potar;
+ u8 res0[4];
+ u32 pobar;
+ u8 res1[4];
+ u32 pocmr;
+ u8 res2[4];
+} pot83xx_t;
+
+/*
+ * Sequencer
+ */
+typedef struct ios83xx {
+ pot83xx_t pot[6];
+ u8 res0[0x60];
+ u32 pmcr;
+ u8 res1[4];
+ u32 dtcr;
+ u8 res2[4];
+} ios83xx_t;
+
+/*
+ * PCI Controller Control and Status Registers
+ */
+typedef struct pcictrl83xx {
+ u32 esr;
+ u32 ecdr;
+ u32 eer;
+ u32 eatcr;
+ u32 eacr;
+ u32 eeacr;
+ u32 edlcr;
+ u32 edhcr;
+ u32 gcr;
+ u32 ecr;
+ u32 gsr;
+ u8 res0[12];
+ u32 pitar2;
+ u8 res1[4];
+ u32 pibar2;
+ u32 piebar2;
+ u32 piwar2;
+ u8 res2[4];
+ u32 pitar1;
+ u8 res3[4];
+ u32 pibar1;
+ u32 piebar1;
+ u32 piwar1;
+ u8 res4[4];
+ u32 pitar0;
+ u8 res5[4];
+ u32 pibar0;
+ u8 res6[4];
+ u32 piwar0;
+ u8 res7[132];
+} pcictrl83xx_t;
+
+/*
+ * USB
+ */
+typedef struct usb83xx {
+ u8 fixme[0x1000];
+} usb83xx_t;
+
+/*
+ * TSEC
+ */
+typedef struct tsec83xx {
+ u8 fixme[0x1000];
+} tsec83xx_t;
+
+/*
+ * Security
+ */
+typedef struct security83xx {
+ u8 fixme[0x10000];
+} security83xx_t;
+
+/*
+ * PCI Express
+ */
+struct pex_inbound_window {
+ u32 ar;
+ u32 tar;
+ u32 barl;
+ u32 barh;
+};
+
+struct pex_outbound_window {
+ u32 ar;
+ u32 bar;
+ u32 tarl;
+ u32 tarh;
+};
+
+struct pex_csb_bridge {
+ u32 pex_csb_ver;
+ u32 pex_csb_cab;
+ u32 pex_csb_ctrl;
+ u8 res0[8];
+ u32 pex_dms_dstmr;
+ u8 res1[4];
+ u32 pex_cbs_stat;
+ u8 res2[0x20];
+ u32 pex_csb_obctrl;
+ u32 pex_csb_obstat;
+ u8 res3[0x98];
+ u32 pex_csb_ibctrl;
+ u32 pex_csb_ibstat;
+ u8 res4[0xb8];
+ u32 pex_wdma_ctrl;
+ u32 pex_wdma_addr;
+ u32 pex_wdma_stat;
+ u8 res5[0x94];
+ u32 pex_rdma_ctrl;
+ u32 pex_rdma_addr;
+ u32 pex_rdma_stat;
+ u8 res6[0xd4];
+ u32 pex_ombcr;
+ u32 pex_ombdr;
+ u8 res7[0x38];
+ u32 pex_imbcr;
+ u32 pex_imbdr;
+ u8 res8[0x38];
+ u32 pex_int_enb;
+ u32 pex_int_stat;
+ u32 pex_int_apio_vec1;
+ u32 pex_int_apio_vec2;
+ u8 res9[0x10];
+ u32 pex_int_ppio_vec1;
+ u32 pex_int_ppio_vec2;
+ u32 pex_int_wdma_vec1;
+ u32 pex_int_wdma_vec2;
+ u32 pex_int_rdma_vec1;
+ u32 pex_int_rdma_vec2;
+ u32 pex_int_misc_vec;
+ u8 res10[4];
+ u32 pex_int_axi_pio_enb;
+ u32 pex_int_axi_wdma_enb;
+ u32 pex_int_axi_rdma_enb;
+ u32 pex_int_axi_misc_enb;
+ u32 pex_int_axi_pio_stat;
+ u32 pex_int_axi_wdma_stat;
+ u32 pex_int_axi_rdma_stat;
+ u32 pex_int_axi_misc_stat;
+ u8 res11[0xa0];
+ struct pex_outbound_window pex_outbound_win[4];
+ u8 res12[0x100];
+ u32 pex_epiwtar0;
+ u32 pex_epiwtar1;
+ u32 pex_epiwtar2;
+ u32 pex_epiwtar3;
+ u8 res13[0x70];
+ struct pex_inbound_window pex_inbound_win[4];
+};
+
+typedef struct pex83xx {
+ u8 pex_cfg_header[0x404];
+ u32 pex_ltssm_stat;
+ u8 res0[0x30];
+ u32 pex_ack_replay_timeout;
+ u8 res1[4];
+ u32 pex_gclk_ratio;
+ u8 res2[0xc];
+ u32 pex_pm_timer;
+ u32 pex_pme_timeout;
+ u8 res3[4];
+ u32 pex_aspm_req_timer;
+ u8 res4[0x18];
+ u32 pex_ssvid_update;
+ u8 res5[0x34];
+ u32 pex_cfg_ready;
+ u8 res6[0x24];
+ u32 pex_bar_sizel;
+ u8 res7[4];
+ u32 pex_bar_sel;
+ u8 res8[0x20];
+ u32 pex_bar_pf;
+ u8 res9[0x88];
+ u32 pex_pme_to_ack_tor;
+ u8 res10[0xc];
+ u32 pex_ss_intr_mask;
+ u8 res11[0x25c];
+ struct pex_csb_bridge bridge;
+ u8 res12[0x160];
+} pex83xx_t;
+
+/*
+ * SATA
+ */
+typedef struct sata83xx {
+ u8 fixme[0x1000];
+} sata83xx_t;
+
+/*
+ * eSDHC
+ */
+typedef struct sdhc83xx {
+ u8 fixme[0x1000];
+} sdhc83xx_t;
+
+/*
+ * SerDes
+ */
+typedef struct serdes83xx {
+ u32 srdscr0;
+ u32 srdscr1;
+ u32 srdscr2;
+ u32 srdscr3;
+ u32 srdscr4;
+ u8 res0[0xc];
+ u32 srdsrstctl;
+ u8 res1[0xdc];
+} serdes83xx_t;
+
+/*
+ * On Chip ROM
+ */
+typedef struct rom83xx {
+#if defined(CONFIG_ARCH_MPC8309)
+ u8 mem[0x8000];
+#else
+ u8 mem[0x10000];
+#endif
+} rom83xx_t;
+
+/*
+ * TDM
+ */
+typedef struct tdm83xx {
+ u8 fixme[0x200];
+} tdm83xx_t;
+
+/*
+ * TDM DMAC
+ */
+typedef struct tdmdmac83xx {
+ u8 fixme[0x2000];
+} tdmdmac83xx_t;
+
+#if defined(CONFIG_ARCH_MPC834X)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x200];
+ u8 dll_ddr[0x100];
+ u8 dll_lbc[0x100];
+ u8 res1[0xE00];
+#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
+ struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
+#else
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+#endif
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res4[0x1000];
+ spi8xxx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
+ u8 res5[0x19900];
+ usb83xx_t usb[2];
+ tsec83xx_t tsec[2];
+ u8 res6[0xA000];
+ security83xx_t security;
+ u8 res7[0xC0000];
+} immap_t;
+
+#ifndef CONFIG_ARCH_MPC834X
+#ifdef CONFIG_HAS_FSL_MPH_USB
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
+#else
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
+#endif
+#else
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
+#endif
+
+#elif defined(CONFIG_ARCH_MPC8313)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[1]; /* General purpose I/O module */
+ u8 res0[0x1300];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res1[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res2[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res3[0x1000];
+ spi8xxx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res4[0x80];
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res5[0x1aa00];
+ usb83xx_t usb[1];
+ tsec83xx_t tsec[2];
+ u8 res6[0xA000];
+ security83xx_t security;
+ u8 res7[0xC0000];
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC8315)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[1]; /* General purpose I/O module */
+ u8 res0[0x1300];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[1]; /* I2C Controllers */
+ u8 res1[0x1400];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res2[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res3[0x1000];
+ spi8xxx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res4[0x80];
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res5[0xa00];
+ pex83xx_t pciexp[2]; /* PCI Express Controller */
+ u8 res6[0xb000];
+ tdm83xx_t tdm; /* TDM Controller */
+ u8 res7[0x1e00];
+ sata83xx_t sata[2]; /* SATA Controller */
+ u8 res8[0x9000];
+ usb83xx_t usb[1]; /* USB DR Controller */
+ tsec83xx_t tsec[2];
+ u8 res9[0x6000];
+ tdmdmac83xx_t tdmdmac; /* TDM DMAC */
+ u8 res10[0x2000];
+ security83xx_t security;
+ u8 res11[0xA3000];
+ serdes83xx_t serdes[1]; /* SerDes Registers */
+ u8 res12[0x1CF00];
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC8308)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[1]; /* Global Timers Module */
+ u8 res0[0x100];
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[1]; /* General purpose I/O module */
+ u8 res1[0x1300];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res4[0x1000];
+ spi8xxx_t spi; /* Serial Peripheral Interface */
+ u8 res5[0x1000];
+ pex83xx_t pciexp[1]; /* PCI Express Controller */
+ u8 res6[0x19000];
+ usb83xx_t usb[1]; /* USB DR Controller */
+ tsec83xx_t tsec[2];
+ u8 res7[0x6000];
+ tdmdmac83xx_t tdmdmac; /* TDM DMAC */
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res8[0xb4000];
+ serdes83xx_t serdes[1]; /* SerDes Registers */
+ u8 res9[0x1CF00];
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC837X)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x1200];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res1[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res2[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res3[0x1000];
+ spi8xxx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res4[0x80];
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res5[0xa00];
+ pex83xx_t pciexp[2]; /* PCI Express Controller */
+ u8 res6[0xd000];
+ sata83xx_t sata[4]; /* SATA Controller */
+ u8 res7[0x7000];
+ usb83xx_t usb[1]; /* USB DR Controller */
+ tsec83xx_t tsec[2];
+ u8 res8[0x8000];
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res9[0x1000];
+ security83xx_t security;
+ u8 res10[0xA3000];
+ serdes83xx_t serdes[2]; /* SerDes Registers */
+ u8 res11[0xCE00];
+ rom83xx_t rom; /* On Chip ROM */
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC8360)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ u8 res0[0x200];
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ u8 res1[0x300];
+ u8 dll_ddr[0x100];
+ u8 dll_lbc[0x100];
+ u8 res2[0x200];
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
+ u8 res3[0x400];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res4[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res5[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res6[0x2000];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res7[128];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res8[0x4A00];
+ ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
+ u8 res9[0x22000];
+ security83xx_t security;
+ u8 res10[0xC0000];
+ u8 qe[0x100000]; /* QE block */
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC832X)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ u8 res0[0x300];
+ u8 dll_ddr[0x100];
+ u8 dll_lbc[0x100];
+ u8 res1[0x200];
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ u8 res2[0x800];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res3[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res4[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res5[0x2000];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res6[128];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res7[0x27A00];
+ security83xx_t security;
+ u8 res8[0xC0000];
+ u8 qe[0x100000]; /* QE block */
+} immap_t;
+#elif defined(CONFIG_ARCH_MPC8309)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ u8 res1[0x800];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x200];
+ duart83xx_t duart1[2]; /* DUART */
+ u8 res4[0x500];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res5[0x1000];
+ u8 spi[0x100];
+ u8 res6[0xf00];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
+ u8 res7[0x80];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
+ u8 res8[0x13A00];
+ u8 can1[0x1000]; /* Flexcan 1 */
+ u8 can2[0x1000]; /* Flexcan 2 */
+ u8 res9[0x5000];
+ usb83xx_t usb;
+ u8 res10[0x5000];
+ u8 can3[0x1000]; /* Flexcan 3 */
+ u8 can4[0x1000]; /* Flexcan 4 */
+ u8 res11[0x1000];
+ u8 dma1[0x2000]; /* DMA */
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res12[0xC1000];
+ rom83xx_t rom; /* On Chip ROM */
+ u8 res13[0x8000];
+ u8 qe[0x100000]; /* QE block */
+ u8 res14[0xE00000];/* Added for 8309 */
+} immap_t;
+#endif
+
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
+#define CONFIG_SYS_FSL_DDR_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
+#define CONFIG_SYS_MPC83xx_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
+#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+
+#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000
+#endif
+#define CONFIG_SYS_MPC83xx_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
+#if defined(CONFIG_ARCH_MPC834X)
+#define CONFIG_SYS_MPC83xx_USB2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
+#endif
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
+
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#endif /* __IMMAP_83xx__ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
new file mode 100644
index 0000000..bfa601e
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -0,0 +1,3141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * Copyright(c) 2002,2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ */
+
+#ifndef __IMMAP_85xx__
+#define __IMMAP_85xx__
+
+#include <asm/types.h>
+#include <asm/fsl_dma.h>
+#include <asm/fsl_i2c.h>
+#include <fsl_ifc.h>
+#include <fsl_sec.h>
+#include <fsl_sfp.h>
+#include <asm/fsl_lbc.h>
+#include <fsl_fman.h>
+#include <fsl_immap.h>
+
+typedef struct ccsr_local {
+ u32 ccsrbarh; /* CCSR Base Addr High */
+ u32 ccsrbarl; /* CCSR Base Addr Low */
+ u32 ccsrar; /* CCSR Attr */
+#define CCSRAR_C 0x80000000 /* Commit */
+ u8 res1[4];
+ u32 altcbarh; /* Alternate Configuration Base Addr High */
+ u32 altcbarl; /* Alternate Configuration Base Addr Low */
+ u32 altcar; /* Alternate Configuration Attr */
+ u8 res2[4];
+ u32 bstrh; /* Boot space translation high */
+ u32 bstrl; /* Boot space translation Low */
+ u32 bstrar; /* Boot space translation attributes */
+ u8 res3[0xbd4];
+ struct {
+ u32 lawbarh; /* LAWn base addr high */
+ u32 lawbarl; /* LAWn base addr low */
+ u32 lawar; /* LAWn attributes */
+ u8 res4[4];
+ } law[32];
+ u8 res35[0x204];
+} ccsr_local_t;
+
+/* Local-Access Registers & ECM Registers */
+typedef struct ccsr_local_ecm {
+ u32 ccsrbar; /* CCSR Base Addr */
+ u8 res1[4];
+ u32 altcbar; /* Alternate Configuration Base Addr */
+ u8 res2[4];
+ u32 altcar; /* Alternate Configuration Attr */
+ u8 res3[12];
+ u32 bptr; /* Boot Page Translation */
+ u8 res4[3044];
+ u32 lawbar0; /* Local Access Window 0 Base Addr */
+ u8 res5[4];
+ u32 lawar0; /* Local Access Window 0 Attrs */
+ u8 res6[20];
+ u32 lawbar1; /* Local Access Window 1 Base Addr */
+ u8 res7[4];
+ u32 lawar1; /* Local Access Window 1 Attrs */
+ u8 res8[20];
+ u32 lawbar2; /* Local Access Window 2 Base Addr */
+ u8 res9[4];
+ u32 lawar2; /* Local Access Window 2 Attrs */
+ u8 res10[20];
+ u32 lawbar3; /* Local Access Window 3 Base Addr */
+ u8 res11[4];
+ u32 lawar3; /* Local Access Window 3 Attrs */
+ u8 res12[20];
+ u32 lawbar4; /* Local Access Window 4 Base Addr */
+ u8 res13[4];
+ u32 lawar4; /* Local Access Window 4 Attrs */
+ u8 res14[20];
+ u32 lawbar5; /* Local Access Window 5 Base Addr */
+ u8 res15[4];
+ u32 lawar5; /* Local Access Window 5 Attrs */
+ u8 res16[20];
+ u32 lawbar6; /* Local Access Window 6 Base Addr */
+ u8 res17[4];
+ u32 lawar6; /* Local Access Window 6 Attrs */
+ u8 res18[20];
+ u32 lawbar7; /* Local Access Window 7 Base Addr */
+ u8 res19[4];
+ u32 lawar7; /* Local Access Window 7 Attrs */
+ u8 res19_8a[20];
+ u32 lawbar8; /* Local Access Window 8 Base Addr */
+ u8 res19_8b[4];
+ u32 lawar8; /* Local Access Window 8 Attrs */
+ u8 res19_9a[20];
+ u32 lawbar9; /* Local Access Window 9 Base Addr */
+ u8 res19_9b[4];
+ u32 lawar9; /* Local Access Window 9 Attrs */
+ u8 res19_10a[20];
+ u32 lawbar10; /* Local Access Window 10 Base Addr */
+ u8 res19_10b[4];
+ u32 lawar10; /* Local Access Window 10 Attrs */
+ u8 res19_11a[20];
+ u32 lawbar11; /* Local Access Window 11 Base Addr */
+ u8 res19_11b[4];
+ u32 lawar11; /* Local Access Window 11 Attrs */
+ u8 res20[652];
+ u32 eebacr; /* ECM CCB Addr Configuration */
+ u8 res21[12];
+ u32 eebpcr; /* ECM CCB Port Configuration */
+ u8 res22[3564];
+ u32 eedr; /* ECM Error Detect */
+ u8 res23[4];
+ u32 eeer; /* ECM Error Enable */
+ u32 eeatr; /* ECM Error Attrs Capture */
+ u32 eeadr; /* ECM Error Addr Capture */
+ u8 res24[492];
+} ccsr_local_ecm_t;
+
+#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
+#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
+
+/* I2C Registers */
+typedef struct ccsr_i2c {
+ struct fsl_i2c_base i2c[1];
+ u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
+} ccsr_i2c_t;
+
+#if defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8548) || \
+ defined(CONFIG_ARCH_MPC8555)
+/* DUART Registers */
+typedef struct ccsr_duart {
+ u8 res1[1280];
+/* URBR1, UTHR1, UDLB1 with the same addr */
+ u8 urbr1_uthr1_udlb1;
+/* UIER1, UDMB1 with the same addr01 */
+ u8 uier1_udmb1;
+/* UIIR1, UFCR1, UAFR1 with the same addr */
+ u8 uiir1_ufcr1_uafr1;
+ u8 ulcr1; /* UART1 Line Control */
+ u8 umcr1; /* UART1 Modem Control */
+ u8 ulsr1; /* UART1 Line Status */
+ u8 umsr1; /* UART1 Modem Status */
+ u8 uscr1; /* UART1 Scratch */
+ u8 res2[8];
+ u8 udsr1; /* UART1 DMA Status */
+ u8 res3[239];
+/* URBR2, UTHR2, UDLB2 with the same addr */
+ u8 urbr2_uthr2_udlb2;
+/* UIER2, UDMB2 with the same addr */
+ u8 uier2_udmb2;
+/* UIIR2, UFCR2, UAFR2 with the same addr */
+ u8 uiir2_ufcr2_uafr2;
+ u8 ulcr2; /* UART2 Line Control */
+ u8 umcr2; /* UART2 Modem Control */
+ u8 ulsr2; /* UART2 Line Status */
+ u8 umsr2; /* UART2 Modem Status */
+ u8 uscr2; /* UART2 Scratch */
+ u8 res4[8];
+ u8 udsr2; /* UART2 DMA Status */
+ u8 res5[2543];
+} ccsr_duart_t;
+#else /* MPC8560 uses UART on its CPM */
+typedef struct ccsr_duart {
+ u8 res[4096];
+} ccsr_duart_t;
+#endif
+
+/* eSPI Registers */
+typedef struct ccsr_espi {
+ u32 mode; /* eSPI mode */
+ u32 event; /* eSPI event */
+ u32 mask; /* eSPI mask */
+ u32 com; /* eSPI command */
+ u32 tx; /* eSPI transmit FIFO access */
+ u32 rx; /* eSPI receive FIFO access */
+ u8 res1[8]; /* reserved */
+ u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
+ u8 res2[4048]; /* fill up to 0x1000 */
+} ccsr_espi_t;
+
+/* PCI Registers */
+typedef struct ccsr_pcix {
+ u32 cfg_addr; /* PCIX Configuration Addr */
+ u32 cfg_data; /* PCIX Configuration Data */
+ u32 int_ack; /* PCIX IRQ Acknowledge */
+ u8 res000c[52];
+ u32 liodn_base; /* PCIX LIODN base register */
+ u8 res0044[2996];
+ u32 ipver1; /* PCIX IP block revision register 1 */
+ u32 ipver2; /* PCIX IP block revision register 2 */
+ u32 potar0; /* PCIX Outbound Transaction Addr 0 */
+ u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
+ u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
+ u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
+ u32 powar0; /* PCIX Outbound Window Attrs 0 */
+ u8 res2[12];
+ u32 potar1; /* PCIX Outbound Transaction Addr 1 */
+ u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
+ u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
+ u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
+ u32 powar1; /* PCIX Outbound Window Attrs 1 */
+ u8 res3[12];
+ u32 potar2; /* PCIX Outbound Transaction Addr 2 */
+ u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
+ u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
+ u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
+ u32 powar2; /* PCIX Outbound Window Attrs 2 */
+ u8 res4[12];
+ u32 potar3; /* PCIX Outbound Transaction Addr 3 */
+ u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
+ u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
+ u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
+ u32 powar3; /* PCIX Outbound Window Attrs 3 */
+ u8 res5[12];
+ u32 potar4; /* PCIX Outbound Transaction Addr 4 */
+ u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
+ u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
+ u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
+ u32 powar4; /* PCIX Outbound Window Attrs 4 */
+ u8 res6[268];
+ u32 pitar3; /* PCIX Inbound Translation Addr 3 */
+ u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
+ u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
+ u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
+ u32 piwar3; /* PCIX Inbound Window Attrs 3 */
+ u8 res7[12];
+ u32 pitar2; /* PCIX Inbound Translation Addr 2 */
+ u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
+ u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
+ u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
+ u32 piwar2; /* PCIX Inbound Window Attrs 2 */
+ u8 res8[12];
+ u32 pitar1; /* PCIX Inbound Translation Addr 1 */
+ u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
+ u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
+ u8 res9[4];
+ u32 piwar1; /* PCIX Inbound Window Attrs 1 */
+ u8 res10[12];
+ u32 pedr; /* PCIX Error Detect */
+ u32 pecdr; /* PCIX Error Capture Disable */
+ u32 peer; /* PCIX Error Enable */
+ u32 peattrcr; /* PCIX Error Attrs Capture */
+ u32 peaddrcr; /* PCIX Error Addr Capture */
+ u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
+ u32 pedlcr; /* PCIX Error Data Low Capture */
+ u32 pedhcr; /* PCIX Error Error Data High Capture */
+ u32 gas_timr; /* PCIX Gasket Timer */
+ u8 res11[476];
+} ccsr_pcix_t;
+
+#define PCIX_COMMAND 0x62
+#define POWAR_EN 0x80000000
+#define POWAR_IO_READ 0x00080000
+#define POWAR_MEM_READ 0x00040000
+#define POWAR_IO_WRITE 0x00008000
+#define POWAR_MEM_WRITE 0x00004000
+#define POWAR_MEM_512M 0x0000001c
+#define POWAR_IO_1M 0x00000013
+
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_LOCAL 0x00f00000
+#define PIWAR_READ_SNOOP 0x00050000
+#define PIWAR_WRITE_SNOOP 0x00005000
+#define PIWAR_MEM_2G 0x0000001e
+
+#ifndef CONFIG_MPC85XX_GPIO
+typedef struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+} ccsr_gpio_t;
+#endif
+
+/* L2 Cache Registers */
+typedef struct ccsr_l2cache {
+ u32 l2ctl; /* L2 configuration 0 */
+ u8 res1[12];
+ u32 l2cewar0; /* L2 cache external write addr 0 */
+ u8 res2[4];
+ u32 l2cewcr0; /* L2 cache external write control 0 */
+ u8 res3[4];
+ u32 l2cewar1; /* L2 cache external write addr 1 */
+ u8 res4[4];
+ u32 l2cewcr1; /* L2 cache external write control 1 */
+ u8 res5[4];
+ u32 l2cewar2; /* L2 cache external write addr 2 */
+ u8 res6[4];
+ u32 l2cewcr2; /* L2 cache external write control 2 */
+ u8 res7[4];
+ u32 l2cewar3; /* L2 cache external write addr 3 */
+ u8 res8[4];
+ u32 l2cewcr3; /* L2 cache external write control 3 */
+ u8 res9[180];
+ u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
+ u8 res10[4];
+ u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
+ u8 res11[3316];
+ u32 l2errinjhi; /* L2 error injection mask high */
+ u32 l2errinjlo; /* L2 error injection mask low */
+ u32 l2errinjctl; /* L2 error injection tag/ECC control */
+ u8 res12[20];
+ u32 l2captdatahi; /* L2 error data high capture */
+ u32 l2captdatalo; /* L2 error data low capture */
+ u32 l2captecc; /* L2 error ECC capture */
+ u8 res13[20];
+ u32 l2errdet; /* L2 error detect */
+ u32 l2errdis; /* L2 error disable */
+ u32 l2errinten; /* L2 error interrupt enable */
+ u32 l2errattr; /* L2 error attributes capture */
+ u32 l2erraddr; /* L2 error addr capture */
+ u8 res14[4];
+ u32 l2errctl; /* L2 error control */
+ u8 res15[420];
+} ccsr_l2cache_t;
+
+#define MPC85xx_L2CTL_L2E 0x80000000
+#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
+#define MPC85xx_L2ERRDIS_MBECC 0x00000008
+#define MPC85xx_L2ERRDIS_SBECC 0x00000004
+
+/* DMA Registers */
+typedef struct ccsr_dma {
+ u8 res1[256];
+ struct fsl_dma dma[4];
+ u32 dgsr; /* DMA General Status */
+ u8 res2[11516];
+} ccsr_dma_t;
+
+/* tsec */
+typedef struct ccsr_tsec {
+ u8 res1[16];
+ u32 ievent; /* IRQ Event */
+ u32 imask; /* IRQ Mask */
+ u32 edis; /* Error Disabled */
+ u8 res2[4];
+ u32 ecntrl; /* Ethernet Control */
+ u32 minflr; /* Minimum Frame Len */
+ u32 ptv; /* Pause Time Value */
+ u32 dmactrl; /* DMA Control */
+ u32 tbipa; /* TBI PHY Addr */
+ u8 res3[88];
+ u32 fifo_tx_thr; /* FIFO transmit threshold */
+ u8 res4[8];
+ u32 fifo_tx_starve; /* FIFO transmit starve */
+ u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
+ u8 res5[96];
+ u32 tctrl; /* TX Control */
+ u32 tstat; /* TX Status */
+ u8 res6[4];
+ u32 tbdlen; /* TX Buffer Desc Data Len */
+ u8 res7[16];
+ u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
+ u32 ctbptr; /* Current TX Buffer Desc Ptr */
+ u8 res8[88];
+ u32 tbptrh; /* TX Buffer Desc Ptr High */
+ u32 tbptr; /* TX Buffer Desc Ptr Low */
+ u8 res9[120];
+ u32 tbaseh; /* TX Desc Base Addr High */
+ u32 tbase; /* TX Desc Base Addr */
+ u8 res10[168];
+ u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
+ u32 ostbdp; /* OOS TX Data Buffer Ptr */
+ u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
+ u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
+ u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
+ u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
+ u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
+ u8 res11[52];
+ u32 rctrl; /* RX Control */
+ u32 rstat; /* RX Status */
+ u8 res12[4];
+ u32 rbdlen; /* RxBD Data Len */
+ u8 res13[16];
+ u32 crbptrh; /* Current RX Buffer Desc Ptr High */
+ u32 crbptr; /* Current RX Buffer Desc Ptr */
+ u8 res14[24];
+ u32 mrblr; /* Maximum RX Buffer Len */
+ u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
+ u8 res15[56];
+ u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
+ u32 rbptr; /* RX Buffer Desc Ptr */
+ u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
+ u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
+ u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
+ u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
+ u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
+ u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
+ u8 res16[96];
+ u32 rbaseh; /* RX Desc Base Addr High 0 */
+ u32 rbase; /* RX Desc Base Addr */
+ u32 rbaseh1; /* RX Desc Base Addr High 1 */
+ u32 rbasel1; /* RX Desc Base Addr Low 1 */
+ u32 rbaseh2; /* RX Desc Base Addr High 2 */
+ u32 rbasel2; /* RX Desc Base Addr Low 2 */
+ u32 rbaseh3; /* RX Desc Base Addr High 3 */
+ u32 rbasel3; /* RX Desc Base Addr Low 3 */
+ u8 res17[224];
+ u32 maccfg1; /* MAC Configuration 1 */
+ u32 maccfg2; /* MAC Configuration 2 */
+ u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
+ u32 hafdup; /* Half Duplex */
+ u32 maxfrm; /* Maximum Frame Len */
+ u8 res18[12];
+ u32 miimcfg; /* MII Management Configuration */
+ u32 miimcom; /* MII Management Cmd */
+ u32 miimadd; /* MII Management Addr */
+ u32 miimcon; /* MII Management Control */
+ u32 miimstat; /* MII Management Status */
+ u32 miimind; /* MII Management Indicator */
+ u8 res19[4];
+ u32 ifstat; /* Interface Status */
+ u32 macstnaddr1; /* Station Addr Part 1 */
+ u32 macstnaddr2; /* Station Addr Part 2 */
+ u8 res20[312];
+ u32 tr64; /* TX & RX 64-byte Frame Counter */
+ u32 tr127; /* TX & RX 65-127 byte Frame Counter */
+ u32 tr255; /* TX & RX 128-255 byte Frame Counter */
+ u32 tr511; /* TX & RX 256-511 byte Frame Counter */
+ u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
+ u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
+ u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
+ u32 rbyt; /* RX Byte Counter */
+ u32 rpkt; /* RX Packet Counter */
+ u32 rfcs; /* RX FCS Error Counter */
+ u32 rmca; /* RX Multicast Packet Counter */
+ u32 rbca; /* RX Broadcast Packet Counter */
+ u32 rxcf; /* RX Control Frame Packet Counter */
+ u32 rxpf; /* RX Pause Frame Packet Counter */
+ u32 rxuo; /* RX Unknown OP Code Counter */
+ u32 raln; /* RX Alignment Error Counter */
+ u32 rflr; /* RX Frame Len Error Counter */
+ u32 rcde; /* RX Code Error Counter */
+ u32 rcse; /* RX Carrier Sense Error Counter */
+ u32 rund; /* RX Undersize Packet Counter */
+ u32 rovr; /* RX Oversize Packet Counter */
+ u32 rfrg; /* RX Fragments Counter */
+ u32 rjbr; /* RX Jabber Counter */
+ u32 rdrp; /* RX Drop Counter */
+ u32 tbyt; /* TX Byte Counter Counter */
+ u32 tpkt; /* TX Packet Counter */
+ u32 tmca; /* TX Multicast Packet Counter */
+ u32 tbca; /* TX Broadcast Packet Counter */
+ u32 txpf; /* TX Pause Control Frame Counter */
+ u32 tdfr; /* TX Deferral Packet Counter */
+ u32 tedf; /* TX Excessive Deferral Packet Counter */
+ u32 tscl; /* TX Single Collision Packet Counter */
+ u32 tmcl; /* TX Multiple Collision Packet Counter */
+ u32 tlcl; /* TX Late Collision Packet Counter */
+ u32 txcl; /* TX Excessive Collision Packet Counter */
+ u32 tncl; /* TX Total Collision Counter */
+ u8 res21[4];
+ u32 tdrp; /* TX Drop Frame Counter */
+ u32 tjbr; /* TX Jabber Frame Counter */
+ u32 tfcs; /* TX FCS Error Counter */
+ u32 txcf; /* TX Control Frame Counter */
+ u32 tovr; /* TX Oversize Frame Counter */
+ u32 tund; /* TX Undersize Frame Counter */
+ u32 tfrg; /* TX Fragments Frame Counter */
+ u32 car1; /* Carry One */
+ u32 car2; /* Carry Two */
+ u32 cam1; /* Carry Mask One */
+ u32 cam2; /* Carry Mask Two */
+ u8 res22[192];
+ u32 iaddr0; /* Indivdual addr 0 */
+ u32 iaddr1; /* Indivdual addr 1 */
+ u32 iaddr2; /* Indivdual addr 2 */
+ u32 iaddr3; /* Indivdual addr 3 */
+ u32 iaddr4; /* Indivdual addr 4 */
+ u32 iaddr5; /* Indivdual addr 5 */
+ u32 iaddr6; /* Indivdual addr 6 */
+ u32 iaddr7; /* Indivdual addr 7 */
+ u8 res23[96];
+ u32 gaddr0; /* Global addr 0 */
+ u32 gaddr1; /* Global addr 1 */
+ u32 gaddr2; /* Global addr 2 */
+ u32 gaddr3; /* Global addr 3 */
+ u32 gaddr4; /* Global addr 4 */
+ u32 gaddr5; /* Global addr 5 */
+ u32 gaddr6; /* Global addr 6 */
+ u32 gaddr7; /* Global addr 7 */
+ u8 res24[96];
+ u32 pmd0; /* Pattern Match Data */
+ u8 res25[4];
+ u32 pmask0; /* Pattern Mask */
+ u8 res26[4];
+ u32 pcntrl0; /* Pattern Match Control */
+ u8 res27[4];
+ u32 pattrb0; /* Pattern Match Attrs */
+ u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd1; /* Pattern Match Data */
+ u8 res28[4];
+ u32 pmask1; /* Pattern Mask */
+ u8 res29[4];
+ u32 pcntrl1; /* Pattern Match Control */
+ u8 res30[4];
+ u32 pattrb1; /* Pattern Match Attrs */
+ u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd2; /* Pattern Match Data */
+ u8 res31[4];
+ u32 pmask2; /* Pattern Mask */
+ u8 res32[4];
+ u32 pcntrl2; /* Pattern Match Control */
+ u8 res33[4];
+ u32 pattrb2; /* Pattern Match Attrs */
+ u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd3; /* Pattern Match Data */
+ u8 res34[4];
+ u32 pmask3; /* Pattern Mask */
+ u8 res35[4];
+ u32 pcntrl3; /* Pattern Match Control */
+ u8 res36[4];
+ u32 pattrb3; /* Pattern Match Attrs */
+ u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd4; /* Pattern Match Data */
+ u8 res37[4];
+ u32 pmask4; /* Pattern Mask */
+ u8 res38[4];
+ u32 pcntrl4; /* Pattern Match Control */
+ u8 res39[4];
+ u32 pattrb4; /* Pattern Match Attrs */
+ u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd5; /* Pattern Match Data */
+ u8 res40[4];
+ u32 pmask5; /* Pattern Mask */
+ u8 res41[4];
+ u32 pcntrl5; /* Pattern Match Control */
+ u8 res42[4];
+ u32 pattrb5; /* Pattern Match Attrs */
+ u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd6; /* Pattern Match Data */
+ u8 res43[4];
+ u32 pmask6; /* Pattern Mask */
+ u8 res44[4];
+ u32 pcntrl6; /* Pattern Match Control */
+ u8 res45[4];
+ u32 pattrb6; /* Pattern Match Attrs */
+ u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd7; /* Pattern Match Data */
+ u8 res46[4];
+ u32 pmask7; /* Pattern Mask */
+ u8 res47[4];
+ u32 pcntrl7; /* Pattern Match Control */
+ u8 res48[4];
+ u32 pattrb7; /* Pattern Match Attrs */
+ u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd8; /* Pattern Match Data */
+ u8 res49[4];
+ u32 pmask8; /* Pattern Mask */
+ u8 res50[4];
+ u32 pcntrl8; /* Pattern Match Control */
+ u8 res51[4];
+ u32 pattrb8; /* Pattern Match Attrs */
+ u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd9; /* Pattern Match Data */
+ u8 res52[4];
+ u32 pmask9; /* Pattern Mask */
+ u8 res53[4];
+ u32 pcntrl9; /* Pattern Match Control */
+ u8 res54[4];
+ u32 pattrb9; /* Pattern Match Attrs */
+ u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd10; /* Pattern Match Data */
+ u8 res55[4];
+ u32 pmask10; /* Pattern Mask */
+ u8 res56[4];
+ u32 pcntrl10; /* Pattern Match Control */
+ u8 res57[4];
+ u32 pattrb10; /* Pattern Match Attrs */
+ u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd11; /* Pattern Match Data */
+ u8 res58[4];
+ u32 pmask11; /* Pattern Mask */
+ u8 res59[4];
+ u32 pcntrl11; /* Pattern Match Control */
+ u8 res60[4];
+ u32 pattrb11; /* Pattern Match Attrs */
+ u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd12; /* Pattern Match Data */
+ u8 res61[4];
+ u32 pmask12; /* Pattern Mask */
+ u8 res62[4];
+ u32 pcntrl12; /* Pattern Match Control */
+ u8 res63[4];
+ u32 pattrb12; /* Pattern Match Attrs */
+ u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd13; /* Pattern Match Data */
+ u8 res64[4];
+ u32 pmask13; /* Pattern Mask */
+ u8 res65[4];
+ u32 pcntrl13; /* Pattern Match Control */
+ u8 res66[4];
+ u32 pattrb13; /* Pattern Match Attrs */
+ u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd14; /* Pattern Match Data */
+ u8 res67[4];
+ u32 pmask14; /* Pattern Mask */
+ u8 res68[4];
+ u32 pcntrl14; /* Pattern Match Control */
+ u8 res69[4];
+ u32 pattrb14; /* Pattern Match Attrs */
+ u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
+ u32 pmd15; /* Pattern Match Data */
+ u8 res70[4];
+ u32 pmask15; /* Pattern Mask */
+ u8 res71[4];
+ u32 pcntrl15; /* Pattern Match Control */
+ u8 res72[4];
+ u32 pattrb15; /* Pattern Match Attrs */
+ u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
+ u8 res73[248];
+ u32 attr; /* Attrs */
+ u32 attreli; /* Attrs Extract Len & Idx */
+ u8 res74[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers */
+typedef struct ccsr_pic {
+ u8 res1[64];
+ u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
+ u8 res2[12];
+ u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
+ u8 res3[12];
+ u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
+ u8 res4[12];
+ u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
+ u8 res5[12];
+ u32 ctpr; /* Current Task Priority */
+ u8 res6[12];
+ u32 whoami; /* Who Am I */
+ u8 res7[12];
+ u32 iack; /* IRQ Acknowledge */
+ u8 res8[12];
+ u32 eoi; /* End Of IRQ */
+ u8 res9[3916];
+ u32 frr; /* Feature Reporting */
+ u8 res10[28];
+ u32 gcr; /* Global Configuration */
+#define MPC85xx_PICGCR_RST 0x80000000
+#define MPC85xx_PICGCR_M 0x20000000
+ u8 res11[92];
+ u32 vir; /* Vendor Identification */
+ u8 res12[12];
+ u32 pir; /* Processor Initialization */
+ u8 res13[12];
+ u32 ipivpr0; /* IPI Vector/Priority 0 */
+ u8 res14[12];
+ u32 ipivpr1; /* IPI Vector/Priority 1 */
+ u8 res15[12];
+ u32 ipivpr2; /* IPI Vector/Priority 2 */
+ u8 res16[12];
+ u32 ipivpr3; /* IPI Vector/Priority 3 */
+ u8 res17[12];
+ u32 svr; /* Spurious Vector */
+ u8 res18[12];
+ u32 tfrr; /* Timer Frequency Reporting */
+ u8 res19[12];
+ u32 gtccr0; /* Global Timer Current Count 0 */
+ u8 res20[12];
+ u32 gtbcr0; /* Global Timer Base Count 0 */
+ u8 res21[12];
+ u32 gtvpr0; /* Global Timer Vector/Priority 0 */
+ u8 res22[12];
+ u32 gtdr0; /* Global Timer Destination 0 */
+ u8 res23[12];
+ u32 gtccr1; /* Global Timer Current Count 1 */
+ u8 res24[12];
+ u32 gtbcr1; /* Global Timer Base Count 1 */
+ u8 res25[12];
+ u32 gtvpr1; /* Global Timer Vector/Priority 1 */
+ u8 res26[12];
+ u32 gtdr1; /* Global Timer Destination 1 */
+ u8 res27[12];
+ u32 gtccr2; /* Global Timer Current Count 2 */
+ u8 res28[12];
+ u32 gtbcr2; /* Global Timer Base Count 2 */
+ u8 res29[12];
+ u32 gtvpr2; /* Global Timer Vector/Priority 2 */
+ u8 res30[12];
+ u32 gtdr2; /* Global Timer Destination 2 */
+ u8 res31[12];
+ u32 gtccr3; /* Global Timer Current Count 3 */
+ u8 res32[12];
+ u32 gtbcr3; /* Global Timer Base Count 3 */
+ u8 res33[12];
+ u32 gtvpr3; /* Global Timer Vector/Priority 3 */
+ u8 res34[12];
+ u32 gtdr3; /* Global Timer Destination 3 */
+ u8 res35[268];
+ u32 tcr; /* Timer Control */
+ u8 res36[12];
+ u32 irqsr0; /* IRQ_OUT Summary 0 */
+ u8 res37[12];
+ u32 irqsr1; /* IRQ_OUT Summary 1 */
+ u8 res38[12];
+ u32 cisr0; /* Critical IRQ Summary 0 */
+ u8 res39[12];
+ u32 cisr1; /* Critical IRQ Summary 1 */
+ u8 res40[188];
+ u32 msgr0; /* Message 0 */
+ u8 res41[12];
+ u32 msgr1; /* Message 1 */
+ u8 res42[12];
+ u32 msgr2; /* Message 2 */
+ u8 res43[12];
+ u32 msgr3; /* Message 3 */
+ u8 res44[204];
+ u32 mer; /* Message Enable */
+ u8 res45[12];
+ u32 msr; /* Message Status */
+ u8 res46[60140];
+ u32 eivpr0; /* External IRQ Vector/Priority 0 */
+ u8 res47[12];
+ u32 eidr0; /* External IRQ Destination 0 */
+ u8 res48[12];
+ u32 eivpr1; /* External IRQ Vector/Priority 1 */
+ u8 res49[12];
+ u32 eidr1; /* External IRQ Destination 1 */
+ u8 res50[12];
+ u32 eivpr2; /* External IRQ Vector/Priority 2 */
+ u8 res51[12];
+ u32 eidr2; /* External IRQ Destination 2 */
+ u8 res52[12];
+ u32 eivpr3; /* External IRQ Vector/Priority 3 */
+ u8 res53[12];
+ u32 eidr3; /* External IRQ Destination 3 */
+ u8 res54[12];
+ u32 eivpr4; /* External IRQ Vector/Priority 4 */
+ u8 res55[12];
+ u32 eidr4; /* External IRQ Destination 4 */
+ u8 res56[12];
+ u32 eivpr5; /* External IRQ Vector/Priority 5 */
+ u8 res57[12];
+ u32 eidr5; /* External IRQ Destination 5 */
+ u8 res58[12];
+ u32 eivpr6; /* External IRQ Vector/Priority 6 */
+ u8 res59[12];
+ u32 eidr6; /* External IRQ Destination 6 */
+ u8 res60[12];
+ u32 eivpr7; /* External IRQ Vector/Priority 7 */
+ u8 res61[12];
+ u32 eidr7; /* External IRQ Destination 7 */
+ u8 res62[12];
+ u32 eivpr8; /* External IRQ Vector/Priority 8 */
+ u8 res63[12];
+ u32 eidr8; /* External IRQ Destination 8 */
+ u8 res64[12];
+ u32 eivpr9; /* External IRQ Vector/Priority 9 */
+ u8 res65[12];
+ u32 eidr9; /* External IRQ Destination 9 */
+ u8 res66[12];
+ u32 eivpr10; /* External IRQ Vector/Priority 10 */
+ u8 res67[12];
+ u32 eidr10; /* External IRQ Destination 10 */
+ u8 res68[12];
+ u32 eivpr11; /* External IRQ Vector/Priority 11 */
+ u8 res69[12];
+ u32 eidr11; /* External IRQ Destination 11 */
+ u8 res70[140];
+ u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
+ u8 res71[12];
+ u32 iidr0; /* Internal IRQ Destination 0 */
+ u8 res72[12];
+ u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
+ u8 res73[12];
+ u32 iidr1; /* Internal IRQ Destination 1 */
+ u8 res74[12];
+ u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
+ u8 res75[12];
+ u32 iidr2; /* Internal IRQ Destination 2 */
+ u8 res76[12];
+ u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
+ u8 res77[12];
+ u32 iidr3; /* Internal IRQ Destination 3 */
+ u8 res78[12];
+ u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
+ u8 res79[12];
+ u32 iidr4; /* Internal IRQ Destination 4 */
+ u8 res80[12];
+ u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
+ u8 res81[12];
+ u32 iidr5; /* Internal IRQ Destination 5 */
+ u8 res82[12];
+ u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
+ u8 res83[12];
+ u32 iidr6; /* Internal IRQ Destination 6 */
+ u8 res84[12];
+ u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
+ u8 res85[12];
+ u32 iidr7; /* Internal IRQ Destination 7 */
+ u8 res86[12];
+ u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
+ u8 res87[12];
+ u32 iidr8; /* Internal IRQ Destination 8 */
+ u8 res88[12];
+ u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
+ u8 res89[12];
+ u32 iidr9; /* Internal IRQ Destination 9 */
+ u8 res90[12];
+ u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
+ u8 res91[12];
+ u32 iidr10; /* Internal IRQ Destination 10 */
+ u8 res92[12];
+ u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
+ u8 res93[12];
+ u32 iidr11; /* Internal IRQ Destination 11 */
+ u8 res94[12];
+ u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
+ u8 res95[12];
+ u32 iidr12; /* Internal IRQ Destination 12 */
+ u8 res96[12];
+ u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
+ u8 res97[12];
+ u32 iidr13; /* Internal IRQ Destination 13 */
+ u8 res98[12];
+ u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
+ u8 res99[12];
+ u32 iidr14; /* Internal IRQ Destination 14 */
+ u8 res100[12];
+ u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
+ u8 res101[12];
+ u32 iidr15; /* Internal IRQ Destination 15 */
+ u8 res102[12];
+ u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
+ u8 res103[12];
+ u32 iidr16; /* Internal IRQ Destination 16 */
+ u8 res104[12];
+ u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
+ u8 res105[12];
+ u32 iidr17; /* Internal IRQ Destination 17 */
+ u8 res106[12];
+ u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
+ u8 res107[12];
+ u32 iidr18; /* Internal IRQ Destination 18 */
+ u8 res108[12];
+ u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
+ u8 res109[12];
+ u32 iidr19; /* Internal IRQ Destination 19 */
+ u8 res110[12];
+ u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
+ u8 res111[12];
+ u32 iidr20; /* Internal IRQ Destination 20 */
+ u8 res112[12];
+ u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
+ u8 res113[12];
+ u32 iidr21; /* Internal IRQ Destination 21 */
+ u8 res114[12];
+ u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
+ u8 res115[12];
+ u32 iidr22; /* Internal IRQ Destination 22 */
+ u8 res116[12];
+ u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
+ u8 res117[12];
+ u32 iidr23; /* Internal IRQ Destination 23 */
+ u8 res118[12];
+ u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
+ u8 res119[12];
+ u32 iidr24; /* Internal IRQ Destination 24 */
+ u8 res120[12];
+ u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
+ u8 res121[12];
+ u32 iidr25; /* Internal IRQ Destination 25 */
+ u8 res122[12];
+ u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
+ u8 res123[12];
+ u32 iidr26; /* Internal IRQ Destination 26 */
+ u8 res124[12];
+ u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
+ u8 res125[12];
+ u32 iidr27; /* Internal IRQ Destination 27 */
+ u8 res126[12];
+ u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
+ u8 res127[12];
+ u32 iidr28; /* Internal IRQ Destination 28 */
+ u8 res128[12];
+ u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
+ u8 res129[12];
+ u32 iidr29; /* Internal IRQ Destination 29 */
+ u8 res130[12];
+ u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
+ u8 res131[12];
+ u32 iidr30; /* Internal IRQ Destination 30 */
+ u8 res132[12];
+ u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
+ u8 res133[12];
+ u32 iidr31; /* Internal IRQ Destination 31 */
+ u8 res134[4108];
+ u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
+ u8 res135[12];
+ u32 midr0; /* Messaging IRQ Destination 0 */
+ u8 res136[12];
+ u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
+ u8 res137[12];
+ u32 midr1; /* Messaging IRQ Destination 1 */
+ u8 res138[12];
+ u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
+ u8 res139[12];
+ u32 midr2; /* Messaging IRQ Destination 2 */
+ u8 res140[12];
+ u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
+ u8 res141[12];
+ u32 midr3; /* Messaging IRQ Destination 3 */
+ u8 res142[59852];
+ u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
+ u8 res143[12];
+ u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
+ u8 res144[12];
+ u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
+ u8 res145[12];
+ u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
+ u8 res146[12];
+ u32 ctpr0; /* Current Task Priority for Processor 0 */
+ u8 res147[12];
+ u32 whoami0; /* Who Am I for Processor 0 */
+ u8 res148[12];
+ u32 iack0; /* IRQ Acknowledge for Processor 0 */
+ u8 res149[12];
+ u32 eoi0; /* End Of IRQ for Processor 0 */
+ u8 res150[130892];
+} ccsr_pic_t;
+
+/* CPM Block */
+#ifndef CONFIG_CPM2
+typedef struct ccsr_cpm {
+ u8 res[262144];
+} ccsr_cpm_t;
+#else
+/*
+ * DPARM
+ * General SIU
+ */
+typedef struct ccsr_cpm_siu {
+ u8 res1[80];
+ u32 smaer;
+ u32 smser;
+ u32 smevr;
+ u8 res2[4];
+ u32 lmaer;
+ u32 lmser;
+ u32 lmevr;
+ u8 res3[2964];
+} ccsr_cpm_siu_t;
+
+/* IRQ Controller */
+typedef struct ccsr_cpm_intctl {
+ u16 sicr;
+ u8 res1[2];
+ u32 sivec;
+ u32 sipnrh;
+ u32 sipnrl;
+ u32 siprr;
+ u32 scprrh;
+ u32 scprrl;
+ u32 simrh;
+ u32 simrl;
+ u32 siexr;
+ u8 res2[88];
+ u32 sccr;
+ u8 res3[124];
+} ccsr_cpm_intctl_t;
+
+/* input/output port */
+typedef struct ccsr_cpm_iop {
+ u32 pdira;
+ u32 ppara;
+ u32 psora;
+ u32 podra;
+ u32 pdata;
+ u8 res1[12];
+ u32 pdirb;
+ u32 pparb;
+ u32 psorb;
+ u32 podrb;
+ u32 pdatb;
+ u8 res2[12];
+ u32 pdirc;
+ u32 pparc;
+ u32 psorc;
+ u32 podrc;
+ u32 pdatc;
+ u8 res3[12];
+ u32 pdird;
+ u32 ppard;
+ u32 psord;
+ u32 podrd;
+ u32 pdatd;
+ u8 res4[12];
+} ccsr_cpm_iop_t;
+
+/* CPM timers */
+typedef struct ccsr_cpm_timer {
+ u8 tgcr1;
+ u8 res1[3];
+ u8 tgcr2;
+ u8 res2[11];
+ u16 tmr1;
+ u16 tmr2;
+ u16 trr1;
+ u16 trr2;
+ u16 tcr1;
+ u16 tcr2;
+ u16 tcn1;
+ u16 tcn2;
+ u16 tmr3;
+ u16 tmr4;
+ u16 trr3;
+ u16 trr4;
+ u16 tcr3;
+ u16 tcr4;
+ u16 tcn3;
+ u16 tcn4;
+ u16 ter1;
+ u16 ter2;
+ u16 ter3;
+ u16 ter4;
+ u8 res3[608];
+} ccsr_cpm_timer_t;
+
+/* SDMA */
+typedef struct ccsr_cpm_sdma {
+ u8 sdsr;
+ u8 res1[3];
+ u8 sdmr;
+ u8 res2[739];
+} ccsr_cpm_sdma_t;
+
+/* FCC1 */
+typedef struct ccsr_cpm_fcc1 {
+ u32 gfmr;
+ u32 fpsmr;
+ u16 ftodr;
+ u8 res1[2];
+ u16 fdsr;
+ u8 res2[2];
+ u16 fcce;
+ u8 res3[2];
+ u16 fccm;
+ u8 res4[2];
+ u8 fccs;
+ u8 res5[3];
+ u8 ftirr_phy[4];
+} ccsr_cpm_fcc1_t;
+
+/* FCC2 */
+typedef struct ccsr_cpm_fcc2 {
+ u32 gfmr;
+ u32 fpsmr;
+ u16 ftodr;
+ u8 res1[2];
+ u16 fdsr;
+ u8 res2[2];
+ u16 fcce;
+ u8 res3[2];
+ u16 fccm;
+ u8 res4[2];
+ u8 fccs;
+ u8 res5[3];
+ u8 ftirr_phy[4];
+} ccsr_cpm_fcc2_t;
+
+/* FCC3 */
+typedef struct ccsr_cpm_fcc3 {
+ u32 gfmr;
+ u32 fpsmr;
+ u16 ftodr;
+ u8 res1[2];
+ u16 fdsr;
+ u8 res2[2];
+ u16 fcce;
+ u8 res3[2];
+ u16 fccm;
+ u8 res4[2];
+ u8 fccs;
+ u8 res5[3];
+ u8 res[36];
+} ccsr_cpm_fcc3_t;
+
+/* FCC1 extended */
+typedef struct ccsr_cpm_fcc1_ext {
+ u32 firper;
+ u32 firer;
+ u32 firsr_h;
+ u32 firsr_l;
+ u8 gfemr;
+ u8 res[15];
+
+} ccsr_cpm_fcc1_ext_t;
+
+/* FCC2 extended */
+typedef struct ccsr_cpm_fcc2_ext {
+ u32 firper;
+ u32 firer;
+ u32 firsr_h;
+ u32 firsr_l;
+ u8 gfemr;
+ u8 res[31];
+} ccsr_cpm_fcc2_ext_t;
+
+/* FCC3 extended */
+typedef struct ccsr_cpm_fcc3_ext {
+ u8 gfemr;
+ u8 res[47];
+} ccsr_cpm_fcc3_ext_t;
+
+/* TC layers */
+typedef struct ccsr_cpm_tmp1 {
+ u8 res[496];
+} ccsr_cpm_tmp1_t;
+
+/* BRGs:5,6,7,8 */
+typedef struct ccsr_cpm_brg2 {
+ u32 brgc5;
+ u32 brgc6;
+ u32 brgc7;
+ u32 brgc8;
+ u8 res[608];
+} ccsr_cpm_brg2_t;
+
+/* I2C */
+typedef struct ccsr_cpm_i2c {
+ u8 i2mod;
+ u8 res1[3];
+ u8 i2add;
+ u8 res2[3];
+ u8 i2brg;
+ u8 res3[3];
+ u8 i2com;
+ u8 res4[3];
+ u8 i2cer;
+ u8 res5[3];
+ u8 i2cmr;
+ u8 res6[331];
+} ccsr_cpm_i2c_t;
+
+/* CPM core */
+typedef struct ccsr_cpm_cp {
+ u32 cpcr;
+ u32 rccr;
+ u8 res1[14];
+ u16 rter;
+ u8 res2[2];
+ u16 rtmr;
+ u16 rtscr;
+ u8 res3[2];
+ u32 rtsr;
+ u8 res4[12];
+} ccsr_cpm_cp_t;
+
+/* BRGs:1,2,3,4 */
+typedef struct ccsr_cpm_brg1 {
+ u32 brgc1;
+ u32 brgc2;
+ u32 brgc3;
+ u32 brgc4;
+} ccsr_cpm_brg1_t;
+
+/* SCC1-SCC4 */
+typedef struct ccsr_cpm_scc {
+ u32 gsmrl;
+ u32 gsmrh;
+ u16 psmr;
+ u8 res1[2];
+ u16 todr;
+ u16 dsr;
+ u16 scce;
+ u8 res2[2];
+ u16 sccm;
+ u8 res3;
+ u8 sccs;
+ u8 res4[8];
+} ccsr_cpm_scc_t;
+
+typedef struct ccsr_cpm_tmp2 {
+ u8 res[32];
+} ccsr_cpm_tmp2_t;
+
+/* SPI */
+typedef struct ccsr_cpm_spi {
+ u16 spmode;
+ u8 res1[4];
+ u8 spie;
+ u8 res2[3];
+ u8 spim;
+ u8 res3[2];
+ u8 spcom;
+ u8 res4[82];
+} ccsr_cpm_spi_t;
+
+/* CPM MUX */
+typedef struct ccsr_cpm_mux {
+ u8 cmxsi1cr;
+ u8 res1;
+ u8 cmxsi2cr;
+ u8 res2;
+ u32 cmxfcr;
+ u32 cmxscr;
+ u8 res3[2];
+ u16 cmxuar;
+ u8 res4[16];
+} ccsr_cpm_mux_t;
+
+/* SI,MCC,etc */
+typedef struct ccsr_cpm_tmp3 {
+ u8 res[58592];
+} ccsr_cpm_tmp3_t;
+
+typedef struct ccsr_cpm_iram {
+ u32 iram[8192];
+ u8 res[98304];
+} ccsr_cpm_iram_t;
+
+typedef struct ccsr_cpm {
+ /* Some references are into the unique & known dpram spaces,
+ * others are from the generic base.
+ */
+#define im_dprambase im_dpram1
+ u8 im_dpram1[16*1024];
+ u8 res1[16*1024];
+ u8 im_dpram2[16*1024];
+ u8 res2[16*1024];
+ ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
+ ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
+ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
+ ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
+ ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
+ ccsr_cpm_fcc1_t im_cpm_fcc1;
+ ccsr_cpm_fcc2_t im_cpm_fcc2;
+ ccsr_cpm_fcc3_t im_cpm_fcc3;
+ ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
+ ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
+ ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
+ ccsr_cpm_tmp1_t im_cpm_tmp1;
+ ccsr_cpm_brg2_t im_cpm_brg2;
+ ccsr_cpm_i2c_t im_cpm_i2c;
+ ccsr_cpm_cp_t im_cpm_cp;
+ ccsr_cpm_brg1_t im_cpm_brg1;
+ ccsr_cpm_scc_t im_cpm_scc[4];
+ ccsr_cpm_tmp2_t im_cpm_tmp2;
+ ccsr_cpm_spi_t im_cpm_spi;
+ ccsr_cpm_mux_t im_cpm_mux;
+ ccsr_cpm_tmp3_t im_cpm_tmp3;
+ ccsr_cpm_iram_t im_cpm_iram;
+} ccsr_cpm_t;
+#endif
+
+#ifdef CONFIG_SYS_SRIO
+/* Architectural regsiters */
+struct rio_arch {
+ u32 didcar; /* Device Identity CAR */
+ u32 dicar; /* Device Information CAR */
+ u32 aidcar; /* Assembly Identity CAR */
+ u32 aicar; /* Assembly Information CAR */
+ u32 pefcar; /* Processing Element Features CAR */
+ u8 res0[4];
+ u32 socar; /* Source Operations CAR */
+ u32 docar; /* Destination Operations CAR */
+ u8 res1[32];
+ u32 mcsr; /* Mailbox CSR */
+ u32 pwdcsr; /* Port-Write and Doorbell CSR */
+ u8 res2[4];
+ u32 pellccsr; /* Processing Element Logic Layer CCSR */
+ u8 res3[12];
+ u32 lcsbacsr; /* Local Configuration Space BACSR */
+ u32 bdidcsr; /* Base Device ID CSR */
+ u8 res4[4];
+ u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
+ u32 ctcsr; /* Component Tag CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial Port registers */
+struct rio_lp_serial_port {
+ u32 plmreqcsr; /* Port Link Maintenance Request CSR */
+ u32 plmrespcsr; /* Port Link Maintenance Response CS */
+ u32 plascsr; /* Port Local Ackid Status CSR */
+ u8 res0[12];
+ u32 pescsr; /* Port Error and Status CSR */
+ u32 pccsr; /* Port Control CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial registers */
+struct rio_lp_serial {
+ u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
+ u8 res0[28];
+ u32 pltoccsr; /* Port Link Time-out CCSR */
+ u32 prtoccsr; /* Port Response Time-out CCSR */
+ u8 res1[20];
+ u32 pgccsr; /* Port General CSR */
+ struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Logical error reporting registers */
+struct rio_logical_err {
+ u32 erbh; /* Error Reporting Block Header Register */
+ u8 res0[4];
+ u32 ltledcsr; /* Logical/Transport layer error DCSR */
+ u32 ltleecsr; /* Logical/Transport layer error ECSR */
+ u8 res1[4];
+ u32 ltlaccsr; /* Logical/Transport layer ACCSR */
+ u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
+ u32 ltlcccsr; /* Logical/Transport layer control CCSR */
+};
+
+/* Physical error reporting port registers */
+struct rio_phys_err_port {
+ u32 edcsr; /* Port error detect CSR */
+ u32 erecsr; /* Port error rate enable CSR */
+ u32 ecacsr; /* Port error capture attributes CSR */
+ u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
+ u32 peccsr[3]; /* Port error capture CSR */
+ u8 res0[12];
+ u32 ercsr; /* Port error rate CSR */
+ u32 ertcsr; /* Port error rate threshold CSR */
+ u8 res1[16];
+};
+
+/* Physical error reporting registers */
+struct rio_phys_err {
+ struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Implementation Space: General Port-Common */
+struct rio_impl_common {
+ u8 res0[4];
+ u32 llcr; /* Logical Layer Configuration Register */
+ u8 res1[8];
+ u32 epwisr; /* Error / Port-Write Interrupt SR */
+ u8 res2[12];
+ u32 lretcr; /* Logical Retry Error Threshold CR */
+ u8 res3[92];
+ u32 pretcr; /* Physical Retry Erorr Threshold CR */
+ u8 res4[124];
+};
+
+/* Implementation Space: Port Specific */
+struct rio_impl_port_spec {
+ u32 adidcsr; /* Port Alt. Device ID CSR */
+ u8 res0[28];
+ u32 ptaacr; /* Port Pass-Through/Accept-All CR */
+ u32 lopttlcr;
+ u8 res1[8];
+ u32 iecsr; /* Port Implementation Error CSR */
+ u8 res2[12];
+ u32 pcr; /* Port Phsyical Configuration Register */
+ u8 res3[20];
+ u32 slcsr; /* Port Serial Link CSR */
+ u8 res4[4];
+ u32 sleicr; /* Port Serial Link Error Injection */
+ u32 a0txcr; /* Port Arbitration 0 Tx CR */
+ u32 a1txcr; /* Port Arbitration 1 Tx CR */
+ u32 a2txcr; /* Port Arbitration 2 Tx CR */
+ u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
+ u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
+};
+
+/* Implementation Space: register */
+struct rio_implement {
+ struct rio_impl_common com;
+ struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Revision Control Register */
+struct rio_rev_ctrl {
+ u32 ipbrr[2]; /* IP Block Revision Register */
+};
+
+struct rio_atmu_row {
+ u32 rowtar; /* RapidIO Outbound Window TAR */
+ u32 rowtear; /* RapidIO Outbound Window TEAR */
+ u32 rowbar;
+ u8 res0[4];
+ u32 rowar; /* RapidIO Outbound Attributes Register */
+ u32 rowsr[3]; /* Port RapidIO outbound window segment register */
+};
+
+struct rio_atmu_riw {
+ u32 riwtar; /* RapidIO Inbound Window Translation AR */
+ u8 res0[4];
+ u32 riwbar; /* RapidIO Inbound Window Base AR */
+ u8 res1[4];
+ u32 riwar; /* RapidIO Inbound Attributes Register */
+ u8 res2[12];
+};
+
+/* ATMU window registers */
+struct rio_atmu_win {
+ struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+ u8 res0[64];
+ struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+};
+
+struct rio_atmu {
+ struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+#ifdef CONFIG_SYS_FSL_RMU
+struct rio_msg {
+ u32 omr; /* Outbound Mode Register */
+ u32 osr; /* Outbound Status Register */
+ u32 eodqdpar; /* Extended Outbound DQ DPAR */
+ u32 odqdpar; /* Outbound Descriptor Queue DPAR */
+ u32 eosar; /* Extended Outbound Unit Source AR */
+ u32 osar; /* Outbound Unit Source AR */
+ u32 odpr; /* Outbound Destination Port Register */
+ u32 odatr; /* Outbound Destination Attributes Register */
+ u32 odcr; /* Outbound Doubleword Count Register */
+ u32 eodqepar; /* Extended Outbound DQ EPAR */
+ u32 odqepar; /* Outbound Descriptor Queue EPAR */
+ u32 oretr; /* Outbound Retry Error Threshold Register */
+ u32 omgr; /* Outbound Multicast Group Register */
+ u32 omlr; /* Outbound Multicast List Register */
+ u8 res0[40];
+ u32 imr; /* Outbound Mode Register */
+ u32 isr; /* Inbound Status Register */
+ u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
+ u32 idqdpar; /* Inbound Descriptor Queue DPAR */
+ u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
+ u32 ifqepar; /* Inbound Frame Queue EPAR */
+ u32 imirir; /* Inbound Maximum Interrutp RIR */
+ u8 res1[4];
+ u32 eihqepar; /* Extended inbound message header queue EPAR */
+ u32 ihqepar; /* Inbound message header queue EPAR */
+ u8 res2[120];
+};
+
+struct rio_dbell {
+ u32 odmr; /* Outbound Doorbell Mode Register */
+ u32 odsr; /* Outbound Doorbell Status Register */
+ u8 res0[16];
+ u32 oddpr; /* Outbound Doorbell Destination Port */
+ u32 oddatr; /* Outbound Doorbell Destination AR */
+ u8 res1[12];
+ u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
+ u8 res2[48];
+ u32 idmr; /* Inbound Doorbell Mode Register */
+ u32 idsr; /* Inbound Doorbell Status Register */
+ u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
+ u32 iqdpar; /* Inbound Doorbell Queue DPAR */
+ u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
+ u32 idqepar; /* Inbound Doorbell Queue EPAR */
+ u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
+};
+
+struct rio_pw {
+ u32 pwmr; /* Port-Write Mode Register */
+ u32 pwsr; /* Port-Write Status Register */
+ u32 epwqbar; /* Extended Port-Write Queue BAR */
+ u32 pwqbar; /* Port-Write Queue Base Address Register */
+};
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+struct rio_liodn {
+ u32 plbr;
+ u8 res0[28];
+ u32 plaor;
+ u8 res1[12];
+ u32 pludr;
+ u32 plldr;
+ u8 res2[456];
+};
+#endif
+
+/* RapidIO Registers */
+struct ccsr_rio {
+ struct rio_arch arch;
+ u8 res0[144];
+ struct rio_lp_serial lp_serial;
+ u8 res1[1152];
+ struct rio_logical_err logical_err;
+ u8 res2[32];
+ struct rio_phys_err phys_err;
+ u8 res3[63808];
+ struct rio_implement impl;
+ u8 res4[2552];
+ struct rio_rev_ctrl rev;
+ struct rio_atmu atmu;
+#ifdef CONFIG_SYS_FSL_RMU
+ u8 res5[8192];
+ struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+ u8 res6[512];
+ struct rio_dbell dbell;
+ u8 res7[100];
+ struct rio_pw pw;
+#endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+ u8 res5[8192];
+ struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+#endif
+};
+#endif
+
+/* Quick Engine Block Pin Muxing Registers */
+typedef struct par_io {
+ u32 cpodr;
+ u32 cpdat;
+ u32 cpdir1;
+ u32 cpdir2;
+ u32 cppar1;
+ u32 cppar2;
+ u8 res[8];
+} par_io_t;
+
+#ifdef CONFIG_SYS_FSL_CPC
+/*
+ * Define a single offset that is the start of all the CPC register
+ * blocks - if there is more than one CPC, we expect these to be
+ * contiguous 4k regions
+ */
+
+typedef struct cpc_corenet {
+ u32 cpccsr0; /* Config/status reg */
+ u32 res1;
+ u32 cpccfg0; /* Configuration register */
+ u32 res2;
+ u32 cpcewcr0; /* External Write reg 0 */
+ u32 cpcewabr0; /* External write base reg 0 */
+ u32 res3[2];
+ u32 cpcewcr1; /* External Write reg 1 */
+ u32 cpcewabr1; /* External write base reg 1 */
+ u32 res4[54];
+ u32 cpcsrcr1; /* SRAM control reg 1 */
+ u32 cpcsrcr0; /* SRAM control reg 0 */
+ u32 res5[62];
+ struct {
+ u32 id; /* partition ID */
+ u32 res;
+ u32 alloc; /* partition allocation */
+ u32 way; /* partition way */
+ } partition_regs[16];
+ u32 res6[704];
+ u32 cpcerrinjhi; /* Error injection high */
+ u32 cpcerrinjlo; /* Error injection lo */
+ u32 cpcerrinjctl; /* Error injection control */
+ u32 res7[5];
+ u32 cpccaptdatahi; /* capture data high */
+ u32 cpccaptdatalo; /* capture data low */
+ u32 cpcaptecc; /* capture ECC */
+ u32 res8[5];
+ u32 cpcerrdet; /* error detect */
+ u32 cpcerrdis; /* error disable */
+ u32 cpcerrinten; /* errir interrupt enable */
+ u32 cpcerrattr; /* error attribute */
+ u32 cpcerreaddr; /* error extended address */
+ u32 cpcerraddr; /* error address */
+ u32 cpcerrctl; /* error control */
+ u32 res9[41]; /* pad out to 4k */
+ u32 cpchdbcr0; /* hardware debug control register 0 */
+ u32 res10[63]; /* pad out to 4k */
+} cpc_corenet_t;
+
+#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
+#define CPC_CSR0_PE 0x40000000 /* Enable ECC */
+#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
+#define CPC_CSR0_WT 0x00080000 /* Write-through mode */
+#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
+#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
+#define CPC_CFG0_SZ_MASK 0x00003fff
+#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
+#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
+#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
+#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
+#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
+ & CPC_SRCR1_SRBARU_MASK)
+#define CPC_SRCR0_SRBARL_MASK 0xffff8000
+#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
+#define CPC_SRCR0_INTLVEN 0x00000100
+#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
+#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
+#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
+#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
+#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
+#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
+#define CPC_SRCR0_SRAMEN 0x00000001
+#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
+#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
+#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
+#endif /* CONFIG_SYS_FSL_CPC */
+
+/* Global Utilities Block */
+#ifdef CONFIG_FSL_CORENET
+typedef struct ccsr_gur {
+ u32 porsr1; /* POR status 1 */
+ u32 porsr2; /* POR status 2 */
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
+#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
+#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
+#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
+#endif
+ u8 res_008[0x20-0x8];
+ u32 gpporcr1; /* General-purpose POR configuration */
+ u32 gpporcr2; /* General-purpose POR configuration 2 */
+ u32 dcfg_fusesr; /* Fuse status register */
+#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
+ u8 res_02c[0x70-0x2c];
+ u32 devdisr; /* Device disable control */
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ u32 devdisr5; /* Device disable control 5 */
+#define FSL_CORENET_DEVDISR_PBL 0x80000000
+#define FSL_CORENET_DEVDISR_PMAN 0x40000000
+#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
+#define FSL_CORENET_DEVDISR_DMA1 0x00800000
+#define FSL_CORENET_DEVDISR_DMA2 0x00400000
+#define FSL_CORENET_DEVDISR_USB1 0x00080000
+#define FSL_CORENET_DEVDISR_USB2 0x00040000
+#define FSL_CORENET_DEVDISR_SATA1 0x00008000
+#define FSL_CORENET_DEVDISR_SATA2 0x00004000
+#define FSL_CORENET_DEVDISR_PME 0x00000800
+#define FSL_CORENET_DEVDISR_SEC 0x00000200
+#define FSL_CORENET_DEVDISR_RMU 0x00000080
+#define FSL_CORENET_DEVDISR_DCE 0x00000040
+#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
+#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
+#else
+#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
+#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
+#endif
+#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
+#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
+#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
+#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
+#define FSL_CORENET_DEVDISR2_FM1 0x00000080
+#define FSL_CORENET_DEVDISR2_FM2 0x00000040
+#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
+#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
+#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
+#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
+#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
+#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
+#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
+#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
+#define FSL_CORENET_DEVDISR3_LA1 0x00008000
+#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
+#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
+#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
+#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
+#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
+#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
+#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
+#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
+#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
+#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
+#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
+#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
+#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
+#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
+#define FSL_CORENET_DEVDISR5_IFC 0x00800000
+#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
+#define FSL_CORENET_DEVDISR5_DBG 0x00200000
+#define FSL_CORENET_DEVDISR5_NAL 0x00100000
+#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
+#define FSL_CORENET_NUM_DEVDISR 5
+#else
+#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
+#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
+#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
+#define FSL_CORENET_DEVDISR_RMU 0x08000000
+#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
+#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
+#define FSL_CORENET_DEVDISR_DMA1 0x00400000
+#define FSL_CORENET_DEVDISR_DMA2 0x00200000
+#define FSL_CORENET_DEVDISR_DDR1 0x00100000
+#define FSL_CORENET_DEVDISR_DDR2 0x00080000
+#define FSL_CORENET_DEVDISR_DBG 0x00010000
+#define FSL_CORENET_DEVDISR_NAL 0x00008000
+#define FSL_CORENET_DEVDISR_SATA1 0x00004000
+#define FSL_CORENET_DEVDISR_SATA2 0x00002000
+#define FSL_CORENET_DEVDISR_ELBC 0x00001000
+#define FSL_CORENET_DEVDISR_USB1 0x00000800
+#define FSL_CORENET_DEVDISR_USB2 0x00000400
+#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
+#define FSL_CORENET_DEVDISR_GPIO 0x00000080
+#define FSL_CORENET_DEVDISR_ESPI 0x00000040
+#define FSL_CORENET_DEVDISR_I2C1 0x00000020
+#define FSL_CORENET_DEVDISR_I2C2 0x00000010
+#define FSL_CORENET_DEVDISR_DUART1 0x00000002
+#define FSL_CORENET_DEVDISR_DUART2 0x00000001
+#define FSL_CORENET_DEVDISR2_PME 0x80000000
+#define FSL_CORENET_DEVDISR2_SEC 0x40000000
+#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
+#define FSL_CORENET_DEVDISR2_FM1 0x02000000
+#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
+#define FSL_CORENET_DEVDISR2_FM2 0x00020000
+#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
+#define FSL_CORENET_NUM_DEVDISR 2
+ u32 powmgtcsr; /* Power management status & control */
+#endif
+ u8 res8[12];
+ u32 coredisru; /* uppper portion for support of 64 cores */
+ u32 coredisrl; /* lower portion for support of 64 cores */
+ u8 res9[8];
+ u32 pvr; /* Processor version */
+ u32 svr; /* System version */
+ u8 res10[8];
+ u32 rstcr; /* Reset control */
+ u32 rstrqpblsr; /* Reset request preboot loader status */
+ u8 res11[8];
+ u32 rstrqmr1; /* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
+#endif
+ u8 res12[4];
+ u32 rstrqsr1; /* Reset request status */
+ u8 res13[4];
+ u8 res14[4];
+ u32 rstrqwdtmrl; /* Reset request WDT mask */
+ u8 res15[4];
+ u32 rstrqwdtsrl; /* Reset request WDT status */
+ u8 res16[4];
+ u32 brrl; /* Boot release */
+ u8 res17[24];
+ u32 rcwsr[16]; /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX 7
+#define RCW_SB_EN_MASK 0x00200000
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
+/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
+#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
+#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
+#define PXCKEN_MASK 0x80000000
+#define PXCK_MASK 0x00FF0000
+#define PXCK_BITS_START 16
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
+#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
+#define FSL_CORENET_RCWSR13_EC2 0x0c000000
+#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
+#define PXCKEN_MASK 0x80000000
+#define PXCK_MASK 0x00FF0000
+#define PXCK_BITS_START 16
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
+#endif
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
+#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
+#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
+#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
+#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
+#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
+#ifdef CONFIG_ARCH_P4080
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
+#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
+#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
+#endif
+#if defined(CONFIG_ARCH_P2041) || \
+ defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
+#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
+#endif
+#if defined(CONFIG_ARCH_P5040)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
+#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
+#endif
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
+#endif
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
+#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
+#endif
+ u8 res18[192];
+ u32 scratchrw[4]; /* Scratch Read/Write */
+ u8 res19[240];
+ u32 scratchw1r[4]; /* Scratch Read (Write once) */
+ u8 res20[240];
+ u32 scrtsr[8]; /* Core reset status */
+ u8 res21[224];
+ u32 pex1liodnr; /* PCI Express 1 LIODN */
+ u32 pex2liodnr; /* PCI Express 2 LIODN */
+ u32 pex3liodnr; /* PCI Express 3 LIODN */
+ u32 pex4liodnr; /* PCI Express 4 LIODN */
+ u32 rio1liodnr; /* RIO 1 LIODN */
+ u32 rio2liodnr; /* RIO 2 LIODN */
+ u32 rio3liodnr; /* RIO 3 LIODN */
+ u32 rio4liodnr; /* RIO 4 LIODN */
+ u32 usb1liodnr; /* USB 1 LIODN */
+ u32 usb2liodnr; /* USB 2 LIODN */
+ u32 usb3liodnr; /* USB 3 LIODN */
+ u32 usb4liodnr; /* USB 4 LIODN */
+ u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
+ u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
+ u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
+ u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
+ u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
+ u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
+ u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
+ u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
+ u32 sata1liodnr; /* SATA 1 LIODN */
+ u32 sata2liodnr; /* SATA 2 LIODN */
+ u32 sata3liodnr; /* SATA 3 LIODN */
+ u32 sata4liodnr; /* SATA 4 LIODN */
+ u8 res22[20];
+ u32 tdmliodnr; /* TDM LIODN */
+ u32 qeliodnr; /* QE LIODN */
+ u8 res_57c[4];
+ u32 dma1liodnr; /* DMA 1 LIODN */
+ u32 dma2liodnr; /* DMA 2 LIODN */
+ u32 dma3liodnr; /* DMA 3 LIODN */
+ u32 dma4liodnr; /* DMA 4 LIODN */
+ u8 res23[48];
+ u8 res24[64];
+ u32 pblsr; /* Preboot loader status */
+ u32 pamubypenr; /* PAMU bypass enable */
+ u32 dmacr1; /* DMA control */
+ u8 res25[4];
+ u32 gensr1; /* General status */
+ u8 res26[12];
+ u32 gencr1; /* General control */
+ u8 res27[12];
+ u8 res28[4];
+ u32 cgensrl; /* Core general status */
+ u8 res29[8];
+ u8 res30[4];
+ u32 cgencrl; /* Core general control */
+ u8 res31[184];
+ u32 sriopstecr; /* SRIO prescaler timer enable control */
+ u32 dcsrcr; /* DCSR Control register */
+ u8 res31a[56];
+ u32 tp_ityp[64]; /* Topology Initiator Type Register */
+ struct {
+ u32 upper;
+ u32 lower;
+ } tp_cluster[16]; /* Core Cluster n Topology Register */
+ u8 res32[1344];
+ u32 pmuxcr; /* Pin multiplexing control */
+ u8 res33[60];
+ u32 iovselsr; /* I/O voltage selection status */
+ u8 res34[28];
+ u32 ddrclkdr; /* DDR clock disable */
+ u8 res35;
+ u32 elbcclkdr; /* eLBC clock disable */
+ u8 res36[20];
+ u32 sdhcpcr; /* eSDHC polarity configuration */
+ u8 res37[380];
+} ccsr_gur_t;
+
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_OTHER 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+
+#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
+#define FSL_CORENET_DCSR_SZ_4M 0x0
+#define FSL_CORENET_DCSR_SZ_1G 0x3
+
+/*
+ * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
+ * everything after has RMan thus msg unit LIODN is used for maintenance
+ */
+#define rmuliodnr rio1maintliodnr
+
+typedef struct ccsr_clk {
+ struct {
+ u32 clkcncsr; /* core cluster n clock control status */
+ u8 res_004[0x0c];
+ u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
+ u8 res_014[0x0c];
+ } clkcsr[12];
+ u8 res_100[0x680]; /* 0x100 */
+ struct {
+ u32 pllcngsr;
+ u8 res10[0x1c];
+ } pllcgsr[12];
+ u8 res21[0x280];
+ u32 pllpgsr; /* 0xc00 Platform PLL General Status */
+ u8 res16[0x1c];
+ u32 plldgsr; /* 0xc20 DDR PLL General Status */
+ u8 res17[0x3dc];
+} ccsr_clk_t;
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+typedef struct ccsr_rcpm {
+ u8 res_00[12];
+ u32 tph10sr0; /* Thread PH10 Status Register */
+ u8 res_10[12];
+ u32 tph10setr0; /* Thread PH10 Set Control Register */
+ u8 res_20[12];
+ u32 tph10clrr0; /* Thread PH10 Clear Control Register */
+ u8 res_30[12];
+ u32 tph10psr0; /* Thread PH10 Previous Status Register */
+ u8 res_40[12];
+ u32 twaitsr0; /* Thread Wait Status Register */
+ u8 res_50[96];
+ u32 pcph15sr; /* Physical Core PH15 Status Register */
+ u32 pcph15setr; /* Physical Core PH15 Set Control Register */
+ u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
+ u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
+ u8 res_c0[16];
+ u32 pcph20sr; /* Physical Core PH20 Status Register */
+ u32 pcph20setr; /* Physical Core PH20 Set Control Register */
+ u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
+ u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
+ u32 pcpw20sr; /* Physical Core PW20 Status Register */
+ u8 res_e0[12];
+ u32 pcph30sr; /* Physical Core PH30 Status Register */
+ u32 pcph30setr; /* Physical Core PH30 Set Control Register */
+ u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
+ u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
+ u8 res_100[32];
+ u32 ippwrgatecr; /* IP Power Gating Control Register */
+ u8 res_124[12];
+ u32 powmgtcsr; /* Power Management Control & Status Reg */
+ u8 res_134[12];
+ u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
+ u8 res_150[12];
+ u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
+ u8 res_160[12];
+ u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
+ u8 res_170[12];
+ u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
+ u8 res_180[12];
+ u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
+ u8 res_190[12];
+ u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
+ u32 pctbenr; /* Physical Core Time Base Enable Reg */
+ u32 pctbclkselr; /* Physical Core Time Base Clock Select */
+ u32 tbclkdivr; /* Time Base Clock Divider Register */
+ u8 res_1ac[4];
+ u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
+ u32 clpcl10sr; /* Cluster PCL10 Status Register */
+ u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
+ u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
+ u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
+ u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
+ u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
+ u32 cdpwroksetr; /* Core Domain Power OK Set Register */
+ u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
+ u32 cdpwrensr; /* Core Domain Power Enable Status Register */
+ u32 cddslsr; /* Core Domain Deep Sleep Status Register */
+ u8 res_1e8[8];
+ u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
+ u8 res_300[3568];
+} ccsr_rcpm_t;
+
+#define ctbenrl pctbenr
+
+#else
+typedef struct ccsr_rcpm {
+ u8 res1[4];
+ u32 cdozsrl; /* Core Doze Status */
+ u8 res2[4];
+ u32 cdozcrl; /* Core Doze Control */
+ u8 res3[4];
+ u32 cnapsrl; /* Core Nap Status */
+ u8 res4[4];
+ u32 cnapcrl; /* Core Nap Control */
+ u8 res5[4];
+ u32 cdozpsrl; /* Core Doze Previous Status */
+ u8 res6[4];
+ u32 cdozpcrl; /* Core Doze Previous Control */
+ u8 res7[4];
+ u32 cwaitsrl; /* Core Wait Status */
+ u8 res8[8];
+ u32 powmgtcsr; /* Power Mangement Control & Status */
+ u8 res9[12];
+ u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
+ u8 res10[12];
+ u8 res11[4];
+ u32 cpmimrl; /* Core PM IRQ Masking */
+ u8 res12[4];
+ u32 cpmcimrl; /* Core PM Critical IRQ Masking */
+ u8 res13[4];
+ u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
+ u8 res14[4];
+ u32 cpmnmimrl; /* Core PM NMI Masking */
+ u8 res15[4];
+ u32 ctbenrl; /* Core Time Base Enable */
+ u8 res16[4];
+ u32 ctbclkselrl; /* Core Time Base Clock Select */
+ u8 res17[4];
+ u32 ctbhltcrl; /* Core Time Base Halt Control */
+ u8 res18[0xf68];
+} ccsr_rcpm_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#else
+typedef struct ccsr_gur {
+ u32 porpllsr; /* POR PLL ratio status */
+#ifdef CONFIG_ARCH_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
+#elif defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
+ & MPC85xx_PORDEVSR2_DDR_SPD_0) \
+ >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
+#else
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
+#endif
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
+#endif
+#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
+#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
+#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
+#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
+ u32 porbmsr; /* POR boot mode status */
+#define MPC85xx_PORBMSR_HA 0x00070000
+#define MPC85xx_PORBMSR_HA_SHIFT 16
+#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
+#define PORBMSR_ROMLOC_SPI 0x6
+#define PORBMSR_ROMLOC_SDHC 0x7
+#define PORBMSR_ROMLOC_NAND_2K 0x9
+#define PORBMSR_ROMLOC_NOR 0xf
+ u32 porimpscr; /* POR I/O impedance status & control */
+ u32 pordevsr; /* POR I/O device status regsiter */
+#if defined(CONFIG_ARCH_P1023)
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
+#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
+#else
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
+#endif
+#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
+#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
+#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
+#define MPC85xx_PORDEVSR_PCI1 0x00800000
+#if defined(CONFIG_ARCH_P1022)
+#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
+#elif defined(CONFIG_ARCH_P1023)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
+#else
+#if defined(CONFIG_ARCH_P1010)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
+#elif defined(CONFIG_ARCH_BSC9132)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
+#elif defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
+#else
+#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
+#endif /* if defined(CONFIG_ARCH_P1010) */
+#endif
+#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
+#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
+#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
+#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
+ u32 pordbgmsr; /* POR debug mode status */
+ u32 pordevsr2; /* POR I/O device status 2 */
+#if defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
+#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
+#endif
+#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
+/* The 8544 RM says this is bit 26, but it's really bit 24 */
+#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
+ u8 res1[8];
+ u32 gpporcr; /* General-purpose POR configuration */
+ u8 res2[12];
+#if defined(CONFIG_ARCH_MPC8536)
+ u32 gencfgr; /* General Configuration Register */
+#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
+#else
+ u32 gpiocr; /* GPIO control */
+#endif
+ u8 res3[12];
+#if defined(CONFIG_ARCH_MPC8569)
+ u32 plppar1; /* Platform port pin assignment 1 */
+ u32 plppar2; /* Platform port pin assignment 2 */
+ u32 plpdir1; /* Platform port pin direction 1 */
+ u32 plpdir2; /* Platform port pin direction 2 */
+#else
+ u32 gpoutdr; /* General-purpose output data */
+ u8 res4[12];
+#endif
+ u32 gpindr; /* General-purpose input data */
+ u8 res5[12];
+ u32 pmuxcr; /* Alt. function signal multiplex control */
+#if defined(CONFIG_ARCH_P1010)
+#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
+#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
+#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
+#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
+#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
+#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
+#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
+#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
+#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
+#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
+#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
+#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
+#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
+#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
+#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
+#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
+#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
+#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
+#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
+#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
+#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
+#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
+#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
+#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
+#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
+#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
+#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
+#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
+#define MPC85xx_PMUXCR_SPI_RES 0x00000030
+#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
+#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
+#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
+#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
+#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
+#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
+#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
+#endif
+#if defined(CONFIG_ARCH_P1023)
+#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
+#else
+#define MPC85xx_PMUXCR_SD_DATA 0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
+#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
+#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
+#define MPC85xx_PMUXCR_QE0 0x00008000
+#define MPC85xx_PMUXCR_QE1 0x00004000
+#define MPC85xx_PMUXCR_QE2 0x00002000
+#define MPC85xx_PMUXCR_QE3 0x00001000
+#define MPC85xx_PMUXCR_QE4 0x00000800
+#define MPC85xx_PMUXCR_QE5 0x00000400
+#define MPC85xx_PMUXCR_QE6 0x00000200
+#define MPC85xx_PMUXCR_QE7 0x00000100
+#define MPC85xx_PMUXCR_QE8 0x00000080
+#define MPC85xx_PMUXCR_QE9 0x00000040
+#define MPC85xx_PMUXCR_QE10 0x00000020
+#define MPC85xx_PMUXCR_QE11 0x00000010
+#define MPC85xx_PMUXCR_QE12 0x00000008
+#endif
+#if defined(CONFIG_ARCH_P1022)
+#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
+#define MPC85xx_PMUXCR_TDM 0x00014800
+#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
+#define MPC85xx_PMUXCR_SPI 0x00000000
+#endif
+#if defined(CONFIG_ARCH_BSC9131)
+#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
+#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
+#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
+#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
+#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
+#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
+#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
+#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
+#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
+#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
+#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
+#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
+#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
+#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
+#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
+#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
+#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
+#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
+#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
+#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
+#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
+#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
+#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
+#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
+#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
+#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
+#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
+#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
+#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
+#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
+#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
+#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
+#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
+#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
+#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
+#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
+#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
+#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
+#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
+#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
+#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
+#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
+#endif
+#ifdef CONFIG_ARCH_BSC9132
+#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
+#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
+#endif
+#if defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
+#define MPC85xx_PMUXCR_SPI 0x00000000
+#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
+#endif
+ u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_ARCH_P1010)
+#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
+#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
+#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
+#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
+#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
+#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
+#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
+#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
+#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
+#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
+#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
+#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
+#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
+#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
+#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
+#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
+#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
+#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
+#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
+#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
+#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
+#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
+#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
+#endif
+#if defined(CONFIG_ARCH_P1022)
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
+#define MPC85xx_PMUXCR2_USB 0x00150000
+#endif
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131)
+#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
+#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
+#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
+#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
+#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
+#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
+#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
+#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
+#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
+#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
+#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
+#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
+#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
+#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
+#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
+#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
+#endif
+ u32 pmuxcr3;
+#if defined(CONFIG_ARCH_BSC9131)
+#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
+#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
+#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
+#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
+#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
+#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
+#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
+#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
+#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
+#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
+#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
+#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
+#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
+#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
+#endif
+#ifdef CONFIG_ARCH_BSC9132
+#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
+#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
+#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
+#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
+#endif
+ u32 pmuxcr4;
+#else
+ u8 res6[8];
+#endif
+ u32 devdisr; /* Device disable control */
+#define MPC85xx_DEVDISR_PCI1 0x80000000
+#define MPC85xx_DEVDISR_PCI2 0x40000000
+#define MPC85xx_DEVDISR_PCIE 0x20000000
+#define MPC85xx_DEVDISR_LBC 0x08000000
+#define MPC85xx_DEVDISR_PCIE2 0x04000000
+#define MPC85xx_DEVDISR_PCIE3 0x02000000
+#define MPC85xx_DEVDISR_SEC 0x01000000
+#define MPC85xx_DEVDISR_SRIO 0x00080000
+#define MPC85xx_DEVDISR_RMSG 0x00040000
+#define MPC85xx_DEVDISR_DDR 0x00010000
+#define MPC85xx_DEVDISR_CPU 0x00008000
+#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
+#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1 0x00002000
+#define MPC85xx_DEVDISR_TB1 0x00001000
+#define MPC85xx_DEVDISR_DMA 0x00000400
+#define MPC85xx_DEVDISR_TSEC1 0x00000080
+#define MPC85xx_DEVDISR_TSEC2 0x00000040
+#define MPC85xx_DEVDISR_TSEC3 0x00000020
+#define MPC85xx_DEVDISR_TSEC4 0x00000010
+#define MPC85xx_DEVDISR_I2C 0x00000004
+#define MPC85xx_DEVDISR_DUART 0x00000002
+ u8 res7[12];
+ u32 powmgtcsr; /* Power management status & control */
+ u8 res8[12];
+ u32 mcpsumr; /* Machine check summary */
+ u8 res9[12];
+ u32 pvr; /* Processor version */
+ u32 svr; /* System version */
+ u8 res10[8];
+ u32 rstcr; /* Reset control */
+#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
+ u8 res11a[76];
+ par_io_t qe_par_io[7];
+ u8 res11b[1600];
+#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
+ u8 res11a[12];
+ u32 iovselsr;
+ u8 res11b[60];
+ par_io_t qe_par_io[3];
+ u8 res11c[1496];
+#else
+ u8 res11a[1868];
+#endif
+ u32 clkdvdr; /* Clock Divide register */
+ u8 res12[1532];
+ u32 clkocr; /* Clock out select */
+ u8 res13[12];
+ u32 ddrdllcr; /* DDR DLL control */
+ u8 res14[12];
+ u32 lbcdllcr; /* LBC DLL control */
+#if defined(CONFIG_ARCH_BSC9131)
+ u8 res15[12];
+ u32 halt_req_mask;
+#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
+ u8 res18[232];
+#else
+ u8 res15[248];
+#endif
+ u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
+ u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
+ u32 ddrioovcr; /* DDR IO Override Control */
+ u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
+ u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
+ u8 res16[52];
+ u32 sdhcdcr; /* SDHC debug control register */
+ u8 res17[61592];
+} ccsr_gur_t;
+#endif
+
+#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define MAX_SERDES 4
+#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#define SRDS_MAX_LANES 4
+#else
+#define SRDS_MAX_LANES 8
+#endif
+#define SRDS_MAX_BANK 2
+typedef struct serdes_corenet {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+#define SRDS_RSTCTL_RST 0x80000000
+#define SRDS_RSTCTL_RSTDONE 0x40000000
+#define SRDS_RSTCTL_RSTERR 0x20000000
+#define SRDS_RSTCTL_SWRST 0x10000000
+#define SRDS_RSTCTL_SDEN 0x00000020
+#define SRDS_RSTCTL_SDRST_B 0x00000040
+#define SRDS_RSTCTL_PLLRST_B 0x00000080
+#define SRDS_RSTCTL_RSTERR_SHIFT 29
+ u32 pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF 0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_PLL_LCK 0x00800000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
+#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
+#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
+ u32 pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_BCAP_EN 0x20000000
+#define SRDS_PLLCR1_BCAP_OVD 0x10000000
+#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+#define SRDS_PLLCR1_BYP_CAL 0x02000000
+ u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN 0x00800000
+#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
+#define SRDS_PLLSR2_FCAP 0x003F0000
+#define SRDS_PLLSR2_FCAP_SHIFT 16
+#define SRDS_PLLSR2_DCBIAS 0x000F0000
+#define SRDS_PLLSR2_DCBIAS_SHIFT 16
+ u32 pllcr3;
+ u32 pllcr4;
+ u8 res_18[0x20-0x18];
+ } bank[2];
+ u8 res_40[0x90-0x40];
+ u32 srdstcalcr; /* 0x90 TX Calibration Control */
+ u8 res_94[0xa0-0x94];
+ u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
+ u8 res_a4[0xb0-0xa4];
+ u32 srdsgr0; /* 0xb0 General Register 0 */
+ u8 res_b4[0xe0-0xb4];
+ u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
+ u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
+ u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
+ u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
+ u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
+ u8 res_f4[0x100-0xf4];
+ struct {
+ u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+ u8 res_104[0x120-0x104];
+ } srdslnpssr[8];
+ u8 res_200[0x800-0x200];
+ struct {
+ u32 gcr0; /* 0x800 General Control Register 0 */
+ u32 gcr1; /* 0x804 General Control Register 1 */
+ u32 gcr2; /* 0x808 General Control Register 2 */
+ u32 res_80c;
+ u32 recr0; /* 0x810 Receive Equalization Control */
+ u32 res_814;
+ u32 tecr0; /* 0x818 Transmit Equalization Control */
+ u32 res_81c;
+ u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
+ u8 res_824[0x840-0x824];
+ } lane[8]; /* Lane A, B, C, D, E, F, G, H */
+ u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
+} serdes_corenet_t;
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define SRDS_MAX_LANES 18
+#define SRDS_MAX_BANK 3
+typedef struct serdes_corenet {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+#define SRDS_RSTCTL_RST 0x80000000
+#define SRDS_RSTCTL_RSTDONE 0x40000000
+#define SRDS_RSTCTL_RSTERR 0x20000000
+#define SRDS_RSTCTL_SDPD 0x00000020
+ u32 pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
+#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
+#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
+ u32 pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+ u32 res[5];
+ } bank[3];
+ u32 res1[12];
+ u32 srdstcalcr; /* TX Calibration Control */
+ u32 res2[3];
+ u32 srdsrcalcr; /* RX Calibration Control */
+ u32 res3[3];
+ u32 srdsgr0; /* General Register 0 */
+ u32 res4[11];
+ u32 srdspccr0; /* Protocol Converter Config 0 */
+ u32 srdspccr1; /* Protocol Converter Config 1 */
+ u32 srdspccr2; /* Protocol Converter Config 2 */
+#define SRDS_PCCR2_RST_XGMII1 0x00800000
+#define SRDS_PCCR2_RST_XGMII2 0x00400000
+ u32 res5[197];
+ struct serdes_lane {
+ u32 gcr0; /* General Control Register 0 */
+#define SRDS_GCR0_RRST 0x00400000
+#define SRDS_GCR0_1STLANE 0x00010000
+#define SRDS_GCR0_UOTHL 0x00100000
+ u32 gcr1; /* General Control Register 1 */
+#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
+#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
+#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
+#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
+#define SRDS_GCR1_OPAD_CTL 0x04000000
+ u32 res1[4];
+ u32 tecr0; /* TX Equalization Control Reg 0 */
+#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
+#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
+ u32 res3;
+ u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
+#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
+#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
+#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
+#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
+#define SRDS_TTLCR0_PM_DIS 0x00004000
+#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
+ u32 res4[7];
+ } lane[24];
+ u32 res6[384];
+} serdes_corenet_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+enum {
+ FSL_SRDS_B1_LANE_A = 0,
+ FSL_SRDS_B1_LANE_B = 1,
+ FSL_SRDS_B1_LANE_C = 2,
+ FSL_SRDS_B1_LANE_D = 3,
+ FSL_SRDS_B1_LANE_E = 4,
+ FSL_SRDS_B1_LANE_F = 5,
+ FSL_SRDS_B1_LANE_G = 6,
+ FSL_SRDS_B1_LANE_H = 7,
+ FSL_SRDS_B1_LANE_I = 8,
+ FSL_SRDS_B1_LANE_J = 9,
+ FSL_SRDS_B2_LANE_A = 16,
+ FSL_SRDS_B2_LANE_B = 17,
+ FSL_SRDS_B2_LANE_C = 18,
+ FSL_SRDS_B2_LANE_D = 19,
+ FSL_SRDS_B3_LANE_A = 20,
+ FSL_SRDS_B3_LANE_B = 21,
+ FSL_SRDS_B3_LANE_C = 22,
+ FSL_SRDS_B3_LANE_D = 23,
+};
+
+typedef struct ccsr_pme {
+ u8 res0[0x804];
+ u32 liodnbr; /* LIODN Base Register */
+ u8 res1[0x1f8];
+ u32 srcidr; /* Source ID Register */
+ u8 res2[8];
+ u32 liodnr; /* LIODN Register */
+ u8 res3[0x1e8];
+ u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
+ u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
+ u8 res4[0x400];
+} ccsr_pme_t;
+
+struct ccsr_pamu {
+ u32 ppbah;
+ u32 ppbal;
+ u32 pplah;
+ u32 pplal;
+ u32 spbah;
+ u32 spbal;
+ u32 splah;
+ u32 splal;
+ u32 obah;
+ u32 obal;
+ u32 olah;
+ u32 olal;
+};
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct ccsr_raide {
+ u8 res0[0x543];
+ u32 liodnbr; /* LIODN Base Register */
+ u8 res1[0xab8];
+ struct {
+ struct {
+ u32 cfg0; /* cfg register 0 */
+ u32 cfg1; /* cfg register 1 */
+ u8 res1[0x3f8];
+ } ring[2];
+ u8 res[0x800];
+ } jq[2];
+};
+#endif
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct ccsr_rman {
+ u8 res0[0xf64];
+ u32 mmliodnbr; /* Message Manager LIODN Base Register */
+ u32 mmitar; /* RMAN Inbound Translation Address Register */
+ u32 mmitdr; /* RMAN Inbound Translation Data Register */
+ u8 res4[0x1f090];
+};
+#endif
+
+#ifdef CONFIG_SYS_PMAN
+struct ccsr_pman {
+ u8 res_00[0x40];
+ u32 poes1; /* PMAN Operation Error Status Register 1 */
+ u32 poes2; /* PMAN Operation Error Status Register 2 */
+ u32 poeah; /* PMAN Operation Error Address High */
+ u32 poeal; /* PMAN Operation Error Address Low */
+ u8 res_50[0x50];
+ u32 pr1; /* PMAN Revision Register 1 */
+ u32 pr2; /* PMAN Revision Register 2 */
+ u8 res_a8[0x8];
+ u32 pcap; /* PMAN Capabilities Register */
+ u8 res_b4[0xc];
+ u32 pc1; /* PMAN Control Register 1 */
+ u32 pc2; /* PMAN Control Register 2 */
+ u32 pc3; /* PMAN Control Register 3 */
+ u32 pc4; /* PMAN Control Register 4 */
+ u32 pc5; /* PMAN Control Register 5 */
+ u32 pc6; /* PMAN Control Register 6 */
+ u8 res_d8[0x8];
+ u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
+ u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
+ u8 res_e8[0x8];
+ u32 pics; /* PMAN Interrupt Control and Status */
+ u8 res_f4[0xf0c];
+};
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#ifdef CONFIG_SYS_PMAN
+#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
+#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
+#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
+#endif
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
+#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
+#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
+#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ * * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET 0x200
+#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET 0xE8000
+#endif
+#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
+#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
+#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
+#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
+#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
+#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
+#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
+#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
+#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
+#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
+#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
+ !defined(CONFIG_ARCH_B4420)
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
+#else
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
+#endif
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
+#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
+#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
+#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
+#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
+#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
+#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
+#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
+#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
+#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
+#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
+#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
+#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
+#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
+#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
+#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
+#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
+#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
+#else
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
+#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
+#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
+#else
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
+#endif
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
+#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
+#ifdef CONFIG_TSECV2
+#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
+#elif defined(CONFIG_TSECV2_1)
+#define CONFIG_SYS_TSEC1_OFFSET 0x10000
+#else
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#endif
+#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
+#if defined(CONFIG_ARCH_C29X)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
+#else
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
+#endif
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
+#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
+#define CONFIG_SYS_SFP_OFFSET 0xE7000
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
+#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
+#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
+#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
+#endif
+
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
+#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
+
+#if defined(CONFIG_ARCH_BSC9132)
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
+ (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
+#endif
+
+#define CONFIG_SYS_FSL_CPC_ADDR \
+ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_ADDR \
+ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
+ (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
+ (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
+#define CONFIG_SYS_FSL_QMAN_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
+#define CONFIG_SYS_FSL_BMAN_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
+#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_ECM_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CONFIG_SYS_FSL_DDR_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_FSL_DDR2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_FSL_DDR3_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
+#define CONFIG_SYS_LBC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_IFC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
+#define CONFIG_SYS_MPC85xx_L2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
+#define CONFIG_SYS_MPC85xx_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
+#define CONFIG_SYS_MPC85xx_CPM_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CONFIG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CONFIG_SYS_FSL_FM2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
+#define CONFIG_SYS_FSL_SRIO_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CONFIG_SYS_PAMU_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
+
+#define CONFIG_SYS_PCI1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+#define CONFIG_SYS_PCI2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+#define CONFIG_SYS_PCIE1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+#define CONFIG_SYS_PCIE2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+#define CONFIG_SYS_PCIE3_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+#define CONFIG_SYS_PCIE4_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+
+#define CONFIG_SYS_SFP_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
+#define CONFIG_SYS_SEC_MON_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+struct ccsr_cluster_l2 {
+ u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
+ u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
+ u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
+ u8 res_0c[500];/* 0x00c - 0x1ff */
+ u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
+ u8 res_204[4];
+ u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
+ u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
+ u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
+ u8 res_214[4];
+ u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
+ u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
+ u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
+ u8 res_224[4];
+ u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
+ u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
+ u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
+ u8 res_234[4];
+ u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
+ u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
+ u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
+ u8 res244[4];
+ u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
+ u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
+ u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
+ u8 res_254[4];
+ u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
+ u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
+ u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
+ u8 res_264[4];
+ u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
+ u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
+ u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
+ u8 res274[4];
+ u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
+ u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
+ u8 res_280[0xb80]; /* 0x280 - 0xdff */
+ u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
+ u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
+ u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
+ u8 res_e0c[20]; /* 0xe0c - 0x01f */
+ u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
+ u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
+ u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
+ u8 res_e2c[20]; /* 0xe2c - 0xe3f */
+ u32 l2errdet; /* 0xe40 L2 cache error detect */
+ u32 l2errdis; /* 0xe44 L2 cache error disable */
+ u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
+ u32 l2errattr; /* 0xe4c L2 cache error attribute */
+ u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
+ u32 l2erraddr; /* 0xe54 L2 cache error address */
+ u32 l2errctl; /* 0xe58 L2 cache error control */
+};
+#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
+struct dcsr_dcfg_regs {
+ u8 res_0[0x520];
+ u32 ecccr1;
+#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
+#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
+ u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
+};
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+ u32 dpslpcr; /* 0x000 Deep Sleep Control register */
+ u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
+ u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
+ u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
+ u32 res1[4];
+ u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
+ u32 res2;
+ u32 pixclkcr; /* 0x028 Pixel Clock Control register */
+ u32 res3[245];
+ u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
+ u32 emiiocr; /* 0x404 EMI MDIO Control Register */
+ u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
+ u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
+ u32 res4[60];
+ u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
+};
+#endif /*__IMMAP_85xx__*/
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
new file mode 100644
index 0000000..1fbc63a
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -0,0 +1,1221 @@
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Copyright 2004, 2011 Freescale Semiconductor
+ * Jeff Brown (Jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ */
+
+#ifndef __IMMAP_86xx__
+#define __IMMAP_86xx__
+
+#include <fsl_immap.h>
+#include <asm/types.h>
+#include <asm/fsl_dma.h>
+#include <asm/fsl_lbc.h>
+#include <asm/fsl_i2c.h>
+
+/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
+typedef struct ccsr_local_mcm {
+ uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
+ char res1[4];
+ uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
+ char res2[4];
+ uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
+ char res3[12];
+ uint bptr; /* 0x20 - Boot Page Translation Register */
+ char res4[3044];
+ uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
+ char res5[4];
+ uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
+ char res6[20];
+ uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
+ char res7[4];
+ uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
+ char res8[20];
+ uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
+ char res9[4];
+ uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
+ char res10[20];
+ uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
+ char res11[4];
+ uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
+ char res12[20];
+ uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
+ char res13[4];
+ uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
+ char res14[20];
+ uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
+ char res15[4];
+ uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
+ char res16[20];
+ uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
+ char res17[4];
+ uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
+ char res18[20];
+ uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
+ char res19[4];
+ uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
+ char res20[20];
+ uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
+ char res21[4];
+ uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
+ char res22[20];
+ uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
+ char res23[4];
+ uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
+ char res24[716];
+ uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
+ char res25[4];
+ uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
+ char res26[4];
+ uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
+ char res27[44];
+ uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
+ uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
+ uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
+ uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
+ char res28[16];
+ uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
+ uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
+ uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
+ char res29[3476];
+ uint edr; /* 0x1e00 - MCM Error Detect Register */
+ char res30[4];
+ uint eer; /* 0x1e08 - MCM Error Enable Register */
+ uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
+ uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
+ uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
+ char res31[488];
+} ccsr_local_mcm_t;
+
+/* Daul I2C Registers(0x3000-0x4000) */
+typedef struct ccsr_i2c {
+ struct fsl_i2c_base i2c[2];
+ u8 res[4096 - 2 * sizeof(struct fsl_i2c_base)];
+} ccsr_i2c_t;
+
+/* DUART Registers(0x4000-0x5000) */
+typedef struct ccsr_duart {
+ char res1[1280];
+ u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
+ u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
+ u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
+ u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
+ u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
+ u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
+ u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
+ u_char uscr1; /* 0x4507 - UART1 Scratch Register */
+ char res2[8];
+ u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
+ char res3[239];
+ u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
+ u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
+ u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
+ u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
+ u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
+ u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
+ u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
+ u_char uscr2; /* 0x4607 - UART2 Scratch Register */
+ char res4[8];
+ u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
+ char res5[2543];
+} ccsr_duart_t;
+
+/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
+typedef struct ccsr_pex {
+ uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
+ uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
+ char res1[4];
+ uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
+ char res2[16];
+ uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
+ uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
+ uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
+ uint pm_command; /* 0x802c - PEX PM Command register */
+ char res3[3016];
+ uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
+ uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
+ uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
+ uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
+ char res4[8];
+ uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
+ char res5[12];
+ uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
+ uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
+ uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
+ char res6[4];
+ uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
+ char res7[12];
+ uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
+ uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
+ uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
+ char res8[4];
+ uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
+ char res9[12];
+ uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
+ uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
+ uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
+ char res10[4];
+ uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
+ char res11[12];
+ uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
+ uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
+ uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
+ char res12[4];
+ uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
+ char res13[12];
+ char res14[256];
+ uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
+ char res15[4];
+ uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
+ uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
+ uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
+ char res16[12];
+ uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
+ char res17[4];
+ uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
+ uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
+ uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
+ char res18[12];
+ uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
+ char res19[4];
+ uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
+ uint piwbear1;
+ uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
+ char res20[12];
+ uint pedr; /* 0x8e00 - PEX Error Detect Register */
+ char res21[4];
+ uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
+ char res22[4];
+ uint pecdr; /* 0x8e10 - PEX Error Disable Register */
+ char res23[12];
+ uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
+ char res24[4];
+ uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
+ uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
+ uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
+ uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
+ char res25[452];
+ char res26[4];
+} ccsr_pex_t;
+
+/* Hyper Transport Register Block (0xA000-0xB000) */
+typedef struct ccsr_ht {
+ uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
+ uint hcfg_data; /* 0xa004 - HT Configuration Data register */
+ char res1[3064];
+ uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
+ char res2[12];
+ uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
+ char res3[12];
+ uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
+ char res4[4];
+ uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
+ char res5[4];
+ uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
+ char res6[12];
+ uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
+ char res7[4];
+ uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
+ char res8[4];
+ uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
+ char res9[12];
+ uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
+ char res10[4];
+ uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
+ char res11[4];
+ uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
+ char res12[12];
+ uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
+ char res13[4];
+ uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
+ char res14[4];
+ uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
+ char res15[236];
+ uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
+ char res16[4];
+ uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
+ char res17[4];
+ uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
+ char res18[12];
+ uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
+ char res19[4];
+ uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
+ char res20[4];
+ uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
+ char res21[12];
+ uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
+ char res22[4];
+ uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
+ char res23[4];
+ uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
+ char res24[12];
+ uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
+ char res25[4];
+ uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
+ char res26[4];
+ uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
+ char res27[12];
+ uint hedr; /* 0xae00 - HT Error Detect register */
+ char res28[4];
+ uint heier; /* 0xae08 - HT Error Interrupt Enable register */
+ char res29[4];
+ uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
+ char res30[12];
+ uint hecsr; /* 0xae20 - HT Error Capture Status register */
+ char res31[4];
+ uint hec0; /* 0xae28 - HT Error Capture 0 register */
+ uint hec1; /* 0xae2c - HT Error Capture 1 register */
+ uint hec2; /* 0xae30 - HT Error Capture 2 register */
+ char res32[460];
+} ccsr_ht_t;
+
+/* DMA Registers(0x2_1000-0x2_2000) */
+typedef struct ccsr_dma {
+ char res1[256];
+ struct fsl_dma dma[4];
+ uint dgsr; /* 0x21300 - DMA General Status Register */
+ char res2[3324];
+} ccsr_dma_t;
+
+/* tsec1-4: 24000-28000 */
+typedef struct ccsr_tsec {
+ uint id; /* 0x24000 - Controller ID Register */
+ char res1[12];
+ uint ievent; /* 0x24010 - Interrupt Event Register */
+ uint imask; /* 0x24014 - Interrupt Mask Register */
+ uint edis; /* 0x24018 - Error Disabled Register */
+ char res2[4];
+ uint ecntrl; /* 0x24020 - Ethernet Control Register */
+ char res2_1[4];
+ uint ptv; /* 0x24028 - Pause Time Value Register */
+ uint dmactrl; /* 0x2402c - DMA Control Register */
+ uint tbipa; /* 0x24030 - TBI PHY Address Register */
+ char res3[88];
+ uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
+ char res4[8];
+ uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
+ uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
+ char res4_1[4];
+ uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
+ uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
+ char res5[84];
+ uint tctrl; /* 0x24100 - Transmit Control Register */
+ uint tstat; /* 0x24104 - Transmit Status Register */
+ uint dfvlan; /* 0x24108 - Default VLAN control word */
+ char res6[4];
+ uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
+ uint tqueue; /* 0x24114 - Transmit Queue Control Register */
+ char res7[40];
+ uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
+ uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
+ char res8[52];
+ uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
+ char res9[4];
+ uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
+ char res10[4];
+ uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
+ char res11[4];
+ uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
+ char res12[4];
+ uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
+ char res13[4];
+ uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
+ char res14[4];
+ uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
+ char res15[4];
+ uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
+ char res16[4];
+ uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
+ char res17[64];
+ uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
+ uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
+ char res18[4];
+ uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
+ char res19[4];
+ uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
+ char res20[4];
+ uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
+ char res21[4];
+ uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
+ char res22[4];
+ uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
+ char res23[4];
+ uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
+ char res24[4];
+ uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
+ char res25[192];
+ uint rctrl; /* 0x24300 - Receive Control Register */
+ uint rstat; /* 0x24304 - Receive Status Register */
+ char res26[8];
+ uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
+ uint rqueue; /* 0x24314 - Receive queue control register */
+ char res27[24];
+ uint rbifx; /* 0x24330 - Receive bit field extract control Register */
+ uint rqfar; /* 0x24334 - Receive queue filing table address Register */
+ uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
+ uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
+ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
+ char res28[56];
+ uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
+ char res29[4];
+ uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
+ char res30[4];
+ uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
+ char res31[4];
+ uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
+ char res32[4];
+ uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
+ char res33[4];
+ uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
+ char res34[4];
+ uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
+ char res35[4];
+ uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
+ char res36[4];
+ uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
+ char res37[64];
+ uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
+ uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
+ char res38[4];
+ uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
+ char res39[4];
+ uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
+ char res40[4];
+ uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
+ char res41[4];
+ uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
+ char res42[4];
+ uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
+ char res43[4];
+ uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
+ char res44[4];
+ uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
+ char res45[192];
+ uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
+ uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
+ uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
+ uint hafdup; /* 0x2450c - Half Duplex Register */
+ uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
+ char res46[12];
+ uint miimcfg; /* 0x24520 - MII Management Configuration Register */
+ uint miimcom; /* 0x24524 - MII Management Command Register */
+ uint miimadd; /* 0x24528 - MII Management Address Register */
+ uint miimcon; /* 0x2452c - MII Management Control Register */
+ uint miimstat; /* 0x24530 - MII Management Status Register */
+ uint miimind; /* 0x24534 - MII Management Indicator Register */
+ uint ifctrl; /* 0x24538 - Interface Contrl Register */
+ uint ifstat; /* 0x2453c - Interface Status Register */
+ uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
+ uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
+ uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
+ uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
+ uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
+ uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
+ uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
+ uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
+ uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
+ uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
+ uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
+ uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
+ uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
+ uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
+ uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
+ uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
+ uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
+ uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
+ uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
+ uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
+ uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
+ uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
+ uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
+ uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
+ uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
+ uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
+ uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
+ uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
+ uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
+ uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
+ uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
+ uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
+ char res48[192];
+ uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
+ uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
+ uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
+ uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
+ uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
+ uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
+ uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
+ uint rbyt; /* 0x2469c - Receive Byte Counter */
+ uint rpkt; /* 0x246a0 - Receive Packet Counter */
+ uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
+ uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
+ uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
+ uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
+ uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
+ uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
+ uint raln; /* 0x246bc - Receive Alignment Error Counter */
+ uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
+ uint rcde; /* 0x246c4 - Receive Code Error Counter */
+ uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
+ uint rund; /* 0x246cc - Receive Undersize Packet Counter */
+ uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
+ uint rfrg; /* 0x246d4 - Receive Fragments Counter */
+ uint rjbr; /* 0x246d8 - Receive Jabber Counter */
+ uint rdrp; /* 0x246dc - Receive Drop Counter */
+ uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
+ uint tpkt; /* 0x246e4 - Transmit Packet Counter */
+ uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
+ uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
+ uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
+ uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
+ uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
+ uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
+ uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
+ uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
+ uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
+ uint tncl; /* 0x2470c - Transmit Total Collision Counter */
+ char res49[4];
+ uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
+ uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
+ uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
+ uint txcf; /* 0x24720 - Transmit Control Frame Counter */
+ uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
+ uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
+ uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
+ uint car1; /* 0x24730 - Carry Register One */
+ uint car2; /* 0x24734 - Carry Register Two */
+ uint cam1; /* 0x24738 - Carry Mask Register One */
+ uint cam2; /* 0x2473c - Carry Mask Register Two */
+ uint rrej; /* 0x24740 - Receive filer rejected packet counter */
+ char res50[188];
+ uint iaddr0; /* 0x24800 - Indivdual address register 0 */
+ uint iaddr1; /* 0x24804 - Indivdual address register 1 */
+ uint iaddr2; /* 0x24808 - Indivdual address register 2 */
+ uint iaddr3; /* 0x2480c - Indivdual address register 3 */
+ uint iaddr4; /* 0x24810 - Indivdual address register 4 */
+ uint iaddr5; /* 0x24814 - Indivdual address register 5 */
+ uint iaddr6; /* 0x24818 - Indivdual address register 6 */
+ uint iaddr7; /* 0x2481c - Indivdual address register 7 */
+ char res51[96];
+ uint gaddr0; /* 0x24880 - Global address register 0 */
+ uint gaddr1; /* 0x24884 - Global address register 1 */
+ uint gaddr2; /* 0x24888 - Global address register 2 */
+ uint gaddr3; /* 0x2488c - Global address register 3 */
+ uint gaddr4; /* 0x24890 - Global address register 4 */
+ uint gaddr5; /* 0x24894 - Global address register 5 */
+ uint gaddr6; /* 0x24898 - Global address register 6 */
+ uint gaddr7; /* 0x2489c - Global address register 7 */
+ char res52[352];
+ uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
+ char res53[500];
+ uint attr; /* 0x24BF8 - DMA Attribute register */
+ uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
+ char res54[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers(0x4_0000-0x6_1000) */
+
+typedef struct ccsr_pic {
+ char res1[64];
+ uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
+ char res2[12];
+ uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
+ char res3[12];
+ uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
+ char res4[12];
+ uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
+ char res5[12];
+ uint ctpr; /* 0x40080 - Current Task Priority Register */
+ char res6[12];
+ uint whoami; /* 0x40090 - Who Am I Register */
+ char res7[12];
+ uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
+ char res8[12];
+ uint eoi; /* 0x400b0 - End Of Interrupt Register */
+ char res9[3916];
+ uint frr; /* 0x41000 - Feature Reporting Register */
+ char res10[28];
+ uint gcr; /* 0x41020 - Global Configuration Register */
+#define MPC86xx_PICGCR_RST 0x80000000
+#define MPC86xx_PICGCR_MODE 0x20000000
+ char res11[92];
+ uint vir; /* 0x41080 - Vendor Identification Register */
+ char res12[12];
+ uint pir; /* 0x41090 - Processor Initialization Register */
+ char res13[12];
+ uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
+ char res14[12];
+ uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
+ char res15[12];
+ uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
+ char res16[12];
+ uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
+ char res17[12];
+ uint svr; /* 0x410e0 - Spurious Vector Register */
+ char res18[12];
+ uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
+ char res19[12];
+ uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
+ char res20[12];
+ uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
+ char res21[12];
+ uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
+ char res22[12];
+ uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
+ char res23[12];
+ uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
+ char res24[12];
+ uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
+ char res25[12];
+ uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
+ char res26[12];
+ uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
+ char res27[12];
+ uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
+ char res28[12];
+ uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
+ char res29[12];
+ uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
+ char res30[12];
+ uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
+ char res31[12];
+ uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
+ char res32[12];
+ uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
+ char res33[12];
+ uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
+ char res34[12];
+ uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
+ char res35[268];
+ uint tcr; /* 0x41300 - Timer Control Register */
+ char res36[12];
+ uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
+ char res37[12];
+ uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
+ char res38[12];
+ uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
+ char res39[12];
+ uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
+ char res40[12];
+ uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
+ char res41[12];
+ uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
+ char res42[12];
+ uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
+ char res43[12];
+ uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
+ char res44[12];
+ uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
+ char res45[12];
+ uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
+ char res46[12];
+ uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
+ char res47[12];
+ uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
+ char res48[60];
+ uint msgr0; /* 0x41400 - Message Register 0 */
+ char res49[12];
+ uint msgr1; /* 0x41410 - Message Register 1 */
+ char res50[12];
+ uint msgr2; /* 0x41420 - Message Register 2 */
+ char res51[12];
+ uint msgr3; /* 0x41430 - Message Register 3 */
+ char res52[204];
+ uint mer; /* 0x41500 - Message Enable Register */
+ char res53[12];
+ uint msr; /* 0x41510 - Message Status Register */
+ char res54[60140];
+ uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
+ char res55[12];
+ uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
+ char res56[12];
+ uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
+ char res57[12];
+ uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
+ char res58[12];
+ uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
+ char res59[12];
+ uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
+ char res60[12];
+ uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
+ char res61[12];
+ uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
+ char res62[12];
+ uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
+ char res63[12];
+ uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
+ char res64[12];
+ uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
+ char res65[12];
+ uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
+ char res66[12];
+ uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
+ char res67[12];
+ uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
+ char res68[12];
+ uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
+ char res69[12];
+ uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
+ char res70[12];
+ uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
+ char res71[12];
+ uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
+ char res72[12];
+ uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
+ char res73[12];
+ uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
+ char res74[12];
+ uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
+ char res75[12];
+ uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
+ char res76[12];
+ uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
+ char res77[12];
+ uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
+ char res78[140];
+ uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
+ char res79[12];
+ uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
+ char res80[12];
+ uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
+ char res81[12];
+ uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
+ char res82[12];
+ uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
+ char res83[12];
+ uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
+ char res84[12];
+ uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
+ char res85[12];
+ uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
+ char res86[12];
+ uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
+ char res87[12];
+ uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
+ char res88[12];
+ uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
+ char res89[12];
+ uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
+ char res90[12];
+ uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
+ char res91[12];
+ uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
+ char res92[12];
+ uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
+ char res93[12];
+ uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
+ char res94[12];
+ uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
+ char res95[12];
+ uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
+ char res96[12];
+ uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
+ char res97[12];
+ uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
+ char res98[12];
+ uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
+ char res99[12];
+ uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
+ char res100[12];
+ uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
+ char res101[12];
+ uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
+ char res102[12];
+ uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
+ char res103[12];
+ uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
+ char res104[12];
+ uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
+ char res105[12];
+ uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
+ char res106[12];
+ uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
+ char res107[12];
+ uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
+ char res108[12];
+ uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
+ char res109[12];
+ uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
+ char res110[12];
+ uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
+ char res111[12];
+ uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
+ char res112[12];
+ uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
+ char res113[12];
+ uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
+ char res114[12];
+ uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
+ char res115[12];
+ uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
+ char res116[12];
+ uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
+ char res117[12];
+ uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
+ char res118[12];
+ uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
+ char res119[12];
+ uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
+ char res120[12];
+ uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
+ char res121[12];
+ uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
+ char res122[12];
+ uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
+ char res123[12];
+ uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
+ char res124[12];
+ uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
+ char res125[12];
+ uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
+ char res126[12];
+ uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
+ char res127[12];
+ uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
+ char res128[12];
+ uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
+ char res129[12];
+ uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
+ char res130[12];
+ uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
+ char res131[12];
+ uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
+ char res132[12];
+ uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
+ char res133[12];
+ uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
+ char res134[12];
+ uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
+ char res135[12];
+ uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
+ char res136[12];
+ uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
+ char res137[12];
+ uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
+ char res138[12];
+ uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
+ char res139[12];
+ uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
+ char res140[12];
+ uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
+ char res141[12];
+ uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
+ char res142[4108];
+ uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
+ char res143[12];
+ uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
+ char res144[12];
+ uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
+ char res145[12];
+ uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
+ char res146[12];
+ uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
+ char res147[12];
+ uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
+ char res148[12];
+ uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
+ char res149[12];
+ uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
+ char res150[59852];
+ uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
+ char res151[12];
+ uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
+ char res152[12];
+ uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
+ char res153[12];
+ uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
+ char res154[12];
+ uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
+ char res155[12];
+ uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
+ char res156[12];
+ uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
+ char res157[12];
+ uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
+ char res158[3916];
+} ccsr_pic_t;
+
+/* RapidIO Registers(0xc_0000-0xe_0000) */
+
+typedef struct ccsr_rio {
+ uint didcar; /* 0xc0000 - Device Identity Capability Register */
+ uint dicar; /* 0xc0004 - Device Information Capability Register */
+ uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
+ uint aicar; /* 0xc000c - Assembly Information Capability Register */
+ uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
+ uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
+ uint socar; /* 0xc0018 - Source Operations Capability Register */
+ uint docar; /* 0xc001c - Destination Operations Capability Register */
+ char res1[32];
+ uint msr; /* 0xc0040 - Mailbox Command And Status Register */
+ uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+ char res2[4];
+ uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+ char res3[12];
+ uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+ uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
+ char res4[4];
+ uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+ uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
+ char res5[144];
+ uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+ char res6[28];
+ uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
+ uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
+ char res7[20];
+ uint pgccsr; /* 0xc013c - Port General Command and Status Register */
+ uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+ uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+ uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
+ char res8[12];
+ uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
+ uint pccsr; /* 0xc015c - Port Control Command and Status Register */
+ char res9[1184];
+ uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
+ char res10[4];
+ uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
+ uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
+ char res11[4];
+ uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
+ uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
+ uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
+ char res12[32];
+ uint edcsr; /* 0xc0640 - Port 0 error detect status register */
+ uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
+ uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
+ uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
+ uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
+ uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
+ uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
+ char res13[12];
+ uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
+ uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
+ char res14[63892];
+ uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
+ char res15[12];
+ uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
+ char res16[12];
+ uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
+ char res17[92];
+ uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
+ char res18[124];
+ uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
+ char res19[28];
+ uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
+ char res20[12];
+ uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
+ char res21[12];
+ uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
+ char res22[20];
+ uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
+ char res23[4];
+ uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
+ char res24[2716];
+ uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+ uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
+ char res25[8];
+ uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+ char res26[12];
+ uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+ uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
+ uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+ char res27[4];
+ uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+ uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
+ uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
+ uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
+ uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+ uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
+ uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+ char res28[4];
+ uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+ uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
+ uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
+ uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
+ uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+ uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
+ uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+ char res29[4];
+ uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+ uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
+ uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
+ uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
+ uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+ uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
+ uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+ char res30[4];
+ uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+ uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
+ uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
+ uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
+ uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+ uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
+ uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+ char res31[4];
+ uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+ uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
+ uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
+ uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
+ uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+ uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
+ uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+ char res32[4];
+ uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+ uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
+ uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
+ uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
+ uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+ uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
+ uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+ char res33[4];
+ uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+ uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
+ uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
+ uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
+ uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+ uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
+ uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+ char res34[4];
+ uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+ uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
+ uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
+ uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
+ char res35[64];
+ uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+ uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+ char res36[4];
+ uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+ char res37[12];
+ uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+ char res38[4];
+ uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+ char res39[4];
+ uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+ char res40[12];
+ uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+ char res41[4];
+ uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+ char res42[4];
+ uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+ char res43[12];
+ uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+ char res44[4];
+ uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+ char res45[4];
+ uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+ char res46[12];
+ uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+ char res47[12];
+ uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+ char res48[12];
+ uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+ uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+ uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+ uint pecr; /* 0xd0e0c - Port Error Control Register */
+ uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+ uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
+ uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
+ char res49[4];
+ uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
+ char res50[4];
+ uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
+ uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
+ char res51[8656];
+ uint omr; /* 0xd3000 - Outbound Mode Register */
+ uint osr; /* 0xd3004 - Outbound Status Register */
+ uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+ uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
+ uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
+ uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
+ uint odpr; /* 0xd3018 - Outbound Destination Port Register */
+ uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
+ uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
+ uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+ uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
+ uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
+ uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
+ uint omlr; /* 0xd3034 - Outbound Multicast List Register */
+ char res52[40];
+ uint imr; /* 0xd3060 - Outbound Mode Register */
+ uint isr; /* 0xd3064 - Inbound Status Register */
+ uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+ uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
+ uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
+ uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
+ uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
+ char res53[900];
+ uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
+ uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
+ char res54[16];
+ uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
+ uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
+ char res55[12];
+ uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
+ char res56[48];
+ uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
+ uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
+ uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
+ uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
+ uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
+ uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
+ uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
+ char res57[100];
+ uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
+ uint pwsr; /* 0xd34e4 - Port-Write Status Register */
+ uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
+ uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
+ char res58[51984];
+} ccsr_rio_t;
+
+/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+typedef struct ccsr_gur {
+ uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+ uint porbmsr; /* 0xe0004 - POR boot mode status register */
+ uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
+ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
+ char res1[12];
+ uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
+ char res2[12];
+ uint gpiocr; /* 0xe0030 - GPIO control register */
+ char res3[12];
+ uint gpoutdr; /* 0xe0040 - General-purpose output data register */
+ char res4[12];
+ uint gpindr; /* 0xe0050 - General-purpose input data register */
+ char res5[12];
+ uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+ char res6[12];
+ uint devdisr; /* 0xe0070 - Device disable control */
+ char res7[12];
+ uint powmgtcsr; /* 0xe0080 - Power management status and control register */
+ char res8[12];
+ uint mcpsumr; /* 0xe0090 - Machine check summary register */
+ uint rstrscr; /* 0xe0094 - Reset request status and control register */
+ char res9[8];
+ uint pvr; /* 0xe00a0 - Processor version register */
+ uint svr; /* 0xe00a4 - System version register */
+ char res10a[8];
+ uint rstcr; /* 0xe00b0 - Reset control register */
+ char res10b[1868];
+ uint clkdvdr; /* 0xe0800 - Clock Divide register */
+ char res10c[796];
+ uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */
+ char res10d[4];
+ uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */
+ char res10e[724];
+ uint clkocr; /* 0xe0e00 - Clock out select register */
+ char res11[12];
+ uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
+ char res12[12];
+ uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
+ char res13a[224];
+ uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */
+ char res13b[4];
+ uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */
+ char res14[24];
+ uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
+ char res15a[24];
+ uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
+ uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */
+ char res16[184];
+} ccsr_gur_t;
+
+#define MPC8610_PORBMSR_HA 0x00070000
+#define MPC8610_PORBMSR_HA_SHIFT 16
+#define MPC8641_PORBMSR_HA 0x00060000
+#define MPC8641_PORBMSR_HA_SHIFT 17
+#define MPC8610_PORDEVSR_IO_SEL 0x00380000
+#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19
+#define MPC8641_PORDEVSR_IO_SEL 0x000F0000
+#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16
+#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
+#define MPC86xx_DEVDISR_PCIEX1 0x80000000
+#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+#define MPC86xx_DEVDISR_PCI1 0x80000000
+#define MPC86xx_DEVDISR_PCIE1 0x40000000
+#define MPC86xx_DEVDISR_PCIE2 0x20000000
+#define MPC86xx_DEVDISR_SRIO 0x00080000
+#define MPC86xx_DEVDISR_RMSG 0x00040000
+#define MPC86xx_DEVDISR_CPU0 0x00008000
+#define MPC86xx_DEVDISR_CPU1 0x00004000
+#define MPC86xx_RSTCR_HRST_REQ 0x00000002
+
+/*
+ * Watchdog register block(0xe_4000-0xe_4fff)
+ */
+typedef struct ccsr_wdt {
+ uint res0;
+ uint swcrr; /* System watchdog control register */
+ uint swcnr; /* System watchdog count register */
+ char res1[2];
+ ushort swsrr; /* System watchdog service register */
+ char res2[4080];
+} ccsr_wdt_t;
+
+typedef struct immap {
+ ccsr_local_mcm_t im_local_mcm;
+ struct ccsr_ddr im_ddr1;
+ ccsr_i2c_t im_i2c;
+ ccsr_duart_t im_duart;
+ fsl_lbc_t im_lbc;
+ struct ccsr_ddr im_ddr2;
+ char res1[4096];
+ ccsr_pex_t im_pex1;
+ ccsr_pex_t im_pex2;
+ ccsr_ht_t im_ht;
+ char res2[90112];
+ ccsr_dma_t im_dma;
+ char res3[8192];
+ ccsr_tsec_t im_tsec1;
+ ccsr_tsec_t im_tsec2;
+ ccsr_tsec_t im_tsec3;
+ ccsr_tsec_t im_tsec4;
+ char res4[98304];
+ ccsr_pic_t im_pic;
+ char res5[389120];
+ ccsr_rio_t im_rio;
+ ccsr_gur_t im_gur;
+ char res6[12288];
+ ccsr_wdt_t im_wdt;
+} immap_t;
+
+extern immap_t *immr;
+
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
+#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
+#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
+
+
+#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
+#ifdef CONFIG_ARCH_MPC8610
+#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
+#else
+#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
+#endif
+#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000
+
+#define CONFIG_SYS_PCI1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
+#define CONFIG_SYS_PCI2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
+#define CONFIG_SYS_PCIE1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
+#define CONFIG_SYS_PCIE2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
+
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
+#endif /*__IMMAP_86xx__*/
diff --git a/arch/powerpc/include/asm/immap_8xx.h b/arch/powerpc/include/asm/immap_8xx.h
new file mode 100644
index 0000000..3999a02
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_8xx.h
@@ -0,0 +1,468 @@
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions. It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try. -- Dan
+ */
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef struct sys_conf {
+ uint sc_siumcr;
+ uint sc_sypcr;
+ uint sc_swt;
+ char res1[2];
+ ushort sc_swsr;
+ uint sc_sipend;
+ uint sc_simask;
+ uint sc_siel;
+ uint sc_sivec;
+ uint sc_tesr;
+ char res2[0xc];
+ uint sc_sdcr;
+ char res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+ uint pcmc_pbr0;
+ uint pcmc_por0;
+ uint pcmc_pbr1;
+ uint pcmc_por1;
+ uint pcmc_pbr2;
+ uint pcmc_por2;
+ uint pcmc_pbr3;
+ uint pcmc_por3;
+ uint pcmc_pbr4;
+ uint pcmc_por4;
+ uint pcmc_pbr5;
+ uint pcmc_por5;
+ uint pcmc_pbr6;
+ uint pcmc_por6;
+ uint pcmc_pbr7;
+ uint pcmc_por7;
+ char res1[0x20];
+ uint pcmc_pgcra;
+ uint pcmc_pgcrb;
+ uint pcmc_pscr;
+ char res2[4];
+ uint pcmc_pipr;
+ char res3[4];
+ uint pcmc_per;
+ char res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct mem_ctlr {
+ uint memc_br0;
+ uint memc_or0;
+ uint memc_br1;
+ uint memc_or1;
+ uint memc_br2;
+ uint memc_or2;
+ uint memc_br3;
+ uint memc_or3;
+ uint memc_br4;
+ uint memc_or4;
+ uint memc_br5;
+ uint memc_or5;
+ uint memc_br6;
+ uint memc_or6;
+ uint memc_br7;
+ uint memc_or7;
+ char res1[0x24];
+ uint memc_mar;
+ uint memc_mcr;
+ char res2[4];
+ uint memc_mamr;
+ uint memc_mbmr;
+ ushort memc_mstat;
+ ushort memc_mptpr;
+ uint memc_mdr;
+ char res3[0x80];
+} memctl8xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct sys_int_timers {
+ ushort sit_tbscr;
+ char res0[0x02];
+ uint sit_tbreff0;
+ uint sit_tbreff1;
+ char res1[0x14];
+ ushort sit_rtcsc;
+ char res2[0x02];
+ uint sit_rtc;
+ uint sit_rtsec;
+ uint sit_rtcal;
+ char res3[0x10];
+ ushort sit_piscr;
+ char res4[2];
+ uint sit_pitc;
+ uint sit_pitr;
+ char res5[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK ((ushort)0xff00)
+#define TBSCR_REFA ((ushort)0x0080)
+#define TBSCR_REFB ((ushort)0x0040)
+#define TBSCR_REFAE ((ushort)0x0008)
+#define TBSCR_REFBE ((ushort)0x0004)
+#define TBSCR_TBF ((ushort)0x0002)
+#define TBSCR_TBE ((ushort)0x0001)
+
+#define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
+#define RTCSC_SEC ((ushort)0x0080)
+#define RTCSC_ALR ((ushort)0x0040)
+#define RTCSC_38K ((ushort)0x0010)
+#define RTCSC_SIE ((ushort)0x0008)
+#define RTCSC_ALE ((ushort)0x0004)
+#define RTCSC_RTF ((ushort)0x0002)
+#define RTCSC_RTE ((ushort)0x0001)
+
+#define PISCR_PIRQ_MASK ((ushort)0xff00)
+#define PISCR_PS ((ushort)0x0080)
+#define PISCR_PIE ((ushort)0x0004)
+#define PISCR_PTF ((ushort)0x0002)
+#define PISCR_PTE ((ushort)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+ uint car_sccr;
+ uint car_plprcr;
+ uint car_rsr;
+ char res[0x74]; /* Reserved area */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+ uint sitk_tbscrk;
+ uint sitk_tbreff0k;
+ uint sitk_tbreff1k;
+ uint sitk_tbk;
+ char res1[0x10];
+ uint sitk_rtcsck;
+ uint sitk_rtck;
+ uint sitk_rtseck;
+ uint sitk_rtcalk;
+ char res2[0x10];
+ uint sitk_piscrk;
+ uint sitk_pitck;
+ char res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+ uint cark_sccrk;
+ uint cark_plprcrk;
+ uint cark_rsrk;
+ char res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY ((unsigned int)0x55ccaa33)
+
+/* I2C
+*/
+typedef struct i2c {
+ u_char i2c_i2mod;
+ char res1[3];
+ u_char i2c_i2add;
+ char res2[3];
+ u_char i2c_i2brg;
+ char res3[3];
+ u_char i2c_i2com;
+ char res4[3];
+ u_char i2c_i2cer;
+ char res5[3];
+ u_char i2c_i2cmr;
+ char res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+ char res1[4];
+ uint sdma_sdar;
+ u_char sdma_sdsr;
+ char res3[3];
+ u_char sdma_sdmr;
+ char res4[3];
+ u_char sdma_idsr1;
+ char res5[3];
+ u_char sdma_idmr1;
+ char res6[3];
+ u_char sdma_idsr2;
+ char res7[3];
+ u_char sdma_idmr2;
+ char res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+ ushort cpic_civr;
+ char res[0xe];
+ uint cpic_cicr;
+ uint cpic_cipr;
+ uint cpic_cimr;
+ uint cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+ ushort iop_padir;
+ ushort iop_papar;
+ ushort iop_paodr;
+ ushort iop_padat;
+ char res1[8];
+ ushort iop_pcdir;
+ ushort iop_pcpar;
+ ushort iop_pcso;
+ ushort iop_pcdat;
+ ushort iop_pcint;
+ char res2[6];
+ ushort iop_pddir;
+ ushort iop_pdpar;
+ char res3[2];
+ ushort iop_pddat;
+ uint utmode;
+ char res4[4];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+ ushort cpmt_tgcr;
+ char res1[0xe];
+ ushort cpmt_tmr1;
+ ushort cpmt_tmr2;
+ ushort cpmt_trr1;
+ ushort cpmt_trr2;
+ ushort cpmt_tcr1;
+ ushort cpmt_tcr2;
+ ushort cpmt_tcn1;
+ ushort cpmt_tcn2;
+ ushort cpmt_tmr3;
+ ushort cpmt_tmr4;
+ ushort cpmt_trr3;
+ ushort cpmt_trr4;
+ ushort cpmt_tcr3;
+ ushort cpmt_tcr4;
+ ushort cpmt_tcn3;
+ ushort cpmt_tcn4;
+ ushort cpmt_ter1;
+ ushort cpmt_ter2;
+ ushort cpmt_ter3;
+ ushort cpmt_ter4;
+ char res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc { /* Serial communication channels */
+ uint scc_gsmrl;
+ uint scc_gsmrh;
+ ushort scc_psmr;
+ char res1[2];
+ ushort scc_todr;
+ ushort scc_dsr;
+ ushort scc_scce;
+ char res2[2];
+ ushort scc_sccm;
+ char res3;
+ u_char scc_sccs;
+ char res4[8];
+} scc_t;
+
+typedef struct smc { /* Serial management channels */
+ char res1[2];
+ ushort smc_smcmr;
+ char res2[2];
+ u_char smc_smce;
+ char res3[3];
+ u_char smc_smcm;
+ char res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+
+typedef struct fec {
+ uint fec_addr_low; /* lower 32 bits of station address */
+ ushort fec_addr_high; /* upper 16 bits of station address */
+ ushort res1; /* reserved */
+ uint fec_hash_table_high; /* upper 32-bits of hash table */
+ uint fec_hash_table_low; /* lower 32-bits of hash table */
+ uint fec_r_des_start; /* beginning of Rx descriptor ring */
+ uint fec_x_des_start; /* beginning of Tx descriptor ring */
+ uint fec_r_buff_size; /* Rx buffer size */
+ uint res2[9]; /* reserved */
+ uint fec_ecntrl; /* ethernet control register */
+ uint fec_ievent; /* interrupt event register */
+ uint fec_imask; /* interrupt mask register */
+ uint fec_ivec; /* interrupt level and vector status */
+ uint fec_r_des_active; /* Rx ring updated flag */
+ uint fec_x_des_active; /* Tx ring updated flag */
+ uint res3[10]; /* reserved */
+ uint fec_mii_data; /* MII data register */
+ uint fec_mii_speed; /* MII speed control register */
+ uint res4[17]; /* reserved */
+ uint fec_r_bound; /* end of RAM (read-only) */
+ uint fec_r_fstart; /* Rx FIFO start address */
+ uint res5[6]; /* reserved */
+ uint fec_x_fstart; /* Tx FIFO start address */
+ uint res6[17]; /* reserved */
+ uint fec_fun_code; /* fec SDMA function code */
+ uint res7[3]; /* reserved */
+ uint fec_r_cntrl; /* Rx control register */
+ uint fec_r_hash; /* Rx hash register */
+ uint res8[14]; /* reserved */
+ uint fec_x_cntrl; /* Tx control register */
+ uint res9[0x1e]; /* reserved */
+} fec_t;
+
+typedef struct comm_proc {
+ /* General control and status registers.
+ */
+ ushort cp_cpcr;
+ u_char res1[2];
+ ushort cp_rccr;
+ u_char res2;
+ u_char cp_rmds;
+ u_char res3[4];
+ ushort cp_cpmcr1;
+ ushort cp_cpmcr2;
+ ushort cp_cpmcr3;
+ ushort cp_cpmcr4;
+ u_char res4[2];
+ ushort cp_rter;
+ u_char res5[2];
+ ushort cp_rtmr;
+ u_char res6[0x14];
+
+ /* Baud rate generators.
+ */
+ uint cp_brgc1;
+ uint cp_brgc2;
+ uint cp_brgc3;
+ uint cp_brgc4;
+
+ /* Serial Communication Channels.
+ */
+ scc_t cp_scc[4];
+
+ /* Serial Management Channels.
+ */
+ smc_t cp_smc[2];
+
+ /* Serial Peripheral Interface.
+ */
+ ushort cp_spmode;
+ u_char res7[4];
+ u_char cp_spie;
+ u_char res8[3];
+ u_char cp_spim;
+ u_char res9[2];
+ u_char cp_spcom;
+ u_char res10[2];
+
+ /* Parallel Interface Port.
+ */
+ u_char res11[2];
+ ushort cp_pipc;
+ u_char res12[2];
+ ushort cp_ptpr;
+ uint cp_pbdir;
+ uint cp_pbpar;
+ u_char res13[2];
+ ushort cp_pbodr;
+ uint cp_pbdat;
+
+ /* Port E - MPC87x/88x only.
+ */
+ uint cp_pedir;
+ uint cp_pepar;
+ uint cp_peso;
+ uint cp_peodr;
+ uint cp_pedat;
+
+ /* Communications Processor Timing Register -
+ Contains RMII Timing for the FECs on MPC87x/88x only.
+ */
+ uint cp_cptr;
+
+ /* Serial Interface and Time Slot Assignment.
+ */
+ uint cp_simode;
+ u_char cp_sigmr;
+ u_char res15;
+ u_char cp_sistr;
+ u_char cp_sicmr;
+ u_char res16[4];
+ uint cp_sicr;
+ uint cp_sirp;
+ u_char res17[0xc];
+
+ u_char res19[0x100];
+ u_char cp_siram[0x200];
+
+ /* The fast ethernet controller is not really part of the CPM,
+ * but it resides in the address space.
+ */
+ fec_t cp_fec;
+ char res18[0xE00];
+
+ /* The MPC885 family has a second FEC here */
+ fec_t cp_fec2;
+#define cp_fec1 cp_fec /* consistency macro */
+
+ /* Dual Ported RAM follows.
+ * There are many different formats for this memory area
+ * depending upon the devices used and options chosen.
+ * Some processors don't have all of it populated.
+ */
+ u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
+
+ /* Parameter RAM */
+ union {
+ u_char cp_dparam[0x400];
+ u16 cp_dparam16[0x200];
+ };
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+ sysconf8xx_t im_siu_conf; /* SIU Configuration */
+ pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
+ memctl8xx_t im_memctl; /* Memory Controller */
+ sit8xx_t im_sit; /* System integration timers */
+ car8xx_t im_clkrst; /* Clocks and reset */
+ sitk8xx_t im_sitk; /* Sys int timer keys */
+ cark8xx_t im_clkrstk; /* Clocks and reset keys */
+ char res[96];
+ i2c8xx_t im_i2c; /* I2C control/status */
+ sdma8xx_t im_sdma; /* SDMA control/status */
+ cpic8xx_t im_cpic; /* CPM Interrupt Controller */
+ iop8xx_t im_ioport; /* IO Port control/status */
+ cpmtimer8xx_t im_cpmtimer; /* CPM timers */
+ cpm8xx_t im_cpm; /* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h
new file mode 100644
index 0000000..cda21a2
--- /dev/null
+++ b/arch/powerpc/include/asm/interrupt.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+ * This work has been supported by: QTechnology http://qtec.com/
+ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
+ */
+#ifndef INTERRUPT_H
+#define INTERRUPT_H
+
+void external_interrupt(struct pt_regs *regs);
+
+#endif
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
new file mode 100644
index 0000000..6d76e3e
--- /dev/null
+++ b/arch/powerpc/include/asm/io.h
@@ -0,0 +1,325 @@
+/* originally from linux source.
+ * removed the dependencies on CONFIG_ values
+ * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
+ * Modified By Rob Taylor, Flying Pig Systems, 2000
+ */
+
+#ifndef _PPC_IO_H
+#define _PPC_IO_H
+
+#include <asm/byteorder.h>
+
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
+#define SIO_CONFIG_RA 0x398
+#define SIO_CONFIG_RD 0x399
+
+#ifndef _IO_BASE
+#define _IO_BASE 0
+#endif
+
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr) (*(volatile u16 *) (addr))
+#define readl(addr) (*(volatile u32 *) (addr))
+#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case. - paulus
+ */
+#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port) in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+#define inb_p(port) in_8((u8 *)((port)+_IO_BASE))
+#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
+#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE))
+#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE))
+#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
+
+extern void _insb(volatile u8 *port, void *buf, int ns);
+extern void _outsb(volatile u8 *port, const void *buf, int ns);
+extern void _insw(volatile u16 *port, void *buf, int ns);
+extern void _outsw(volatile u16 *port, const void *buf, int ns);
+extern void _insl(volatile u32 *port, void *buf, int nl);
+extern void _outsl(volatile u32 *port, const void *buf, int nl);
+extern void _insw_ns(volatile u16 *port, void *buf, int ns);
+extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
+extern void _insl_ns(volatile u32 *port, void *buf, int nl);
+extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+
+#define IO_SPACE_LIMIT ~0
+
+#define memset_io(a,b,c) memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+
+/*
+ * Enforce In-order Execution of I/O:
+ * Acts as a barrier to ensure all previous I/O accesses have
+ * completed before any further ones are issued.
+ */
+static inline void eieio(void)
+{
+ __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void sync(void)
+{
+ __asm__ __volatile__ ("sync" : : : "memory");
+}
+
+static inline void isync(void)
+{
+ __asm__ __volatile__ ("isync" : : : "memory");
+}
+
+/* Enforce in-order execution of data I/O.
+ * No distinction between read/write on PPC; use eieio for all three.
+ */
+#define iobarrier_rw() eieio()
+#define iobarrier_r() eieio()
+#define iobarrier_w() eieio()
+
+#define mb() sync()
+#define isb() isync()
+
+/*
+ * Non ordered and non-swapping "raw" accessors
+ */
+#define PCI_FIX_ADDR(addr) (addr)
+
+static inline unsigned char __raw_readb(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned short __raw_readw(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned int __raw_readl(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
+}
+static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
+{
+ *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
+{
+ *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
+{
+ *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
+}
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ *
+ * Read operations have additional twi & isync to make sure the read
+ * is actually performed (i.e. the data has come back) before we start
+ * executing any following instructions.
+ */
+static inline u8 in_8(const volatile unsigned char __iomem *addr)
+{
+ u8 ret;
+
+ __asm__ __volatile__(
+ "sync; lbz%U1%X1 %0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) : "m" (*addr));
+ return ret;
+}
+
+static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
+{
+ __asm__ __volatile__("sync;\n"
+ "stb%U0%X0 %1,%0;\n"
+ : "=m" (*addr)
+ : "r" (val));
+}
+
+static inline u16 in_le16(const volatile unsigned short __iomem *addr)
+{
+ u16 ret;
+
+ __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) :
+ "r" (addr), "m" (*addr));
+ return ret;
+}
+
+static inline u16 in_be16(const volatile unsigned short __iomem *addr)
+{
+ u16 ret;
+
+ __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) : "m" (*addr));
+ return ret;
+}
+
+static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
+{
+ __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
+ "r" (val), "r" (addr));
+}
+
+static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
+{
+ __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+}
+
+static inline u32 in_le32(const volatile unsigned __iomem *addr)
+{
+ u32 ret;
+
+ __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) :
+ "r" (addr), "m" (*addr));
+ return ret;
+}
+
+static inline u32 in_be32(const volatile unsigned __iomem *addr)
+{
+ u32 ret;
+
+ __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) : "m" (*addr));
+ return ret;
+}
+
+static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
+{
+ __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
+ "r" (val), "r" (addr));
+}
+
+static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
+{
+ __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+}
+
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+ out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+ out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#define readb_be(addr) \
+ __raw_readb((__force unsigned *)(addr))
+#define readw_be(addr) \
+ be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr) \
+ be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr) \
+ be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
+
+#define writeb_be(val, addr) \
+ __raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr) \
+ __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr) \
+ __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr) \
+ __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
+
+static inline void *phys_to_virt(phys_addr_t paddr)
+{
+#ifdef CONFIG_ADDR_MAP
+ return addrmap_phys_to_virt(paddr);
+#else
+ return (void *)((unsigned long)paddr);
+#endif
+}
+#define phys_to_virt phys_to_virt
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+#ifdef CONFIG_ADDR_MAP
+ return addrmap_virt_to_phys(vaddr);
+#else
+ return (phys_addr_t)((unsigned long)vaddr);
+#endif
+}
+#define virt_to_phys virt_to_phys
+
+#include <asm-generic/io.h>
+
+#endif
diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
new file mode 100644
index 0000000..a41b332
--- /dev/null
+++ b/arch/powerpc/include/asm/iopin_8xx.h
@@ -0,0 +1,466 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * MPC8xx I/O port pin manipulation functions
+ * Roughly based on iopin_8260.h
+ */
+
+#ifndef _ASM_IOPIN_8XX_H_
+#define _ASM_IOPIN_8XX_H_
+
+#include <linux/types.h>
+#include <asm/immap_8xx.h>
+#include <asm/io.h>
+
+#ifdef __KERNEL__
+
+typedef struct {
+ u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
+ u_char pin:5; /* port pin (0-31) */
+ u_char flag:1; /* for whatever */
+} iopin_t;
+
+#define IOPIN_PORTA 0
+#define IOPIN_PORTB 1
+#define IOPIN_PORTC 2
+#define IOPIN_PORTD 3
+
+static inline void iopin_set_high(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ setbits_be32(datp, 1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline void iopin_set_low(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ clrbits_be32(datp, 1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline uint iopin_is_high(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ return (in_be32(datp) >> (31 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+static inline uint iopin_is_low(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ return ((in_be32(datp) >> (31 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+static inline void iopin_set_out(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ setbits_be32(dirp, 1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline void iopin_set_in(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ clrbits_be32(dirp, 1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline uint iopin_is_out(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ return (in_be32(dirp) >> (31 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+static inline uint iopin_is_in(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ return ((in_be32(dirp) >> (31 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+static inline void iopin_set_odr(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ setbits_be16(odrp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ setbits_be16(odrp, 1 << (31 - iopin->pin));
+ }
+}
+
+static inline void iopin_set_act(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ clrbits_be16(odrp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ clrbits_be16(odrp, 1 << (31 - iopin->pin));
+ }
+}
+
+static inline uint iopin_is_odr(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ return (in_be16(odrp) >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ return (in_be16(odrp) >> (31 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+static inline uint iopin_is_act(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ return ((in_be16(odrp) >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ return ((in_be16(odrp) >> (31 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+static inline void iopin_set_ded(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ setbits_be32(parp, 1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline void iopin_set_gen(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ clrbits_be32(parp, 1 << (31 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline uint iopin_is_ded(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ return (in_be32(parp) >> (31 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+static inline uint iopin_is_gen(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTA) {
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTB) {
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ return ((in_be32(parp) >> (31 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+ } else if (iopin->port == IOPIN_PORTD) {
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+static inline void iopin_set_opt2(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ setbits_be16(sorp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline void iopin_set_opt1(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ clrbits_be16(sorp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline uint iopin_is_opt2(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ return (in_be16(sorp) >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+static inline uint iopin_is_opt1(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ return ((in_be16(sorp) >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+static inline void iopin_set_falledge(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ setbits_be16(intp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline void iopin_set_anyedge(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ clrbits_be16(intp, 1 << (15 - iopin->pin));
+ }
+}
+
+static inline uint iopin_is_falledge(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ return (in_be16(intp) >> (15 - iopin->pin)) & 1;
+ }
+ return 0;
+}
+
+static inline uint iopin_is_anyedge(iopin_t *iopin)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ if (iopin->port == IOPIN_PORTC) {
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ return ((in_be16(intp) >> (15 - iopin->pin)) & 1) ^ 1;
+ }
+ return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_8XX_H_ */
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
new file mode 100644
index 0000000..f9b036e
--- /dev/null
+++ b/arch/powerpc/include/asm/linkage.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/* We don't need anything here at present */
diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h
new file mode 100644
index 0000000..5f806c4
--- /dev/null
+++ b/arch/powerpc/include/asm/mc146818rtc.h
@@ -0,0 +1,27 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_PPC_MC146818RTC_H
+#define __ASM_PPC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x) (0x70 + (x))
+#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#endif /* __ASM_PPC_MC146818RTC_H */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
new file mode 100644
index 0000000..82e5f9f
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu.h
@@ -0,0 +1,588 @@
+/*
+ * PowerPC memory management structures
+ */
+
+#ifndef _PPC_MMU_H_
+#define _PPC_MMU_H_
+
+#ifndef __ASSEMBLY__
+/* Hardware Page Table Entry */
+typedef struct _PTE {
+#ifdef CONFIG_PPC64BRIDGE
+ unsigned long long vsid:52;
+ unsigned long api:5;
+ unsigned long :5;
+ unsigned long h:1;
+ unsigned long v:1;
+ unsigned long long rpn:52;
+#else /* CONFIG_PPC64BRIDGE */
+ unsigned long v:1; /* Entry is valid */
+ unsigned long vsid:24; /* Virtual segment identifier */
+ unsigned long h:1; /* Hash algorithm indicator */
+ unsigned long api:6; /* Abbreviated page index */
+ unsigned long rpn:20; /* Real (physical) page number */
+#endif /* CONFIG_PPC64BRIDGE */
+ unsigned long :3; /* Unused */
+ unsigned long r:1; /* Referenced */
+ unsigned long c:1; /* Changed */
+ unsigned long w:1; /* Write-thru cache mode */
+ unsigned long i:1; /* Cache inhibited */
+ unsigned long m:1; /* Memory coherence */
+ unsigned long g:1; /* Guarded */
+ unsigned long :1; /* Unused */
+ unsigned long pp:2; /* Page protection */
+} PTE;
+
+/* Values for PP (assumes Ks=0, Kp=1) */
+#define PP_RWXX 0 /* Supervisor read/write, User none */
+#define PP_RWRX 1 /* Supervisor read/write, User read */
+#define PP_RWRW 2 /* Supervisor read/write, User read/write */
+#define PP_RXRX 3 /* Supervisor read, User read */
+
+/* Segment Register */
+typedef struct _SEGREG {
+ unsigned long t:1; /* Normal or I/O type */
+ unsigned long ks:1; /* Supervisor 'key' (normally 0) */
+ unsigned long kp:1; /* User 'key' (normally 1) */
+ unsigned long n:1; /* No-execute */
+ unsigned long :4; /* Unused */
+ unsigned long vsid:24; /* Virtual Segment Identifier */
+} SEGREG;
+
+/* Block Address Translation (BAT) Registers */
+typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
+ unsigned long bepi:15; /* Effective page index (virtual address) */
+ unsigned long :8; /* unused */
+ unsigned long w:1;
+ unsigned long i:1; /* Cache inhibit */
+ unsigned long m:1; /* Memory coherence */
+ unsigned long ks:1; /* Supervisor key (normally 0) */
+ unsigned long kp:1; /* User key (normally 1) */
+ unsigned long pp:2; /* Page access protections */
+} P601_BATU;
+
+typedef struct _BATU { /* Upper part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+ unsigned long long bepi:47;
+#else /* CONFIG_PPC64BRIDGE */
+ unsigned long bepi:15; /* Effective page index (virtual address) */
+#endif /* CONFIG_PPC64BRIDGE */
+ unsigned long :4; /* Unused */
+ unsigned long bl:11; /* Block size mask */
+ unsigned long vs:1; /* Supervisor valid */
+ unsigned long vp:1; /* User valid */
+} BATU;
+
+typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
+ unsigned long brpn:15; /* Real page index (physical address) */
+ unsigned long :10; /* Unused */
+ unsigned long v:1; /* Valid bit */
+ unsigned long bl:6; /* Block size mask */
+} P601_BATL;
+
+typedef struct _BATL { /* Lower part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+ unsigned long long brpn:47;
+#else /* CONFIG_PPC64BRIDGE */
+ unsigned long brpn:15; /* Real page index (physical address) */
+#endif /* CONFIG_PPC64BRIDGE */
+ unsigned long :10; /* Unused */
+ unsigned long w:1; /* Write-thru cache */
+ unsigned long i:1; /* Cache inhibit */
+ unsigned long m:1; /* Memory coherence */
+ unsigned long g:1; /* Guarded (MBZ in IBAT) */
+ unsigned long :1; /* Unused */
+ unsigned long pp:2; /* Page access protections */
+} BATL;
+
+typedef struct _BAT {
+ BATU batu; /* Upper register */
+ BATL batl; /* Lower register */
+} BAT;
+
+typedef struct _P601_BAT {
+ P601_BATU batu; /* Upper register */
+ P601_BATL batl; /* Lower register */
+} P601_BAT;
+
+/*
+ * Simulated two-level MMU. This structure is used by the kernel
+ * to keep track of MMU mappings and is used to update/maintain
+ * the hardware HASH table which is really a cache of mappings.
+ *
+ * The simulated structures mimic the hardware available on other
+ * platforms, notably the 80x86 and 680x0.
+ */
+
+typedef struct _pte {
+ unsigned long page_num:20;
+ unsigned long flags:12; /* Page flags (some unused bits) */
+} pte;
+
+#define PD_SHIFT (10+12) /* Page directory */
+#define PD_MASK 0x02FF
+#define PT_SHIFT (12) /* Page Table */
+#define PT_MASK 0x02FF
+#define PG_SHIFT (12) /* Page Entry */
+
+
+/* MMU context */
+
+typedef struct _MMU_context {
+ SEGREG segs[16]; /* Segment registers */
+ pte **pmap; /* Two-level page-map structure */
+} MMU_context;
+
+extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
+extern void _tlbia(void); /* invalidate all TLB entries */
+
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
+
+typedef enum {
+ IBAT0 = 0, IBAT1, IBAT2, IBAT3,
+ DBAT0, DBAT1, DBAT2, DBAT3,
+#ifdef CONFIG_HIGH_BATS
+ IBAT4, IBAT5, IBAT6, IBAT7,
+ DBAT4, DBAT5, DBAT6, DBAT7
+#endif
+} ppc_bat_t;
+
+extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
+extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+extern void print_bats(void);
+
+#endif /* __ASSEMBLY__ */
+
+#define BATU_VS 0x00000002
+#define BATU_VP 0x00000001
+#define BATU_INVALID 0x00000000
+
+#define BATL_WRITETHROUGH 0x00000040
+#define BATL_CACHEINHIBIT 0x00000020
+#define BATL_MEMCOHERENCE 0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+#define BATL_NO_ACCESS 0x00000000
+
+#define BATL_PP_MSK 0x00000003
+#define BATL_PP_00 0x00000000 /* No access */
+#define BATL_PP_01 0x00000001 /* Read-only */
+#define BATL_PP_10 0x00000002 /* Read-write */
+#define BATL_PP_11 0x00000003
+
+#define BATL_PP_NO_ACCESS BATL_PP_00
+#define BATL_PP_RO BATL_PP_01
+#define BATL_PP_RW BATL_PP_10
+
+/* BAT Block size values */
+#define BATU_BL_128K 0x00000000
+#define BATU_BL_256K 0x00000004
+#define BATU_BL_512K 0x0000000c
+#define BATU_BL_1M 0x0000001c
+#define BATU_BL_2M 0x0000003c
+#define BATU_BL_4M 0x0000007c
+#define BATU_BL_8M 0x000000fc
+#define BATU_BL_16M 0x000001fc
+#define BATU_BL_32M 0x000003fc
+#define BATU_BL_64M 0x000007fc
+#define BATU_BL_128M 0x00000ffc
+#define BATU_BL_256M 0x00001ffc
+
+/* Block lengths for processors that support extended block length */
+#ifdef HID0_XBSEN
+#define BATU_BL_512M 0x00003ffc
+#define BATU_BL_1G 0x00007ffc
+#define BATU_BL_2G 0x0000fffc
+#define BATU_BL_4G 0x0001fffc
+#define BATU_BL_MAX BATU_BL_4G
+#else
+#define BATU_BL_MAX BATU_BL_256M
+#endif
+
+/* BAT Access Protection */
+#define BPP_XX 0x00 /* No access */
+#define BPP_RX 0x01 /* Read only */
+#define BPP_RW 0x02 /* Read/write */
+
+/* Macros to get values from BATs, once data is in the BAT register format */
+#define BATU_VALID(x) (x & 0x3)
+#define BATU_VADDR(x) (x & 0xfffe0000)
+#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
+ | ((x & 0x0e00ULL) << 24) \
+ | ((x & 0x04ULL) << 30)))
+#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+
+/* bytes into BATU_BL */
+#define TO_BATU_BL(x) \
+ (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
+
+/* Used to set up SDR1 register */
+#define HASH_TABLE_SIZE_64K 0x00010000
+#define HASH_TABLE_SIZE_128K 0x00020000
+#define HASH_TABLE_SIZE_256K 0x00040000
+#define HASH_TABLE_SIZE_512K 0x00080000
+#define HASH_TABLE_SIZE_1M 0x00100000
+#define HASH_TABLE_SIZE_2M 0x00200000
+#define HASH_TABLE_SIZE_4M 0x00400000
+#define HASH_TABLE_MASK_64K 0x000
+#define HASH_TABLE_MASK_128K 0x001
+#define HASH_TABLE_MASK_256K 0x003
+#define HASH_TABLE_MASK_512K 0x007
+#define HASH_TABLE_MASK_1M 0x00F
+#define HASH_TABLE_MASK_2M 0x01F
+#define HASH_TABLE_MASK_4M 0x03F
+
+/* Control/status registers for the MPC8xx.
+ * A write operation to these registers causes serialized access.
+ * During software tablewalk, the registers used perform mask/shift-add
+ * operations when written/read. A TLB entry is created when the Mx_RPN
+ * is written, and the contents of several registers are used to
+ * create the entry.
+ */
+#define MI_CTR 784 /* Instruction TLB control register */
+#define MI_GPM 0x80000000 /* Set domain manager mode */
+#define MI_PPM 0x40000000 /* Set subpage protection */
+#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
+#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
+#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
+#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
+#define MI_RESETVAL 0x00000000 /* Value of register at reset */
+
+/* These are the Ks and Kp from the PowerPC books. For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define MI_AP 786
+#define MI_Ks 0x80000000 /* Should not be set */
+#define MI_Kp 0x40000000 /* Should always be set */
+
+/* The effective page number register. When read, contains the information
+ * about the last instruction TLB miss. When MI_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define MI_EPN 787
+#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
+#define MI_EVALID 0x00000200 /* Entry is valid */
+#define MI_ASIDMASK 0x0000000f /* ASID match value */
+ /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the instruction TLB, it contains bits that get loaded into the
+ * TLB entry when the MI_RPN is written.
+ */
+#define MI_TWC 789
+#define MI_APG 0x000001e0 /* Access protection group (0) */
+#define MI_GUARDED 0x00000010 /* Guarded storage */
+#define MI_PSMASK 0x0000000c /* Mask of page size bits */
+#define MI_PS8MEG 0x0000000c /* 8M page size */
+#define MI_PS512K 0x00000004 /* 512K page size */
+#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
+#define MI_SVALID 0x00000001 /* Segment entry is valid */
+ /* Reset value is undefined */
+
+/* Real page number. Defined by the pte. Writing this register
+ * causes a TLB entry to be created for the instruction TLB, using
+ * additional information from the MI_EPN, and MI_TWC registers.
+ */
+#define MI_RPN 790
+
+/* Define an RPN value for mapping kernel memory to large virtual
+ * pages for boot initialization. This has real page number of 0,
+ * large page size, shared page, cache enabled, and valid.
+ * Also mark all subpages valid and write access.
+ */
+#define MI_BOOTINIT 0x000001fd
+
+#define MD_CTR 792 /* Data TLB control register */
+#define MD_GPM 0x80000000 /* Set domain manager mode */
+#define MD_PPM 0x40000000 /* Set subpage protection */
+#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
+#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
+#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
+#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
+#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
+#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
+#define MD_RESETVAL 0x04000000 /* Value of register at reset */
+
+#define M_CASID 793 /* Address space ID (context) to match */
+#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
+
+
+/* These are the Ks and Kp from the PowerPC books. For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define MD_AP 794
+#define MD_Ks 0x80000000 /* Should not be set */
+#define MD_Kp 0x40000000 /* Should always be set */
+
+/* The effective page number register. When read, contains the information
+ * about the last instruction TLB miss. When MD_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define MD_EPN 795
+#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
+#define MD_EVALID 0x00000200 /* Entry is valid */
+#define MD_ASIDMASK 0x0000000f /* ASID match value */
+ /* Reset value is undefined */
+
+/* The pointer to the base address of the first level page table.
+ * During a software tablewalk, reading this register provides the address
+ * of the entry associated with MD_EPN.
+ */
+#define M_TWB 796
+#define M_L1TB 0xfffff000 /* Level 1 table base address */
+#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
+ /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the data TLB, it contains bits that get loaded into the TLB entry
+ * when the MD_RPN is written. It is also provides the hardware assist
+ * for finding the PTE address during software tablewalk.
+ */
+#define MD_TWC 797
+#define MD_L2TB 0xfffff000 /* Level 2 table base address */
+#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
+#define MD_APG 0x000001e0 /* Access protection group (0) */
+#define MD_GUARDED 0x00000010 /* Guarded storage */
+#define MD_PSMASK 0x0000000c /* Mask of page size bits */
+#define MD_PS8MEG 0x0000000c /* 8M page size */
+#define MD_PS512K 0x00000004 /* 512K page size */
+#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
+#define MD_WT 0x00000002 /* Use writethrough page attribute */
+#define MD_SVALID 0x00000001 /* Segment entry is valid */
+ /* Reset value is undefined */
+
+
+/* Real page number. Defined by the pte. Writing this register
+ * causes a TLB entry to be created for the data TLB, using
+ * additional information from the MD_EPN, and MD_TWC registers.
+ */
+#define MD_RPN 798
+
+/* This is a temporary storage register that could be used to save
+ * a processor working register during a tablewalk.
+ */
+#define M_TW 799
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully- associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively.
+ */
+
+#define PPC4XX_TLB_SIZE 64
+
+/*
+ * TLB entries are defined by a "high" tag portion and a "low" data
+ * portion. On all architectures, the data portion is 32-bits.
+ *
+ * TLB entries are managed entirely under software control by reading,
+ * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
+ * instructions.
+ */
+
+/*
+ * FSL Book-E support
+ */
+
+#define MAS0_TLBSEL_MSK 0x30000000
+#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
+#define MAS0_ESEL_MSK 0x0FFF0000
+#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
+#define MAS0_NV(x) ((x) & 0x00000FFF)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
+#define MAS1_TS 0x00001000
+#define MAS1_TSIZE(x) (((x) << 7) & 0x00000F80)
+#define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10))
+
+#define MAS2_EPN 0xFFFFF000
+#define MAS2_X0 0x00000040
+#define MAS2_X1 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN 0xFFFFF000
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+
+#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
+#define MAS4_TIDDSEL 0x000F0000
+#define MAS4_TSIZED(x) MAS1_TSIZE(x)
+#define MAS4_X0D 0x00000040
+#define MAS4_X1D 0x00000020
+#define MAS4_WD 0x00000010
+#define MAS4_ID 0x00000008
+#define MAS4_MD 0x00000004
+#define MAS4_GD 0x00000002
+#define MAS4_ED 0x00000001
+
+#define MAS6_SPID0 0x3FFF0000
+#define MAS6_SPID1 0x00007FFE
+#define MAS6_SAS 0x00000001
+#define MAS6_SPID MAS6_SPID0
+
+#define MAS7_RPN 0xFFFFFFFF
+
+#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
+ (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
+#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
+ ((((v) << 31) & MAS1_VALID) |\
+ (((iprot) << 30) & MAS1_IPROT) |\
+ (MAS1_TID(tid)) |\
+ (((ts) << 12) & MAS1_TS) |\
+ (MAS1_TSIZE(tsize)))
+#define FSL_BOOKE_MAS2(epn, wimge) \
+ (((epn) & MAS3_RPN) | (wimge))
+#define FSL_BOOKE_MAS3(rpn, user, perms) \
+ (((rpn) & MAS3_RPN) | (user) | (perms))
+#define FSL_BOOKE_MAS7(rpn) \
+ (((u64)(rpn)) >> 32)
+
+#define BOOKE_PAGESZ_1K 0
+#define BOOKE_PAGESZ_2K 1
+#define BOOKE_PAGESZ_4K 2
+#define BOOKE_PAGESZ_8K 3
+#define BOOKE_PAGESZ_16K 4
+#define BOOKE_PAGESZ_32K 5
+#define BOOKE_PAGESZ_64K 6
+#define BOOKE_PAGESZ_128K 7
+#define BOOKE_PAGESZ_256K 8
+#define BOOKE_PAGESZ_512K 9
+#define BOOKE_PAGESZ_1M 10
+#define BOOKE_PAGESZ_2M 11
+#define BOOKE_PAGESZ_4M 12
+#define BOOKE_PAGESZ_8M 13
+#define BOOKE_PAGESZ_16M 14
+#define BOOKE_PAGESZ_32M 15
+#define BOOKE_PAGESZ_64M 16
+#define BOOKE_PAGESZ_128M 17
+#define BOOKE_PAGESZ_256M 18
+#define BOOKE_PAGESZ_512M 19
+#define BOOKE_PAGESZ_1G 20
+#define BOOKE_PAGESZ_2G 21
+#define BOOKE_PAGESZ_4G 22
+#define BOOKE_PAGESZ_8G 23
+#define BOOKE_PAGESZ_16GB 24
+#define BOOKE_PAGESZ_32GB 25
+#define BOOKE_PAGESZ_64GB 26
+#define BOOKE_PAGESZ_128GB 27
+#define BOOKE_PAGESZ_256GB 28
+#define BOOKE_PAGESZ_512GB 29
+#define BOOKE_PAGESZ_1TB 30
+#define BOOKE_PAGESZ_2TB 31
+
+#define TLBIVAX_ALL 4
+#define TLBIVAX_TLB0 0
+#define TLBIVAX_TLB1 8
+
+#ifdef CONFIG_E500
+#ifndef __ASSEMBLY__
+extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
+ u8 perms, u8 wimge,
+ u8 ts, u8 esel, u8 tsize, u8 iprot);
+extern void disable_tlb(u8 esel);
+extern void invalidate_tlb(u8 tlb);
+extern void init_tlbs(void);
+extern int find_tlb_idx(void *addr, u8 tlbsel);
+extern void init_used_tlb_cams(void);
+extern int find_free_tlbcam(void);
+extern void print_tlbcam(void);
+
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
+extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
+
+enum tlb_map_type {
+ TLB_MAP_RAM,
+ TLB_MAP_IO,
+};
+
+extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+ enum tlb_map_type map_type);
+
+extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
+
+#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
+ { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
+ .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
+ .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \
+ .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
+ .mas7 = FSL_BOOKE_MAS7(_rpn), }
+
+struct fsl_e_tlb_entry {
+ u32 mas0;
+ u32 mas1;
+ u32 mas2;
+ u32 mas3;
+ u32 mas7;
+};
+
+extern struct fsl_e_tlb_entry tlb_table[];
+extern int num_tlb_entries;
+#endif
+#endif
+
+#ifdef CONFIG_E300
+#define LAWAR_EN 0x80000000
+#define LAWAR_SIZE 0x0000003F
+
+#define LAWAR_TRGT_IF_PCI 0x00000000
+#define LAWAR_TRGT_IF_PCI1 0x00000000
+#define LAWAR_TRGT_IF_PCIX 0x00000000
+#define LAWAR_TRGT_IF_PCI2 0x00100000
+#define LAWAR_TRGT_IF_PCIE1 0x00200000
+#define LAWAR_TRGT_IF_PCIE2 0x00100000
+#define LAWAR_TRGT_IF_PCIE3 0x00300000
+#define LAWAR_TRGT_IF_LBC 0x00400000
+#define LAWAR_TRGT_IF_CCSR 0x00800000
+#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
+#define LAWAR_TRGT_IF_RIO 0x00c00000
+#define LAWAR_TRGT_IF_DDR 0x00f00000
+#define LAWAR_TRGT_IF_DDR1 0x00f00000
+#define LAWAR_TRGT_IF_DDR2 0x01600000
+
+#define LAWAR_SIZE_BASE 0xa
+#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
+#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
+#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
+#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
+#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
+#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
+#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
+#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
+#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
+#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
+#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
+#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
+#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
+#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
+#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
+#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
+#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
+#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
+#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
+#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
+#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
+#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
+#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
+#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
+#endif
+
+#endif /* _PPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
new file mode 100644
index 0000000..8dacd27
--- /dev/null
+++ b/arch/powerpc/include/asm/mp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_MP_H_
+#define _ASM_MP_H_
+
+#include <lmb.h>
+
+void setup_mp(void);
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+u32 determine_mp_bootpg(unsigned int *pagesize);
+int is_core_disabled(int nr);
+
+#ifdef CONFIG_E6500
+#define thread_to_core(x) (x >> 1)
+#else
+#define thread_to_core(x) (x)
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/mpc8349_pci.h b/arch/powerpc/include/asm/mpc8349_pci.h
new file mode 100644
index 0000000..7a1adba
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8349_pci.h
@@ -0,0 +1,168 @@
+#ifndef _PPC_KERNEL_MPC8349_PCI_H
+#define _PPC_KERNEL_MPC8349_PCI_H
+
+
+#define M8265_PCIBR0 0x101ac
+#define M8265_PCIBR1 0x101b0
+#define M8265_PCIMSK0 0x101c4
+#define M8265_PCIMSK1 0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE 0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
+#define PCIMSK_64KB 0xFFFF0000
+#define PCIMSK_128KB 0xFFFE0000
+#define PCIMSK_256KB 0xFFFC0000
+#define PCIMSK_512KB 0xFFF80000
+#define PCIMSK_1MB 0xFFF00000
+#define PCIMSK_2MB 0xFFE00000
+#define PCIMSK_4MB 0xFFC00000
+#define PCIMSK_8MB 0xFF800000
+#define PCIMSK_16MB 0xFF000000
+#define PCIMSK_32MB 0xFE000000
+#define PCIMSK_64MB 0xFC000000
+#define PCIMSK_128MB 0xF8000000
+#define PCIMSK_256MB 0xF0000000
+#define PCIMSK_512MB 0xE0000000
+#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus
+ * (local) addresses are translated to PCI addresses when the MPC826x is
+ * a PCI bus master (initiator).
+ */
+
+#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1 0x10818
+#define POTAR_REG2 0x10830
+
+#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
+#define POBAR_REG1 0x10820
+#define POBAR_REG2 0x10838
+
+#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1 0x10828
+#define POCMR_REG2 0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB 0x000FFFFF
+#define POCMR_MASK_8KB 0x000FFFFE
+#define POCMR_MASK_16KB 0x000FFFFC
+#define POCMR_MASK_32KB 0x000FFFF8
+#define POCMR_MASK_64KB 0x000FFFF0
+#define POCMR_MASK_128KB 0x000FFFE0
+#define POCMR_MASK_256KB 0x000FFFC0
+#define POCMR_MASK_512KB 0x000FFF80
+#define POCMR_MASK_1MB 0x000FFF00
+#define POCMR_MASK_2MB 0x000FFE00
+#define POCMR_MASK_4MB 0x000FFC00
+#define POCMR_MASK_8MB 0x000FF800
+#define POCMR_MASK_16MB 0x000FF000
+#define POCMR_MASK_32MB 0x000FE000
+#define POCMR_MASK_64MB 0x000FC000
+#define POCMR_MASK_128MB 0x000F8000
+#define POCMR_MASK_256MB 0x000F0000
+#define POCMR_MASK_512MB 0x000E0000
+#define POCMR_MASK_1GB 0x000C0000
+
+#define POCMR_ENABLE 0x80000000
+#define POCMR_PCI_IO 0x40000000
+#define POCMR_PREFETCH_EN 0x20000000
+#define POCMR_PCI2 0x10000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG 0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN 0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI
+ * addresses are translated to 60x bus (local) addresses when the
+ * MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1 0x108D0
+#define PIBAR_REG1 0x108D8
+#define PICMR_REG1 0x108E0
+#define PITAR_REG0 0x108E8
+#define PIBAR_REG0 0x108F0
+#define PICMR_REG0 0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB 0x000FFFFF
+#define PICMR_MASK_8KB 0x000FFFFE
+#define PICMR_MASK_16KB 0x000FFFFC
+#define PICMR_MASK_32KB 0x000FFFF8
+#define PICMR_MASK_64KB 0x000FFFF0
+#define PICMR_MASK_128KB 0x000FFFE0
+#define PICMR_MASK_256KB 0x000FFFC0
+#define PICMR_MASK_512KB 0x000FFF80
+#define PICMR_MASK_1MB 0x000FFF00
+#define PICMR_MASK_2MB 0x000FFE00
+#define PICMR_MASK_4MB 0x000FFC00
+#define PICMR_MASK_8MB 0x000FF800
+#define PICMR_MASK_16MB 0x000FF000
+#define PICMR_MASK_32MB 0x000FE000
+#define PICMR_MASK_64MB 0x000FC000
+#define PICMR_MASK_128MB 0x000F8000
+#define PICMR_MASK_256MB 0x000F0000
+#define PICMR_MASK_512MB 0x000E0000
+#define PICMR_MASK_1GB 0x000C0000
+
+#define PICMR_ENABLE 0x80000000
+#define PICMR_NO_SNOOP_EN 0x40000000
+#define PICMR_PREFETCH_EN 0x20000000
+
+/* PCI error Registers */
+
+#define PCI_ERROR_STATUS_REG 0x10884
+#define PCI_ERROR_MASK_REG 0x10888
+#define PCI_ERROR_CONTROL_REG 0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
+
+/* PCI error Register bit defines */
+
+#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
+#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
+#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
+#define PCI_ERROR_PCI_NO_RSP 0x00000008
+#define PCI_ERROR_PCI_TAR_ABT 0x00000010
+#define PCI_ERROR_PCI_SERR 0x00000020
+#define PCI_ERROR_PCI_PERR_RD 0x00000040
+#define PCI_ERROR_PCI_PERR_WR 0x00000080
+#define PCI_ERROR_I2O_OFQO 0x00000100
+#define PCI_ERROR_I2O_IPQO 0x00000200
+#define PCI_ERROR_IRA 0x00000400
+#define PCI_ERROR_NMI 0x00000800
+#define PCI_ERROR_I2O_DBMC 0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG 0x10900
+#define PCI_CFG_DATA_REG 0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI 0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
new file mode 100644
index 0000000..1b332f0
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 eXMeritus, A Boeing Company
+ */
+
+#ifndef POWERPC_ASM_MPC85XX_GPIO_H_
+#define POWERPC_ASM_MPC85XX_GPIO_H_
+
+# include <asm/immap_85xx.h>
+
+/*
+ * The following internal functions are an MPC85XX-specific GPIO API which
+ * allows setting and querying multiple GPIOs in a single operation.
+ *
+ * All of these look relatively large, but the arguments are almost always
+ * constants, so they compile down to just a few instructions and a
+ * memory-mapped IO operation or two.
+ */
+static inline void mpc85xx_gpio_set(unsigned int mask,
+ unsigned int dir, unsigned int val)
+{
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+ /* First mask off the unwanted parts of "dir" and "val" */
+ dir &= mask;
+ val &= mask;
+
+ /* Now read in the values we're supposed to preserve */
+ dir |= (in_be32(&gpio->gpdir) & ~mask);
+ val |= (in_be32(&gpio->gpdat) & ~mask);
+
+ /*
+ * Poke the new output values first, then set the direction. This
+ * helps to avoid transient data when switching from input to output
+ * and vice versa.
+ */
+ out_be32(&gpio->gpdat, val);
+ out_be32(&gpio->gpdir, dir);
+}
+
+static inline void mpc85xx_gpio_set_in(unsigned int gpios)
+{
+ mpc85xx_gpio_set(gpios, 0x00000000, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_low(unsigned int gpios)
+{
+ mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_high(unsigned int gpios)
+{
+ mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF);
+}
+
+static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
+{
+ ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+ /* Read the requested values */
+ return in_be32(&gpio->gpdat) & mask;
+}
+
+/*
+ * These implement the generic Linux GPIO API on top of the other functions
+ * in this header.
+ */
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+ /* Compatibility shim */
+ return 0;
+}
+
+static inline int gpio_free(unsigned gpio)
+{
+ /* Compatibility shim */
+ return 0;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+ mpc85xx_gpio_set_in(1U << gpio);
+ return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+ if (value)
+ mpc85xx_gpio_set_high(1U << gpio);
+ else
+ mpc85xx_gpio_set_low(1U << gpio);
+ return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ return !!mpc85xx_gpio_get(1U << gpio);
+}
+
+static inline int gpio_set_value(unsigned gpio, int value)
+{
+ if (value)
+ mpc85xx_gpio_set_high(1U << gpio);
+ else
+ mpc85xx_gpio_set_low(1U << gpio);
+ return 0;
+}
+
+static inline int gpio_is_valid(int gpio)
+{
+ return (gpio >= 0) && (gpio < 32);
+}
+
+#endif /* not POWERPC_ASM_MPC85XX_GPIO_H_ */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
new file mode 100644
index 0000000..b583a32
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Freescale non-CPM SPI Controller
+ *
+ * Copyright 2008 Qstreams Networks, Inc.
+ */
+
+#ifndef _ASM_MPC8XXX_SPI_H_
+#define _ASM_MPC8XXX_SPI_H_
+
+#include <asm/types.h>
+
+#if defined(CONFIG_ARCH_MPC8308) || \
+ defined(CONFIG_ARCH_MPC8313) || \
+ defined(CONFIG_ARCH_MPC8315) || \
+ defined(CONFIG_ARCH_MPC834X) || \
+ defined(CONFIG_ARCH_MPC837X)
+
+typedef struct spi8xxx {
+ u8 res0[0x20]; /* 0x0-0x01f reserved */
+ u32 mode; /* mode register */
+ u32 event; /* event register */
+ u32 mask; /* mask register */
+ u32 com; /* command register */
+ u32 tx; /* transmit register */
+ u32 rx; /* receive register */
+ u8 res1[0xFC8]; /* fill up to 0x1000 */
+} spi8xxx_t;
+
+#endif
+
+#endif /* _ASM_MPC8XXX_SPI_H_ */
diff --git a/arch/powerpc/include/asm/pci_io.h b/arch/powerpc/include/asm/pci_io.h
new file mode 100644
index 0000000..9b738c3
--- /dev/null
+++ b/arch/powerpc/include/asm/pci_io.h
@@ -0,0 +1,43 @@
+/* originally from linux source (asm-ppc/io.h).
+ * Sanity added by Rob Taylor, Flying Pig Systems, 2000
+ */
+#ifndef _PCI_IO_H_
+#define _PCI_IO_H_
+
+#include "io.h"
+
+
+#define pci_read_le16(addr, dest) \
+ __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \
+ "r" (addr), "m" (*addr));
+
+#define pci_write_le16(addr, val) \
+ __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \
+ "r" (val), "r" (addr));
+
+
+#define pci_read_le32(addr, dest) \
+ __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \
+ "r" (addr), "m" (*addr));
+
+#define pci_write_le32(addr, val) \
+__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \
+ "r" (val), "r" (addr));
+
+#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr))
+#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+
+#if !defined(__BIG_ENDIAN)
+#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr))
+#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr))
+#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b))
+#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b))
+#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b))
+#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b))
+#endif
+
+
+#endif /* _PCI_IO_H_ */
diff --git a/arch/powerpc/include/asm/posix_types.h b/arch/powerpc/include/asm/posix_types.h
new file mode 100644
index 0000000..9170728
--- /dev/null
+++ b/arch/powerpc/include/asm/posix_types.h
@@ -0,0 +1,109 @@
+#ifndef _PPC_POSIX_TYPES_H
+#define _PPC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int __kernel_dev_t;
+typedef unsigned int __kernel_ino_t;
+typedef unsigned int __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned int __kernel_old_uid_t;
+typedef unsigned int __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+ int val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+#define __FD_ZERO(set) \
+ ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+ || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+ unsigned int *tmp = (unsigned int *)p->fds_bits;
+ int i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 8:
+ tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
+ tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
+ return;
+ }
+ }
+ i = __FDSET_LONGS;
+ while (i) {
+ i--;
+ *tmp = 0;
+ tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _PPC_POSIX_TYPES_H */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
new file mode 100644
index 0000000..5765f6b
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Ugly header containing required header files. This could be adjusted
+ * so that including asm/arch/hardware includes the correct file.
+ *
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __ASM_PPC_H
+#define __ASM_PPC_H
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_MPC8xx)
+#include <asm/immap_8xx.h>
+#endif
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
+#ifdef CONFIG_MPC85xx
+#include <mpc85xx.h>
+#include <asm/immap_85xx.h>
+#endif
+#ifdef CONFIG_MPC83xx
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
+
+#include <asm/processor.h>
+
+static inline uint get_immr(void)
+{
+ return mfspr(SPRN_IMMR);
+}
+
+static inline uint get_pvr(void)
+{
+ return mfspr(PVR);
+}
+
+static inline uint get_svr(void)
+{
+ return mfspr(SVR);
+}
+
+#if defined(CONFIG_MPC85xx) || \
+ defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_MPC83xx)
+unsigned char in8(unsigned int);
+void out8(unsigned int, unsigned char);
+unsigned short in16(unsigned int);
+unsigned short in16r(unsigned int);
+void out16(unsigned int, unsigned short value);
+void out16r(unsigned int, unsigned short value);
+unsigned long in32(unsigned int);
+unsigned long in32r(unsigned int);
+void out32(unsigned int, unsigned long value);
+void out32r(unsigned int, unsigned long value);
+void ppcDcbf(unsigned long value);
+void ppcDcbi(unsigned long value);
+void ppcSync(void);
+void ppcDcbz(unsigned long value);
+#endif
+#if defined(CONFIG_MPC83xx)
+void ppcDWload(unsigned int *addr, unsigned int *ret);
+void ppcDWstore(unsigned int *addr, unsigned int *value);
+void disable_addr_trans(void);
+void enable_addr_trans(void);
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+#endif
+
+#if defined(CONFIG_MPC85xx)
+typedef MPC85xx_SYS_INFO sys_info_t;
+void get_sys_info(sys_info_t *);
+void ft_fixup_cpu(void *, u64);
+void ft_fixup_num_cores(void *);
+#endif
+#if defined(CONFIG_MPC86xx)
+ulong get_bus_freq(ulong);
+typedef MPC86xx_SYS_INFO sys_info_t;
+void get_sys_info(sys_info_t *);
+static inline ulong get_ddr_freq(ulong dummy)
+{
+ return get_bus_freq(dummy);
+}
+#else
+ulong get_ddr_freq(ulong);
+#endif
+
+static inline unsigned long get_msr(void)
+{
+ unsigned long msr;
+
+ asm volatile ("mfmsr %0" : "=r" (msr) : );
+
+ return msr;
+}
+
+static inline void set_msr(unsigned long msr)
+{
+ asm volatile ("mtmsr %0" : : "r" (msr));
+}
+
+#ifdef CONFIG_CMD_REGINFO
+void print_reginfo(void);
+#endif
+
+void interrupt_init_cpu(unsigned *);
+void timer_interrupt_cpu(struct pt_regs *);
+unsigned long search_exception_table(unsigned long addr);
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef CONFIG_PPC
+/*
+ * Has to be included outside of the #ifndef __ASSEMBLY__ section.
+ * Otherwise might lead to compilation errors in assembler files.
+ */
+#include <asm/cache.h>
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
new file mode 100644
index 0000000..e03ab21
--- /dev/null
+++ b/arch/powerpc/include/asm/processor.h
@@ -0,0 +1,1220 @@
+#ifndef __ASM_PPC_PROCESSOR_H
+#define __ASM_PPC_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+/* Machine State Register (MSR) Fields */
+
+#ifdef CONFIG_PPC64BRIDGE
+#define MSR_SF (1<<63)
+#define MSR_ISF (1<<61)
+#endif /* CONFIG_PPC64BRIDGE */
+#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
+#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
+#define MSR_SPE (1<<25) /* Enable SPE(e500) */
+#define MSR_POW (1<<18) /* Enable Power Management */
+#define MSR_WE (1<<18) /* Wait State Enable */
+#define MSR_TGPR (1<<17) /* TLB Update registers in use */
+#define MSR_CE (1<<17) /* Critical Interrupt Enable */
+#define MSR_ILE (1<<16) /* Interrupt Little Endian */
+#define MSR_EE (1<<15) /* External Interrupt Enable */
+#define MSR_PR (1<<14) /* Problem State / Privilege Level */
+#define MSR_FP (1<<13) /* Floating Point enable */
+#define MSR_ME (1<<12) /* Machine Check Enable */
+#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
+#define MSR_SE (1<<10) /* Single Step */
+#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
+#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
+#define MSR_BE (1<<9) /* Branch Trace */
+#define MSR_DE (1<<9) /* Debug Exception Enable */
+#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
+#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
+#define MSR_IR (1<<5) /* Instruction Relocate */
+#define MSR_IS (1<<5) /* Book E Instruction space */
+#define MSR_DR (1<<4) /* Data Relocate */
+#define MSR_DS (1<<4) /* Book E Data space */
+#define MSR_PE (1<<3) /* Protection Enable */
+#define MSR_PX (1<<2) /* Protection Exclusive Mode */
+#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
+#define MSR_RI (1<<1) /* Recoverable Exception */
+#define MSR_LE (1<<0) /* Little Endian */
+
+#ifdef CONFIG_APUS_FAST_EXCEPT
+#define MSR_ MSR_ME|MSR_IP|MSR_RI
+#else
+#define MSR_ MSR_ME|MSR_RI
+#endif
+#ifndef CONFIG_E500
+#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
+#else
+#define MSR_KERNEL MSR_ME
+#endif
+
+/* Floating Point Status and Control Register (FPSCR) Fields */
+
+#define FPSCR_FX 0x80000000 /* FPU exception summary */
+#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
+#define FPSCR_VX 0x20000000 /* Invalid operation summary */
+#define FPSCR_OX 0x10000000 /* Overflow exception summary */
+#define FPSCR_UX 0x08000000 /* Underflow exception summary */
+#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
+#define FPSCR_XX 0x02000000 /* Inexact exception summary */
+#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
+#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
+#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
+#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
+#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
+#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
+#define FPSCR_FR 0x00040000 /* Fraction rounded */
+#define FPSCR_FI 0x00020000 /* Fraction inexact */
+#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
+#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
+#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
+#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
+#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
+#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
+#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
+#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
+#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
+#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
+#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
+#define FPSCR_RN 0x00000003 /* FPU rounding control */
+
+/* Special Purpose Registers (SPRNs)*/
+
+#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
+#ifdef CONFIG_BOOKE
+#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
+#endif
+#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
+#define SPRN_CTR 0x009 /* Count Register */
+#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
+#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
+#else
+#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
+#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
+#endif /* CONFIG_BOOKE */
+#define SPRN_DAR 0x013 /* Data Address Register */
+#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
+#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
+#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
+#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
+#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
+#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
+#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
+#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
+#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
+#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
+#define DBCR_EDM 0x80000000
+#define DBCR_IDM 0x40000000
+#define DBCR_RST(x) (((x) & 0x3) << 28)
+#define DBCR_RST_NONE 0
+#define DBCR_RST_CORE 1
+#define DBCR_RST_CHIP 2
+#define DBCR_RST_SYSTEM 3
+#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
+#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
+#define DBCR_EDE 0x02000000 /* Exception Debug Event */
+#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
+#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
+#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
+#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define DAC_BYTE 0
+#define DAC_HALF 1
+#define DAC_WORD 2
+#define DAC_QUAD 3
+#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
+#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
+#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
+#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
+#define DBCR_SIA 0x00000008 /* Second IAC Enable */
+#define DBCR_SDA 0x00000004 /* Second DAC Enable */
+#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
+#ifndef CONFIG_BOOKE
+#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
+#else
+#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
+#endif /* CONFIG_BOOKE */
+#ifndef CONFIG_BOOKE
+#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
+#define SPRN_DBSR 0x3F0 /* Debug Status Register */
+#else
+#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define SPRN_DBDR 0x3f3 /* Debug Data Register */
+#endif
+#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
+#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
+#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
+#endif /* CONFIG_BOOKE */
+#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
+#define DCCR_NOCACHE 0 /* Noncacheable */
+#define DCCR_CACHE 1 /* Cacheable */
+#ifndef CONFIG_BOOKE
+#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
+#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
+#endif
+#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
+#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
+#define DCWR_COPY 0 /* Copy-back */
+#define DCWR_WRITE 1 /* Write-through */
+#ifndef CONFIG_BOOKE
+#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
+#else
+#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
+#endif /* CONFIG_BOOKE */
+#define SPRN_DEC 0x016 /* Decrement Register */
+#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
+#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
+#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
+#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
+#endif
+#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
+#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
+#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
+#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
+#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
+#endif
+#define SPRN_EAR 0x11A /* External Address Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
+#else
+#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
+#endif /* CONFIG_BOOKE */
+#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
+#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
+#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
+#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
+#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
+#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
+#define ESR_PTR 0x02000000 /* Program Exception - Trap */
+#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
+#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
+#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
+#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
+#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
+#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT 15
+#define HID0_DCE_SHIFT 14
+#define HID0_DLOCK_SHIFT 12
+
+#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
+#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
+#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
+#define HID0_SBCLK (1<<27)
+#define HID0_EICE (1<<26)
+#define HID0_ECLK (1<<25)
+#define HID0_PAR (1<<24)
+#define HID0_DOZE (1<<23)
+#define HID0_NAP (1<<22)
+#define HID0_SLEEP (1<<21)
+#define HID0_DPM (1<<20)
+#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
+#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
+#define HID0_TBEN (1<<14) /* Time Base Enable */
+#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
+#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
+#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
+#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
+#define HID0_DCI HID0_DCFI
+#define HID0_SPD (1<<9) /* Speculative disable */
+#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
+#define HID0_SGE (1<<7) /* Store Gathering Enable */
+#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
+#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
+#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
+#define HID0_ABE (1<<3) /* Address Broadcast Enable */
+#define HID0_BHTE (1<<2) /* Branch History Table Enable */
+#define HID0_BTCD (1<<1) /* Branch target cache disable */
+#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
+#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
+#define HID1_ASTME (1<<13) /* Address bus streaming mode */
+#define HID1_ABE (1<<12) /* Address broadcast enable */
+#define HID1_MBDD (1<<6) /* optimized sync instruction */
+#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
+#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
+#else
+#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
+#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
+#endif /* CONFIG_BOOKE */
+#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
+#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
+#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
+#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
+#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
+#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
+#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
+#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
+#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
+#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
+#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
+#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
+#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
+#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
+#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
+#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
+#define ICCR_NOCACHE 0 /* Noncacheable */
+#define ICCR_CACHE 1 /* Cacheable */
+#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
+#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
+#endif
+#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
+#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
+#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
+#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
+#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
+#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
+#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
+#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
+#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
+#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
+#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
+#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
+#endif
+#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
+#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
+#define SPRN_LR 0x008 /* Link Register */
+#define SPRN_MBAR 0x137 /* System memory base address */
+#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
+#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define SPRN_MMUCR 0x3b2 /* MMU Control Register */
+#endif
+#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
+#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
+#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
+#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
+#ifndef CONFIG_BOOKE
+#define SPRN_PID 0x3B1 /* Process ID */
+#define SPRN_PIR 0x3FF /* Processor Identification Register */
+#else
+#define SPRN_PID 0x030 /* Book E Process ID */
+#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
+#endif /* CONFIG_BOOKE */
+#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
+#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
+#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
+#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
+#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
+#define SPRN_PVR 0x11F /* Processor Version Register */
+#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_RSTCFG 0x39b /* Reset Configuration */
+#endif
+#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
+#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
+#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
+#define SGR_NORMAL 0
+#define SGR_GUARDED 1
+#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
+#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
+#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
+#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
+#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
+#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
+#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
+#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
+#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
+#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
+#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
+#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
+#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+
+#ifdef CONFIG_BOOKE
+#define SPRN_SVR 0x3FF /* System Version Register */
+#else
+#define SPRN_SVR 0x11E /* System Version Register */
+#endif
+#define SPRN_TBHI 0x3DC /* Time Base High */
+#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
+#define SPRN_TBLO 0x3DD /* Time Base Low */
+#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
+#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
+#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
+#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
+#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_TCR 0x3DA /* Timer Control Register */
+#else
+#define SPRN_TCR 0x154 /* Book E Timer Control Register */
+#endif /* CONFIG_BOOKE */
+#ifdef CONFIG_E500MC
+#define TCR_WP(x) (((64-x)&0x3)<<30)| \
+ (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
+#else
+#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
+#define WP_2_17 0 /* 2^17 clocks */
+#define WP_2_21 1 /* 2^21 clocks */
+#define WP_2_25 2 /* 2^25 clocks */
+#define WP_2_29 3 /* 2^29 clocks */
+#endif /* CONFIG_E500 */
+#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
+#define WRC_NONE 0 /* No reset will occur */
+#define WRC_CORE 1 /* Core reset will occur */
+#define WRC_CHIP 2 /* Chip reset will occur */
+#define WRC_SYSTEM 3 /* System reset will occur */
+#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
+#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
+#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
+#define FP_2_9 0 /* 2^9 clocks */
+#define FP_2_13 1 /* 2^13 clocks */
+#define FP_2_17 2 /* 2^17 clocks */
+#define FP_2_21 3 /* 2^21 clocks */
+#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
+#define TCR_ARE 0x00400000 /* Auto Reload Enable */
+#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
+#define THRM1_TIN (1<<0)
+#define THRM1_TIV (1<<1)
+#define THRM1_THRES (0x7f<<2)
+#define THRM1_TID (1<<29)
+#define THRM1_TIE (1<<30)
+#define THRM1_V (1<<31)
+#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
+#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
+#define THRM3_E (1<<31)
+#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_TSR 0x3D8 /* Timer Status Register */
+#else
+#define SPRN_TSR 0x150 /* Book E Timer Status Register */
+#endif /* CONFIG_BOOKE */
+#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
+#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
+#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
+#define WRS_NONE 0 /* No WDT reset occurred */
+#define WRS_CORE 1 /* WDT forced core reset */
+#define WRS_CHIP 2 /* WDT forced chip reset */
+#define WRS_SYSTEM 3 /* WDT forced system reset */
+#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
+#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
+#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
+#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
+#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
+#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
+#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
+#define SPRN_XER 0x001 /* Fixed Point Exception Register */
+#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
+
+/* Book E definitions */
+#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
+#define SPRN_CSRR0 0x03A /* Critical SRR0 */
+#define SPRN_CSRR1 0x03B /* Critical SRR0 */
+#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
+#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
+#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
+#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
+#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
+#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
+#define SPRN_IVOR38 0x1b0 /* Interrupt Vector Offset Register 38 */
+#define SPRN_IVOR39 0x1b1 /* Interrupt Vector Offset Register 39 */
+#define SPRN_IVOR40 0x1b2 /* Interrupt Vector Offset Register 40 */
+#define SPRN_IVOR41 0x1b3 /* Interrupt Vector Offset Register 41 */
+#define SPRN_GIVOR2 0x1b8 /* Guest Interrupt Vector Offset Register 2 */
+#define SPRN_GIVOR3 0x1b9 /* Guest Interrupt Vector Offset Register 3 */
+#define SPRN_GIVOR4 0x1ba /* Guest Interrupt Vector Offset Register 4 */
+#define SPRN_GIVOR8 0x1bb /* Guest Interrupt Vector Offset Register 8 */
+#define SPRN_GIVOR13 0x1bc /* Guest Interrupt Vector Offset Register 13 */
+#define SPRN_GIVOR14 0x1bd /* Guest Interrupt Vector Offset Register 14 */
+
+/* e500 definitions */
+#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
+#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
+#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
+#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
+#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
+#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
+#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
+#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
+#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
+#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
+#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
+#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
+#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
+#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
+#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
+#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
+#define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */
+#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */
+#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
+#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
+#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
+#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
+#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
+#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
+#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
+#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
+#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
+
+/* e6500 */
+#define L2CSR0_L2REP_SPLRUAGE 0x00000000 /* L2REP Streaming PLRU with Aging */
+#define L2CSR0_L2REP_FIFO 0x00001000 /* L2REP FIFO */
+#define L2CSR0_L2REP_SPLRU 0x00002000 /* L2REP Streaming PLRU */
+#define L2CSR0_L2REP_PLRU 0x00003000 /* L2REP PLRU */
+
+#define L2CSR0_L2REP_MODE L2CSR0_L2REP_SPLRUAGE
+
+#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
+#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
+#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
+#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
+#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
+
+#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
+#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define TLBnCFG_NENTRY_MASK 0x00000fff
+#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
+#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
+#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
+#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
+#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
+#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
+#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
+#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
+#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
+#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
+#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
+#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
+#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
+#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
+#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
+
+#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
+#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
+#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
+#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
+
+#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
+#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
+#define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */
+#define BUCSR_LS_EN 0x00400000 /* Link stack enable */
+#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
+#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
+#define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
+#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
+#define SPRN_PID1 0x279 /* Process ID Register 1 */
+#define SPRN_PID2 0x27a /* Process ID Register 2 */
+#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
+#define SPRN_MCAR 0x23d /* Machine Check Address register */
+#define MCSR_MCS 0x80000000 /* Machine Check Summary */
+#define MCSR_IB 0x40000000 /* Instruction PLB Error */
+#define MCSR_DB 0x20000000 /* Data PLB Error */
+#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
+#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
+#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
+#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
+#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
+#define ESR_ST 0x00800000 /* Store Operation */
+
+#if defined(CONFIG_MPC86xx)
+#define SPRN_MSSCR0 0x3f6
+#define SPRN_MSSSR0 0x3f7
+#endif
+
+#define SPRN_HDBCR0 0x3d0
+#define SPRN_HDBCR1 0x3d1
+#define SPRN_HDBCR2 0x3d2
+#define SPRN_HDBCR3 0x3d3
+#define SPRN_HDBCR4 0x3d4
+#define SPRN_HDBCR5 0x3d5
+#define SPRN_HDBCR6 0x3d6
+#define SPRN_HDBCR7 0x277
+#define SPRN_HDBCR8 0x278
+
+/* Short-hand versions for a number of the above SPRNs */
+
+#define CTR SPRN_CTR /* Counter Register */
+#define DAR SPRN_DAR /* Data Address Register */
+#define DABR SPRN_DABR /* Data Address Breakpoint Register */
+#define DAC1 SPRN_DAC1 /* Data Address Register 1 */
+#define DAC2 SPRN_DAC2 /* Data Address Register 2 */
+#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
+#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
+#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
+#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
+#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
+#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
+#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
+#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
+#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
+#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
+#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
+#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
+#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
+#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
+#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
+#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
+#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
+#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
+#define DBSR SPRN_DBSR /* Debug Status Register */
+#define DCMP SPRN_DCMP /* Data TLB Compare Register */
+#define DEC SPRN_DEC /* Decrement Register */
+#define DMISS SPRN_DMISS /* Data TLB Miss Register */
+#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
+#define EAR SPRN_EAR /* External Address Register */
+#define ESR SPRN_ESR /* Exception Syndrome Register */
+#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
+#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
+#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
+#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
+#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
+#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
+#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
+#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
+#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
+#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
+#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
+#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
+#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
+#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
+#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
+#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
+#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
+#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
+#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
+#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
+#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
+#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
+#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
+#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
+#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
+#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
+#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
+#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
+#define LR SPRN_LR
+#define MBAR SPRN_MBAR /* System memory base address */
+#if defined(CONFIG_MPC86xx)
+#define MSSCR0 SPRN_MSSCR0
+#endif
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#define PIR SPRN_PIR
+#endif
+#define SVR SPRN_SVR /* System-On-Chip Version Register */
+#define PVR SPRN_PVR /* Processor Version */
+#define RPA SPRN_RPA /* Required Physical Address Register */
+#define SDR1 SPRN_SDR1 /* MMU hash base register */
+#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
+#define SPR1 SPRN_SPRG1
+#define SPR2 SPRN_SPRG2
+#define SPR3 SPRN_SPRG3
+#define SPRG0 SPRN_SPRG0
+#define SPRG1 SPRN_SPRG1
+#define SPRG2 SPRN_SPRG2
+#define SPRG3 SPRN_SPRG3
+#define SPRG4 SPRN_SPRG4
+#define SPRG5 SPRN_SPRG5
+#define SPRG6 SPRN_SPRG6
+#define SPRG7 SPRN_SPRG7
+#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
+#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
+#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
+#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
+#define SVR SPRN_SVR /* System Version Register */
+#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
+#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
+#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
+#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
+#define TCR SPRN_TCR /* Timer Control Register */
+#define TSR SPRN_TSR /* Timer Status Register */
+#define ICTC 1019
+#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
+#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
+#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
+#define XER SPRN_XER
+
+#define DECAR SPRN_DECAR
+#define CSRR0 SPRN_CSRR0
+#define CSRR1 SPRN_CSRR1
+#define IVPR SPRN_IVPR
+#define USPRG0 SPRN_USPRG
+#define SPRG4R SPRN_SPRG4R
+#define SPRG5R SPRN_SPRG5R
+#define SPRG6R SPRN_SPRG6R
+#define SPRG7R SPRN_SPRG7R
+#define SPRG4W SPRN_SPRG4W
+#define SPRG5W SPRN_SPRG5W
+#define SPRG6W SPRN_SPRG6W
+#define SPRG7W SPRN_SPRG7W
+#define DEAR SPRN_DEAR
+#define DBCR2 SPRN_DBCR2
+#define IAC3 SPRN_IAC3
+#define IAC4 SPRN_IAC4
+#define DVC1 SPRN_DVC1
+#define DVC2 SPRN_DVC2
+#define IVOR0 SPRN_IVOR0
+#define IVOR1 SPRN_IVOR1
+#define IVOR2 SPRN_IVOR2
+#define IVOR3 SPRN_IVOR3
+#define IVOR4 SPRN_IVOR4
+#define IVOR5 SPRN_IVOR5
+#define IVOR6 SPRN_IVOR6
+#define IVOR7 SPRN_IVOR7
+#define IVOR8 SPRN_IVOR8
+#define IVOR9 SPRN_IVOR9
+#define IVOR10 SPRN_IVOR10
+#define IVOR11 SPRN_IVOR11
+#define IVOR12 SPRN_IVOR12
+#define IVOR13 SPRN_IVOR13
+#define IVOR14 SPRN_IVOR14
+#define IVOR15 SPRN_IVOR15
+#define IVOR32 SPRN_IVOR32
+#define IVOR33 SPRN_IVOR33
+#define IVOR34 SPRN_IVOR34
+#define IVOR35 SPRN_IVOR35
+#define MCSRR0 SPRN_MCSRR0
+#define MCSRR1 SPRN_MCSRR1
+#define L1CSR0 SPRN_L1CSR0
+#define L1CSR1 SPRN_L1CSR1
+#define L1CSR2 SPRN_L1CSR2
+#define L1CFG0 SPRN_L1CFG0
+#define L1CFG1 SPRN_L1CFG1
+#define L2CFG0 SPRN_L2CFG0
+#define L2CSR0 SPRN_L2CSR0
+#define L2CSR1 SPRN_L2CSR1
+#define MCSR SPRN_MCSR
+#define MMUCSR0 SPRN_MMUCSR0
+#define BUCSR SPRN_BUCSR
+#define PID0 SPRN_PID
+#define PID1 SPRN_PID1
+#define PID2 SPRN_PID2
+#define MAS0 SPRN_MAS0
+#define MAS1 SPRN_MAS1
+#define MAS2 SPRN_MAS2
+#define MAS3 SPRN_MAS3
+#define MAS4 SPRN_MAS4
+#define MAS5 SPRN_MAS5
+#define MAS6 SPRN_MAS6
+#define MAS7 SPRN_MAS7
+#define MAS8 SPRN_MAS8
+
+#if defined(CONFIG_MPC85xx)
+#define DAR_DEAR DEAR
+#else
+#define DAR_DEAR DAR
+#endif
+
+/* Device Control Registers */
+
+#define DCRN_BEAR 0x090 /* Bus Error Address Register */
+#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
+#define BESR_DSES 0x80000000 /* Data-Side Error Status */
+#define BESR_DMES 0x40000000 /* DMA Error Status */
+#define BESR_RWS 0x20000000 /* Read/Write Status */
+#define BESR_ETMASK 0x1C000000 /* Error Type */
+#define ET_PROT 0
+#define ET_PARITY 1
+#define ET_NCFG 2
+#define ET_BUSERR 4
+#define ET_BUSTO 6
+#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
+#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
+#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
+#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
+#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
+#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
+#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
+#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
+#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
+#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
+#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
+#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
+#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
+#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
+#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
+#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
+#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
+#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
+#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
+#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
+#define DCRN_DMASR 0x0E0 /* DMA Status Register */
+#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
+#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
+#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
+#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
+#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
+#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
+#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
+#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
+#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
+#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
+#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
+#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
+#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
+#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
+#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
+#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
+#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
+#define IOCR_E0TE 0x80000000
+#define IOCR_E0LP 0x40000000
+#define IOCR_E1TE 0x20000000
+#define IOCR_E1LP 0x10000000
+#define IOCR_E2TE 0x08000000
+#define IOCR_E2LP 0x04000000
+#define IOCR_E3TE 0x02000000
+#define IOCR_E3LP 0x01000000
+#define IOCR_E4TE 0x00800000
+#define IOCR_E4LP 0x00400000
+#define IOCR_EDT 0x00080000
+#define IOCR_SOR 0x00040000
+#define IOCR_EDO 0x00008000
+#define IOCR_2XC 0x00004000
+#define IOCR_ATC 0x00002000
+#define IOCR_SPD 0x00001000
+#define IOCR_BEM 0x00000800
+#define IOCR_PTD 0x00000400
+#define IOCR_ARE 0x00000080
+#define IOCR_DRC 0x00000020
+#define IOCR_RDM(x) (((x) & 0x3) << 3)
+#define IOCR_TCS 0x00000004
+#define IOCR_SCS 0x00000002
+#define IOCR_SPC 0x00000001
+
+/* System-On-Chip Version Register */
+
+/* System-On-Chip Version Register (SVR) field extraction */
+
+#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
+#define SVR_REV(svr) (((svr) >> 0) & 0xFF) /* Revision field */
+
+#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
+#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
+#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
+#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
+#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
+#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
+#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
+
+/* Processor Version Register */
+
+/* Processor Version Register (PVR) field extraction */
+
+#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
+#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
+
+/*
+ * AMCC has further subdivided the standard PowerPC 16-bit version and
+ * revision subfields of the PVR for the PowerPC 403s into the following:
+ */
+
+#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
+#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
+#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
+#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
+#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
+#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
+
+/* e600 core PVR fields */
+
+#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
+#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
+#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
+#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
+
+/* Processor Version Numbers */
+
+#define PVR_403GA 0x00200000
+#define PVR_403GB 0x00200100
+#define PVR_403GC 0x00200200
+#define PVR_403GCX 0x00201400
+#define PVR_405GP 0x40110000
+#define PVR_405GP_RB 0x40110040
+#define PVR_405GP_RC 0x40110082
+#define PVR_405GP_RD 0x401100C4
+#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
+#define PVR_405EP_RA 0x51210950
+#define PVR_405GPR_RB 0x50910951
+#define PVR_405EZ_RA 0x41511460
+#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
+#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
+#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
+#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
+#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
+#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
+#define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */
+#define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */
+#define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */
+#define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */
+#define PVR_440GP_RB 0x40120440
+#define PVR_440GP_RC 0x40120481
+#define PVR_440EP_RA 0x42221850
+#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
+#define PVR_440GX_RA 0x51B21850
+#define PVR_440GX_RB 0x51B21851
+#define PVR_440GX_RC 0x51B21892
+#define PVR_440GX_RF 0x51B21894
+#define PVR_405EP_RB 0x51210950
+#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
+#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
+#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
+#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
+#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
+#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
+#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
+#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
+#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
+#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/
+#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
+#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/
+#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
+#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
+#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
+#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
+#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */
+#define PVR_601 0x00010000
+#define PVR_602 0x00050000
+#define PVR_603 0x00030000
+#define PVR_603e 0x00060000
+#define PVR_603ev 0x00070000
+#define PVR_603r 0x00071000
+#define PVR_604 0x00040000
+#define PVR_604e 0x00090000
+#define PVR_604r 0x000A0000
+#define PVR_620 0x00140000
+#define PVR_740 0x00080000
+#define PVR_750 PVR_740
+#define PVR_740P 0x10080000
+#define PVR_750P PVR_740P
+#define PVR_7400 0x000C0000
+#define PVR_7410 0x800C0000
+#define PVR_7450 0x80000000
+
+#define PVR_85xx 0x80200000
+#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
+#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
+#define PVR_VER_E500_V1 0x8020
+#define PVR_VER_E500_V2 0x8021
+#define PVR_VER_E500MC 0x8023
+#define PVR_VER_E5500 0x8024
+#define PVR_VER_E6500 0x8040
+
+#define PVR_86xx 0x80040000
+
+#define PVR_VIRTEX5 0x7ff21912
+
+/*
+ * For the 8xx processors, all of them report the same PVR family for
+ * the PowerPC core. The various versions of these processors must be
+ * differentiated by the version number in the Communication Processor
+ * Module (CPM).
+ */
+#define PVR_8xx 0x00500000
+
+#define PVR_7400 0x000C0000
+
+/*
+ * MPC 52xx
+ */
+#define PVR_5200 0x80822011
+#define PVR_5200B 0x80822014
+
+/*
+ * 405EX/EXr CHIP_21 Errata
+ */
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
+#endif
+
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
+#endif
+
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
+#endif
+
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
+#endif
+
+/*
+ * System Version Register
+ */
+
+/* System Version Register (SVR) field extraction */
+
+#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
+
+#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
+#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
+
+#ifdef CONFIG_ARCH_MPC8536
+#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
+#else
+#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
+#endif
+#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
+
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
+
+/* whether MPC8xxxE (i.e. has SEC) */
+#if defined(CONFIG_MPC85xx)
+#define IS_E_PROCESSOR(svr) (svr & 0x80000)
+#else
+#if defined(CONFIG_MPC83xx)
+#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
+#endif
+#endif
+
+#define IS_SVR_REV(svr, maj, min) \
+ ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
+
+/*
+ * SVR_SOC_VER() Version Values
+ */
+
+#define SVR_8533 0x803400
+#define SVR_8535 0x803701
+#define SVR_8536 0x803700
+#define SVR_8540 0x803000
+#define SVR_8541 0x807200
+#define SVR_8543 0x803200
+#define SVR_8544 0x803401
+#define SVR_8545 0x803102
+#define SVR_8547 0x803101
+#define SVR_8548 0x803100
+#define SVR_8555 0x807100
+#define SVR_8560 0x807000
+#define SVR_8567 0x807501
+#define SVR_8568 0x807500
+#define SVR_8569 0x808000
+#define SVR_8572 0x80E000
+#define SVR_P1010 0x80F100
+#define SVR_P1011 0x80E500
+#define SVR_P1012 0x80E501
+#define SVR_P1013 0x80E700
+#define SVR_P1014 0x80F101
+#define SVR_P1017 0x80F700
+#define SVR_P1020 0x80E400
+#define SVR_P1021 0x80E401
+#define SVR_P1022 0x80E600
+#define SVR_P1023 0x80F600
+#define SVR_P1024 0x80E402
+#define SVR_P1025 0x80E403
+#define SVR_P2010 0x80E300
+#define SVR_P2020 0x80E200
+#define SVR_P2040 0x821000
+#define SVR_P2041 0x821001
+#define SVR_P3041 0x821103
+#define SVR_P4040 0x820100
+#define SVR_P4080 0x820000
+#define SVR_P5010 0x822100
+#define SVR_P5020 0x822000
+#define SVR_P5021 0X820500
+#define SVR_P5040 0x820400
+#define SVR_T4240 0x824000
+#define SVR_T4120 0x824001
+#define SVR_T4160 0x824100
+#define SVR_T4080 0x824102
+#define SVR_C291 0x850000
+#define SVR_C292 0x850020
+#define SVR_C293 0x850030
+#define SVR_B4860 0X868000
+#define SVR_G4860 0x868001
+#define SVR_B4460 0x868003
+#define SVR_B4440 0x868100
+#define SVR_G4440 0x868101
+#define SVR_B4420 0x868102
+#define SVR_B4220 0x868103
+#define SVR_T1040 0x852000
+#define SVR_T1041 0x852001
+#define SVR_T1042 0x852002
+#define SVR_T1020 0x852100
+#define SVR_T1021 0x852101
+#define SVR_T1022 0x852102
+#define SVR_T1024 0x854000
+#define SVR_T1023 0x854100
+#define SVR_T1014 0x854400
+#define SVR_T1013 0x854500
+#define SVR_T2080 0x853000
+#define SVR_T2081 0x853100
+
+#define SVR_8610 0x80A000
+#define SVR_8641 0x809000
+#define SVR_8641D 0x809001
+
+#define SVR_9130 0x860001
+#define SVR_9131 0x860000
+#define SVR_9132 0x861000
+#define SVR_9232 0x861400
+
+#define SVR_Unknown 0xFFFFFF
+
+#define _GLOBAL(n)\
+ .globl n;\
+n:
+
+/* Macros for setting and retrieving special purpose registers */
+
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#define mfdcr(rn) ({unsigned int rval; \
+ asm volatile("mfdcr %0," stringify(rn) \
+ : "=r" (rval)); rval;})
+#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
+
+#define mfmsr() ({unsigned int rval; \
+ asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
+
+#define mfspr(rn) ({unsigned int rval; \
+ asm volatile("mfspr %0," stringify(rn) \
+ : "=r" (rval)); rval;})
+#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
+
+#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
+
+/* Segment Registers */
+
+#define SR0 0
+#define SR1 1
+#define SR2 2
+#define SR3 3
+#define SR4 4
+#define SR5 5
+#define SR6 6
+#define SR7 7
+#define SR8 8
+#define SR9 9
+#define SR10 10
+#define SR11 11
+#define SR12 12
+#define SR13 13
+#define SR14 14
+#define SR15 15
+
+#ifndef __ASSEMBLY__
+
+struct cpu_type {
+ char name[15];
+ u32 soc_ver;
+ u32 num_cores;
+ u32 mask; /* which cpu(s) actually exist */
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ u32 dsp_num_cores;
+ u32 dsp_mask; /* which DSP cpu(s) actually exist */
+#endif
+};
+
+struct cpu_type *identify_cpu(u32 ver);
+int fixup_cpu(void);
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
+
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#define CPU_TYPE_ENTRY(n, v, nc) \
+ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
+ .mask = (1 << (nc)) - 1 }
+#define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
+ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
+#else
+#if defined(CONFIG_MPC83xx)
+#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
+#endif
+#endif
+
+struct task_struct;
+
+#ifndef CONFIG_CPU_MPC83XX
+int prt_83xx_rsr(void);
+#endif
+
+#endif /* ndef ASSEMBLY*/
+
+#if defined(CONFIG_MPC85xx)
+ #define EPAPR_MAGIC (0x45504150)
+#else
+ #define EPAPR_MAGIC (0x65504150)
+#endif
+
+#endif /* __ASM_PPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
new file mode 100644
index 0000000..2d56de6
--- /dev/null
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -0,0 +1,105 @@
+#ifndef _PPC_PTRACE_H
+#define _PPC_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ *
+ * this should only contain volatile regs
+ * since we can keep non-volatile in the thread_struct
+ * should set this up when only volatiles are saved
+ * by intr code.
+ *
+ * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
+ * that the overall structure is a multiple of 16 bytes in length.
+ *
+ * Note that the offsets of the fields in this struct correspond with
+ * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
+ */
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC64BRIDGE
+#define PPC_REG unsigned long /*long*/
+#else
+#define PPC_REG unsigned long
+#endif
+struct pt_regs {
+ PPC_REG gpr[32];
+ PPC_REG nip;
+ PPC_REG msr;
+ PPC_REG orig_gpr3; /* Used for restarting system calls */
+ PPC_REG ctr;
+ PPC_REG link;
+ PPC_REG xer;
+ PPC_REG ccr;
+ PPC_REG mq; /* 601 only (not used at present) */
+ /* Used on APUS to hold IPL value. */
+ PPC_REG trap; /* Reason for being here */
+ PPC_REG dar; /* Fault registers */
+ PPC_REG dsisr;
+ PPC_REG result; /* Result of a system call */
+};
+#endif
+
+#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE 64
+
+#define instruction_pointer(regs) ((regs)->nip)
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0 0
+#define PT_R1 1
+#define PT_R2 2
+#define PT_R3 3
+#define PT_R4 4
+#define PT_R5 5
+#define PT_R6 6
+#define PT_R7 7
+#define PT_R8 8
+#define PT_R9 9
+#define PT_R10 10
+#define PT_R11 11
+#define PT_R12 12
+#define PT_R13 13
+#define PT_R14 14
+#define PT_R15 15
+#define PT_R16 16
+#define PT_R17 17
+#define PT_R18 18
+#define PT_R19 19
+#define PT_R20 20
+#define PT_R21 21
+#define PT_R22 22
+#define PT_R23 23
+#define PT_R24 24
+#define PT_R25 25
+#define PT_R26 26
+#define PT_R27 27
+#define PT_R28 28
+#define PT_R29 29
+#define PT_R30 30
+#define PT_R31 31
+
+#define PT_NIP 32
+#define PT_MSR 33
+#ifdef __KERNEL__
+#define PT_ORIG_R3 34
+#endif
+#define PT_CTR 35
+#define PT_LNK 36
+#define PT_XER 37
+#define PT_CCR 38
+#define PT_MQ 39
+
+#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#endif
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
new file mode 100644
index 0000000..ccd28ac
--- /dev/null
+++ b/arch/powerpc/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_POWERPC_SECTIONS_H
+#define __ASM_POWERPC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/powerpc/include/asm/sigcontext.h b/arch/powerpc/include/asm/sigcontext.h
new file mode 100644
index 0000000..715c868
--- /dev/null
+++ b/arch/powerpc/include/asm/sigcontext.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_PPC_SIGCONTEXT_H
+#define _ASM_PPC_SIGCONTEXT_H
+
+#include <asm/ptrace.h>
+
+
+struct sigcontext_struct {
+ unsigned long _unused[4];
+ int signal;
+ unsigned long handler;
+ unsigned long oldmask;
+ struct pt_regs *regs;
+};
+
+#endif
diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h
new file mode 100644
index 0000000..b11a28e
--- /dev/null
+++ b/arch/powerpc/include/asm/signal.h
@@ -0,0 +1,154 @@
+#ifndef _ASMPPC_SIGNAL_H
+#define _ASMPPC_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems. */
+struct siginfo;
+
+/* Most things should be clean enough to redefine this at will, if care
+ is taken to make libc match. */
+
+#define _NSIG 64
+#define _NSIG_BPW 32
+#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t; /* at least 32 bits */
+
+typedef struct {
+ unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#define SIGHUP 1
+#define SIGINT 2
+#define SIGQUIT 3
+#define SIGILL 4
+#define SIGTRAP 5
+#define SIGABRT 6
+#define SIGIOT 6
+#define SIGBUS 7
+#define SIGFPE 8
+#define SIGKILL 9
+#define SIGUSR1 10
+#define SIGSEGV 11
+#define SIGUSR2 12
+#define SIGPIPE 13
+#define SIGALRM 14
+#define SIGTERM 15
+#define SIGSTKFLT 16
+#define SIGCHLD 17
+#define SIGCONT 18
+#define SIGSTOP 19
+#define SIGTSTP 20
+#define SIGTTIN 21
+#define SIGTTOU 22
+#define SIGURG 23
+#define SIGXCPU 24
+#define SIGXFSZ 25
+#define SIGVTALRM 26
+#define SIGPROF 27
+#define SIGWINCH 28
+#define SIGIO 29
+#define SIGPOLL SIGIO
+/*
+#define SIGLOST 29
+*/
+#define SIGPWR 30
+#define SIGSYS 31
+#define SIGUNUSED 31
+
+/* These should not be considered constants from userland. */
+#define SIGRTMIN 32
+#define SIGRTMAX (_NSIG-1)
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP 0x00000001
+#define SA_NOCLDWAIT 0x00000002 /* not supported yet */
+#define SA_SIGINFO 0x00000004
+#define SA_ONSTACK 0x08000000
+#define SA_RESTART 0x10000000
+#define SA_NODEFER 0x40000000
+#define SA_RESETHAND 0x80000000
+
+#define SA_NOMASK SA_NODEFER
+#define SA_ONESHOT SA_RESETHAND
+#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */
+
+#define SA_RESTORER 0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK 1
+#define SS_DISABLE 2
+
+#define MINSIGSTKSZ 2048
+#define SIGSTKSZ 8192
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE SA_ONESHOT
+#define SA_SAMPLE_RANDOM SA_RESTART
+#define SA_SHIRQ 0x04000000
+#endif
+
+#define SIG_BLOCK 0 /* for blocking signals */
+#define SIG_UNBLOCK 1 /* for unblocking signals */
+#define SIG_SETMASK 2 /* for setting the signal mask */
+
+/* Type of a signal handler. */
+typedef void (*__sighandler_t)(int);
+
+#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
+
+struct old_sigaction {
+ __sighandler_t sa_handler;
+ old_sigset_t sa_mask;
+ unsigned long sa_flags;
+ void (*sa_restorer)(void);
+};
+
+struct sigaction {
+ __sighandler_t sa_handler;
+ unsigned long sa_flags;
+ void (*sa_restorer)(void);
+ sigset_t sa_mask; /* mask last for extensibility */
+};
+
+struct k_sigaction {
+ struct sigaction sa;
+};
+
+typedef struct sigaltstack {
+ void *ss_sp;
+ int ss_flags;
+ size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/spl.h b/arch/powerpc/include/asm/spl.h
new file mode 100644
index 0000000..60a7d37
--- /dev/null
+++ b/arch/powerpc/include/asm/spl.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _ASM_SPL_H_
+#define _ASM_SPL_H_
+
+#define BOOT_DEVICE_NOR 1
+
+#endif
diff --git a/arch/powerpc/include/asm/string.h b/arch/powerpc/include/asm/string.h
new file mode 100644
index 0000000..036805e
--- /dev/null
+++ b/arch/powerpc/include/asm/string.h
@@ -0,0 +1,29 @@
+#ifndef _PPC_STRING_H_
+#define _PPC_STRING_H_
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRLEN
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRCAT
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_BCOPY
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMCHR
+
+extern int strcasecmp(const char *, const char *);
+extern int strncasecmp(const char *, const char *, __kernel_size_t);
+extern char * strcpy(char *,const char *);
+extern char * strncpy(char *,const char *, __kernel_size_t);
+extern __kernel_size_t strlen(const char *);
+extern int strcmp(const char *,const char *);
+extern char * strcat(char *, const char *);
+extern void * memset(void *,int,__kernel_size_t);
+extern void * memcpy(void *,const void *,__kernel_size_t);
+extern void * memmove(void *,const void *,__kernel_size_t);
+extern int memcmp(const void *,const void *,__kernel_size_t);
+extern void * memchr(const void *,int,__kernel_size_t);
+
+#endif
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
new file mode 100644
index 0000000..cc8d123
--- /dev/null
+++ b/arch/powerpc/include/asm/types.h
@@ -0,0 +1,36 @@
+#ifndef _PPC_TYPES_H
+#define _PPC_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+typedef struct {
+ __u32 u[4];
+} __attribute__((aligned(16))) vector128;
+
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+#else
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+#endif
+
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
new file mode 100644
index 0000000..1841565
--- /dev/null
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __U_BOOT_H__
+#define __U_BOOT_H__
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_PPC
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#include <asm/ppc.h>
+
+#endif /* __U_BOOT_H__ */
diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h
new file mode 100644
index 0000000..5f1b1e3
--- /dev/null
+++ b/arch/powerpc/include/asm/unaligned.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_POWERPC_UNALIGNED_H
+#define _ASM_POWERPC_UNALIGNED_H
+
+#ifdef __KERNEL__
+
+/*
+ * The PowerPC can do unaligned accesses itself in big endian mode.
+ */
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_UNALIGNED_H */